sw:matcha: Update Tock register setting to match matcha
* plic definition
* mailbox address and interrupt IDs
Change-Id: I41907f6b445a72cdd51cf9662675d233ae68a558
diff --git a/config/src/lib.rs b/config/src/lib.rs
index 01ca4be..08308c6 100644
--- a/config/src/lib.rs
+++ b/config/src/lib.rs
@@ -34,9 +34,9 @@
pub const PLIC_BASE: u32 = 0x48000000; // TOP_MATCHA_RV_PLIC_BASE_ADDR
pub const MAILBOX_BASE: u32 = 0x40800000; // TOP_MATCHA_MAILBOX_SEC_BASE_ADDR
-pub const MAILBOX_WTIRQ: u32 = 190; // kTopMatchaPlicIrqIdMailboxSecWtirq
-pub const MAILBOX_RTIRQ: u32 = 191; // kTopMatchaPlicIrqIdMailboxSecRtirq
-pub const MAILBOX_EIRQ: u32 = 192; // kTopMatchaPlicIrqIdMailboxSecEirq
+pub const MAILBOX_WTIRQ: u32 = 187; // kTopMatchaPlicIrqIdMailboxSecWtirq
+pub const MAILBOX_RTIRQ: u32 = 188; // kTopMatchaPlicIrqIdMailboxSecRtirq
+pub const MAILBOX_EIRQ: u32 = 189; // kTopMatchaPlicIrqIdMailboxSecEirq
pub const UART0_BASE_ADDRESS: u32 = 0x40000000; // TOP_MATCHA_UART0_BASE_ADDR
pub const UART0_BAUDRATE: u32 = 115200;
diff --git a/hal/src/plic_constants.rs b/hal/src/plic_constants.rs
index 6e9d598..455dafb 100644
--- a/hal/src/plic_constants.rs
+++ b/hal/src/plic_constants.rs
@@ -1,4 +1,4 @@
-// Generated register constants for RV_PLIC
+// Generated register constants for rv_plic
// Copyright information found in source file:
// Copyright lowRISC contributors.
@@ -8,7 +8,7 @@
// SPDX-License-Identifier: Apache-2.0
// Number of interrupt sources
-pub const RV_PLIC_PARAM_NUM_SRC: u32 = 193;
+pub const RV_PLIC_PARAM_NUM_SRC: u32 = 190;
// Number of Targets (Harts)
pub const RV_PLIC_PARAM_NUM_TARGET: u32 = 2;
@@ -972,25 +972,10 @@
pub const RV_PLIC_PRIO189_PRIO189_MASK: u32 = 0x3;
pub const RV_PLIC_PRIO189_PRIO189_OFFSET: usize = 0;
-// Interrupt Source 190 Priority
-pub const RV_PLIC_PRIO190_REG_OFFSET: usize = 0x2f8;
-pub const RV_PLIC_PRIO190_PRIO190_MASK: u32 = 0x3;
-pub const RV_PLIC_PRIO190_PRIO190_OFFSET: usize = 0;
-
-// Interrupt Source 191 Priority
-pub const RV_PLIC_PRIO191_REG_OFFSET: usize = 0x2fc;
-pub const RV_PLIC_PRIO191_PRIO191_MASK: u32 = 0x3;
-pub const RV_PLIC_PRIO191_PRIO191_OFFSET: usize = 0;
-
-// Interrupt Source 192 Priority
-pub const RV_PLIC_PRIO192_REG_OFFSET: usize = 0x300;
-pub const RV_PLIC_PRIO192_PRIO192_MASK: u32 = 0x3;
-pub const RV_PLIC_PRIO192_PRIO192_OFFSET: usize = 0;
-
// Interrupt Pending (common parameters)
pub const RV_PLIC_IP_P_FIELD_WIDTH: u32 = 1;
pub const RV_PLIC_IP_P_FIELDS_PER_REG: u32 = 32;
-pub const RV_PLIC_IP_MULTIREG_COUNT: u32 = 7;
+pub const RV_PLIC_IP_MULTIREG_COUNT: u32 = 6;
// Interrupt Pending
pub const RV_PLIC_IP_0_REG_OFFSET: usize = 0x1000;
@@ -1199,17 +1184,11 @@
pub const RV_PLIC_IP_5_P_187_BIT: u32 = 27;
pub const RV_PLIC_IP_5_P_188_BIT: u32 = 28;
pub const RV_PLIC_IP_5_P_189_BIT: u32 = 29;
-pub const RV_PLIC_IP_5_P_190_BIT: u32 = 30;
-pub const RV_PLIC_IP_5_P_191_BIT: u32 = 31;
-
-// Interrupt Pending
-pub const RV_PLIC_IP_6_REG_OFFSET: usize = 0x1018;
-pub const RV_PLIC_IP_6_P_192_BIT: u32 = 0;
// Interrupt Enable for Target 0 (common parameters)
pub const RV_PLIC_IE0_E_FIELD_WIDTH: u32 = 1;
pub const RV_PLIC_IE0_E_FIELDS_PER_REG: u32 = 32;
-pub const RV_PLIC_IE0_MULTIREG_COUNT: u32 = 7;
+pub const RV_PLIC_IE0_MULTIREG_COUNT: u32 = 6;
// Interrupt Enable for Target 0
pub const RV_PLIC_IE0_0_REG_OFFSET: usize = 0x2000;
@@ -1418,17 +1397,11 @@
pub const RV_PLIC_IE0_5_E_187_BIT: u32 = 27;
pub const RV_PLIC_IE0_5_E_188_BIT: u32 = 28;
pub const RV_PLIC_IE0_5_E_189_BIT: u32 = 29;
-pub const RV_PLIC_IE0_5_E_190_BIT: u32 = 30;
-pub const RV_PLIC_IE0_5_E_191_BIT: u32 = 31;
-
-// Interrupt Enable for Target 0
-pub const RV_PLIC_IE0_6_REG_OFFSET: usize = 0x2018;
-pub const RV_PLIC_IE0_6_E_192_BIT: u32 = 0;
// Interrupt Enable for Target 1 (common parameters)
pub const RV_PLIC_IE1_E_FIELD_WIDTH: u32 = 1;
pub const RV_PLIC_IE1_E_FIELDS_PER_REG: u32 = 32;
-pub const RV_PLIC_IE1_MULTIREG_COUNT: u32 = 7;
+pub const RV_PLIC_IE1_MULTIREG_COUNT: u32 = 6;
// Interrupt Enable for Target 1
pub const RV_PLIC_IE1_0_REG_OFFSET: usize = 0x2100;
@@ -1637,12 +1610,6 @@
pub const RV_PLIC_IE1_5_E_187_BIT: u32 = 27;
pub const RV_PLIC_IE1_5_E_188_BIT: u32 = 28;
pub const RV_PLIC_IE1_5_E_189_BIT: u32 = 29;
-pub const RV_PLIC_IE1_5_E_190_BIT: u32 = 30;
-pub const RV_PLIC_IE1_5_E_191_BIT: u32 = 31;
-
-// Interrupt Enable for Target 1
-pub const RV_PLIC_IE1_6_REG_OFFSET: usize = 0x2118;
-pub const RV_PLIC_IE1_6_E_192_BIT: u32 = 0;
// Threshold of priority for Target 0
pub const RV_PLIC_THRESHOLD0_REG_OFFSET: usize = 0x200000;
@@ -1676,4 +1643,4 @@
pub const RV_PLIC_ALERT_TEST_REG_OFFSET: usize = 0x4004000;
pub const RV_PLIC_ALERT_TEST_FATAL_FAULT_BIT: u32 = 0;
-// End generated register constants for RV_PLIC
\ No newline at end of file
+// End generated register constants for rv_plic
\ No newline at end of file
