Update PLIC register map.
The secure core's PLIC was updated to the RISC-V standard. This means
moving register locations around.
Update constants with latest info:
./hw/opentitan-upstream/util/regtool.py -R -o /usr/local/google/home/jesionowski/shodan/sw/matcha/hal/src/plic_constants.rs ./hw/opentitan-upstream/hw/top_matcha/ip_autogen/rv_plic/data/rv_plic.hjson
Interrupt source was removed, so remove reference to those registers.
The security core shouldn't refer to the SMC's PLIC, removed reference.
This breaks an unused function, added TODO for Austin.
Change-Id: If0758f222982127016b4faa72d36a56400773991
diff --git a/hal/src/mailbox.rs b/hal/src/mailbox.rs
index f653a2f..53c996a 100644
--- a/hal/src/mailbox.rs
+++ b/hal/src/mailbox.rs
@@ -124,10 +124,11 @@
}
}
+ // TODO(aappleby): Refactor
pub unsafe fn recv_message(&self, message: &mut [u32], send_ack: bool) {
// Enable the SEND irq line and wait for new mail. The ISR will disable the
// irq line once it fires.
- set_bit(plic::PLIC_EN1, self.plic_irq_send);
+ // set_bit(plic::PLIC_EN1, self.plic_irq_send);
self.wait_until_full();
self.regs.irq_send.set(0);
diff --git a/hal/src/plic.rs b/hal/src/plic.rs
index 59bf065..f85c56c 100644
--- a/hal/src/plic.rs
+++ b/hal/src/plic.rs
@@ -4,32 +4,27 @@
use kernel::common::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite};
use kernel::common::StaticRef;
-pub const PLIC_EN0: u32 = 0x41010400;
-pub const PLIC_CCCR0: u32 = 0x4101041C;
-pub const PLIC_MSIP0: u32 = 0x41010420;
+pub const PLIC_ADDR: u32 = 0x4800_0000;
-pub const PLIC_EN1: u32 = 0x41010500;
-pub const PLIC_CCCR1: u32 = 0x4101051C;
-pub const PLIC_MSIP1: u32 = 0x41010520;
+pub const PLIC_EN0: u32 = PLIC_ADDR + RV_PLIC_IE0_0_REG_OFFSET as u32;
+pub const PLIC_CCCR0: u32 = PLIC_ADDR + RV_PLIC_CC0_REG_OFFSET as u32;
register_structs! {
pub PlicRegisters {
- /// Interrupt Pending Register
- (RV_PLIC_IP_0_REG_OFFSET => pending: [ReadOnly<u32>; RV_PLIC_IP_MULTIREG_COUNT as usize]),
- /// Interrupt Source Register
- (RV_PLIC_LE_0_REG_OFFSET => source: [ReadWrite<u32>; RV_PLIC_LE_MULTIREG_COUNT as usize]),
/// Interrupt Priority Registers
(RV_PLIC_PRIO0_REG_OFFSET => priority: [ReadWrite<u32, priority::Register>; RV_PLIC_PARAM_NUM_SRC as usize]),
- (0x30C => _reserved0: [ReadWrite<u32>; 61]),
+ (RV_PLIC_PRIO0_REG_OFFSET + 4*(RV_PLIC_PARAM_NUM_SRC as usize) => _reserved0),
+ /// Interrupt Pending Register
+ (RV_PLIC_IP_0_REG_OFFSET => pending: [ReadOnly<u32>; RV_PLIC_IP_MULTIREG_COUNT as usize]),
+ (RV_PLIC_IP_0_REG_OFFSET + 4*(RV_PLIC_IP_MULTIREG_COUNT as usize) => _reserved1),
/// Interrupt Enable Register
(RV_PLIC_IE0_0_REG_OFFSET => enable: [ReadWrite<u32>; RV_PLIC_IE0_MULTIREG_COUNT as usize]),
+ (RV_PLIC_IE0_0_REG_OFFSET + 4*(RV_PLIC_IE0_MULTIREG_COUNT as usize) => _reserved2),
/// Priority Threshold Register
(RV_PLIC_THRESHOLD0_REG_OFFSET => threshold: ReadWrite<u32, priority::Register>),
/// Claim/Complete Register
(RV_PLIC_CC0_REG_OFFSET => claim: ReadWrite<u32>),
- /// MSIP Register
- (RV_PLIC_MSIP0_REG_OFFSET => msip: ReadWrite<u32>),
- (RV_PLIC_MSIP0_REG_OFFSET + 4 => @END),
+ (RV_PLIC_CC0_REG_OFFSET + 4 => @END),
}
}
@@ -40,7 +35,7 @@
];
const PLIC_BASE: StaticRef<PlicRegisters> =
- unsafe { StaticRef::new(0x4101_0000 as *const PlicRegisters) };
+ unsafe { StaticRef::new(PLIC_ADDR as *const PlicRegisters) };
/// Clear all pending interrupts.
pub unsafe fn clear_all_pending() {
@@ -51,6 +46,7 @@
pub unsafe fn enable_all() {
let plic: &PlicRegisters = &*PLIC_BASE;
+ // TODO(aappleby): Enable all relevant interrupts.
// USB hardware on current OT master branch seems to have
// interrupt bugs: running Alarms causes persistent USB
// CONNECTED interrupts that can't be masked from USBDEV and
@@ -59,13 +55,15 @@
// USB interrurupts.
//
// https://github.com/lowRISC/opentitan/issues/3388
- plic.enable[0].set(0xFFFF_FFFF);
+ plic.enable[0].set(0xFFFF_FFFE);
plic.enable[1].set(0xFFFF_FFFF);
plic.enable[2].set(0xFFFF_0000); // USB are 64-79
// Set the max priority for each interrupt. This is not really used
// at this point.
- for priority in plic.priority.iter() {
+ let mut iter = plic.priority.iter();
+ iter.next(); // Interrupt source 0 can't be enabled.
+ for priority in iter {
priority.write(priority::Priority.val(3));
}
diff --git a/hal/src/plic_constants.rs b/hal/src/plic_constants.rs
index 0c13387..3e0deab 100644
--- a/hal/src/plic_constants.rs
+++ b/hal/src/plic_constants.rs
@@ -11,7 +11,7 @@
// SPDX-License-Identifier: Apache-2.0
// Number of interrupt sources
-pub const RV_PLIC_PARAM_NUM_SRC: u32 = 183;
+pub const RV_PLIC_PARAM_NUM_SRC: u32 = 186;
// Number of Targets (Harts)
pub const RV_PLIC_PARAM_NUM_TARGET: u32 = 2;
@@ -25,13 +25,943 @@
// Register width
pub const RV_PLIC_PARAM_REG_WIDTH: u32 = 32;
+// Interrupt Source 0 Priority
+pub const RV_PLIC_PRIO0_REG_OFFSET: usize = 0x0;
+pub const RV_PLIC_PRIO0_PRIO0_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO0_PRIO0_OFFSET: usize = 0;
+
+// Interrupt Source 1 Priority
+pub const RV_PLIC_PRIO1_REG_OFFSET: usize = 0x4;
+pub const RV_PLIC_PRIO1_PRIO1_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO1_PRIO1_OFFSET: usize = 0;
+
+// Interrupt Source 2 Priority
+pub const RV_PLIC_PRIO2_REG_OFFSET: usize = 0x8;
+pub const RV_PLIC_PRIO2_PRIO2_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO2_PRIO2_OFFSET: usize = 0;
+
+// Interrupt Source 3 Priority
+pub const RV_PLIC_PRIO3_REG_OFFSET: usize = 0xc;
+pub const RV_PLIC_PRIO3_PRIO3_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO3_PRIO3_OFFSET: usize = 0;
+
+// Interrupt Source 4 Priority
+pub const RV_PLIC_PRIO4_REG_OFFSET: usize = 0x10;
+pub const RV_PLIC_PRIO4_PRIO4_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO4_PRIO4_OFFSET: usize = 0;
+
+// Interrupt Source 5 Priority
+pub const RV_PLIC_PRIO5_REG_OFFSET: usize = 0x14;
+pub const RV_PLIC_PRIO5_PRIO5_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO5_PRIO5_OFFSET: usize = 0;
+
+// Interrupt Source 6 Priority
+pub const RV_PLIC_PRIO6_REG_OFFSET: usize = 0x18;
+pub const RV_PLIC_PRIO6_PRIO6_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO6_PRIO6_OFFSET: usize = 0;
+
+// Interrupt Source 7 Priority
+pub const RV_PLIC_PRIO7_REG_OFFSET: usize = 0x1c;
+pub const RV_PLIC_PRIO7_PRIO7_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO7_PRIO7_OFFSET: usize = 0;
+
+// Interrupt Source 8 Priority
+pub const RV_PLIC_PRIO8_REG_OFFSET: usize = 0x20;
+pub const RV_PLIC_PRIO8_PRIO8_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO8_PRIO8_OFFSET: usize = 0;
+
+// Interrupt Source 9 Priority
+pub const RV_PLIC_PRIO9_REG_OFFSET: usize = 0x24;
+pub const RV_PLIC_PRIO9_PRIO9_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO9_PRIO9_OFFSET: usize = 0;
+
+// Interrupt Source 10 Priority
+pub const RV_PLIC_PRIO10_REG_OFFSET: usize = 0x28;
+pub const RV_PLIC_PRIO10_PRIO10_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO10_PRIO10_OFFSET: usize = 0;
+
+// Interrupt Source 11 Priority
+pub const RV_PLIC_PRIO11_REG_OFFSET: usize = 0x2c;
+pub const RV_PLIC_PRIO11_PRIO11_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO11_PRIO11_OFFSET: usize = 0;
+
+// Interrupt Source 12 Priority
+pub const RV_PLIC_PRIO12_REG_OFFSET: usize = 0x30;
+pub const RV_PLIC_PRIO12_PRIO12_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO12_PRIO12_OFFSET: usize = 0;
+
+// Interrupt Source 13 Priority
+pub const RV_PLIC_PRIO13_REG_OFFSET: usize = 0x34;
+pub const RV_PLIC_PRIO13_PRIO13_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO13_PRIO13_OFFSET: usize = 0;
+
+// Interrupt Source 14 Priority
+pub const RV_PLIC_PRIO14_REG_OFFSET: usize = 0x38;
+pub const RV_PLIC_PRIO14_PRIO14_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO14_PRIO14_OFFSET: usize = 0;
+
+// Interrupt Source 15 Priority
+pub const RV_PLIC_PRIO15_REG_OFFSET: usize = 0x3c;
+pub const RV_PLIC_PRIO15_PRIO15_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO15_PRIO15_OFFSET: usize = 0;
+
+// Interrupt Source 16 Priority
+pub const RV_PLIC_PRIO16_REG_OFFSET: usize = 0x40;
+pub const RV_PLIC_PRIO16_PRIO16_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO16_PRIO16_OFFSET: usize = 0;
+
+// Interrupt Source 17 Priority
+pub const RV_PLIC_PRIO17_REG_OFFSET: usize = 0x44;
+pub const RV_PLIC_PRIO17_PRIO17_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO17_PRIO17_OFFSET: usize = 0;
+
+// Interrupt Source 18 Priority
+pub const RV_PLIC_PRIO18_REG_OFFSET: usize = 0x48;
+pub const RV_PLIC_PRIO18_PRIO18_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO18_PRIO18_OFFSET: usize = 0;
+
+// Interrupt Source 19 Priority
+pub const RV_PLIC_PRIO19_REG_OFFSET: usize = 0x4c;
+pub const RV_PLIC_PRIO19_PRIO19_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO19_PRIO19_OFFSET: usize = 0;
+
+// Interrupt Source 20 Priority
+pub const RV_PLIC_PRIO20_REG_OFFSET: usize = 0x50;
+pub const RV_PLIC_PRIO20_PRIO20_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO20_PRIO20_OFFSET: usize = 0;
+
+// Interrupt Source 21 Priority
+pub const RV_PLIC_PRIO21_REG_OFFSET: usize = 0x54;
+pub const RV_PLIC_PRIO21_PRIO21_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO21_PRIO21_OFFSET: usize = 0;
+
+// Interrupt Source 22 Priority
+pub const RV_PLIC_PRIO22_REG_OFFSET: usize = 0x58;
+pub const RV_PLIC_PRIO22_PRIO22_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO22_PRIO22_OFFSET: usize = 0;
+
+// Interrupt Source 23 Priority
+pub const RV_PLIC_PRIO23_REG_OFFSET: usize = 0x5c;
+pub const RV_PLIC_PRIO23_PRIO23_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO23_PRIO23_OFFSET: usize = 0;
+
+// Interrupt Source 24 Priority
+pub const RV_PLIC_PRIO24_REG_OFFSET: usize = 0x60;
+pub const RV_PLIC_PRIO24_PRIO24_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO24_PRIO24_OFFSET: usize = 0;
+
+// Interrupt Source 25 Priority
+pub const RV_PLIC_PRIO25_REG_OFFSET: usize = 0x64;
+pub const RV_PLIC_PRIO25_PRIO25_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO25_PRIO25_OFFSET: usize = 0;
+
+// Interrupt Source 26 Priority
+pub const RV_PLIC_PRIO26_REG_OFFSET: usize = 0x68;
+pub const RV_PLIC_PRIO26_PRIO26_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO26_PRIO26_OFFSET: usize = 0;
+
+// Interrupt Source 27 Priority
+pub const RV_PLIC_PRIO27_REG_OFFSET: usize = 0x6c;
+pub const RV_PLIC_PRIO27_PRIO27_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO27_PRIO27_OFFSET: usize = 0;
+
+// Interrupt Source 28 Priority
+pub const RV_PLIC_PRIO28_REG_OFFSET: usize = 0x70;
+pub const RV_PLIC_PRIO28_PRIO28_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO28_PRIO28_OFFSET: usize = 0;
+
+// Interrupt Source 29 Priority
+pub const RV_PLIC_PRIO29_REG_OFFSET: usize = 0x74;
+pub const RV_PLIC_PRIO29_PRIO29_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO29_PRIO29_OFFSET: usize = 0;
+
+// Interrupt Source 30 Priority
+pub const RV_PLIC_PRIO30_REG_OFFSET: usize = 0x78;
+pub const RV_PLIC_PRIO30_PRIO30_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO30_PRIO30_OFFSET: usize = 0;
+
+// Interrupt Source 31 Priority
+pub const RV_PLIC_PRIO31_REG_OFFSET: usize = 0x7c;
+pub const RV_PLIC_PRIO31_PRIO31_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO31_PRIO31_OFFSET: usize = 0;
+
+// Interrupt Source 32 Priority
+pub const RV_PLIC_PRIO32_REG_OFFSET: usize = 0x80;
+pub const RV_PLIC_PRIO32_PRIO32_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO32_PRIO32_OFFSET: usize = 0;
+
+// Interrupt Source 33 Priority
+pub const RV_PLIC_PRIO33_REG_OFFSET: usize = 0x84;
+pub const RV_PLIC_PRIO33_PRIO33_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO33_PRIO33_OFFSET: usize = 0;
+
+// Interrupt Source 34 Priority
+pub const RV_PLIC_PRIO34_REG_OFFSET: usize = 0x88;
+pub const RV_PLIC_PRIO34_PRIO34_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO34_PRIO34_OFFSET: usize = 0;
+
+// Interrupt Source 35 Priority
+pub const RV_PLIC_PRIO35_REG_OFFSET: usize = 0x8c;
+pub const RV_PLIC_PRIO35_PRIO35_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO35_PRIO35_OFFSET: usize = 0;
+
+// Interrupt Source 36 Priority
+pub const RV_PLIC_PRIO36_REG_OFFSET: usize = 0x90;
+pub const RV_PLIC_PRIO36_PRIO36_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO36_PRIO36_OFFSET: usize = 0;
+
+// Interrupt Source 37 Priority
+pub const RV_PLIC_PRIO37_REG_OFFSET: usize = 0x94;
+pub const RV_PLIC_PRIO37_PRIO37_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO37_PRIO37_OFFSET: usize = 0;
+
+// Interrupt Source 38 Priority
+pub const RV_PLIC_PRIO38_REG_OFFSET: usize = 0x98;
+pub const RV_PLIC_PRIO38_PRIO38_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO38_PRIO38_OFFSET: usize = 0;
+
+// Interrupt Source 39 Priority
+pub const RV_PLIC_PRIO39_REG_OFFSET: usize = 0x9c;
+pub const RV_PLIC_PRIO39_PRIO39_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO39_PRIO39_OFFSET: usize = 0;
+
+// Interrupt Source 40 Priority
+pub const RV_PLIC_PRIO40_REG_OFFSET: usize = 0xa0;
+pub const RV_PLIC_PRIO40_PRIO40_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO40_PRIO40_OFFSET: usize = 0;
+
+// Interrupt Source 41 Priority
+pub const RV_PLIC_PRIO41_REG_OFFSET: usize = 0xa4;
+pub const RV_PLIC_PRIO41_PRIO41_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO41_PRIO41_OFFSET: usize = 0;
+
+// Interrupt Source 42 Priority
+pub const RV_PLIC_PRIO42_REG_OFFSET: usize = 0xa8;
+pub const RV_PLIC_PRIO42_PRIO42_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO42_PRIO42_OFFSET: usize = 0;
+
+// Interrupt Source 43 Priority
+pub const RV_PLIC_PRIO43_REG_OFFSET: usize = 0xac;
+pub const RV_PLIC_PRIO43_PRIO43_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO43_PRIO43_OFFSET: usize = 0;
+
+// Interrupt Source 44 Priority
+pub const RV_PLIC_PRIO44_REG_OFFSET: usize = 0xb0;
+pub const RV_PLIC_PRIO44_PRIO44_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO44_PRIO44_OFFSET: usize = 0;
+
+// Interrupt Source 45 Priority
+pub const RV_PLIC_PRIO45_REG_OFFSET: usize = 0xb4;
+pub const RV_PLIC_PRIO45_PRIO45_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO45_PRIO45_OFFSET: usize = 0;
+
+// Interrupt Source 46 Priority
+pub const RV_PLIC_PRIO46_REG_OFFSET: usize = 0xb8;
+pub const RV_PLIC_PRIO46_PRIO46_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO46_PRIO46_OFFSET: usize = 0;
+
+// Interrupt Source 47 Priority
+pub const RV_PLIC_PRIO47_REG_OFFSET: usize = 0xbc;
+pub const RV_PLIC_PRIO47_PRIO47_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO47_PRIO47_OFFSET: usize = 0;
+
+// Interrupt Source 48 Priority
+pub const RV_PLIC_PRIO48_REG_OFFSET: usize = 0xc0;
+pub const RV_PLIC_PRIO48_PRIO48_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO48_PRIO48_OFFSET: usize = 0;
+
+// Interrupt Source 49 Priority
+pub const RV_PLIC_PRIO49_REG_OFFSET: usize = 0xc4;
+pub const RV_PLIC_PRIO49_PRIO49_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO49_PRIO49_OFFSET: usize = 0;
+
+// Interrupt Source 50 Priority
+pub const RV_PLIC_PRIO50_REG_OFFSET: usize = 0xc8;
+pub const RV_PLIC_PRIO50_PRIO50_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO50_PRIO50_OFFSET: usize = 0;
+
+// Interrupt Source 51 Priority
+pub const RV_PLIC_PRIO51_REG_OFFSET: usize = 0xcc;
+pub const RV_PLIC_PRIO51_PRIO51_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO51_PRIO51_OFFSET: usize = 0;
+
+// Interrupt Source 52 Priority
+pub const RV_PLIC_PRIO52_REG_OFFSET: usize = 0xd0;
+pub const RV_PLIC_PRIO52_PRIO52_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO52_PRIO52_OFFSET: usize = 0;
+
+// Interrupt Source 53 Priority
+pub const RV_PLIC_PRIO53_REG_OFFSET: usize = 0xd4;
+pub const RV_PLIC_PRIO53_PRIO53_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO53_PRIO53_OFFSET: usize = 0;
+
+// Interrupt Source 54 Priority
+pub const RV_PLIC_PRIO54_REG_OFFSET: usize = 0xd8;
+pub const RV_PLIC_PRIO54_PRIO54_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO54_PRIO54_OFFSET: usize = 0;
+
+// Interrupt Source 55 Priority
+pub const RV_PLIC_PRIO55_REG_OFFSET: usize = 0xdc;
+pub const RV_PLIC_PRIO55_PRIO55_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO55_PRIO55_OFFSET: usize = 0;
+
+// Interrupt Source 56 Priority
+pub const RV_PLIC_PRIO56_REG_OFFSET: usize = 0xe0;
+pub const RV_PLIC_PRIO56_PRIO56_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO56_PRIO56_OFFSET: usize = 0;
+
+// Interrupt Source 57 Priority
+pub const RV_PLIC_PRIO57_REG_OFFSET: usize = 0xe4;
+pub const RV_PLIC_PRIO57_PRIO57_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO57_PRIO57_OFFSET: usize = 0;
+
+// Interrupt Source 58 Priority
+pub const RV_PLIC_PRIO58_REG_OFFSET: usize = 0xe8;
+pub const RV_PLIC_PRIO58_PRIO58_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO58_PRIO58_OFFSET: usize = 0;
+
+// Interrupt Source 59 Priority
+pub const RV_PLIC_PRIO59_REG_OFFSET: usize = 0xec;
+pub const RV_PLIC_PRIO59_PRIO59_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO59_PRIO59_OFFSET: usize = 0;
+
+// Interrupt Source 60 Priority
+pub const RV_PLIC_PRIO60_REG_OFFSET: usize = 0xf0;
+pub const RV_PLIC_PRIO60_PRIO60_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO60_PRIO60_OFFSET: usize = 0;
+
+// Interrupt Source 61 Priority
+pub const RV_PLIC_PRIO61_REG_OFFSET: usize = 0xf4;
+pub const RV_PLIC_PRIO61_PRIO61_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO61_PRIO61_OFFSET: usize = 0;
+
+// Interrupt Source 62 Priority
+pub const RV_PLIC_PRIO62_REG_OFFSET: usize = 0xf8;
+pub const RV_PLIC_PRIO62_PRIO62_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO62_PRIO62_OFFSET: usize = 0;
+
+// Interrupt Source 63 Priority
+pub const RV_PLIC_PRIO63_REG_OFFSET: usize = 0xfc;
+pub const RV_PLIC_PRIO63_PRIO63_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO63_PRIO63_OFFSET: usize = 0;
+
+// Interrupt Source 64 Priority
+pub const RV_PLIC_PRIO64_REG_OFFSET: usize = 0x100;
+pub const RV_PLIC_PRIO64_PRIO64_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO64_PRIO64_OFFSET: usize = 0;
+
+// Interrupt Source 65 Priority
+pub const RV_PLIC_PRIO65_REG_OFFSET: usize = 0x104;
+pub const RV_PLIC_PRIO65_PRIO65_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO65_PRIO65_OFFSET: usize = 0;
+
+// Interrupt Source 66 Priority
+pub const RV_PLIC_PRIO66_REG_OFFSET: usize = 0x108;
+pub const RV_PLIC_PRIO66_PRIO66_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO66_PRIO66_OFFSET: usize = 0;
+
+// Interrupt Source 67 Priority
+pub const RV_PLIC_PRIO67_REG_OFFSET: usize = 0x10c;
+pub const RV_PLIC_PRIO67_PRIO67_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO67_PRIO67_OFFSET: usize = 0;
+
+// Interrupt Source 68 Priority
+pub const RV_PLIC_PRIO68_REG_OFFSET: usize = 0x110;
+pub const RV_PLIC_PRIO68_PRIO68_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO68_PRIO68_OFFSET: usize = 0;
+
+// Interrupt Source 69 Priority
+pub const RV_PLIC_PRIO69_REG_OFFSET: usize = 0x114;
+pub const RV_PLIC_PRIO69_PRIO69_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO69_PRIO69_OFFSET: usize = 0;
+
+// Interrupt Source 70 Priority
+pub const RV_PLIC_PRIO70_REG_OFFSET: usize = 0x118;
+pub const RV_PLIC_PRIO70_PRIO70_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO70_PRIO70_OFFSET: usize = 0;
+
+// Interrupt Source 71 Priority
+pub const RV_PLIC_PRIO71_REG_OFFSET: usize = 0x11c;
+pub const RV_PLIC_PRIO71_PRIO71_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO71_PRIO71_OFFSET: usize = 0;
+
+// Interrupt Source 72 Priority
+pub const RV_PLIC_PRIO72_REG_OFFSET: usize = 0x120;
+pub const RV_PLIC_PRIO72_PRIO72_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO72_PRIO72_OFFSET: usize = 0;
+
+// Interrupt Source 73 Priority
+pub const RV_PLIC_PRIO73_REG_OFFSET: usize = 0x124;
+pub const RV_PLIC_PRIO73_PRIO73_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO73_PRIO73_OFFSET: usize = 0;
+
+// Interrupt Source 74 Priority
+pub const RV_PLIC_PRIO74_REG_OFFSET: usize = 0x128;
+pub const RV_PLIC_PRIO74_PRIO74_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO74_PRIO74_OFFSET: usize = 0;
+
+// Interrupt Source 75 Priority
+pub const RV_PLIC_PRIO75_REG_OFFSET: usize = 0x12c;
+pub const RV_PLIC_PRIO75_PRIO75_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO75_PRIO75_OFFSET: usize = 0;
+
+// Interrupt Source 76 Priority
+pub const RV_PLIC_PRIO76_REG_OFFSET: usize = 0x130;
+pub const RV_PLIC_PRIO76_PRIO76_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO76_PRIO76_OFFSET: usize = 0;
+
+// Interrupt Source 77 Priority
+pub const RV_PLIC_PRIO77_REG_OFFSET: usize = 0x134;
+pub const RV_PLIC_PRIO77_PRIO77_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO77_PRIO77_OFFSET: usize = 0;
+
+// Interrupt Source 78 Priority
+pub const RV_PLIC_PRIO78_REG_OFFSET: usize = 0x138;
+pub const RV_PLIC_PRIO78_PRIO78_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO78_PRIO78_OFFSET: usize = 0;
+
+// Interrupt Source 79 Priority
+pub const RV_PLIC_PRIO79_REG_OFFSET: usize = 0x13c;
+pub const RV_PLIC_PRIO79_PRIO79_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO79_PRIO79_OFFSET: usize = 0;
+
+// Interrupt Source 80 Priority
+pub const RV_PLIC_PRIO80_REG_OFFSET: usize = 0x140;
+pub const RV_PLIC_PRIO80_PRIO80_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO80_PRIO80_OFFSET: usize = 0;
+
+// Interrupt Source 81 Priority
+pub const RV_PLIC_PRIO81_REG_OFFSET: usize = 0x144;
+pub const RV_PLIC_PRIO81_PRIO81_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO81_PRIO81_OFFSET: usize = 0;
+
+// Interrupt Source 82 Priority
+pub const RV_PLIC_PRIO82_REG_OFFSET: usize = 0x148;
+pub const RV_PLIC_PRIO82_PRIO82_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO82_PRIO82_OFFSET: usize = 0;
+
+// Interrupt Source 83 Priority
+pub const RV_PLIC_PRIO83_REG_OFFSET: usize = 0x14c;
+pub const RV_PLIC_PRIO83_PRIO83_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO83_PRIO83_OFFSET: usize = 0;
+
+// Interrupt Source 84 Priority
+pub const RV_PLIC_PRIO84_REG_OFFSET: usize = 0x150;
+pub const RV_PLIC_PRIO84_PRIO84_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO84_PRIO84_OFFSET: usize = 0;
+
+// Interrupt Source 85 Priority
+pub const RV_PLIC_PRIO85_REG_OFFSET: usize = 0x154;
+pub const RV_PLIC_PRIO85_PRIO85_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO85_PRIO85_OFFSET: usize = 0;
+
+// Interrupt Source 86 Priority
+pub const RV_PLIC_PRIO86_REG_OFFSET: usize = 0x158;
+pub const RV_PLIC_PRIO86_PRIO86_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO86_PRIO86_OFFSET: usize = 0;
+
+// Interrupt Source 87 Priority
+pub const RV_PLIC_PRIO87_REG_OFFSET: usize = 0x15c;
+pub const RV_PLIC_PRIO87_PRIO87_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO87_PRIO87_OFFSET: usize = 0;
+
+// Interrupt Source 88 Priority
+pub const RV_PLIC_PRIO88_REG_OFFSET: usize = 0x160;
+pub const RV_PLIC_PRIO88_PRIO88_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO88_PRIO88_OFFSET: usize = 0;
+
+// Interrupt Source 89 Priority
+pub const RV_PLIC_PRIO89_REG_OFFSET: usize = 0x164;
+pub const RV_PLIC_PRIO89_PRIO89_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO89_PRIO89_OFFSET: usize = 0;
+
+// Interrupt Source 90 Priority
+pub const RV_PLIC_PRIO90_REG_OFFSET: usize = 0x168;
+pub const RV_PLIC_PRIO90_PRIO90_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO90_PRIO90_OFFSET: usize = 0;
+
+// Interrupt Source 91 Priority
+pub const RV_PLIC_PRIO91_REG_OFFSET: usize = 0x16c;
+pub const RV_PLIC_PRIO91_PRIO91_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO91_PRIO91_OFFSET: usize = 0;
+
+// Interrupt Source 92 Priority
+pub const RV_PLIC_PRIO92_REG_OFFSET: usize = 0x170;
+pub const RV_PLIC_PRIO92_PRIO92_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO92_PRIO92_OFFSET: usize = 0;
+
+// Interrupt Source 93 Priority
+pub const RV_PLIC_PRIO93_REG_OFFSET: usize = 0x174;
+pub const RV_PLIC_PRIO93_PRIO93_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO93_PRIO93_OFFSET: usize = 0;
+
+// Interrupt Source 94 Priority
+pub const RV_PLIC_PRIO94_REG_OFFSET: usize = 0x178;
+pub const RV_PLIC_PRIO94_PRIO94_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO94_PRIO94_OFFSET: usize = 0;
+
+// Interrupt Source 95 Priority
+pub const RV_PLIC_PRIO95_REG_OFFSET: usize = 0x17c;
+pub const RV_PLIC_PRIO95_PRIO95_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO95_PRIO95_OFFSET: usize = 0;
+
+// Interrupt Source 96 Priority
+pub const RV_PLIC_PRIO96_REG_OFFSET: usize = 0x180;
+pub const RV_PLIC_PRIO96_PRIO96_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO96_PRIO96_OFFSET: usize = 0;
+
+// Interrupt Source 97 Priority
+pub const RV_PLIC_PRIO97_REG_OFFSET: usize = 0x184;
+pub const RV_PLIC_PRIO97_PRIO97_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO97_PRIO97_OFFSET: usize = 0;
+
+// Interrupt Source 98 Priority
+pub const RV_PLIC_PRIO98_REG_OFFSET: usize = 0x188;
+pub const RV_PLIC_PRIO98_PRIO98_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO98_PRIO98_OFFSET: usize = 0;
+
+// Interrupt Source 99 Priority
+pub const RV_PLIC_PRIO99_REG_OFFSET: usize = 0x18c;
+pub const RV_PLIC_PRIO99_PRIO99_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO99_PRIO99_OFFSET: usize = 0;
+
+// Interrupt Source 100 Priority
+pub const RV_PLIC_PRIO100_REG_OFFSET: usize = 0x190;
+pub const RV_PLIC_PRIO100_PRIO100_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO100_PRIO100_OFFSET: usize = 0;
+
+// Interrupt Source 101 Priority
+pub const RV_PLIC_PRIO101_REG_OFFSET: usize = 0x194;
+pub const RV_PLIC_PRIO101_PRIO101_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO101_PRIO101_OFFSET: usize = 0;
+
+// Interrupt Source 102 Priority
+pub const RV_PLIC_PRIO102_REG_OFFSET: usize = 0x198;
+pub const RV_PLIC_PRIO102_PRIO102_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO102_PRIO102_OFFSET: usize = 0;
+
+// Interrupt Source 103 Priority
+pub const RV_PLIC_PRIO103_REG_OFFSET: usize = 0x19c;
+pub const RV_PLIC_PRIO103_PRIO103_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO103_PRIO103_OFFSET: usize = 0;
+
+// Interrupt Source 104 Priority
+pub const RV_PLIC_PRIO104_REG_OFFSET: usize = 0x1a0;
+pub const RV_PLIC_PRIO104_PRIO104_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO104_PRIO104_OFFSET: usize = 0;
+
+// Interrupt Source 105 Priority
+pub const RV_PLIC_PRIO105_REG_OFFSET: usize = 0x1a4;
+pub const RV_PLIC_PRIO105_PRIO105_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO105_PRIO105_OFFSET: usize = 0;
+
+// Interrupt Source 106 Priority
+pub const RV_PLIC_PRIO106_REG_OFFSET: usize = 0x1a8;
+pub const RV_PLIC_PRIO106_PRIO106_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO106_PRIO106_OFFSET: usize = 0;
+
+// Interrupt Source 107 Priority
+pub const RV_PLIC_PRIO107_REG_OFFSET: usize = 0x1ac;
+pub const RV_PLIC_PRIO107_PRIO107_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO107_PRIO107_OFFSET: usize = 0;
+
+// Interrupt Source 108 Priority
+pub const RV_PLIC_PRIO108_REG_OFFSET: usize = 0x1b0;
+pub const RV_PLIC_PRIO108_PRIO108_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO108_PRIO108_OFFSET: usize = 0;
+
+// Interrupt Source 109 Priority
+pub const RV_PLIC_PRIO109_REG_OFFSET: usize = 0x1b4;
+pub const RV_PLIC_PRIO109_PRIO109_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO109_PRIO109_OFFSET: usize = 0;
+
+// Interrupt Source 110 Priority
+pub const RV_PLIC_PRIO110_REG_OFFSET: usize = 0x1b8;
+pub const RV_PLIC_PRIO110_PRIO110_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO110_PRIO110_OFFSET: usize = 0;
+
+// Interrupt Source 111 Priority
+pub const RV_PLIC_PRIO111_REG_OFFSET: usize = 0x1bc;
+pub const RV_PLIC_PRIO111_PRIO111_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO111_PRIO111_OFFSET: usize = 0;
+
+// Interrupt Source 112 Priority
+pub const RV_PLIC_PRIO112_REG_OFFSET: usize = 0x1c0;
+pub const RV_PLIC_PRIO112_PRIO112_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO112_PRIO112_OFFSET: usize = 0;
+
+// Interrupt Source 113 Priority
+pub const RV_PLIC_PRIO113_REG_OFFSET: usize = 0x1c4;
+pub const RV_PLIC_PRIO113_PRIO113_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO113_PRIO113_OFFSET: usize = 0;
+
+// Interrupt Source 114 Priority
+pub const RV_PLIC_PRIO114_REG_OFFSET: usize = 0x1c8;
+pub const RV_PLIC_PRIO114_PRIO114_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO114_PRIO114_OFFSET: usize = 0;
+
+// Interrupt Source 115 Priority
+pub const RV_PLIC_PRIO115_REG_OFFSET: usize = 0x1cc;
+pub const RV_PLIC_PRIO115_PRIO115_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO115_PRIO115_OFFSET: usize = 0;
+
+// Interrupt Source 116 Priority
+pub const RV_PLIC_PRIO116_REG_OFFSET: usize = 0x1d0;
+pub const RV_PLIC_PRIO116_PRIO116_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO116_PRIO116_OFFSET: usize = 0;
+
+// Interrupt Source 117 Priority
+pub const RV_PLIC_PRIO117_REG_OFFSET: usize = 0x1d4;
+pub const RV_PLIC_PRIO117_PRIO117_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO117_PRIO117_OFFSET: usize = 0;
+
+// Interrupt Source 118 Priority
+pub const RV_PLIC_PRIO118_REG_OFFSET: usize = 0x1d8;
+pub const RV_PLIC_PRIO118_PRIO118_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO118_PRIO118_OFFSET: usize = 0;
+
+// Interrupt Source 119 Priority
+pub const RV_PLIC_PRIO119_REG_OFFSET: usize = 0x1dc;
+pub const RV_PLIC_PRIO119_PRIO119_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO119_PRIO119_OFFSET: usize = 0;
+
+// Interrupt Source 120 Priority
+pub const RV_PLIC_PRIO120_REG_OFFSET: usize = 0x1e0;
+pub const RV_PLIC_PRIO120_PRIO120_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO120_PRIO120_OFFSET: usize = 0;
+
+// Interrupt Source 121 Priority
+pub const RV_PLIC_PRIO121_REG_OFFSET: usize = 0x1e4;
+pub const RV_PLIC_PRIO121_PRIO121_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO121_PRIO121_OFFSET: usize = 0;
+
+// Interrupt Source 122 Priority
+pub const RV_PLIC_PRIO122_REG_OFFSET: usize = 0x1e8;
+pub const RV_PLIC_PRIO122_PRIO122_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO122_PRIO122_OFFSET: usize = 0;
+
+// Interrupt Source 123 Priority
+pub const RV_PLIC_PRIO123_REG_OFFSET: usize = 0x1ec;
+pub const RV_PLIC_PRIO123_PRIO123_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO123_PRIO123_OFFSET: usize = 0;
+
+// Interrupt Source 124 Priority
+pub const RV_PLIC_PRIO124_REG_OFFSET: usize = 0x1f0;
+pub const RV_PLIC_PRIO124_PRIO124_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO124_PRIO124_OFFSET: usize = 0;
+
+// Interrupt Source 125 Priority
+pub const RV_PLIC_PRIO125_REG_OFFSET: usize = 0x1f4;
+pub const RV_PLIC_PRIO125_PRIO125_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO125_PRIO125_OFFSET: usize = 0;
+
+// Interrupt Source 126 Priority
+pub const RV_PLIC_PRIO126_REG_OFFSET: usize = 0x1f8;
+pub const RV_PLIC_PRIO126_PRIO126_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO126_PRIO126_OFFSET: usize = 0;
+
+// Interrupt Source 127 Priority
+pub const RV_PLIC_PRIO127_REG_OFFSET: usize = 0x1fc;
+pub const RV_PLIC_PRIO127_PRIO127_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO127_PRIO127_OFFSET: usize = 0;
+
+// Interrupt Source 128 Priority
+pub const RV_PLIC_PRIO128_REG_OFFSET: usize = 0x200;
+pub const RV_PLIC_PRIO128_PRIO128_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO128_PRIO128_OFFSET: usize = 0;
+
+// Interrupt Source 129 Priority
+pub const RV_PLIC_PRIO129_REG_OFFSET: usize = 0x204;
+pub const RV_PLIC_PRIO129_PRIO129_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO129_PRIO129_OFFSET: usize = 0;
+
+// Interrupt Source 130 Priority
+pub const RV_PLIC_PRIO130_REG_OFFSET: usize = 0x208;
+pub const RV_PLIC_PRIO130_PRIO130_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO130_PRIO130_OFFSET: usize = 0;
+
+// Interrupt Source 131 Priority
+pub const RV_PLIC_PRIO131_REG_OFFSET: usize = 0x20c;
+pub const RV_PLIC_PRIO131_PRIO131_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO131_PRIO131_OFFSET: usize = 0;
+
+// Interrupt Source 132 Priority
+pub const RV_PLIC_PRIO132_REG_OFFSET: usize = 0x210;
+pub const RV_PLIC_PRIO132_PRIO132_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO132_PRIO132_OFFSET: usize = 0;
+
+// Interrupt Source 133 Priority
+pub const RV_PLIC_PRIO133_REG_OFFSET: usize = 0x214;
+pub const RV_PLIC_PRIO133_PRIO133_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO133_PRIO133_OFFSET: usize = 0;
+
+// Interrupt Source 134 Priority
+pub const RV_PLIC_PRIO134_REG_OFFSET: usize = 0x218;
+pub const RV_PLIC_PRIO134_PRIO134_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO134_PRIO134_OFFSET: usize = 0;
+
+// Interrupt Source 135 Priority
+pub const RV_PLIC_PRIO135_REG_OFFSET: usize = 0x21c;
+pub const RV_PLIC_PRIO135_PRIO135_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO135_PRIO135_OFFSET: usize = 0;
+
+// Interrupt Source 136 Priority
+pub const RV_PLIC_PRIO136_REG_OFFSET: usize = 0x220;
+pub const RV_PLIC_PRIO136_PRIO136_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO136_PRIO136_OFFSET: usize = 0;
+
+// Interrupt Source 137 Priority
+pub const RV_PLIC_PRIO137_REG_OFFSET: usize = 0x224;
+pub const RV_PLIC_PRIO137_PRIO137_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO137_PRIO137_OFFSET: usize = 0;
+
+// Interrupt Source 138 Priority
+pub const RV_PLIC_PRIO138_REG_OFFSET: usize = 0x228;
+pub const RV_PLIC_PRIO138_PRIO138_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO138_PRIO138_OFFSET: usize = 0;
+
+// Interrupt Source 139 Priority
+pub const RV_PLIC_PRIO139_REG_OFFSET: usize = 0x22c;
+pub const RV_PLIC_PRIO139_PRIO139_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO139_PRIO139_OFFSET: usize = 0;
+
+// Interrupt Source 140 Priority
+pub const RV_PLIC_PRIO140_REG_OFFSET: usize = 0x230;
+pub const RV_PLIC_PRIO140_PRIO140_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO140_PRIO140_OFFSET: usize = 0;
+
+// Interrupt Source 141 Priority
+pub const RV_PLIC_PRIO141_REG_OFFSET: usize = 0x234;
+pub const RV_PLIC_PRIO141_PRIO141_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO141_PRIO141_OFFSET: usize = 0;
+
+// Interrupt Source 142 Priority
+pub const RV_PLIC_PRIO142_REG_OFFSET: usize = 0x238;
+pub const RV_PLIC_PRIO142_PRIO142_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO142_PRIO142_OFFSET: usize = 0;
+
+// Interrupt Source 143 Priority
+pub const RV_PLIC_PRIO143_REG_OFFSET: usize = 0x23c;
+pub const RV_PLIC_PRIO143_PRIO143_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO143_PRIO143_OFFSET: usize = 0;
+
+// Interrupt Source 144 Priority
+pub const RV_PLIC_PRIO144_REG_OFFSET: usize = 0x240;
+pub const RV_PLIC_PRIO144_PRIO144_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO144_PRIO144_OFFSET: usize = 0;
+
+// Interrupt Source 145 Priority
+pub const RV_PLIC_PRIO145_REG_OFFSET: usize = 0x244;
+pub const RV_PLIC_PRIO145_PRIO145_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO145_PRIO145_OFFSET: usize = 0;
+
+// Interrupt Source 146 Priority
+pub const RV_PLIC_PRIO146_REG_OFFSET: usize = 0x248;
+pub const RV_PLIC_PRIO146_PRIO146_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO146_PRIO146_OFFSET: usize = 0;
+
+// Interrupt Source 147 Priority
+pub const RV_PLIC_PRIO147_REG_OFFSET: usize = 0x24c;
+pub const RV_PLIC_PRIO147_PRIO147_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO147_PRIO147_OFFSET: usize = 0;
+
+// Interrupt Source 148 Priority
+pub const RV_PLIC_PRIO148_REG_OFFSET: usize = 0x250;
+pub const RV_PLIC_PRIO148_PRIO148_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO148_PRIO148_OFFSET: usize = 0;
+
+// Interrupt Source 149 Priority
+pub const RV_PLIC_PRIO149_REG_OFFSET: usize = 0x254;
+pub const RV_PLIC_PRIO149_PRIO149_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO149_PRIO149_OFFSET: usize = 0;
+
+// Interrupt Source 150 Priority
+pub const RV_PLIC_PRIO150_REG_OFFSET: usize = 0x258;
+pub const RV_PLIC_PRIO150_PRIO150_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO150_PRIO150_OFFSET: usize = 0;
+
+// Interrupt Source 151 Priority
+pub const RV_PLIC_PRIO151_REG_OFFSET: usize = 0x25c;
+pub const RV_PLIC_PRIO151_PRIO151_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO151_PRIO151_OFFSET: usize = 0;
+
+// Interrupt Source 152 Priority
+pub const RV_PLIC_PRIO152_REG_OFFSET: usize = 0x260;
+pub const RV_PLIC_PRIO152_PRIO152_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO152_PRIO152_OFFSET: usize = 0;
+
+// Interrupt Source 153 Priority
+pub const RV_PLIC_PRIO153_REG_OFFSET: usize = 0x264;
+pub const RV_PLIC_PRIO153_PRIO153_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO153_PRIO153_OFFSET: usize = 0;
+
+// Interrupt Source 154 Priority
+pub const RV_PLIC_PRIO154_REG_OFFSET: usize = 0x268;
+pub const RV_PLIC_PRIO154_PRIO154_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO154_PRIO154_OFFSET: usize = 0;
+
+// Interrupt Source 155 Priority
+pub const RV_PLIC_PRIO155_REG_OFFSET: usize = 0x26c;
+pub const RV_PLIC_PRIO155_PRIO155_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO155_PRIO155_OFFSET: usize = 0;
+
+// Interrupt Source 156 Priority
+pub const RV_PLIC_PRIO156_REG_OFFSET: usize = 0x270;
+pub const RV_PLIC_PRIO156_PRIO156_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO156_PRIO156_OFFSET: usize = 0;
+
+// Interrupt Source 157 Priority
+pub const RV_PLIC_PRIO157_REG_OFFSET: usize = 0x274;
+pub const RV_PLIC_PRIO157_PRIO157_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO157_PRIO157_OFFSET: usize = 0;
+
+// Interrupt Source 158 Priority
+pub const RV_PLIC_PRIO158_REG_OFFSET: usize = 0x278;
+pub const RV_PLIC_PRIO158_PRIO158_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO158_PRIO158_OFFSET: usize = 0;
+
+// Interrupt Source 159 Priority
+pub const RV_PLIC_PRIO159_REG_OFFSET: usize = 0x27c;
+pub const RV_PLIC_PRIO159_PRIO159_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO159_PRIO159_OFFSET: usize = 0;
+
+// Interrupt Source 160 Priority
+pub const RV_PLIC_PRIO160_REG_OFFSET: usize = 0x280;
+pub const RV_PLIC_PRIO160_PRIO160_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO160_PRIO160_OFFSET: usize = 0;
+
+// Interrupt Source 161 Priority
+pub const RV_PLIC_PRIO161_REG_OFFSET: usize = 0x284;
+pub const RV_PLIC_PRIO161_PRIO161_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO161_PRIO161_OFFSET: usize = 0;
+
+// Interrupt Source 162 Priority
+pub const RV_PLIC_PRIO162_REG_OFFSET: usize = 0x288;
+pub const RV_PLIC_PRIO162_PRIO162_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO162_PRIO162_OFFSET: usize = 0;
+
+// Interrupt Source 163 Priority
+pub const RV_PLIC_PRIO163_REG_OFFSET: usize = 0x28c;
+pub const RV_PLIC_PRIO163_PRIO163_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO163_PRIO163_OFFSET: usize = 0;
+
+// Interrupt Source 164 Priority
+pub const RV_PLIC_PRIO164_REG_OFFSET: usize = 0x290;
+pub const RV_PLIC_PRIO164_PRIO164_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO164_PRIO164_OFFSET: usize = 0;
+
+// Interrupt Source 165 Priority
+pub const RV_PLIC_PRIO165_REG_OFFSET: usize = 0x294;
+pub const RV_PLIC_PRIO165_PRIO165_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO165_PRIO165_OFFSET: usize = 0;
+
+// Interrupt Source 166 Priority
+pub const RV_PLIC_PRIO166_REG_OFFSET: usize = 0x298;
+pub const RV_PLIC_PRIO166_PRIO166_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO166_PRIO166_OFFSET: usize = 0;
+
+// Interrupt Source 167 Priority
+pub const RV_PLIC_PRIO167_REG_OFFSET: usize = 0x29c;
+pub const RV_PLIC_PRIO167_PRIO167_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO167_PRIO167_OFFSET: usize = 0;
+
+// Interrupt Source 168 Priority
+pub const RV_PLIC_PRIO168_REG_OFFSET: usize = 0x2a0;
+pub const RV_PLIC_PRIO168_PRIO168_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO168_PRIO168_OFFSET: usize = 0;
+
+// Interrupt Source 169 Priority
+pub const RV_PLIC_PRIO169_REG_OFFSET: usize = 0x2a4;
+pub const RV_PLIC_PRIO169_PRIO169_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO169_PRIO169_OFFSET: usize = 0;
+
+// Interrupt Source 170 Priority
+pub const RV_PLIC_PRIO170_REG_OFFSET: usize = 0x2a8;
+pub const RV_PLIC_PRIO170_PRIO170_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO170_PRIO170_OFFSET: usize = 0;
+
+// Interrupt Source 171 Priority
+pub const RV_PLIC_PRIO171_REG_OFFSET: usize = 0x2ac;
+pub const RV_PLIC_PRIO171_PRIO171_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO171_PRIO171_OFFSET: usize = 0;
+
+// Interrupt Source 172 Priority
+pub const RV_PLIC_PRIO172_REG_OFFSET: usize = 0x2b0;
+pub const RV_PLIC_PRIO172_PRIO172_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO172_PRIO172_OFFSET: usize = 0;
+
+// Interrupt Source 173 Priority
+pub const RV_PLIC_PRIO173_REG_OFFSET: usize = 0x2b4;
+pub const RV_PLIC_PRIO173_PRIO173_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO173_PRIO173_OFFSET: usize = 0;
+
+// Interrupt Source 174 Priority
+pub const RV_PLIC_PRIO174_REG_OFFSET: usize = 0x2b8;
+pub const RV_PLIC_PRIO174_PRIO174_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO174_PRIO174_OFFSET: usize = 0;
+
+// Interrupt Source 175 Priority
+pub const RV_PLIC_PRIO175_REG_OFFSET: usize = 0x2bc;
+pub const RV_PLIC_PRIO175_PRIO175_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO175_PRIO175_OFFSET: usize = 0;
+
+// Interrupt Source 176 Priority
+pub const RV_PLIC_PRIO176_REG_OFFSET: usize = 0x2c0;
+pub const RV_PLIC_PRIO176_PRIO176_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO176_PRIO176_OFFSET: usize = 0;
+
+// Interrupt Source 177 Priority
+pub const RV_PLIC_PRIO177_REG_OFFSET: usize = 0x2c4;
+pub const RV_PLIC_PRIO177_PRIO177_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO177_PRIO177_OFFSET: usize = 0;
+
+// Interrupt Source 178 Priority
+pub const RV_PLIC_PRIO178_REG_OFFSET: usize = 0x2c8;
+pub const RV_PLIC_PRIO178_PRIO178_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO178_PRIO178_OFFSET: usize = 0;
+
+// Interrupt Source 179 Priority
+pub const RV_PLIC_PRIO179_REG_OFFSET: usize = 0x2cc;
+pub const RV_PLIC_PRIO179_PRIO179_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO179_PRIO179_OFFSET: usize = 0;
+
+// Interrupt Source 180 Priority
+pub const RV_PLIC_PRIO180_REG_OFFSET: usize = 0x2d0;
+pub const RV_PLIC_PRIO180_PRIO180_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO180_PRIO180_OFFSET: usize = 0;
+
+// Interrupt Source 181 Priority
+pub const RV_PLIC_PRIO181_REG_OFFSET: usize = 0x2d4;
+pub const RV_PLIC_PRIO181_PRIO181_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO181_PRIO181_OFFSET: usize = 0;
+
+// Interrupt Source 182 Priority
+pub const RV_PLIC_PRIO182_REG_OFFSET: usize = 0x2d8;
+pub const RV_PLIC_PRIO182_PRIO182_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO182_PRIO182_OFFSET: usize = 0;
+
+// Interrupt Source 183 Priority
+pub const RV_PLIC_PRIO183_REG_OFFSET: usize = 0x2dc;
+pub const RV_PLIC_PRIO183_PRIO183_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO183_PRIO183_OFFSET: usize = 0;
+
+// Interrupt Source 184 Priority
+pub const RV_PLIC_PRIO184_REG_OFFSET: usize = 0x2e0;
+pub const RV_PLIC_PRIO184_PRIO184_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO184_PRIO184_OFFSET: usize = 0;
+
+// Interrupt Source 185 Priority
+pub const RV_PLIC_PRIO185_REG_OFFSET: usize = 0x2e4;
+pub const RV_PLIC_PRIO185_PRIO185_MASK: u32 = 0x7;
+pub const RV_PLIC_PRIO185_PRIO185_OFFSET: usize = 0;
+
// Interrupt Pending (common parameters)
pub const RV_PLIC_IP_P_FIELD_WIDTH: u32 = 1;
pub const RV_PLIC_IP_P_FIELDS_PER_REG: u32 = 32;
pub const RV_PLIC_IP_MULTIREG_COUNT: u32 = 6;
// Interrupt Pending
-pub const RV_PLIC_IP_0_REG_OFFSET: usize = 0x0;
+pub const RV_PLIC_IP_0_REG_OFFSET: usize = 0x1000;
pub const RV_PLIC_IP_0_P_0_BIT: u32 = 0;
pub const RV_PLIC_IP_0_P_1_BIT: u32 = 1;
pub const RV_PLIC_IP_0_P_2_BIT: u32 = 2;
@@ -66,7 +996,7 @@
pub const RV_PLIC_IP_0_P_31_BIT: u32 = 31;
// Interrupt Pending
-pub const RV_PLIC_IP_1_REG_OFFSET: usize = 0x4;
+pub const RV_PLIC_IP_1_REG_OFFSET: usize = 0x1004;
pub const RV_PLIC_IP_1_P_32_BIT: u32 = 0;
pub const RV_PLIC_IP_1_P_33_BIT: u32 = 1;
pub const RV_PLIC_IP_1_P_34_BIT: u32 = 2;
@@ -101,7 +1031,7 @@
pub const RV_PLIC_IP_1_P_63_BIT: u32 = 31;
// Interrupt Pending
-pub const RV_PLIC_IP_2_REG_OFFSET: usize = 0x8;
+pub const RV_PLIC_IP_2_REG_OFFSET: usize = 0x1008;
pub const RV_PLIC_IP_2_P_64_BIT: u32 = 0;
pub const RV_PLIC_IP_2_P_65_BIT: u32 = 1;
pub const RV_PLIC_IP_2_P_66_BIT: u32 = 2;
@@ -136,7 +1066,7 @@
pub const RV_PLIC_IP_2_P_95_BIT: u32 = 31;
// Interrupt Pending
-pub const RV_PLIC_IP_3_REG_OFFSET: usize = 0xc;
+pub const RV_PLIC_IP_3_REG_OFFSET: usize = 0x100c;
pub const RV_PLIC_IP_3_P_96_BIT: u32 = 0;
pub const RV_PLIC_IP_3_P_97_BIT: u32 = 1;
pub const RV_PLIC_IP_3_P_98_BIT: u32 = 2;
@@ -171,7 +1101,7 @@
pub const RV_PLIC_IP_3_P_127_BIT: u32 = 31;
// Interrupt Pending
-pub const RV_PLIC_IP_4_REG_OFFSET: usize = 0x10;
+pub const RV_PLIC_IP_4_REG_OFFSET: usize = 0x1010;
pub const RV_PLIC_IP_4_P_128_BIT: u32 = 0;
pub const RV_PLIC_IP_4_P_129_BIT: u32 = 1;
pub const RV_PLIC_IP_4_P_130_BIT: u32 = 2;
@@ -206,7 +1136,7 @@
pub const RV_PLIC_IP_4_P_159_BIT: u32 = 31;
// Interrupt Pending
-pub const RV_PLIC_IP_5_REG_OFFSET: usize = 0x14;
+pub const RV_PLIC_IP_5_REG_OFFSET: usize = 0x1014;
pub const RV_PLIC_IP_5_P_160_BIT: u32 = 0;
pub const RV_PLIC_IP_5_P_161_BIT: u32 = 1;
pub const RV_PLIC_IP_5_P_162_BIT: u32 = 2;
@@ -230,1127 +1160,9 @@
pub const RV_PLIC_IP_5_P_180_BIT: u32 = 20;
pub const RV_PLIC_IP_5_P_181_BIT: u32 = 21;
pub const RV_PLIC_IP_5_P_182_BIT: u32 = 22;
-
-// Interrupt Source mode. 0: Level, 1: Edge-triggered (common parameters)
-pub const RV_PLIC_LE_LE_FIELD_WIDTH: u32 = 1;
-pub const RV_PLIC_LE_LE_FIELDS_PER_REG: u32 = 32;
-pub const RV_PLIC_LE_MULTIREG_COUNT: u32 = 6;
-
-// Interrupt Source mode. 0: Level, 1: Edge-triggered
-pub const RV_PLIC_LE_0_REG_OFFSET: usize = 0x18;
-pub const RV_PLIC_LE_0_LE_0_BIT: u32 = 0;
-pub const RV_PLIC_LE_0_LE_1_BIT: u32 = 1;
-pub const RV_PLIC_LE_0_LE_2_BIT: u32 = 2;
-pub const RV_PLIC_LE_0_LE_3_BIT: u32 = 3;
-pub const RV_PLIC_LE_0_LE_4_BIT: u32 = 4;
-pub const RV_PLIC_LE_0_LE_5_BIT: u32 = 5;
-pub const RV_PLIC_LE_0_LE_6_BIT: u32 = 6;
-pub const RV_PLIC_LE_0_LE_7_BIT: u32 = 7;
-pub const RV_PLIC_LE_0_LE_8_BIT: u32 = 8;
-pub const RV_PLIC_LE_0_LE_9_BIT: u32 = 9;
-pub const RV_PLIC_LE_0_LE_10_BIT: u32 = 10;
-pub const RV_PLIC_LE_0_LE_11_BIT: u32 = 11;
-pub const RV_PLIC_LE_0_LE_12_BIT: u32 = 12;
-pub const RV_PLIC_LE_0_LE_13_BIT: u32 = 13;
-pub const RV_PLIC_LE_0_LE_14_BIT: u32 = 14;
-pub const RV_PLIC_LE_0_LE_15_BIT: u32 = 15;
-pub const RV_PLIC_LE_0_LE_16_BIT: u32 = 16;
-pub const RV_PLIC_LE_0_LE_17_BIT: u32 = 17;
-pub const RV_PLIC_LE_0_LE_18_BIT: u32 = 18;
-pub const RV_PLIC_LE_0_LE_19_BIT: u32 = 19;
-pub const RV_PLIC_LE_0_LE_20_BIT: u32 = 20;
-pub const RV_PLIC_LE_0_LE_21_BIT: u32 = 21;
-pub const RV_PLIC_LE_0_LE_22_BIT: u32 = 22;
-pub const RV_PLIC_LE_0_LE_23_BIT: u32 = 23;
-pub const RV_PLIC_LE_0_LE_24_BIT: u32 = 24;
-pub const RV_PLIC_LE_0_LE_25_BIT: u32 = 25;
-pub const RV_PLIC_LE_0_LE_26_BIT: u32 = 26;
-pub const RV_PLIC_LE_0_LE_27_BIT: u32 = 27;
-pub const RV_PLIC_LE_0_LE_28_BIT: u32 = 28;
-pub const RV_PLIC_LE_0_LE_29_BIT: u32 = 29;
-pub const RV_PLIC_LE_0_LE_30_BIT: u32 = 30;
-pub const RV_PLIC_LE_0_LE_31_BIT: u32 = 31;
-
-// Interrupt Source mode. 0: Level, 1: Edge-triggered
-pub const RV_PLIC_LE_1_REG_OFFSET: usize = 0x1c;
-pub const RV_PLIC_LE_1_LE_32_BIT: u32 = 0;
-pub const RV_PLIC_LE_1_LE_33_BIT: u32 = 1;
-pub const RV_PLIC_LE_1_LE_34_BIT: u32 = 2;
-pub const RV_PLIC_LE_1_LE_35_BIT: u32 = 3;
-pub const RV_PLIC_LE_1_LE_36_BIT: u32 = 4;
-pub const RV_PLIC_LE_1_LE_37_BIT: u32 = 5;
-pub const RV_PLIC_LE_1_LE_38_BIT: u32 = 6;
-pub const RV_PLIC_LE_1_LE_39_BIT: u32 = 7;
-pub const RV_PLIC_LE_1_LE_40_BIT: u32 = 8;
-pub const RV_PLIC_LE_1_LE_41_BIT: u32 = 9;
-pub const RV_PLIC_LE_1_LE_42_BIT: u32 = 10;
-pub const RV_PLIC_LE_1_LE_43_BIT: u32 = 11;
-pub const RV_PLIC_LE_1_LE_44_BIT: u32 = 12;
-pub const RV_PLIC_LE_1_LE_45_BIT: u32 = 13;
-pub const RV_PLIC_LE_1_LE_46_BIT: u32 = 14;
-pub const RV_PLIC_LE_1_LE_47_BIT: u32 = 15;
-pub const RV_PLIC_LE_1_LE_48_BIT: u32 = 16;
-pub const RV_PLIC_LE_1_LE_49_BIT: u32 = 17;
-pub const RV_PLIC_LE_1_LE_50_BIT: u32 = 18;
-pub const RV_PLIC_LE_1_LE_51_BIT: u32 = 19;
-pub const RV_PLIC_LE_1_LE_52_BIT: u32 = 20;
-pub const RV_PLIC_LE_1_LE_53_BIT: u32 = 21;
-pub const RV_PLIC_LE_1_LE_54_BIT: u32 = 22;
-pub const RV_PLIC_LE_1_LE_55_BIT: u32 = 23;
-pub const RV_PLIC_LE_1_LE_56_BIT: u32 = 24;
-pub const RV_PLIC_LE_1_LE_57_BIT: u32 = 25;
-pub const RV_PLIC_LE_1_LE_58_BIT: u32 = 26;
-pub const RV_PLIC_LE_1_LE_59_BIT: u32 = 27;
-pub const RV_PLIC_LE_1_LE_60_BIT: u32 = 28;
-pub const RV_PLIC_LE_1_LE_61_BIT: u32 = 29;
-pub const RV_PLIC_LE_1_LE_62_BIT: u32 = 30;
-pub const RV_PLIC_LE_1_LE_63_BIT: u32 = 31;
-
-// Interrupt Source mode. 0: Level, 1: Edge-triggered
-pub const RV_PLIC_LE_2_REG_OFFSET: usize = 0x20;
-pub const RV_PLIC_LE_2_LE_64_BIT: u32 = 0;
-pub const RV_PLIC_LE_2_LE_65_BIT: u32 = 1;
-pub const RV_PLIC_LE_2_LE_66_BIT: u32 = 2;
-pub const RV_PLIC_LE_2_LE_67_BIT: u32 = 3;
-pub const RV_PLIC_LE_2_LE_68_BIT: u32 = 4;
-pub const RV_PLIC_LE_2_LE_69_BIT: u32 = 5;
-pub const RV_PLIC_LE_2_LE_70_BIT: u32 = 6;
-pub const RV_PLIC_LE_2_LE_71_BIT: u32 = 7;
-pub const RV_PLIC_LE_2_LE_72_BIT: u32 = 8;
-pub const RV_PLIC_LE_2_LE_73_BIT: u32 = 9;
-pub const RV_PLIC_LE_2_LE_74_BIT: u32 = 10;
-pub const RV_PLIC_LE_2_LE_75_BIT: u32 = 11;
-pub const RV_PLIC_LE_2_LE_76_BIT: u32 = 12;
-pub const RV_PLIC_LE_2_LE_77_BIT: u32 = 13;
-pub const RV_PLIC_LE_2_LE_78_BIT: u32 = 14;
-pub const RV_PLIC_LE_2_LE_79_BIT: u32 = 15;
-pub const RV_PLIC_LE_2_LE_80_BIT: u32 = 16;
-pub const RV_PLIC_LE_2_LE_81_BIT: u32 = 17;
-pub const RV_PLIC_LE_2_LE_82_BIT: u32 = 18;
-pub const RV_PLIC_LE_2_LE_83_BIT: u32 = 19;
-pub const RV_PLIC_LE_2_LE_84_BIT: u32 = 20;
-pub const RV_PLIC_LE_2_LE_85_BIT: u32 = 21;
-pub const RV_PLIC_LE_2_LE_86_BIT: u32 = 22;
-pub const RV_PLIC_LE_2_LE_87_BIT: u32 = 23;
-pub const RV_PLIC_LE_2_LE_88_BIT: u32 = 24;
-pub const RV_PLIC_LE_2_LE_89_BIT: u32 = 25;
-pub const RV_PLIC_LE_2_LE_90_BIT: u32 = 26;
-pub const RV_PLIC_LE_2_LE_91_BIT: u32 = 27;
-pub const RV_PLIC_LE_2_LE_92_BIT: u32 = 28;
-pub const RV_PLIC_LE_2_LE_93_BIT: u32 = 29;
-pub const RV_PLIC_LE_2_LE_94_BIT: u32 = 30;
-pub const RV_PLIC_LE_2_LE_95_BIT: u32 = 31;
-
-// Interrupt Source mode. 0: Level, 1: Edge-triggered
-pub const RV_PLIC_LE_3_REG_OFFSET: usize = 0x24;
-pub const RV_PLIC_LE_3_LE_96_BIT: u32 = 0;
-pub const RV_PLIC_LE_3_LE_97_BIT: u32 = 1;
-pub const RV_PLIC_LE_3_LE_98_BIT: u32 = 2;
-pub const RV_PLIC_LE_3_LE_99_BIT: u32 = 3;
-pub const RV_PLIC_LE_3_LE_100_BIT: u32 = 4;
-pub const RV_PLIC_LE_3_LE_101_BIT: u32 = 5;
-pub const RV_PLIC_LE_3_LE_102_BIT: u32 = 6;
-pub const RV_PLIC_LE_3_LE_103_BIT: u32 = 7;
-pub const RV_PLIC_LE_3_LE_104_BIT: u32 = 8;
-pub const RV_PLIC_LE_3_LE_105_BIT: u32 = 9;
-pub const RV_PLIC_LE_3_LE_106_BIT: u32 = 10;
-pub const RV_PLIC_LE_3_LE_107_BIT: u32 = 11;
-pub const RV_PLIC_LE_3_LE_108_BIT: u32 = 12;
-pub const RV_PLIC_LE_3_LE_109_BIT: u32 = 13;
-pub const RV_PLIC_LE_3_LE_110_BIT: u32 = 14;
-pub const RV_PLIC_LE_3_LE_111_BIT: u32 = 15;
-pub const RV_PLIC_LE_3_LE_112_BIT: u32 = 16;
-pub const RV_PLIC_LE_3_LE_113_BIT: u32 = 17;
-pub const RV_PLIC_LE_3_LE_114_BIT: u32 = 18;
-pub const RV_PLIC_LE_3_LE_115_BIT: u32 = 19;
-pub const RV_PLIC_LE_3_LE_116_BIT: u32 = 20;
-pub const RV_PLIC_LE_3_LE_117_BIT: u32 = 21;
-pub const RV_PLIC_LE_3_LE_118_BIT: u32 = 22;
-pub const RV_PLIC_LE_3_LE_119_BIT: u32 = 23;
-pub const RV_PLIC_LE_3_LE_120_BIT: u32 = 24;
-pub const RV_PLIC_LE_3_LE_121_BIT: u32 = 25;
-pub const RV_PLIC_LE_3_LE_122_BIT: u32 = 26;
-pub const RV_PLIC_LE_3_LE_123_BIT: u32 = 27;
-pub const RV_PLIC_LE_3_LE_124_BIT: u32 = 28;
-pub const RV_PLIC_LE_3_LE_125_BIT: u32 = 29;
-pub const RV_PLIC_LE_3_LE_126_BIT: u32 = 30;
-pub const RV_PLIC_LE_3_LE_127_BIT: u32 = 31;
-
-// Interrupt Source mode. 0: Level, 1: Edge-triggered
-pub const RV_PLIC_LE_4_REG_OFFSET: usize = 0x28;
-pub const RV_PLIC_LE_4_LE_128_BIT: u32 = 0;
-pub const RV_PLIC_LE_4_LE_129_BIT: u32 = 1;
-pub const RV_PLIC_LE_4_LE_130_BIT: u32 = 2;
-pub const RV_PLIC_LE_4_LE_131_BIT: u32 = 3;
-pub const RV_PLIC_LE_4_LE_132_BIT: u32 = 4;
-pub const RV_PLIC_LE_4_LE_133_BIT: u32 = 5;
-pub const RV_PLIC_LE_4_LE_134_BIT: u32 = 6;
-pub const RV_PLIC_LE_4_LE_135_BIT: u32 = 7;
-pub const RV_PLIC_LE_4_LE_136_BIT: u32 = 8;
-pub const RV_PLIC_LE_4_LE_137_BIT: u32 = 9;
-pub const RV_PLIC_LE_4_LE_138_BIT: u32 = 10;
-pub const RV_PLIC_LE_4_LE_139_BIT: u32 = 11;
-pub const RV_PLIC_LE_4_LE_140_BIT: u32 = 12;
-pub const RV_PLIC_LE_4_LE_141_BIT: u32 = 13;
-pub const RV_PLIC_LE_4_LE_142_BIT: u32 = 14;
-pub const RV_PLIC_LE_4_LE_143_BIT: u32 = 15;
-pub const RV_PLIC_LE_4_LE_144_BIT: u32 = 16;
-pub const RV_PLIC_LE_4_LE_145_BIT: u32 = 17;
-pub const RV_PLIC_LE_4_LE_146_BIT: u32 = 18;
-pub const RV_PLIC_LE_4_LE_147_BIT: u32 = 19;
-pub const RV_PLIC_LE_4_LE_148_BIT: u32 = 20;
-pub const RV_PLIC_LE_4_LE_149_BIT: u32 = 21;
-pub const RV_PLIC_LE_4_LE_150_BIT: u32 = 22;
-pub const RV_PLIC_LE_4_LE_151_BIT: u32 = 23;
-pub const RV_PLIC_LE_4_LE_152_BIT: u32 = 24;
-pub const RV_PLIC_LE_4_LE_153_BIT: u32 = 25;
-pub const RV_PLIC_LE_4_LE_154_BIT: u32 = 26;
-pub const RV_PLIC_LE_4_LE_155_BIT: u32 = 27;
-pub const RV_PLIC_LE_4_LE_156_BIT: u32 = 28;
-pub const RV_PLIC_LE_4_LE_157_BIT: u32 = 29;
-pub const RV_PLIC_LE_4_LE_158_BIT: u32 = 30;
-pub const RV_PLIC_LE_4_LE_159_BIT: u32 = 31;
-
-// Interrupt Source mode. 0: Level, 1: Edge-triggered
-pub const RV_PLIC_LE_5_REG_OFFSET: usize = 0x2c;
-pub const RV_PLIC_LE_5_LE_160_BIT: u32 = 0;
-pub const RV_PLIC_LE_5_LE_161_BIT: u32 = 1;
-pub const RV_PLIC_LE_5_LE_162_BIT: u32 = 2;
-pub const RV_PLIC_LE_5_LE_163_BIT: u32 = 3;
-pub const RV_PLIC_LE_5_LE_164_BIT: u32 = 4;
-pub const RV_PLIC_LE_5_LE_165_BIT: u32 = 5;
-pub const RV_PLIC_LE_5_LE_166_BIT: u32 = 6;
-pub const RV_PLIC_LE_5_LE_167_BIT: u32 = 7;
-pub const RV_PLIC_LE_5_LE_168_BIT: u32 = 8;
-pub const RV_PLIC_LE_5_LE_169_BIT: u32 = 9;
-pub const RV_PLIC_LE_5_LE_170_BIT: u32 = 10;
-pub const RV_PLIC_LE_5_LE_171_BIT: u32 = 11;
-pub const RV_PLIC_LE_5_LE_172_BIT: u32 = 12;
-pub const RV_PLIC_LE_5_LE_173_BIT: u32 = 13;
-pub const RV_PLIC_LE_5_LE_174_BIT: u32 = 14;
-pub const RV_PLIC_LE_5_LE_175_BIT: u32 = 15;
-pub const RV_PLIC_LE_5_LE_176_BIT: u32 = 16;
-pub const RV_PLIC_LE_5_LE_177_BIT: u32 = 17;
-pub const RV_PLIC_LE_5_LE_178_BIT: u32 = 18;
-pub const RV_PLIC_LE_5_LE_179_BIT: u32 = 19;
-pub const RV_PLIC_LE_5_LE_180_BIT: u32 = 20;
-pub const RV_PLIC_LE_5_LE_181_BIT: u32 = 21;
-pub const RV_PLIC_LE_5_LE_182_BIT: u32 = 22;
-
-// Interrupt Source 0 Priority
-pub const RV_PLIC_PRIO0_REG_OFFSET: usize = 0x30;
-pub const RV_PLIC_PRIO0_PRIO0_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO0_PRIO0_OFFSET: usize = 0;
-
-// Interrupt Source 1 Priority
-pub const RV_PLIC_PRIO1_REG_OFFSET: usize = 0x34;
-pub const RV_PLIC_PRIO1_PRIO1_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO1_PRIO1_OFFSET: usize = 0;
-
-// Interrupt Source 2 Priority
-pub const RV_PLIC_PRIO2_REG_OFFSET: usize = 0x38;
-pub const RV_PLIC_PRIO2_PRIO2_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO2_PRIO2_OFFSET: usize = 0;
-
-// Interrupt Source 3 Priority
-pub const RV_PLIC_PRIO3_REG_OFFSET: usize = 0x3c;
-pub const RV_PLIC_PRIO3_PRIO3_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO3_PRIO3_OFFSET: usize = 0;
-
-// Interrupt Source 4 Priority
-pub const RV_PLIC_PRIO4_REG_OFFSET: usize = 0x40;
-pub const RV_PLIC_PRIO4_PRIO4_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO4_PRIO4_OFFSET: usize = 0;
-
-// Interrupt Source 5 Priority
-pub const RV_PLIC_PRIO5_REG_OFFSET: usize = 0x44;
-pub const RV_PLIC_PRIO5_PRIO5_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO5_PRIO5_OFFSET: usize = 0;
-
-// Interrupt Source 6 Priority
-pub const RV_PLIC_PRIO6_REG_OFFSET: usize = 0x48;
-pub const RV_PLIC_PRIO6_PRIO6_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO6_PRIO6_OFFSET: usize = 0;
-
-// Interrupt Source 7 Priority
-pub const RV_PLIC_PRIO7_REG_OFFSET: usize = 0x4c;
-pub const RV_PLIC_PRIO7_PRIO7_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO7_PRIO7_OFFSET: usize = 0;
-
-// Interrupt Source 8 Priority
-pub const RV_PLIC_PRIO8_REG_OFFSET: usize = 0x50;
-pub const RV_PLIC_PRIO8_PRIO8_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO8_PRIO8_OFFSET: usize = 0;
-
-// Interrupt Source 9 Priority
-pub const RV_PLIC_PRIO9_REG_OFFSET: usize = 0x54;
-pub const RV_PLIC_PRIO9_PRIO9_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO9_PRIO9_OFFSET: usize = 0;
-
-// Interrupt Source 10 Priority
-pub const RV_PLIC_PRIO10_REG_OFFSET: usize = 0x58;
-pub const RV_PLIC_PRIO10_PRIO10_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO10_PRIO10_OFFSET: usize = 0;
-
-// Interrupt Source 11 Priority
-pub const RV_PLIC_PRIO11_REG_OFFSET: usize = 0x5c;
-pub const RV_PLIC_PRIO11_PRIO11_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO11_PRIO11_OFFSET: usize = 0;
-
-// Interrupt Source 12 Priority
-pub const RV_PLIC_PRIO12_REG_OFFSET: usize = 0x60;
-pub const RV_PLIC_PRIO12_PRIO12_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO12_PRIO12_OFFSET: usize = 0;
-
-// Interrupt Source 13 Priority
-pub const RV_PLIC_PRIO13_REG_OFFSET: usize = 0x64;
-pub const RV_PLIC_PRIO13_PRIO13_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO13_PRIO13_OFFSET: usize = 0;
-
-// Interrupt Source 14 Priority
-pub const RV_PLIC_PRIO14_REG_OFFSET: usize = 0x68;
-pub const RV_PLIC_PRIO14_PRIO14_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO14_PRIO14_OFFSET: usize = 0;
-
-// Interrupt Source 15 Priority
-pub const RV_PLIC_PRIO15_REG_OFFSET: usize = 0x6c;
-pub const RV_PLIC_PRIO15_PRIO15_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO15_PRIO15_OFFSET: usize = 0;
-
-// Interrupt Source 16 Priority
-pub const RV_PLIC_PRIO16_REG_OFFSET: usize = 0x70;
-pub const RV_PLIC_PRIO16_PRIO16_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO16_PRIO16_OFFSET: usize = 0;
-
-// Interrupt Source 17 Priority
-pub const RV_PLIC_PRIO17_REG_OFFSET: usize = 0x74;
-pub const RV_PLIC_PRIO17_PRIO17_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO17_PRIO17_OFFSET: usize = 0;
-
-// Interrupt Source 18 Priority
-pub const RV_PLIC_PRIO18_REG_OFFSET: usize = 0x78;
-pub const RV_PLIC_PRIO18_PRIO18_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO18_PRIO18_OFFSET: usize = 0;
-
-// Interrupt Source 19 Priority
-pub const RV_PLIC_PRIO19_REG_OFFSET: usize = 0x7c;
-pub const RV_PLIC_PRIO19_PRIO19_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO19_PRIO19_OFFSET: usize = 0;
-
-// Interrupt Source 20 Priority
-pub const RV_PLIC_PRIO20_REG_OFFSET: usize = 0x80;
-pub const RV_PLIC_PRIO20_PRIO20_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO20_PRIO20_OFFSET: usize = 0;
-
-// Interrupt Source 21 Priority
-pub const RV_PLIC_PRIO21_REG_OFFSET: usize = 0x84;
-pub const RV_PLIC_PRIO21_PRIO21_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO21_PRIO21_OFFSET: usize = 0;
-
-// Interrupt Source 22 Priority
-pub const RV_PLIC_PRIO22_REG_OFFSET: usize = 0x88;
-pub const RV_PLIC_PRIO22_PRIO22_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO22_PRIO22_OFFSET: usize = 0;
-
-// Interrupt Source 23 Priority
-pub const RV_PLIC_PRIO23_REG_OFFSET: usize = 0x8c;
-pub const RV_PLIC_PRIO23_PRIO23_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO23_PRIO23_OFFSET: usize = 0;
-
-// Interrupt Source 24 Priority
-pub const RV_PLIC_PRIO24_REG_OFFSET: usize = 0x90;
-pub const RV_PLIC_PRIO24_PRIO24_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO24_PRIO24_OFFSET: usize = 0;
-
-// Interrupt Source 25 Priority
-pub const RV_PLIC_PRIO25_REG_OFFSET: usize = 0x94;
-pub const RV_PLIC_PRIO25_PRIO25_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO25_PRIO25_OFFSET: usize = 0;
-
-// Interrupt Source 26 Priority
-pub const RV_PLIC_PRIO26_REG_OFFSET: usize = 0x98;
-pub const RV_PLIC_PRIO26_PRIO26_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO26_PRIO26_OFFSET: usize = 0;
-
-// Interrupt Source 27 Priority
-pub const RV_PLIC_PRIO27_REG_OFFSET: usize = 0x9c;
-pub const RV_PLIC_PRIO27_PRIO27_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO27_PRIO27_OFFSET: usize = 0;
-
-// Interrupt Source 28 Priority
-pub const RV_PLIC_PRIO28_REG_OFFSET: usize = 0xa0;
-pub const RV_PLIC_PRIO28_PRIO28_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO28_PRIO28_OFFSET: usize = 0;
-
-// Interrupt Source 29 Priority
-pub const RV_PLIC_PRIO29_REG_OFFSET: usize = 0xa4;
-pub const RV_PLIC_PRIO29_PRIO29_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO29_PRIO29_OFFSET: usize = 0;
-
-// Interrupt Source 30 Priority
-pub const RV_PLIC_PRIO30_REG_OFFSET: usize = 0xa8;
-pub const RV_PLIC_PRIO30_PRIO30_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO30_PRIO30_OFFSET: usize = 0;
-
-// Interrupt Source 31 Priority
-pub const RV_PLIC_PRIO31_REG_OFFSET: usize = 0xac;
-pub const RV_PLIC_PRIO31_PRIO31_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO31_PRIO31_OFFSET: usize = 0;
-
-// Interrupt Source 32 Priority
-pub const RV_PLIC_PRIO32_REG_OFFSET: usize = 0xb0;
-pub const RV_PLIC_PRIO32_PRIO32_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO32_PRIO32_OFFSET: usize = 0;
-
-// Interrupt Source 33 Priority
-pub const RV_PLIC_PRIO33_REG_OFFSET: usize = 0xb4;
-pub const RV_PLIC_PRIO33_PRIO33_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO33_PRIO33_OFFSET: usize = 0;
-
-// Interrupt Source 34 Priority
-pub const RV_PLIC_PRIO34_REG_OFFSET: usize = 0xb8;
-pub const RV_PLIC_PRIO34_PRIO34_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO34_PRIO34_OFFSET: usize = 0;
-
-// Interrupt Source 35 Priority
-pub const RV_PLIC_PRIO35_REG_OFFSET: usize = 0xbc;
-pub const RV_PLIC_PRIO35_PRIO35_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO35_PRIO35_OFFSET: usize = 0;
-
-// Interrupt Source 36 Priority
-pub const RV_PLIC_PRIO36_REG_OFFSET: usize = 0xc0;
-pub const RV_PLIC_PRIO36_PRIO36_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO36_PRIO36_OFFSET: usize = 0;
-
-// Interrupt Source 37 Priority
-pub const RV_PLIC_PRIO37_REG_OFFSET: usize = 0xc4;
-pub const RV_PLIC_PRIO37_PRIO37_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO37_PRIO37_OFFSET: usize = 0;
-
-// Interrupt Source 38 Priority
-pub const RV_PLIC_PRIO38_REG_OFFSET: usize = 0xc8;
-pub const RV_PLIC_PRIO38_PRIO38_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO38_PRIO38_OFFSET: usize = 0;
-
-// Interrupt Source 39 Priority
-pub const RV_PLIC_PRIO39_REG_OFFSET: usize = 0xcc;
-pub const RV_PLIC_PRIO39_PRIO39_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO39_PRIO39_OFFSET: usize = 0;
-
-// Interrupt Source 40 Priority
-pub const RV_PLIC_PRIO40_REG_OFFSET: usize = 0xd0;
-pub const RV_PLIC_PRIO40_PRIO40_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO40_PRIO40_OFFSET: usize = 0;
-
-// Interrupt Source 41 Priority
-pub const RV_PLIC_PRIO41_REG_OFFSET: usize = 0xd4;
-pub const RV_PLIC_PRIO41_PRIO41_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO41_PRIO41_OFFSET: usize = 0;
-
-// Interrupt Source 42 Priority
-pub const RV_PLIC_PRIO42_REG_OFFSET: usize = 0xd8;
-pub const RV_PLIC_PRIO42_PRIO42_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO42_PRIO42_OFFSET: usize = 0;
-
-// Interrupt Source 43 Priority
-pub const RV_PLIC_PRIO43_REG_OFFSET: usize = 0xdc;
-pub const RV_PLIC_PRIO43_PRIO43_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO43_PRIO43_OFFSET: usize = 0;
-
-// Interrupt Source 44 Priority
-pub const RV_PLIC_PRIO44_REG_OFFSET: usize = 0xe0;
-pub const RV_PLIC_PRIO44_PRIO44_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO44_PRIO44_OFFSET: usize = 0;
-
-// Interrupt Source 45 Priority
-pub const RV_PLIC_PRIO45_REG_OFFSET: usize = 0xe4;
-pub const RV_PLIC_PRIO45_PRIO45_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO45_PRIO45_OFFSET: usize = 0;
-
-// Interrupt Source 46 Priority
-pub const RV_PLIC_PRIO46_REG_OFFSET: usize = 0xe8;
-pub const RV_PLIC_PRIO46_PRIO46_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO46_PRIO46_OFFSET: usize = 0;
-
-// Interrupt Source 47 Priority
-pub const RV_PLIC_PRIO47_REG_OFFSET: usize = 0xec;
-pub const RV_PLIC_PRIO47_PRIO47_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO47_PRIO47_OFFSET: usize = 0;
-
-// Interrupt Source 48 Priority
-pub const RV_PLIC_PRIO48_REG_OFFSET: usize = 0xf0;
-pub const RV_PLIC_PRIO48_PRIO48_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO48_PRIO48_OFFSET: usize = 0;
-
-// Interrupt Source 49 Priority
-pub const RV_PLIC_PRIO49_REG_OFFSET: usize = 0xf4;
-pub const RV_PLIC_PRIO49_PRIO49_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO49_PRIO49_OFFSET: usize = 0;
-
-// Interrupt Source 50 Priority
-pub const RV_PLIC_PRIO50_REG_OFFSET: usize = 0xf8;
-pub const RV_PLIC_PRIO50_PRIO50_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO50_PRIO50_OFFSET: usize = 0;
-
-// Interrupt Source 51 Priority
-pub const RV_PLIC_PRIO51_REG_OFFSET: usize = 0xfc;
-pub const RV_PLIC_PRIO51_PRIO51_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO51_PRIO51_OFFSET: usize = 0;
-
-// Interrupt Source 52 Priority
-pub const RV_PLIC_PRIO52_REG_OFFSET: usize = 0x100;
-pub const RV_PLIC_PRIO52_PRIO52_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO52_PRIO52_OFFSET: usize = 0;
-
-// Interrupt Source 53 Priority
-pub const RV_PLIC_PRIO53_REG_OFFSET: usize = 0x104;
-pub const RV_PLIC_PRIO53_PRIO53_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO53_PRIO53_OFFSET: usize = 0;
-
-// Interrupt Source 54 Priority
-pub const RV_PLIC_PRIO54_REG_OFFSET: usize = 0x108;
-pub const RV_PLIC_PRIO54_PRIO54_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO54_PRIO54_OFFSET: usize = 0;
-
-// Interrupt Source 55 Priority
-pub const RV_PLIC_PRIO55_REG_OFFSET: usize = 0x10c;
-pub const RV_PLIC_PRIO55_PRIO55_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO55_PRIO55_OFFSET: usize = 0;
-
-// Interrupt Source 56 Priority
-pub const RV_PLIC_PRIO56_REG_OFFSET: usize = 0x110;
-pub const RV_PLIC_PRIO56_PRIO56_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO56_PRIO56_OFFSET: usize = 0;
-
-// Interrupt Source 57 Priority
-pub const RV_PLIC_PRIO57_REG_OFFSET: usize = 0x114;
-pub const RV_PLIC_PRIO57_PRIO57_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO57_PRIO57_OFFSET: usize = 0;
-
-// Interrupt Source 58 Priority
-pub const RV_PLIC_PRIO58_REG_OFFSET: usize = 0x118;
-pub const RV_PLIC_PRIO58_PRIO58_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO58_PRIO58_OFFSET: usize = 0;
-
-// Interrupt Source 59 Priority
-pub const RV_PLIC_PRIO59_REG_OFFSET: usize = 0x11c;
-pub const RV_PLIC_PRIO59_PRIO59_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO59_PRIO59_OFFSET: usize = 0;
-
-// Interrupt Source 60 Priority
-pub const RV_PLIC_PRIO60_REG_OFFSET: usize = 0x120;
-pub const RV_PLIC_PRIO60_PRIO60_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO60_PRIO60_OFFSET: usize = 0;
-
-// Interrupt Source 61 Priority
-pub const RV_PLIC_PRIO61_REG_OFFSET: usize = 0x124;
-pub const RV_PLIC_PRIO61_PRIO61_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO61_PRIO61_OFFSET: usize = 0;
-
-// Interrupt Source 62 Priority
-pub const RV_PLIC_PRIO62_REG_OFFSET: usize = 0x128;
-pub const RV_PLIC_PRIO62_PRIO62_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO62_PRIO62_OFFSET: usize = 0;
-
-// Interrupt Source 63 Priority
-pub const RV_PLIC_PRIO63_REG_OFFSET: usize = 0x12c;
-pub const RV_PLIC_PRIO63_PRIO63_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO63_PRIO63_OFFSET: usize = 0;
-
-// Interrupt Source 64 Priority
-pub const RV_PLIC_PRIO64_REG_OFFSET: usize = 0x130;
-pub const RV_PLIC_PRIO64_PRIO64_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO64_PRIO64_OFFSET: usize = 0;
-
-// Interrupt Source 65 Priority
-pub const RV_PLIC_PRIO65_REG_OFFSET: usize = 0x134;
-pub const RV_PLIC_PRIO65_PRIO65_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO65_PRIO65_OFFSET: usize = 0;
-
-// Interrupt Source 66 Priority
-pub const RV_PLIC_PRIO66_REG_OFFSET: usize = 0x138;
-pub const RV_PLIC_PRIO66_PRIO66_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO66_PRIO66_OFFSET: usize = 0;
-
-// Interrupt Source 67 Priority
-pub const RV_PLIC_PRIO67_REG_OFFSET: usize = 0x13c;
-pub const RV_PLIC_PRIO67_PRIO67_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO67_PRIO67_OFFSET: usize = 0;
-
-// Interrupt Source 68 Priority
-pub const RV_PLIC_PRIO68_REG_OFFSET: usize = 0x140;
-pub const RV_PLIC_PRIO68_PRIO68_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO68_PRIO68_OFFSET: usize = 0;
-
-// Interrupt Source 69 Priority
-pub const RV_PLIC_PRIO69_REG_OFFSET: usize = 0x144;
-pub const RV_PLIC_PRIO69_PRIO69_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO69_PRIO69_OFFSET: usize = 0;
-
-// Interrupt Source 70 Priority
-pub const RV_PLIC_PRIO70_REG_OFFSET: usize = 0x148;
-pub const RV_PLIC_PRIO70_PRIO70_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO70_PRIO70_OFFSET: usize = 0;
-
-// Interrupt Source 71 Priority
-pub const RV_PLIC_PRIO71_REG_OFFSET: usize = 0x14c;
-pub const RV_PLIC_PRIO71_PRIO71_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO71_PRIO71_OFFSET: usize = 0;
-
-// Interrupt Source 72 Priority
-pub const RV_PLIC_PRIO72_REG_OFFSET: usize = 0x150;
-pub const RV_PLIC_PRIO72_PRIO72_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO72_PRIO72_OFFSET: usize = 0;
-
-// Interrupt Source 73 Priority
-pub const RV_PLIC_PRIO73_REG_OFFSET: usize = 0x154;
-pub const RV_PLIC_PRIO73_PRIO73_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO73_PRIO73_OFFSET: usize = 0;
-
-// Interrupt Source 74 Priority
-pub const RV_PLIC_PRIO74_REG_OFFSET: usize = 0x158;
-pub const RV_PLIC_PRIO74_PRIO74_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO74_PRIO74_OFFSET: usize = 0;
-
-// Interrupt Source 75 Priority
-pub const RV_PLIC_PRIO75_REG_OFFSET: usize = 0x15c;
-pub const RV_PLIC_PRIO75_PRIO75_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO75_PRIO75_OFFSET: usize = 0;
-
-// Interrupt Source 76 Priority
-pub const RV_PLIC_PRIO76_REG_OFFSET: usize = 0x160;
-pub const RV_PLIC_PRIO76_PRIO76_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO76_PRIO76_OFFSET: usize = 0;
-
-// Interrupt Source 77 Priority
-pub const RV_PLIC_PRIO77_REG_OFFSET: usize = 0x164;
-pub const RV_PLIC_PRIO77_PRIO77_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO77_PRIO77_OFFSET: usize = 0;
-
-// Interrupt Source 78 Priority
-pub const RV_PLIC_PRIO78_REG_OFFSET: usize = 0x168;
-pub const RV_PLIC_PRIO78_PRIO78_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO78_PRIO78_OFFSET: usize = 0;
-
-// Interrupt Source 79 Priority
-pub const RV_PLIC_PRIO79_REG_OFFSET: usize = 0x16c;
-pub const RV_PLIC_PRIO79_PRIO79_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO79_PRIO79_OFFSET: usize = 0;
-
-// Interrupt Source 80 Priority
-pub const RV_PLIC_PRIO80_REG_OFFSET: usize = 0x170;
-pub const RV_PLIC_PRIO80_PRIO80_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO80_PRIO80_OFFSET: usize = 0;
-
-// Interrupt Source 81 Priority
-pub const RV_PLIC_PRIO81_REG_OFFSET: usize = 0x174;
-pub const RV_PLIC_PRIO81_PRIO81_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO81_PRIO81_OFFSET: usize = 0;
-
-// Interrupt Source 82 Priority
-pub const RV_PLIC_PRIO82_REG_OFFSET: usize = 0x178;
-pub const RV_PLIC_PRIO82_PRIO82_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO82_PRIO82_OFFSET: usize = 0;
-
-// Interrupt Source 83 Priority
-pub const RV_PLIC_PRIO83_REG_OFFSET: usize = 0x17c;
-pub const RV_PLIC_PRIO83_PRIO83_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO83_PRIO83_OFFSET: usize = 0;
-
-// Interrupt Source 84 Priority
-pub const RV_PLIC_PRIO84_REG_OFFSET: usize = 0x180;
-pub const RV_PLIC_PRIO84_PRIO84_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO84_PRIO84_OFFSET: usize = 0;
-
-// Interrupt Source 85 Priority
-pub const RV_PLIC_PRIO85_REG_OFFSET: usize = 0x184;
-pub const RV_PLIC_PRIO85_PRIO85_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO85_PRIO85_OFFSET: usize = 0;
-
-// Interrupt Source 86 Priority
-pub const RV_PLIC_PRIO86_REG_OFFSET: usize = 0x188;
-pub const RV_PLIC_PRIO86_PRIO86_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO86_PRIO86_OFFSET: usize = 0;
-
-// Interrupt Source 87 Priority
-pub const RV_PLIC_PRIO87_REG_OFFSET: usize = 0x18c;
-pub const RV_PLIC_PRIO87_PRIO87_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO87_PRIO87_OFFSET: usize = 0;
-
-// Interrupt Source 88 Priority
-pub const RV_PLIC_PRIO88_REG_OFFSET: usize = 0x190;
-pub const RV_PLIC_PRIO88_PRIO88_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO88_PRIO88_OFFSET: usize = 0;
-
-// Interrupt Source 89 Priority
-pub const RV_PLIC_PRIO89_REG_OFFSET: usize = 0x194;
-pub const RV_PLIC_PRIO89_PRIO89_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO89_PRIO89_OFFSET: usize = 0;
-
-// Interrupt Source 90 Priority
-pub const RV_PLIC_PRIO90_REG_OFFSET: usize = 0x198;
-pub const RV_PLIC_PRIO90_PRIO90_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO90_PRIO90_OFFSET: usize = 0;
-
-// Interrupt Source 91 Priority
-pub const RV_PLIC_PRIO91_REG_OFFSET: usize = 0x19c;
-pub const RV_PLIC_PRIO91_PRIO91_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO91_PRIO91_OFFSET: usize = 0;
-
-// Interrupt Source 92 Priority
-pub const RV_PLIC_PRIO92_REG_OFFSET: usize = 0x1a0;
-pub const RV_PLIC_PRIO92_PRIO92_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO92_PRIO92_OFFSET: usize = 0;
-
-// Interrupt Source 93 Priority
-pub const RV_PLIC_PRIO93_REG_OFFSET: usize = 0x1a4;
-pub const RV_PLIC_PRIO93_PRIO93_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO93_PRIO93_OFFSET: usize = 0;
-
-// Interrupt Source 94 Priority
-pub const RV_PLIC_PRIO94_REG_OFFSET: usize = 0x1a8;
-pub const RV_PLIC_PRIO94_PRIO94_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO94_PRIO94_OFFSET: usize = 0;
-
-// Interrupt Source 95 Priority
-pub const RV_PLIC_PRIO95_REG_OFFSET: usize = 0x1ac;
-pub const RV_PLIC_PRIO95_PRIO95_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO95_PRIO95_OFFSET: usize = 0;
-
-// Interrupt Source 96 Priority
-pub const RV_PLIC_PRIO96_REG_OFFSET: usize = 0x1b0;
-pub const RV_PLIC_PRIO96_PRIO96_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO96_PRIO96_OFFSET: usize = 0;
-
-// Interrupt Source 97 Priority
-pub const RV_PLIC_PRIO97_REG_OFFSET: usize = 0x1b4;
-pub const RV_PLIC_PRIO97_PRIO97_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO97_PRIO97_OFFSET: usize = 0;
-
-// Interrupt Source 98 Priority
-pub const RV_PLIC_PRIO98_REG_OFFSET: usize = 0x1b8;
-pub const RV_PLIC_PRIO98_PRIO98_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO98_PRIO98_OFFSET: usize = 0;
-
-// Interrupt Source 99 Priority
-pub const RV_PLIC_PRIO99_REG_OFFSET: usize = 0x1bc;
-pub const RV_PLIC_PRIO99_PRIO99_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO99_PRIO99_OFFSET: usize = 0;
-
-// Interrupt Source 100 Priority
-pub const RV_PLIC_PRIO100_REG_OFFSET: usize = 0x1c0;
-pub const RV_PLIC_PRIO100_PRIO100_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO100_PRIO100_OFFSET: usize = 0;
-
-// Interrupt Source 101 Priority
-pub const RV_PLIC_PRIO101_REG_OFFSET: usize = 0x1c4;
-pub const RV_PLIC_PRIO101_PRIO101_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO101_PRIO101_OFFSET: usize = 0;
-
-// Interrupt Source 102 Priority
-pub const RV_PLIC_PRIO102_REG_OFFSET: usize = 0x1c8;
-pub const RV_PLIC_PRIO102_PRIO102_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO102_PRIO102_OFFSET: usize = 0;
-
-// Interrupt Source 103 Priority
-pub const RV_PLIC_PRIO103_REG_OFFSET: usize = 0x1cc;
-pub const RV_PLIC_PRIO103_PRIO103_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO103_PRIO103_OFFSET: usize = 0;
-
-// Interrupt Source 104 Priority
-pub const RV_PLIC_PRIO104_REG_OFFSET: usize = 0x1d0;
-pub const RV_PLIC_PRIO104_PRIO104_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO104_PRIO104_OFFSET: usize = 0;
-
-// Interrupt Source 105 Priority
-pub const RV_PLIC_PRIO105_REG_OFFSET: usize = 0x1d4;
-pub const RV_PLIC_PRIO105_PRIO105_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO105_PRIO105_OFFSET: usize = 0;
-
-// Interrupt Source 106 Priority
-pub const RV_PLIC_PRIO106_REG_OFFSET: usize = 0x1d8;
-pub const RV_PLIC_PRIO106_PRIO106_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO106_PRIO106_OFFSET: usize = 0;
-
-// Interrupt Source 107 Priority
-pub const RV_PLIC_PRIO107_REG_OFFSET: usize = 0x1dc;
-pub const RV_PLIC_PRIO107_PRIO107_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO107_PRIO107_OFFSET: usize = 0;
-
-// Interrupt Source 108 Priority
-pub const RV_PLIC_PRIO108_REG_OFFSET: usize = 0x1e0;
-pub const RV_PLIC_PRIO108_PRIO108_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO108_PRIO108_OFFSET: usize = 0;
-
-// Interrupt Source 109 Priority
-pub const RV_PLIC_PRIO109_REG_OFFSET: usize = 0x1e4;
-pub const RV_PLIC_PRIO109_PRIO109_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO109_PRIO109_OFFSET: usize = 0;
-
-// Interrupt Source 110 Priority
-pub const RV_PLIC_PRIO110_REG_OFFSET: usize = 0x1e8;
-pub const RV_PLIC_PRIO110_PRIO110_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO110_PRIO110_OFFSET: usize = 0;
-
-// Interrupt Source 111 Priority
-pub const RV_PLIC_PRIO111_REG_OFFSET: usize = 0x1ec;
-pub const RV_PLIC_PRIO111_PRIO111_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO111_PRIO111_OFFSET: usize = 0;
-
-// Interrupt Source 112 Priority
-pub const RV_PLIC_PRIO112_REG_OFFSET: usize = 0x1f0;
-pub const RV_PLIC_PRIO112_PRIO112_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO112_PRIO112_OFFSET: usize = 0;
-
-// Interrupt Source 113 Priority
-pub const RV_PLIC_PRIO113_REG_OFFSET: usize = 0x1f4;
-pub const RV_PLIC_PRIO113_PRIO113_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO113_PRIO113_OFFSET: usize = 0;
-
-// Interrupt Source 114 Priority
-pub const RV_PLIC_PRIO114_REG_OFFSET: usize = 0x1f8;
-pub const RV_PLIC_PRIO114_PRIO114_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO114_PRIO114_OFFSET: usize = 0;
-
-// Interrupt Source 115 Priority
-pub const RV_PLIC_PRIO115_REG_OFFSET: usize = 0x1fc;
-pub const RV_PLIC_PRIO115_PRIO115_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO115_PRIO115_OFFSET: usize = 0;
-
-// Interrupt Source 116 Priority
-pub const RV_PLIC_PRIO116_REG_OFFSET: usize = 0x200;
-pub const RV_PLIC_PRIO116_PRIO116_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO116_PRIO116_OFFSET: usize = 0;
-
-// Interrupt Source 117 Priority
-pub const RV_PLIC_PRIO117_REG_OFFSET: usize = 0x204;
-pub const RV_PLIC_PRIO117_PRIO117_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO117_PRIO117_OFFSET: usize = 0;
-
-// Interrupt Source 118 Priority
-pub const RV_PLIC_PRIO118_REG_OFFSET: usize = 0x208;
-pub const RV_PLIC_PRIO118_PRIO118_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO118_PRIO118_OFFSET: usize = 0;
-
-// Interrupt Source 119 Priority
-pub const RV_PLIC_PRIO119_REG_OFFSET: usize = 0x20c;
-pub const RV_PLIC_PRIO119_PRIO119_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO119_PRIO119_OFFSET: usize = 0;
-
-// Interrupt Source 120 Priority
-pub const RV_PLIC_PRIO120_REG_OFFSET: usize = 0x210;
-pub const RV_PLIC_PRIO120_PRIO120_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO120_PRIO120_OFFSET: usize = 0;
-
-// Interrupt Source 121 Priority
-pub const RV_PLIC_PRIO121_REG_OFFSET: usize = 0x214;
-pub const RV_PLIC_PRIO121_PRIO121_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO121_PRIO121_OFFSET: usize = 0;
-
-// Interrupt Source 122 Priority
-pub const RV_PLIC_PRIO122_REG_OFFSET: usize = 0x218;
-pub const RV_PLIC_PRIO122_PRIO122_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO122_PRIO122_OFFSET: usize = 0;
-
-// Interrupt Source 123 Priority
-pub const RV_PLIC_PRIO123_REG_OFFSET: usize = 0x21c;
-pub const RV_PLIC_PRIO123_PRIO123_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO123_PRIO123_OFFSET: usize = 0;
-
-// Interrupt Source 124 Priority
-pub const RV_PLIC_PRIO124_REG_OFFSET: usize = 0x220;
-pub const RV_PLIC_PRIO124_PRIO124_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO124_PRIO124_OFFSET: usize = 0;
-
-// Interrupt Source 125 Priority
-pub const RV_PLIC_PRIO125_REG_OFFSET: usize = 0x224;
-pub const RV_PLIC_PRIO125_PRIO125_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO125_PRIO125_OFFSET: usize = 0;
-
-// Interrupt Source 126 Priority
-pub const RV_PLIC_PRIO126_REG_OFFSET: usize = 0x228;
-pub const RV_PLIC_PRIO126_PRIO126_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO126_PRIO126_OFFSET: usize = 0;
-
-// Interrupt Source 127 Priority
-pub const RV_PLIC_PRIO127_REG_OFFSET: usize = 0x22c;
-pub const RV_PLIC_PRIO127_PRIO127_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO127_PRIO127_OFFSET: usize = 0;
-
-// Interrupt Source 128 Priority
-pub const RV_PLIC_PRIO128_REG_OFFSET: usize = 0x230;
-pub const RV_PLIC_PRIO128_PRIO128_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO128_PRIO128_OFFSET: usize = 0;
-
-// Interrupt Source 129 Priority
-pub const RV_PLIC_PRIO129_REG_OFFSET: usize = 0x234;
-pub const RV_PLIC_PRIO129_PRIO129_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO129_PRIO129_OFFSET: usize = 0;
-
-// Interrupt Source 130 Priority
-pub const RV_PLIC_PRIO130_REG_OFFSET: usize = 0x238;
-pub const RV_PLIC_PRIO130_PRIO130_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO130_PRIO130_OFFSET: usize = 0;
-
-// Interrupt Source 131 Priority
-pub const RV_PLIC_PRIO131_REG_OFFSET: usize = 0x23c;
-pub const RV_PLIC_PRIO131_PRIO131_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO131_PRIO131_OFFSET: usize = 0;
-
-// Interrupt Source 132 Priority
-pub const RV_PLIC_PRIO132_REG_OFFSET: usize = 0x240;
-pub const RV_PLIC_PRIO132_PRIO132_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO132_PRIO132_OFFSET: usize = 0;
-
-// Interrupt Source 133 Priority
-pub const RV_PLIC_PRIO133_REG_OFFSET: usize = 0x244;
-pub const RV_PLIC_PRIO133_PRIO133_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO133_PRIO133_OFFSET: usize = 0;
-
-// Interrupt Source 134 Priority
-pub const RV_PLIC_PRIO134_REG_OFFSET: usize = 0x248;
-pub const RV_PLIC_PRIO134_PRIO134_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO134_PRIO134_OFFSET: usize = 0;
-
-// Interrupt Source 135 Priority
-pub const RV_PLIC_PRIO135_REG_OFFSET: usize = 0x24c;
-pub const RV_PLIC_PRIO135_PRIO135_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO135_PRIO135_OFFSET: usize = 0;
-
-// Interrupt Source 136 Priority
-pub const RV_PLIC_PRIO136_REG_OFFSET: usize = 0x250;
-pub const RV_PLIC_PRIO136_PRIO136_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO136_PRIO136_OFFSET: usize = 0;
-
-// Interrupt Source 137 Priority
-pub const RV_PLIC_PRIO137_REG_OFFSET: usize = 0x254;
-pub const RV_PLIC_PRIO137_PRIO137_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO137_PRIO137_OFFSET: usize = 0;
-
-// Interrupt Source 138 Priority
-pub const RV_PLIC_PRIO138_REG_OFFSET: usize = 0x258;
-pub const RV_PLIC_PRIO138_PRIO138_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO138_PRIO138_OFFSET: usize = 0;
-
-// Interrupt Source 139 Priority
-pub const RV_PLIC_PRIO139_REG_OFFSET: usize = 0x25c;
-pub const RV_PLIC_PRIO139_PRIO139_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO139_PRIO139_OFFSET: usize = 0;
-
-// Interrupt Source 140 Priority
-pub const RV_PLIC_PRIO140_REG_OFFSET: usize = 0x260;
-pub const RV_PLIC_PRIO140_PRIO140_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO140_PRIO140_OFFSET: usize = 0;
-
-// Interrupt Source 141 Priority
-pub const RV_PLIC_PRIO141_REG_OFFSET: usize = 0x264;
-pub const RV_PLIC_PRIO141_PRIO141_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO141_PRIO141_OFFSET: usize = 0;
-
-// Interrupt Source 142 Priority
-pub const RV_PLIC_PRIO142_REG_OFFSET: usize = 0x268;
-pub const RV_PLIC_PRIO142_PRIO142_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO142_PRIO142_OFFSET: usize = 0;
-
-// Interrupt Source 143 Priority
-pub const RV_PLIC_PRIO143_REG_OFFSET: usize = 0x26c;
-pub const RV_PLIC_PRIO143_PRIO143_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO143_PRIO143_OFFSET: usize = 0;
-
-// Interrupt Source 144 Priority
-pub const RV_PLIC_PRIO144_REG_OFFSET: usize = 0x270;
-pub const RV_PLIC_PRIO144_PRIO144_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO144_PRIO144_OFFSET: usize = 0;
-
-// Interrupt Source 145 Priority
-pub const RV_PLIC_PRIO145_REG_OFFSET: usize = 0x274;
-pub const RV_PLIC_PRIO145_PRIO145_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO145_PRIO145_OFFSET: usize = 0;
-
-// Interrupt Source 146 Priority
-pub const RV_PLIC_PRIO146_REG_OFFSET: usize = 0x278;
-pub const RV_PLIC_PRIO146_PRIO146_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO146_PRIO146_OFFSET: usize = 0;
-
-// Interrupt Source 147 Priority
-pub const RV_PLIC_PRIO147_REG_OFFSET: usize = 0x27c;
-pub const RV_PLIC_PRIO147_PRIO147_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO147_PRIO147_OFFSET: usize = 0;
-
-// Interrupt Source 148 Priority
-pub const RV_PLIC_PRIO148_REG_OFFSET: usize = 0x280;
-pub const RV_PLIC_PRIO148_PRIO148_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO148_PRIO148_OFFSET: usize = 0;
-
-// Interrupt Source 149 Priority
-pub const RV_PLIC_PRIO149_REG_OFFSET: usize = 0x284;
-pub const RV_PLIC_PRIO149_PRIO149_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO149_PRIO149_OFFSET: usize = 0;
-
-// Interrupt Source 150 Priority
-pub const RV_PLIC_PRIO150_REG_OFFSET: usize = 0x288;
-pub const RV_PLIC_PRIO150_PRIO150_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO150_PRIO150_OFFSET: usize = 0;
-
-// Interrupt Source 151 Priority
-pub const RV_PLIC_PRIO151_REG_OFFSET: usize = 0x28c;
-pub const RV_PLIC_PRIO151_PRIO151_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO151_PRIO151_OFFSET: usize = 0;
-
-// Interrupt Source 152 Priority
-pub const RV_PLIC_PRIO152_REG_OFFSET: usize = 0x290;
-pub const RV_PLIC_PRIO152_PRIO152_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO152_PRIO152_OFFSET: usize = 0;
-
-// Interrupt Source 153 Priority
-pub const RV_PLIC_PRIO153_REG_OFFSET: usize = 0x294;
-pub const RV_PLIC_PRIO153_PRIO153_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO153_PRIO153_OFFSET: usize = 0;
-
-// Interrupt Source 154 Priority
-pub const RV_PLIC_PRIO154_REG_OFFSET: usize = 0x298;
-pub const RV_PLIC_PRIO154_PRIO154_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO154_PRIO154_OFFSET: usize = 0;
-
-// Interrupt Source 155 Priority
-pub const RV_PLIC_PRIO155_REG_OFFSET: usize = 0x29c;
-pub const RV_PLIC_PRIO155_PRIO155_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO155_PRIO155_OFFSET: usize = 0;
-
-// Interrupt Source 156 Priority
-pub const RV_PLIC_PRIO156_REG_OFFSET: usize = 0x2a0;
-pub const RV_PLIC_PRIO156_PRIO156_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO156_PRIO156_OFFSET: usize = 0;
-
-// Interrupt Source 157 Priority
-pub const RV_PLIC_PRIO157_REG_OFFSET: usize = 0x2a4;
-pub const RV_PLIC_PRIO157_PRIO157_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO157_PRIO157_OFFSET: usize = 0;
-
-// Interrupt Source 158 Priority
-pub const RV_PLIC_PRIO158_REG_OFFSET: usize = 0x2a8;
-pub const RV_PLIC_PRIO158_PRIO158_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO158_PRIO158_OFFSET: usize = 0;
-
-// Interrupt Source 159 Priority
-pub const RV_PLIC_PRIO159_REG_OFFSET: usize = 0x2ac;
-pub const RV_PLIC_PRIO159_PRIO159_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO159_PRIO159_OFFSET: usize = 0;
-
-// Interrupt Source 160 Priority
-pub const RV_PLIC_PRIO160_REG_OFFSET: usize = 0x2b0;
-pub const RV_PLIC_PRIO160_PRIO160_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO160_PRIO160_OFFSET: usize = 0;
-
-// Interrupt Source 161 Priority
-pub const RV_PLIC_PRIO161_REG_OFFSET: usize = 0x2b4;
-pub const RV_PLIC_PRIO161_PRIO161_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO161_PRIO161_OFFSET: usize = 0;
-
-// Interrupt Source 162 Priority
-pub const RV_PLIC_PRIO162_REG_OFFSET: usize = 0x2b8;
-pub const RV_PLIC_PRIO162_PRIO162_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO162_PRIO162_OFFSET: usize = 0;
-
-// Interrupt Source 163 Priority
-pub const RV_PLIC_PRIO163_REG_OFFSET: usize = 0x2bc;
-pub const RV_PLIC_PRIO163_PRIO163_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO163_PRIO163_OFFSET: usize = 0;
-
-// Interrupt Source 164 Priority
-pub const RV_PLIC_PRIO164_REG_OFFSET: usize = 0x2c0;
-pub const RV_PLIC_PRIO164_PRIO164_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO164_PRIO164_OFFSET: usize = 0;
-
-// Interrupt Source 165 Priority
-pub const RV_PLIC_PRIO165_REG_OFFSET: usize = 0x2c4;
-pub const RV_PLIC_PRIO165_PRIO165_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO165_PRIO165_OFFSET: usize = 0;
-
-// Interrupt Source 166 Priority
-pub const RV_PLIC_PRIO166_REG_OFFSET: usize = 0x2c8;
-pub const RV_PLIC_PRIO166_PRIO166_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO166_PRIO166_OFFSET: usize = 0;
-
-// Interrupt Source 167 Priority
-pub const RV_PLIC_PRIO167_REG_OFFSET: usize = 0x2cc;
-pub const RV_PLIC_PRIO167_PRIO167_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO167_PRIO167_OFFSET: usize = 0;
-
-// Interrupt Source 168 Priority
-pub const RV_PLIC_PRIO168_REG_OFFSET: usize = 0x2d0;
-pub const RV_PLIC_PRIO168_PRIO168_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO168_PRIO168_OFFSET: usize = 0;
-
-// Interrupt Source 169 Priority
-pub const RV_PLIC_PRIO169_REG_OFFSET: usize = 0x2d4;
-pub const RV_PLIC_PRIO169_PRIO169_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO169_PRIO169_OFFSET: usize = 0;
-
-// Interrupt Source 170 Priority
-pub const RV_PLIC_PRIO170_REG_OFFSET: usize = 0x2d8;
-pub const RV_PLIC_PRIO170_PRIO170_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO170_PRIO170_OFFSET: usize = 0;
-
-// Interrupt Source 171 Priority
-pub const RV_PLIC_PRIO171_REG_OFFSET: usize = 0x2dc;
-pub const RV_PLIC_PRIO171_PRIO171_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO171_PRIO171_OFFSET: usize = 0;
-
-// Interrupt Source 172 Priority
-pub const RV_PLIC_PRIO172_REG_OFFSET: usize = 0x2e0;
-pub const RV_PLIC_PRIO172_PRIO172_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO172_PRIO172_OFFSET: usize = 0;
-
-// Interrupt Source 173 Priority
-pub const RV_PLIC_PRIO173_REG_OFFSET: usize = 0x2e4;
-pub const RV_PLIC_PRIO173_PRIO173_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO173_PRIO173_OFFSET: usize = 0;
-
-// Interrupt Source 174 Priority
-pub const RV_PLIC_PRIO174_REG_OFFSET: usize = 0x2e8;
-pub const RV_PLIC_PRIO174_PRIO174_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO174_PRIO174_OFFSET: usize = 0;
-
-// Interrupt Source 175 Priority
-pub const RV_PLIC_PRIO175_REG_OFFSET: usize = 0x2ec;
-pub const RV_PLIC_PRIO175_PRIO175_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO175_PRIO175_OFFSET: usize = 0;
-
-// Interrupt Source 176 Priority
-pub const RV_PLIC_PRIO176_REG_OFFSET: usize = 0x2f0;
-pub const RV_PLIC_PRIO176_PRIO176_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO176_PRIO176_OFFSET: usize = 0;
-
-// Interrupt Source 177 Priority
-pub const RV_PLIC_PRIO177_REG_OFFSET: usize = 0x2f4;
-pub const RV_PLIC_PRIO177_PRIO177_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO177_PRIO177_OFFSET: usize = 0;
-
-// Interrupt Source 178 Priority
-pub const RV_PLIC_PRIO178_REG_OFFSET: usize = 0x2f8;
-pub const RV_PLIC_PRIO178_PRIO178_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO178_PRIO178_OFFSET: usize = 0;
-
-// Interrupt Source 179 Priority
-pub const RV_PLIC_PRIO179_REG_OFFSET: usize = 0x2fc;
-pub const RV_PLIC_PRIO179_PRIO179_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO179_PRIO179_OFFSET: usize = 0;
-
-// Interrupt Source 180 Priority
-pub const RV_PLIC_PRIO180_REG_OFFSET: usize = 0x300;
-pub const RV_PLIC_PRIO180_PRIO180_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO180_PRIO180_OFFSET: usize = 0;
-
-// Interrupt Source 181 Priority
-pub const RV_PLIC_PRIO181_REG_OFFSET: usize = 0x304;
-pub const RV_PLIC_PRIO181_PRIO181_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO181_PRIO181_OFFSET: usize = 0;
-
-// Interrupt Source 182 Priority
-pub const RV_PLIC_PRIO182_REG_OFFSET: usize = 0x308;
-pub const RV_PLIC_PRIO182_PRIO182_MASK: u32 = 0x7;
-pub const RV_PLIC_PRIO182_PRIO182_OFFSET: usize = 0;
+pub const RV_PLIC_IP_5_P_183_BIT: u32 = 23;
+pub const RV_PLIC_IP_5_P_184_BIT: u32 = 24;
+pub const RV_PLIC_IP_5_P_185_BIT: u32 = 25;
// Interrupt Enable for Target 0 (common parameters)
pub const RV_PLIC_IE0_E_FIELD_WIDTH: u32 = 1;
@@ -1358,7 +1170,7 @@
pub const RV_PLIC_IE0_MULTIREG_COUNT: u32 = 6;
// Interrupt Enable for Target 0
-pub const RV_PLIC_IE0_0_REG_OFFSET: usize = 0x400;
+pub const RV_PLIC_IE0_0_REG_OFFSET: usize = 0x2000;
pub const RV_PLIC_IE0_0_E_0_BIT: u32 = 0;
pub const RV_PLIC_IE0_0_E_1_BIT: u32 = 1;
pub const RV_PLIC_IE0_0_E_2_BIT: u32 = 2;
@@ -1393,7 +1205,7 @@
pub const RV_PLIC_IE0_0_E_31_BIT: u32 = 31;
// Interrupt Enable for Target 0
-pub const RV_PLIC_IE0_1_REG_OFFSET: usize = 0x404;
+pub const RV_PLIC_IE0_1_REG_OFFSET: usize = 0x2004;
pub const RV_PLIC_IE0_1_E_32_BIT: u32 = 0;
pub const RV_PLIC_IE0_1_E_33_BIT: u32 = 1;
pub const RV_PLIC_IE0_1_E_34_BIT: u32 = 2;
@@ -1428,7 +1240,7 @@
pub const RV_PLIC_IE0_1_E_63_BIT: u32 = 31;
// Interrupt Enable for Target 0
-pub const RV_PLIC_IE0_2_REG_OFFSET: usize = 0x408;
+pub const RV_PLIC_IE0_2_REG_OFFSET: usize = 0x2008;
pub const RV_PLIC_IE0_2_E_64_BIT: u32 = 0;
pub const RV_PLIC_IE0_2_E_65_BIT: u32 = 1;
pub const RV_PLIC_IE0_2_E_66_BIT: u32 = 2;
@@ -1463,7 +1275,7 @@
pub const RV_PLIC_IE0_2_E_95_BIT: u32 = 31;
// Interrupt Enable for Target 0
-pub const RV_PLIC_IE0_3_REG_OFFSET: usize = 0x40c;
+pub const RV_PLIC_IE0_3_REG_OFFSET: usize = 0x200c;
pub const RV_PLIC_IE0_3_E_96_BIT: u32 = 0;
pub const RV_PLIC_IE0_3_E_97_BIT: u32 = 1;
pub const RV_PLIC_IE0_3_E_98_BIT: u32 = 2;
@@ -1498,7 +1310,7 @@
pub const RV_PLIC_IE0_3_E_127_BIT: u32 = 31;
// Interrupt Enable for Target 0
-pub const RV_PLIC_IE0_4_REG_OFFSET: usize = 0x410;
+pub const RV_PLIC_IE0_4_REG_OFFSET: usize = 0x2010;
pub const RV_PLIC_IE0_4_E_128_BIT: u32 = 0;
pub const RV_PLIC_IE0_4_E_129_BIT: u32 = 1;
pub const RV_PLIC_IE0_4_E_130_BIT: u32 = 2;
@@ -1533,7 +1345,7 @@
pub const RV_PLIC_IE0_4_E_159_BIT: u32 = 31;
// Interrupt Enable for Target 0
-pub const RV_PLIC_IE0_5_REG_OFFSET: usize = 0x414;
+pub const RV_PLIC_IE0_5_REG_OFFSET: usize = 0x2014;
pub const RV_PLIC_IE0_5_E_160_BIT: u32 = 0;
pub const RV_PLIC_IE0_5_E_161_BIT: u32 = 1;
pub const RV_PLIC_IE0_5_E_162_BIT: u32 = 2;
@@ -1557,20 +1369,9 @@
pub const RV_PLIC_IE0_5_E_180_BIT: u32 = 20;
pub const RV_PLIC_IE0_5_E_181_BIT: u32 = 21;
pub const RV_PLIC_IE0_5_E_182_BIT: u32 = 22;
-
-// Threshold of priority for Target 0
-pub const RV_PLIC_THRESHOLD0_REG_OFFSET: usize = 0x418;
-pub const RV_PLIC_THRESHOLD0_THRESHOLD0_MASK: u32 = 0x7;
-pub const RV_PLIC_THRESHOLD0_THRESHOLD0_OFFSET: usize = 0;
-
-// Claim interrupt by read, complete interrupt by write for Target 0.
-pub const RV_PLIC_CC0_REG_OFFSET: usize = 0x41c;
-pub const RV_PLIC_CC0_CC0_MASK: u32 = 0xff;
-pub const RV_PLIC_CC0_CC0_OFFSET: usize = 0;
-
-// msip for Hart 0.
-pub const RV_PLIC_MSIP0_REG_OFFSET: usize = 0x420;
-pub const RV_PLIC_MSIP0_MSIP0_BIT: u32 = 0;
+pub const RV_PLIC_IE0_5_E_183_BIT: u32 = 23;
+pub const RV_PLIC_IE0_5_E_184_BIT: u32 = 24;
+pub const RV_PLIC_IE0_5_E_185_BIT: u32 = 25;
// Interrupt Enable for Target 1 (common parameters)
pub const RV_PLIC_IE1_E_FIELD_WIDTH: u32 = 1;
@@ -1578,7 +1379,7 @@
pub const RV_PLIC_IE1_MULTIREG_COUNT: u32 = 6;
// Interrupt Enable for Target 1
-pub const RV_PLIC_IE1_0_REG_OFFSET: usize = 0x500;
+pub const RV_PLIC_IE1_0_REG_OFFSET: usize = 0x2100;
pub const RV_PLIC_IE1_0_E_0_BIT: u32 = 0;
pub const RV_PLIC_IE1_0_E_1_BIT: u32 = 1;
pub const RV_PLIC_IE1_0_E_2_BIT: u32 = 2;
@@ -1613,7 +1414,7 @@
pub const RV_PLIC_IE1_0_E_31_BIT: u32 = 31;
// Interrupt Enable for Target 1
-pub const RV_PLIC_IE1_1_REG_OFFSET: usize = 0x504;
+pub const RV_PLIC_IE1_1_REG_OFFSET: usize = 0x2104;
pub const RV_PLIC_IE1_1_E_32_BIT: u32 = 0;
pub const RV_PLIC_IE1_1_E_33_BIT: u32 = 1;
pub const RV_PLIC_IE1_1_E_34_BIT: u32 = 2;
@@ -1648,7 +1449,7 @@
pub const RV_PLIC_IE1_1_E_63_BIT: u32 = 31;
// Interrupt Enable for Target 1
-pub const RV_PLIC_IE1_2_REG_OFFSET: usize = 0x508;
+pub const RV_PLIC_IE1_2_REG_OFFSET: usize = 0x2108;
pub const RV_PLIC_IE1_2_E_64_BIT: u32 = 0;
pub const RV_PLIC_IE1_2_E_65_BIT: u32 = 1;
pub const RV_PLIC_IE1_2_E_66_BIT: u32 = 2;
@@ -1683,7 +1484,7 @@
pub const RV_PLIC_IE1_2_E_95_BIT: u32 = 31;
// Interrupt Enable for Target 1
-pub const RV_PLIC_IE1_3_REG_OFFSET: usize = 0x50c;
+pub const RV_PLIC_IE1_3_REG_OFFSET: usize = 0x210c;
pub const RV_PLIC_IE1_3_E_96_BIT: u32 = 0;
pub const RV_PLIC_IE1_3_E_97_BIT: u32 = 1;
pub const RV_PLIC_IE1_3_E_98_BIT: u32 = 2;
@@ -1718,7 +1519,7 @@
pub const RV_PLIC_IE1_3_E_127_BIT: u32 = 31;
// Interrupt Enable for Target 1
-pub const RV_PLIC_IE1_4_REG_OFFSET: usize = 0x510;
+pub const RV_PLIC_IE1_4_REG_OFFSET: usize = 0x2110;
pub const RV_PLIC_IE1_4_E_128_BIT: u32 = 0;
pub const RV_PLIC_IE1_4_E_129_BIT: u32 = 1;
pub const RV_PLIC_IE1_4_E_130_BIT: u32 = 2;
@@ -1753,7 +1554,7 @@
pub const RV_PLIC_IE1_4_E_159_BIT: u32 = 31;
// Interrupt Enable for Target 1
-pub const RV_PLIC_IE1_5_REG_OFFSET: usize = 0x514;
+pub const RV_PLIC_IE1_5_REG_OFFSET: usize = 0x2114;
pub const RV_PLIC_IE1_5_E_160_BIT: u32 = 0;
pub const RV_PLIC_IE1_5_E_161_BIT: u32 = 1;
pub const RV_PLIC_IE1_5_E_162_BIT: u32 = 2;
@@ -1777,23 +1578,40 @@
pub const RV_PLIC_IE1_5_E_180_BIT: u32 = 20;
pub const RV_PLIC_IE1_5_E_181_BIT: u32 = 21;
pub const RV_PLIC_IE1_5_E_182_BIT: u32 = 22;
+pub const RV_PLIC_IE1_5_E_183_BIT: u32 = 23;
+pub const RV_PLIC_IE1_5_E_184_BIT: u32 = 24;
+pub const RV_PLIC_IE1_5_E_185_BIT: u32 = 25;
+
+// Threshold of priority for Target 0
+pub const RV_PLIC_THRESHOLD0_REG_OFFSET: usize = 0x200000;
+pub const RV_PLIC_THRESHOLD0_THRESHOLD0_MASK: u32 = 0x7;
+pub const RV_PLIC_THRESHOLD0_THRESHOLD0_OFFSET: usize = 0;
+
+// Claim interrupt by read, complete interrupt by write for Target 0.
+pub const RV_PLIC_CC0_REG_OFFSET: usize = 0x200004;
+pub const RV_PLIC_CC0_CC0_MASK: u32 = 0xff;
+pub const RV_PLIC_CC0_CC0_OFFSET: usize = 0;
// Threshold of priority for Target 1
-pub const RV_PLIC_THRESHOLD1_REG_OFFSET: usize = 0x518;
+pub const RV_PLIC_THRESHOLD1_REG_OFFSET: usize = 0x201000;
pub const RV_PLIC_THRESHOLD1_THRESHOLD1_MASK: u32 = 0x7;
pub const RV_PLIC_THRESHOLD1_THRESHOLD1_OFFSET: usize = 0;
// Claim interrupt by read, complete interrupt by write for Target 1.
-pub const RV_PLIC_CC1_REG_OFFSET: usize = 0x51c;
+pub const RV_PLIC_CC1_REG_OFFSET: usize = 0x201004;
pub const RV_PLIC_CC1_CC1_MASK: u32 = 0xff;
pub const RV_PLIC_CC1_CC1_OFFSET: usize = 0;
+// msip for Hart 0.
+pub const RV_PLIC_MSIP0_REG_OFFSET: usize = 0x4000000;
+pub const RV_PLIC_MSIP0_MSIP0_BIT: u32 = 0;
+
// msip for Hart 1.
-pub const RV_PLIC_MSIP1_REG_OFFSET: usize = 0x520;
+pub const RV_PLIC_MSIP1_REG_OFFSET: usize = 0x4000004;
pub const RV_PLIC_MSIP1_MSIP1_BIT: u32 = 0;
// Alert Test Register.
-pub const RV_PLIC_ALERT_TEST_REG_OFFSET: usize = 0x600;
+pub const RV_PLIC_ALERT_TEST_REG_OFFSET: usize = 0x4004000;
pub const RV_PLIC_ALERT_TEST_FATAL_FAULT_BIT: u32 = 0;
-// End generated register constants for RV_PLIC
+// End generated register constants for RV_PLIC
\ No newline at end of file
diff --git a/utils/src/lib.rs b/utils/src/lib.rs
index 5677c81..a8cd612 100644
--- a/utils/src/lib.rs
+++ b/utils/src/lib.rs
@@ -6,7 +6,7 @@
pub mod elf_loader;
pub mod tar_loader;
-pub const SMC_CONTROL_BLOCK: *mut u32 = 0x49000000 as *mut u32;
+pub const SMC_CONTROL_BLOCK: *mut u32 = 0x50020000 as *mut u32;
fn round_up_to_page(addr: u32) -> u32 {
return (addr + 4095) & !4095;
