matcha/tock: add hal support for rv_core_ibex
Change-Id: I804da6fa4217d22eb87338917c46c35127b43cb5
diff --git a/config/src/lib.rs b/config/src/lib.rs
index 08308c6..636ef84 100644
--- a/config/src/lib.rs
+++ b/config/src/lib.rs
@@ -38,5 +38,7 @@
pub const MAILBOX_RTIRQ: u32 = 188; // kTopMatchaPlicIrqIdMailboxSecRtirq
pub const MAILBOX_EIRQ: u32 = 189; // kTopMatchaPlicIrqIdMailboxSecEirq
+pub const RV_CORE_IBEX_SEC_CFG_BASE_ADDRESS: u32 = 0x411F_0000; // TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDRESS
+
pub const UART0_BASE_ADDRESS: u32 = 0x40000000; // TOP_MATCHA_UART0_BASE_ADDR
pub const UART0_BAUDRATE: u32 = 115200;
diff --git a/hal/src/lib.rs b/hal/src/lib.rs
index 4cd367b..20c518c 100644
--- a/hal/src/lib.rs
+++ b/hal/src/lib.rs
@@ -9,6 +9,7 @@
pub mod mailbox_hal;
pub mod plic_constants;
pub mod plic_hal;
+pub mod rv_core_ibex_hal;
pub mod timer_hal;
pub mod uart_hal;
diff --git a/hal/src/rv_core_ibex_hal.rs b/hal/src/rv_core_ibex_hal.rs
new file mode 100644
index 0000000..a2eeecb
--- /dev/null
+++ b/hal/src/rv_core_ibex_hal.rs
@@ -0,0 +1,155 @@
+// Generated register constants for RV_CORE_IBEX.
+// This file is licensed under either of:
+// Apache License, Version 2.0 (LICENSE-APACHE <http://www.apache.org/licenses/LICENSE-2.0>)
+// MIT License (LICENSE-MIT <http://opensource.org/licenses/MIT>)
+
+// Build date: 2023-02-22T20:24:05.302615
+
+// Original reference file: ./hw/opentitan-upstream/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
+use kernel::common::registers::{
+ register_bitfields, register_structs, ReadWrite
+};
+use kernel::common::StaticRef;
+// Number of software triggerable alerts
+pub const RV_CORE_IBEX_PARAM_NUM_SW_ALERTS: u32 = 2;
+// Number of translatable regions per ibex bus
+pub const RV_CORE_IBEX_PARAM_NUM_REGIONS: u32 = 2;
+// Number of scratch words maintained.
+pub const RV_CORE_IBEX_PARAM_NUM_SCRATCH_WORDS: u32 = 8;
+// Number of alerts
+pub const RV_CORE_IBEX_PARAM_NUM_ALERTS: u32 = 4;
+// Register width
+pub const RV_CORE_IBEX_PARAM_REG_WIDTH: u32 = 32;
+
+pub const RV_CORE_IBEX_SEC_REGISTERS: StaticRef<RvCoreIbexRegisters> =
+ unsafe { StaticRef::new(matcha_config::RV_CORE_IBEX_SEC_CFG_BASE_ADDRESS as *const RvCoreIbexRegisters) };
+pub static mut RV_CORE_IBEX_SEC: RvCoreIbex = RvCoreIbex::new(RV_CORE_IBEX_SEC_REGISTERS);
+
+register_structs! {
+ pub RvCoreIbexRegisters {
+ // Alert Test Register
+ (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
+ // Software recoverable error
+ (0x0004 => pub(crate) sw_recov_err: ReadWrite<u32, SW_RECOV_ERR::Register>),
+ // Software fatal error
+ (0x0008 => pub(crate) sw_fatal_err: ReadWrite<u32, SW_FATAL_ERR::Register>),
+ // Ibus address control regwen.
+ (0x000c => pub(crate) ibus_regwen: [ReadWrite<u32, IBUS_REGWEN::Register>; 2]),
+ // Enable Ibus address matching
+ (0x0014 => pub(crate) ibus_addr_en: [ReadWrite<u32, IBUS_ADDR_EN::Register>; 2]),
+ // Matching region programming for ibus.
+ (0x001c => pub(crate) ibus_addr_matching: [ReadWrite<u32, IBUS_ADDR_MATCHING::Register>; 2]),
+ // The remap address after a match has been made.
+ (0x0024 => pub(crate) ibus_remap_addr: [ReadWrite<u32, IBUS_REMAP_ADDR::Register>; 2]),
+ // Dbus address control regwen.
+ (0x002c => pub(crate) dbus_regwen: [ReadWrite<u32, DBUS_REGWEN::Register>; 2]),
+ // Enable dbus address matching
+ (0x0034 => pub(crate) dbus_addr_en: [ReadWrite<u32, DBUS_ADDR_EN::Register>; 2]),
+ // See !!IBUS_ADDR_MATCHING_0 for detailed description.
+ (0x003c => pub(crate) dbus_addr_matching: [ReadWrite<u32, DBUS_ADDR_MATCHING::Register>; 2]),
+ // See !!IBUS_REMAP_ADDR_0 for a detailed description.
+ (0x0044 => pub(crate) dbus_remap_addr: [ReadWrite<u32, DBUS_REMAP_ADDR::Register>; 2]),
+ // Enable mask for NMI.
+ (0x004c => pub(crate) nmi_enable: ReadWrite<u32, NMI_ENABLE::Register>),
+ // Current NMI state
+ (0x0050 => pub(crate) nmi_state: ReadWrite<u32, NMI_STATE::Register>),
+ // error status
+ (0x0054 => pub(crate) err_status: ReadWrite<u32, ERR_STATUS::Register>),
+ // Random data from EDN
+ (0x0058 => pub(crate) rnd_data: ReadWrite<u32, RND_DATA::Register>),
+ // Status of random data in !!RND_DATA
+ (0x005c => pub(crate) rnd_status: ReadWrite<u32, RND_STATUS::Register>),
+ // FPGA build timestamp info.
+ (0x0060 => pub(crate) fpga_info: ReadWrite<u32, FPGA_INFO::Register>),
+ // Memory area: Exposed tlul window for DV only purposes.
+ (0x0080 => pub(crate) dv_sim_window: [ReadWrite<u32>; 8]),
+ (0x00a0 => @END),
+ }
+}
+
+register_bitfields![u32,
+ pub(crate) ALERT_TEST [
+ FATAL_SW_ERR OFFSET(0) NUMBITS(1) [],
+ RECOV_SW_ERR OFFSET(1) NUMBITS(1) [],
+ FATAL_HW_ERR OFFSET(2) NUMBITS(1) [],
+ RECOV_HW_ERR OFFSET(3) NUMBITS(1) []
+ ],
+ pub(crate) SW_RECOV_ERR [
+ VAL OFFSET(0) NUMBITS(4) []
+ ],
+ pub(crate) SW_FATAL_ERR [
+ VAL OFFSET(0) NUMBITS(4) []
+ ],
+ pub(crate) IBUS_REGWEN [
+ EN_0 OFFSET(0) NUMBITS(1) [
+ LOCKED = 0,
+ ENABLED = 1
+ ]
+ ],
+ pub(crate) IBUS_ADDR_EN [
+ IBUS_ADDR_EN OFFSET(0) NUMBITS(1) []
+ ],
+ pub(crate) IBUS_ADDR_MATCHING [
+ IBUS_ADDR_MATCHING OFFSET(0) NUMBITS(32) []
+ ],
+ pub(crate) IBUS_REMAP_ADDR [
+ IBUS_REMAP_ADDR OFFSET(0) NUMBITS(32) []
+ ],
+ pub(crate) DBUS_REGWEN [
+ EN_0 OFFSET(0) NUMBITS(1) [
+ LOCKED = 0,
+ ENABLED = 1
+ ]
+ ],
+ pub(crate) DBUS_ADDR_EN [
+ EN_0 OFFSET(0) NUMBITS(1) []
+ ],
+ pub(crate) DBUS_ADDR_MATCHING [
+ DEBUS_ADDR_MATCHING OFFSET(0) NUMBITS(32) []
+ ],
+ pub(crate) DBUS_REMAP_ADDR [
+ DBUS_REMAP_ADDR OFFSET(0) NUMBITS(32) []
+ ],
+ pub(crate) NMI_ENABLE [
+ ALERT_EN OFFSET(0) NUMBITS(1) [],
+ WDOG_EN OFFSET(1) NUMBITS(1) []
+ ],
+ pub(crate) NMI_STATE [
+ ALERT OFFSET(0) NUMBITS(1) [],
+ WDOG OFFSET(1) NUMBITS(1) []
+ ],
+ pub(crate) ERR_STATUS [
+ REG_INTG_ERR OFFSET(0) NUMBITS(1) [],
+ FATAL_INTG_ERR OFFSET(8) NUMBITS(1) [],
+ FATAL_CORE_ERR OFFSET(9) NUMBITS(1) [],
+ RECOV_CORE_ERR OFFSET(10) NUMBITS(1) []
+ ],
+ pub(crate) RND_DATA [
+ RND_DATA OFFSET(0) NUMBITS(32) []
+ ],
+ pub(crate) RND_STATUS [
+ RND_DATA_VALID OFFSET(0) NUMBITS(1) [],
+ RND_DATA_FIPS OFFSET(1) NUMBITS(1) []
+ ],
+ pub(crate) FPGA_INFO [
+ FPGA_INFO OFFSET(0) NUMBITS(32) []
+ ]
+];
+
+// End generated register constants for RV_CORE_IBEX
+
+pub struct RvCoreIbex {
+ registers: StaticRef<RvCoreIbexRegisters>,
+}
+
+impl RvCoreIbex {
+ pub const fn new(base: StaticRef<RvCoreIbexRegisters>) -> RvCoreIbex {
+ RvCoreIbex {
+ registers: base,
+ }
+ }
+
+ pub fn fpga_version(&self) -> u32 {
+ self.registers.fpga_info.get()
+ }
+}
