Bump riscv-tests revision, run zbb suite

Change-Id: I411f40875aeac50fe90293ad696ce3bfcd7e71e5

build_tools/bazel/repos.bzl

diff --git a/build_tools/bazel/repos.bzl b/build_tools/bazel/repos.bzl
index b36850f..848682e 100644
--- a/build_tools/bazel/repos.bzl
+++ b/build_tools/bazel/repos.bzl
@@ -43,7 +43,7 @@
         name = "riscv-tests",
         build_file = "@kelvin_sw//third_party/riscv:BUILD.riscv-tests",
         remote = "https://github.com/riscv-software-src/riscv-tests",
-        commit = "d4eaa5bd6674b51d3b9b24913713c4638e99cdd9",
+        commit = "a3498c6d2f770af95964a0a7ba46f285cecd1eb3",
         recursive_init_submodules = True,
         patch_args = [
             "-p1",

tests/riscv-tests/BUILD

diff --git a/tests/riscv-tests/BUILD b/tests/riscv-tests/BUILD
index 9a131fc..b37da62 100644
--- a/tests/riscv-tests/BUILD
+++ b/tests/riscv-tests/BUILD
@@ -145,6 +145,61 @@
     ],
 ) for test in RV32UM_TESTS]
 
+# andn.S  clz.S  cpop.S  ctz.S  Makefrag  max.S  maxu.S  min.S  minu.S  orc_b.S  orn.S  rev8.S  rol.S  rori.S  ror.S  sext_b.S  sext_h.S  xnor.S  zext_h.S
+RV32UZBB_TESTS_64 = [
+    "andn",
+    "max",
+    "maxu",
+    "min",
+    "minu",
+    "orn",
+    "sext_b",
+    "sext_h",
+    "xnor",
+    "zext_h",
+]
+
+[kelvin_test(
+    name = "rv32uzbb_{}".format(test),
+    srcs = [
+        "@riscv-tests//:isa/rv64uzbb/{}.S".format(test),
+    ],
+    copts = [
+        "-Itests/riscv-tests",
+        "-Iexternal/riscv-tests/isa/macros/scalar",
+        "-Wno-variadic-macros",
+    ],
+    defines = [
+        "RVTEST_RV64U=RVTEST_RV32U"
+    ],
+    hw_test_size = "small",
+    deps = [
+        ":riscv_tests_base",
+    ],
+) for test in RV32UZBB_TESTS_64]
+
+RV32UZBB_TESTS = [
+    "clz",
+    "cpop",
+    "ctz",
+]
+
+[kelvin_test(
+    name = "rv32uzbb_{}".format(test),
+    srcs = [
+        "@riscv-tests//:isa/rv32uzbb/{}.S".format(test),
+    ],
+    copts = [
+        "-Itests/riscv-tests",
+        "-Iexternal/riscv-tests/isa/macros/scalar",
+        "-Wno-variadic-macros",
+    ],
+    hw_test_size = "small",
+    deps = [
+        ":riscv_tests_base",
+    ],
+) for test in RV32UZBB_TESTS]
+
 kelvin_test(
     name = "rv32mi_mcsr",
     srcs = [