Fix `vsrans` and `vsraqs` spec doc

Remove unsupported data types and modes

Bug: 296481517
Change-Id: Ibb1c5d6d37166ed32467a2460fa2bbc3e8b6e525

docs/kelvin_isa.md

diff --git a/docs/kelvin_isa.md b/docs/kelvin_isa.md
index c69d554..121ba65 100644
--- a/docs/kelvin_isa.md
+++ b/docs/kelvin_isa.md
@@ -1866,8 +1866,8 @@
 
 **Encodings**
 
-vsrans{u}.[b,h,w].{r}.vv.{m} vd, vs1, vs2 \
-vsrans{u}.[b,h,w].{r}.vx.{m} vd, vs1, xs2
+vsrans{u}.[b,h].{r}.vv.{m} vd, vs1, vs2 \
+vsrans{u}.[b,h].{r}.vx.{m} vd, vs1, xs2
 
 **Operation**
 
@@ -1893,8 +1893,8 @@
 
 **Encodings**
 
-vsraqs{u}.[b,h].{r}.vv.{m} vd, vs1, vs2 \
-vsraqs{u}.[b,h].{r}.vx.{m} vd, vs1, xs2
+vsraqs{u}.b.{r}.vv.{m} vd, vs1, vs2 \
+vsraqs{u}.b.{r}.vx.{m} vd, vs1, xs2
 
 **Operation**
 
@@ -1910,7 +1910,7 @@
 ```
 
 Note: The register interleaving is [0,2,1,3] and not [0,1,2,3] as this matches
-vconv/vdwconv requirements, and one vsrxqs is the same as two chained vsrxns.
+vconv/vdwconv requirements, and one vsraqs is the same as two chained vsrans.
 
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