Add riscv CSR tests, enable zicsr

- Add build rules for the riscv-tests csr and mcsr targets, and enable
  the zicsr extension in the device config. Define macros needed to
  compile the tests, as well.

Change-Id: I2fa571359eb44738a4e1c064a8944762d23a819d

platforms/riscv32/devices.bzl

diff --git a/platforms/riscv32/devices.bzl b/platforms/riscv32/devices.bzl
index e6f0b56..8382df2 100644
--- a/platforms/riscv32/devices.bzl
+++ b/platforms/riscv32/devices.bzl
@@ -24,7 +24,7 @@
             "@platforms//os:none",
         ],
         substitutions = {
-            "ARCHITECTURE": "rv32i2p1m_zifencei_zbb",
+            "ARCHITECTURE": "rv32i2p1m_zicsr_zifencei_zbb",
             "ABI": "ilp32",
             "CMODEL": "medany",
             "[STACK_PROTECTOR]": "-fstack-protector-strong",

tests/riscv-tests/BUILD

diff --git a/tests/riscv-tests/BUILD b/tests/riscv-tests/BUILD
index 74b274b..23a147b 100644
--- a/tests/riscv-tests/BUILD
+++ b/tests/riscv-tests/BUILD
@@ -124,6 +124,45 @@
 ) for test in RV32UM_TESTS]
 
 kelvin_test(
+    name = "rv32mi_mcsr",
+    srcs = [
+        "@riscv-tests//:isa/rv64mi/mcsr.S",
+    ],
+    copts = [
+        "-Itests/riscv-tests",
+        "-Iexternal/riscv-tests/isa/macros/scalar",
+        "-Wno-variadic-macros",
+    ],
+    defines = [
+        "RVTEST_RV64M=RVTEST_RV32M",
+    ],
+    hw_test_size = "small",
+    deps = [
+        ":riscv_tests_base",
+    ],
+)
+
+kelvin_test(
+    name = "rv32mi_csr",
+    srcs = [
+        "@riscv-tests//:isa/rv64si/csr.S",
+    ],
+    copts = [
+        "-Itests/riscv-tests",
+        "-Iexternal/riscv-tests/isa/macros/scalar",
+        "-Wno-variadic-macros",
+    ],
+    defines = [
+        "RVTEST_RV64S=RVTEST_RV32M",
+        "__MACHINE_MODE",
+    ],
+    hw_test_size = "small",
+    deps = [
+        ":riscv_tests_base",
+    ],
+)
+
+kelvin_test(
     name = "alu",
     srcs = [
         "alu.cc",

tests/riscv-tests/riscv_test.h

diff --git a/tests/riscv-tests/riscv_test.h b/tests/riscv-tests/riscv_test.h
index 9d86895..b16cbd3 100644
--- a/tests/riscv-tests/riscv_test.h
+++ b/tests/riscv-tests/riscv_test.h
@@ -21,6 +21,9 @@
 #define RVTEST_RV32U \
   .macro init;       \
   .endm
+#define RVTEST_RV32M \
+  .macro init;       \
+  .endm
 #define RVTEST_CODE_BEGIN \
   .globl _start;          \
   _start:
@@ -44,4 +47,10 @@
   .align 4;              \
   .global end_signature; \
   end_signature:
+
+#define MSTATUS_FS (0x00006000)
+#define MSTATUS_MPP (0x00001800)
+#define CAUSE_USER_ECALL (0x8)
+#define CAUSE_ILLEGAL_INSTRUCTION (0x2)
+
 #endif  // TESTS_RISCV_TESTS_RISCV_TEST_H_