sim:config: Refactor cpu2 --> ML Core

Split the single test core (springbok)  vs. shodan integrated ML core
with separated vec_controlblock setting (wMMUs and IRQs)

Change-Id: I68d8d2bd0aa97230612cab3d8a398317b9806f7d

platforms/ml_core.repl

diff --git a/platforms/ml_core.repl b/platforms/ml_core.repl
new file mode 100644
index 0000000..7a0ad98
--- /dev/null
+++ b/platforms/ml_core.repl
@@ -0,0 +1,29 @@
+// Copyright 2022 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// ***************************************************
+// ML Core
+// ***************************************************
+
+cpu2: CPU.SpringbokRiscV32 @ sysbus
+    hartId: 2
+
+// TODO(b/196910893): Revert the temporary change on DMEM memory later
+//RAM_VEC_DMEM      [‘h3400_0000 - ‘h34FF_FFFF)   16MB RAM for Vector core Data
+ram_vec_dmem: Memory.MappedMemory @ sysbus 0x34000000
+    size: 0x01000000
+
+//RAM_VEC_CSR       [‘h3800_0000 - ‘h3800_0FFF)   4KB RAM for SMC core data storage
+ram_vec_csr: Memory.MappedMemory @ sysbus 0x38000000
+    size: 0x00001000

platforms/shodan.repl

diff --git a/platforms/shodan.repl b/platforms/shodan.repl
index e6fcc2e..6431e45 100644
--- a/platforms/shodan.repl
+++ b/platforms/shodan.repl
@@ -1,6 +1,6 @@
 using "sim/config/platforms/smc.repl"
 using "sim/config/platforms/secure.repl"
-using "sim/config/platforms/springbok.repl"
+using "sim/config/platforms/ml_core.repl"
 
 // To model the TLUL mailbox spec, we need a Renode peripheral that listens
 // to address ranges for both endpoints of the mailbox. This is the current
@@ -27,7 +27,12 @@
     rtirq_B -> smc_plic@11 // kTopMatchaPlicIrqIdMailboxSmcRtirq
     eirq_B  -> smc_plic@12 // kTopMatchaPlicIrqIdMailboxSmcEirq
 
-vec_controlblock :
+vec_controlblock : CPU.SpringbokRiscV32_ControlBlock @ sysbus 0x47000000
+    core: cpu2
+    mmuNumWindows: 6 // See: go/shodan-vc-memory
+    mmuVirtualWindowSize: 0x1000000
+    mmuMemorySize: 0x1000000
+    mmuRangeStart: 0x34000000
     HostReqIRQ -> smc_plic@13           // kTopMatchaPlicIrqIdVcTopHostReq @ top_matcha.h
     FinishIRQ -> smc_plic@14            // kTopMatchaPlicIrqIdVcTopFinish @ top_matcha.h
     InstructionFaultIRQ -> smc_plic@15  // kTopMatchaPlicIrqIdVcTopInstructionFault @ top_matcha.h

platforms/springbok.repl

diff --git a/platforms/springbok.repl b/platforms/springbok.repl
index 348b678..37fc388 100644
--- a/platforms/springbok.repl
+++ b/platforms/springbok.repl
@@ -13,24 +13,14 @@
 // limitations under the License.
 
 // ***************************************************
-// Springbok
+// Springbok single test core (no mmu enabled)
 // ***************************************************
 
-cpu2: CPU.SpringbokRiscV32 @ sysbus
-    hartId: 2
-
-// TODO(b/196910893): Revert the temporary change on DMEM memory later
-//RAM_VEC_DMEM      [‘h3400_0000 - ‘h34FF_FFFF)   16MB RAM for Vector core Data
-ram_vec_dmem: Memory.MappedMemory @ sysbus 0x34000000
-    size: 0x01000000
-
-//RAM_VEC_CSR       [‘h3800_0000 - ‘h3800_0FFF)   4KB RAM for SMC core data storage
-ram_vec_csr: Memory.MappedMemory @ sysbus 0x38000000
-    size: 0x00001000
+using "sim/config/platforms/ml_core.repl"
 
 vec_controlblock : CPU.SpringbokRiscV32_ControlBlock @ sysbus 0x47000000
     core: cpu2
-    mmuNumWindows: 6 // See: go/shodan-vc-memory
+    mmuNumWindows: 1
     mmuVirtualWindowSize: 0x1000000
     mmuMemorySize: 0x1000000
     mmuRangeStart: 0x34000000