| // |
| // Copyright (c) 2024 Google LLC |
| // |
| // Licensed under the Apache License, Version 2.0 (the "License"); |
| // you may not use this file except in compliance with the License. |
| // You may obtain a copy of the License at |
| // |
| // https://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, software |
| // distributed under the License is distributed on an "AS IS" BASIS, |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| // See the License for the specific language governing permissions and |
| // limitations under the License. |
| |
| // *************************************************** |
| // Sencha SMC is a CHERIoT RISC-V CPU |
| // *************************************************** |
| |
| // XXX set sysbus address elsewhere |
| cpu1: MpactCPU.MpactCheriotCPU @ sysbus |
| id: 1 |
| cpuType: "Mpact.Cheriot" |
| endianness: Endianess.LittleEndian |
| memoryBase: 0x80000000 |
| memorySize: 0x04000000 |
| revocationMemoryBase: 0x83000000 // Shadow bitmap |
| clintMMRBase: 0 // NB: disables simulator built-in impl |
| |
| ram_smc: MpactPeripheral.MpactCheriotPeripheral @ sysbus 0x80000000 |
| size: 0x04000000 |
| id: 1 // NB: must match MpactCheriotCPU.id |
| |
| // Control block for the SMC, lets us pause/restart the core at an arbitrary PC. |
| smc_control: MpactCPU.SmcCheriot_ControlBlock @ sysbus 0x54020000 |
| cpu: cpu1 |
| pc: 0x80000000 |
| |
| smc_clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000 |
| frequency: 66000000 |
| [0, 1] ->cpu1@[3, 7] |
| |
| smc_plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x60000000 // TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR @ top_matcha.h |
| // Numbers on the left (0 ->) index PLIC GetGPIOs. |
| // |
| // Numbers on the right reference bits in the target MIP. |
| // Bit 11 corresponds MEIP and bit 9 to SEIP. |
| 0 -> cpu1@11 |
| numberOfSources: 42 |
| numberOfContexts: 1 // MEIP only |
| prioritiesEnabled: false |
| |
| // XXX use TrivialUart until cheriot-rtos has an OpenTitan_UART driver |
| uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x54000000 |
