sencha/bancha: use OpenTitan uart
With the addition of Sonata board support the OpenTitan uart is
supported so switch sencha (uart5) + bancha (uart0).
While here cleanup bancha a bit.
Bypass-Presubmit-Reason: only relevant flow passes (shodan flows are broken by futures crate version issue)
Change-Id: I82e4e3e34e80d32d465a3dfd243544a404e4731e
diff --git a/bancha.resc b/bancha.resc
index c8c4255..53da385 100644
--- a/bancha.resc
+++ b/bancha.resc
@@ -28,8 +28,6 @@
include @sim/config/shodan_infrastructure/KelvinCPU.cs
EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.KelvinCPU"
EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.CPU.MlTopControlBlock"
-#include @sim/config/shodan_infrastructure/SmcCheriotCPU.cs
-#include @sim/config/shodan_infrastructure/Mailbox.cs
include @sim/config/shodan_infrastructure/AddressRangeStub.cs
include @sim/config/shodan_infrastructure/MatchaI2S.cs
EnsureTypeIsLoaded "Antmicro.Renode.Peripherals.Sound.MatchaI2S"
@@ -40,14 +38,12 @@
$term_port?=3456
emulation CreateServerSocketTerminal $term_port "term" false
-connector Connect uart5 term
+connector Connect uart0 term
showAnalyzer "uart0-analyzer" sysbus.uart0 Antmicro.Renode.Analyzers.LoggingUartAnalyzer
-showAnalyzer "uart5-analyzer" sysbus.uart5 Antmicro.Renode.Analyzers.LoggingUartAnalyzer
-# Set the uarts host/virt timestamp format. Options: None, Virtual, Host, Full.
+# Set the uart host/virt timestamp format. Options: None, Virtual, Host, Full.
uart0-analyzer TimestampFormat None
-uart5-analyzer TimestampFormat None
cpu0 IsHalted true
$cheriotLibrary ?= @out/cheriot/sim/librenode_mpact_cheriot.so
@@ -55,11 +51,11 @@
# Configure an I$ and a D$.
# Each configuration is a string of the form:
-# "size,block_size,associativity,write_allocate"
-# for instance "8k,16,2,false".
+# "size,block_size,associativity,write_allocate,[c|nc]:<start_address>:<size>*"
+# where the last items optionally specify cacheable (c) and noncacheable (nc)
+# address ranges. For instance "8k,16,2,false" or "1M,16,2,false,c0x100:0x3ff".
# NB: Statistics are collected only when MemProfile is enabled (see below).
#sysbus.cpu0 ICache "8k,16,2,false"
-# NB: D$ can be configured but is not implemented yet
#sysbus.cpu0 DCache "1k,8,1,false"
# Load the boot rom into the 32k rom at 0x8000 (useVirtualAddress = false, allowLoadsOnlyToMemory = false)
@@ -100,10 +96,6 @@
$vector_core_mips ?= 1000
sysbus.cpu2 PerformanceInMips $vector_core_mips
-# NB: model is normally loaded from SPI
-#$kelvin_bin?=@out/cheriot/sim/kelvin.bin
-#sysbus LoadBinary $kelvin_bin 0x5A000000
-
# Start GDB and halt both cores so we can connect GDB before the bootrom has
# started.
# cpu2 does not support GDB. Please follow docs/KelvinIssDebugging.md to debug
diff --git a/platforms/sencha_smc.repl b/platforms/sencha_smc.repl
index f7bbac3..f8487ce 100644
--- a/platforms/sencha_smc.repl
+++ b/platforms/sencha_smc.repl
@@ -24,4 +24,12 @@
cpu: cpu1
pc: 0x80000000
-uart5: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x54000000
+uart5: UART.OpenTitan_UART @ sysbus 0x54000000
+ TxWatermarkIRQ -> smc_plic@1
+ RxWatermarkIRQ -> smc_plic@2
+ TxEmptyIRQ -> smc_plic@3
+ RxOverflowIRQ -> smc_plic@4
+ RxFrameErrorIRQ -> smc_plic@5
+ RxBreakErrorIRQ -> smc_plic@6
+ RxTimeoutIRQ -> smc_plic@7
+ RxParityErrorIRQ -> smc_plic@8
