| // |
| // Copyright (c) 2024 Google LLC |
| // |
| // Licensed under the Apache License, Version 2.0 (the "License"); |
| // you may not use this file except in compliance with the License. |
| // You may obtain a copy of the License at |
| // |
| // https://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, software |
| // distributed under the License is distributed on an "AS IS" BASIS, |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| // See the License for the specific language governing permissions and |
| // limitations under the License. |
| |
| // *************************************************** |
| // Sencha SMC is a CHERIoT RISC-V CPU |
| // *************************************************** |
| |
| using "sim/config/platforms/cheriot.repl" |
| |
| // Control block for the SMC, lets us pause/restart the core at an arbitrary PC. |
| smc_control: MpactCPU.SmcCheriot_ControlBlock @ sysbus 0x54020000 |
| cpu: cpu1 |
| pc: 0x80000000 |
| |
| uart5: UART.OpenTitan_UART @ sysbus 0x54000000 |
| TxWatermarkIRQ -> smc_plic@1 |
| RxWatermarkIRQ -> smc_plic@2 |
| TxEmptyIRQ -> smc_plic@3 |
| RxOverflowIRQ -> smc_plic@4 |
| RxFrameErrorIRQ -> smc_plic@5 |
| RxBreakErrorIRQ -> smc_plic@6 |
| RxTimeoutIRQ -> smc_plic@7 |
| RxParityErrorIRQ -> smc_plic@8 |
