Initial commit of top_sencha
- Copy current configuration of top_matcha, omiting some system
level DV, cdc, rdc, and FPV files for now, with no arch changes
- Do not include autogen'd files here
- Copy exported sparrow folder from the ASIC as a placeholder to
preserve bazel select rules for a future build
-- NOTE: rv_plic_smc.hjson is updated during the hardware gen flow, but
is required to exist before its updated due to how topgen_matcha.py is
set up. rstmgr_sec_cm_testplan.hjson was generated but eventually
manually edited so we include it here.
Change-Id: I5c06443df971f36c66ffd3003f9797183946eb5c
diff --git a/hw/top_sencha/BUILD b/hw/top_sencha/BUILD
new file mode 100644
index 0000000..90dd159
--- /dev/null
+++ b/hw/top_sencha/BUILD
@@ -0,0 +1,199 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+load("@lowrisc_opentitan//rules:autogen.bzl", "autogen_hjson_header")
+load("//rules:autogen.bzl", "autogen_top_gen_hjson")
+
+package(default_visibility = ["//visibility:public"])
+
+autogen_hjson_header(
+ name = "rv_plic_regs",
+ srcs = [
+ "ip_autogen/rv_plic/data/rv_plic.hjson",
+ ],
+)
+
+autogen_hjson_header(
+ name = "rv_plic_smc_regs",
+ srcs = [
+ "ip_autogen/rv_plic_smc/data/rv_plic_smc.hjson",
+ ],
+)
+
+autogen_hjson_header(
+ name = "alert_handler_regs",
+ srcs = [
+ "ip_autogen/alert_handler/data/alert_handler.hjson",
+ ],
+)
+
+# Need to add the template and hjson files to the data to support topgen_matcha.
+# This rule assumes all the top_sencha hjson files are already up-to-date.
+autogen_top_gen_hjson(
+ name = "top_gen_rom_ctrl_hjson",
+ srcs = "//hw/top_sencha/data:top_sencha.hjson",
+ data = [
+ ":all_hjson_files",
+ "@lowrisc_opentitan//hw:all_files",
+ ],
+ output = "data/autogen/top_sencha.gen.rom_ctrl.hjson",
+)
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/ip:all_files",
+ "//hw/top_sencha/data:all_files",
+ "//hw/top_sencha/dv:all_files",
+ "//hw/top_sencha/ip:all_files",
+ "//hw/top_sencha/sw:all_files",
+ ],
+)
+
+filegroup(
+ name = "all_hjson_files",
+ srcs = glob(["ip_autogen/**/*.hjson"]) + [
+ "//hw/ip:all_hjson_files",
+ "//hw/top_sencha/data:all_hjson_files",
+ "//hw/top_sencha/ip:all_hjson_files",
+ ],
+)
+
+cc_library(
+ name = "alert_handler_regs_h",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_sencha/sparrow/hw/top_sencha:alert_handler_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_sencha",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_sencha:alert_handler_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "ast_regs",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_sencha/sparrow/hw/top_sencha:ip/ast/data/ast_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_sencha/ip/ast/data",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_sencha/ip/ast/data:ast_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "clkmgr_regs",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_sencha/sparrow/hw/top_sencha:ip/clkmgr/data/autogen/clkmgr_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_sencha/ip/clkmgr/data/autogen",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_sencha/ip/clkmgr/data/autogen:clkmgr_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "pinmux_regs",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_sencha/sparrow/hw/top_sencha:ip/pinmux/data/autogen/pinmux_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_sencha/ip/pinmux/data/autogen",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_sencha/ip/pinmux/data/autogen:pinmux_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "rv_plic_regs_h",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_sencha/sparrow/hw/top_sencha:rv_plic_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_sencha",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_sencha:rv_plic_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "rv_plic_smc_regs_h",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_sencha/sparrow/hw/top_sencha:rv_plic_smc_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_sencha",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_sencha:rv_plic_smc_regs",
+ ],
+ }),
+)
diff --git a/hw/top_sencha/chip_sencha_asic.core b/hw/top_sencha/chip_sencha_asic.core
new file mode 100644
index 0000000..a189f99
--- /dev/null
+++ b/hw/top_sencha/chip_sencha_asic.core
@@ -0,0 +1,86 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:chip_sencha_asic:0.1"
+description: "Sencha chip level"
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:systems:top_sencha:0.1
+ - lowrisc:systems:top_sencha_pkg
+ - lowrisc:systems:padring
+ - "fileset_partner ? (partner:systems:ast)"
+ - "fileset_partner ? (partner:systems:scan_role_pkg)"
+ - "!fileset_partner ? (google:systems:ast)"
+ - "!fileset_partner ? (lowrisc:systems:scan_role_pkg)"
+ files:
+ - rtl/autogen/chip_sencha_asic.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/chip_sencha_asic.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+ IBEX_CUSTOM_PMP_RESET_VALUES:
+ datatype: bool
+ default: true
+ paramtype: vlogdefine
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
+ toplevel: chip_sencha_asic
+ parameters:
+ - IBEX_CUSTOM_PMP_RESET_VALUES
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
+ syn:
+ <<: *default_target
+ # TODO: set default to DC once
+ # this option is available
+ # olofk/edalize#89
+ default_tool: icarus
+ parameters:
+ - SYNTHESIS=true
+ toplevel: chip_sencha_asic
+
+ formal:
+ <<: *default_target
+ toplevel: chip_sencha_asic
diff --git a/hw/top_sencha/chip_sencha_nexus.core b/hw/top_sencha/chip_sencha_nexus.core
new file mode 100644
index 0000000..fc0e7df
--- /dev/null
+++ b/hw/top_sencha/chip_sencha_nexus.core
@@ -0,0 +1,106 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:systems:chip_sencha_nexus:0.1"
+description: "Sencha toplevel for the Nexus board"
+filesets:
+ files_rtl_nexus:
+ depend:
+ - lowrisc:systems:top_sencha:0.1
+ - lowrisc:systems:top_sencha_pkg
+ - google:systems:ast
+ - lowrisc:systems:padring
+ files:
+ - rtl/clkgen_xilultrascaleplus.sv
+ - rtl/usr_access_xil7series.sv
+ - rtl/autogen/chip_sencha_nexus.sv
+ file_type: systemVerilogSource
+
+ files_constraints:
+ files:
+ - data/clocks_nexus.xdc
+ - data/pins_nexus.xdc
+ - data/placement.xdc
+ - data/synth.xdc
+ file_type: xdc
+
+ files_tcl:
+ files:
+ - util/vivado_setup_hooks.tcl: { file_type: tclSource }
+ # File copied by fusesoc into the workroot (the file containing the
+ # .eda.yml file), and referenced from vivado_setup_hooks.tcl
+ - util/vivado_hook_synth_design_pre.tcl: { file_type: user, copyto: vivado_hook_synth_design_pre.tcl }
+ - util/vivado_hook_write_bitstream_pre.tcl: { file_type: user, copyto: vivado_hook_write_bitstream_pre.tcl }
+ - util/vivado_hook_opt_design_post.tcl: { file_type: user, copyto: vivado_hook_opt_design_post.tcl }
+
+parameters:
+ # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
+ # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
+ # --BootRomInitFile=$PWD/build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexus.scr.39.vmem
+ # XXX: The VMEM file should be added to the sources of the Vivado project to
+ # make the Vivado dependency tracking work. However this requires changes to
+ # fusesoc first.
+ BootRomInitFile:
+ datatype: str
+ description: Scrambled boot ROM initialization file in 40 bit vmem hex format
+ default: "../../../../../../out/sencha/hw/rom_splices/test_rom_fpga_nexus.scr.39.vmem"
+ paramtype: vlogparam
+ OtpCtrlMemInitFile:
+ datatype: str
+ description: OTP initialization file in vmem hex format
+ default: "../../../../../../out/sencha/hw/rom_splices/otp_img_fpga_nexus.vmem"
+ paramtype: vlogparam
+ # For value definition, please see ip/prim/rtl/prim_pkg.sv
+ PRIM_DEFAULT_IMPL:
+ datatype: str
+ paramtype: vlogdefine
+ description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
+ AST_BYPASS_CLK:
+ datatype: bool
+ paramtype: vlogdefine
+ IBEX_CUSTOM_PMP_RESET_VALUES:
+ datatype: bool
+ default: true
+ paramtype: vlogdefine
+ # New parameter for ISP so the CG can be bypassed.
+ FPGA:
+ datatype: bool
+ default: true
+ paramtype: vlogdefine
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl_nexus
+ toplevel: chip_sencha_nexus
+ parameters:
+ - IBEX_CUSTOM_PMP_RESET_VALUES
+ - AST_BYPASS_CLK=true
+
+ synth:
+ default_tool: vivado
+ filesets:
+ - files_rtl_nexus
+ - files_constraints
+ - files_tcl
+ toplevel: chip_sencha_nexus
+ parameters:
+ - BootRomInitFile
+ - OtpCtrlMemInitFile
+ - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
+ - IBEX_CUSTOM_PMP_RESET_VALUES
+ - AST_BYPASS_CLK=true
+ - FPGA=true
+ tools:
+ vivado:
+ part: "xcvu13p-fhga2104-2-e" # nexus with XCVU13P-FHGA2104-2-e
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_sencha/chip_sencha_verilator.core b/hw/top_sencha/chip_sencha_verilator.core
new file mode 100644
index 0000000..af7197f
--- /dev/null
+++ b/hw/top_sencha/chip_sencha_verilator.core
@@ -0,0 +1,47 @@
+CAPI=2:
+# Copyright 2024 Google LLC.
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:chip_sencha_verilator:0.1"
+description: "Sencha top level for simulation with verilator"
+filesets:
+ files_sim_verilator:
+ depend:
+ - lowrisc:systems:top_sencha:0.1
+ - lowrisc:systems:top_sencha_pkg
+ - lowrisc:smc:smc_tracer
+ - lowrisc:ibex:ibex_tracer
+ - lowrisc:prim:clock_div
+ - google:systems:ast
+ - lowrisc:systems:scan_role_pkg
+
+ files:
+ - rtl/chip_sencha_verilator.sv: { file_type: systemVerilogSource }
+
+parameters:
+ AST_BYPASS_CLK:
+ datatype: bool
+ paramtype: vlogdefine
+ IBEX_CUSTOM_PMP_RESET_VALUES:
+ datatype: bool
+ default: true
+ paramtype: vlogdefine
+
+targets:
+ default: &default_target
+ filesets:
+ - files_sim_verilator
+ parameters:
+ - IBEX_CUSTOM_PMP_RESET_VALUES
+ - AST_BYPASS_CLK=true
+ toplevel: chip_sencha_verilator
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_sencha/data/BUILD b/hw/top_sencha/data/BUILD
new file mode 100644
index 0000000..ee7aa69
--- /dev/null
+++ b/hw/top_sencha/data/BUILD
@@ -0,0 +1,228 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+load("@lowrisc_opentitan//rules:otp.bzl", "otp_image", "otp_json", "otp_partition")
+
+package(default_visibility = ["//visibility:public"])
+
+exports_files(glob(["autogen/**"]))
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
+
+filegroup(
+ name = "all_hjson_files",
+ srcs = glob(["**/*.hjson"]),
+)
+
+# A fork from opentitan's hw/ip/otp_ctrl/data:img_rma target. However, there is
+# no otp_json_alert_digest_cfg overlay for it requires opentitantool to generate
+# the new OWNER_SW_CFG_ROM_ALERT_DIGEST_* values.
+otp_image(
+ name = "otp_img_rma",
+ src = "@lowrisc_opentitan//hw/ip/otp_ctrl/data:otp_json_rma",
+ overlays = [
+ "@lowrisc_opentitan//hw/ip/otp_ctrl/data:otp_json_creator_sw_cfg",
+ "@lowrisc_opentitan//hw/ip/otp_ctrl/data:otp_json_owner_sw_cfg",
+ "@lowrisc_opentitan//hw/ip/otp_ctrl/data:otp_json_hw_cfg",
+ ],
+)
+
+################
+
+otp_json(
+ name = "otp_json_empty",
+ partitions = [
+ otp_partition(
+ name = "SECRET0",
+ items = {
+ "TEST_UNLOCK_TOKEN": "0",
+ "TEST_EXIT_TOKEN": "0",
+ },
+ lock = False,
+ ),
+ otp_partition(
+ name = "SECRET1",
+ items = {
+ "FLASH_ADDR_KEY_SEED": "0",
+ "FLASH_DATA_KEY_SEED": "0",
+ "SRAM_DATA_KEY_SEED": "0",
+ },
+ lock = False,
+ ),
+ otp_partition(
+ name = "SECRET2",
+ items = {
+ "RMA_TOKEN": "0",
+ "CREATOR_ROOT_KEY_SHARE0": "0",
+ "CREATOR_ROOT_KEY_SHARE1": "0",
+ },
+ lock = False,
+ ),
+ otp_partition(
+ name = "LIFE_CYCLE",
+ count = 8,
+ # Should we set this to TEST_UNLOCKED0?
+ state = "TEST_UNLOCKED0",
+ ),
+ ],
+ seed = "0",
+)
+
+otp_json(
+ name = "otp_json_creator_sw_cfg",
+ partitions = [
+ otp_partition(
+ name = "CREATOR_SW_CFG",
+ items = {
+ "CREATOR_SW_CFG_DIGEST": "0x0",
+ # Use software mod_exp implementation for signature
+ # verification. See the definition of `hardened_bool_t` in
+ # sw/device/lib/base/hardened.h.
+ "CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN": "0",
+ # Mark the first three keys as valid and remaining as invalid
+ # since we currently have only three keys. See the definition of
+ # `hardened_byte_bool_t` in sw/device/lib/base/hardened.h.
+ "CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN": "0",
+ # Enable use of entropy for countermeasures. See the definition
+ # of `hardened_bool_t` in sw/device/lib/base/hardened.h.
+ "CREATOR_SW_CFG_RNG_EN": "0",
+ # ROM execution is enabled if this item is set to a non-zero
+ # value.
+ "CREATOR_SW_CFG_ROM_EXEC_EN": "0",
+ # Value to write to the cpuctrl CSR in `rom_init()`.
+ # See:
+ # https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cpu-control-register-cpuctrl
+ "CREATOR_SW_CFG_CPUCTRL": "0",
+ "CREATOR_SW_CFG_JITTER_EN": "0",
+ # Value of the min_security_version_rom_ext field of the
+ # default boot data.
+ "CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT": "0x0",
+ # Value of the min_security_version_bl0 field of the default
+ # boot data.
+ "CREATOR_SW_CFG_MIN_SEC_VER_BL0": "0x0",
+ # Enable the default boot data in PROD and PROD_END life cycle
+ # states. See the definition of `hardened_bool_t` in
+ # sw/device/lib/base/hardened.h.
+ "CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN": "0",
+ # Enable AST initialization.
+ "CREATOR_SW_CFG_AST_INIT_EN": "0",
+ # TODO: This enables a busyloop in the ROM to give time to
+ # trigger an RMA lifecycle transition via JTAG. The current
+ # value of 10 cycles is useful for test code which verifies
+ # the path through the ROM. This value is not useful for a
+ # real chip.
+ "CREATOR_SW_CFG_RMA_SPIN_EN": "0",
+ "CREATOR_SW_CFG_RMA_SPIN_CYCLES": "0",
+ # Entropy source health check default values. This needs to be
+ # populated when `CREATOR_SW_CFG_RNG_EN` is set to true.
+ "CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS": "0",
+ "CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS": "0",
+ "CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS": "0",
+ "CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS": "0",
+ "CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS": "0",
+ "CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS": "0",
+ "CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS": "0",
+ "CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS": "0",
+ "CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS": "0",
+ "CREATOR_SW_CFG_RNG_ALERT_THRESHOLD": "0",
+ "CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST": "0",
+ },
+ ),
+ ],
+)
+
+otp_json(
+ name = "otp_json_owner_sw_cfg",
+ partitions = [
+ otp_partition(
+ name = "OWNER_SW_CFG",
+ items = {
+ "OWNER_SW_CFG_DIGEST": "0x0",
+ # Enable bootstrap. See `hardened_bool_t` in
+ # sw/device/lib/base/hardened.h.
+ "OWNER_SW_CFG_ROM_BOOTSTRAP_EN": "0",
+ # Set to 0x739 to use the ROM_EXT hash measurement as the key
+ # manager attestation binding value.
+ "OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN": "0x0",
+ # Report errors without any redaction.
+ "OWNER_SW_CFG_ROM_ERROR_REPORTING": "0",
+ # Set the enables to kAlertEnableNone.
+ # See `alert_enable_t` in
+ # sw/device/silicon_creator/lib/drivers/alert.h
+ "OWNER_SW_CFG_ROM_ALERT_CLASS_EN": "0",
+ # Set the esclation policies to kAlertEscalateNone.
+ # See `alert_escalate_t` in
+ # sw/device/silicon_creator/lib/drivers/alert.h
+ "OWNER_SW_CFG_ROM_ALERT_ESCALATION": "0",
+ # Set the classifiactions to kAlertClassX.
+ # See `alert_class_t` in
+ # sw/device/silicon_creator/lib/drivers/alert.h
+ "OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION": ["0"] * 80,
+ # Set the classifiactions to kAlertClassX. See `alert_class_t` in
+ # sw/device/silicon_creator/lib/drivers/alert.h
+ "OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION": ["0"] * 16,
+ # Set the alert accumulation thresholds to 0 per class.
+ "OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH": ["0x00000000"] * 4,
+ # Set the alert timeout cycles to 0 per class.
+ "OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES": ["0x00000000"] * 4,
+ # Set the alert phase cycles to 0,10,10,0xFFFFFFFF for classes
+ # A and B, and to all zeros for classes C and D.
+ "OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES": [
+ "0x0",
+ "0",
+ "0",
+ "0",
+ "0x0",
+ "0",
+ "0",
+ "0",
+ "0x0",
+ "0x0",
+ "0x0",
+ "0x0",
+ "0x0",
+ "0x0",
+ "0x0",
+ "0x0",
+ ],
+ },
+ ),
+ ],
+)
+
+otp_json(
+ name = "otp_json_hw_cfg",
+ partitions = [
+ otp_partition(
+ name = "HW_CFG",
+ items = {
+ "DEVICE_ID": "0",
+ # Cryptolib and chip-level tests require access to the CSRNG
+ # software interfaces.
+ "EN_CSRNG_SW_APP_READ": False,
+ "EN_SRAM_IFETCH": False,
+ # Cryptolib and chip-level tests require access to the
+ # entropy_src FW data interface.
+ "EN_ENTROPY_SRC_FW_READ": False,
+ # Cryptolib and chip-level tests require access to the
+ # entropy_src FW override interface.
+ "EN_ENTROPY_SRC_FW_OVER": False,
+ },
+ lock = False,
+ ),
+ ],
+)
+
+otp_image(
+ name = "otp_img_empty",
+ src = ":otp_json_empty",
+ overlays = [
+ ":otp_json_creator_sw_cfg",
+ ":otp_json_owner_sw_cfg",
+ ":otp_json_hw_cfg",
+ ],
+)
diff --git a/hw/top_sencha/data/chip_conn_testplan.hjson b/hw/top_sencha/data/chip_conn_testplan.hjson
new file mode 100644
index 0000000..3c2db54
--- /dev/null
+++ b/hw/top_sencha/data/chip_conn_testplan.hjson
@@ -0,0 +1,1434 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+{
+ name: conn
+ testpoints: [
+
+ /////////////////////////
+ // aon_timer_rst.csv //
+ /////////////////////////
+ {
+ name: aon_timer_rst
+ desc: '''Verify rstmgr's resets_o is connected to aon_timer's reset port.'''
+ stage: V2
+ tests: ["aon_timer_rst"]
+ tags: ["conn"]
+ }
+ {
+ name: aon_timer_rst_aon
+ desc: '''Verify rstmgr's resets_o is connected to aon_timer's aon-reset port.'''
+ stage: V2
+ tests: ["aon_timer_rst_aon"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // ast_clkmgr.csv //
+ /////////////////////////
+ {
+ name: ast_clockmgr_clocks
+ desc: '''Verify the clock connectivity between AST and clock manager.
+ '''
+ stage: V2
+ tests: ["ast_clk_sys_out",
+ "ast_clk_aon_out",
+ "ast_clk_usb_out",
+ "ast_clk_io_out",
+ "ast_all_byp_ack_out",
+ "ast_io_byp_ack_out",
+ "ast_clk_adc_in",
+ "ast_clk_alert_in",
+ "ast_clk_es_in",
+ "ast_clk_rng_in",
+ "ast_clk_tlul_in",
+ "ast_clk_usb_in",
+ "ast_clk_sns_in",
+ "ast_clk_jen_in",
+ "ast_all_byp_ack_in",
+ "ast_io_byp_ack_in",
+ "ast_hispeed_sel_in"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // pwrmgr_ast.csv //
+ /////////////////////////
+ {
+ name: ast_pwrmgr_pok
+ desc: '''Verify the connectivity of power-related signals between AST and power manager.
+ '''
+ stage: V2
+ tests: ["ast_clk_sys_val_out",
+ "ast_clk_aon_val_out",
+ "ast_clk_usb_val_out",
+ "ast_clk_io_val_out",
+ "ast_main_pok_out",
+ "ast_clk_sys_en_in",
+ "ast_clk_usb_en_in",
+ "ast_clk_io_en_in"]
+ tags: ["conn"]
+ }
+ /////////////////////////
+ // rstmgr_ast.csv //
+ /////////////////////////
+ {
+ name: ast_rstmgr_resets
+ desc: '''Verify the reset connectivity between AST and reset manager.
+ '''
+ stage: V2
+ tests: ["ast_rst_adc_in",
+ "ast_rst_alert_in",
+ "ast_rst_es_in",
+ "ast_rst_rng_in",
+ "ast_rst_tlul_in",
+ "ast_rst_usb_in",
+ "ast_rst_sns_in"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // ast_infra.csv //
+ /////////////////////////
+ {
+ name: ast_pad_shorts
+ desc: '''Verify pads that are directly shorted to pads
+ '''
+ stage: V2
+ tests: ["ast_pad0",
+ "ast_pad1"]
+ tags: ["conn"]
+ }
+ {
+ name: ast_pinmux
+ desc: '''Verify AST -> pinmux connectivity
+ '''
+ stage: V2
+ tests: ["ast_pinmux"]
+ tags: ["conn"]
+ }
+ {
+ name: ast_pad_inputs
+ desc: '''Verify pad inputs that are connected to AST
+ '''
+ stage: V2
+ tests: ["pad_ast"]
+ tags: ["conn"]
+ }
+ {
+ name: ast_other_clocks
+ desc: '''Verify clock connectivity between AST and other blocks in the system,
+ excluding clkmgr connections.
+ '''
+ stage: V2
+ tests: ["ast_clk_ext_in", "ast_clk_spi_sns_in"]
+ tags: ["conn"]
+ }
+ {
+ name: ast_other_resets
+ desc: '''Verify reset connectivity between AST and other blocks in the system,
+ excluding rstmgr connections.
+ '''
+ stage: V2
+ tests: ["ast_rst_por_in"]
+ tags: ["conn"]
+ }
+ {
+ name: ast_other_pok
+ desc: '''Verify the connectivity of power-related signals between AST and other blocks in
+ the system, excluding power manager.
+ '''
+ stage: V2
+ tests: ["ast_usb_ref_in",
+ "ast_usb_ref_val_in",
+ "ast_otp_pwr_seq_in",
+ "ast_main_pd_in",
+ "ast_main_iso_en_in",
+ "ast_otp_pwr_seq_out",]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // ast_mem_cfg.csv //
+ /////////////////////////
+ {
+ name: ast_dft_ram_2p_cfg
+ desc: '''Verify ast model's dual port configuration bits are connected to the dual port RAMs
+ in the following blocks:
+ - spi_device
+ - usbdev
+ '''
+ stage: V2
+ tests: ["ast_dft_spi_device_ram_2p_cfg", "ast_dft_usbdev_ram_2p_cfg"]
+ tags: ["conn"]
+ }
+ {
+ name: ast_dft_ram_1p_cfg
+ desc: '''Verify ast model's single port configuration bits are connected to the single port
+ RAMs in the following blocks:
+ - otbn_imem
+ - otbn_dmem
+ - rv_core_ibex_tag0
+ - rv_core_ibex_tag1
+ - rv_core_ibex_data0
+ - rv_core_ibex_data1
+ - sram_main
+ - sram_retention
+ - rom
+ - smc_ram
+ - ml_dmem
+ '''
+ stage: V2
+ tests: ["ast_dft_otbn_imem_ram_1p_cfg",
+ "ast_dft_otbn_dmem_ram_1p_cfg",
+ "ast_dft_rv_core_ibex_tag0_ram_1p_cfg",
+ "ast_dft_rv_core_ibex_tag1_ram_1p_cfg",
+ "ast_dft_rv_core_ibex_data0_ram_1p_cfg",
+ "ast_dft_rv_core_ibex_data1_ram_1p_cfg",
+ "ast_dft_sram_main_ram_1p_cfg",
+ "ast_dft_sram_ret_ram_1p_cfg",
+ "ast_dft_rom_cfg",
+ "ast_dft_smc_ram_1p_cfg",
+ "ast_dft_ml_dmem_1p_cfg"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // ast_scanmode.csv //
+ /////////////////////////
+ {
+ name: scanmode_connections
+ desc: '''Verify the connectivity of scanmode to the following IPs:
+ - clkmgr
+ - flash_ctrl
+ - lc_ctrl
+ - otp_ctrl
+ - padring
+ - pinmux
+ - rstmgr
+ - rv_core_ibex
+ - rv_dm
+ - spi_device
+ - xbar_main
+ - xbar_peri
+ '''
+ stage: V2
+ tests: ["ast_scanmode_padring", "ast_scanmode_clkmgr", "ast_scanmode_flash_ctrl",
+ "ast_scanmode_lc_ctrl", "ast_scanmode_otp_ctrl", "ast_scanmode_pinmux",
+ "ast_scanmode_rstmgr", "ast_scanmode_rv_core_ibex", "ast_scanmode_rv_dm",
+ "ast_scanmode_spi_device", "ast_scanmode_xbar_main", "ast_scanmode_xbar_peri"]
+ tags: ["conn"]
+ }
+
+ //////////////////////////////
+ // otp_lc_vendor_test.csv //
+ //////////////////////////////
+ {
+ name: vendor_test_connections
+ desc: '''Verify the connectivity of vendor_test IOs between otp_ctrl and lc_ctrl.'''
+ stage: V2
+ tests: ["lc_otp_vendor_test_ctrl", "lc_otp_vendor_test_status"]
+ tags: ["conn"]
+ }
+
+
+ //////////////////////////
+ // clkmgr_cg_en.csv //
+ //////////////////////////
+ {
+ name: cg_en_io_peri
+ desc: '''Verify clkmgr's cg_en_o.io_peri is connected to alert_handler's lpg_cg_en[7].'''
+ stage: V2
+ tests: ["clkmgr_io_peri_alert_7_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_io_div2_peri
+ desc: '''Verify clkmgr's cg_en_o.io_div2_peri is connected to alert_handler's lpg_cg_en[8].'''
+ stage: V2
+ tests: ["clkmgr_io_div2_peri_alert_8_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_io_div4_infra
+ desc: '''Verify clkmgr's cg_en_o.io_div4_infra is connected to:
+ - alert_handler's lpg_cg_en_i[12]
+ - alert_handler's lpg_cg_en_i[16]
+ '''
+ stage: V2
+ tests: ["clkmgr_io_div2_infra_alert_12_cg_en",
+ "clkmgr_io_div4_infra_alert_16_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_io_div4_peri
+ desc: '''Verify clkmgr's cg_en_o.io_div4_peri is connected to the following:
+ - alert_handler's lpg_cg_en_i[4:0]
+ - alert_handler's lpg_cg_en_i[13]
+ '''
+ stage: V2
+ tests: ["clkmgr_io_div4_peri_alert_0_cg_en",
+ "clkmgr_io_div4_peri_alert_1_cg_en",
+ "clkmgr_io_div4_peri_alert_2_cg_en",
+ "clkmgr_io_div4_peri_alert_3_cg_en",
+ "clkmgr_io_div4_peri_alert_4_cg_en",
+ "clkmgr_io_div4_peri_alert_13_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_io_div4_powerup
+ desc: '''Verify clkmgr's cg_en_o.io_div4_powerup is connected to the following:
+ - alert_handler's lpg_cg_en_i[11:10]
+ - alert_handler's lpg_cg_en_i[14]
+ '''
+ stage: V2
+ tests: ["clkmgr_io_div4_powerup_alert_10_cg_en",
+ "clkmgr_io_div4_powerup_alert_11_cg_en",
+ "clkmgr_io_div4_powerup_alert_14_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_io_div4_secure
+ desc: '''Verify clkmgr's cg_en_o.io_div4_secure is connected to the following:
+ - alert_handler's lpg_cg_en_i[6]
+ - alert_handler's lpg_cg_en_i[17]
+ '''
+ stage: V2
+ tests: ["clkmgr_io_div4_secure_alert_6_cg_en",
+ "clkmgr_io_div4_secure_alert_17_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_io_div4_timers
+ desc: '''Verify clkmgr's cg_en_o.io_div4_timers is connected to the following:
+ - alert_handler's lpg_cg_en_i[5]
+ - alert_handler's lpg_cg_en_i[15]
+ '''
+ stage: V2
+ tests: ["clkmgr_io_div4_timers_alert_5_cg_en",
+ "clkmgr_io_div4_timers_alert_15_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_main_aes
+ desc: '''Verify clkmgr's cg_en_o.main_aes is connected to alert_handler's lpg_cg_en[21].'''
+ stage: V2
+ tests: ["clkmgr_main_aes_alert_21_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_main_infra
+ desc: '''Verify clkmgr's cg_en_o.main_infra is connected to alert_handler's lpg_cg_en[19:18].'''
+ stage: V2
+ tests: ["clkmgr_main_infra_alert_18_cg_en",
+ "clkmgr_main_infra_alert_19_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_main_secure
+ desc: '''Verify clkmgr's cg_en_o.main_secure is connected to alert_handler's lpg_cg_en[20].'''
+ stage: V2
+ tests: ["clkmgr_main_secure_alert_20_cg_en"]
+ tags: ["conn"]
+ }
+ {
+ name: cg_en_usb_peri
+ desc: '''Verify clkmgr's cg_en_o.usb_peri is connected to alert_handler's lpg_cg_en[9].'''
+ stage: V2
+ tests: ["clkmgr_usb_peri_alert_9_cg_en"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // clkmgr_idle.csv //
+ /////////////////////////
+ {
+ name: clkmgr_idle
+ desc: '''Verify clkmgr's `idle_i` bits are connected to the following ports:
+ - index 0 to aes's `idle_o`
+ - index 1 to hmac's `idle_o`
+ - index 2 to kmac's `idle_o`
+ - index 3 to otbn's `idle_o`
+ '''
+ stage: V2
+ tests: ["clkmgr_idle0", "clkmgr_idle1", "clkmgr_idle2", "clkmgr_idle3"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // clkmgr_infra.csv //
+ /////////////////////////
+ {
+ name: clkmgr_clk_io_div4_infra
+ desc: '''Verify clkmgr's `clk_io_div4_infra` is connected to the following block's clock
+ input:
+ - flash_ctrl clk_otp_i
+ - sram_ctrl main clk_otp_i
+ - sram_ctrl retention clk_i
+ - sram_ctrl retention clk_otp_i
+ - sysrst_ctrl clk_i
+ - xbar_main clk_fixed_i
+ - xbar_peri clk_peri_i
+ '''
+ stage: V2
+ tests: ["clkmgr_infra_clk_flash_ctrl_otp_clk",
+ "clkmgr_infra_clk_sram_ctrl_main_otp_clk",
+ "clkmgr_infra_clk_sram_ctrl_ret_clk",
+ "clkmgr_infra_clk_sram_ctrl_ret_otp_clk",
+ "clkmgr_infra_clk_sysrst_ctrl_clk",
+ "clkmgr_infra_clk_xbar_main_fixed_clk",
+ "clkmgr_infra_clk_xbar_peri_peri_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_main_infra
+ desc: '''Verify clkmgr's `clk_main_infra` is connected to the following blocks' clock input:
+ - flash_ctrl clk_i
+ - rv_dm clk_i
+ - rom_ctrl clk_i
+ - rv_core_ibex clk_i
+ - rv_core_ibex clk_edn_i
+ - sram_ctrl main clk_i
+ - xbar_main clk_main_i
+ '''
+ stage: V2
+ tests: ["clkmgr_infra_clk_flash_ctrl_clk",
+ "clkmgr_infra_clk_rv_dm_clk",
+ "clkmgr_infra_clk_rom_clk",
+ "clkmgr_infra_clk_rv_core_ibex_clk",
+ "clkmgr_infra_clk_rv_core_ibex_edn_clk",
+ "clkmgr_infra_clk_sram_ctrl_main_clk",
+ "clkmgr_infra_clk_xbar_main_main_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_aon_infra
+ desc: '''Verify clkmgr's `clk_aon_infra` is connected to the following block's clock input:
+ - sysrst_ctrl clk_aon_i
+ '''
+ stage: V2
+ tests: ["clkmgr_infra_clk_sysrst_ctrl_aon_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_io_infra
+ desc: '''Verify clkmgr's `clk_io_infra` is connected to the following block's clock input:
+ - xbar_main's clk_spi_host0_i
+ '''
+ stage: V2
+ tests: ["clkmgr_infra_clk_xbar_main_spi_host0_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_io_div2_infra
+ desc: '''Verify clkmgr's `clk_io_div2_infra` is connected to the following block's clock
+ input:
+ - xbar_main clk_spi_host1_i
+ '''
+ stage: V2
+ tests: ["clkmgr_infra_clk_xbar_main_spi_host1_clk"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // clkmgr_peri.csv //
+ /////////////////////////
+ {
+ name: clkmgr_clk_io_div4_peri
+ desc: '''Verify clkmgr's `clk_io_div4_peri` is connected to the following blocks' clock
+ input:
+ - adc_ctrl clk_i
+ - gpio clk_i
+ - spi_device clk_i
+ - i2c0 clk_i
+ - i2c1 clk_i
+ - i2c2 clk_i
+ - pattgen clk_i
+ - uart0 clk_i
+ - uart1 clk_i
+ - uart2 clk_i
+ - uart3 clk_i
+ '''
+ stage: V2
+ tests: ["clkmgr_peri_clk_adc_ctrl_aon_clk",
+ "clkmgr_peri_clk_gpio_clk",
+ "clkmgr_peri_clk_spi_device_clk",
+ "clkmgr_peri_clk_i2c0_clk",
+ "clkmgr_peri_clk_i2c1_clk",
+ "clkmgr_peri_clk_i2c2_clk",
+ "clkmgr_peri_clk_pattgen_clk",
+ "clkmgr_peri_clk_uart0_clk",
+ "clkmgr_peri_clk_uart1_clk",
+ "clkmgr_peri_clk_uart2_clk",
+ "clkmgr_peri_clk_uart3_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_io_div2_peri
+ desc: '''Verify clkmgr's `clk_io_div2_peri` is connected to the following blocks' clock
+ input:
+ - spi_device's scan_clk_i
+ - spi_host1 clk_i
+ '''
+ stage: V2
+ tests: ["clkmgr_peri_clk_spi_device_scan_clk",
+ "clkmgr_peri_clk_spi_host1_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_io_peri
+ desc: '''Verify clkmgr's `clk_io_peri` is connected to the following block's clock input:
+ - spi_host0's clk_i
+ '''
+ stage: V2
+ tests: ["clkmgr_peri_clk_spi_host0_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_usb_peri
+ desc: '''Verify clkmgr's `clk_usb_peri` is connected to the following:
+ - usbdev's clk_i
+ '''
+ stage: V2
+ tests: ["clkmgr_peri_clk_usbdev_usb_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_aon_peri
+ desc: '''Verify clkmgr's `clk_aon_peri` is connected to the following blocks' clock input:
+ - usbdev clk_aon_i
+ '''
+ stage: V2
+ tests: ["clkmgr_peri_clk_usbdev_aon_clk"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // clkmgr powerup //
+ /////////////////////////
+ {
+ name: clkmgr_clk_io_div4_powerup
+ desc: '''Verify clkmgr's `clk_io_div4_powerup` is connected to the following blocks' clock
+ input:
+ - clkmgr clk_i
+ - pinmux clk_i
+ - pwm clk_i
+ - pwrmgr clk_i
+ - rstmgr clk_i
+ - rstmgr clk_io_div4_i
+ '''
+ stage: V2
+ tests: ["clkmgr_powerup_clk_clkmgr_clk",
+ "clkmgr_powerup_clk_pinmux_clk",
+ "clkmgr_powerup_clk_pwm_clk",
+ "clkmgr_powerup_clk_pwrmgr_clk",
+ "clkmgr_powerup_clk_pwrmgr_lc_clk",
+ "clkmgr_powerup_clk_rstmgr_por_clk",
+ "clkmgr_powerup_clk_rstmgr_io4_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_aon_powerup
+ desc: '''Verify clkmgr's `clk_aon_powerup` is connected to the following blocks' clock input:
+ - pinmux's clk_aon_i
+ - pwm clk_core_i
+ - pwrmgr clk_slow_i
+ - rstmgr clk_aon_i
+ '''
+ stage: V2
+ tests: ["clkmgr_powerup_clk_pinmux_aon_clk",
+ "clkmgr_powerup_clk_pwm_core_clk",
+ "clkmgr_powerup_clk_pwrmgr_slow_clk",
+ "clkmgr_powerup_clk_rstmgr_aon_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_main_powerup
+ desc: '''Verify clkmgr's `clk_main_powerup` is connected to the following block's clock
+ input:
+ - rstmgr's clk_main_i
+ '''
+ stage: V2
+ tests: ["clkmgr_powerup_clk_rstmgr_main_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_io_powerup
+ desc: '''Verify clkmgr's `clk_io_powerup` is connected to rstmgr's io clock.'''
+ stage: V2
+ tests: ["clkmgr_powerup_clk_rstmgr_io_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_usb_powerup
+ desc: '''Verify clkmgr's `clk_usb_powerup` is connected to rstmgr's usb clock.'''
+ stage: V2
+ tests: ["clkmgr_powerup_clk_rstmgr_usb_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_io_div2_powerup
+ desc: '''Verify clkmgr's `clk_io_div2_powerup` is connected to rstmgr's io_div2 clock.'''
+ stage: V2
+ tests: ["clkmgr_powerup_clk_rstmgr_io2_clk"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // clkmgr_secure.csv //
+ /////////////////////////
+ {
+ name: clkmgr_clk_io_div4_secure
+ desc: '''Verify clkmgr's `clk_io_div4_secure` is connected to the following blocks' clock
+ input:
+ - alert_handler clk_i
+ - lc_ctrl clk_i
+ - otbn clk_otp_i
+ - otp_ctrl clk_i
+ - pwrmgr clk_lc_i
+ - rv_core_ibex clk_esc_i
+ - rv_core_ibex clk_otp_i
+ - sensor_ctrl clk_i
+ '''
+ stage: V2
+ tests: ["clkmgr_secure_clk_alert_handler_clk",
+ "clkmgr_secure_clk_lc_ctrl_clk",
+ "clkmgr_secure_clk_otbn_otp_clk",
+ "clkmgr_secure_clk_otp_ctrl_clk",
+ "clkmgr_secure_clk_rv_core_ibex_clk",
+ "clkmgr_secure_clk_rv_core_ibex_otp_clk",
+ "clkmgr_secure_clk_sensor_ctrl_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_main_secure
+ desc: '''Verify clkmgr's `clk_main_secure` is connected to the following blocks' clock input:
+ - alert_handler's clk_edn_i
+ - csrgn clk_i
+ - edn0 clk_i
+ - edn1 clk_i
+ - entropy_src clk_i
+ - keymgr clk_i
+ - keymgr clk_edn_i
+ - lc_ctrl clk_kmac_i
+ - otbn clk_edn_i
+ - otp_ctrl clk_edn_i
+ - rv_plic clk_i
+ '''
+ stage: V2
+ tests: ["clkmgr_secure_clk_alert_handler_edn_clk",
+ "clkmgr_secure_clk_csrng_clk",
+ "clkmgr_secure_clk_edn0_clk",
+ "clkmgr_secure_clk_edn1_clk",
+ "clkmgr_secure_clk_entropy_src_clk",
+ "clkmgr_secure_clk_keymgr_clk",
+ "clkmgr_secure_clk_keymgr_edn_clk",
+ "clkmgr_secure_clk_lc_ctrl_kmac_clk",
+ "clkmgr_secure_clk_otbn_edn_clk",
+ "clkmgr_secure_clk_otp_ctrl_edn_clk",
+ "clkmgr_secure_clk_rv_plic_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_aon_secure
+ desc: '''Verify clkmgr's `clk_aon_secure` is connected to the following blocks' clock input:
+ - sensor_ctrl clk_aon_i
+ '''
+ stage: V2
+ tests: ["clkmgr_secure_clk_sensor_ctrl_aon_clk"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // clkmgr_timers.csv //
+ /////////////////////////
+ {
+ name: clkmgr_clk_io_div4_timers
+ desc: '''Verify clkmgr's `clk_io_div4_timers` is connected to the following blocks' clock
+ input:
+ - aon_timer clk_i
+ - rv_timer clk_i
+ '''
+ stage: V2
+ tests: ["clkmgr_timers_clk_aon_timer_clk", "clkmgr_timers_clk_rv_timer_clk"]
+ tags: ["conn"]
+ }
+ {
+ name: clkmgr_clk_aon_timers
+ desc: '''Verify clkmgr's `clk_aon_timers` is connected to aon_timer's aon clock.'''
+ stage: V2
+ tests: ["clkmgr_timers_clk_aon_timer_aon_clk"]
+ tags: ["conn"]
+ }
+
+ //////////////////////
+ // clkmgr_trans.csv //
+ //////////////////////
+ {
+ name: clk_main_aes
+ desc: '''Verify clkmgr's clk_main_aes is connected to the following block's clocks:
+ - aes clk_i
+ - aes clk_edn_i
+ '''
+ stage: V2
+ tests: ["clkmgr_trans_aes", "clkmgr_trans_aes_edn"]
+ tags: ["conn"]
+ }
+ {
+ name: clk_main_hmac
+ desc: '''Verify clkmgr's clk_main_hmac is connected to hmac's clk_i.'''
+ stage: V2
+ tests: ["clkmgr_trans_hmac"]
+ tags: ["conn"]
+ }
+ {
+ name: clk_main_kmac
+ desc: '''Verify clkmgr's clk_main_kmac is connected to kmac's clk_i and clk_edn_i.'''
+ stage: V2
+ tests: ["clkmgr_trans_kmac", "clkmgr_trans_kmac_edn"]
+ tags: ["conn"]
+ }
+ {
+ name: clk_main_otbn
+ desc: '''Verify clkmgr's clk_main_otbn is connected to otbn's clk_i.'''
+ stage: V2
+ tests: ["clkmgr_trans_otbn"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // ast_flash.csv //
+ /////////////////////////
+ {
+ name: ast_flash_ctrl
+ desc: '''Verify ast's flash signals are connected to the flash controller.'''
+ stage: V2
+ tests: ["ast_flash_obs_ctrl",
+ "ast_flash_pwr_dwn_out",
+ "ast_flash_pwr_rdy_out",
+ "ast_flash_bist_en_out"]
+ tags: ["conn"]
+ }
+ /////////////////////////////
+ // ast_entropy_src_cfg.csv //
+ /////////////////////////////
+ {
+ name: chip_sw_entropy_src_ast_fips
+ desc: '''
+ Verify the connectivity of rng_fips_o feedback signal to RNG.
+ '''
+ stage: V2
+ tests: ["ast_entropy_src_rng_val",
+ "ast_entropy_src_rng_b",
+ "ast_entropy_src_rng_fips",
+ "ast_entropy_src_rng_en"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // jtag.csv //
+ /////////////////////////
+ {
+ name: flash_jtag
+ desc: "Verify jtag interface is connected to flash_phy_req interface."
+ stage: V2
+ tests: ["pinmux_flash_ctrl_tck", "pinmux_flash_ctrl_tms", "pinmux_flash_ctrl_tdi",
+ "pinmux_flash_ctrl_tdo", "pinmux_flash_ctrl_tdo_en"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_jtag_trst
+ desc: "Verify jtag rst pin is connected to lc_ctrl interface."
+ stage: V2
+ tests: ["pinmux_lc_ctrl_jtag_req", "pinmux_lc_ctrl_jtag_rsp"]
+ tags: ["conn"]
+ }
+
+ //////////////////////////
+ // lc_ctrl_broadcast.sv //
+ //////////////////////////
+ {
+ name: lc_escalate_en
+ desc: '''Verify lc_ctrl's `lc_escalate_en_o` is connected to the following blocks'
+ `lc_escalate_en_i`:
+ - otp_ctrl
+ - aon_timer
+ - sram_ctrl main
+ - sram_ctrl retention
+ - flash_ctrl
+ - aes
+ - kmac
+ - otbn
+ '''
+ stage: V2
+ tests: ["lc_escalate_en_otp",
+ "lc_escalate_en_aon_timer",
+ "lc_escalate_en_sram_main",
+ "lc_escalate_en_sram_ret",
+ "lc_escalate_en_flash",
+ "lc_escalate_en_aes",
+ "lc_escalate_en_kmac",
+ "lc_escalate_en_otbn"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_keymgr_en
+ desc: "Verify that lc_ctrl's keymanager enable signal and diversification value are correctly connected to the keymgr."
+ stage: V2
+ tests: ["lc_keymgr_en_keymgr",
+ "lc_keymgr_div_keymgr"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_nvm_debug_en
+ desc: "Verify lc_ctrl's lc_nvm_debug_en is connected correctly to flash_ctrl."
+ stage: V2
+ tests: ["lc_nvm_debug_en_flash_ctrl"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_cpu_en
+ desc: "Verify that the lc_ctrl's lc_cpu_en_o signal is correctly connected to rv_core_ibex."
+ stage: V2
+ tests: ["lc_cpu_en_rv_core_ibex"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_hw_debug_en
+ desc: "Verify that lc_ctrl's lc_hw_debug_en_o signal is correctly connected to IPs."
+ stage: V2
+ tests: ["lc_hw_debug_en_pwrmgr",
+ "lc_hw_debug_en_clkmgr",
+ "lc_hw_debug_en_pinmux",
+ "lc_hw_debug_en_sram_ctrl_main",
+ "lc_hw_debug_en_rv_dm",
+ "lc_hw_debug_en_csrng"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_hw_dft_en
+ desc: "Verify that lc_ctrl's lc_dft_en_o signal is correctly connected to IPs."
+ stage: V2
+ tests: ["lc_dft_en_otp",
+ "lc_dft_en_pwrmgr",
+ "lc_dft_en_pinmux",
+ "lc_dft_en_ast"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_flash_otbn_rma
+ desc: "Verify lc_ctrl's RMA request connections."
+ stage: V2
+ tests: ["lc_rma_seed_flash_ctrl",
+ "lc_rma_req_flash_ctrl",
+ "flash_ctrl_rma_ack_otbn",
+ "otbn_rma_ack_lc"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_clk_byp
+ desc: "Verify lc_ctrl's clock bypass request connections."
+ stage: V2
+ tests: ["lc_clk_byp_req_clkmgr",
+ "clkmgr_clk_byp_ack_lc"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_otp_check_byp
+ desc: "Verify lc_ctrl's check bypass signal is correctly connected to OTP (used when programming a life cycle transition)."
+ stage: V2
+ tests: ["lc_check_byp_en_otp"]
+ tags: ["conn"]
+ }
+ {
+ name: lc_access_control
+ desc: "Verify lc_ctrl's access control modulation signals are correctly connected to flash and OTP."
+ stage: V2
+ tests: ["lc_creator_seed_sw_rw_en_otp",
+ "lc_seed_hw_rd_en_otp",
+ "lc_creator_seed_sw_rw_en_flash",
+ "lc_seed_hw_rd_en_flash",
+ "lc_owner_seed_sw_rw_en_flash",
+ "lc_iso_part_sw_rd_en_flash",
+ "lc_iso_part_sw_wr_en_flash"]
+ tags: ["conn"]
+ }
+ /////////////////////////
+ // pwrmgr_rstmgr.sv //
+ /////////////////////////
+ {
+ name: pwrmgr_rst_lc_req
+ desc: '''Verify pwrmgr's `rst_lc_req` is connected to rstmgr's `rst_lc_req`.'''
+ stage: V2
+ tests: ["pwrmgr_rst_lc_req"]
+ tags: ["conn"]
+ }
+ {
+ name: pwrmgr_rst_sys_req
+ desc: '''Verify pwrmgr's `rst_sys_req` is connected to rstmgr's `rst_sys_req`.'''
+ stage: V2
+ tests: ["pwrmgr_rst_sys_req"]
+ tags: ["conn"]
+ }
+ {
+ name: rstmgr_rst_lc_src_n
+ desc: '''Verify rstmgr's `rst_lc_src_n` is connected to pwrmgr's `rst_lc_src_n`.'''
+ stage: V2
+ tests: ["rstmgr_rst_lc_src_n"]
+ tags: ["conn"]
+ }
+ {
+ name: rstmgr_rst_sys_src_n
+ desc: '''Verify rstmgr's `rst_sys_src_n` is connected to rstmgr's `rst_sys_src_n`.'''
+ stage: V2
+ tests: ["rstmgr_rst_sys_src_n"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // rstmgr_resets_o.csv //
+ /////////////////////////
+ {
+ name: rst_i2c0_n_d0
+ desc: '''Verify rstmgr's rst_i2c0_n[1] is connected to i2c0's rst_ni.'''
+ stage: V2
+ tests: ["rstmgr_i2c0_d0_i2c0_rst_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_i2c1_n_d0
+ desc: '''Verify rstmgr's rst_i2c1_n[1] is connected to i2c1's rst_ni.'''
+ stage: V2
+ tests: ["rstmgr_i2c0_d0_i2c1_rst_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_i2c2_n_d0
+ desc: '''Verify rstmgr's rst_i2c2_n[1] is connected to i2c2's rst_ni.'''
+ stage: V2
+ tests: ["rstmgr_i2c2_d0_i2c2_rst_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_lc_aon_aon
+ desc: '''Verify rstmgr's rst_lc_aon_n[0] is connected to the following:
+ - aon_timer's rst_aon_ni
+ - clkmgr's rst_aon_ni
+ - pinmux's rst_aon_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_lc_aon_aon_aon_timer_rst_aon_ni",
+ "rstmgr_lc_aon_aon_clkmgr_rst_aon_ni",
+ "rstmgr_lc_aon_aon_pinmux_rst_aon_ni"]
+ tags: ["conn"]
+ }
+
+ {
+ name: rst_lc_io_div2_n_aon
+ desc: '''Verify rstmgr's rst_i2c2_n[1] is connected to clkmgr's rst_io_div2_ni.'''
+ stage: V2
+ tests: ["rstmgr_lc_io_div2_aon_clkmgr_rst_io_div2_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_lc_io_div4_aon
+ desc: '''Verify rstmgr's rst_lc_io_div4_n[0] is connected to the following:
+ - aon_timer's rst_ni
+ - clkmgr's rst_ni
+ - clkmgr's rst_io_div4_ni
+ - pinmux's rst_ni
+ - sram_ctrl_ret's rst_otp_ni
+ - rstmgr's rst_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_lc_io_div4_aon_aon_timer_rst_ni",
+ "rstmgr_lc_io_div4_aon_clkmgr_rst_ni",
+ "rstmgr_lc_io_div4_aon_clkmgr_rst_io_div4_ni",
+ "rstmgr_lc_io_div4_aon_pwrmgr_rst_lc_ni",
+ "rstmgr_lc_io_div4_aon_pinmux_rst_ni",
+ "rstmgr_lc_io_div4_aon_sram_ctrl_ret_rst_otp_ni",
+ "rstmgr_lc_io_div4_aon_rstmgr_rst_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_lc_io_div4_d0
+ desc: '''Verify rstmgr's rst_lc_io_div4_n[1] is connected to the following:
+ - alert_handler's rst_ni
+ - lc_ctrl's rst_ni
+ - otbn's rst_otp_ni
+ - otp_ctrl's rst_ni
+ - pwrmgr's rst_lc_ni
+ - rv_core_ibex's rst_esc_ni
+ - rv_core_ibex's rst_otp_ni
+ - sram_ctrl_main's rst_otp_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_lc_io_div4_d0_alert_handler_rst_ni",
+ "rstmgr_lc_io_div4_d0_lc_ctrl_rst_ni",
+ "rstmgr_lc_io_div4_d0_otbn_rst_otp_ni",
+ "rstmgr_lc_io_div4_d0_otp_ctrl_rst_ni",
+ "rstmgr_lc_io_div4_d0_rv_core_ibex_rst_esc_ni",
+ "rstmgr_lc_io_div4_d0_rv_core_ibex_rst_otp_ni",
+ "rstmgr_lc_io_div4_d0_sram_ctrl_main_rst_otp_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_lc_io_div4_shadowed_aon
+ desc: '''Verify rstmgr's rst_lc_io_div4_shadowed_n[0] is connected to clkmgr's rst_shadowed_ni.'''
+ stage: V2
+ tests: ["rstmgr_lc_io_div4_shadowed_aon_clkmgr_rst_shadowed_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_lc_io_div4_shadowed_d0
+ desc: '''Verify rstmgr's rst_lc_io_div4_shadowed_n[1] is connected to alert_handler's rst_shadowed_ni.'''
+ stage: V2
+ tests: ["rstmgr_lc_io_div4_shadowed_d0_alert_handler_rst_shadowed_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_lc_aon
+ desc: '''Verify rstmgr's rst_lc_n[0] is connected to clkmgr's rst_main_ni.'''
+ stage: V2
+ tests: ["rstmgr_lc_aon_clkmgr_rst_main_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_lc_io_aon
+ desc: '''Verify rstmgr's rst_lc_io_n[0] is connected to clkmgr's rst_io_ni.'''
+ stage: V2
+ tests: ["rstmgr_lc_io_aon_clkmgr_rst_io_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_lc_usb_aon
+ desc: '''Verify rstmgr's rst_lc_usb_n[0] is connected to clkmgr's rst_usb_ni.'''
+ stage: V2
+ tests: ["rstmgr_lc_usb_aon_clkmgr_rst_usb_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_por_aon_aon
+ desc: '''Verify rstmgr's rst_por_aon_n[0] is connected to pwrmgr's rst_slow_ni.'''
+ stage: V2
+ tests: ["rstmgr_por_aon_aon_pwrmgr_rst_slow_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_por_aon_d0
+ desc: '''Verify rstmgr's rst_por_aon_n[1] is connected to pwrmgr's rst_main_ni.'''
+ stage: V2
+ tests: ["rstmgr_por_aon_d0_pwrmgr_rst_main_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_por_aon
+ desc: '''Verify rstmgr's rst_por_n[0] is connected to clkmgr's rst_root_main_ni.'''
+ stage: V2
+ tests: ["rstmgr_por_aon_clkmgr_rst_root_main_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_por_io_aon
+ desc: '''Verify rstmgr's rst_por_io_n[0] is connected to clkmgr's rst_root_io_ni.'''
+ stage: V2
+ tests: ["rstmgr_por_io_aon_clkmgr_rst_root_io_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_por_io_div2_aon
+ desc: '''Verify rstmgr's rst_por_io_div2_n[0] is connected to clkmgr's rst_root_io_div2_ni.'''
+ stage: V2
+ tests: ["rstmgr_por_io_div2_aon_clkmgr_rst_root_io_div2_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_por_io_div4_aon
+ desc: '''Verify rstmgr's rst_por_io_div4_n[0] is connected to the following:
+ - clkmgr's rst_root_io_div4_ni
+ - clkmgr's rst_root_ni
+ - pwrmgr's rst_ni
+ - rstmgr's rst_por_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_por_io_div4_aon_clkmgr_rst_root_io_div4_ni",
+ "rstmgr_por_io_div4_aon_clkmgr_rst_root_ni",
+ "rstmgr_por_io_div4_aon_pwrmgr_rst_ni",
+ "rstmgr_por_io_div4_aon_rstmgr_rst_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_por_usb_aon
+ desc: '''Verify rstmgr's rst_por_usb_n[0] is connected to clkmgr's rst_root_usb_ni.'''
+ stage: V2
+ tests: ["rstmgr_por_usb_aon_clkmgr_rst_root_usb_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_spi_device_d0
+ desc: '''Verify rstmgr's rst_spi_device_n[1] is connected to spi_device's rst_ni.'''
+ stage: V2
+ tests: ["rstmgr_spi_device_d0_spi_device_rst_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_spi_host0_d0
+ desc: '''Verify rstmgr's rst_spi_host0_n[1] is connected to spi_host0's rst_ni.'''
+ stage: V2
+ tests: ["rstmgr_spi_host0_d0_spi_host0_rst_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_spi_host1_d0
+ desc: '''Verify rstmgr's rst_spi_host1_n[1] is connected to spi_host1's rst_ni.'''
+ stage: V2
+ tests: ["rstmgr_spi_host1_d0_spi_host1_rst_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_sys_aon_aon
+ desc: '''Verify rstmgr's rst_sys_aon_n[0] is connected to the following:
+ - adc_ctrl's rst_aon_ni
+ - pwm's rst_core_ni
+ - sensor_ctrl's rst_aon_ni
+ - sysrst_ctrl's rst_aon_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_sys_aon_aon_adc_ctrl_rst_aon_ni",
+ "rstmgr_sys_aon_aon_pwm_rst_aon_ni",
+ "rstmgr_sys_aon_aon_sensor_ctrl_rst_aon_ni",
+ "rstmgr_sys_aon_aon_sysrst_ctrl_rst_aon_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_sys_io_d0
+ desc: '''Verify rstmgr's rst_sys_io_n[1] is connected to xbar_main's rst_spi_host0_ni.'''
+ stage: V2
+ tests: ["rstmgr_sys_io_d0_xbar_main_rst_spi_host0_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_sys_io_div2_d0
+ desc: '''Verify rstmgr's rst_sys_io_div2_n[1] is connected to xbar_main's rst_spi_host1_ni.'''
+ stage: V2
+ tests: ["rstmgr_sys_io_div2_d0_xbar_main_rst_spi_host1_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_sys_io_div4_aon
+ desc: '''Verify rstmgr's rst_sys_io_div4_n[0] is connected to the following:
+ - adc_ctrl's rst_ni
+ - pwm's rst_ni
+ - sensor_ctrl's rst_ni
+ - sram_ctrl_ret's rst_ni
+ - sysrst_ctrl's rst_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_sys_io_div4_aon_adc_ctrl_rst_ni",
+ "rstmgr_sys_io_div4_aon_pwm_rst_ni",
+ "rstmgr_sys_io_div4_aon_sensor_ctrl_rst_ni",
+ "rstmgr_sys_io_div4_aon_sram_ctrl_ret_rst_ni",
+ "rstmgr_sys_io_div4_aon_sysrst_ctrl_rst_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_sys_io_div4_d0
+ desc: '''Verify rstmgr's rst_sys_io_div4_n[1] is connected to the following:
+ - flash_ctrl's rst_otp_ni
+ - gpio's rst_ni
+ - pattgen's rst_ni
+ - rv_timer's rst_ni
+ - uart0's rst_ni
+ - uart1's rst_ni
+ - uart2's rst_ni
+ - uart3's rst_ni
+ - xbar_main's rst_fixed_ni
+ - xbar_peri's rst_peri_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_sys_io_div4_d0_flash_ctrl_rst_otp_ni",
+ "rstmgr_sys_io_div4_d0_gpio_rst_ni",
+ "rstmgr_sys_io_div4_d0_pattgen_rst_ni",
+ "rstmgr_sys_io_div4_d0_rv_timer_rst_ni",
+ "rstmgr_sys_io_div4_d0_uart0_rst_ni",
+ "rstmgr_sys_io_div4_d0_uart1_rst_ni",
+ "rstmgr_sys_io_div4_d0_uart2_rst_ni",
+ "rstmgr_sys_io_div4_d0_uart3_rst_ni",
+ "rstmgr_sys_io_div4_d0_xbar_main_rst_fixed_ni",
+ "rstmgr_sys_io_div4_d0_xbar_peri_rst_peri_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_sys_d0
+ desc: '''Verify rstmgr's rst_sys_n[1] is connected to the following:
+ - aes's rst_edn_ni
+ - aes's rst_ni
+ - alert_handler's rst_edn_ni
+ - csrng's rst_ni
+ - edn0's rst_ni
+ - edn1's rst_ni
+ - entropy_src's rst_ni
+ - flash_ctrl's rst_ni
+ - hmac's rst_ni
+ - keymgr's rst_edn_ni
+ - keymgr's rst_ni
+ - kmac's rst_edn_ni
+ - kmac's rst_ni
+ - otbn's rst_edn_ni
+ - otbn's rst_ni
+ - lc_ctrl's rst_kmac_ni
+ - otp_ctrl's rst_edn_ni
+ - rv_core_ibex's rst_edn_ni
+ - rv_core_ibex's rst_ni
+ - rv_plic's rst_ni
+ - sram_ctrl_main's rst_ni
+ - xbar_main's rst_main_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_sys_d0_aes_rst_edn_ni",
+ "rstmgr_sys_d0_aes_rst_ni",
+ "rstmgr_sys_d0_alert_handler_rst_edn_ni",
+ "rstmgr_sys_d0_csrng_rst_ni",
+ "rstmgr_sys_d0_edn0_rst_ni",
+ "rstmgr_sys_d0_edn1_rst_ni",
+ "rstmgr_sys_d0_entropy_src_rst_ni",
+ "rstmgr_sys_d0_flash_ctrl_rst_ni",
+ "rstmgr_sys_d0_hmac_rst_ni",
+ "rstmgr_sys_d0_keymgr_rst_edn_ni",
+ "rstmgr_sys_d0_keymgr_rst_ni",
+ "rstmgr_sys_d0_kmac_rst_edn_ni",
+ "rstmgr_sys_d0_kmac_rst_ni",
+ "rstmgr_sys_d0_otbn_rst_edn_ni",
+ "rstmgr_sys_d0_otbn_rst_ni",
+ "rstmgr_sys_d0_lc_ctrl_rst_kmac_ni",
+ "rstmgr_sys_d0_otp_ctrl_rst_edn_ni",
+ "rstmgr_sys_d0_rv_core_ibex_rst_edn_ni",
+ "rstmgr_sys_d0_rv_core_ibex_rst_ni",
+ "rstmgr_sys_d0_rv_plic_rst_ni",
+ "rstmgr_sys_d0_sram_ctrl_main_rst_ni",
+ "rstmgr_sys_d0_xbar_main_rst_main_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_sys_shadowed_d0
+ desc: '''Verify rstmgr's rst_sys_shadowed_n[1] is connected to the following:
+ - aes's rst_shadowed_ni
+ - flash_ctrl's rst_shadowed_ni
+ - keymgr's rst_shadowed_ni
+ - kmac's rst_shadowed_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_sys_shadowed_d0_aes_rst_shadowed_ni",
+ "rstmgr_sys_shadowed_d0_flash_ctrl_rst_shadowed_ni",
+ "rstmgr_sys_shadowed_d0_keymgr_rst_shadowed_ni",
+ "rstmgr_sys_shadowed_d0_kmac_rst_shadowed_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_sys_usb_d0
+ desc: '''Verify rstmgr's rst_sys_usb_n[1] is connected to xbar_main's rst_usb_ni.'''
+ stage: V2
+ tests: ["rstmgr_sys_usb_d0_xbar_main_rst_usb_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_usb_aon_d0
+ desc: '''Verify rstmgr's rst_usb_aon_n[1] is connected to usbdev's rst_aon_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_usb_aon_d0_usbdev_rst_aon_ni"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_usb_d0
+ desc: '''Verify rstmgr's rst_usb_n[1] is connected to the following:
+ - usbdev's rst_ni
+ '''
+ stage: V2
+ tests: ["rstmgr_usb_d0_usbdev_rst_ni"]
+ tags: ["conn"]
+ }
+ ///////////////////////
+ // rstmgr_rst_en.csv //
+ ///////////////////////
+ {
+ name: rst_en_i2c0_d0
+ desc: '''Verify rstmgr's rst_en_o.i2c0[1] connects to alert_handler's lpg_rst_en[2].'''
+ stage: V2
+ tests: ["rstmgr_i2c0_d0_alert_2_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_i2c1_d0
+ desc: '''Verify rstmgr's rst_en_o.i2c1[1] connects to alert_handler's lpg_rst_en[3].'''
+ stage: V2
+ tests: ["rstmgr_i2c1_d0_alert_3_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_i2c2_d0
+ desc: '''Verify rstmgr's rst_en_o.i2c2[1] connects to alert_handler's lpg_rst_en[4].'''
+ stage: V2
+ tests: ["rstmgr_i2c2_d0_alert_4_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_lc_d0
+ desc: '''Verify rstmgr's rst_en_o.lc[1] connects to alert_handler's lpg_rst_en[19].'''
+ stage: V2
+ tests: ["rstmgr_lc_d0_alert_19_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_lc_io_div4_aon
+ desc: '''Verify rstmgr's rst_en_o.lc_io_div4[0] connects to the following:
+ - alert_handler's lpg_rst_en[11]
+ - alert_handler's lpg_rst_en[15]
+ '''
+ stage: V2
+ tests: ["rstmgr_lc_io_div4_aon_alert_11_rst_en",
+ "rstmgr_lc_io_div4_aon_alert_15_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_lc_io_div4_d0
+ desc: '''Verify rstmgr's rst_en_o.lc_io_div4[1] connects to alert_handler's lpg_rst_en[6].'''
+ stage: V2
+ tests: ["rstmgr_lc_io_div4_d0_alert_6_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_por_io_div4_d0
+ desc: '''Verify rstmgr's rst_en_o.por_io_div4[1] connects to alert_handler's lpg_rst_en[10].'''
+ stage: V2
+ tests: ["rstmgr_por_io_div4_d0_alert_10_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_spi_host0_d0
+ desc: '''Verify rstmgr's rst_en_o.spi_host0[1] connects to alert_handler's lpg_rst_en[7].'''
+ stage: V2
+ tests: ["rstmgr_spi_host0_d0_alert_7_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_spi_host1_d0
+ desc: '''Verify rstmgr's rst_en_o.spi_host1[1] connects to alert_handler's lpg_rst_en[8].'''
+ stage: V2
+ tests: ["rstmgr_spi_host1_d0_alert_8_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_spi_device_d0
+ desc: '''Verify rstmgr's rst_en_o.spi_device[1] connects to alert_handler's lpg_rst_en[1].'''
+ stage: V2
+ tests: ["rstmgr_spi_device_d0_alert_1_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_sys_d0
+ desc: '''Verify rstmgr's rst_en_o.sys[1] connects to the following:
+ - alert_handler's lpg_rst_en[18]
+ - alert_handler's lpg_rst_en[20]
+ - alert_handler's lpg_rst_en[21]
+ '''
+ stage: V2
+ tests: ["rstmgr_sys_d0_alert_18_rst_en",
+ "rstmgr_sys_d0_alert_20_rst_en",
+ "rstmgr_sys_d0_alert_21_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_sys_io_div4_aon
+ desc: '''Verify rstmgr's rst_en_o.sys_io_div4[0] connects to the following:
+ - alert_handler's lpg_rst_en[12]
+ - alert_handler's lpg_rst_en[13]
+ - alert_handler's lpg_rst_en[14]
+ - alert_handler's lpg_rst_en[17]
+ '''
+ stage: V2
+ tests: ["rstmgr_sys_io_div4_aon_alert_12_rst_en",
+ "rstmgr_sys_io_div4_aon_alert_13_rst_en",
+ "rstmgr_sys_io_div4_aon_alert_14_rst_en",
+ "rstmgr_sys_io_div4_aon_alert_17_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_sys_io_div4_d0
+ desc: '''Verify rstmgr's rst_en_o.sys_io_div4[1] connects to the following:
+ - alert_handler's lpg_rst_en[0]
+ - alert_handler's lpg_rst_en[5]
+ - alert_handler's lpg_rst_en[16]
+ '''
+ stage: V2
+ tests: ["rstmgr_sys_io_div4_d0_alert_0_rst_en",
+ "rstmgr_sys_io_div4_d0_alert_5_rst_en",
+ "rstmgr_sys_io_div4_d0_alert_16_rst_en"]
+ tags: ["conn"]
+ }
+ {
+ name: rst_en_usb_d0
+ desc: '''Verify rstmgr's rst_en_o.usb[1] connects to alert_handler's lpg_rst_en[9].'''
+ stage: V2
+ tests: ["rstmgr_usb_d0_alert_9_rst_en"]
+ tags: ["conn"]
+ }
+
+ //////////////////////////
+ // rstmgr_crashdump.csv //
+ //////////////////////////
+ {
+ name: rstmgr_crashdump
+ desc: '''Verify that the Ibex and alert_handler crashdump outputs are correctly connected to the rstmgr.'''
+ stage: V2
+ tests: ["alert_handler_rstmgr_crashdump",
+ "rv_core_ibex_rstmgr_crashdump"]
+ tags: ["conn"]
+ }
+
+ /////////////////////////
+ // analog_sigs.csv //
+ /////////////////////////
+ {
+ name: otp_ctrl_external_voltage
+ desc: "Verify the connectivity between the external voltage pad and otp_ctrl."
+ stage: V2
+ tests: ["otp_ext_volt"]
+ tags: ["conn"]
+ }
+ {
+ name: flash_ctrl_test_voltage
+ desc: "Verify the connectivity between the test voltage pad and flash_ctrl."
+ stage: V2
+ tests: ["flash_test_volt"]
+ tags: ["conn"]
+ }
+ {
+ name: flash_ctrl_test_mode
+ desc: "Verify the connectivity between the test mode pads and flash_ctrl."
+ stage: V2
+ tests: ["flash_test_mode0",
+ "flash_test_mode1"]
+ tags: ["conn"]
+ }
+ {
+ name: ast_adc
+ desc: "Verify the connectivity between the CC pads and the ast ADC input."
+ stage: V2
+ tests: ["ast_cc1",
+ "ast_cc2"]
+ tags: ["conn"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/data/chip_testplan.hjson b/hw/top_sencha/data/chip_testplan.hjson
new file mode 100644
index 0000000..e4c7bb6
--- /dev/null
+++ b/hw/top_sencha/data/chip_testplan.hjson
@@ -0,0 +1,4065 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+{
+ name: "chip"
+
+ // TODO: remove the common testplans if not applicable
+ import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
+ // TODO #5484, comment these 2 lines out because spi host memory is dummy
+ // "hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
+ // Integrity error is tested in a SW test.
+ "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+ "hw/ip/tlul/data/tlul_testplan.hjson",
+ // TODO: Will enable the rom-e2e test after rebase to opentitan TOT
+ "hw/top_sencha/data/chip_conn_testplan.hjson"]
+
+ testpoints: [
+ ///////////////////////////////////////////////////////////////////////////
+ // IO Peripherals //
+ // UART, GPIO, I2C, SPIDEV, SPIHOST, USB, PINMUX & PADCTRL, PATTGEN, PWM //
+ ///////////////////////////////////////////////////////////////////////////
+
+ // UART (pre-verified IP) integration tests:
+ {
+ name: chip_sw_uart_tx_rx
+ desc: '''Verify transmission of data over the TX and RX port.
+
+ SW test sends a known payload over the TX port. The testbench, at the same time
+ sends a known payload over RX. On reception, both payloads are checked for integrity.
+ SW validates the reception of TX watermark, RX watermark, and the TX empty interrupts.
+ Choosing the max supported baud rate for the UART is sufficient.
+
+ Verify each UART instance at the chip level independently. Verify there is no aliasing
+ on all UART ports across the instances, including SMC_UART.
+ '''
+ stage: V1
+ tests: ["chip_sw_uart_tx_rx"]
+ tags: ["gls"]
+ }
+ {
+ name: chip_sw_uart_rx_overflow
+ desc: '''Verify the RX overflow interrupt.
+
+ The testbench sends a random payload of size greater than the RX fifo size (32). The SW
+ ignores the received the data to allow the RX overflow interrupt to assert.
+
+ Verify each UART instance at the chip level independently. Verify there is no aliasing
+ on all UART ports across the instances, including SMC_UART.
+ '''
+ stage: V1
+ tests: ["chip_sw_uart_tx_rx", "chip_sw_uart_tx_rx_idx1", "chip_sw_uart_tx_rx_idx2",
+ "chip_sw_uart_tx_rx_idx3"]
+ }
+ {
+ name: chip_sw_uart_rand_baudrate
+ desc: '''Verify UART transmission of data at various speeds.
+
+ Randomly pick one of the UART instances and configure it to run with any of these baud
+ rates - 9600bps, 115200bps, 230400bps, 128Kbps, 256Kbps, 1Mkbps, 1.5Mkbps.
+
+ '''
+ stage: V1
+ tests: ["chip_sw_uart_rand_baudrate"]
+ }
+ {
+ name: chip_sw_uart_tx_rx_alt_clk_freq
+ desc: '''Verify the transmission of UART via using external clock as uart core clock.
+
+ Extend from chip_sw_uart_rand_baudrate with following added settings.
+ - Configure LC to RMA state, so that it allows clkmgr to use external clock.
+ - Configure clkmgr to select external clock.
+ - Randomize `HI_SPEED_SEL`, so that uart core clock frequency can be either
+ ext_clk_freq / 4 or ext_clk_freq / 2.
+ '''
+ stage: V1
+ tests: ["chip_sw_uart_tx_rx_alt_clk_freq", "chip_sw_uart_tx_rx_alt_clk_freq_low_speed"]
+ }
+
+ // GPIO (pre-verified IP) integration tests:
+ {
+ name: chip_sw_gpio_out
+ desc: '''Verify GPIO outputs.
+
+ SW test configures the GPIOs to be in the output mode. The test walks a 1 through the
+ pins. The testbench checks the value for correctness and verifies that there is no
+ aliasing between the pins.
+ '''
+ stage: V1
+ tests: ["chip_sw_gpio"]
+ }
+ {
+ name: chip_sw_gpio_in
+ desc: '''Verify GPIO inputs.
+
+ The SW test configures the GPIOs to be in input mode. The testbench walks a 1 through
+ the pins. SW test ensures that the GPIO values read from the CSR is correct.
+ '''
+ stage: V1
+ tests: ["chip_sw_gpio"]
+ }
+ {
+ name: chip_sw_gpio_irq
+ desc: '''Verify GPIO interrupts.
+
+ The SW test configures the GPIOs to be in input mode and enables all of them to generate
+ an interrupt. The testbench walks a 1 through the pins. SW test ensures that the
+ interrupt corresponding to the right pin is seen.
+ '''
+ stage: V1
+ tests: ["chip_sw_gpio"]
+ }
+ {
+ name: chip_sw_crt_test
+ desc: '''Verify C runtime functionality.
+
+ - The SW test setup data in .bss and .data region.
+ - The SW test verify both CRT clear and copy functions.
+ '''
+ stage: V1
+ tests: ["chip_sw_crt_test"]
+ }
+
+ // SPI_DEVICE (pre-verified IP) integration tests:
+ {
+ name: chip_sw_spi_device_tx_rx
+ desc: '''Verify the transmission of data on the chip's SPI device port in firmware mode with
+ single mode.
+
+ - The testbench sends a known payload over the chip's SPI device input port.
+ - The SW test, at the same time sends a known payload out over the chip's SPI device
+ output port.
+ - On reception, both payloads are checked for integrity.
+ - SW validates the reception of RX fifo full, RX fifo over level, TX fifo under level,
+ RX overflow and TX underflow interrupts.
+ - Run with min (6MHz), typical (30-48Mhz) and max(48MHz) SPI clk frequencies.
+ should use
+ - Also, ensure that the spi_device does not receive transactions when the csb is high.
+ - TODO, consider to test this mode with a real use case. The actual use case of this
+ mdoe is not clear right now.
+ '''
+ stage: V2
+ tests: ["chip_sw_spi_device_tx_rx"]
+ }
+ {
+ name: chip_sw_spi_device_flash_mode
+ desc: '''Verify the SPI device in flash mode.
+
+ - SW puts the SPI device in flash mode
+ - Load a firmware image (bootstrap) through flash commands to the spi_device memory.
+ - SW verifies the integrity of the image upon reception by reading the spi_device
+ memory.
+ - Ensure the image is executed correctly
+ '''
+ stage: V2
+ tests: ["chip_sw_uart_tx_rx_bootstrap"]
+ }
+ {
+ name: chip_sw_spi_device_pass_through
+ desc: '''Verify the pass through mode from an end-to-end perspective.
+
+ - Configure the SPI device and host in pass through mode.
+ - Program the cmd_filter_* CSRs to filter out random commands.
+ - Configure and enable both spi_host0 and spi_host1
+ - Send a random flash commands over the SPI device interface (chip IOs) from the
+ testbench.
+ - Verify the flash commands which pass through spi_host0, are received on chip IOs.
+ - Verify that only the payloads that are not filtered show up on the SPI host interface
+ at chip IOs.
+ - Verify spi_host1 doesn't send out any data from spi_device
+ - Run with min (6MHz), typical (24Mhz) and max (30MHz) SPI clk frequencies.
+ - Run with single, dual and quad SPI modes.
+ - Testbench should test the following commands:
+ - Read Normal, Fast Read, Fast Dual, Fast Quad, Chip Erase, Program
+ '''
+ stage: V2
+ tests: ["chip_sw_spi_device_pass_through"]
+ }
+
+ {
+ name: chip_sw_spi_device_pass_through_flash_model
+ desc: '''Verify the command filtering mechanism in passthrough mode.
+
+ - Extend the chip_spi_device_pass_through test.
+ - Connect with a real flash model on spi_host
+ - Verify that the flash commands are received and interpreted correctly in the flash
+ model
+ '''
+ stage: V3
+ tests: []
+ }
+
+ {
+ name: chip_sw_spi_device_pass_through_collision
+ desc: '''Verify the collisions on driving spi_host is handled properly
+
+ - Enable upload related interrupts and configure the spi_device in passthrough mode.
+ - Configure a command slot to enable upload for a flash program/erase command.
+ - Excecute two parallel threads:
+ 1. SPI host agent.
+ - Send this command via an upstream SPI host agent, then the agent keeps sending
+ read_status to poll the busy bit.
+ - When the busy bit is low, issue a read command to read data from the downstream
+ SPI port, and check data correctness.
+ 2. A SW process.
+ - SW receives an upload interrupt and reads the command in the upload fifo to check.
+ - SW configures the SPI host that shows the same downstream port, to send the
+ uploaded command to the downstream SPI port.
+ - SW clears busy bit to allow the upstream SPI host to proceed to the next command.
+ '''
+ stage: V2
+ tests: ["chip_sw_spi_device_pass_through_collision"]
+ }
+ {
+ name: chip_sw_spi_device_tpm
+ desc: '''Verify the basic operation of the spi tpm mode..
+
+ - The testbench sends a known payload over the chip's SPI device tpm input port.
+ - The testbench sends a read command.
+ - The software test should playback the data received in the write command as the read
+ response.
+ - The testbench should check if the written and read data match.
+ '''
+ stage: V2
+ tests: ["chip_sw_spi_device_tpm"]
+ }
+
+ // SPI_HOST (pre-verified IP) integration tests:
+ {
+ name: chip_sw_spi_host_tx_rx
+ desc: '''Verify the transmission of data on the chip's SPI host port.
+
+ - Program the SPI host to send a known payload out of the chip on the SPI host ports.
+ - The testbench receives the payload and plays it back to the SPI host interface.
+ - The SW verifies the sent payload matches the read response and services SPI event
+ interrupts.
+ - Run with min and max SPI clk frequencies and with single, dual and quad SPI modes.
+
+ Verify all SPI host instances in the chip.
+ '''
+ stage: V2
+ tests: ["chip_sw_spi_host_tx_rx"]
+ }
+
+ // I2C (pre-verified IP) integration tests:
+ {
+ name: chip_sw_i2c_host_tx_rx
+ desc: '''Verify the transmission of data over the chip's I2C host interface.
+
+ - Program the I2C to be in host mode.
+ - The SW test writes a known payload over the chip's I2C host interface, which is
+ received by the testbench.
+ - The testbench then loops this data back to the chip's I2C host and exercises the
+ read interface.
+ - SW validates the reception of FMT watermark and trans complete interrupts.
+ - SW validates that the data read matches the original data written.
+ - Verify the virtual / true open drain capability.
+
+ Verify all instances of I2C in the chip.
+ '''
+ stage: V2
+ tests: ["chip_sw_i2c_host_tx_rx",
+ "chip_sw_i2c_host_tx_rx_idx1",
+ "chip_sw_i2c_host_tx_rx_idx2"]
+ }
+ {
+ name: chip_sw_i2c_device_tx_rx
+ desc: '''Verify the transmission of data over the chip's I2C device interface.
+
+ - Program the I2C to be in device mode.
+ - The testbench writes a known payload over the chip's I2C device interface, which is
+ received and verified by the SW test for correctness.
+ - The testbench reads and verifies a known payload over the chip's I2C device interface,
+ - SW validates the reception of tx empty and trans complete interrupts.
+ - Verify the virtual / true open drain capability.
+
+ Verify all instances of I2C in the chip.
+ '''
+ stage: V2
+ tests: ["chip_sw_i2c_device_tx_rx"]
+ }
+ {
+ name: chip_sw_cam_i2c_host_tx_rx
+ desc: '''Verify the transmission of data over the chip's CAM_I2C host interface.
+
+ - Program the CAM_I2C to be in host mode.
+ - The SW test writes a known payload over the chip's CAM_I2C host interface, which is
+ received and verified by the testbench for correctness.
+ - SW validates the reception of interrupts for "FMT watermark" and "trans complete".
+ - Verify the virtual / true open drain capability.
+ Verify CAM_I2C in the chip.
+ '''
+ stage: V2
+ // TBD if it can be combined with chip_sw_i2c_host_tx_rx
+ tests: []
+ }
+
+ // I2S integration tests:
+ {
+ name: chip_sw_i2s_tx_rx
+ desc: '''Verify the transmission of data over the chip's I2S interface.
+
+ - Setup I2S tx rx IRQs in plic.
+ - Create a workload and send it over I2S.
+ - Check the interrupt is received.
+ - Check the transaction is finished and the fifo is empty.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_i2s_rx_test",
+ "chip_sw_smc_i2s_tx_test"]
+ }
+
+ // USB (pre-verified IP) integration tests:
+ {
+ name: chip_sw_usb_fs_tx_rx
+ desc: '''Verify the transmission of single-ended data over the USB at full speed. As a part of
+ this test, the enablement of USB pullup is also expected to be verified.
+
+ - Set `tx_differential_mode` to single-ended and `rx_differential_mode` to
+ differential. The other modes are not supported in OpenTitan.
+ - configure Link state to `Active`.
+ - Send and receive packets to fill the entire buffer. Ensure all the packets are
+ correct.
+ - Check interrupts (connected, pkt_received, pkt_sent, av_empty, rx_full) are triggered
+ correcly.
+ '''
+ stage: V3
+ tests: []
+ }
+ {
+ name: chip_sw_usb_vbus
+ desc: '''Verify that the USB device can detect the presence of VBUS from the USB host.
+
+ - This test extends from `chip_usb_fs_df_tx_rx`, add below at the end of the sequence.
+ - VBUS is controlled by SW, through programming CSRs (`override_pwr_sense_en` and
+ `override_pwr_sense_val`) to connect / disconnect the USB.
+ - Disconnect the USB to trigger `disconnected` interrupt.
+ - Then reconnect it and check the `connected` interrupt.
+ - Re-enable data transfer and ensure data correctness.
+ - Observe valid reference pulse usb_ref_val/pulse_o.
+ '''
+ stage: V3
+ tests: []
+ }
+ {
+ name: chip_sw_usb_suspend
+ desc: '''Verify that the USB device can detect the presence of VBUS from the USB host.
+
+ - This test extends from `chip_usb_fs_df_tx_rx`, add below at the end of the sequence.
+ - Configure USB device to enter `Suspend` state and ensure `link_suspend` interrupt is
+ triggered.
+ - Test these 2 power modes.
+ - Normal sleep:
+ - Configure pwrmgr to enter normal sleep mode, then clocks are disable while powers
+ are kept on.
+ - Resume the device through pinmux and check the `link_resume` interrupt.
+ - Ensure that previously enumerated information is kept.
+ - Deep sleep:
+ - Before entering deep sleep, store previously enumerated information in retention
+ RAM. (optional)
+ - Configure pwrmgr to enter deep sleep mode, and powers are turned off.
+ - Resume the device through pinmux and check the `link_resume` interrupt.
+ - Ensure that previously enumerated information and configuration (non-default
+ values) are wiped, as USB has been reset before wakeup.
+ - Restore previously enumerated information (if it's stored) or re-enumerate the
+ USB.
+ - Re-enable data transfer and ensure data correctness.
+ '''
+ stage: V3
+ tests: []
+ }
+ {
+ name: chip_usb_sof
+ desc: '''Verify that USB can detect SOF and respond with `usb_ref_pulse_o` and
+ `usb_ref_val_o`.
+
+ - Configure to enable `usb_ref_disable`.
+ - Send a frame with the same frame number as the USB device to trigger `frame`
+ interrupt.
+ - Ensure `usb_ref_pulse_o` and `usb_ref_val_o` behave correctly.
+ - Stop sending any frame and check the `host_lost` interrupt. Ensure `use_ref_*` behave
+ correctly.
+ '''
+ stage: V3
+ tests: []
+ }
+ {
+ name: chip_usb_wake_debug
+ desc: '''Verify that `usb_state_debug_i` can be read from the CSR
+
+ - Drive random value on `usb_state_debug_i`.
+ - Ensure the CSR `wake_debug` returns correctly value.
+ '''
+ stage: V3
+ tests: []
+ }
+ {
+ name: chip_usb_enumeration
+ desc: '''Verify USB enumeration. Details are not clear.
+
+ - TODO
+ '''
+ stage: V3
+ tests: []
+ }
+
+ // PINMUX & PADRING (pre-verified IP) integration tests:
+ {
+ name: chip_pin_mux
+ desc: '''Verify the MIO muxing at input and output sides.
+
+ - Enable `stub_cpu` mode.
+ - Add a forcing interface to pinmux's pad-facing DIO and MIO ports, including the output
+ enables; and a sampling interface for the peripheral facing DIO and MIO ports.
+ - Similarly, add a driving / sampling interface for all DIOs and MIOs at the chip pads.
+ - In the output direction:
+ - Program all MIO outsel and pad attribute registers to random values.
+ - Force the pad-facing pinmux MIO ports and output enables to random values.
+ - Verify all MIO pad values for correctness.
+ - For the input direction:
+ - Program all MIO insel and pad attribute registers to random values.
+ - Drive the MIO pads to random values.
+ - Probe and sample the peripheral facing MIO ports of the pinmux and verify the values
+ for correctness.
+ - Follow a similar testing procedure for DIOs.
+ '''
+ stage: V2
+ tests: ["chip_padctrl_attributes"]
+ }
+ {
+ name: chip_padctrl_attributes
+ desc: '''Verify pad attribute settings for all MIO and DIO pads.
+
+ - Follow the same procedure as the `chip_pin_mux` test, ensuring the padctrl attribute
+ registers for all MIOs and DIOs are also randomized when verifying the outcomes.
+ - Verify weak pull enable, output inversion and virtual open drain and drive strength
+ (bit 0) signaling in the output direction.
+ - Verify weak pull enable and input inversion in the input direction.
+ - Verify multiple pad attributes for each pad set at the same time through
+ randomization.
+
+ Cross-references the `chip_pin_mux` test.
+ '''
+ stage: V2
+ tests: ["chip_padctrl_attributes"]
+ }
+ {
+ name: chip_sw_sleep_pin_mio_dio_val
+ desc: '''Verify the MIO output values in any sleep states.
+
+ - Pick between normal sleep and deep sleep randomly
+ - Pick between tie-0, tie-1, or High-Z randomly for all muxed,
+ dedicated outputs coming from non-AON IPs.
+
+ SW programs the MIO OUTSEL CSRs to ensure that in sleep it randomly picks
+ between tie-0, tie-1 or hi-Z for all muxed outputs coming from non-AON IPs. If an AON
+ peripheral output is muxed, then that peripheral's output is selected to ensure in deep
+ sleep the peripheral can continue its signaling even in deep sleep. The testbench
+ verifies the correctness of the reflected values once the chip goes into deep sleep.
+ This is replicated for DIO pins as well.
+
+ In this test, passthrough feature is not tested. The feature is
+ covered in other tests such as chip_sw_sleep_pwm_pulses.
+ '''
+ stage: V2
+ tests: ["chip_sw_sleep_pin_mio_dio_val"]
+ }
+ {
+ name: chip_sw_sleep_pin_wake
+ desc: '''Verify pin wake up from any sleep states.
+
+ Verify one of the 8 possible MIO or DIO pad inputs (randomly configured) can cause the
+ chip to wake up from sleep state. Verifying wake on posedge is sufficient for the chip
+ level integration testing. Upon wake up, SW reads the wake cause CSR to verify
+ correctness.
+
+ For V3, enhance this test to configure all wakeup detectors rather than configure only
+ one, then have the host randomly pick one of the IOs configured for wakeup in one of
+ those detectors. Also, randomize and test all wakeup modes and enable debounce filter.
+ '''
+ stage: V2
+ tests: ["chip_sw_sleep_pin_wake"]
+ }
+ {
+ name: chip_sw_sleep_pin_retention
+ desc: '''Verify the retention logic in pinmux that is activated during deep sleep.
+
+ - Pick a pin (such as GPIO0) and enable it in output mode. Set a known value to it (0 or
+ 1) and verify the correctless of the value on the chip IO..
+ - Program the pin's retention value during deep sleep to be opposite of the active power
+ value programmed in the previous step.
+ - Reuse an existing deep sleep / low power wake up test, such as
+ `chip_sw_sleep_pin_wake` test to enter low power.
+ - Once the chip enters the deep sleep state, verify that this pin holds the correct
+ retention value throughout the low power state.
+ - Wake up the chip from sleep using the chosen method.
+ - Verify the pin value at the chip IOs is no longer holding the retention value once the
+ chip is back in active power.
+ '''
+ stage: V2
+ tests: ["chip_sw_sleep_pin_retention"]
+ }
+ {
+ name: chip_sw_tap_strap_sampling
+ desc: '''Verify tap accesses in different LC states.
+
+ Verify pinmux can select the life_cycle, RISC-V, and DFT taps after reset.
+ Verify that in TEST_UNLOCKED* and RMA states, pinmux can switch between the three TAPs
+ without issuing reset.
+ Verify in PROD state, only the LC tap can be selected.
+ Verify in DEV state, only the LC tap and RISC-V taps can be selected.
+ Verify DFT test mode straps are sampled and output to AST via
+ top_sencha.dft_strap_test_o in TEST_UNLOCKED* and RMA states.
+ Verify top_sencha.dft_strap_test_o is always 0 in the states other than TEST_UNLOCKED*
+ and RMA, regardless of the value on DFT SW straps.
+ Verify loss of DFT functionality when DFT straps are deasserted on the next POR cycle.
+
+ Note: these tests require the ROM init stage to complete. So a test ROM image is loaded,
+ but the software does not test anything. The CPU boots and runs to completion while the
+ host (SV testbench) performs these stimulus / checks.
+ '''
+ stage: V2
+ tests: ["chip_tap_straps_dev", "chip_tap_straps_prod", "chip_tap_straps_rma"]
+ }
+
+ // PATTGEN (pre-verified IP) integration tests:
+ {
+ name: chip_sw_pattgen_ios
+ desc: '''Verify pattern generation to chip output pads.
+
+ - Program the pattgen to generate a known pattern in each lane.
+ - Program the pinmux to route the chosen output to the chip IOs.
+ - Verify that the correct pattern is seen on the IOs by hooking up the pattgen monitor.
+ - Validate the reception of the done interrupt.
+ - Verify both pattgen channels independently.
+ '''
+ stage: V2
+ tests: ["chip_sw_pattgen_ios"]
+ }
+
+ // PWM (pre-verified IP) integration tests:
+ {
+ name: chip_sw_sleep_pwm_pulses
+ desc: '''Verify PWM signaling to chip output pads during deep sleep.
+
+ - Program each PWM output to pulse in a known pattern.
+ - Program the pinmux to route the chosen PWM output to the chip IOs.
+ - Program the pwrmgr to go to deep sleep state, with AON timer wakeup.
+ - Initiate the sleep state by issuing a WFI.
+ - Verify that in the sleep state, the PWM signals are active and pulsing correctly, by
+ hooking up the PWM monitor.
+ - Repeat the steps for all 6 PWM signals.
+ '''
+ stage: V2
+ tests: ["chip_sw_sleep_pwm_pulses"]
+ }
+
+ //////////////////////////////////////////////////////////////////////////////////////
+ // System Peripherals //
+ // XBAR, RV_DM, RV_TIMER, AON_TIMER, SC_PLIC, CLK/RST/PWR MGR, ALERT_HANDLER, //
+ // LC_CTRL, ADC_CTRL, SYSRST_CTRL, SMC_CTRL, CAM_CTRL, SMC_PLIC, MAILBOX //
+ //////////////////////////////////////////////////////////////////////////////////////
+
+ // XBAR (pre-verified IP) tests:
+ {
+ name: chip_sw_data_integrity
+ desc: '''
+ Verify the alert signaling mechanism due to integrity violations of load ops.
+
+ An SW test which performs the following on main and retention SRAMs to verify the memory
+ end-to-end integrity scheme:
+ - Corrupt a random data / integrity bit in the memory using SV force.
+ - SW reads that address and the corrupted data is sent to ibex.
+ - Verify that ibex detects the integrity violation and triggers an alert.
+ - Check the alert up to the NMI phase and make sure that the alert cause is from Ibex.
+ '''
+ stage: V2
+ tests: ["chip_sw_data_integrity_escalation"]
+ }
+ {
+ name: chip_sw_instruction_integrity
+ desc: '''
+ Verify the alert signaling mechanism due to integrity violations of instruction fetches.
+
+ An SW test which performs the following on main SRAM to verify the memory end-to-end
+ integrity scheme:
+ - Corrupt a data / integrity bit in a test function in the main SRAM using SV force.
+ - SW jumps to that test function in the main SRAM.
+ - Verify that ibex detects the integrity violation and triggers an alert.
+ - Check the alert up to the NMI phase and make sure that the alert cause is from Ibex.
+ '''
+ stage: V2
+ tests: ["chip_sw_data_integrity_escalation"]
+ }
+
+ // RV_DM (JTAG) tests:
+ {
+ name: chip_jtag_csr_rw
+ desc: '''
+ Verify accessibility of all the CSRs in the chip over JTAG.
+
+ - Shuffle the list of CSRs first to remove the effect of ordering.
+ - Write all CSRs via JTAG interface with a random value.
+ - Shuffle the list of CSRs yet again.
+ - Read all CSRs back and check their values for correctness while adhering to the CSR's
+ access policies.
+ - Accesses to CSRs external to `rv_dm` go through RV_DM SBA interface into the `xbar`.
+ - TO-DO: Enhance Opentitan csr_rw test to include new blocks in SMC and ML subsystem.
+ fork it to our own top_sencha/sw/device/tests/.
+ '''
+ stage: V2
+ tests: ["chip_jtag_csr_rw"]
+ }
+ {
+ name: chip_jtag_mem_access
+ desc: '''
+ Verify accessibility of all the memories in the chip over JTAG.
+
+ This test will target the following memories in the chip:
+ sram_main, sram_ret, otbn i|dmem, ROM, SMC_RAM, ML_RAM
+
+ - Shuffle the list of memories first to remove the effect of ordering.
+ - Write a location in a randomly chosen set of addresses within each memory via JTAG
+ interface with random values.
+ - For read-only memories, preload the memory with random data via backdoor.
+ - Shuffle the list of memories again.
+ - Read the previously written addresses in the memories back again and check the read
+ value for correctness. Pick some random addresses to verify in case of read-only
+ memories.
+ - TO-DO: enhance opentitan mem_access test to include smc_ram and ml_ram.
+ '''
+ stage: V2
+ tests: ["chip_jtag_mem_access"]
+ }
+ {
+ name: chip_rv_dm_perform_debug
+ desc: '''
+ - X-ref'ed with rom_e2e_jtag_inject from rom testplan.
+ - X-ref'ed with chip_sw_flash_lc_iso_part_sw_wr_en.
+ - X-ref'ed with manuf_cp_device_info_flash_wr from manufacturing testplan.
+ - Using the sram injection mechanism from rom_e2e_jtag_inject, load a SRAM program that
+ writes to isolated flash partition while the device is in TEST_UNLOCKED state.
+ - After writing, verify that the test program cannot read back the written value.
+
+ '''
+ stage: V3
+ tests: ["rom_e2e_jtag_debug_test_unlocked0", "rom_e2e_jtag_debug_dev",
+ "rom_e2e_jtag_debug_rma"]
+ }
+ {
+ name: chip_rv_dm_ndm_reset_req
+ desc: '''Verify non-debug reset request initiated from RV_DM when the chip is awake.
+
+ - Program some CSRs / mem that are under life cycle reset tree and system reset tree.
+ - Configure RV_DM to send NDM reset request to reset sytem reset tree.
+ - While NDM reset is ongoing, ensure the RV_DM debug module registers can still be
+ accessed.
+ - Read the programmed CSRs / mem to ensure that everything under system reset tree is
+ reset to the original values, while values under life cycle reset will be preserved.
+ - Read CSRs / mem in the debug domain to ensure that the values survive the reset.
+ '''
+ stage: V2
+ tests: ["chip_rv_dm_ndm_reset_req"]
+ }
+ {
+ name: chip_sw_rv_dm_ndm_reset_req_when_cpu_halted
+ desc: '''Verify non-debug reset request initiated from RV_DM when the CPU is in halted state.
+
+ - Initialize the DUT in a HW-debug enabled life cycle state.
+ - Activate the RISCV debug module.
+ - Run some SW test on the CPU.
+ - Initiate a CPU halt request via JTAG.
+ - Wait for the CPU to be in halted state via JTAG by polling dmstatus.anyhalted.
+ - Deassert the CPU haltreq and verify that we are still in halted state.
+ - (Optional) Using the abstract command, read the dcsr register to verify the cause
+ reflects the debug halt request.
+ - Issue an NDM reset request. All non-debug parts of the chip should reset. Read the
+ dmstatus.anyhalted / dvstatus.allhalted and verify that they are cleared.
+ - Verify that the debug logic is fully accessible during this time, while the NDM reset
+ is being processed and the chip is rebooted, by continuously accessing the DMI
+ register space in `rv_dm` over JTAG.
+ - De-assert the NDM reset request and wait for the CPU to reboot and finish the post-NDM
+ reset phase of the test.
+ - TODO: enhance the test to cover the second CPU (SMC) in the debug chain.
+ '''
+ stage: V2
+ tests: ["chip_sw_rv_dm_ndm_reset_req_when_cpu_halted"]
+ }
+ {
+ name: chip_rv_dm_access_after_wakeup
+ desc: '''Verify RV_DM works after wakes up from sleep.
+
+ - Put the chip into sleep mode and then wake up (both deep sleep and normal sleep).
+ - If waking up from normal sleep, an activation should not be required for RV_DM CSR
+ accesses to work.
+ - If waking up from deep sleep, an activation is required for RV_DM CSR accesses to work.
+ '''
+ stage: V2
+ tests: ["chip_sw_rv_dm_access_after_wakeup"]
+ }
+ {
+ name: chip_sw_rv_dm_access_after_hw_reset
+ desc: '''Verify RV_DM works after a watchdog or escalated reset.
+
+ - Access some RV_DM CSRs both before and after resets.
+ - An activation would be required, and the tap strap would also be sampled again.
+ '''
+ stage: V3
+ tests: ["chip_sw_rv_dm_access_after_escalation_reset"]
+ }
+ {
+ name: chip_sw_rv_dm_jtag_tap_sel
+ desc: '''Verify ability to select all available TAPs.
+
+ - Put life cycle on Test or RMA state, so that TAPs can be selected between life cycle
+ RV_DM and DFT.
+ - Verify the TAP is selected correctly.
+ - X-ref'ed with chip_sw_tap_strap_sampling.
+ '''
+ stage: V2
+ tests: ["chip_tap_straps_rma"]
+ }
+ {
+ name: chip_rv_dm_lc_disabled
+ desc: '''Verify that the debug capabilities are disabled in certain life cycle stages.
+
+ - Put life cycle in a random life cycle state.
+ - Verify that the rv_dm bus device is inaccessible from the CPU as well as external
+ JTAG if the life cycle state is not in TEST_UNLOCKED*, DEV or RMA.
+ - The bus access check is performed by randomly reading or writing a CSR inside the
+ RV_DM and checking whether the TL-UL bus errors out.
+ - The JTAG access check is performed by writing and then reading a register that is
+ accessible via the TAP/DMI inside the RV_DM. If the JTAG wires are gated, it is
+ expected that the RV_DM returns all-zero instead of the written value.
+ - X-ref'ed with `chip_tap_strap_sampling`
+ '''
+ stage: V2
+ tests: ["chip_rv_dm_lc_disabled"]
+ }
+
+ // RV_TIMER (pre-verified IP) integration tests:
+ {
+ name: chip_sw_timer
+ desc: '''Verify the timeout interrupt assertion.
+
+ - Configure the RV_TIMER to generate interrupt after a set timeout.
+ - Issue a WFI to wait for the interrupt to trigger.
+ - Service the interrupt when it triggers; verify that it came from rv_timer.
+ - Verify that the interrupt triggered only after the timeout elapsed.
+ '''
+ stage: V2
+ tests: ["chip_sw_rv_timer_irq"]
+ }
+ {
+ name: chip_sw_smc_env_test
+ desc: '''Verify the timeout interrupt assertion.
+
+ - Bring up both secure core and SMC core.
+ - Verify SMC could be terminated by writing the status register.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_env_test"]
+ }
+ {
+ name: chip_sw_smc_timer
+ desc: '''Verify the timeout interrupt assertion.
+
+ - Configure the SMC_TIMER to generate interrupt after a set timeout.
+ - Issue a WFI to wait for the interrupt to trigger.
+ - Service the interrupt when it triggers; verify that it came from smc_timer.
+ - Verify that the interrupt triggered only after the timeout elapsed.
+ - TO-DO: tests to be added, and should run from SMC core.
+ '''
+ stage: V2
+ tests: []
+ }
+ // AON_TIMER (pre-verified IP) integration tests:
+ {
+ name: chip_sw_aon_timer_wakeup_irq
+ desc: '''Verify the AON timer wake up interrupt in normal operating state.
+
+ - Program the PLIC to let the AON timer wake up interrupt the CPU.
+ - Program the AON timer to generate the wake up timeout interrupt after some time.
+ - Issue a WFI to wait for the interrupt to trigger.
+ - Service the interrupt when it triggers; verify that it came from AON timer.
+ - Verify that the interrupt triggered only after the timeout elapsed.
+ '''
+ stage: V2
+ tests: ["chip_sw_aon_timer_irq"]
+ }
+ {
+ name: chip_sw_aon_timer_sleep_wakeup
+ desc: '''Verify that AON timer can wake up the chip from a deep sleep state.
+
+ - Read the reset cause register in rstmgr to confirm that the SW is in the POR reset
+ phase.
+ - Program the pwrmgr to go to deep sleep state (clocks off, power off).
+ - Program the AON timer to wake up the chip in a reasonable amount of time.
+ - Have the CPU issue WFI to signal the pwrmgr to go into sleep state.
+ - Verify via assertion checks, the wake up request occurs after the timeout has elapsed.
+ - After reset followed by AON timer wake up, read the reset cause register to confirm
+ the AON timer wake up phase.
+ - After the test sequence is complete, read the wake up threshold register - it should
+ not be reset.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_smoketest"]
+ }
+ {
+ name: chip_sw_aon_timer_wdog_bark_irq
+ desc: '''Verify the watchdog bark reception in normal state.
+
+ - Program the PLIC to let the wdog bark signal interrupt the CPU.
+ - Program the AON timer wdog to 'bark' after some time and enable the bark interrupt.
+ - Service the bark interrupt upon reception.
+ '''
+ stage: V2
+ tests: ["chip_sw_aon_timer_irq"]
+ }
+ {
+ name: chip_sw_aon_timer_wdog_lc_escalate
+ desc: '''Verify that the LC escalation signal disables the AON timer wdog.
+
+ - Program the AON timer wdog to 'bark' after some time and enable the bark interrupt.
+ - Start the escalation process and fail the test in the interrupt handler in case the
+ bark interrupt is fired.
+ - Program the alert handler to escalate on alerts upto phase 2 (i.e. reset) but the
+ phase 1 (i.e. wipe secrets) should occur and last during the time the wdog is
+ programed to bark and bite.
+ - Trigger an alert to cause an escalation condition before the bark signal asserts.
+ - After the reset ensure that the reset cause was due to the escalation to prove that
+ the wdog was disabled.
+ '''
+ stage: V2
+ tests: ["chip_sw_aon_timer_wdog_lc_escalate"]
+ }
+ {
+ name: chip_sw_aon_timer_wdog_bite_reset
+ desc: '''Verify the watchdog bite causing reset in the normal state.
+
+ - Read the reset cause register in rstmgr to confirm that the SW is in the POR reset
+ phase.
+ - Program the AON timer wdog to 'bark' after some time.
+ - Let the bark escalate to bite, which should result in a reset request.
+ - After reset, read the reset cause register in rstmgr to confirm that the SW is now in
+ the wdog reset phase.
+ '''
+ stage: V2
+ tests: ["chip_sw_aon_timer_wdog_bite_reset"]
+ }
+ {
+ name: chip_sw_aon_timer_sleep_wdog_bite_reset
+ desc: '''Verify the watchdog bite causing reset in sleep state.
+
+ - Repeat the steps in chip_aon_timer_wdog_bite_reset test, but with following changes:
+ - Program the pwrmgr to go to deep sleep state (clocks off, power off).
+ - Issue a WFI after programming the wdog, so that the reset request due to bite occurs
+ during deep sleep state.
+ - After reset, read the reset cause register in rstmgr to confirm that the SW is now in
+ the wdog reset phase.
+ '''
+ stage: V2
+ tests: ["chip_sw_aon_timer_wdog_bite_reset"]
+ }
+ {
+ name: chip_sw_aon_timer_sleep_wdog_sleep_pause
+ desc: '''Verify that the wdog can be paused in sleep state.
+
+ - Repeat the steps in chip_aon_timer_sleep_wakeup test, but with following changes:
+ - Program the wdog to 'bite' a little sooner than the AON timer wake up.
+ - Also, program the wdog to pause during sleep.
+ - Issue a WFI after programming the wdog, so that the reset request occurs during deep
+ sleep state.
+ - After reset followed by AON timer wake up, read the reset cause register to confirm
+ that the AON timer woke up the chip, not the wdog reset.
+ - Un-pause the wdog and service the bark interrupt.
+ '''
+ stage: V2
+ tests: ["chip_sw_aon_timer_sleep_wdog_sleep_pause"]
+ }
+
+ // PLIC integration tests:
+ {
+ name: chip_sw_plic_all_irqs
+ desc: '''Verify all interrupts from all peripherals aggregated at the PLIC.
+
+ The automated SW test enables all interrupts at the PLIC to interrupt the core. It uses
+ the `intr_test` CSR in each peripheral to mock assert an interrupt, looping through all
+ available interrupts in that peripheral. The ISR verifies that the right interrupt
+ occurred. This is used as a catch-all interrupt test for all peripheral integration
+ testing within which functionally asserting an interrupt is hard to achieve or not of
+ high value.
+ '''
+ stage: V2
+ tests: ["chip_plic_all_irqs"]
+ }
+ {
+ name: chip_sw_plic_sw_irq
+ desc: '''Verify the SW interrupt to the CPU.
+
+ Enable all peripheral interrupts at PLIC. Enable all types of interrupt at the CPU core.
+ Write to the MSIP CSR to generate a SW interrupt to the CPU. Verify that the only
+ interrupt that is seen is the SW interrupt.
+ '''
+ stage: V2
+ tests: ["chip_sw_plic_sw_irq"]
+ }
+ {
+ name: chip_plic_fatal_alert
+ desc: '''Verify that the fatal alert is fired from PLIC due to bus integrity violation.
+
+ - PLIC is a non-preverified IP, so it is necessary to test the assertion of fatal alert
+ via fault injection.
+ - In stub CPU mode, read a register in PLIC.
+ - Intercept the access in the SystemVerilog testbench and using force, inject an
+ integrity error on the command channel.
+ - Verify that the fatal alert fired on the PLIC output.
+ - Reboot the chip and this time, inject a fatal alert through violation of the reg
+ write-enable one hot check using the standardized sec_cm_pkg framework.
+ - Verify that the fatal alert fired on the PLIC output.
+ '''
+ stage: V3
+ tests: []
+ }
+ {
+ name: chip_sw_plic_alerts
+ desc: '''Verify alerts from PLIC due to both, TL intg and reg WE onehot check faults.
+
+ - Since PLIC is not pre-verified in a DV environment, we need to ensure these are tested
+ separately.
+ '''
+ stage: V3
+ tests: []
+ }
+ {
+ name: chip_sw_smc_plic_all_irqs
+ desc: '''Verify all interrupts from all SMC_peripherals aggregated at the SMC_PLIC.
+
+ The automated SW test enables all interrupts at the PLIC to interrupt the core. It uses
+ the `intr_test` CSR in each peripheral to mock assert an interrupt, looping through all
+ available interrupts in that peripheral. The ISR verifies that the right interrupt
+ occurred. This is used as a catch-all interrupt test for all peripheral integration
+ testing within which functionally asserting an interrupt is hard to achieve or not of
+ high value.
+ -TO-DO: test name?
+ '''
+ stage: V2
+ tests: []
+ }
+ {
+ name: chip_sw_smc_plic_sw_irq
+ desc: '''Verify the SW interrupt to the SMC_CPU.
+
+ Enable all SMC_peripheral interrupts at SMC_PLIC. Enable all types of interrupt at
+ the CPU core.
+ Write to the MSIP CSR to generate a SW interrupt to the CPU. Verify that the only
+ interrupt that is seen is the SW interrupt.
+ -TO-DO: test name?
+ '''
+ stage: V2
+ tests: []
+ }
+ {
+ name: chip_sw_smc_plic_vsi_irq
+ desc: '''Verify the interrupts from VSI ips to the SMC_CPU.
+
+ - SW configure camera with test pattern which generate irqs.
+ - SW configure isp with test pattern which generate irqs.
+ - SW check if the expected irqs are received.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_plic_vsi_irq"]
+ }
+ {
+ name: chip_sw_atomics_test
+ desc: '''Verify atomic instruction on SMC core.
+
+ - SW bringup SMC core
+ - SW config valid and invalid address.
+ - SW runs atomic instructions and verify the functionality
+ '''
+ stage: V2
+ tests: ["chip_sw_atomics_test"]
+ }
+ // CLKMGR tests:
+ {
+ name: chip_sw_clkmgr_idle_trans
+ desc: '''Verify the ability to turn off the transactional clock via SW.
+
+ Ensure that the clock to transactional units will be turned off after any activity
+ completes in the transactional IP. Verify it is off via spinwait in hints_status CSR.
+ Verify that turning off this clock does not affect the other derived clocks.
+ '''
+ stage: V2
+ tests: ["chip_sw_aes_idle",
+ "chip_sw_hmac_enc_idle",
+ "chip_sw_kmac_idle",
+ "chip_sw_otbn_randomness"]
+ }
+ {
+ name: chip_sw_clkmgr_off_trans
+ desc: '''Verify the turned off transactional units.
+
+ Verify CSR accesses do not complete in units that are off. Using the watchdog timers,
+ turn off a transactional unit's clock, issue a CSR access to that unit, verify a
+ watchdog event results, and verify the rstmgr crash dump info records the CSR address.
+
+ A stretch goal is to check the PC corresponds to the code performing the CSR access
+ (stretch since it could be difficult to maintain this check).
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_off_aes_trans",
+ "chip_sw_clkmgr_off_hmac_trans",
+ "chip_sw_clkmgr_off_kmac_trans",
+ "chip_sw_clkmgr_off_otbn_trans"]
+ }
+ {
+ name: chip_sw_clkmgr_off_trans_sencha
+ desc: '''Verify the transactional units added in sencha can be turned off by disabling the
+ gateable clocks
+
+ Verify that when the gateable clock is turned off, the corresponding output signal from
+ clkmgr is constant 0
+ '''
+ stage: V3
+ tests: ["chip_sw_clkmgr_off_smc_trans",
+ "chip_sw_clkmgr_off_ml_trans",
+ "chip_sw_clkmgr_off_video_trans",
+ "chip_sw_clkmgr_off_audio_trans"]
+ }
+ {
+ name: chip_sw_clkmgr_off_peri
+ desc: '''Verify the ability to turn off the peripheral clock via SW.
+
+ Verify CSR accesses do not complete in peripherals that are off. Using the watchdog
+ timers, turn off a peripheral's clock, issue a CSR access to that peripheral, verify a
+ watchdog event results, and verify the rstmgr crash dump info records the CSR address.
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_off_peri"]
+ }
+ {
+ name: chip_sw_clkmgr_div
+ desc: '''Verify clk division logic is working correctly.
+
+ The IP level checks the divided clocks via SVA, and these are also bound at chip level.
+ Connectivity tests check peripherals are connected to the clock they expect.
+ Use the clkmgr count measurement feature to verify clock division.
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_external_clk_src_for_sw_fast",
+ "chip_sw_clkmgr_external_clk_src_for_sw_slow",
+ "chip_sw_clkmgr_external_clk_src_for_lc"]
+ }
+ {
+ name: chip_sw_clkmgr_external_clk_src_for_lc
+ desc: '''Verify the clkmgr requests ext clk src during certain LC states.
+
+ On POR lc asserts lc_clk_byp_req on some LC states, and de-asserts
+ it when lc_program completes. This also triggers divided clocks to step down. It may be
+ best to verify this via SVA, unless we implement clock cycle counters.
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_external_clk_src_for_lc"]
+ }
+ {
+ name: chip_sw_clkmgr_external_clk_src_for_sw
+ desc: '''Verify SW causes the clkmgr requests ext clk src during certain LC states.
+
+ In RMA and TEST_UNLOCKED lc states the external clock is enabled in response to
+ `extclk_ctrl.sel` CSR writes. In addition `extclk_ctrl.hi_speed_sel` CSR causes the
+ divided clocks to step down. Verify this via SVA bound to clkmgr, and clock cycle
+ counters.
+
+ Disable external clock source and verify the AST reliably falls back to the internal
+ clock. Ensure the chip operates normally.
+ X-ref with chip_sw_uart_tx_rx_alt_clk_freq, which needs to deal with this as well.
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_external_clk_src_for_sw_fast",
+ "chip_sw_clkmgr_external_clk_src_for_sw_slow"]
+ }
+ {
+ name: chip_sw_clkmgr_jitter
+ desc: '''Verify the clock jitter functionality.
+
+ Enable clock jitter setting the clkmgr `jitter_enable` CSR high. This causes the
+ jitter_o clkmgr output to toggle. Verify this output is connected to AST's
+ clk_src_sys_jen_i input using formal.
+
+ X-ref with various specific jitter enable tests.
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_jitter",
+ "chip_sw_flash_ctrl_ops_jitter_en",
+ "chip_sw_flash_ctrl_access_jitter_en",
+ "chip_sw_otbn_ecdsa_op_irq_jitter_en",
+ "chip_sw_aes_enc_jitter_en",
+ "chip_sw_hmac_enc_jitter_en",
+ "chip_sw_keymgr_key_derivation_jitter_en",
+ "chip_sw_kmac_mode_kmac_jitter_en",
+ "chip_sw_sram_ctrl_scrambled_access_jitter_en",
+ "chip_sw_edn_entropy_reqs_jitter"]
+ }
+ {
+ name: chip_sw_clkmgr_extended_range
+ desc: '''Verify that the system can run at a reduced, calibrated clock frequency.
+
+ This test should check that the system can run at a reduced, calibrated clock frequency
+ (70MHz) with jitter enabled (which can lower the frequency down to ~55 MHz
+ momentarily). This option is intended as a fall-back in case there are issues running
+ the system with at 100MHz (calibrated).
+
+ This testpoint can be covered by extending the DV environment to support the extended
+ range clock option via a flag, and running several existing chip-level tests with that
+ option.
+
+ Test the following functionalities with reduced clock:
+
+ - flash_ctrl initialization
+ - flash_ctrl program, read and erase operations
+ - AES, HMAC, KMAC and OTBN operations
+ - Keymgr key derivation
+ - Scramble-enabled access from the main SRAM
+ - Csrng edn concurrency
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_jitter_reduced_freq",
+ "chip_sw_flash_ctrl_ops_jitter_en_reduced_freq",
+ "chip_sw_flash_ctrl_access_jitter_en_reduced_freq",
+ "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq",
+ "chip_sw_aes_enc_jitter_en_reduced_freq",
+ "chip_sw_hmac_enc_jitter_en_reduced_freq",
+ "chip_sw_keymgr_key_derivation_jitter_en_reduced_freq",
+ "chip_sw_kmac_mode_kmac_jitter_en_reduced_freq",
+ "chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq",
+ "chip_sw_flash_init_reduced_freq",
+ "chip_sw_csrng_edn_concurrency_reduced_freq"]
+ }
+ {
+ name: chip_sw_clkmgr_deep_sleep_frequency
+ desc: '''Verify the frequency measurement through deep sleep.
+
+ Enable clock cycle counts. Put the chip in deep sleep. Upon wakeup reset the
+ clock measurements should be off, but the recoverable fault status should not
+ be cleared.
+ '''
+ stage: V2
+ tests: ["chip_sw_ast_clk_outputs"]
+ }
+ {
+ name: chip_sw_clkmgr_sleep_frequency
+ desc: '''Verify the frequency measurement through shallow sleep.
+
+ Enable clock cycle counts. Put the chip in shallow sleep with pwrmgr's CONTROL CSR
+ keeping some clocks disabled. Upon wakeup the clock measurements should be on, and the
+ recoverable fault status should show no errors for the disabled clocks.
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_sleep_frequency"]
+ }
+ {
+ name: chip_sw_clkmgr_reset_frequency
+ desc: '''Verify the frequency measurement through reset.
+
+ Enable clock cycle counts, configured to cause errors. Trigger a chip reset via SW.
+ After reset the clock measurements should be off and the recoverable fault status
+ should be cleared.
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_reset_frequency"]
+ }
+ {
+ name: chip_sw_clkmgr_escalation_reset
+ desc: '''Verify the clock manager resets to a clean state after an escalation reset.
+
+ Trigger an internal fatal fault for the regfile onehot checker and let it escalate to
+ reset. Upon alert escalation reset, the internal status should be clear and clkmgr
+ should not attempt to send out more alerts.
+ '''
+ stage: V2
+ tests: ["chip_sw_all_escalation_resets"]
+ }
+ {
+ name: chip_sw_flash_ctrl_escalation_reset
+ desc: '''Verify the flash ctrl fatal error does not disturb escalation process
+ and operation of ibex core.
+
+ Trigger an internal fatal fault (host_gnt_err) from flash_ctrl
+ and let it escalate to reset. Upon alert escalation reset,
+ the internal status should be clean and should not send out more alerts.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_crash_alert"]
+ }
+
+ // PWRMGR tests:
+ {
+ name: chip_sw_pwrmgr_external_full_reset
+ desc: '''Verify the cold boot sequence by wiggling of chip's `POR_N`.
+
+ This ensures that both FSMs are properly reset on the POR signal. The check is that
+ the processor ends up running. Also verify, the rstmgr recorded POR in `reset_info` CSR
+ by checking retention SRAM for reset_reason.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_full_aon_reset"]
+ }
+ {
+ name: chip_sw_pwrmgr_random_sleep_all_wake_ups
+ desc: '''Verify that the chip can go into random low power states and be woken up by ALL wake
+ up sources.
+
+ This verifies ALL wake up sources. This also verifies that the pwrmgr sequencing is
+ working correctly as expected. X-ref'ed with all individual IP tests. For each wakeup
+ source clear and enable `wake_info` CSR, enable the wakeup from that source with the
+ `wakeup_en` CSR, bring the chip to both normal and low power sleep, optionally
+ disabling the source's clock, have the source issue a wakeup event and verify
+ `wake_info` indicates the expected wakeup.
+
+ Each test should perform a minimum of 2 low power transitions to ensure there are no
+ state dependent corner cases with wakeup interactions.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_random_sleep_all_wake_ups"]
+ }
+ {
+ name: chip_sw_pwrmgr_normal_sleep_all_wake_ups
+ desc: '''Verify that the chip can go into normal sleep state and be woken up by ALL wake up
+ sources.
+
+ This verifies ALL wake up sources. This also verifies that the pwrmgr sequencing is
+ working correctly as expected. X-ref'ed with all individual IP tests. For each wakeup
+ source clear and enable `wake_info` CSR, enable the wakeup from that source with the
+ `wakeup_en` CSR, bring the chip to normal sleep, optionally disabling the source's
+ clock, have the source issue a wakeup event and verify `wake_info` indicates the
+ expected wakeup.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_normal_sleep_all_wake_ups"]
+ }
+ {
+ name: chip_sw_pwrmgr_sleep_all_reset_reqs
+ desc: '''Verify that the chip can go into normal sleep state and be reset by ALL reset req
+ sources.
+
+ This verifies ALL reset sources. This also verifies that the pwrmgr sequencing is
+ working correctly as expected. X-ref'ed with all individual IP tests. For each reset
+ source, enable the source and bring the chip to low power, issue a reset, and verify the
+ rstmgr's `reset_info` indicated the expected reset by checking retention SRAM for
+ reset_reason.
+ '''
+ stage: V2
+ tests: ["chip_sw_aon_timer_wdog_bite_reset"]
+ }
+ {
+ name: chip_sw_pwrmgr_deep_sleep_all_wake_ups
+ desc: '''Verify that the chip can go into deep sleep state and be woken up by ALL wake up
+ sources.
+
+ This verifies ALL wake up sources. This also verifies that the pwrmgr sequencing is
+ working correctly as expected. X-ref'ed with all individual IP tests. Similar to
+ chip_pwrmgr_sleep_all_wake_ups, except `control.main_pd_n` is set to 0.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_deep_sleep_all_wake_ups"]
+ }
+ {
+ name: chip_sw_pwrmgr_deep_sleep_all_reset_reqs
+ desc: '''Verify that the chip can go into deep sleep state and be reset up by ALL reset req
+ sources.
+
+ This verifies ALL reset sources.
+ - 7 resets are generated randomly with deep sleeps
+ - POR (HW PAD) reset, SW POR, sysrst, wdog timer reset, esc rst, SW req
+ - esc reset is followd by normal mode because it does not work with sleep mode
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_deep_sleep_all_reset_reqs"]
+ }
+ {
+ name: chip_sw_pwrmgr_normal_sleep_all_reset_reqs
+ desc: '''Verify that the chip can go into normal sleep state and be reset up by ALL reset req
+ sources.
+
+ This verifies ALL reset sources.
+ - 7 resets are generated randomly with normal sleeps
+ - POR (HW PAD) reset, SW POR, sysrst, wdog timer reset, esc rst, SW req
+ - esc reset is followed by normal mode and cleared by reset because it does not work
+ with sleep mode
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_normal_sleep_all_reset_reqs"]
+ }
+ {
+ name: chip_sw_pwrmgr_wdog_reset
+ desc: '''Verify that the chip can be reset by watchdog timer reset source.
+
+ This verifies watchdog timer reset source. This also verifies that the pwrmgr sequencing
+ is working correctly as expected. X-ref'ed with all individual IP tests. Similar to
+ chip_pwrmgr_sleep_all_reset_reqs, except the chip is not put in low power mode.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_wdog_reset"]
+ }
+ {
+ name: chip_sw_pwrmgr_aon_power_glitch_reset
+ desc: '''Verify the cold boot sequence through an AON power glitch.
+
+
+ Pulsing the AST vcaon_supp_i input causes an AON power glitch which becomes a POR.
+ This ensures that both FSMs are properly reset on the POR signal. The check is that
+ the processor ends up running. Also verify, the rstmgr recorded POR in `reset_info` CSR
+ by checking retention SRAM for reset_reason.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_full_aon_reset"]
+ }
+ {
+ name: chip_sw_pwrmgr_main_power_glitch_reset
+ desc: '''Verify the effect of a glitch in main power rail.
+
+ The vcmain_supp_i AST input is forced to drop once the test is running. This triggers
+ a MainPwr reset request, which is checked by reading retention SRAM's reset_reason to
+ see that the reset_info CSR's POR bit is not set when the test restarts.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_main_power_glitch_reset"]
+ }
+ {
+ name: chip_sw_pwrmgr_random_sleep_power_glitch_reset
+ desc: '''Verify the effect of a glitch in main power rail in random sleep states.
+
+ The vcmain_supp_i AST input is forced to drop right after putting the chip in a random
+ sleep state. This triggers a MainPwr reset request, which is checked by reading
+ retention SRAM's reset_reason to show that the reset_info CSR's POR bit is not set when
+ the test restarts.
+
+ Note: the glitch has to be sent in a very narrow window:
+ - If sent too early the chip won't have started to process deep sleep.
+ - If too late the hardware won't monitor main power okay so the glitch will have no
+ effect, and the test will timeout.
+
+ Each test should perform a minimum of 2 low power transitions to ensure there are no
+ state dependent corner cases with power glitch handling.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_random_sleep_power_glitch_reset"]
+ }
+ {
+ name: chip_sw_pwrmgr_deep_sleep_power_glitch_reset
+ desc: '''Verify the effect of a glitch in main power rail in deep sleep.
+
+ The vcmain_supp_i AST input is forced to drop right after putting the chip in deep
+ sleep. This triggers a MainPwr reset request, which is checked by reading retention
+ SRAM's reset_reason to show that the reset_info CSR's POR bit is not set when the test
+ restarts.
+
+ Note: the glitch has to be sent in a very narrow window:
+ - If sent too early the chip won't have started to process deep sleep.
+ - If too late the hardware won't monitor main power okay so the glitch will have no
+ effect, and the test will timeout.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_deep_sleep_power_glitch_reset"]
+ }
+ {
+ name: chip_sw_pwrmgr_sleep_power_glitch_reset
+ desc: '''Verify the effect of a glitch in main power rail in shallow sleep.
+
+ The vcmain_supp_i AST input is forced to drop after putting the chip in shallow sleep.
+ This triggers a MainPwr reset request, which is checked by reading the retention SRAM's
+ reset_reason shows that the reset_info CSR's POR bit is not set when the
+ test restarts.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_sleep_power_glitch_reset"]
+ }
+ {
+ name: chip_sw_pwrmgr_random_sleep_all_reset_reqs
+ desc: '''Verify that this chip can be reset by All available reset sources.
+
+ - 12 resets are generated randomly with normal/deep sleeps
+ - POR (HW PAD) reset, SW POR, sysrst, wdog timer reset, esc rst, SW req
+ - esc reset is followd by normal mode because it does not work with sleep mode
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_random_sleep_all_reset_reqs"]
+ }
+ {
+ name: chip_sw_pwrmgr_sysrst_ctrl_reset
+ desc: '''Verify the effect of a sysrst_ctrl output in main power rail.
+
+ - Read the reset cause register in rstmgr to confirm that the SW is in the POR reset
+ phase.
+ - After sysrst reset is generated by forcing, read the reset cause register in rstmgr to
+ confirm that the SW is now in the sysrst reset phase.
+ - Generate sysrst by driving input PAD.
+ - After reset, read the reset cause register in rstmgr to confirm that the SW is now in
+ the sysrst reset phase.
+ - Program the AON timer wdog to 'bark' after some time.
+ - Let the bark escalate to bite, which should result in a reset request.
+ - After reset, read the reset cause register in rstmgr to confirm that the SW is now in
+ the wdog reset phase.
+ - Program the AON timer wdog to 'bark' after some time.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_sysrst_ctrl_reset"]
+ }
+ {
+ name: chip_sw_pwrmgr_b2b_sleep_reset_req
+ desc: '''Verify that the pwrmgr sequences sleep_req and reset req coming in almost at the same
+ time, one after the other. Use POR_N PAD to trigger reset.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_b2b_sleep_reset_req"]
+ }
+ {
+ name: chip_sw_pwrmgr_sleep_disabled
+ desc: '''Verify that the chip does not go to sleep on WFI when low power hint is 0.
+
+ This calls WFI with low_power_hint disabled and pwrmgr interrupts enabled,
+ and fails if the pwrmgr ISR is called.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_sleep_disabled"]
+ }
+ {
+ name: chip_sw_pwrmgr_escalation_reset
+ desc: '''Verify the power manager resets to a clean state after an escalation reset.
+
+ Trigger an internal fatal fault for the regfile onehot checker and let it escalate to
+ reset. Upon alert escalation reset, the internal status should be clear and pwrmgr
+ should not attempt to send out more alerts.
+ '''
+ stage: V2
+ tests: ["chip_sw_all_escalation_resets"]
+ }
+
+ // RSTMGR tests:
+ {
+ name: chip_sw_rstmgr_non_sys_reset_info
+ desc: '''Verify the `reset_info` CSR register for lc or higher resets.
+
+ Generate the 5 types of reset at `lc` level or higher, and check the retention SRAM's
+ reset_reason to show that `reset_info` CSR is as expected. This and other rstmgr
+ testpoints that require different resets cross-reference the individual IP tests that
+ generate those resets, and this testpoint merely adds reset checks in them. Those IP
+ blocks are `pwrmgr`, `alert_handler`, `aon_timer`, and `sysrst_ctrl`.
+
+ This should also check the reset's destination IP to make sure some reset side-effect
+ is present. Setting some `intr_enable` CSR bit when the test starts and checking it
+ after reset seems suitable. The `spi_host` IPs receive multiple resets so they will
+ need special consideration.
+ TODO(maturana) Add specific tests once they are developed.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_smoketest"]
+ }
+ {
+ name: chip_sw_rstmgr_sys_reset_info
+ desc: '''Verify the `reset_info` CSR register for sys reset.
+
+ Generate reset triggered by `rv_dm`, which results in a sys level reset, and check the
+ retention SRAM's reset_reason to show that the `reset_info` CSR is as expected. This
+ testpoint cross-reference the `rv_dm` tests that generate this reset, and this
+ testpoint merely adds reset checks in them.
+
+ This should also check the reset's destination IP to make sure some reset side-effect
+ is present. Setting some `intr_enable` CSR bit when the test starts and checking it
+ after reset seems suitable. The `spi_host` IPs receive multiple resets so they will
+ need special consideration.
+
+ X-ref with chip_rv_dm_ndm_reset_req.
+
+ '''
+ stage: V2
+ tests: ["chip_rv_dm_ndm_reset_req"]
+ }
+ {
+ name: chip_sw_rstmgr_cpu_info
+ desc: '''Verify the expected values from the `cpu_info` CSR on reset.
+
+ For some software induced resets we can predict the expected contents of `cpu_info`;
+ reads of writes to unmapped addresses for example. Generate these resets and verify
+ the `cpu_info` register contents when reset is handled.
+ Refer to `chip_*sys_rstmgr_reset_info`.
+ '''
+ stage: V2
+ tests: ["chip_sw_rstmgr_cpu_info"]
+ }
+ {
+ name: chip_sw_rstmgr_sw_req_reset
+ desc: '''Verify software requested device reset.
+
+ Generate a reset request by directly writing the `reset_req` CSR.
+ The reset created should be identical to those caused by hardware sources.
+ After reset, the retention SRAM's reset_reason should show that the `reset_info` CSR
+ reflects that a software request was the reset cause.
+ '''
+ stage: V2
+ tests: ["chip_sw_rstmgr_sw_req"]
+ }
+ {
+ name: chip_sw_rstmgr_alert_info
+ desc: '''Verify the expected values from the `alert_info` CSR on reset.
+
+ Various alerts can be created, for example, timeouts, and integrity errors, and at
+ least part of the `alert_info` CSR can be predicted. To cause some of these to
+ cause a reset, mask the relevant processor interrupts. Trigger these resets and
+ verify the `alert_info` register contents when reset is handled.
+ Refer to `chip_*sys_rstmgr_reset_info`.
+ '''
+ stage: V2
+ tests: ["chip_sw_rstmgr_alert_info"]
+ }
+ {
+ name: chip_sw_rstmgr_sw_rst
+ desc: '''Verify `sw_rst_ctrl_n` CSR resets individual peripherals.
+
+ - Pick a rw type CSR in each peripheral and program arbitrary value
+ that does not cause any adverse side-effects.
+ - Pulse the reset to the peripheral via software.
+ - Read the resister after reset and verify it returns the reset value.
+ - Repeat these steps for each of these software resettable peripherals:
+ `spi_device`, `spi_host0`, `spi_host1`, `usb`, `i2c0`, `i2c1`, `i2c2`.
+
+ Notice the two `spi_host` IPs receive two different resets, `spi_host*`.
+ '''
+ stage: V2
+ tests: ["chip_sw_rstmgr_sw_rst"]
+ }
+ {
+ name: chip_sw_rstmgr_escalation_reset
+ desc: '''Verify the reset manager resets to a clean state after an escalation reset.
+
+ Trigger an internal fatal fault for the regfile onehot checker and let it escalate to
+ reset. Upon alert escalation reset, the internal status should be clear and rstmgr
+ should not attempt to send out more alerts.
+ '''
+ stage: V2
+ tests: ["chip_sw_all_escalation_resets"]
+ }
+
+ // ALERT_HANDLER (pre-verified IP) integration tests:
+ {
+ name: chip_sw_alert_handler_alerts
+ desc: '''Verify all alerts coming into the alert_handler.
+
+ An automated SW test, which does the following (applies to all alerts in all IPs):
+ - Program the alert_test CSR in each block to trigger each alert one by one.
+ - Ensure that all alerts are properly connected to the alert handler and cause the
+ escalation paths to trigger.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_test"]
+ }
+ {
+ name: chip_sw_alert_handler_escalations
+ desc: '''Verify all alert escalation paths.
+
+ Verify all escalation paths triggered by an alert.
+ - Verify the first escalation results in NMI interrupt serviced by the CPU.
+ - Verify the second results in device being put in scrap state, via the LC JTAG TAP.
+ - Verify the third results in chip reset.
+ - Ensure that all escalation handshakes complete without errors.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_handler_escalation"]
+ }
+ {
+ name: chip_sw_all_escalation_resets
+ desc: '''Verify escalation from all unit integrity errors
+
+ Inject integrity errors in any unit that has a one-hot checker for CSR register
+ writes, and verify escalation is triggered. Allow escalation to go through reset.
+ Use the rstmgr alert info and the unit's fault CSRs to check the alert cause is right.
+ Each run of the test randomly chooses some one-hot checker for the error to be injected.
+ Keep state across resets in flash to check the expected interrupts and the right number
+ of resets occur.
+ - Verify the integrity error results in a regular interrupt.
+ - Verify the first escalation results in NMI serviced by the CPU.
+ - Verify the alert id in both these interrupts.
+ - Verify the unit's fault CSR correctly captured the fault kind.
+ - Verify any timer interrupts are disabled by escalation.
+ - Verify after the escalation reset all faults are cleared, and that the alert
+ info captured the correct alert.
+ - Check that no additional resets occur.
+ '''
+ stage: V2
+ tests: ["chip_sw_all_escalation_resets"]
+ }
+ {
+ name: chip_sw_alert_handler_irqs
+ desc: '''Verify all classes of alert handler interrupts to the CPU.
+
+ X-ref'ed with the automated PLIC test.
+ '''
+ stage: V2
+ tests: ["chip_plic_all_irqs"]
+ }
+ {
+ name: chip_sw_alert_handler_entropy
+ desc: '''Verify the alert handler entropy input to ensure pseudo-random ping timer.
+
+ - Force `alert_handler_ping_timer` input signal `wait_cyc_mask_i` to `8'h07` to
+ shorten the simulation time.
+ - Verify that the alert_handler can request EDN to provide entropy.
+ - Ensure that the alert ping handshake to all alert sources and escalation receivers
+ complete without errors.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_handler_entropy"]
+ }
+ {
+ name: chip_sw_alert_handler_crashdump
+ desc: '''Verify the alert handler crashdump signal.
+
+ When the chip resets due to alert escalating to cause the chip to reset, verify the
+ reset cause to verify the alert crashdump.
+
+ Xref'ed with chip_sw_rstmgr_alert_info.
+ '''
+ stage: V2
+ tests: ["chip_sw_rstmgr_alert_info"]
+ }
+ {
+ name: chip_sw_alert_handler_ping_timeout
+ desc: '''Verify the alert senders' ping timeout.
+
+ Set alert_handler's ping timeout cycle to 2 and enable alert_senders. Verify that
+ alert_handler detects the ping timeout and reflects it on the `loc_alert_cause`
+ register.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_handler_ping_timeout"]
+ }
+ {
+ name: chip_sw_alert_handler_lpg_sleep_mode_alerts
+ desc: '''Verify alert_handler can preserve alerts during low_power mode.
+
+ - Trigger fatal alerts for all IPs but configure alert_handler so it won't trigger
+ reset.
+ - Randomly enter normal or deep sleep mode.
+ - Wait random cycles then wake up from the sleep mode.
+ - After wake up from normal sleep mode, clear all alert cause registers and check that
+ all alerts are still firing after waking up.
+ - Repeat the previous steps for random number of iterations.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_handler_lpg_sleep_mode_alerts"]
+ }
+ {
+ name: chip_sw_alert_handler_lpg_sleep_mode_pings
+ desc: '''Verify alert_handler's ping mechanism works correctly during sleep and wake up.
+
+ There are two scenarios to check:
+ - Configure alert_handler's ping timeout register to a reasonble value that won't cause
+ ping timeout in normal cases.
+ Then randomly enter and exit normal or deep sleep modes.
+ Check that no local alerts triggered in alert_handler.
+ This scenario ensures that ping mechanism won't send out spurious failure.
+ - Configure alert_handler's ping timeout register to a small value that will always
+ causes ping timeout.
+ Then randomly enter and exit normal or deep sleep modes.
+ Clear local alert cause register and check that alert ping timeout continue to fire
+ after wake up.
+ This scenario ensures the ping mechanism will continue to send out pings after waking
+ up from sleep modes.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_handler_lpg_sleep_mode_pings"]
+ }
+ {
+ name: chip_sw_alert_handler_lpg_clock_off
+ desc: '''Verify alert_handler's works correctly when sender clock is turned off.
+
+ - Configure clkmgr to randomly turn off one of the IP's clock and check alert_handler
+ won't trigger a ping timeout error on that block.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_handler_lpg_clkoff"]
+ }
+ {
+ name: chip_sw_alert_handler_lpg_reset_toggle
+ desc: '''Verify alert_handler's works correctly when sender reset is toggled.
+
+ - Configure rstmgr to randomly toggle one IP block's SW reset and check alert_handler
+ won't trigger a ping timeout error on that block.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_handler_lpg_reset_toggle"]
+ }
+ {
+ name: chip_sw_alert_handler_reverse_ping_in_deep_sleep
+ desc: '''Verify escalation reverse ping timer disabled in sleep mode.
+
+ Check that escalation receivers located inside always-on blocks do not auto-escalate
+ due to the reverse ping feature while the system is in deep sleep.
+
+ ## Reverse ping timeout calculation
+
+ The reverse ping timeout calculation is done using the following formula available in
+ `prim_esc_receiver`:
+
+ ```
+ 4 * N_ESC_SEV * (2 * 2 * 2^PING_CNT_DW)
+ ```
+
+ `pwrmgr` is the only block consuming the `N_ESC_SEV` and `PING_CNT_DW` compile time
+ parameters:
+
+ ```
+ alert_handler_reg_pkg::N_ESC_SEV = 4
+ alert_handler_reg_pkg::PING_CNT_DW = 16
+ ```
+
+ The alert escalation responder inside `pwrmgr` is connected to the `io_div4` clock,
+ yielding a target 24MHz frequency. The result expected timeout based on the above
+ parameters is thus:
+
+ ```
+ reverse_ping_timeout = 0.175s = (4 * 4 ( 2 * 2 * 2^16)) / 24e6
+ ```
+
+ ## Procedure
+
+ - On POR reset:
+ - Enable all alerts assigning them to ClassA.
+ - Enable all local alerts and assign to ClassB.
+ - Set escalation configuration to trigger before test wake up time.
+ - Set ping timeout to a time less than wake up time.
+ - Lock alert configuration and enable ping mechanism.
+ - Wait for polling counters to cycle through by busy polling on Ibex for
+ `reverse_ping_timeout >> 2` usec.
+ - Configure AON to wake up device at a later time, making sure it is greater than the
+ `reverse_ping_timeout` calculated in the previous section.
+ - Enter deep sleep.
+ - On wake up from sleep:
+ - Ensure reset status is low power exit. A `kDifRstmgrResetInfoEscalation` signals
+ that there was a local escalation and should result in test failure.
+ - Disable AON timer.
+ - Check there are no flagged local alerts.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_handler_reverse_ping_in_deep_sleep"]
+ }
+
+ // LC_CTRL (pre-verified IP) integration tests:
+ {
+ name: chip_sw_lc_ctrl_alert_handler_escalation
+ desc: '''Verify that the escalation signals from the alert handler are connected to LC ctrl.
+
+ - Trigger an alert to initiate the escalations.
+ - Check that the escalation signals are connected to the LC ctrl:
+ - First escalation has no effect on the LC ctrl. Read LC_STATE CSR to confirm
+ this is the case.
+ - Second escalation should cause the `lc_escalation_en` output to be asserted and for
+ the LC_STATE to transition to scrap state. Confirm by reading the LC_STATE CSR
+ - Verify that all decoded outputs except for escalate_en are
+ disabled. X-ref'ed with the respective IP tests that consume these signals.
+
+ X-ref'ed with chip_sw_lc_ctrl_broadcast test, which verifies the connectivity of the LC
+ decoded outputs to other IPs.
+ X-ref'ed with alert_handler's escalation test.
+ '''
+ stage: V2
+ tests: ["chip_sw_alert_handler_escalation"]
+ }
+ {
+ name: chip_sw_lc_ctrl_jtag_access
+ desc: '''Verify enable to access LC ctrl via JTAG.
+
+ Using the JTAG agent, write and read LC ctrl CSRs, verify the read value for
+ correctness.
+ '''
+ stage: V2
+ tests: ["chip_tap_straps_dev", "chip_tap_straps_prod", "chip_tap_straps_rma"]
+ }
+ {
+ name: chip_sw_lc_ctrl_otp_hw_cfg
+ desc: '''Verify the device_ID and ID_state CSRs
+
+ - Preload the hw_cfg partition in OTP ctrl with random data.
+ - Read the device ID and the ID state CSRs to verify their correctness.
+ - Reset the chip and repeat the first 2 steps to verify a different set of values.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_otp_hw_cfg"]
+ }
+ {
+ name: chip_sw_lc_ctrl_init
+ desc: '''Verify the LC ctrl initialization on power up.
+
+ Verify that the chip powers up correctly on POR.
+ - The pwrmgr initiates a handshake with OTP ctrl and later, with LC ctrl in subsequent
+ FSM states. Ensure that the whole power up sequence does not hang.
+ - Verify with connectivity assertion checks, the handshake signals are connected.
+ - Ensure that no interrupts or alerts are triggered.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_transition"]
+ }
+ {
+ name: chip_sw_lc_ctrl_transitions
+ desc: '''Verify the LC ctrl can transit from one state to another valid state with the
+ correct tokens.
+
+ - Preload OTP image with a LC state and required tokens to transfer to next state.
+ - Initiate an LC ctrl state transition via SW if CPU is enabled, or via JTAG interface
+ if CPU is disable.
+ - Ensure that the LC program request is received by the OTP ctrl.
+ - Verify the updated data output from OTP ctrl to LC ctrl is correct.
+ - Ensure that there is no background or otp_init error.
+ - Verify that the LC ctrl has transitioned to the programmed state after a reboot.
+ Re-randomize the lc_transition tokens and repeat the sequence above.
+
+ X-ref'ed chip_sw_otp_ctrl_program.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_transition"]
+ }
+ {
+ name: chip_sw_lc_ctrl_kmac_req
+ desc: '''Verify the token requested from KMAC.
+
+ - For conditional transition, the LC ctrl will send out a token request to KMAC.
+ - Verify that the KMAC returns a hashed token, which should match one of the
+ transition token CSRs.
+
+ X-ref'ed with chip_kmac_lc_req.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_transition"]
+ }
+ {
+ name: chip_sw_lc_ctrl_key_div
+ desc: '''Verify the keymgr div output to keymgr.
+
+ - Verify in different LC states, LC ctrl outputs the correct `key_div_o` to keymgr.
+ - Verify that the keymgr uses the given `key_div_o` value to compute the keys.
+ '''
+ stage: V2
+ tests: ["chip_sw_keymgr_key_derivation_prod"]
+ }
+ {
+ name: chip_sw_lc_ctrl_broadcast
+ desc: '''Verify broadcast signals from lc_ctrl.
+
+ - Preload the LC partition in the otp_ctrl with the following states: RMA, DEV,
+ TEST_LOCKED[N] & SCRAP.
+ - Verify that the following broadcast signals are having the right effect in the
+ respective IPs that consume them:
+ - lc_dft_en_o: impacts pinmux, pwrmgr, otp_ctrl, AST
+ - lc_hw_debug_en_o: impacts pinmux, pwrmgr, sram_ctrl (main and ret) & the rv_dm
+ - lc_keymgr_en_o: impacts keymgr
+ - lc_clk_byp_req_o: impacts clkmgr (handshake with lc_clk_byp_ack_i)
+ - lc_flash_rma_req_o: impacts flash_ctrl (handshake with lc_flash_ram_ack_i)
+ - lc_flash_rma_seed_o: impacts flash_ctrl
+ - lc_check_byp_en_o: impacts otp_ctrl
+ - lc_creator_seed_sw_rw_en_o: impacts flash_ctrl & otp_ctrl
+ - lc_owner_seed_sw_rw_en_o: impacts flash_ctrl
+ - lc_iso_part_sw_rd_en_o: impacts flash_ctrl
+ - lc_iso_part_sw_wr_en_o: impacts flash_ctrl
+ - lc_seed_hw_rd_en_o: impacts flash_ctrl & otp_ctrl
+ - These outputs are enabled per the
+ [life cycle architecture spec]({{< relref "doc/security/specs/device_life_cycle/#architecture" >}}).
+
+ X-ref'ed with the respective IP tests that consume these signals.
+
+ Note that the following signals are already verified with connectivity tests and SVAs:
+ - lc_dft_en_o (AST connection)
+ - lc_cpu_en_o (rv_core_ibex)
+ - lc_nvm_debug_en_o (flash_ctrl)
+ - lc_escalate_en_o (multiple)
+ '''
+ stage: V2
+ tests: [
+ "chip_prim_tl_access", // lc_dft_en_o: otp_ctrl
+ "chip_tap_straps_dev", // lc_dft_en_o, lc_hw_debug_en_o: pinmux
+ "chip_tap_straps_prod", // lc_dft_en_o, lc_hw_debug_en_o: pinmux
+ "chip_tap_straps_rma", // lc_dft_en_o, lc_hw_debug_en_o: pinmux
+ "chip_sw_rom_ctrl_integrity_check", // lc_dft_en_o, lc_hw_debug_en_o: pwrmgr
+ "chip_sw_clkmgr_external_clk_src_for_sw_fast", // lc_hw_debug_en_o: clkmgr
+ "chip_sw_clkmgr_external_clk_src_for_sw_slow", // lc_hw_debug_en_o: clkmgr
+ "chip_sw_sram_ctrl_execution_main", // lc_hw_debug_en_o: sram_ctrl main
+ "chip_rv_dm_lc_disabled" // lc_hw_debug_en_o: rv_dm
+ "chip_sw_keymgr_key_derivation", // lc_keymgr_en_o: keymgr
+ "chip_sw_clkmgr_external_clk_src_for_lc", // lc_clk_byp_req_o: clkmgr
+ "chip_sw_flash_rma_unlocked", // lc_flash_rma_req_o, lc_flash_rma_seed_o: flash_ctrl
+ "chip_sw_lc_ctrl_transition", // lc_check_byp_en_o: otp_ctrl
+ "chip_sw_flash_ctrl_lc_rw_en", // lc_creator*, lc_seed*, lc_owner*, lc_iso*: flash_ctrl
+ "chip_sw_otp_ctrl_lc_signals_test_unlocked0", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl
+ "chip_sw_otp_ctrl_lc_signals_dev", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl
+ "chip_sw_otp_ctrl_lc_signals_prod", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl
+ "chip_sw_otp_ctrl_lc_signals_rma", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl
+ ]
+ }
+ {
+ name: chip_sw_lc_ctrl_kmac_error
+ desc: '''
+ Verify the effect of KMAC returning an error during the hash generation of LC tokens.
+
+ - Follow the steps in `chip_sw_lc_ctrl_kmac_req` test.
+ - While the KMAC is actively computing the digest, glitch the KMAC app sparse FSM to
+ trigger a fault.
+ - Verify that KMAC returns an error signal to the LC controller.
+ - TBD
+ '''
+ stage: V3
+ tests: []
+ }
+
+
+ // SYSRST_CTRL (pre-verified IP) integration tests:
+ {
+ name: chip_sw_sysrst_ctrl_inputs
+ desc: '''Verify that the SYSRST ctrl input pin values can be read.
+
+ - Drive a known value on ac_reset, ec_rst_l, flash_wp_l, pwrb, lid_open and key* pins at
+ the chip inputs.
+ - Read the pin_in_value CSR to check for correctness.
+ '''
+ stage: V2
+ tests: ["chip_sw_sysrst_ctrl_inputs"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_outputs
+ desc: '''Verify that the SYSRST ctrl output pin values can be set.
+
+ - Drive a known value on ac_reset, ec_rst_l, flash_wp_l, pwrb, lid_open and key* pins
+ at the chip inputs.
+ - Verify that SYSRST ctrl correctly loops them back to the chip outputs.
+ - Write the pin_allowed_ctl register to allow some of the pins to be overridden with
+ either 0 or 1 or both.
+ - Write the pin_out_ctl register to enable the override on some of the pins.
+ - Write the pin_out_value register to set known values on those pins.
+ - Verify that at the chip outputs, pins on which override should be active is
+ reflecting the overridden values. All others should reflect the values driven on chip
+ inputs.
+ - Via assertion checks (or equivalent) verify that the transitions at the inputs
+ immediately reflect at the outputs, if not intercepted / debounced by sysrst_ctrl.
+ '''
+ stage: V2
+ tests: ["chip_sw_sysrst_ctrl_outputs"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_in_irq
+ desc: '''Verify the SYSRST ctrl can detect an input combination to signal an interrupt.
+
+ - Program a specific combination of transitions on pwrb, key*, ac_present and ec_reset_l
+ pins to trigger an interrupt by writing to key_intr_ctl register.
+ - Program the key_intr_debounce_ctl register to debounce an appropriate time.
+ - Enable the interrupt at SYSRST ctrl as well as at the PLIC.
+ - Create glitches only for some time less than detection time and check that there is no
+ - interrupt triggered.
+ - Glitch the inputs at the chip IOs before stabilizing on the programmed transitions.
+ - SW services the interrupt when triggered, verifies the pin input value and
+ key_intr_status for correctness and clears the interrupt status.
+ - Verify separately, each key combination sufccessfully generates an interrupt.
+ '''
+ stage: V2
+ tests: ["chip_sw_sysrst_ctrl_in_irq"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_sleep_wakeup
+ desc: '''Verify the SYSRST ctrl can wake up the chip from deep sleep.
+
+ - Read the reset cause register in rstmgr to confirm we are in POR reset phase.
+ - Program one of the com_sel_ctl_* CSRs to choose a set of inputs to be detected as
+ a low power wakeup signal for the pwrmgr.
+ - Program the associated detection timer.
+ - Program the detection outcome CSR's (com_out_ctl) interrupt bit to 1.
+ - Program the pwrmgr to put the chip in deep sleep state and wake up on chip wake up
+ event.
+ - Issue a WFI to bring the chip in low power state.
+ - After the chip has entered low power mode, set the SYSRST ctrl inputs at the chip IOs
+ to the programmed combination for the duration of the detection timer.
+ - Read the reset cause register to confirm wake up from low power exit phase.
+ - Read the pwrmgr wake up status register to confirm chip wake up.
+ - Read the pin input value and the combo_intr_status CSRs to verify the correct
+ combination on inputs woke up the chip from sleep.
+ '''
+ stage: V2
+ tests: ["chip_sw_sysrst_ctrl_reset"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_reset
+ desc: '''Verify the SYSRST ctrl can reset the chip from normal state.
+
+ - Read the reset cause register in rstmgr to confirm we are in POR reset phase.
+ - Program one of the com_sel_ctl_* CSRs to choose a set of inputs to be detected as
+ the chip reset signal.
+ - Program the associated detection timer.
+ - Program the detection outcome CSR's (com_out_ctl) chip reset bit to 1.
+ - After some time, set the SYSRST ctrl inputs at the chip IOs to the programmed
+ combination for the duration of the detection timer.
+ - The pwrmgr will power cycle the chip once it receives the chip reset input.
+ - Check that ec_rst_l and flash_wp_l (on pads IOR8 and IOR9) are asserted right after
+ the pwrmgr has power cycled the system.
+ - Read the reset cause register after boot up to confirm peripheral reset phase.
+ - Read the pwrmgr reset status register to confirm chip reset.
+ - Read the com_sel_ctl_* CSR in SYSRST ctrl we programmed earlier - it should have been
+ reset.
+ '''
+ stage: V2
+ tests: ["chip_sw_sysrst_ctrl_reset"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_sleep_reset
+ desc: '''Verify the SYSRST ctrl can reset the chip from deep sleep.
+
+ - Read the reset cause register in rstmgr to confirm we are in POR reset phase.
+ - Program one of the com_sel_ctl_* CSRs to choose a set of inputs to be detected as
+ the chip reset signal.
+ - Program the associated detection timer.
+ - Program the detection outcome CSR's (com_out_ctl) chip reset bit to 1.
+ - Program the pwrmgr to put the chip in deep sleep state and allow it to be reset by the
+ chip reset bit.
+ - Issue a WFI to bring the chip in low power state.
+ - After the chip has entered low power mode, set the SYSRST ctrl inputs at the chip IOs
+ to the programmed combination for the duration of the detection timer.
+ - The pwrmgr will power cycle the chip from the deep sleep state once it receives the
+ chip reset input.
+ - Read the reset cause register after boot up to confirm peripheral reset phase.
+ - Read the pwrmgr reset status register to confirm chip reset.
+ - Read the com_sel_ctl_* CSR in SYSRST ctrl we programmed earlier - it should have been
+ reset.
+ '''
+ stage: V2
+ tests: ["chip_sw_sysrst_ctrl_reset"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_ec_rst_l
+ desc: '''Verify that the ec_rst_l stays asserted on power-on-reset until SW can control it.
+
+ - Verify that ec_rst_l stays asserted as the chip is brought out of reset.
+ - Verify that the pin continues to remain low until SW is alive.
+ - Have the SW write to pin_allowed|out_ctrl CSRs to control the ec_rst_l value and
+ verify the value at the chip output.
+ - Optionally, also verify ec_rst_l pulse stretching by setting the ec_rst_ctl register
+ with a suitable pulse width.
+ '''
+ stage: V2
+ tests: ["chip_sw_sysrst_ctrl_ec_rst_l"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_flash_wp_l
+ desc: '''Verify that the flash_wp_l stays asserted on power-on-reset until SW can control it.
+
+ - Exactly the same as chip_sysrst_ctrl_ec_rst_l, but covers the flash_wp_l pin.
+ '''
+ stage: V2
+ tests: ["chip_sw_sysrst_ctrl_ec_rst_l"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_ulp_z3_wakeup
+ desc: '''Verify the z3_wakeup signaling.
+
+ - Start off with ac_present = 0, lid_open = 0 and pwrb = 0 at the chip inputs.
+ - Program the ulp_ac|lid|pwrb_debounce_ctl registers to debounce these inputs for an
+ appropriate time.
+ - Enable the ULP wakeup feature by writing to the ulp_ctl register.
+ - Read the ulp_wakeup register and verify that no wakeup event is detected, after some
+ amount of delay.
+ - Glitch the lid_open input at the chip IOs before stabilizing on value 1.
+ - Read the ulp_wakeup register to verify that the wakeup event is detected this time.
+ - Verify that the z3_wakeup output at the chip IOs is reflecting the value of 1.
+ '''
+ stage: V2
+ tests: [
+ "chip_sw_adc_ctrl_sleep_debug_cable_wakeup",
+ "chip_sw_sysrst_ctrl_ulp_z3_wakeup"
+ ]
+ }
+
+ // ADC_CTRL (pre-verified IP) integration tests:
+ {
+ name: chip_sw_adc_ctrl_debug_cable_irq
+ desc: '''Verify that the ADC correctly detects the voltage level programmed for each channel.
+
+ - Program both ADC channels to detect mutually exclusive range of voltages. Setting only
+ one filter CSR is sufficient.
+ - Program the ADC intr ctrl CSR to detect the selected filter on both channels.
+ Enable the debug cable interrupt at ADC ctrl as well as PLIC.
+ - Enable the ADC ctrl to run with defaults in normal mode (depending on simulation
+ runtime).
+ - Verify through assertion checks, the ADC with AST stays powered down periodically in
+ slow scan mode.
+ - After some time, force the ADC output of AST to be a value within the programmed range
+ for each channel. Glitch it out of range for some time before stabilizing to ensure
+ that debouce logic works.
+ - Service the debug cable irq. Read the intr status register to verify that the selected
+ filter caused the interrupt to fire. Read the ADC channel value register to verify the
+ correctness of the detected value that was forced in the AST for each channel.
+ '''
+ stage: V2
+ tests: ["chip_sw_adc_ctrl_sleep_debug_cable_wakeup"]
+ }
+ {
+ name: chip_sw_adc_ctrl_sleep_debug_cable_wakeup
+ desc: '''Verify that in deep sleep, ADC ctrl can signal the ADC within the AST to power down.
+
+ - Read the reset cause register in rstmgr to confirm we are in POR reset phase.
+ - Follow the same steps as chip_adc_ctrl_debug_cable_irq, but instead of programming the
+ selected filter to interrupt, program it to wake up the chip from sleep.
+ - Program the pwrmgr to put the chip in deep sleep state and wake up on debug cable
+ detection.
+ - Issue a WFI to bring the chip in low power state.
+ - After some time, force the ADC output of AST to be a value within the programmed
+ filter range. That should cause the pwrmgr to wake up.
+ - Read the reset cause register to confirm wake up from low power exit phase.
+ - Read the pwrmgr wake up status register to confirm wake up was due to debug cable
+ detection.
+ - Read the ADC channel value register to verify the correctness of the detected value
+ that was forced in the AST.
+ - Repeat for both ADC channels.
+ '''
+ stage: V2
+ tests: ["chip_sw_adc_ctrl_sleep_debug_cable_wakeup"]
+ }
+
+ // SMC_CTRL (pre-verified IP) integration tests:
+ {
+ name: chip_sw_smc_ctrl
+ desc: '''Verify that the smc_ctrl can enable smc core to boot.
+
+ - Program the smc_ctrl register to enable SMC core to boot.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_ctrl_test"]
+ }
+
+ // CAM_CTRL (pre-verified IP) integration tests:
+ {
+ name: chip_sw_cam_ctrl
+ desc: '''Verify that the cam_ctrl can control himax cam sensor.
+
+ - Program the cam_ctrl to toggle internal registers and verify the result
+ - Program the cam_ctrl to driver the trigger output to sensor.
+ - Program testbench to generate interrupt from cam_sensor, to verify if cam_ctrl
+ generate interrupt to host's PLIC (SMC core).
+ - TO-DO: test to be added.
+ '''
+ stage: V2
+ tests: ["chip_sw_cam_ctrl_test"]
+ }
+ // Mailbox (pre-verified IP) integration tests:
+ {
+ name: chip_sw_tlul_mailbox_test
+ desc: '''Verify that the tlul_mailbox can send info between security core and SMC core.
+
+ - Security core SW write data into tlul_mailbox till it exceed threshould, and verify if SMC
+ core receive the interrupt.
+ - SMC core side read out the data from tlul_mailbox, and make sure the interrupt un-asserted.
+ - SMC core SW write data into tlul_mailbox till it exceed threshould, and verify if Security
+ core receive the interrupt.
+ - Security core read out the data from tlul_mailbox, and make sure the interrupt un-asserted.
+ -
+ - TO-DO: test to be added.
+ '''
+ stage: V2
+ tests: []
+ }
+
+ // Mailbox (pre-verified IP) integration tests:
+ {
+ name: chip_sw_smc_tlul_mailbox_test
+ desc: '''Verify that the tlul_mailbox can send info between security core and SMC core.
+ - Security core SW write data into tlul_mailbox till it exceed threshould, and verify if SMC
+ core receive the interrupt.
+ - SMC core side read out the data from tlul_mailbox, and make sure the interrupt un-asserted.
+ - SMC core SW write data into tlul_mailbox till it exceed threshould, and verify if Security
+ core receive the interrupt.
+ - Security core read out the data from tlul_mailbox, and make sure the interrupt un-asserted.
+ -
+ - TO-DO: test to be added.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_tlul_mailbox_test"]
+ }
+
+ // DMA integration tests:
+ {
+ name: chip_sw_dma_main_test
+ desc: '''Verify that the DMA can perform a memory to memory transaction intiated
+ by the secure core and propagate interrupts to the PLIC.
+
+ - Read DMA configuration register and verify bus interfaces are congfigured for TLUL.
+ - Configure both the reader and writer start addresses to the main SRAM and SMC SRAM
+ respectively, with arbitary offsets.
+ - Configure the reader and writer to transfer four 32 bit messages and enable their
+ interrupts.
+ - Configure the PLIC to enable the write interrupt from the DMA and set its priority.
+ - Begin the transaction, set the secure core to sleep, and check the data in the SMC
+ SRAM to verify the transction completed.
+ - Write 1 to the IP writer bit in the interrupt register to clear it and verify only
+ it was cleared.
+ '''
+ stage: V2
+ tests: ["chip_sw_dma_main_test"]
+ }
+ ///////////////////////////////////////////////////////
+ // Security Peripherals //
+ // AES, HMAC, KMAC, CSRNG, ENTROPY_SRC, KEYMGR, OTBN //
+ ///////////////////////////////////////////////////////
+
+ // AES (pre-verified IP) integration tests:
+ {
+ name: chip_sw_aes_enc
+ desc: '''Verify the AES operation.
+
+ Write a 32-byte key and a 16-byte plain text to the AES registers and trigger the AES
+ computation to start. Wait for the AES operation to complete by polling the status
+ register. Check the digest registers for correctness against the expected digest value.
+ '''
+ stage: V2
+ tests: ["chip_sw_aes_enc",
+ "chip_sw_aes_enc_jitter_en"]
+ }
+ {
+ name: chip_sw_aes_entropy
+ desc: '''Verify the AES entropy input used by the internal PRNGs.
+
+ - Write the initial key share, IV and data in CSRs (known combinations).
+ - Configure the entropy_src to generate entropy in LFSR mode.
+ - Write the PRNG_RESEED bit to reseed the internal state of the PRNG.
+ - Poll the status idle bit to ensure reseed operation is complete.
+ - Trigger the AES operation to run and wait for it to complete.
+ - Check the digest against the expected value.
+ - Write the KEY_IV_DATA_IN_CLEAR and DATA_OUT_CLEAR trigger bits to 1 and wait for it to
+ complete by polling the status idle bit.
+ - Read back the data out CSRs - they should all read garbage values.
+ - Assertion check verifies that the IV are also garbage, i.e. different from the
+ originally written values.
+ '''
+ stage: V2
+ tests: ["chip_sw_aes_entropy"]
+ }
+ {
+ name: chip_sw_aes_idle
+ desc: '''Verify AES idle signaling to clkmgr.
+
+ - Write the AES clk hint to 0 within clkmgr to indicate AES clk can be gated and
+ verify that the AES clk hint status within clkmgr reads 0 (AES is disabled).
+ - Write the AES clk hint to 1 within clkmgr to indicate AES clk can be enabled.
+ - Initiate an AES operation with a known key, plain text and digest, write AES clk
+ hint to 0 and verify that the AES clk hint status within clkmgr now reads 1 (AES
+ is enabled), before the AES operation is complete.
+ - After the AES operation is complete verify that the AES clk hint status within
+ clkmgr now reads 0 again (AES is disabled).
+ - Write the AES clk hint to 1, read and check the AES output for correctness.
+ '''
+ stage: V2
+ tests: ["chip_sw_aes_idle"]
+ }
+ {
+ name: chip_sw_aes_sideload
+ desc: '''Verify the AES sideload mechanism.
+
+ - Configure the keymgr to generate an aes key.
+ - Configure the AES to use the sideloaded key.
+ - Load the plaintext into the AES.
+ - Trigger the AES encryption and wait for it to complete.
+ - Verify that the ciphertext is different from the plaintext.
+ - Load the ciphertext into the AES.
+ - Trigger the AES decryption and wait for it to complete.
+ - Verify that the output is equal to the plain text.
+ - Clear the key in the keymgr and decrypt the ciphertext again.
+ - Verify that output is not equal to the plain text.
+ '''
+ stage: V2
+ tests: ["chip_sw_keymgr_sideload_aes"]
+ }
+ {
+ name: chip_sw_aes_masking_off
+ desc: '''Verify the AES masking off feature for ES.
+
+ - Perform known-answer test using CSRNG SW application interface.
+ - Verify CSRNG produces the deterministic seed leading to an all-zero output of the AES
+ masking PRNG.
+ - Configure EDN to perform a CSRNG instantiate followed by repeated generate and reseed
+ commands using the maximum amount of additional data and no entropy input in automatic
+ mode.
+ - Let CSRNG produce and forward to EDN the deterministic seed leading to an all-zero
+ output of the AES masking PRNG.
+ - Initialize AES and set the force_masks configuration bit.
+ - Configure an AES key of which the second share is zero.
+ - Trigger a reseed operation of the masking PRNG inside AES to load the deterministic
+ seed produced by CSRNG and distributed by EDN.
+ - Verify that the masking PRNG outputs an all-zero vector.
+ - Encrypt a message of multiple blocks using AES.
+ - Verify that the second share of the initial, intermediate and output state is zero.
+ - Verify that the second share of the SubBytes input and output is zero.
+ - Verify that the produced cipher text is correct.
+ '''
+ stage: V2S
+ tests: ["chip_sw_aes_masking_off"]
+ }
+
+ // HMAC (pre-verified IP) integration tests:
+ {
+ name: chip_sw_hmac_enc
+ desc: '''Verify HMAC operation.
+
+ SW test verifies an HMAC operation with a known key, plain text and digest (pick one of
+ the NIST vectors). SW test verifies the digest against the pre-computed value. Verify
+ the HMAC done and FIFO empty interrupts as a part of this test.
+ '''
+ stage: V2
+ tests: ["chip_sw_hmac_enc",
+ "chip_sw_hmac_enc_jitter_en"]
+ }
+ {
+ name: chip_sw_hmac_idle
+ desc: '''Verify the HMAC clk idle signal to clkmgr.
+
+ - Write the HMAC clk hint to 0 within clkmgr to indicate HMAC clk can be gated and
+ verify that the HMAC clk hint status within clkmgr reads 0 (HMAC is disabled).
+ - Write the HMAC clk hint to 1 within clkmgr to indicate HMAC clk can be enabled.
+ Verify that the HMAC clk hint status within clkmgr reads 1 (HMAC is enabled).
+ - Initiate an HMAC operation with a known key, plain text and digest.
+ Write HMAC clock hint to 0 and verify the HMAC clk hint status within clkmgr reads 1
+ (HMAC is enabled), before the HMAC operation is complete.
+ - After the HMAC operation is complete, verify the digest for correctness. Verify that
+ the HMAC clk hint status within clkmgr now reads 0 again (HMAC is disabled).
+ - This process is repeated for two hmac operations needed to verify the resulting hmac
+ digest.
+ '''
+ stage: V2
+ tests: ["chip_sw_hmac_enc_idle"]
+ }
+
+ // KMAC pre-verified IP) integration tests:
+ {
+ name: chip_sw_kmac_enc
+ desc: '''Verify the SHA3 operation.
+
+ SW test verifies SHA3 operation with a known key, plain text and digest (pick one of
+ the NIST vectors). SW validates the reception of kmac done and fifo empty interrupts.
+ '''
+ stage: V2
+ tests: ["chip_sw_kmac_mode_cshake", "chip_sw_kmac_mode_kmac",
+ "chip_sw_kmac_mode_kmac_jitter_en"]
+ }
+ {
+ name: chip_sw_kmac_app_keymgr
+ desc: '''Verify the keymgr interface to KMAC.
+
+ - Configure the keymgr to start sending known message data to the KMAC.
+ - Keymgr should transmit a sideloaded key to the KMAC as well.
+ - KMAC should finish hashing successfully (not visible to SW) and return digest to
+ keymgr.
+ - This digest is compared against the known digest value for correctness.
+ - Verify that the keymgr has received valid output from the KMAC.
+
+ X-ref'ed with keymgr test.
+ '''
+ stage: V2
+ tests: ["chip_sw_keymgr_key_derivation"]
+ }
+ {
+ name: chip_sw_kmac_app_lc
+ desc: '''Verify the LC interface to KMAC.
+
+ - Configure the LC_CTRL to start a token hash using KMAC interface.
+ - KMAC should finish hashing successfully (not visible to SW) and return digest to
+ LC_CTRL.
+
+ X-ref'ed with LC_CTRL test/env.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_transition"]
+ }
+ {
+ name: chip_sw_kmac_app_rom
+ desc: '''Verify the ROM interface to KMAC.
+
+ - Backdoor initialize ROM memory immediately out of reset.
+ - ROM will send message to the KMAC containing its memory contents,
+ - KMAC will hash and return the digest to the ROM.
+ - ROM will compare received digest against its first 8 logical memory lines for
+ correctness.
+
+ X-ref'ed with ROM_CTRL test/env.
+ '''
+ stage: V2
+ tests: ["chip_sw_kmac_app_rom"]
+ }
+ {
+ name: chip_sw_kmac_entropy
+ desc: '''Verify the EDN interface to KMAC.
+
+ Requires `EnMasking` parameter to be enabled.
+ SW randomly configures the KMAC in any hashing mode/strength, and enable EDN mode.
+ Randomly enable/disable the `entropy_refresh`.
+ Randomly configure `wait_timer` values (zero for disable, non-zero for timer expire).
+ - Program `wait_timer` to a small value.
+ Check if EDN timeout error occurs after issuing the hashing op.
+ - Adjust `wait_timer` greater than expected EDN latency (with correct `prescaler`
+ too). Then check if Digest is correct.
+ KMAC should send EDN request after `entropy_ready` is set.
+ KMAC also should send out another request to EDN when either:
+ - kmac hash counter hits the configured threshold (assuming it is non-zero)
+ - Hash count exceeds the threshold.
+ SW verifies that KMAC produces the correct digest value.
+
+ TODO: This is pending security review discussion. It is unclear if this feature will be
+ implemented.
+
+ X-ref'ed with EDN test/env.
+ '''
+ stage: V2
+ tests: ["chip_sw_kmac_entropy"]
+ }
+ {
+ name: chip_sw_kmac_idle
+ desc: '''Verify the KMAC idle signaling to clkmgr.
+
+ - Write the KMAC clk hint to 0 within clkmgr to indicate KMAC clk can be gated and
+ verify that the KMAC clk hint status within clkmgr reads 0 (KMAC is disabled).
+ - Write the KMAC clk hint to 1 within clkmgr to indicate KMAC clk can be enabled.
+ Verify that the KMAC clk hint status within clkmgr reads 1 (KMAC is enabled).
+ - Initiate a KMAC operation with a known key, plain text and digest.
+ Write KMAC clock hint to 0 and verify the KMAC clk hint status within clkmgr reads 1
+ (KMAC is enabled), before the KMAC operation is complete.
+ - After the KMAC operation is complete, verify the digest for correctness. Verify that
+ the KMAC clk hint status within clkmgr now reads 0 again (KMAC is disabled).
+ '''
+ stage: V2
+ tests: ["chip_sw_kmac_idle"]
+ }
+
+ // ENTROPY_SRC (pre-verified IP) integration tests:
+ {
+ name: chip_sw_entropy_src_ast_rng_req
+ //TODO(#13460): A dv enginner should add an assertion to check the connectivity for this test.
+ desc: '''Verify the RNG req to ast.
+
+ - Program the entropy src in normal RNG mode.
+ - Route the entropy data received from RNG to the FIFO.
+ - Verify that the FIFO depth is non-zero via SW - indicating the reception of data over
+ the AST RNG interface.
+ - Verify the correctness of the received data with assertion based connectivity checks.
+ '''
+ stage: V2
+ tests: ["chip_sw_entropy_src_ast_rng_req"]
+ }
+ {
+ name: chip_sw_entropy_src_csrng
+ desc: '''Verify the transfer of entropy bits to CSRNG.
+
+ Verify the entropy valid interrupt.
+ At the CSRNG, validate the reception of entropy req interrupt.
+
+ - Disable edn0, edn1, csrng and entropy_src, as these are enabled by the test ROM.
+ - Enable entropy_src in fips mode routing data to csrng.
+ - Enable csrng and enable the entropy request interrupt.
+ - Issue csrng instantiate and reseed commands. Check that for each csrng command,
+ there is a corresponding entropy request interrupt.
+ - Generate output and ensure the data output is valid, and that csrng is not reporting
+ any errors.
+ - Issue instantiate and reseed commands from edn0 and edn1. Check that for each
+ command, there is a corresponding entropy request interrupt.
+ '''
+ stage: V2
+ tests: ["chip_sw_entropy_src_csrng"]
+ }
+ {
+ name: chip_sw_entropy_src_cs_aes_halt
+ desc: '''Verify the `entropy_src`'s aes halt handshake with CSRNG.
+
+ - Through one of the application interfaces of CSRNG, issue a reseed command. This can
+ be done via a hardware peripheral requesting entropy via EDN.
+ - Through the SW application interface, issue a generate command.
+ - While the CSRNG is performing the generate operation, issue another reseed command
+ via the first application interface. Verify via backdoor probes, the SHA3 in the
+ entropy_src module is triggered at the same time the AES engine in CSRNG is
+ performing an operation.
+ - The second reseed command should trigger the entropy_src to request that the CSRNG
+ halts the AES engine until entropy is available. Verify via assertion checks, the halt
+ request successfully completed. Also verify that the AES engine is indeed paused
+ during this time.
+
+ Note: There may be existing tests that already create this scenario. It should be
+ sufficient to augment those tests with the backdoor / assertion checks.
+ '''
+ stage: V3
+ tests: []
+ }
+ {
+ name: chip_sw_entropy_src_fuse_en_fw_read
+ desc: '''Verify the fuse input entropy_src.
+
+ - Initialize the OTP with the fuse that controls whether the SW can read the entropy src
+ enabled.
+ - Read the OTP and verify that the fuse is enabled.
+ - Read the entropy_data_fifo via SW and verify that it reads valid values.
+ - Reset the chip, but this time, initialize the OTP with with the fuse disabled.
+ - Read the OTP and verify that fuse is disabled.
+ - Read the internal state via SW and verify that the entropy valid bit is zero.
+ '''
+ stage: V2
+ tests: ["chip_sw_entropy_src_fuse_en_fw_read_test"]
+ }
+ {
+ name: chip_sw_entropy_src_known_answer_tests
+ desc: '''Verify our ability to run known-answer tests in SW.
+
+ - Configure the device in firmware-bypass mode.
+ - Feed NIST test-defined entropy sequences into the conditioner
+ - Read the entropy_data_fifo via SW; verify that it reads the expected values.
+ '''
+ stage: V2
+ tests: ["chip_sw_entropy_src_kat_test"]
+ }
+
+ // CSRNG (pre-verified IP) integration tests:
+ {
+ name: chip_sw_csrng_edn_cmd
+ desc: '''Verify incoming command interface from EDN.
+
+ - Have each EDN instance issue an instantiate, reseed and generate command to CSRNG.
+ - On each command done, verify the reception of edn cmd req done interrupt.
+ - Run OTBN randomness test to test the output from EDN0 and EDN1.
+ - Check the data returned to EDN via connectivity assertion checks.
+ '''
+ stage: V2
+ tests: ["chip_sw_entropy_src_csrng"]
+ }
+ {
+ name: chip_sw_csrng_fuse_en_sw_app_read
+ desc: '''Verify the fuse input to CSRNG.
+
+ - Initialize the OTP with the fuse that control whether the SW can read the CSRNG state
+ enabled.
+ - Issue an instantiate command to request entropy.
+ - Verify that SW can read the internal state values.
+ - Reset the chip and repeat the steps above, but this time, initialized the OTP with
+ fuse disabled.
+ - Verify that the SW reads back all zeros when reading the internal state values.
+ '''
+ stage: V2
+ tests: ["chip_sw_csrng_fuse_en_sw_app_read_test"]
+ }
+ {
+ name: chip_sw_csrng_lc_hw_debug_en
+ desc: '''Verify the effect of LC HW debug enable on CSRNG.
+
+ lc_hw_debug_en is used to diversify the csrng seed.
+ - Configure entropy_src into bypassing the conditioner and directly inject known
+ entropy.
+ - Instantiate CSRNG with the known entropy while in TEST state (hw_debug_en = 1).
+ - Retrieve entropy from csrng and save it in flash and reset the system.
+ - Run the process again and ensure the exact same result can be reproduced (similar to
+ KAT).
+ - Advance the device to PROD or DEV state.
+ - Again configure entropy_src to bypass the conditioner and use direct injection.
+ - Instantiate CSRNG with the same fixed seed and fetch entropy again while in the NEW
+ state.
+ - The newly fetched entropy and the old entropy stored in flash should not match.
+ '''
+ stage: V2
+ tests: ["chip_sw_csrng_lc_hw_debug_en_test"]
+ }
+ {
+ name: chip_sw_csrng_known_answer_tests
+ desc: '''Verify our ability to run known-answer tests in SW.
+
+ - Configure the software instance with the expected seed (as per
+ the NIST-specified test for CTR_DRBG operation). Compare the
+ DRBG internal K and V state against the test vector expected
+ values.
+ - Perform generate operations as required by the test vector.
+ - Compare the results to test expectations.
+ '''
+ stage: V2
+ tests: ["chip_sw_csrng_kat_test"]
+ }
+ {
+ name: chip_sw_csrng_edn_error
+ desc: '''Verify the outcome of an error response generated by CSRNG when processing an EDN
+ request.
+
+ - Inject a fault in CSRNG while it is processing a request from EDN so that it returns
+ an error response to EDN.
+ - TODO(#16516): How does EDN respond to the error?
+ '''
+ stage: V3
+ tests: []
+ }
+
+ // EDN (pre-verified IP) integration tests:
+ {
+ name: chip_sw_edn_entropy_reqs
+ desc: '''Verify the entropy requests from all peripherals.
+
+ Verify that there are no misconnects between each peripheral requesting entropy.
+ TODO: system level scenario: have all entropy sources request entropy in the same test
+ one after to show boot to post boot load, cycling all entropy blocks off and on again.
+ Ensure there are no deadlocks and everything works as expected.
+ X'ref'ed with each IP test that requsts entropy from EDN.
+ '''
+ stage: V2
+ tests: ["chip_sw_edn_entropy_reqs",
+ "chip_sw_csrng_edn_concurrency"]
+ }
+
+ // KEYMGR (pre-verified IP) integration tests:
+ {
+ name: chip_sw_keymgr_key_derivation
+ desc: '''Verify the keymgr advances to all states and generate identity / SW output.
+
+ - In the SW test, write fixed value to OTP for root_key and write creator and owner
+ seeds in flash. And then roboot the chip.
+ - In the SV sequence, backdoor read Device ID and ROM digest through CSRs.
+ - For HardwareRevisionSecret, use the constant values in design.
+ - Configure the keymgr and advance to `CreatorRootKey` and `OwnerIntermediateKey`.
+ - Check keymgr internal keys after advance operations.
+ - Generate identity / SW output for the Sealing CDI.
+ - No need to test the Attestation CDI in chip-level as the only difference is to
+ use another set of CSR values, and the rest of inputs are the same as the Sealing
+ CDI.
+ - KMAC should finish hashing successfully (not visible to SW) and return digest to
+ keymgr.
+ - Read keymgr CSRs `SW_SHARE*` and verify the return values.
+ - Advance to `Disabled` and verify keymgr enters the state successfully.
+
+ - For each operation, wait for the interrupt `op_done` to be triggered and check CSR
+ `op_status` is `DONE_SUCCESS`.
+
+ - Note: there are 3 ways of calculating the expected digest for comparison. Any of them
+ is acceptable.
+ - Use SW to calculate that, and it will also exercise the Ibex.
+ - SW sends all the keys through CSRs to KMAC to generate the degist data.
+ - DV calls C functions to generate and backdoor load to a specific memory location
+ for SW. (Adpot this approach.)
+
+ X-ref'ed with kmac test.
+ '''
+ stage: V2
+ tests: ["chip_sw_keymgr_key_derivation", "chip_sw_keymgr_key_derivation_jitter_en"]
+ }
+ {
+ name: chip_sw_keymgr_sideload_kmac
+ desc: '''Verify the keymgr sideload interface to KMAC.
+
+ - Configure the keymgr and advance to the `OwnerIntKey` state.
+ - Request keymgr to generate hw key for KMAC sideload key slot.
+ - Request KMAC operation with sideload key configuration.
+ - Verify the digest for correctness (should match the DV-side result).
+ - Clear keymer's KMAC sideload key slot.
+ - Request KMAC operation with sideload key configuration.
+ - Verify the digest value has changed.
+ - Request keymgr to derive the same key for the KMAC sideload key slot.
+ - Request KMAC operation with sideload key configuration.
+ - Verify the digest for correctness (should match the DV-side result again).
+
+ X-ref'ed with chip_kmac_app_keymgr test.
+ '''
+ stage: V2
+ tests: ["chip_sw_keymgr_sideload_kmac"]
+ }
+ {
+ name: chip_sw_keymgr_sideload_aes
+ desc: '''Verify the keymgr sideload interface to AES.
+
+ Same as `chip_keymgr_sideload_kmac`, except, sideload to AES.
+ '''
+ stage: V2
+ tests: ["chip_sw_keymgr_sideload_aes"]
+ }
+ {
+ name: chip_sw_keymgr_sideload_otbn
+ desc: '''Verify the keymgr sideload interface to OTBN.
+
+ Load OTBN binary image, the rest is similar to `chip_keymgr_sideload_kmac`, except
+ sideloading to otbn.
+
+ Clear the sideload key once done.
+ '''
+ stage: V2
+ tests: ["chip_sw_keymgr_sideload_otbn"]
+ }
+ {
+ name: chip_sw_keymgr_sideload_kmac_error
+ desc: '''
+ Verify the effect of KMAC returning an error during a keymgr operation.
+
+ - Configure keymgr to enter any of the 3 working states.
+ - Issue a keymgr operation.
+ - While the KMAC is actively computing the digest, glitch the KMAC app sparse FSM to
+ trigger a fault.
+ - Verify that KMAC returns an error signal to the keymgr via checking keymgr CSRs, when
+ the operation is done:
+ - Check `op_status` is set to `DONE_ERROR`.
+ - Check `fault_status.kmac_done` is set to 1.
+ '''
+ stage: V3
+ tests: []
+ }
+
+ // OTBN (pre-verified IP) integration tests:
+ {
+ name: chip_sw_otbn_op
+ desc: '''Verify an OTBN operation.
+
+ - SW test directs the OTBN engine to perform an ECDSA operation.
+ - SW validates the reception of the otbn done interrupt once the operation is complete.
+ - SW verifies the correctness of the result with the expected value which is
+ pre-computed using a reference model.
+ '''
+ stage: V2
+ tests: ["chip_sw_otbn_ecdsa_op_irq",
+ "chip_sw_otbn_ecdsa_op_irq_jitter_en"]
+ }
+ {
+ name: chip_sw_otbn_rnd_entropy
+ desc: '''Verify OTBN can fetch RND numbers from the entropy src.
+
+ - SW initializes the entropy subsystem to generate randomness.
+ - SW loads an OTBN app that executes instructions to read the RND bits.
+ - The OTBN app ensures that the values when read consequtively do not match, and its not
+ all 0s or all 1s, as a basic measure to ensure that the entropy subsystem is returning
+ some data.
+ '''
+ stage: V2
+ tests: ["chip_sw_otbn_randomness"]
+ }
+ {
+ name: chip_sw_otbn_urnd_entropy
+ desc: '''Verify OTBN can fetch URND numbers from the entropy src.
+
+ - Similar to chip_otbn_rnd_entropy, but verifies the URND bits.
+ '''
+ stage: V2
+ tests: ["chip_sw_otbn_randomness"]
+ }
+ {
+ name: chip_sw_otbn_idle
+ desc: '''Verify the OTBN idle signal to clkmgr.
+
+ - Write the OTBN clk hint to 0 within clkmgr to indicate OTBN clk can be gated
+ and verify that the OTBN clk hint status within clkmgr reads 0 (OTBN is disabled).
+ - Write the OTBN clk hint to 1 within clkmgr to indicate OTBN clk can be enabled.
+ Verify that the OTBN clk hint status within clkmgr reads 1 (OTBN is enabled).
+ - Start an OTBN operation, write the OTBN clk hint to 0 within clkmgr and verify that
+ the OTBN clk hint status within clkmgr reads 1 (OTBN is enabled) before the
+ OTBN operation is complete.
+ - After the OTBN operation is complete, verify that the OTBN clk hint status within
+ clkmgr now reads 0 again (OTBN is disabled).
+ - Write the OTBN clk hint to 1, read and check the OTBN output for correctness.
+ '''
+ stage: V2
+ tests: ["chip_sw_otbn_randomness"]
+ }
+ {
+ name: chip_sw_otbn_mem_scramble
+ desc: '''Verify the OTBN can receive keys from the OTP to scramble the OTBN imem and dmem.
+
+ - Initialize the entropy_src subsystem to enable OTP_CTRL fetch random data (already
+ done by the test_rom startup code).
+ - Extract random address offsets from RV_CORE_IBEX_RND_DATA.
+ - Wait for OTBN to be idle.
+ - Write random address offsets in OTBN imem and dmem.
+ - Read back the written address offsets and compare against expected values. All values
+ must match, no integrity errors must be triggered.
+ - Have OTBN fetch new keys and nonces from the OTP_CTRL.
+ - Wait for OTBN to be idle.
+ - Read back the written address offsets. Most reads should trigger integrity errors. It
+ is possible that after re-scrambling the integrity bits are still valid. But this is
+ expected to happen rarely. If the number of observed integrity errors is below a
+ chosen threshold, the test fails.
+ - Verify the validity of EDN's output to OTP_CTRL via assertions
+ (unique, non-zero data).
+ '''
+ stage: V2
+ tests: ["chip_sw_otbn_mem_scramble"]
+ }
+
+ /////////////////////////////////////////////////////
+ // Memory & Controllers //
+ // ROM_CTRL, RAM, FLASH, FLASH_CTRL, OTP, OTP_CTRL //
+ /////////////////////////////////////////////////////
+
+ // ROM_CTRL (pre-verified IP) integration tests:
+ {
+ name: chip_sw_rom_access
+ desc: '''Verify that the CPU can access the rom contents.
+
+ - Verify that the CPU can fetch instructions from the ROM.
+ '''
+ stage: V2
+ tests: ["chip_sw_rom_ctrl_integrity_check"]
+ }
+ {
+ name: chip_sw_rom_ctrl_integrity_check
+ desc: '''Verify that the ROM ctrl performs the integrity check of the ROM on power up.
+
+ - In non-PROD LC state, the computed digest does not have to match the top 8 words in
+ the ROM. Verify that we can successfully power up the chip in this case.
+ - In PROD LC state, verify that the pwrmgr does not fully power up if the computed
+ digest does not match the top 8 words of the ROM.
+ '''
+ stage: V2
+ tests: ["chip_sw_rom_ctrl_integrity_check"]
+ }
+ {
+ name: chip_sw_rom_ctrl_kmac_error
+ desc: '''
+ Verify the effect of KMAC reporting an error during ROM digest computation.
+
+ - Backdoor load a valid test ROM image and bring the DUT out of reset.
+ - During the ROM checker pwrmgr FSM state, while the ROM controller is actively sending
+ data to KMAC for the digest computation, glitch the KMAC app sparse FSM to trigger a
+ fault.
+ - Verify that KMAC returns an error signal to the ROM controller.
+ - Verify that the ROM controller itself transitions to invalid state and the chip is
+ effectively dead.
+ '''
+ stage: V3
+ tests: []
+ }
+
+ // SRAM (pre-verified IP) integration tests:
+ {
+ name: chip_sw_sram_scrambled_access
+ desc: '''Verify scrambled memory accesses to both main and retention SRAMs.
+
+ - Initialize the entropy_src subsystem to enable OTP_CTRL fetch random data (already
+ done by the test_rom startup code).
+ - Trigger both SRAMs to fetch a new key and nonce from the OTP_CTRL
+ - Drive the CPU to perform random accesses to both RAMs and verify these operations
+ complete successfully by using the backdoor interface
+ - Fetch a new key from the OTP_CTRL and ensure that the previous contents cannot be
+ read anymore.
+ - Verify the validity of EDN's output to OTP_CTRL via assertions
+ (unique, non-zero data).
+ '''
+ stage: V2
+ tests: ["chip_sw_sram_ctrl_scrambled_access",
+ "chip_sw_sram_ctrl_scrambled_access_jitter_en"]
+ }
+ {
+ name: chip_sw_sleep_sram_ret_contents
+ desc: '''Verify that the data within the retention SRAM survives low power entry-exit and reset.
+
+ Ensure that the data within the retention SRAM survives as described in this table.
+ | Mode | Scrambled | Data Preserved |
+ |:----------------------------:|:---------:|:--------------:|
+ | Normal sleep | No | Yes |
+ | Deep sleep | No | Yes |
+ | Reset due to a reset request | No | Yes |
+ | Normal sleep | Yes | Yes |
+ | Deep sleep | Yes | Yes |
+ | Reset due to a reset request | Yes | No |
+ '''
+ stage: V2
+ tests: ["chip_sw_sleep_sram_ret_contents"]
+ }
+ {
+ name: chip_sw_sram_execution
+ desc: '''Verify that CPU can fetch instructions from SRAM if enabled.
+
+ - Create the following combinations of 8 scenarios:
+ - The fetch enable bit in the HW_CFG partition of OTP controller set and not set.
+ - A life cycle state that enables (TEST_UNLOCKED, DEV or RMA) and disables (PROD)
+ hardware debug.
+ - The execution CSR programmed to be enabled and disabled.
+
+ - For both, main and the retention SRAM in each of these 8 scenarios:
+ - Load instruction data into the SRAMs.
+ - If the instruction execution is enabled, verify that the CPU can fetch and execute
+ the instruction from the SRAM correctly.
+ - If the instruction execution is not enabled, verify that the SRAM throws an error
+ response via an exception handler.
+
+ The following table indicates in which of these scenarios should the instruction
+ execution be enabled, for both, main and the retention SRAM instances.
+
+ | OTP HW_CFG[IFETCH] | HW_DEBUG_EN via LC state | EXEC CSR | MAIN SRAM | RET SRAM |
+ |:------------------:|:------------------------:|:--------:|:---------:|:--------:|
+ | 0 | 0 | 0 | disabled | disabled |
+ | 0 | 0 | 1 | disabled | disabled |
+ | 0 | 1 | 0 | enabled | disabled |
+ | 0 | 1 | 1 | enabled | disabled |
+ | 1 | 0 | 0 | disabled | disabled |
+ | 1 | 0 | 1 | enabled | disabled |
+ | 1 | 1 | 0 | disabled | disabled |
+ | 1 | 1 | 1 | enabled | disabled |
+
+ For the retention SRAM, instruction fetch is completely disabled via design parameter.
+ '''
+ stage: V2
+ tests: ["chip_sw_sram_ctrl_execution_main"]
+ }
+ {
+ name: chip_sw_sram_lc_escalation
+ desc: '''Verify the LC escalation path to the SRAMs.
+
+ - Configure the LC_CTRL to trigger an escalation request to the SRAMs.
+ - Verify that the SRAMs stop accepting and responding to new memory requests.
+ - Reset the system to exit the terminal escalation state.
+ - Re-initialize the SRAMs and verify that they can now respond correctly to
+ any further memory requests.
+
+ X-ref with chip_sw_all_escalation_resets and chip_sw_data_integrity.
+ '''
+ stage: V2
+ tests: ["chip_sw_all_escalation_resets",
+ "chip_sw_data_integrity_escalation"]
+ }
+
+ // OTP (pre-verified IP) integration tests:
+ {
+ name: chip_otp_ctrl_init
+ desc: '''Verify the OTP ctrl initialization on chip power up.
+
+ Verify that the chip powers up correctly on POR.
+ - The pwrmgr initiates a handshake with OTP ctrl and later, with LC ctrl in subsequent
+ FSM states. Ensure that the whole power up sequence does not hang.
+ - Verify with connectivity assertion checks, the handshake signals are connected.
+ - Ensure that no interrupts or alerts are triggered.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_transition"]
+ }
+ {
+ name: chip_sw_otp_ctrl_keys
+ desc: '''Verify the proliferation of keys to security peripherals.
+
+ - Verify the correctness of keys provided to SRAM ctrl (main & ret), flash ctrl, keymgr,
+ (note that keymgr does not have handshake), OTBN and the CPU instruction cache.
+ - Ensure that the test requests a new key and verifies the previously written
+ data to an address now returns a garbage value.
+
+ X-ref'ed with the following IP tests that consume these signals:
+ - chip_sw_sram_scrambled_access
+ - chip_sw_flash_scramble
+ - chip_sw_keymgr_key_derivation
+ - chip_sw_otbn_mem_scramble
+ '''
+ stage: V2
+ tests: [// Verifies both, main and retention SRAM scrambling.
+ "chip_sw_sram_ctrl_scrambled_access",
+ "chip_sw_flash_init",
+ "chip_sw_keymgr_key_derivation",
+ "chip_sw_otbn_mem_scramble",
+ "chip_sw_rv_core_ibex_icache_invalidate"]
+ }
+ {
+ name: chip_sw_otp_ctrl_entropy
+ desc: '''Verify the entropy interface from OTP ctrl to EDN.
+
+ This is X-ref'ed with the chip_otp_ctrl_keys test, which needs to handshake with the EDN
+ to receive some entropy bits before the keys for SRAM ctrl and OTBN are computed.
+ '''
+ stage: V2
+ tests: ["chip_sw_sram_ctrl_scrambled_access",
+ "chip_sw_flash_init",
+ "chip_sw_keymgr_key_derivation",
+ "chip_sw_otbn_mem_scramble",
+ "chip_sw_rv_core_ibex_icache_invalidate"]
+ }
+ {
+ name: chip_sw_otp_ctrl_program
+ desc: '''Verify the program request from lc_ctrl.
+
+ - Verify that upon an LC state transition request, LC ctrl signals the OTP ctrl with a
+ program request.
+ - Verify that the OTP ctrl generates the LC data output correctly and is sent to the LC
+ ctrl before it is reset.
+ - Verify that the `lc_check_byp_en_i` from LC ctrl is set.
+ - Ensure that the whole operation does not raise any interrupts or alerts or errors.
+ - After reset, verify that the LC state transition completed successfully by reading the
+ LC state and LC count CSRs.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_transition"]
+ }
+ {
+ name: chip_sw_otp_ctrl_program_error
+ desc: '''Verify the otp program error.
+
+ - Initiate an illegal program request from LC ctrl to OTP ctrl by forcing the
+ `lc_otp_program_i`.
+ - Verify that the LC ctrl triggers an alert when the OTP ctrl responds back with a
+ program error.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_program_error"]
+ }
+ {
+ name: chip_sw_otp_ctrl_hw_cfg
+ desc: '''Verify the correctness of otp_hw_cfg bus in all peripherals that receive it.
+
+ Preload the OTP ctrl's `hw_cfg` partition with random data and verify that all
+ consumers of the hardware configuration bits are receiving the correct values.
+
+ Xref'ed with corresponding IP tests that receive these bits.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_otp_hw_cfg"]
+ }
+ {
+ name: chip_sw_otp_ctrl_lc_signals
+ desc: '''Verify the broadcast signals from LC ctrl.
+
+ - `lc_creator_seed_sw_rw_en_i`: verify that the SECRET2 partition is locked.
+ - `lc_seed_hw_rd_en_i`: verify that the keymgr outputs a default value when enabled.
+ - `lc_dft_en_i`: verify that the test interface within OTP ctrl is accessible.
+ - `lc_check_byp_en_i`: verify that the background check during LC ctrl state
+ programming passes when enabled.
+
+ Note that `lc_escalate_en_i` is verified via a connectivity test.
+
+ The `lc_seed_hw_rd_en_i` signal can be tested by attempting a keymgr advance operation
+ into the CreatorRootKey state, which should fail since the root key will be tied off to
+ all-zero when the SECRET2 partition is not locked in OTP.
+
+ X-ref'ed with chip_sw_lc_ctrl_broadcast test, which verifies the connectivity of the LC
+ decoded outputs to other IPs.
+ '''
+ stage: V2
+ tests: [
+ // lc_dft_en_i
+ "chip_prim_tl_access",
+ // lc_check_byp_en_i
+ "chip_sw_lc_ctrl_transition",
+ // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, also checks lc_keymgr_en_i since it uses
+ // the keymgr.
+ "chip_sw_otp_ctrl_lc_signals_test_unlocked0",
+ "chip_sw_otp_ctrl_lc_signals_dev",
+ "chip_sw_otp_ctrl_lc_signals_prod",
+ "chip_sw_otp_ctrl_lc_signals_rma",
+ ]
+ }
+ {
+ name: chip_sw_otp_prim_tl_access
+ desc: '''Verify that the SW can read / write the prim tlul interface.
+
+ - The prim tlul interface is a open source placeholder for the closed source CSRs that
+ will be implemented in a translation 'shim'.
+ - Verify that when `lc_dft_en_i` is On, this region can be read / written to by the SW.
+ When `lc_dft_en_i` is Off, accessing this region will result in a TLUL error.
+ '''
+ stage: V2
+ tests: ["chip_prim_tl_access"]
+ }
+ {
+ name: chip_sw_otp_ctrl_vendor_test_csr_access
+ desc: '''
+ Verify the vendor test control access in raw, test_*, dev, prod, and rma LC states.
+
+ - Boot the chip successively in raw, test_*, dev, prod and rma LC states.
+ - Verify that the SW is able to access the vendor test control and status registers in
+ raw, test_* and rma LC states.
+ - Verify that in dev / prod LC states, the vendor status always reads back 0s regardless
+ of what is programmed into the vendor test control register.
+ '''
+ stage: V3
+ tests: []
+ }
+
+ // FLASH (pre-verified IP) integration tests:
+ {
+ name: chip_sw_flash_init
+ desc: '''Verify that flash initialization routine works correctly.
+
+ - Initialize the flash ctrl by writing 1 to the INIT register.
+ - Poll the status register for the initialization to complete.
+ - Verify that during the init process, the flash ctrl requested keys from OTP. Verify
+ with different sets of key values programmed in OTP.
+ - Verify the flash ctrl can read seeds when lc_seed_hw_rd_en is set, otherwise all 1s.
+ - Verify that the flash ctrl sent the creator and owner seeds to keymgr. Verify with
+ different seed values.
+
+ - This test needs to execute as a boot rom image.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_init"]
+ }
+ {
+ name: chip_sw_flash_host_access
+ desc: '''Verify that the flash memory contents can be read by the CPU.
+
+ Nothing extra to do here - most SW based tests fetch code from flash.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_ctrl_access",
+ "chip_sw_flash_ctrl_access_jitter_en"]
+ }
+ {
+ name: chip_sw_flash_ctrl_ops
+ desc: '''Verify the SW can initiate flash operations via the controller.
+
+ Verify that the CPU can read / program and erase the flash mem. Pick an operation on
+ all data and info partitions. Erase both, bank and page. SW validates the reception of
+ prog empty, prog level, rd full, rd level and op done interrupts.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_ctrl_ops", "chip_sw_flash_ctrl_ops_jitter_en"]
+ }
+ {
+ name: chip_sw_flash_rma_unlocked
+ desc: '''Verify the flash memory contents can be accessed after in RMA unlock.
+
+ - Provision an RMA_UNLOCK token in OTP.
+ - Repeat the following a few times:
+ - Randomize the otp contents for device id, manufacturing state and RMA_UNLOCK token..
+ - Reset the chip.
+ - Ensure chip revision, device id and manufacturing state can be read through the LC JTAG.
+ - Enable RMA mode, and verify that the SW can access the flash after RMA completion.
+
+ - RMA entry should be done through the JTAG interface.
+
+ - X-ref'ed with manuf_ft_provision_rma_token_and_personalization from the manufacturing
+ testplan.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_rma_unlocked"]
+ }
+ {
+ name: chip_sw_flash_scramble
+ desc: '''Verify flash scrambling via the controller.
+
+ - Extends the chip_flash_init test.
+ - Verify flash scrambling with different key values programmed in OTP.
+ - Verify read of scrambled contents via both, controller and direct host read.
+
+ - Program a new scramble key in OTP and reboot - this time we need to backdoor load the
+ flash with new test image that is re-scrambled with the new key.
+ - Need to understand the bootstrapping requirements.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_init"]
+ }
+ {
+ name: chip_sw_flash_idle_low_power
+ desc: '''Verify flash_idle signaling to pwrmgr.
+
+ - Initiate flash program or erase over the controller.
+ - Program the pwrmgr to go into deep sleep.
+ - Issue a WFI.
+ - Ensure that the low power entry does not happen due to the ongoing flash operation.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_ctrl_idle_low_power"]
+ }
+ {
+ name: chip_sw_flash_keymgr_seeds
+ desc: '''Verify the creator and owner seeds are read on flash init provided lc_hw_seed_rd_en
+ is set.
+
+ X-ref'ed with keymgr test.
+ '''
+ stage: V2
+ tests: ["chip_sw_keymgr_key_derivation"]
+ }
+ {
+ name: chip_sw_flash_lc_creator_seed_sw_rw_en
+ desc: '''Verify the lc_creator_seed_sw_rw_en signal from LC ctrl.
+
+ - Transition from TEST_LOCKED to DEV/PROD to ESCALATION/SCRAP state via OTP and verify
+ that this LC signal transitions from 0 to 1 and back to 0. Verify that the SW
+ accessibility of the corresponding partition depending on the signal value.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_ctrl_lc_rw_en"]
+ }
+ {
+ name: chip_sw_flash_creator_seed_wipe_on_rma
+ desc: '''Verify that the creator seed is wiped by the flash ctrl on RMA entry.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_rma_unlocked"]
+ }
+ {
+ name: chip_sw_flash_lc_owner_seed_sw_rw_en
+ desc: '''Verify the lc_owner_seed_sw_rw_en signal from LC ctrl.
+
+ - Transition from TEST_LOCKED to DEV/PROD to ESCALATION/SCRAP state via OTP and verify
+ that this LC signal transitions from 0 to 1 and back to 0. Verify that the SW
+ accessibility of the corresponding partition depending on the signal value.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_ctrl_lc_rw_en"]
+ }
+ {
+ name: chip_sw_flash_lc_iso_part_sw_rd_en
+ desc: '''Verify the lc_iso_part_sw_rd_en signal from LC ctrl.
+
+ - Transition from DEV to PROD to ESCALATION/SCRAP state via OTP and verify
+ that this LC signal transitions from 0 to 1 and back to 0. Verify that the SW
+ accessibility of the corresponding partition depending on the signal value.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_ctrl_lc_rw_en"]
+ }
+ {
+ name: chip_sw_flash_lc_iso_part_sw_wr_en
+ desc: '''Verify the lc_creator_seed_sw_wr_en signal from LC ctrl.
+
+ - Transition from TEST_LOCKED to DEV/PROD to ESCALATION/SCRAP state via OTP and verify
+ that this LC signal transitions from 0 to 1 and back to 0. Verify that the SW
+ accessibility of the corresponding partition depending on the signal value.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_ctrl_lc_rw_en"]
+ }
+ {
+ name: chip_sw_flash_lc_seed_hw_rd_en
+ desc: '''Verify the lc_seed_hw_rd_en signal from LC ctrl.
+
+ - Transition from TEST_LOCKED to DEV/PROD to ESCALATION/SCRAP state via OTP and verify
+ that this LC signal transitions from 0 to 1 and back to 0. Verify that the flash ctrl
+ does (or does not) read the creator and owner partitions to fetch the seeds for the
+ keymgr.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_ctrl_lc_rw_en"]
+ }
+ {
+ name: chip_sw_flash_lc_escalate_en
+ desc: '''Verify the lc_escalate_en signal from LC ctrl.
+
+ - Trigger an LC escalation signal by generating an alert.
+ - Verify that all flash accesses are disabled when the escalation kicks in.
+ - Confirm flash accesses are disabled by erroing if the device executes the ISR.
+ - Use assertion based connectivity check to prove that this signal is connected to the
+ flash ctrl.
+
+ X-ref with chip_sw_all_escalation_resets.
+ '''
+ stage: V2
+ tests: ["chip_sw_all_escalation_resets"]
+ }
+ {
+ name: chip_sw_flash_prim_tl_access
+ desc: '''Verify that the SW can read / write the prim tlul interface in flash phy.
+
+ - The prim tlul interface is a open source placeholder for the closed source CSRs that
+ will be implemented in a translation 'shim'.
+ - Verify that this region can be read / written to by the SW in any LC state.
+ '''
+ stage: V2
+ tests: ["chip_prim_tl_access"]
+ }
+ {
+ name: chip_sw_flash_ctrl_clock_freqs
+ desc: '''Verify flash program and erase operations over the ctrl over a range of clock freqs.
+
+ - Enable jitter on the clock while performing erase, write and read operations
+ to the flash.
+ - This sets the test for closed source where the flash access timing matters.
+ '''
+ stage: V2
+ tests: ["chip_sw_flash_ctrl_clock_freqs"]
+ }
+
+ ////////////////////////
+ // Analog Peripherals //
+ // AST, SENSOR_CTRL //
+ ////////////////////////
+
+ // AST (pre-verified IP) integration tests:
+ {
+ name: chip_sw_ast_clk_outputs
+ desc: '''Verify that the AST generates the 4 clocks when requested by the clkmgr.
+
+ Verify the clock frequencies are reasonably accurate. Bring the chip to deep sleep,
+ and verify that upon wakeup reset the clock counters are turned off, measure ctrl
+ regwen is enabled, and errors are not cleared.
+ '''
+ stage: V2
+ tests: ["chip_sw_ast_clk_outputs"]
+ }
+ {
+ name: chip_sw_ast_clk_rst_inputs
+ desc: '''Verify the clk and rst inputs to AST (from `clkmgr`).
+
+ Create different scenarios that affect the clocks and resets and see that the AST features
+ (RNG, entropy, alert, ADC) that use those clocks/resets behave correctly.
+ sequence:
+ 1. Check that AST RNG generates data and fills the entropy source fifo
+ 2. Create AST alerts
+ 3. Activate ADC conversion
+ 4. EDN entropy supply to AST
+ Enter sleep/deep sleep/ stop IO/USB clocks
+ Repeat 1-4 to check it is ok.
+ '''
+ stage: V2
+ tests: ["chip_sw_ast_clk_rst_inputs"]
+ }
+ {
+ name: chip_sw_ast_sys_clk_jitter
+ desc: '''Verify that the AST sys clk jitter control.
+
+ X-ref with chip_sw_clkmgr_jitter
+ '''
+ stage: V2
+ tests: ["chip_sw_clkmgr_jitter",
+ "chip_sw_flash_ctrl_ops_jitter_en",
+ "chip_sw_flash_ctrl_access_jitter_en",
+ "chip_sw_otbn_ecdsa_op_irq_jitter_en",
+ "chip_sw_aes_enc_jitter_en",
+ "chip_sw_hmac_enc_jitter_en",
+ "chip_sw_keymgr_key_derivation_jitter_en",
+ "chip_sw_kmac_mode_kmac_jitter_en",
+ "chip_sw_sram_ctrl_scrambled_access_jitter_en",
+ "chip_sw_edn_entropy_reqs_jitter"]
+ }
+ {
+ name: chip_sw_ast_usb_clk_calib
+ desc: '''Verify the USB clk calibration signaling.
+
+ - First place the AST into a mode where usb clock frequency significantly deviates from
+ the ideal.
+ - Verify the clock is "off" using the clkmgr measurement mechanism.
+ - Then, turn on the usb sof calibration machinery and wait a few mS.
+ - Afterwards, measure the usb clock again using the clkmgr measurement controls, at this
+ point the clock should be significantly more accurate.
+ - Note, while the above is ideal, usbdev chip level testing is not yet ready and this
+ test fakes the usb portion through DV forces.
+ - Note also the real AST calibration logic is not available, so the sof testing in the
+ open source is effectively short-circuited.
+ '''
+ stage: V2
+ tests: ["chip_sw_usb_ast_clk_calib"]
+ }
+ {
+ name: chip_sw_ast_alerts
+ desc: '''Verify the alerts from AST aggregating into the sensor_ctrl.
+
+ X-ref'ed with `chip_sensor_ctrl_ast_alerts`.
+ '''
+ stage: V2
+ tests: ["chip_sw_sensor_ctrl_alert"]
+ }
+
+ // SENSOR_CTRL tests:
+ {
+ name: chip_sw_sensor_ctrl_ast_alerts
+ desc: '''Verify the alerts from AST aggregating into the sensor_ctrl.
+
+ Check that AST events can be triggered from sensor_ctrl and that
+ the resulting AST outputs are observed in both sensor_ctrl and
+ the alert_handler.
+
+ For the alert handler case, make sure to test each alert configured
+ as either recoverable or fatal.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup",
+ "chip_sw_sensor_ctrl_alert"]
+ }
+ {
+ name: chip_sw_sensor_ctrl_ast_status
+ desc: '''Verify the io power ok status from AST.
+
+ Check that when the IO POK status changes, an interrupt is triggered
+ from sensor_ctrl. After triggering, the IO status can be read
+ from a sensor_ctrl register.
+ '''
+ stage: V2
+ tests: ["chip_sw_sensor_ctrl_status"]
+ }
+ {
+ name: chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup
+ desc: '''Verify the sensor control is able to wake the device
+ from sleep mode when an alert event is triggered from
+ AST. X-ref'ed chip_sw_pwrmgr_sleep_all_wake_ups.
+ '''
+ stage: V2
+ tests: ["chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup"]
+ }
+
+ //////////////////
+ // CPU //
+ // RV_CORE_IBEX //
+ //////////////////
+
+ {
+ name: chip_sw_nmi_irq
+ desc: '''Verify the NMI interrupt to the CPU and correctness of the cause.
+
+ Randomly use these two methods (simultaneously or choose one of them) to trigger the
+ NMI interrupt:
+ - Trigger the alert_handler escalation pair that maps to NMI.
+ - Trigger a watchdog bark.
+
+ Check rv_core_ibex's NMI interrupt register and clear the interrupt.
+ If the NMI interrupt is triggered by alert_handle and the `class_clr_regwen` register
+ is not locked, check that alert_handler can clear this NMI escalation stage. Then make
+ sure that the alert_handler won't move forward to the next escalation stage.
+ '''
+ stage: V2
+ tests: ["chip_sw_rv_core_ibex_nmi_irq"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_rnd
+ desc: '''Verify the functionality of the random number generation CSRs.
+
+ - Enable entropy complex so `RND_DATA` can get entropy.
+ - Perform multiple reads from `RND_DATA` polling `RND_STATUS` in
+ between to only read valid data. Check different random bits
+ are provided each time and that the random data is never zero or all ones.
+ - Ensure `RND_STATUS` indicate invalid data immediately after
+ `RND_DATA` read.
+ - Perform repeated reads from `RND_DATA` without `RND_STATUS`
+ polling to check read when invalid doesn't block.
+ '''
+ stage: V2
+ tests: ["chip_sw_rv_core_ibex_rnd"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_address_translation
+ desc: '''Verify the simple address translation functionality.
+
+ - Setup address translation for both slots on the the I and D
+ side and check correct translation for I and D accesses.
+ - Switch address translation to use different regions that
+ overlap for both slots and check translation again. Ensure some
+ test accesses match both regions, where the lowest indexed one
+ takes priority.
+ - Turn off address translation and confirm regions are no longer
+ being remapped.
+ '''
+ stage: V2
+ tests: ["chip_sw_rv_core_ibex_address_translation"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_icache_scrambled_access
+ desc: '''Verify scrambled memory accesses to CPU icache.
+
+ - Initialize the entropy_src subsystem to enable OTP_CTRL fetch random data (already
+ done by the test_rom startup code).
+ - Execute the `fence` instruction to invalidate the icache.
+ - Verify using probes, that this resulted in a new scrambling key fetched from the OTP
+ ctrl.
+ '''
+ stage: V2
+ tests: ["chip_sw_rv_core_ibex_icache_invalidate"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_fault_dump
+ desc: '''Verify the functionality of the ibex fault dump.
+
+ - Purposely create an ibex exception during execution through reads to an ummapped
+ address.
+ - Ensure the rstmgr fault dump correctly captures the related addresses to the
+ exception.
+ '''
+ stage: V2
+ tests: ["chip_sw_rstmgr_cpu_info"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_double_fault
+ desc: '''Verify the functionality of the ibex double fault dump.
+
+ - Purposely create an ibex double exception during execution, by performing an
+ unmapped read and in the exception handler perform another unmapped read.
+ - Ensure the rstmgr fault dump correctly captures both dumps correctly and indicates
+ the previous dump is valid.
+ '''
+ stage: V2
+ tests: ["chip_sw_rstmgr_cpu_info"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_lockstep_glitch
+ desc: '''Verify lockstep checking of the Ibex core.
+
+ Ensure suitable alerts are triggered when:
+ - Outputs from the lockstep or the main core are corrupted.
+ - Inputs into the lockstep core are corrupted.
+ '''
+ stage: V2S
+ tests: ["chip_sw_rv_core_ibex_lockstep_glitch"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_alerts
+ desc: '''Inject and verify all available faults in rv_core_ibex / ibex_top.
+
+ Inject faults in the following areas and verify the alert is fired leading to an
+ escalation.
+
+ - Bus integrity error on the data and instruction TL interface (on the response channel)
+ - PC mismatch fault
+ - ECC error in the register file
+ '''
+ stage: V3
+ tests: []
+ }
+
+ ////////////////////////////
+ // System level scenarios //
+ ////////////////////////////
+ {
+ name: chip_sw_example_tests
+ desc: '''Provide example tests for different testing scenarios / needs.
+
+ These tests do not verify the hardware. They are meant to serve as a guide for
+ developing actual tests under different testing scenarios. These example tests
+ demonstrate the capabilities of the DV infrastructure which enables these scenarios:
+
+ 1. Implement test in the ROM stage itself
+ 2. Implement test in the flash stage, using test ROM
+ 3. Implement test in the flash stage, using production ROM
+ 4. Enable external maufacturer hooks in existing tests developed in the open source
+ 5. Enable concurrent threads in tests
+ '''
+ stage: V1
+ tests: ["chip_sw_example_rom",
+ "chip_sw_example_flash",
+ "chip_sw_uart_smoketest_signed",
+ "chip_sw_example_manufacturer",
+ "chip_sw_example_concurrency"
+ ]
+ }
+ {
+ name: chip_sw_smoketest
+ desc: '''Run smoke tests developed for each IP.
+
+ The smoke tests are developed by the SW team to test each IP is
+ alive, and can be actuated by the DIF. We need to ensure that they
+ work in DV as well.
+ '''
+ stage: V2
+ tests: ["chip_sw_aes_smoketest",
+ "chip_sw_aon_timer_smoketest",
+ "chip_sw_clkmgr_smoketest",
+ "chip_sw_csrng_smoketest",
+ "chip_sw_entropy_src_smoketest",
+ "chip_sw_gpio_smoketest",
+ "chip_sw_hmac_smoketest",
+ "chip_sw_kmac_smoketest",
+ "chip_sw_otbn_smoketest",
+ "chip_sw_otp_ctrl_smoketest",
+ "chip_sw_pwrmgr_smoketest",
+ "chip_sw_rv_plic_smoketest",
+ "chip_sw_rv_timer_smoketest",
+ "chip_sw_rstmgr_smoketest",
+ "chip_sw_sram_ctrl_smoketest",
+ "chip_sw_uart_smoketest",
+ "chip_sw_dma_main_smoketest",
+ "chip_sw_smc_i2c_device_smoketest",
+ "chip_sw_smc_sram_smoketest",
+ "chip_sw_smc_plic_smoketest",
+ "chip_sw_smc_ctrl_smoketest",
+ "chip_sw_smc_cam_ctrl_smoketest",
+ "chip_sw_smc_cam_i2c_host_smoketest",
+ "chip_sw_smc_isp_ctrl_smoketest",
+ "chip_sw_smc_isp_dma_smoketest",
+ "chip_sw_smc_timer_smoketest",
+ "chip_sw_smc_gpio_smoketest",
+ "chip_sw_smc_ml_sram_smoketest",
+ ]
+ }
+ {
+ name: chip_sw_rom_functests
+ desc: '''Run some ROM functional tests with test ROM.
+
+ ROM functional tests test ROM drivers and libraries by exercising
+ these components in the flash stage, launched via the test ROM. They
+ primarily are tested on the FPGA, however, we ensure they run in DV
+ as well.
+ '''
+ stage: V2
+ tests: ["rom_keymgr_functest"]
+ }
+ {
+ name: chip_sw_signed
+ desc: '''Run some chip-level tests with ROM.
+
+ In addition to ROM E2E tests, we select at least one (or a few)
+ tests defined in this file to sign, and run via ROM instead of
+ test ROM. We need to ensure our test infrastructure and ROM can
+ boot and run one (or a few) of the same tests our test ROM can.
+ '''
+ stage: V2
+ tests: ["chip_sw_uart_smoketest_signed"]
+ }
+ {
+ name: chip_sw_coremark
+ desc: '''Run the coremark benchmark on the full chip.'''
+ stage: V3
+ tests: [
+ "chip_sw_sc_coremark",
+ "chip_sw_smc_coremark"
+ ]
+ }
+ {
+ name: chip_sw_boot
+ desc: '''Verify the full flash image download with bootstrap signal set.
+
+ - SW puts the SPI device in firmware mode
+ - Load a firmware image (bootstrap) through spi input pin to the spi_device memory.
+ - SW verifies the integrity of the image upon reception by reading the spi_device
+ memory.
+ - Ensure the image is executed correctly
+
+ Note: This flow will be replaced by using spi_device flash mode.
+ For detail, refer to chip_spi_device_flash_mode
+ '''
+ stage: V2
+ tests: ["chip_sw_uart_tx_rx_bootstrap"]
+ }
+ {
+ name: chip_sw_secure_boot
+ desc: '''Verify the secure boot flow.
+
+ X-ref rom_e2e_smoke.
+ In reality this can be any rom based test, which requires secure boot.
+ '''
+ stage: V2
+ tests: ["rom_e2e_smoke"]
+ }
+ {
+ name: chip_lc_scrap
+ desc: '''Ensure it is possible to enter scrap state from every legal life cycle state.
+
+ - Request transition to SCRAP state using the JTAG interface.
+ - It should be possible to transition from every legal state using external clock.
+ - Where it is allowed, transition using internal clocks should also be checked.
+ - After transition, verify that the device is in SCRAP state through LC read.
+ - Verify while in SCRAP state:
+ - RV JTAG interface is unavailable.
+ - Ibex is not executing.
+ - RV_DM is unreachable by the stub CPU.
+
+ - X-ref'd with manuf_scrap from the manufacturing testplan.
+ - X-ref'd with chip_lc_test_locked.
+ - X-ref'd with chip_tap_strap_sampling
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_ctrl_rand_to_scrap",
+ "chip_sw_lc_ctrl_raw_to_scrap",
+ "chip_sw_lc_ctrl_rma_to_scrap",
+ "chip_sw_lc_ctrl_test_locked0_to_scrap"]
+ }
+ {
+ name: chip_lc_test_locked
+ desc: '''Transition from TEST_UNLOCKED to TEST_LOCKED using LC JTAG interface.
+
+ - Check in TEST_UNLOCKED RV JTAG interface is available.
+ - Verify When in TEST_LOCKED state:
+ - RV JTAG interface is unavailable.
+ - Ibex is not executing.
+ - RV_DM is unreachable by the stub CPU.
+
+ - X-ref'd with manuf_cp_test_lock from the manufacturing testplan.
+ - X-ref'd with chip_lc_scrap.
+ - X-ref'd with chip_tap_strap_sampling
+ - X-ref'd with chip_sw_lc_walkthrough
+ - X-ref'd with chip_rv_dm_lc_disabled
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_walkthrough_testunlocks",
+ "chip_rv_dm_lc_disabled"]
+ }
+ {
+ name: chip_sw_lc_walkthrough
+ desc: '''Walk through the life cycle stages from RAW state and reseting the chip each time.
+
+ - Pre-load OTP image with RAW lc_state.
+ - Initiate the LC transition to one of the test unlock state.
+ - Program test_unlock_token, test_exit_token, rma_unlock_token into OTP partitions.
+ - Move forward to next valid LC states via JTAG interface or SW interface if CPU is
+ enabled.
+ Verify that the features that should indeed be disabled are indeed disabled.
+ '''
+ stage: V2
+ tests: ["chip_sw_lc_walkthrough_dev",
+ "chip_sw_lc_walkthrough_prod",
+ "chip_sw_lc_walkthrough_prodend",
+ "chip_sw_lc_walkthrough_rma",
+ "chip_sw_lc_walkthrough_testunlocks"]
+ }
+ {
+ name: chip_sw_power_max_load
+ desc: '''Concurrency test modeling maximum load conditions.
+
+ This concurrency test runs multiple blocks at the same time, to simulate
+ maximum load ("power virus test"). Should be combined with low power
+ entry and exit scenarios.
+
+ The test should be made configurable so that the type of power state and
+ the time spent in a particular power state can be configured via a
+ flag (or similar). This will make it easier to reuse the test for power
+ simulation and characterization later on.
+
+ The test should set a GPIO (mapped to the IOA2 pin) to high while the power
+ state of interest is active.
+
+ Blocks / functionality to run simulatenously in this test:
+
+ - The ADC is continuously sampling new data
+ - Staggered activation of OTBN, aes, KMAC/HMAC.
+ - KMAC / aes would need to take turns being fed data
+ - KMAC activation should be a combination of otp background, key
+ manager background and software
+ - for OTBN, any signature verification / signing event is sufficient
+ - Entropy complex ongoing
+ - reseed / update operation ongoing
+ - Flash scramble ongoing (ideally both instruction and data, but data should be sufficient
+ for now)
+ - instruction scrambling gated by script availability
+ - Simultaneous IO toggling as defined below
+ - ideally for digital activity, 3xUART / I2C modules should be activated
+ - for first pass simplicity can activate IO portion only for now through GPIO
+ - for dedicated pins, focus on SPI device quad activity
+ - USB activity should be activated
+ - for first pass simplicity activate IO portion only for now via pin forcing in usbdev.
+ - Ongoing cpu activity (icache / SRAM scrambling both activated)
+ - servicing ongoing threads and random read/write data to memory
+ - icache needs to be activated, otherwise the system may spend most of its time fetching
+ code
+ - Background checks enabled wherever possible
+ - rstmgr background checks
+ - alert_handler ping checks
+ - OTP background checks
+ - The test should be run both with / without external clock
+
+ This test should leverage the OTTF test framework for supporting
+ concurrency in a FreeRTOS environment. See also the design docs linked
+ in #14095 for more details on how to approach the implementation.
+ '''
+ stage: V3
+ tests: []
+ }
+ {
+ name: chip_sw_power_idle_load
+ desc: '''Concurrency test modeling load conditions in idle state
+
+ This concurrency test models an average idle scenarios.
+
+ The test should be made configurable so that the type of power state and
+ the time spent in a particular power state can be configured via a
+ flag (or similar). This will make it easier to reuse the test for power
+ simulation and characterization later on.
+
+ The test should set a GPIO (mapped to the IOA2 pin) to high while the power
+ state of interest is active.
+
+ The test should cover the following scenarios:
+
+ - Processor polls for nmi interrupt
+ - Background checks enabled wherever possible
+ - rstmgr background checks
+ - alert_handler ping checks
+ - OTP background checks
+ - Timers (regular and AON) are active
+ - Check whether transactional clocks should be enabled or disabled
+ - Check whether PWM should be active
+ '''
+ stage: V2
+ tests: ["chip_sw_power_idle_load"]
+ }
+ {
+ name: chip_sw_power_sleep_load
+ desc: '''Concurrency test modeling load conditions in idle state
+
+ This concurrency test models average sleep scenarios.
+
+ The test should be made configurable so that the type of power state and
+ the time spent in a particular power state can be configured via a
+ flag (or similar). This will make it easier to reuse the test for power
+ simulation and characterization later on.
+
+ The test should cover the following scenarios:
+
+ - System can be in deep or light sleep
+ - The system has the following AON / IO activity:
+ - aon_timer active
+ - adc_ctrl active in low power mode
+ - TBD: check whether sysrst_ctrl and pinmux wakeup detectors should be active
+ - TBD: check whether PWM should be active
+
+ This test should leverage the OTTF test framework for supporting
+ concurrency in a FreeRTOS environment. See also the design docs linked
+ in #14095 for more details on how to approach the implementation.
+ '''
+ stage: V2
+ tests: ["chip_sw_power_sleep_load"]
+ }
+
+ {
+ name: chip_sw_exit_test_unlocked_bootstrap
+ desc: '''End to end test to ensure rom boot strap can be performed after
+ transitioning from TEST states to PROD staets. .
+
+ - Pre-load the device into TEST_UNLOCKED state and ROM_EXEC_EN = 0.
+ - In the same power cycle, advance device to PROD, PROD_END or DEV through LC JTAG request and
+ set ROM_EXEC_EN in OTP to logically true.
+ - Reboot the device and perform boot strap of a simple image, (e.g Hello World).
+ - Ensure boot strap succeeds.
+
+ X-ref'ed with manuf_ft_exit_token from manufacturing test plan.
+ '''
+ stage: V2
+ tests: ["chip_sw_exit_test_unlocked_bootstrap"]
+ }
+
+ {
+ name: chip_sw_inject_scramble_seed
+ desc: '''End to end test to ensure boot strap can succeed after injecting scramble seeds.
+
+ - Pre-load the device into PROD, PROD_END or DEV state.
+ - Backdoor load an unscrambled value into flash isolated partition.
+ - In the test program, populate the scramble seeds (flash / sram).
+ - In the test program, populate OTP entries to inform ROM to scramble flash upon next boot.
+ - Reboot the device and perform boot strap of the same test image, ROM should now program
+ the flash image with scramble enabled.
+ - Upon successful boot strap, ROM jumps to the newly programmed image and de-scrambles the
+ instructions.
+ - In the test program, check whether the OTP partition containing the scramble seeds is
+ locked. Also check that the unscrambled value progarmmed into flash isolated partition
+ can be correctly read back when the region is set to scramble disable.
+ - If either of the above checks is incorrect, return error.
+
+
+ X-ref'ed with manuf_ft_sku_individualization from manufacturing test plan.
+ '''
+ stage: V2
+ tests: ["chip_sw_inject_scramble_seed"]
+ }
+ {
+ name: chip_sw_device_ownership
+ desc: '''Walk through device ownership stages and flows.
+
+ Details TBD.
+ '''
+ stage: V2
+ tests: []
+ }
+ {
+ name: chip_sw_boot_i2c
+ desc: '''Verify the full security core image download with bootstrap signal set.
+
+ - SW puts the i2c device in firmware mode
+ - Load security core firmware image (bootstrap) through i2c input pin to the
+ security core memory.
+ - SW decrypt the message based on OTP.
+ - SW verifies the integrity of the image based on OTP.
+ - Continue boot and ensure the image is executed correctly
+ - TODO: Ask Austin to confirm.
+ '''
+ stage: V2
+ tests: ["chip_sw_i2c_boot"]
+ }
+ {
+ // TODO(b/287644985): revise mem_test.c into smc_sram_smoke test.
+ name: chip_sw_mem_test
+ desc: '''Verify the access to all of the memory instances
+
+ - SW bring up secure core
+ - SW read/write random data in SMC ram memory region
+ - SW read/write random data in ML data memory region
+ - SW vefiry the written data matches the read data
+ '''
+ stage: V2
+ tests: ["chip_sw_mem_test"]
+ }
+
+ //////////////////
+ // CPU //
+ // RV_CORE_SMC //
+ //////////////////
+ {
+ name: chip_sw_boot_smc
+ desc: '''Verify the full SMC core image download with bootstrap signal set.
+
+ - SW puts the QSPI host in firmware mode
+ - Load a firmware image (bootstrap) through QSPI input pin to the SMC memory.
+ - SW decrypt the message based on OTP.
+ - SW verifies the integrity of the image.
+ - Security core enable the SMC boot and ensure the image is executed correctly
+ '''
+ stage: V2
+ tests: []
+ }
+ {
+ name: chip_sw_boot_ml_kelvin_core
+ desc: '''Verify the full Kelvin core image download with bootstrap signal set.
+
+ - SW load a Kelvin core hello_world image to the ML memory.
+ - SW verifies the integrity of the image by reading ML memory.
+ - SMC core boots the Kelvin core and ensures the program executes correctly
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_kelvin_hello_test"]
+ }
+ {
+ name: chip_sw_smc_isp_wrapper_test
+ desc: '''Verify ISP is enabled and generate data
+
+ - SW enable ISP to a simple mode.
+ - SW verify ISP status registers are updated.
+ - SW randomly read/write the memory region which is accessible by ISP.
+ - SW validate the writtne data matches the read data.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_isp_wrapper_test"]
+ }
+ {
+ name: chip_sw_smc_isp_simple_test_data
+ desc: '''Verify ISP control path and data path
+
+ - SW configure ISP to generate known test pattern.
+ - SW configure ISP interal blocks to send raw data.
+ - SW configure write DMA to send one frame of data to ML_DMEM location.
+ - SW check back data and compare with the golden pattern.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_isp_wrapper_tpg_128_64_test"]
+ }
+ {
+ name: chip_sw_smc_isp_dma_smoketest
+ desc: '''Verify the ISP setups dma and transfers data between ISP and sram.
+
+ - SW configure the ISP ctrl registers to generate golden data with different settings.
+ - SW configure the ISP DMA to set different destination memory locations
+ - SW enable ISP to grab one frame of image for each setting.
+ - SW check back data and compare with the golden pattern.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_isp_dma_smoketest"]
+ }
+ {
+ name: chip_sw_smc_cam_irq
+ desc: '''Verify cam raise irq with right input data
+
+ - SW configure camera to stream out test pattern.
+ - SW check whether a cam irq is expected to be received based on the test pattern.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_cam_irq_test"]
+ }
+ {
+ name: chip_sw_smc_isp_irq
+ desc: '''Verify isp raise irq with right input data
+
+ - SW configure isp to generate test pattern.
+ - SW check whether a isp irq is expected to be received based on the test pattern.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_isp_wrapper_irq_test"]
+ }
+ {
+ name: chip_sw_ml_irq
+ desc: '''Verify ml core raise irq when it is triggered
+
+ - SW initialize Kelvin ml core
+ - SW force triggering kelvin core's interrupt and check whether a kelvin core handle it
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_ml_top_irq_test"]
+ }
+ {
+ name: chip_sw_smc_cam_raw_data
+ desc: '''Verify test datapath from camera raw data to ML_DMEM
+
+ - SW configure camera with test pattern: size 324x324, 8bits DVP, frame rate (1fps)
+ - SW configure ISP interal blocks to bypass most of blocks and send raw data to WDMA.
+ - SW configure write DMA to send one frame of data to ML_DMEM location.
+ - SW read back data, compare to the golden pattern to decide pass or fail.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_cam_raw_data"]
+ }
+ {
+ name: chip_sw_smc_cam_mono_data
+ desc: '''Verify test datapath from camera mono data to ML_DMEM
+
+ - SW configure camera with test pattern: mono, size 324x324, 8bits DVP, frame rate (1fps)
+ - SW configure ISP interal blocks to bypass most of blocks and send mono data to WDMA.
+ - SW configure write DMA to send one frame of data to ML_DMEM location.
+ - SW read back data, compare to the golden pattern to decide pass or fail.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_cam_mono_data"]
+ }
+ {
+ name: chip_sw_smc_cam_color_data
+ desc: '''Verify test datapath from camera color data to ML_DMEM
+
+ - SW configure camera with test pattern: color, size 324x324, 8bits DVP, frame rate (1fps)
+ - SW configure ISP interal blocks to bypass most of blocks and send color data to WDMA.
+ - SW configure write DMA to send one frame of data to ML_DMEM location.
+ - SW read back data, compare to the golden pattern to decide pass or fail.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_cam_mono_data"]
+ }
+ {
+ name: chip_sw_smc_virtual_memory
+ desc: '''Verify smc virtual memory functionality
+
+ - SW enable page table
+ - SW enable virtual memory and test in supervisor mode
+ - SW verify the page bounday check
+ - SW verify the interrupt is raised and handled
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_interrupt_boundary_test",
+ "chip_sw_smc_lsu_interrupt_boundary_test",
+ "chip_sw_smc_lsu_page_boundary_test",
+ "chip_sw_smc_page_boundary_test",
+ "chip_sw_smc_supervisor_mode_test",
+ "chip_sw_smc_virtual_memory_test"]
+
+ }
+ // SMC RV_TIMER integration tests:
+ {
+ name: chip_sw_smc_rv_timer_test
+ desc: '''Verify the timeout interrupt assertion.
+
+ - Configure the SMC RV_TIMER to generate interrupt after a set timeout.
+ - Issue a WFI to wait for the interrupt to trigger.
+ - Service the interrupt when it triggers; verify that it came from rv_timer.
+ - Verify that the interrupt triggered only after the timeout elapsed.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_rv_timer_test"]
+ }
+ {
+ name: chip_sw_video_pipe_smoketest
+ desc: '''Verify the video pipeline from image sensor to ML memory.
+
+ - SW configure the camera sensor through CAM_I2C interface.
+ - SW configure the ISP ctrl register.
+ - SW configure the ISP DMA to set destination memory location.
+ - SW enable both camera and ISP to grab one frame of image.
+ - Ensure the image is written into correct memory location for each config.
+ - SW can be run from Security core or SMC core.
+ '''
+ stage: V2
+ tests: ["chip_sw_video_pipe_smoketest"]
+ }
+ {
+ name: chip_sw_smc_kelvin_run_checksum_test
+ desc: '''Verify checksum test on Kelvin core.
+
+ - SW bring up both SMC and ML cores.
+ - SW write a test image onto ML DMEM.
+ - SW start Kelvin core to read image data and compute checksum.
+ - SW validate the compuated checksum matches the golden checksum.
+ '''
+ stage: V2
+ tests: ["chip_sw_smc_kelvin_checksum_test"]
+ }
+
+ ]
+}
diff --git a/hw/top_sencha/data/clocks_nexus.xdc b/hw/top_sencha/data/clocks_nexus.xdc
new file mode 100644
index 0000000..e518ed8
--- /dev/null
+++ b/hw/top_sencha/data/clocks_nexus.xdc
@@ -0,0 +1,144 @@
+# Copyright 2024 Google LLC
+# Copyright lowRISC contributors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+## Clock Signal - 100M >> 1/100e6 = 1e-8s = 10ns
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports IO_CLK]
+
+## Rename MMCM outputs for less bug-prone parsing.
+## Some auto-derived clocks can have names that include brackets.
+create_generated_clock -name clk_main [get_pin clkgen/pll/CLKOUT0]
+create_generated_clock -name clk_usb_48 [get_pin clkgen/pll/CLKOUT1]
+create_generated_clock -name clk_aon [get_pin clkgen/pll/CLKOUT4]
+
+# Store clock periods in variables
+set clk_main_period [get_property PERIOD [get_clocks clk_main]]
+set clk_usb_48_period [get_property PERIOD [get_clocks clk_usb_48]]
+set clk_aon_period [get_property PERIOD [get_clocks clk_aon]]
+
+## Clock Domain Crossings
+set clks_10_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]]
+set clks_48_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT1]]
+set clks_aon_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT4]]
+
+## Divided clock
+## This is not really recommended per Vivado's guidelines, but hopefully these clocks are slow enough and their
+## destination flops few enough.
+
+set u_pll clkgen/pll
+set u_div2 top_*/u_clkmgr_aon/u_no_scan_io_div2_div
+create_generated_clock -name clk_io_div2 -source [get_pin ${u_pll}/CLKOUT0] -divide_by 2 [get_pin ${u_div2}/u_clk_div_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
+
+#Recommended Div4 clock constraints from Xilinx
+#TODO uncomment below line and integrate u_div4 in path to make constraint more generic
+set u_div4 top_*/u_clkmgr_aon/u_no_scan_io_div4_div
+create_generated_clock -name clkDiv4 -divide_by 4 -source [get_pins ${u_div4}/gen_div.clk_int_reg/C] [get_pins ${u_div4}/gen_div.clk_int_reg/Q]
+
+#
+
+# the step-down mux is implemented with a LUT right now and the mux switches on the falling edge.
+# therefore, Vivado propagates both clock edges down the clock network.
+# this implementation is not ideal - but we can at least tell Vivado to only honour the rising edge for
+# timing analysis.
+set_clock_sense -positive \
+ [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \
+ [get_nets -segments -of_objects \
+ [get_pin ${u_div2}/u_clk_div_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/I] \
+ ] \
+ ]
+
+## JTAG clocks -- JTAG clock max frequency is set to 500KHz
+create_clock -add -name lc_jtag_tck -period 2000.00 -waveform {0 1000} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
+create_clock -add -name rv_jtag_tck -period 2000.00 -waveform {0 1000} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
+
+set clk_spi_period 200
+set clk_spi_half_period [expr ${clk_spi_period} / 2]
+## SPI clocks
+set spi_dev_data [get_ports {SPI_DEV_D0 SPI_DEV_D1 SPI_DEV_D2 SPI_DEV_D3}]
+create_clock -add -name clk_spi -period ${clk_spi_period} -waveform "0 ${clk_spi_half_period}" [get_ports SPI_DEV_CLK]
+create_clock -add -name clk_cs -period [expr $clk_spi_period * 10]
+set_input_delay -clock clk_spi 5 ${spi_dev_data} -add_delay
+set_output_delay -clock clk_spi 5 ${spi_dev_data} -add_delay
+# set_input_delay -clock clk_spi -clock_fall -min ${spi_dev_in_delay_min} ${spi_dev_data} -add_delay
+# set_input_delay -clock clk_spi -clock_fall -max ${spi_dev_in_delay_max} ${spi_dev_data} -add_delay
+
+## Camera Clock
+#8-bit, QVGA 60FPS @ 6MHz > setting to 10M to keep numbers round
+#create_clock -add -name clk_cam_pclk -period 100.00 -waveform {0 50} [get_ports ISP_DVP_PCLK]
+
+##SPI Host IO Delay
+## SPI Passthrough constraints
+create_generated_clock -name clk_spi_pt -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_ports SPI_HOST_CLK]
+set spi_pt_data [get_ports {SPI_HOST_D0 SPI_HOST_D1 SPI_HOST_D2 SPI_HOST_D3}]
+set_input_delay -clock clk_spi_pt -clock_fall 7 ${spi_pt_data} -add_delay
+
+set_output_delay -clock clk_spi_pt 7 ${spi_pt_data} -add_delay
+set_output_delay -clock clk_spi_pt 7 [get_ports SPI_HOST_CS_L] -add_delay
+
+
+
+## GPIO IO Delay
+set ioa_muxed_ports [get_ports IOA*]
+set iob_muxed_ports [get_ports IOB*]
+set ioc_muxed_ports [get_ports IOC*]
+set ioc_muxed_ports [get_ports IOD*]
+set ior_muxed_ports [get_ports -filter {NAME != IOR8 && NAME != IOR9} IOR*]
+set all_muxed_ports "${ioa_muxed_ports} ${iob_muxed_ports} ${ioc_muxed_ports} ${ior_muxed_ports}"
+
+set_input_delay -clock clkDiv4 5 [get_ports ${all_muxed_ports}]
+set_output_delay -clock clkDiv4 5 [get_ports ${all_muxed_ports}]
+
+create_generated_clock -name clk_i2s_rx -divide_by 22 -source [get_pin ${u_pll}/CLKOUT1] [get_pins top_sencha/u_i2s0/i2s_core/bufg_rx_audio_clk/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
+create_generated_clock -name clk_i2s_tx -divide_by 22 -source [get_pin ${u_pll}/CLKOUT1] [get_pins top_sencha/u_i2s0/i2s_core/bufg_tx_audio_clk/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
+
+
+# set clock sense on the input to spi buffers to help the tool understand the clocks are shifted versions of each other
+# This can also be accomplished through create_genearted_clocks.
+
+## set clock sense approach
+##set_clock_sense -negative \
+## [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \
+## [get_nets -segments -of_objects \
+## [get_pins top_*/u_spi_device/gen_fpga_buf.gen_bufr.bufr_i_i_1/I] \
+## ] \
+## ] \
+## -clocks clk_spi
+##
+##set_clock_sense -positive \
+## [get_pins -filter {DIRECTION == OUT && IS_LEAF} -of_objects \
+## [get_nets -segments -of_objects \
+## [get_pins top_*/u_spi_device/gen_fpga_buf.gen_bufr.bufr_i_i_1__0/I] \
+## ] \
+## ] \
+## -clocks clk_spi
+
+## create_generated_clock appraoch
+## create_generated_clock is preferred since the buffer cell used here is hand-instantiated, while the set_clock_sense point is simply a LUT
+create_generated_clock -name clk_spi_in -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O]
+create_generated_clock -name clk_spi_out -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O] -invert
+
+set_clock_groups -asynchronous \
+ -group ${clks_10_unbuf} \
+ -group ${clks_48_unbuf} \
+ -group ${clks_aon_unbuf} \
+ -group clk_io_div2 \
+ -group clkDiv4 \
+ -group lc_jtag_tck \
+ -group rv_jtag_tck \
+ -group {clk_spi clk_spi_in clk_spi_out clk_spi_pt} \
+ -group clk_cs \
+ -group sys_clk_pin \
+ -group clk_i2s_rx \
+ -group clk_i2s_tx
diff --git a/hw/top_sencha/data/pins_nexus.xdc b/hw/top_sencha/data/pins_nexus.xdc
new file mode 100644
index 0000000..03393a5
--- /dev/null
+++ b/hw/top_sencha/data/pins_nexus.xdc
@@ -0,0 +1,243 @@
+# Copyright 2024 Google LLC
+# Copyright lowRISC contributors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+## Nexus FPGA Board.
+
+## Clock Signal: 100Mhz REFCLK (Pin U13 and T13 at Bank 72)
+set_property -dict { PACKAGE_PIN U13 IOSTANDARD DIFF_SSTL18_I } [get_ports { IO_CLK }]; # CK_100M00_FPGA_1_P
+set_property -dict { PACKAGE_PIN T13 IOSTANDARD DIFF_SSTL18_I } [get_ports { IO_CLK_N }]; # CK_100M00_FPGA_1_N
+
+## Clock constraints
+## set via clocks.xdc
+
+## Preserve prim_prince modules and setup multi-cycle paths
+## These are no longer required, but kept here as a reference
+## set_property KEEP_HIERARCHY TRUE [get_cells top_sencha/u_flash_eflash/gen_flash_banks[*].i_core/u_scramble/u_cipher]
+## set_multicycle_path -setup 2 -through [get_pins -of_objects [get_cells top_sencha/u_flash_eflash/gen_flash_banks[*].i_core/u_scramble/u_cipher]]
+## set_multicycle_path -hold 1 -through [get_pins -of_objects [get_cells top_sencha/u_flash_eflash/gen_flash_banks[*].i_core/u_scramble/u_cipher]]
+
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IO_SDCK_IBUF]; # SDCK clock to be ignored
+
+## LEDs in Bank 68 LVCMOS12
+set_property -dict { PACKAGE_PIN R36 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOA8 }]; #LED_B_0
+# Commented out following LEDs pins, re-cycled IOB0-6 for camera interface. Keeping for reference.
+#set_property -dict { PACKAGE_PIN T31 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB0 }]; #LED_B_1
+#set_property -dict { PACKAGE_PIN P31 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB1 }]; #LED_B_2
+#set_property -dict { PACKAGE_PIN N37 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB2 }]; #LED_B_3
+#set_property -dict { PACKAGE_PIN M38 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB3 }]; #LED_B_4
+#set_property -dict { PACKAGE_PIN L38 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB4 }]; #LED_B_5
+#set_property -dict { PACKAGE_PIN L36 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB5 }]; #LED_B_6
+#set_property -dict { PACKAGE_PIN K36 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOB6 }]; #LED_B_7
+
+### Buttons in Bank 68 LVCMOS12 #TEMPORARILY REMOVED - should add in addition to FTDI reset
+#set_property -dict { PACKAGE_PIN W31 IOSTANDARD LVCMOS12 } [get_ports { POR_N }]; #pushbutton PBA1
+
+## Switches (4 in Bank60 for Nexus: FPGA_SW[0-3] LVCMOS18, to DIP Switch SW03)
+set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 } [get_ports { IOC8 }]; #FPGA_SW0 #tap0
+set_property -dict { PACKAGE_PIN AT31 IOSTANDARD LVCMOS18 } [get_ports { IOC5 }]; #FPGA_SW1 #tap1
+
+# Removed following SW pins, re-cycled IOA2-7 for camera interface. Keeping for reference.
+#set_property -dict { PACKAGE_PIN AR32 IOSTANDARD LVCMOS18 } [get_ports { IOA2 }]; #FPGA_SW2
+#set_property -dict { PACKAGE_PIN AR33 IOSTANDARD LVCMOS18 } [get_ports { IOA3 }]; #FPGA_SW3
+## Switches (another 4 in Bank66 for Nexus: FPGA_SW[4-7] LVCMOS18, to both DIP switch SW47 and debug header J259)
+#set_property -dict { PACKAGE_PIN BF9 IOSTANDARD LVCMOS18 } [get_ports { IOA4 }]; #FPGA_SW4
+#set_property -dict { PACKAGE_PIN BE9 IOSTANDARD LVCMOS18 } [get_ports { IOA5 }]; #FPGA_SW5
+#set_property -dict { PACKAGE_PIN BF10 IOSTANDARD LVCMOS18 } [get_ports { IOA6 }]; #FPGA_SW6
+#set_property -dict { PACKAGE_PIN BE10 IOSTANDARD LVCMOS18 } [get_ports { IOA7 }]; #FPGA_SW7
+
+#SIGNALS REMOVED FROM SWITCHES TO MAKE WAY FOR OTHER SIGNALS
+#IOA0 removed from FPGA_SW0 to make way for IOC8 (tap0)
+#IOA1 removed from FPGA_SW0 to make way for IOC5 (tap1)
+
+## SPI_Device Option 1: (SPI Device connect to SPI1 to MCU through 1v8<->3V3 level shifter, Bank60 LVCMOS18)
+#set_property -dict { PACKAGE_PIN AT32 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_CLK }]; #SCK (SPI1_SCK/FPGA_MCU_1P8_5)
+#set_property -dict { PACKAGE_PIN AU33 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D0 }]; #SDI (SPI1_MOSI/FPGA_MCU_1P8_3)
+#set_property -dict { PACKAGE_PIN AV34 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D1 }]; #SDO (SPI1_MISO/FPGA_MCU_1P8_4)
+#set_property -dict { PACKAGE_PIN AU32 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_CS_L }];#CSB (SPI1_NSS/FPGA_MCU_1P8_6)
+
+## SPI_Device Option 2: (SPI Device connect to FTDI ADBUS through 1v8<->3V3 level shifter, Bank65 LVCMOS18)
+set_property -dict { PACKAGE_PIN AV19 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_CLK }]; #SCK (FT_AD0_SCK)
+set_property -dict { PACKAGE_PIN AV20 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D0 }]; #SDI (FT_AD1_MOSI)
+set_property -dict { PACKAGE_PIN AV18 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D1 }]; #SDO (FT_AD2_MISO)
+set_property -dict { PACKAGE_PIN BA17 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D2 }]; #SDI (FT_AD4)-placeholder
+set_property -dict { PACKAGE_PIN BB17 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_D3 }]; #SDO (FT_AD5)-placeholder
+set_property -dict { PACKAGE_PIN AW20 IOSTANDARD LVCMOS18 } [get_ports { SPI_DEV_CS_L }];#CSB (FT_AD3_SS)
+
+## JTAG (Dedicate JTAG pin header for ARM/RISC-V, connected to header J291 through level shifter U291)
+## in bank 65 and 66 LVCMOS18
+## This is different from CW310 in which JTAG and SPI_Device are overlaid.
+set_property -dict { PACKAGE_PIN BE18 IOSTANDARD LVCMOS18 PULLTYPE PULLDOWN } [get_ports { IOR0 }]; #JTAG TMS (FPGA_ARM_TMS)
+set_property -dict { PACKAGE_PIN BE17 IOSTANDARD LVCMOS18 PULLTYPE PULLDOWN } [get_ports { IOR1 }]; #JTAG TDO (FPGA_ARM_TDO)
+set_property -dict { PACKAGE_PIN BB19 IOSTANDARD LVCMOS18 PULLTYPE PULLDOWN } [get_ports { IOR2 }]; #JTAG TDI (FPGA_ARM_TDI)
+set_property -dict { PACKAGE_PIN AW18 IOSTANDARD LVCMOS18 PULLTYPE PULLDOWN } [get_ports { IOR3 }]; #JTAG TCK (FPGA_ARM_TCLK)
+set_property -dict { PACKAGE_PIN BC19 IOSTANDARD LVCMOS18 } [get_ports { IOR4 }]; #JTAG_TRST (FPGA_ARAM_TRSTN)
+set_property -dict { PACKAGE_PIN BC16 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { JTAG_SRST_N }]; #JTAG SRST (FPGA_ARM_NSRST)
+
+## SPI HOST (connected to FLASH1 U6 on Nexus, FPGA Bank 73, LVCMOS18)
+set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS18 } [get_ports { SPI_HOST_CLK }]; #SCK (FLASH1_SCK)
+set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { SPI_HOST_D0 }]; #SDO (FLASH1_D0)
+set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { SPI_HOST_D1 }]; #SD1 (FLASH1_D1)
+set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { SPI_HOST_D2 }]; #SD2 (FLASH1_D2)
+set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports { SPI_HOST_D3 }]; #SD3 (FLASH1_D3)
+set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS18 } [get_ports { SPI_HOST_CS_L }]; #CSB (FLASH1_CSB)
+set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [ get_ports { IOC12 }]; #RSTB (FLASH1_RSTB)
+
+## Nexus PMOD3 connect to interace Connector (J263, 3.3V through level shifter), Bank62 LVCMOS18
+set_property -dict { PACKAGE_PIN AU40 IOSTANDARD LVCMOS18 } [get_ports { IOD0 }]; #PMOD3_1_FPGA
+set_property -dict { PACKAGE_PIN AV40 IOSTANDARD LVCMOS18 } [get_ports { IOD1 }]; #PMOD3_2_FPGA
+set_property -dict { PACKAGE_PIN AW40 IOSTANDARD LVCMOS18 } [get_ports { IOD2 }]; #PMOD3_3_FPGA
+set_property -dict { PACKAGE_PIN AY39 IOSTANDARD LVCMOS18 } [get_ports { IOD3 }]; #PMOD3_4_FPGA
+set_property -dict { PACKAGE_PIN AU39 IOSTANDARD LVCMOS18 } [get_ports { IOD4 }]; #PMOD3_7_FPGA
+set_property -dict { PACKAGE_PIN AV39 IOSTANDARD LVCMOS18 } [get_ports { IOD5 }]; #PMOD3_8_FPGA
+# set_property -dict { PACKAGE_PIN AW37 IOSTANDARD LVCMOS18 } [get_ports { IOA1 }]; #PMOD3_9_FPGA
+# set_property -dict { PACKAGE_PIN AW38 IOSTANDARD LVCMOS18 } [get_ports { IOC9 }]; #PMOD3_10_FPGA
+
+
+## Parallel Camera Nexus SMC J14 pins for HPS
+#FORMAT: ASSIGNMENT #SIGNAL_DESCRIPTION #NEXUS_SIGNAL_NAME
+#set_property -dict { PACKAGE_PIN BE35 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D0 }]; #PCAM_D0 #FMC_LA021_P
+#set_property -dict { PACKAGE_PIN BD30 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D1 }]; #PCAM_D1 #FMC_LA12_P
+#set_property -dict { PACKAGE_PIN BB36 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D2 }]; #PCAM_D2 #FMC_LA26_P
+#set_property -dict { PACKAGE_PIN BF30 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D3 }]; #PCAM_D3 #FMC_LA011_P
+#set_property -dict { PACKAGE_PIN BA35 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D4 }]; #PCAM_D4 #FMC_LA27_P
+#set_property -dict { PACKAGE_PIN BD32 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D5 }]; #PCAM_D5 #FMC_LA16_P
+#set_property -dict { PACKAGE_PIN BC35 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D6 }]; #PCAM_D6 #FMC_LA25_P
+#set_property -dict { PACKAGE_PIN BE32 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_D7 }]; #PCAM_D7 #FMC_LA015_P
+#set_property -dict { PACKAGE_PIN AY32 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_PCLK}]; #PCAM_PCLK #FMC_LA18_CC_P
+##set_property -dict { PACKAGE_PIN AW31 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_MCLK }]; #PCAM_MCLK #FMC_LA17_CC_P
+#set_property -dict { PACKAGE_PIN BF26 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_VSYNC }]; #PCAM_FVLD #FMC_LA04_P
+#set_property -dict { PACKAGE_PIN BE29 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_HSYNC }]; #PCAM_LVLD #FMC_LA07_P
+#set_property -dict { PACKAGE_PIN BE34 IOSTANDARD LVCMOS18 } [get_ports { CAM_SCL }]; #PCAM_SCL #FMC_LA019_P
+#set_property -dict { PACKAGE_PIN BC33 IOSTANDARD LVCMOS18 } [get_ports { CAM_SDA }]; #PCAM_SDA #FMC_LA20_P
+#set_property -dict { PACKAGE_PIN BD28 IOSTANDARD LVCMOS18 } [get_ports { CAM_INT }]; # #FMC_LA08_P
+#set_property -dict { PACKAGE_PIN AT37 IOSTANDARD LVCMOS18 } [get_ports { CAM_TRIG }]; #PMOD2_10_FPGA #NOT USED IN HPS > left at pmod
+
+
+### Nexus PMOD1 and 2 for Valiant camera parallel interace Connector (J255), Bank63 LVCMOS18
+set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS18 } [get_ports { IOB0 }]; #PMOD1_7_FPGA -ISP_DVP_D0
+set_property -dict { PACKAGE_PIN AL29 IOSTANDARD LVCMOS18 } [get_ports { IOB1 }]; #PMOD1_1_FPGA -ISP_DVP_D1
+set_property -dict { PACKAGE_PIN AL31 IOSTANDARD LVCMOS18 } [get_ports { IOB2 }]; #PMOD1_8_FPGA -ISP_DVP_D2
+set_property -dict { PACKAGE_PIN AL32 IOSTANDARD LVCMOS18 } [get_ports { IOB3 }]; #PMOD1_2_FPGA -ISP_DVP_D3
+set_property -dict { PACKAGE_PIN AL30 IOSTANDARD LVCMOS18 } [get_ports { IOB4 }]; #PMOD1_9_FPGA -ISP_DVP_D4
+set_property -dict { PACKAGE_PIN AM29 IOSTANDARD LVCMOS18 } [get_ports { IOB5 }]; #PMOD1_3_FPGA -ISP_DVP_D5
+set_property -dict { PACKAGE_PIN AM33 IOSTANDARD LVCMOS18 } [get_ports { IOB6 }]; #PMOD1_10_FPGA -ISP_DVP_D6
+set_property -dict { PACKAGE_PIN AM32 IOSTANDARD LVCMOS18 } [get_ports { IOB7 }]; #PMOD1_4_FPGA -ISP_DVP_D7
+set_property -dict { PACKAGE_PIN AN33 IOSTANDARD LVCMOS18 } [get_ports { IOB8 }]; #PMOD2_1_FPGA -ISP_DVP_PCLK
+#set_property -dict { PACKAGE_PIN AN34 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_MCLK }]; #PMOD2_7_FPGA -ISP_DVP_MCLK
+set_property -dict { PACKAGE_PIN AM31 IOSTANDARD LVCMOS18 } [get_ports { IOA2 }]; #PMOD2_2_FPGA -ISP_DVP_VSYNC
+set_property -dict { PACKAGE_PIN AP33 IOSTANDARD LVCMOS18 } [get_ports { IOA3 }]; #PMOD2_8_FPGA -ISP_DVP_HSYNC
+set_property -dict { PACKAGE_PIN AR35 IOSTANDARD LVCMOS18 } [get_ports { IOA4 }]; #PCAM_SCL/PMOD2_9_FPGA -CAM_SCL
+set_property -dict { PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 } [get_ports { IOA5 }]; #PCAM_SDA/PMOD2_3_FPGA -CAM_SDA
+set_property -dict { PACKAGE_PIN AT36 IOSTANDARD LVCMOS18 } [get_ports { IOA6 }]; #PMOD2_4_FPGA -CAM_INT
+set_property -dict { PACKAGE_PIN AT37 IOSTANDARD LVCMOS18 } [get_ports { IOA7 }]; #PMOD2_10_FPGA -CAM_TRIG
+
+
+
+# PMOD4: (Bank62) Temporarily repurposed for demo display. SPI + 2x (incl CS) + 2x GPIO Required.
+set_property -dict { PACKAGE_PIN AY38 IOSTANDARD LVCMOS18 } [get_ports { IOB10 }]; #PMOD4_1_FPGA -SPI_HOST2_D0
+set_property -dict { PACKAGE_PIN BA39 IOSTANDARD LVCMOS18 } [get_ports { IOB11 }]; #PMOD4_2_FPGA -SPI_HOST2_D1
+set_property -dict { PACKAGE_PIN AW35 IOSTANDARD LVCMOS18 } [get_ports { IOB12 }]; #PMOD4_3_FPGA -SPI_HOST2_D2
+set_property -dict { PACKAGE_PIN AY35 IOSTANDARD LVCMOS18 } [get_ports { IOR11 }]; #PMOD4_4_FPGA -SPI_HOST2_D3
+set_property -dict { PACKAGE_PIN AY40 IOSTANDARD LVCMOS18 } [get_ports { IOR12 }]; #PMOD4_7_FPGA -SPI_HOST2_CLK
+set_property -dict { PACKAGE_PIN BA40 IOSTANDARD LVCMOS18 } [get_ports { IOR13 }]; #PMOD4_8_FPGA -SPI_HOST2_CS_L
+#set_property -dict { PACKAGE_PIN AW36 IOSTANDARD LVCMOS18 } [get_ports { IOB7 }]; #PMOD4_9_FPGA
+#set_property -dict { PACKAGE_PIN BC40 IOSTANDARD LVCMOS18 } [get_ports { IOB8 }]; #PMOD4_10_FPGA
+
+##OLD## J271 pins for prototyping. Bank 63 -- IOB7/8 previously for display control moved. IOD0/1 will be used for display control signals for demo.
+# set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P1
+# set_property -dict { PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P3
+# set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P5
+# set_property -dict { PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P7
+# set_property -dict { PACKAGE_PIN AG31 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P9
+# set_property -dict { PACKAGE_PIN AH31 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P11
+# set_property -dict { PACKAGE_PIN AG32 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P13
+#EXP1x10_J271_P19 held by IO_UPHY_DPPULLUP
+#EXP1x10_J271_P17 unused
+# set_property -dict { PACKAGE_PIN AG33 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P19
+
+###Unused Signals
+set_property -dict { PACKAGE_PIN BD13 IOSTANDARD LVCMOS18 } [get_ports { IO_TRIGGER }]; #FMC_HA02_P
+set_property -dict { PACKAGE_PIN BE13 IOSTANDARD LVCMOS18 } [get_ports { IO_CLKOUT }]; #FMC_HA02_N
+set_property -dict { PACKAGE_PIN BD12 IOSTANDARD LVCMOS18 } [get_ports { USB_P }]; #FMC_HA03_P
+set_property -dict { PACKAGE_PIN BE12 IOSTANDARD LVCMOS18 } [get_ports { USB_N }]; #FMC_HA03_N
+set_property -dict { PACKAGE_PIN BB13 IOSTANDARD LVCMOS18 } [get_ports { IO_USB_SENSE0 }]; #FMC_HA04_P
+set_property -dict { PACKAGE_PIN BB12 IOSTANDARD LVCMOS18 } [get_ports { IO_USB_DNPULLUP0 }]; #FMC_HA04_N
+set_property -dict { PACKAGE_PIN BC11 IOSTANDARD LVCMOS18 } [get_ports { IO_USB_DPPULLUP0 }]; #FMC_HA05_P
+set_property -dict { PACKAGE_PIN BD11 IOSTANDARD LVCMOS18 } [get_ports { IOB9 }]; #FMC_HA05_N
+#MISC from PMOD3
+set_property -dict { PACKAGE_PIN BE15 IOSTANDARD LVCMOS18 } [get_ports { IOA0 }]; #FMC_HA06_P
+set_property -dict { PACKAGE_PIN BF15 IOSTANDARD LVCMOS18 } [get_ports { IOC6 }]; #FMC_HA06_N
+set_property -dict { PACKAGE_PIN BE14 IOSTANDARD LVCMOS18 } [get_ports { IOC7 }]; #FMC_HA07_P
+set_property -dict { PACKAGE_PIN BF14 IOSTANDARD LVCMOS18 } [get_ports { IOA1 }]; #FMC_HA07_N
+set_property -dict { PACKAGE_PIN BC15 IOSTANDARD LVCMOS18 } [get_ports { IOC9 }]; #FMC_HA08_P
+
+
+## TI TUSB1T1105AMHX USB Transceiver "usbdev" testing, Bank 64 LVCMOS18
+#set_property -dict { PACKAGE_PIN AW23 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DP_TX }]; #USB0_VPO
+#set_property -dict { PACKAGE_PIN AW22 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DN_TX }]; #USB0_VMO
+#set_property -dict { PACKAGE_PIN AY22 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DP_RX }]; #USB0_VP
+#set_property -dict { PACKAGE_PIN BA22 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DN_RX }]; #USB0_VM
+## USRUSB_SOFTCONN(not used, conneted to xxxxx as placeholder)
+#set_property -dict { PACKAGE_PIN AH33 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_DPPULLUP }]; ## MOVED TO EXP1x10_J271_P15 to clear up PMOD4
+## Roman added USB voltage sense pin to AY17 of Bank65 of Nexus FPGA in the latest revision board.
+#set_property -dict { PACKAGE_PIN AY17 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_SENSE }]; #USB0_VBUS_SENSEB
+#set_property -dict { PACKAGE_PIN AU21 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_OE_N }]; #USB0_OEB
+#set_property -dict { PACKAGE_PIN AV21 IOSTANDARD LVCMOS18 } [get_ports { IO_UPHY_D_RX }]; #USB0_RCV
+#set_property -dict { PACKAGE_PIN BA21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports { IO_UPHY_SPD }]; #USB0_MODE
+#set_property -dict { PACKAGE_PIN AT21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports { IO_UPHY_SUS }]; #USB0_CFG
+
+## UART0 (Security Core UART0, default connect to FTDI CDBUS, late may map to SOM_FPGA_GPIO for in-system monitor)
+## Bank 65, LVCMOS18
+set_property -dict { PACKAGE_PIN BF20 IOSTANDARD LVCMOS18 } [get_ports { IOC4 }]; #FTDI_RX_FPGA_TX_1P8 - Sencha UART0 TX FTDI
+set_property -dict { PACKAGE_PIN BD20 IOSTANDARD LVCMOS18 } [get_ports { IOC3 }]; #FTDI_TX_FPGA_RX_1P8 - Sencha UART0 RX FTDI
+#set_property -dict { PACKAGE_PIN BC20 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #FTDI_FPGA_CTS - not used in Sencha
+#set_property -dict { PACKAGE_PIN BE20 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #FTDI_FPGA_RTS - not used in Sencha
+
+## UART1 (Security Core UART1 or SMC core UART, default connect to CP2103 U250, Bank 74, LVCMOS18
+## late may map to SOM_FPGA_GPIO for in-system monitor)
+set_property -dict { PACKAGE_PIN R23 IOSTANDARD LVCMOS18 } [get_ports { IOC11 }]; #FPGA_UART_TX - Sencha UART1 TX CP210 USB
+set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS18 } [get_ports { IOC10 }]; #FPGA_UART_RX - Sencha UART1 RX CP210 USB
+#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #FPGA_UART_CTS - not used in Sencha
+#set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #FPGA_UART_RTS - not used in Sencha
+
+## Configuration options, can be used for all designs
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+## Different from 7 Series or UltraScale, no CFGBVS pin in UltraScal+ device,
+## Became RSVGND pin and need to be connected to GND (as Nexus schematic pin AB11)
+#set_property CFGBVS GND [current_design]
+
+# Bootstrap pins
+set_property -dict { PACKAGE_PIN AU18 IOSTANDARD LVCMOS18 } [get_ports { IOC0 }]; # Bootstrap0
+set_property -dict { PACKAGE_PIN AU19 IOSTANDARD LVCMOS18 } [get_ports { IOC1 }]; # Bootstrap1
+set_property -dict { PACKAGE_PIN AR20 IOSTANDARD LVCMOS18 } [get_ports { IOC2 }]; # Bootstrap2
+set_property -dict { PACKAGE_PIN AR19 IOSTANDARD LVCMOS18 } [get_ports { POR_N }];
+
+# Pushbuttons and LEDs on 1.2V Bank 68
+set_property -dict { PACKAGE_PIN U32 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { POR_BUTTON_N }]; #PBC3 BUTTON
+
+set_property -dict { PACKAGE_PIN W31 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR5 }]; #PBA1 BUTTON
+set_property -dict { PACKAGE_PIN U33 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR6 }]; #PBA2 BUTTON
+set_property -dict { PACKAGE_PIN T35 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR7 }]; #PBA3 BUTTON
+# IOR8, IOR9 are direct connect pins
+set_property -dict { PACKAGE_PIN W32 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR10 }]; #PBB1 BUTTON
+#set_property -dict { PACKAGE_PIN V30 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR11 }]; #PBB2 BUTTON MOVED TO SPI
+#set_property -dict { PACKAGE_PIN T36 DRIVE 8 IOSTANDARD LVCMOS12 } [get_ports { IOR12 }]; #PBB3 BUTTON MOVED TO SPI
+
+# Placeholder 1.8V BANK63 GPIO J2612
+set_property -dict { PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18 } [get_ports { IOR8 }]; #FPGA_EXP6X1_2_P4 DIRECT ec_rst_l
+set_property -dict { PACKAGE_PIN AJ32 IOSTANDARD LVCMOS18 } [get_ports { IOR9 }]; #FPGA_EXP6X1_2_P5 DIRECT flash_wp_l
+# Placeholder 1.8V BANK63 GPIO J2613
+#set_property -dict { PACKAGE_PIN AP38 IOSTANDARD LVCMOS18 } [get_ports { IOR13 }]; #FPGA_EXP6X1_3_P5
diff --git a/hw/top_sencha/data/placement.xdc b/hw/top_sencha/data/placement.xdc
new file mode 100644
index 0000000..c9e7bb2
--- /dev/null
+++ b/hw/top_sencha/data/placement.xdc
@@ -0,0 +1,24 @@
+# Copyright 2024 Google LLC
+# Copyright lowRISC contributors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# While the code below looks messy, it was taken directly from a vivado example
+# See here (https://www.xilinx.com/support/answers/66386.html)
+# See also this link (https://github.com/lowRISC/opentitan/pull/8138#issuecomment-916696830)
+# for a thorough explanation of why such a custom placement helps.
+# Note the placement location was not chosen through any systematic means, but through trial
+# and error, it may become necessary in the future to tweak this if other congestion
+# issues arise.
+
+## Delete placement constraint for now since it helps timing closure, but will keep the file for now.
diff --git a/hw/top_sencha/data/standalone_sw_testplan.hjson b/hw/top_sencha/data/standalone_sw_testplan.hjson
new file mode 100644
index 0000000..a2db2be
--- /dev/null
+++ b/hw/top_sencha/data/standalone_sw_testplan.hjson
@@ -0,0 +1,47 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+{
+ name: "self-contained-tests"
+
+ testpoints: [
+ {
+ name: flash_ctrl
+ desc: '''This test checks for correct sanity behavior of the flash.
+ It ensures the flash controller is able to program, read, and page erase fixed locations in multiple flash banks.
+ It also performs a sanity region protection check to make sure a protected page cannot be modified.
+ When the test passes, it will output "PASS!".'''
+ stage: V1
+ tests: ["flash_test"]
+ }
+ {
+ name: hmac
+ desc: '''This test checks for basic functionality of the sha256 engine inside HMAC.
+ It computes the hash of a known input and compares it against the known digest.
+ When the test passes, it will output "PASS!".'''
+ stage: V1
+ tests: ["sha256_test"]
+ }
+ {
+ name: rv_timer
+ desc: '''This test checks for basic timer and interrupt functionality.
+ The test rests in a loop and does not break out until the interrupt handling routine sets a specific value.
+ If the interrupt handling is incorrect, the test will never complete.
+ When the test passes, it will output "PASS!".'''
+ stage: V1
+ tests: ["rv_timer_test"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/data/synth.xdc b/hw/top_sencha/data/synth.xdc
new file mode 100644
index 0000000..8303f9b
--- /dev/null
+++ b/hw/top_sencha/data/synth.xdc
@@ -0,0 +1,23 @@
+# Copyright 2024 Google LLC
+# Copyright lowRISC contributors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# File is configured in vivado_setup_hooks.tcl to only be used for synth
+
+# Force SMC to use ULTRARAM instead of BRAM for memory
+set_property ram_style ultra [get_cells -hierarchical -filter {NAME =~ "*u_ram1p_ram_smc/u_mem/gen_generic.u_impl_generic/mem_reg*"} ]
+
+# Force ML CORE to use ULTRARAM instead of BRAM for memory
+set_property ram_style ultra [get_cells -hierarchical -filter {NAME =~ "*u_ml_dmem/u_ram1p_dmem/u_mem/gen_generic.u_impl_generic/mem_reg*"} ]
diff --git a/hw/top_sencha/data/top_sencha.hjson b/hw/top_sencha/data/top_sencha.hjson
new file mode 100644
index 0000000..be0c1ed
--- /dev/null
+++ b/hw/top_sencha/data/top_sencha.hjson
@@ -0,0 +1,1837 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// TOP Sencha configuration
+{ name: "sencha",
+ type: "top",
+
+ /////////////////////////////////////////////////////////////
+ // Seed for compile-time random constants //
+ // NOTE: REPLACE THIS WITH A NEW VALUE BEFORE THE TAPEOUT //
+ /////////////////////////////////////////////////////////////
+ rnd_cnst_seed: 4881560218908238235
+
+ // 32-bit datawidth
+ datawidth: "32",
+
+ // Power information for the design
+ power: {
+ // Power domains supported by the design
+ // Aon represents domain aon
+ // 0 represents domain 0
+ domains: ["Aon", "0"],
+
+ // Default power domain used for the design
+ default: "0"
+ },
+
+ // This is the clock data structure of the design.
+ // The hier path refers to the clock reference path (struct / port)
+ // - The top/ext desgination follows the same scheme as inter-module
+ // The src key indicates the raw clock sources in the design
+ // The groups key indicates the various clock groupings in the design
+ clocks: {
+
+ hier_paths: {
+ top: "clkmgr_aon_clocks.", // top level is a struct
+ ext: "", // ext is a port of the clock name
+ lpg: "clkmgr_aon_cg_en.", // top level struct for alert lpg reset enables
+ },
+
+ // Clock Source attributes
+ // name: Name of group.
+ // aon: Whether the clock is free running all the time.
+ // If it is, the clock is not hanlded by clkmgr.
+ // freq: Absolute frequency of clk in Hz
+ // ref: indicates the clock is used as a reference for measurement.
+ srcs: [
+ { name: "main", aon: "no", freq: "96000000" }
+ { name: "io", aon: "no", freq: "96000000" }
+ { name: "usb", aon: "no", freq: "48000000" }
+ { name: "aon", aon: "yes", freq: "200000", ref: true}
+ { name: "smc", aon: "no", freq: "96000000" }
+ { name: "ml", aon: "no", freq: "96000000" }
+ { name: "video",aon: "no", freq: "96000000" }
+ { name: "audio",aon: "no", freq: "48000000" } // TODO: Change to 12.288Mhz later to match ASIC
+ ],
+
+ // Derived clock source attributes
+ // name: Name of group.
+ // aon: Whether the clock is free running all the time.
+ // If it is, the clock is not hanlded by clkmgr.
+ // freq: Absolute frequency of clk in Hz
+ // src: From which clock source is the clock derived
+ // div: Ratio between derived clock and source clock
+ derived_srcs: [
+ { name: "io_div2", aon: "no", div: 2, src: "io", freq: "48000000" }
+ { name: "io_div4", aon: "no", div: 4, src: "io", freq: "24000000" }
+ ],
+
+ // Clock Group attributes
+ // name: name of group.
+ //
+ // src: The hierarchical source of the clock
+ // "ext" - clock is supplied from a port of the top module
+ // "top" - clock is supplied from a net inside the top module
+ //
+ // sw_cg: whether software is allowed to gate the clock
+ // "no" - software is not allowed to gate clocks
+ // "yes" - software is allowed to gate clocks
+ // "hint" - software can provide a hint, and hw controls the rest
+ //
+ // unique: whether each module in the group can be separately gated
+ // if sw_cg is "no", this field has no meaning
+ // "yes" - each clock is individually controlled
+ // "no" - the group is controlled as one single unit
+ //
+ // The powerup and proc groups are unique.
+ // The powerup group of clocks do not feed through the clock
+ // controller as they manage clock controller behavior
+ // The proc group is not peripheral, and directly hardwired
+
+ groups: [
+ // the powerup group is used exclusively by clk/pwr/rstmgr/pinmux
+ { name: "ast", src:"ext", sw_cg: "no" }
+ { name: "powerup", src:"top", sw_cg: "no" }
+ { name: "trans", src:"top", sw_cg: "hint", unique: "yes", }
+ { name: "infra", src:"top", sw_cg: "no", }
+ { name: "secure", src:"top", sw_cg: "no" }
+ { name: "peri", src:"top", sw_cg: "yes", unique: "no" }
+ { name: "timers", src:"top", sw_cg: "no" }
+ ],
+ },
+
+ // This is the reset data structure of the design.
+ // The hier path refers to the reset reference path (struct / port)
+ // - The top/ext desgination follows the same scheme as inter-module
+ // The node key represents all the known resets in the design
+ resets: {
+
+ hier_paths: {
+ top: "rstmgr_aon_resets.", // top level is a struct
+ ext: "", // ext is a port of the clock name
+ lpg: "rstmgr_aon_rst_en.", // top level struct for alert lpg reset enables
+ },
+
+ // Reset node attributes
+ // name: name of reset.
+ //
+ // gen: whether the reset is generated
+ // true: it is a generated reset inside rstmgr
+ // false: it is a hardwired design reset inside rstmgr (roots and por)
+ // For non-generated resets, the parent / domain definitions have no meaning.
+ //
+ // type: the reset type [ext, top]
+ // ext: the reset is coming in from the ports, external to sencha
+ // int: the reset is only used inside rstmgr
+ // top: the reset is output from rstmgr to top level struct
+ //
+ // parent: The parent reset
+ // If type is "ext", there is no root, since it is external
+ //
+ // domains: The power domains of a particular reset
+ // This is a list of of the supported power domains.
+ // Valid values are Aon and (power domain)0 ~ (power domain)1.
+ // If no value is supplied, the default is specified by the power configuration.
+ //
+ // clk: related clock domain for synchronous release
+ // If type is "por", there is not related clock, since it is
+ // likely external or generated from a voltage comparator
+ //
+ nodes: [
+ { name: "por_aon", gen: false, type: "top", clk: "aon" }
+ { name: "lc_src", gen: false, type: "int", clk: "io_div4" }
+ { name: "sys_src", gen: false, type: "int", clk: "io_div4" }
+ { name: "por", gen: true, type: "top", parent: "por_aon", clk: "main" }
+ { name: "por_io", gen: true, type: "top", parent: "por_aon", clk: "io" }
+ { name: "por_io_div2", gen: true , type: "top", parent: "por_aon", clk: "io_div2" }
+ { name: "por_io_div4", gen: true , type: "top", parent: "por_aon", clk: "io_div4" }
+ { name: "por_usb", gen: true , type: "top", parent: "por_aon", clk: "usb" }
+ { name: "por_smc", gen: true, type: "top", parent: "por_aon", clk: "smc" }
+ { name: "por_ml", gen: true , type: "top", parent: "por_aon", clk: "ml" }
+ { name: "por_video", gen: true , type: "top", parent: "por_aon", clk: "video" }
+ { name: "por_audio", gen: true , type: "top", parent: "por_aon", clk: "audio" }
+ { name: "lc", gen: true, type: "top", parent: "lc_src", clk: "main" }
+ { name: "lc_aon", gen: true, type: "top", parent: "lc_src", clk: "aon" }
+ { name: "lc_io", gen: true, type: "top", parent: "lc_src", clk: "io" }
+ { name: "lc_io_div2", gen: true, type: "top", parent: "lc_src", clk: "io_div2" }
+ { name: "lc_io_div4", gen: true, type: "top", parent: "lc_src", clk: "io_div4" }
+ { name: "lc_usb", gen: true, type: "top", parent: "lc_src", clk: "usb" }
+ { name: "lc_smc", gen: true, type: "top", parent: "lc_src", clk: "smc" }
+ { name: "lc_ml", gen: true, type: "top", parent: "lc_src", clk: "ml" }
+ { name: "lc_video", gen: true, type: "top", parent: "lc_src", clk: "video" }
+ { name: "lc_audio", gen: true, type: "top", parent: "lc_src", clk: "audio" }
+ { name: "sys", gen: true, type: "top", parent: "sys_src", clk: "main" }
+ { name: "sys_io_div4", gen: true, type: "top", parent: "sys_src", clk: "io_div4" }
+ { name: "spi_device", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true }
+ { name: "spi_host0", gen: true, type: "top", parent: "lc_src", clk: "io", sw: true }
+ { name: "spi_host1", gen: true, type: "top", parent: "lc_src", clk: "io", sw: true }
+ { name: "spi_host2", gen: true, type: "top", parent: "lc_src", clk: "io", sw: true }
+ { name: "usb", gen: true, type: "top", parent: "lc_src", clk: "usb", sw: true }
+ { name: "usb_aon", gen: true, type: "top", parent: "lc_src", clk: "aon", sw: true }
+ { name: "i2c0", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true },
+ { name: "i2c1", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true },
+ { name: "i2c2", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true },
+ { name: "smc", gen: true, type: "top", parent: "lc_src", clk: "smc", sw: true },
+ { name: "ml", gen: true, type: "top", parent: "lc_src", clk: "ml", sw: true },
+ { name: "cam_i2c", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true },
+ { name: "video", gen: true, type: "top", parent: "lc_src", clk: "video", sw: true },
+ { name: "audio", gen: true, type: "top", parent: "lc_src", clk: "audio", sw: true },
+ ]
+ }
+
+ // Number of cores: used in rv_plic and timer
+ num_cores: "2",
+
+ // `module` defines the peripherals.
+ // Details come from each modules' config file `ip.hjson`:
+ // attr: There are a few types of modules supported
+ // normal(default): Normal, non-templated modules that will be instantiated
+ // templated: These modules are templated and must be run through topgen
+ // ipgen: These modules are the same as templated but use the new ipgen flow
+ // reggen_top: These modules are not templated, but need to have reggen run
+ // because they live in hw/top_* (target) or matcha/hw/ip (common Shodan IP),
+ // instead of$(OpenTitan)/hw/ip_*. These modules are also instantiated in the top level.
+ // reggen_only: Similar to reggen_top, but are not instantiated in the top level.
+ // intr_to:
+ // smc: These modules with this parameter will send interrupt to smc core.
+ // sec: If not defined (or sec), the default interrupt target is security core.
+ module: [
+ { name: "uart0", // instance name
+ type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
+ // and `hw/ip/{type}`
+
+ // clock connections defines the port to top level clock connection
+ // the ip.hjson will declare the clock port names
+ // If none are defined at ip.hjson, clk_i is used by default
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ // reset connections defines the port to top level reset connection
+ // the ip.hjson will declare the reset port names
+ // If none are defined at ip.hjson, rst_ni is used by default
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x40000000",
+ },
+ { name: "uart1", // instance name
+ type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
+ // and `hw/ip/{type}`
+
+ // clock connections defines the port to top level clock connection
+ // the ip.hjson will declare the clock port names
+ // If none are defined at ip.hjson, clk_i is used by default
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ // reset connections defines the port to top level reset connection
+ // the ip.hjson will declare the reset port names
+ // If none are defined at ip.hjson, rst_ni is used by default
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x40010000",
+ },
+ { name: "uart2", // instance name
+ type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
+ // and `hw/ip/{type}`
+
+ // clock connections defines the port to top level clock connection
+ // the ip.hjson will declare the clock port names
+ // If none are defined at ip.hjson, clk_i is used by default
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ // reset connections defines the port to top level reset connection
+ // the ip.hjson will declare the reset port names
+ // If none are defined at ip.hjson, rst_ni is used by default
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x40020000",
+ },
+ { name: "uart3", // instance name
+ type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
+ // and `hw/ip/{type}`
+
+ // clock connections defines the port to top level clock connection
+ // the ip.hjson will declare the clock port names
+ // If none are defined at ip.hjson, clk_i is used by default
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ // reset connections defines the port to top level reset connection
+ // the ip.hjson will declare the reset port names
+ // If none are defined at ip.hjson, rst_ni is used by default
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x40030000",
+ },
+ { name: "gpio",
+ type: "gpio",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x40040000",
+ param_decl: {
+ GpioAsyncOn: "1"
+ }
+ }
+ { name: "spi_device",
+ type: "spi_device",
+ clock_srcs: {clk_i: "io_div4", scan_clk_i: "io_div2"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "spi_device"},
+ base_addr: "0x40050000",
+ },
+ { name: "i2c0",
+ type: "i2c",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "i2c0"},
+ base_addr: "0x40080000",
+ },
+ { name: "i2c1",
+ type: "i2c",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "i2c1"},
+ base_addr: "0x40090000",
+ },
+ { name: "i2c2",
+ type: "i2c",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "i2c2"},
+ base_addr: "0x400A0000",
+ },
+ { name: "pattgen",
+ type: "pattgen",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x400E0000",
+ },
+ { name: "rv_timer",
+ type: "rv_timer",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "timers",
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x40100000",
+ },
+ { name: "otp_ctrl",
+ type: "otp_ctrl",
+ clock_srcs: {clk_i: "io_div4", clk_edn_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc_io_div4", rst_edn_ni: "lc"},
+ base_addrs: {core: "0x40130000", prim: "0x40132000"}
+ },
+ { name: "lc_ctrl",
+ type: "lc_ctrl",
+ clock_srcs: {clk_i: "io_div4", clk_kmac_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc_io_div4", rst_kmac_ni: "lc"},
+ base_addr: "0x40140000",
+ param_decl: {
+ ChipGen: "16'h 0000",
+ ChipRev: "16'h 0000",
+ IdcodeValue: "jtag_id_pkg::JTAG_IDCODE",
+ },
+ },
+ { name: "alert_handler",
+ type: "alert_handler",
+ clock_srcs: {clk_i: "io_div4", clk_edn_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc_io_div4", rst_edn_ni: "lc"},
+ base_addr: "0x40150000",
+ attr: "ipgen",
+ },
+ { name: "spi_host0",
+ type: "spi_host",
+ clock_srcs: {clk_i: "io"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "spi_host0"},
+ base_addr: "0x40300000",
+ },
+ { name: "spi_host1",
+ type: "spi_host",
+ clock_srcs: {clk_i: "io"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "spi_host1"},
+ base_addr: "0x40310000",
+ },
+ { name: "usbdev",
+ type: "usbdev",
+ clock_srcs: {clk_i: "usb", clk_aon_i: "aon"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "usb", rst_aon_ni: "usb_aon"},
+ base_addr: "0x40320000",
+ param_decl: {
+ RcvrWakeTimeUs: "100"
+ },
+ },
+ { name: "pwrmgr_aon",
+ type: "pwrmgr",
+ clock_group: "powerup",
+ clock_srcs: {
+ clk_i: "io_div4",
+ clk_slow_i: "aon",
+ clk_lc_i: "io_div4",
+ clk_esc_i: {
+ clock: "io_div4",
+ group: "secure"
+ }
+ },
+ reset_connections: {
+ rst_ni: {
+ name: "por_io_div4",
+ domain: "Aon"
+ },
+ rst_main_ni: {
+ name: "por_aon",
+ domain: "0"
+ },
+ rst_lc_ni: {
+ name: "lc_io_div4",
+ domain: "Aon"
+ },
+ rst_esc_ni: {
+ name: "lc_io_div4",
+ domain: "Aon"
+ },
+ rst_slow_ni: {
+ name: "por_aon",
+ domain: "Aon",
+ },
+ }
+ domain: ["Aon", "0"],
+ base_addr: "0x40400000",
+ attr: "templated",
+
+ },
+ { name: "rstmgr_aon",
+ type: "rstmgr",
+ clock_srcs: {
+ clk_i: {
+ clock: "io_div4",
+ group: "powerup"
+ },
+ clk_por_i: "io_div4", clk_aon_i: "aon", clk_main_i: "main", clk_io_i: "io", clk_usb_i: "usb",
+ clk_io_div2_i: "io_div2", clk_io_div4_i: "io_div4",
+ clk_smc_i: "smc", clk_ml_i: "ml", clk_video_i: "video", clk_audio_i: "audio"
+ },
+ clock_group: "powerup",
+ reset_connections: {
+ rst_ni: {
+ name: "lc_io_div4",
+ domain: "Aon"
+ },
+ rst_por_ni: {
+ name: "por_io_div4",
+ domain: "Aon"
+ },
+ }
+ domain: ["Aon", "0"],
+ base_addr: "0x40410000",
+ attr: "templated",
+ },
+ { name: "clkmgr_aon",
+ type: "clkmgr",
+ clock_srcs: {
+ clk_i: "io_div4",
+ clk_main_i: {
+ group: "ast",
+ clock: "main"
+ },
+ clk_io_i: {
+ group: "ast",
+ clock: "io"
+ },
+ clk_usb_i: {
+ group: "ast",
+ clock: "usb"
+ },
+ clk_aon_i: {
+ group: "ast",
+ clock: "aon"
+ },
+ clk_ml_i: {
+ group: "ast",
+ clock: "ml"
+ },
+ clk_smc_i: {
+ group: "ast",
+ clock: "smc"
+ },
+ clk_video_i: {
+ group: "ast",
+ clock: "video"
+ },
+ clk_audio_i: {
+ group: "ast",
+ clock: "audio"
+ }
+ },
+ clock_group: "powerup",
+ reset_connections: {rst_ni: "lc_io_div4",
+ rst_aon_ni: "lc_aon"
+ rst_io_ni: "lc_io",
+ rst_io_div2_ni: "lc_io_div2",
+ rst_io_div4_ni: "lc_io_div4",
+ rst_main_ni: "lc",
+ rst_usb_ni: "lc_usb",
+ rst_smc_ni: "lc_smc",
+ rst_ml_ni: "lc_ml",
+ rst_video_ni: "lc_video",
+ rst_audio_ni: "lc_audio",
+ rst_root_ni: "por_io_div4",
+ rst_root_io_ni: "por_io",
+ rst_root_io_div2_ni: "por_io_div2",
+ rst_root_io_div4_ni: "por_io_div4",
+ rst_root_main_ni: "por",
+ rst_root_usb_ni: "por_usb",
+ rst_root_smc_ni: "por_smc",
+ rst_root_ml_ni: "por_ml",
+ rst_root_video_ni: "por_video",
+ rst_root_audio_ni: "por_audio",
+ },
+ domain: ["Aon"],
+ base_addr: "0x40420000",
+ attr: "templated",
+ },
+ { name: "sysrst_ctrl_aon",
+ type: "sysrst_ctrl",
+ clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc_io_div4", rst_aon_ni: "lc_aon"},
+ domain: ["Aon"],
+ base_addr: "0x40430000"
+ },
+ { name: "adc_ctrl_aon",
+ type: "adc_ctrl",
+ clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "lc_io_div4", rst_aon_ni: "lc_aon"},
+ domain: ["Aon"],
+ base_addr: "0x40440000"
+ },
+ { name: "pwm_aon",
+ type: "pwm",
+ clock_srcs: {clk_i: "io_div4", clk_core_i: "aon"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "lc_io_div4", rst_core_ni: "lc_aon"},
+ domain: ["Aon"],
+ base_addr: "0x40450000",
+ },
+ { name: "pinmux_aon",
+ type: "pinmux",
+ clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
+ clock_group: "powerup",
+ reset_connections: {rst_ni: "lc_io_div4",
+ rst_aon_ni: "lc_aon",
+ rst_sys_ni: "sys_io_div4"
+ },
+ domain: ["Aon"],
+ base_addr: "0x40460000",
+ attr: "templated",
+ },
+ { name: "aon_timer_aon",
+ type: "aon_timer",
+ clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
+ clock_group: "timers",
+ reset_connections: {rst_ni: "lc_io_div4", rst_aon_ni: "lc_aon"},
+ domain: ["Aon"],
+ base_addr: "0x40470000",
+ },
+ { name: "ast",
+ type: "ast",
+ clock_srcs: {
+ clk_ast_tlul_i: {
+ clock: "io_div4",
+ group: "infra"
+ },
+ clk_ast_adc_i: {
+ clock: "aon",
+ group: "peri"
+ },
+ clk_ast_alert_i: {
+ clock: "io_div4",
+ group: "secure"
+ }
+ clk_ast_es_i: {
+ clock: "main",
+ group: "secure"
+ }
+ clk_ast_rng_i: {
+ clock: "main",
+ group: "secure"
+ }
+ clk_ast_usb_i: {
+ clock: "usb",
+ group: "peri"
+ }
+ },
+ clock_group: "secure",
+ reset_connections: {
+ rst_ast_tlul_ni: {
+ name: "lc_io_div4",
+ domain: "0",
+ }
+ rst_ast_adc_ni: {
+ name: "lc_aon",
+ domain: "Aon"
+ },
+ rst_ast_alert_ni: {
+ name: "lc_io_div4",
+ domain: "0",
+ },
+ rst_ast_es_ni: {
+ name: "lc",
+ domain: "0",
+ },
+ rst_ast_rng_ni: {
+ name: "lc",
+ domain: "0",
+ },
+ rst_ast_usb_ni: {
+ name: "usb",
+ domain: "0"
+ }
+ },
+ domain: ["Aon", "0"],
+ base_addr: "0x40480000",
+ attr: "reggen_only",
+ },
+ { name: "sensor_ctrl",
+ type: "sensor_ctrl",
+ clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc_io_div4", rst_aon_ni: "lc_aon"},
+ domain: ["Aon"],
+ base_addr: "0x40490000",
+ attr: "reggen_top",
+ },
+ { name: "sram_ctrl_ret_aon",
+ type: "sram_ctrl",
+ clock_srcs: {clk_i: "io_div4", clk_otp_i: "io_div4"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "lc_io_div4", rst_otp_ni: "lc_io_div4"}
+ domain: ["Aon"],
+ param_decl: {
+ InstrExec: "0",
+ }
+ base_addrs: {regs: "0x40500000", ram: "0x40600000"},
+ // Memory regions must be associated with a dedicated
+ // TL-UL device interface.
+ memory: {
+ ram: {
+ label: "ram_ret_aon",
+ swaccess: "rw",
+ data_intg_passthru: "true",
+ exec: "True",
+ byte_write: "True",
+ size: "0x1000"
+ }
+ }
+ },
+ { name: "flash_ctrl",
+ type: "flash_ctrl",
+ clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"},
+ base_addrs: {core: "0x41000000", prim: "0x41008000", mem: "0x20000000"}
+ param_decl: {
+ ProgFifoDepth: "4",
+ }
+ memory: {
+ mem: {
+ label: "eflash",
+ swaccess: "ro",
+ data_intg_passthru: "true",
+ exec: "True",
+ byte_write: "False",
+ config: {
+ type: "flash",
+ banks: 2,
+ pages_per_bank: 256,
+ program_resolution: 8, // maximum number of flash words allowed to program at one time
+ }
+ }
+ }
+ attr: "templated",
+ },
+ { name: "rv_dm",
+ type: "rv_dm",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "sys"},
+ param_decl: {
+ IdcodeValue: "jtag_id_pkg::JTAG_IDCODE",
+ }
+ // Note that this module also contains a bus host.
+ base_addrs: {mem: "0x00004000", regs: "0x00006000"}
+ },
+ { name: "rv_plic",
+ type: "rv_plic",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x48000000",
+ attr: "ipgen",
+ },
+ { name: "aes",
+ type: "aes",
+ clock_srcs: {clk_i: "main", clk_edn_i: "main"},
+ clock_group: "trans",
+ reset_connections: {rst_ni: "lc", rst_edn_ni: "lc"},
+ param_decl: {
+ SecMasking: "1",
+ SecSBoxImpl: "aes_pkg::SBoxImplDom"
+ }
+ base_addr: "0x41100000",
+ },
+ { name: "hmac",
+ type: "hmac",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "trans",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x41110000",
+ },
+ { name: "kmac",
+ type: "kmac",
+ param_decl: {
+ EnMasking: "1",
+ }
+ clock_srcs: {clk_i: "main", clk_edn_i: "main"}
+ clock_group: "trans"
+ reset_connections: {rst_ni: "lc", rst_edn_ni: "lc"}
+ base_addr: "0x41120000"
+ },
+ { name: "otbn",
+ type: "otbn",
+ clock_srcs: {
+ clk_i: {
+ clock: "main",
+ group: "trans"
+ },
+ clk_edn_i: {
+ clock: "main",
+ group: "secure"
+ },
+ clk_otp_i: {
+ clock: "io_div4",
+ group: "secure"
+ },
+ },
+ clock_group: "trans",
+ reset_connections: {rst_ni: "lc", rst_edn_ni: "lc", rst_otp_ni: "lc_io_div4"},
+ base_addr: "0x41130000",
+ },
+ { name: "keymgr",
+ type: "keymgr",
+ clock_srcs: {clk_i: "main", clk_edn_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc", rst_edn_ni: "lc"},
+ base_addr: "0x41140000",
+ },
+ { name: "csrng",
+ type: "csrng",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x41150000",
+ },
+ { name: "entropy_src",
+ type: "entropy_src",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x41160000",
+ },
+ { name: "edn0",
+ type: "edn",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x41170000",
+ },
+ { name: "edn1",
+ type: "edn",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x41180000",
+ },
+ { name: "sram_ctrl_main",
+ type: "sram_ctrl",
+ clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"},
+ param_decl: {
+ InstrExec: "1",
+ }
+ base_addrs: {regs: "0x411C0000", ram: "0x10000000"},
+ // Memory regions must be associated with a dedicated
+ // TL-UL device interface.
+ memory: {
+ ram: {
+ label: "ram_main",
+ swaccess: "rw",
+ data_intg_passthru: "true",
+ exec: "True",
+ byte_write: "True",
+ size: "0x20000"
+ }
+ }
+ },
+ { name: "rom_ctrl",
+ type: "rom_ctrl",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "lc"},
+ base_addrs: {rom: "0x00008000", regs: "0x411e0000"}
+ memory: {
+ rom: {
+ label: "rom",
+ swaccess: "ro",
+ data_intg_passthru: "true",
+ exec: "True",
+ byte_write: "False",
+ size: "0x8000"
+ data_intg_passthru: "True"
+ }
+ },
+ param_decl: {
+ SecDisableScrambling: "1'b0"
+ }
+ },
+ { name: "rv_core_ibex_sec",
+ type: "rv_core_ibex",
+ param_decl: {PMPEnable: "1",
+ PMPGranularity: "0",
+ PMPNumRegions: "16",
+ MHPMCounterNum: "10",
+ MHPMCounterWidth: "32",
+ RV32E: "0",
+ RV32M: "ibex_pkg::RV32MSingleCycle",
+ RV32B: "ibex_pkg::RV32BOTEarlGrey",
+ RegFile: "ibex_pkg::RegFileFF",
+ BranchTargetALU: "1",
+ WritebackStage: "1",
+ ICache: "1",
+ ICacheECC: "1",
+ ICacheScramble: "1",
+ BranchPredictor: "0",
+ DbgTriggerEn: "1",
+ DbgHwBreakNum: "4",
+ SecureIbex: "1",
+ DmHaltAddr: "tl_main_pkg::ADDR_SPACE_DBG + dm::HaltAddress[31:0]",
+ DmExceptionAddr: "tl_main_pkg::ADDR_SPACE_DBG + dm::ExceptionAddress[31:0]",
+ PipeLine: "0"
+ },
+ clock_srcs: {
+ clk_i: "main",
+ clk_edn_i: "main",
+ clk_esc_i: {
+ clock: "io_div4",
+ group: "secure",
+ }
+ clk_otp_i: {
+ clock: "io_div4",
+ group: "secure",
+ }
+ },
+ clock_group: "infra",
+ reset_connections: {rst_ni: "lc",
+ rst_edn_ni: "lc",
+ rst_esc_ni: "lc_io_div4",
+ rst_otp_ni: "lc_io_div4"},
+ base_addr: "0x411F0000",
+ },
+ {
+ name: "dma0",
+ type: "dma",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x40200000",
+ attr: "reggen_top",
+ },
+
+
+ // Modules for SMC complex
+ { name: "smc_uart",
+ type: "uart",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x54000000",
+ intr_to: "smc",
+ },
+ { name: "rv_timer_smc",
+ type: "rv_timer",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "timers",
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x54010000",
+ intr_to: "smc",
+ },
+ { name: "smc_ctrl",
+ type: "smc_ctrl",
+ clock_srcs: {clk_i: "smc"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "smc"},
+ base_addr: "0x54020000",
+ attr: "reggen_top",
+ },
+ { name: "cam_i2c",
+ type: "i2c",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "cam_i2c"},
+ base_addr: "0x54040000",
+ intr_to: "smc",
+ },
+ { name: "cam_ctrl",
+ type: "cam_ctrl",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "lc_io_div4"},
+ base_addr: "0x54050000",
+ intr_to: "smc",
+ attr: "reggen_top",
+ },
+ { name: "isp_wrapper",
+ type: "isp_wrapper",
+ clock_srcs: {clk_i: "video", clk_core_i: "video", clk_axi_i: "video"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "smc"}, // SW controlled reset
+ base_addr: "0x54060000",
+ attr: "reggen_top",
+ intr_to: "smc",
+ },
+ {
+ name: "dma_smc",
+ type: "dma",
+ clock_srcs: {clk_i: "smc"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "smc"},
+ base_addr: "0x54070000",
+ intr_to: "smc",
+ attr: "reggen_top",
+ },
+ { name: "rv_plic_smc",
+ type: "rv_plic_smc",
+ clock_srcs: {clk_i: "smc"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "smc"},
+ base_addr: "0x60000000", //per smc.repl
+ attr: "ipgen",
+ },
+
+ // Second tlul_mailbox module is only for reg, interrupt and tlul interface generation only.
+ // There will be only one tlul_mailbox IP in top level RTL. In the toplevel.sv.tpl, the second
+ // tlul_mailbox IP instantiation will be skipped.
+ { name: "tlul_mailbox_sec",
+ type: "tlul_mailbox",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x40800000",
+ //size: "0x1000",
+ attr: "reggen_top",
+ },
+ { name: "tlul_mailbox_smc",
+ type: "tlul_mailbox",
+ clock_srcs: {clk_i: "main"}, // async fifo at xbar_smc side
+ clock_group: "infra",
+ reset_connections: {rst_ni: "lc"},
+ base_addr: "0x540F1000",
+ //size: "0x1000",
+ intr_to: "smc",
+ attr: "reggen_top",
+ },
+
+ // ML/Vector Core
+ { name: "ml_top",
+ type: "ml_top",
+ clock_srcs: {clk_i: "ml"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "ml"}, // SW controlled reset for whole ml_top.
+ base_addrs: {
+ dmem: "0x5A000000",
+ core: "0x5C000000",
+ },
+ // Memory regions must be associated with a dedicated
+ // TL-UL device interface.
+ memory: {
+ dmem: {
+ label: "ram_ml_dmem",
+ swaccess: "rw",
+ exec: "True",
+ byte_write: "True",
+ size: "0x400000"
+ }
+ }
+ intr_to: "smc",
+ attr: "reggen_top",
+ },
+ { name: "spi_host2",
+ type: "spi_host",
+ clock_srcs: {clk_i: "io"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "spi_host2"},
+ base_addr: "0x54090000",
+ intr_to: "smc",
+ },
+ { name: "rv_timer_smc2",
+ type: "rv_timer",
+ clock_srcs: {clk_i: "io_div4"},
+ clock_group: "timers",
+ reset_connections: {rst_ni: "sys_io_div4"},
+ base_addr: "0x54011000",
+ intr_to: "smc",
+ },
+ { name: "i2s0", // TODO: Waiting on audio clock to be ready. USB clk used temporarily.
+ type: "i2s",
+ clock_srcs: {clk_i: "io_div4", clk_audio_i: "audio"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "sys_io_div4"},
+ base_addr: "0x54100000",
+ intr_to: "smc",
+ attr: "reggen_top",
+ },
+ { name: "rv_core_ibex_smc",
+ type: "rv_core_smc",
+ param_decl: {PMPEnable: "0",
+ PMPGranularity: "0",
+ PMPNumRegions: "16",
+ MHPMCounterNum: "10",
+ MHPMCounterWidth: "32",
+ RV32E: "0",
+ RV32M: "smc_pkg::RV32MSingleCycle",
+ RV32B: "smc_pkg::RV32BNone",
+ RV32A: "1",
+ RegFile: "smc_pkg::RegFileFF",
+ BranchTargetALU: "0",
+ WritebackStage: "0",
+ ICache: "0",
+ ICacheECC: "0",
+ BranchPredictor: "0",
+ DbgTriggerEn: "1",
+ SecureSmc: "0",
+ DmHaltAddr: "tl_main_pkg::ADDR_SPACE_DBG + dm::HaltAddress[31:0]",
+ DmExceptionAddr: "tl_main_pkg::ADDR_SPACE_DBG + dm::ExceptionAddress[31:0]",
+ PipeLine: "0",
+ ITLBEntries: "64",
+ DTLBEntries: "64",
+ ASIDWidth: "9"
+ },
+ clock_srcs: {clk_i: "smc", clk_esc_i: "io_div4"},
+ clock_group: "peri",
+ reset_connections: {rst_ni: "smc", rst_esc_ni: "lc_io_div4"},
+ base_addr: "0x54030000",
+ attr: "reggen_top",
+ },
+
+ ]
+ // Memories (ROM, RAM, eFlash) are defined at the top.
+ // It utilizes the primitive cells but configurable
+ // All memories wrapped up in relevant controllers
+ // ram_smc returned to 4MB
+ memory: [
+ { name: "ram_smc",
+ clock_srcs: {clk_i: "smc"},
+ clock_group: "infra",
+ reset_connections: {
+ rst_ni:
+ {
+ name: "smc"
+ domain: "0"
+ }
+ }
+ type: "ram_1p",
+ base_addr: "0x50000000",
+ size: "0x400000",
+ inter_signal_list: [
+ { struct: "tl"
+ package: "tlul_pkg"
+ type: "req_rsp"
+ act: "rsp"
+ name: "tl"
+ }
+ ]
+ },
+ ],
+
+ // The port data structure is not something that should be used liberally.
+ // It is used specifically to assign special attributes to specific ports.
+ // For example, this allows us to designate a port as part of inter-module
+ // connections.
+ port: [
+ { name: "ast",
+ inter_signal_list: [
+ { struct: "edn",
+ type: "req_rsp",
+ name: "edn",
+ // The activity direction for a port inter-signal is "opposite" of
+ // what the external module actually needs.
+ act: "rsp",
+ package: "edn_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_dft_en",
+ // The activity direction for a port inter-signal is "opposite" of
+ // what the external module actually needs.
+ act: "req",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "ram_1p_cfg",
+ package: "prim_ram_1p_pkg",
+ type: "uni",
+ name: "ram_1p_cfg",
+ // The activity direction for a port inter-signal is "opposite" of
+ // what the external module actually needs.
+ act: "rcv"
+ },
+
+ { struct: "ram_2p_cfg",
+ package: "prim_ram_2p_pkg",
+ type: "uni",
+ name: "ram_2p_cfg",
+ // The activity direction for a port inter-signal is "opposite" of
+ // what the external module actually needs.
+ act: "rcv"
+ },
+
+ { struct: "rom_cfg",
+ package: "prim_rom_pkg",
+ type: "uni",
+ name: "rom_cfg",
+ // The activity direction for a port inter-signal is "opposite" of
+ // what the external module actually needs.
+ act: "rcv"
+ }
+
+ { struct: "ast_obs_ctrl",
+ type: "uni",
+ name: "obs_ctrl",
+ // The activity direction for a port inter-signal is "opposite" of
+ // what the external module actually needs.
+ act: "rcv",
+ package: "ast_pkg",
+ },
+ ]
+ },
+ ]
+
+ // Inter-module Connection.
+ // format:
+ // requester: [ resp1, resp2, ... ],
+ //
+ // the field and value should be module_inst.port_name
+ // e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl]
+ inter_module: {
+ 'connect': {
+ 'ast.obs_ctrl' : ['flash_ctrl.obs_ctrl',
+ 'otp_ctrl.obs_ctrl']
+ 'ast.ram_1p_cfg' : ['otbn.ram_cfg',
+ 'sram_ctrl_main.cfg',
+ 'sram_ctrl_ret_aon.cfg',
+ 'rv_core_ibex_sec.ram_cfg',
+ 'rv_core_ibex_smc.ram_cfg'],
+ 'ast.ram_2p_cfg' : ['spi_device.ram_cfg', 'usbdev.ram_cfg'],
+ 'ast.rom_cfg' : ['rom_ctrl.rom_cfg'],
+ 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'],
+ 'alert_handler.esc_rx' : ['rv_core_ibex_sec.esc_rx',
+ 'lc_ctrl.esc_scrap_state0_rx',
+ 'lc_ctrl.esc_scrap_state1_rx'
+ 'pwrmgr_aon.esc_rst_rx'],
+ 'alert_handler.esc_tx' : ['rv_core_ibex_sec.esc_tx',
+ 'lc_ctrl.esc_scrap_state0_tx',
+ 'lc_ctrl.esc_scrap_state1_tx',
+ 'pwrmgr_aon.esc_rst_tx'],
+ 'aon_timer_aon.nmi_wdog_timer_bark' : ['rv_core_ibex_sec.nmi_wdog']
+ 'csrng.csrng_cmd' : ['edn0.csrng_cmd', 'edn1.csrng_cmd'],
+ 'csrng.entropy_src_hw_if' : ['entropy_src.entropy_src_hw_if'],
+ 'csrng.cs_aes_halt' : ['entropy_src.cs_aes_halt'],
+ 'flash_ctrl.keymgr' : ['keymgr.flash'],
+ 'flash_ctrl.otp' : ['otp_ctrl.flash_otp_key'],
+ 'flash_ctrl.rma_seed' : ['lc_ctrl.lc_flash_rma_seed'],
+ 'otp_ctrl.sram_otp_key' : ['sram_ctrl_main.sram_otp_key',
+ 'sram_ctrl_ret_aon.sram_otp_key',
+ 'rv_core_ibex_sec.icache_otp_key']
+ 'pwrmgr_aon.pwr_flash' : ['flash_ctrl.pwrmgr'],
+ 'pwrmgr_aon.pwr_rst' : ['rstmgr_aon.pwr'],
+ 'pwrmgr_aon.pwr_clk' : ['clkmgr_aon.pwr'],
+ 'pwrmgr_aon.pwr_otp' : ['otp_ctrl.pwr_otp'],
+ 'pwrmgr_aon.pwr_lc' : ['lc_ctrl.pwr_lc'],
+ 'pwrmgr_aon.strap' : ['pinmux_aon.strap_en'],
+ 'pwrmgr_aon.low_power' : ['pinmux_aon.sleep_en',
+ 'aon_timer_aon.sleep_mode'],
+ 'pwrmgr_aon.fetch_en' : ['rv_core_ibex_sec.pwrmgr_cpu_en'],
+ 'rom_ctrl.pwrmgr_data' : ['pwrmgr_aon.rom_ctrl'],
+ 'rom_ctrl.keymgr_data' : ['keymgr.rom_digest'],
+ 'flash_ctrl.keymgr' : ['keymgr.flash'],
+ 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'],
+ 'csrng.entropy_src_hw_if' : ['entropy_src.entropy_src_hw_if'],
+
+ // Daisy chained LC RMA req/ack interface: LC -> Flash -> OTBN -> LC
+ 'lc_ctrl.lc_flash_rma_req' : ['flash_ctrl.rma_req'],
+ 'flash_ctrl.rma_ack' : ['otbn.lc_rma_req'],
+ 'otbn.lc_rma_ack' : ['lc_ctrl.lc_flash_rma_ack'],
+
+ // usbdev connection to pinmux
+ 'usbdev.usb_dp_pullup' : ['pinmux_aon.usbdev_dppullup_en'],
+ 'usbdev.usb_dn_pullup' : ['pinmux_aon.usbdev_dnpullup_en'],
+ 'usbdev.usb_aon_suspend_req': ['pinmux_aon.usbdev_suspend_req'],
+ 'usbdev.usb_aon_wake_ack' : ['pinmux_aon.usbdev_wake_ack'],
+ 'usbdev.usb_aon_bus_reset' : ['pinmux_aon.usbdev_bus_reset'],
+ 'usbdev.usb_aon_sense_lost' : ['pinmux_aon.usbdev_sense_lost'],
+ 'pinmux_aon.usbdev_wake_detect_active' : ['usbdev.usb_aon_wake_detect_active'],
+
+ //isp_wrapper connection to ml_top
+ 'isp_wrapper.isp_cvalid' : ['ml_top.isp_cvalid'],
+ 'isp_wrapper.isp_cready' : ['ml_top.isp_cready'],
+ 'isp_wrapper.isp_cwrite' : ['ml_top.isp_cwrite'],
+ 'isp_wrapper.isp_caddr' : ['ml_top.isp_caddr'],
+ 'isp_wrapper.isp_wdata' : ['ml_top.isp_wdata'],
+ 'isp_wrapper.isp_wmask' : ['ml_top.isp_wmask'],
+
+ 'isp_wrapper.isp_sp_cvalid' : ['ml_top.isp_sp_cvalid'],
+ 'isp_wrapper.isp_sp_cready' : ['ml_top.isp_sp_cready'],
+ 'isp_wrapper.isp_sp_cwrite' : ['ml_top.isp_sp_cwrite'],
+ 'isp_wrapper.isp_sp_caddr' : ['ml_top.isp_sp_caddr'],
+ 'isp_wrapper.isp_sp_wdata' : ['ml_top.isp_sp_wdata'],
+ 'isp_wrapper.isp_sp_wmask' : ['ml_top.isp_sp_wmask'],
+
+ // Edn connections
+ 'edn0.edn' : ['keymgr.edn', 'otp_ctrl.edn', 'ast.edn', 'kmac.entropy',
+ 'alert_handler.edn', 'aes.edn', 'otbn.edn_urnd',
+ 'rv_core_ibex_sec.edn'],
+ 'edn1.edn' : ['otbn.edn_rnd'],
+
+ // OTBN OTP scramble key
+ 'otp_ctrl.otbn_otp_key' : ['otbn.otbn_otp_key'],
+
+ // KeyMgr Sideload & KDF function
+ 'otp_ctrl.otp_keymgr_key' : ['keymgr.otp_key'],
+ 'keymgr.aes_key' : ['aes.keymgr_key'],
+ 'keymgr.kmac_key' : ['kmac.keymgr_key'],
+ 'keymgr.otbn_key' : ['otbn.keymgr_key'],
+
+ // KMAC Application Interface
+ 'kmac.app' : ['keymgr.kmac_data', // Keymgr needs to be at index 0
+ 'lc_ctrl.kmac_data', // LC needs to be at index 1
+ 'rom_ctrl.kmac_data'], // ROM needs to be at index 2
+ 'kmac.en_masking' : ['keymgr.kmac_en_masking']
+
+ // The idle connection is automatically connected through topgen.
+ // The user does not need to explicitly declare anything other than
+ // an empty list.
+ 'clkmgr_aon.idle' : [],
+
+ // Pinmux JTAG signals
+ 'pinmux_aon.lc_jtag' : ['lc_ctrl.jtag'],
+ 'pinmux_aon.rv_jtag' : ['rv_dm.jtag'],
+ // Latched HW debug life cycle signal that is forwarded to RV_DM
+ 'pinmux_aon.pinmux_hw_debug_en' : ['rv_dm.pinmux_hw_debug_en'],
+
+ // OTP LC interface
+ 'otp_ctrl.otp_lc_data' : ['lc_ctrl.otp_lc_data'],
+ 'lc_ctrl.lc_otp_program' : ['otp_ctrl.lc_otp_program'],
+ 'lc_ctrl.lc_otp_vendor_test' : ['otp_ctrl.lc_otp_vendor_test'],
+
+ // Diversification constant coming from life cycle
+ 'lc_ctrl.lc_keymgr_div' : ['keymgr.lc_keymgr_div'],
+
+ // LC function control signal broadcast
+ 'lc_ctrl.lc_dft_en' : ['otp_ctrl.lc_dft_en',
+ 'pinmux_aon.lc_dft_en',
+ 'ast.lc_dft_en',
+ 'pwrmgr_aon.lc_dft_en',
+ ],
+ 'lc_ctrl.lc_nvm_debug_en' : ['flash_ctrl.lc_nvm_debug_en'],
+ 'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en',
+ 'pinmux_aon.lc_hw_debug_en',
+ 'csrng.lc_hw_debug_en',
+ 'rv_dm.lc_hw_debug_en',
+ 'clkmgr_aon.lc_hw_debug_en',
+ 'pwrmgr_aon.lc_hw_debug_en',],
+ 'lc_ctrl.lc_cpu_en' : ['rv_core_ibex_sec.lc_cpu_en',
+ 'rv_core_ibex_smc.lc_cpu_en'],
+ 'lc_ctrl.lc_keymgr_en' : ['keymgr.lc_keymgr_en'],
+ 'lc_ctrl.lc_escalate_en' : ['aes.lc_escalate_en',
+ 'kmac.lc_escalate_en',
+ 'otbn.lc_escalate_en',
+ 'otp_ctrl.lc_escalate_en',
+ 'sram_ctrl_main.lc_escalate_en',
+ 'sram_ctrl_ret_aon.lc_escalate_en',
+ 'aon_timer_aon.lc_escalate_en',
+ 'flash_ctrl.lc_escalate_en',
+ 'pinmux_aon.lc_escalate_en'],
+
+ 'lc_ctrl.lc_check_byp_en' : ['otp_ctrl.lc_check_byp_en',
+ 'pinmux_aon.lc_check_byp_en'],
+ 'lc_ctrl.lc_clk_byp_req' : ['clkmgr_aon.lc_clk_byp_req'],
+ 'lc_ctrl.lc_clk_byp_ack' : ['clkmgr_aon.lc_clk_byp_ack'],
+
+ // LC access control signal broadcast
+ 'lc_ctrl.lc_creator_seed_sw_rw_en' : ['otp_ctrl.lc_creator_seed_sw_rw_en',
+ 'flash_ctrl.lc_creator_seed_sw_rw_en'],
+ 'lc_ctrl.lc_owner_seed_sw_rw_en' : ['flash_ctrl.lc_owner_seed_sw_rw_en'],
+ 'lc_ctrl.lc_iso_part_sw_rd_en' : ['flash_ctrl.lc_iso_part_sw_rd_en'],
+ 'lc_ctrl.lc_iso_part_sw_wr_en' : ['flash_ctrl.lc_iso_part_sw_wr_en'],
+ 'lc_ctrl.lc_seed_hw_rd_en' : ['otp_ctrl.lc_seed_hw_rd_en',
+ 'flash_ctrl.lc_seed_hw_rd_en'],
+
+ // rv_plic connections
+ 'rv_plic.msip' : ['rv_core_ibex_sec.irq_software'],
+ 'rv_plic.irq' : ['rv_core_ibex_sec.irq_external'],
+
+ 'rv_plic_smc.msip' : ['rv_core_ibex_smc.irq_software'],
+ 'rv_plic_smc.irq' : ['rv_core_ibex_smc.irq_external'],
+
+ 'rv_dm.debug_req': ['rv_core_ibex_sec.debug_req', 'rv_core_ibex_smc.debug_req',
+ 'ml_top.debug_req'],
+
+ // rv_timer connections
+
+
+ // rv core ibex connections
+ 'rv_core_ibex_sec.crash_dump' : ['rstmgr_aon.cpu_dump'],
+ 'rv_core_ibex_sec.pwrmgr' : ['pwrmgr_aon.pwr_cpu'],
+
+ // smc core connections
+ 'rv_core_ibex_smc.pwrmgr_cpu_en' : ['smc_ctrl.smc_boot_en'],
+
+ // spi passthrough connection
+ 'spi_device.passthrough' : ['spi_host0.passthrough']
+
+ // Debug module reset request to power manager
+ 'rv_dm.ndmreset_req' : ['pwrmgr_aon.ndmreset_req'],
+
+ // Reset manager software reset request to pwrmgr
+ 'rstmgr_aon.sw_rst_req' : ['pwrmgr_aon.sw_rst_req'],
+ }
+
+ // top is to connect to top net/struct.
+ // It defines the signal in the top and connect from the module,
+ // use of the signal is up to top template
+ 'top': [
+ // top level net for clocks
+ 'clkmgr_aon.clocks',
+
+ // top level clock gating indications for alert subsystem
+ 'clkmgr_aon.cg_en',
+
+ // top level net for reset
+ 'rstmgr_aon.resets',
+
+ // top level reset asserted indications for alert subsystem
+ 'rstmgr_aon.rst_en',
+
+ // dedicated timer interrupt
+ 'rv_core_ibex_sec.irq_timer',
+ 'rv_core_ibex_smc.irq_timer',
+
+ // hardwired connections
+ 'rv_core_ibex_sec.hart_id', 'rv_core_ibex_sec.boot_addr',
+ 'rv_core_ibex_smc.hart_id', 'rv_core_ibex_smc.boot_addr',
+
+ // Xbars
+
+ // Pinmux JTAG signals for the tool-inserted DFT TAP
+ 'pinmux_aon.dft_jtag',
+
+ // OTP HW_CFG Broadcast signals.
+ // TODO(#6713): The actual struct breakout and mapping currently needs to
+ // be performed by hand in the toplevel template.
+ 'otp_ctrl.otp_hw_cfg',
+ 'csrng.otp_en_csrng_sw_app_read',
+ 'entropy_src.otp_en_entropy_src_fw_read',
+ 'entropy_src.otp_en_entropy_src_fw_over',
+ 'lc_ctrl.otp_device_id',
+ 'lc_ctrl.otp_manuf_state',
+ 'keymgr.otp_device_id',
+ 'sram_ctrl_main.otp_en_sram_ifetch',
+ ],
+
+ // ext is to create port in the top.
+ 'external': {
+ 'adc_ctrl_aon.adc' : 'adc'
+ 'ast.edn' : '',
+ 'ast.lc_dft_en' : '',
+ 'ast.obs_ctrl' : 'obs_ctrl',
+ 'ast.ram_1p_cfg' : 'ram_1p_cfg',
+ 'ast.ram_2p_cfg' : 'ram_2p_cfg',
+ 'ast.rom_cfg' : 'rom_cfg',
+ 'clkmgr_aon.jitter_en' : 'clk_main_jitter_en',
+ 'clkmgr_aon.io_clk_byp_req' : 'io_clk_byp_req',
+ 'clkmgr_aon.io_clk_byp_ack' : 'io_clk_byp_ack',
+ 'clkmgr_aon.all_clk_byp_req' : 'all_clk_byp_req',
+ 'clkmgr_aon.all_clk_byp_ack' : 'all_clk_byp_ack',
+ 'clkmgr_aon.hi_speed_sel' : 'hi_speed_sel',
+ 'clkmgr_aon.div_step_down_req' : 'div_step_down_req',
+ 'clkmgr_aon.calib_rdy' : 'calib_rdy',
+ 'flash_ctrl.flash_bist_enable' : 'flash_bist_enable',
+ 'flash_ctrl.flash_power_down_h' : 'flash_power_down_h',
+ 'flash_ctrl.flash_power_ready_h' : 'flash_power_ready_h',
+ 'flash_ctrl.flash_test_mode_a' : 'flash_test_mode_a',
+ 'flash_ctrl.flash_test_voltage_h' : 'flash_test_voltage_h',
+ 'flash_ctrl.fla_obs' : 'flash_obs',
+ 'entropy_src.entropy_src_rng' : 'es_rng',
+ 'entropy_src.rng_fips' : 'es_rng_fips',
+ 'peri.tl_ast' : 'ast_tl',
+ 'pinmux_aon.dft_strap_test' : 'dft_strap_test'
+ 'pinmux_aon.dft_hold_tap_sel' : 'dft_hold_tap_sel',
+ 'pinmux_aon.usb_dppullup_en' : 'usb_dp_pullup_en',
+ 'pinmux_aon.usb_dnpullup_en' : 'usb_dn_pullup_en',
+ 'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast',
+ 'otp_ctrl.otp_ast_pwr_seq' : '',
+ 'otp_ctrl.otp_ast_pwr_seq_h' : '',
+ 'otp_ctrl.otp_ext_voltage_h' : 'otp_ext_voltage_h',
+ 'otp_ctrl.otp_obs' : 'otp_obs',
+ 'rstmgr_aon.por_n' : 'por_n',
+ 'rv_core_ibex_sec.fpga_info' : 'fpga_info',
+ 'sensor_ctrl.ast_alert' : 'sensor_ctrl_ast_alert',
+ 'sensor_ctrl.ast_status' : 'sensor_ctrl_ast_status',
+ 'sensor_ctrl.ast2pinmux' : 'ast2pinmux',
+ 'sensor_ctrl.ast_init_done' : 'ast_init_done',
+ 'spi_device.sck_monitor' : 'sck_monitor',
+ 'usbdev.usb_rx_d' : '',
+ 'usbdev.usb_tx_d' : '',
+ 'usbdev.usb_tx_se0' : '',
+ 'usbdev.usb_tx_use_d_se0' : '',
+ 'usbdev.usb_rx_enable' : '',
+ 'usbdev.usb_ref_val' : '',
+ 'usbdev.usb_ref_pulse' : '',
+ },
+ },
+
+ // Crossbars: having a top level crossbar
+ // This version assumes all crossbars are instantiated at the top.
+ // Assume xbar.hjson is located in the same directory of top.hjson
+ xbar: [
+ { name: "main",
+ clock_srcs: {clk_main_i: "main",
+ clk_fixed_i: "io_div4",
+ clk_usb_i: "usb",
+ clk_spi_host0_i: "io",
+ clk_spi_host1_i: "io",
+ clk_smc_i:"smc"},
+ clock_group: "infra",
+ reset: "lc",
+ reset_connections: {rst_main_ni: "lc",
+ rst_fixed_ni: "lc_io_div4",
+ rst_usb_ni: "lc_usb",
+ rst_spi_host0_ni: "lc_io",
+ rst_spi_host1_ni: "lc_io",
+ rst_smc_ni: "smc"}
+ },
+ { name: "peri",
+ clock_srcs: {clk_peri_i: "io_div4", },
+ clock_group: "infra",
+ reset: "lc_io_div4",
+ reset_connections: {rst_peri_ni: "lc_io_div4"},
+ },
+ { name: "smc",
+ clock_srcs: {clk_smc_i: "smc",
+ clk_peri_i: "io_div4",
+ clk_spi_host2_i: "io",
+ clk_ml_i: "ml",
+ clk_video_i: "video",
+ clk_audio_i: "audio",
+ clk_main_i: "main",
+ },
+ clock_group: "infra",
+ reset: "lc",
+ reset_connections: {rst_smc_ni: "smc",
+ rst_peri_ni: "lc_io_div4",
+ rst_spi_host2_ni: "lc_io",
+ rst_ml_ni: "ml",
+ rst_video_ni: "video",
+ rst_audio_ni: "audio",
+ rst_main_ni: "lc"
+ },
+ },
+ { name: "dbg",
+ clock_srcs: {clk_main_i: "main", },
+ clock_group: "infra",
+ reset: "lc",
+ reset_connections: {rst_main_ni: "lc"},
+ },
+ ],
+
+ // ===== PINMUX & PINOUT ======================================================
+
+ pinout: {
+ // IO power bank declaration.
+ // This list defines the IO bank power domains on the ASIC.
+ // Each individual pad must be in one of the declared power domains.
+ banks: ['VCC', 'AVCC', 'VIOA', 'VIOB'],
+ // Pad declaration.
+ // Each entry must have the following four keys:
+ //
+ // - name: Name of the pad (this will be exposed at the chiplevel).
+ //
+ // - type: Pad type (this maps to the pad types defined in prim_pad_wrapper_pkg.sv)
+ //
+ // - bank: Specifies in which of the IO power banks this pad lives.
+ //
+ // - connection: Can have either of the following values:
+ //
+ // 1) 'direct': This is a dedicated IO Pad that is directly connected to a peripheral.
+ //
+ // 2) 'manual': This is a dedicated IO signal that is not directly connected to a
+ // peripheral. It needs to be manually wired up in the template.
+ //
+ // 3) 'muxed': This is a muxed IO pad that will be connected to the pinmux.
+ //
+ // Optionally, each pad can also have a 'desc' field for further description, and a 'port_type' field
+ // to override the default 'inout wire' type (this is currently only used for simulating ADC connections
+ // where the ports have to be switched to a real type when the ANALOGSIM macro is defined).
+ pads: [
+ // Special manually connected pads
+ { name: 'POR_N' , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'System reset'},
+ { name: 'USB_P' , type: 'DualBidirTol', bank: 'VCC' , connection: 'manual', desc: 'USB P signal'},
+ { name: 'USB_N' , type: 'DualBidirTol', bank: 'VCC' , connection: 'manual', desc: 'USB N signal'},
+ { name: 'CC1' , type: 'InputStd', bank: 'AVCC', connection: 'manual', desc: 'ADC input 1', port_type: '`INOUT_AI'},
+ { name: 'CC2' , type: 'InputStd', bank: 'AVCC', connection: 'manual', desc: 'ADC input 2', port_type: '`INOUT_AI'},
+ { name: 'FLASH_TEST_VOLT' , type: 'AnalogIn0', bank: 'VCC' , connection: 'manual', desc: 'Flash test voltage input'},
+ { name: 'FLASH_TEST_MODE0', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'FLASH_TEST_MODE1', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'OTP_EXT_VOLT' , type: 'AnalogIn1', bank: 'VCC' , connection: 'manual', desc: 'OTP external voltage input'},
+ //{ name: 'CAM_SCL' , type: 'BidirOd', bank: 'VCC' , connection: 'manual', desc: 'CAM I2C Clock'},
+ //{ name: 'CAM_SDA' , type: 'BidirOd', bank: 'VCC' , connection: 'manual', desc: 'CAM I2C Data'},
+ // Dedicated IOs
+ { name: 'SPI_HOST_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_D2' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_D3' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_CLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host clock'},
+ { name: 'SPI_HOST_CS_L' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host chip select'},
+ //{ name: 'SPI_HOST2_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ //{ name: 'SPI_HOST2_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ //{ name: 'SPI_HOST2_D2' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ //{ name: 'SPI_HOST2_D3' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ //{ name: 'SPI_HOST2_CLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host clock'},
+ //{ name: 'SPI_HOST2_CS_L' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host chip select'},
+ { name: 'SPI_DEV_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_D2' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_D3' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_CLK' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device clock'},
+ { name: 'SPI_DEV_CS_L' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device chip select'},
+ //{ name: 'ISP_DVP_PCLK' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR CLK'},
+ //{ name: 'ISP_DVP_D0' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR DATA'},
+ //{ name: 'ISP_DVP_D1' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR DATA'},
+ //{ name: 'ISP_DVP_D2' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR DATA'},
+ //{ name: 'ISP_DVP_D3' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR DATA'},
+ //{ name: 'ISP_DVP_D4' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR DATA'},
+ //{ name: 'ISP_DVP_D5' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR DATA'},
+ //{ name: 'ISP_DVP_D6' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR DATA'},
+ //{ name: 'ISP_DVP_D7' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR DATA'},
+ //{ name: 'ISP_DVP_HSYNC' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR HSYNC'},
+ //{ name: 'ISP_DVP_VSYNC' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SENSOR VSYNC'},
+ //{ name: 'CAM_TRIG' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'CAM trigger'},
+ //{ name: 'CAM_INT' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'CAM Interrupt'},
+ //{ name: 'I2S0_RX_SCLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S rx host clock'},
+ //{ name: 'I2S0_RX_WS' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S rx host word select'},
+ //{ name: 'I2S0_RX_SD' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S rx serial data'},
+ //{ name: 'I2S0_TX_SCLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S tx host clock'},
+ //{ name: 'I2S0_TX_WS' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S tx host word select'},
+ //{ name: 'I2S0_TX_SD' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'I2S tx serial data'},
+
+ // IOA
+ { name: 'IOA0' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA1' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA2' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad', port_type: '`INOUT_AO'},
+ { name: 'IOA3' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad', port_type: '`INOUT_AO'},
+ { name: 'IOA4' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA5' , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA6' , type: 'BidirOd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA7' , type: 'BidirOd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA8' , type: 'BidirOd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOB
+ { name: 'IOB0' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB1' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB2' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB3' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB4' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB5' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB6' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB7' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB8' , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB9' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB10' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB11' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB12' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOC
+ { name: 'IOC0' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC1' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC2' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC3' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC4' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC5' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC6' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC7' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC8' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC9' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC10' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC11' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC12' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOR
+ { name: 'IOR0' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR1' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR2' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR3' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR4' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR5' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR6' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR7' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR8' , type: 'BidirOd' , bank: 'VCC' , connection: 'direct', desc: 'Dedicated sysrst_ctrl output (ec_rst_l)'},
+ { name: 'IOR9' , type: 'BidirOd' , bank: 'VCC' , connection: 'direct', desc: 'Dedicated sysrst_ctrl output (flash_wp_l)'},
+ { name: 'IOR10' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR11' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR12' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR13' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOD
+ { name: 'IOD0' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOD1' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOD2' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOD3' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOD4' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOD5' , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ ]
+ }
+
+ pinmux: {
+ // Signal to pinmux/pad mapping.
+ // Each entry in the list below must have the following two mandatory keys:
+ //
+ // - instance: This is the comportable IO instance name where the IO signal comes from.
+ //
+ // - connection: This key is similar to the connection key in the pinout/pad configuration and
+ // can have either of the following values:
+ //
+ // 1) 'direct': This is a dedicated IO signal that is directly connected to a pad.
+ // Such an IO signal must also specify the 'port' and 'pad' keys
+ // (see further below).
+ //
+ // 2) 'manual': This is a dedicated IO signal that is not directly connected to a pad.
+ // It needs to be manually wired up in the template.
+ // Such an IO signal may have a 'port' key, but no 'pad' key.
+ //
+ // 3) 'muxed': This is a muxed IO signal that will be connected to the pinmux.
+ // Such an IO signal may have a 'port' key, but no 'pad' key.
+ //
+ // Depending on the connection type specified, each entry may have the following optional keys:
+ //
+ // - port: Name of the available IO signal of the instance.
+ // This is required for 'direct' connections, but optional for the others.
+ // Individual signals of a bus IO signal must be indexed with square brackets, e.g. mybus[1].
+ // Not specifying this key or setting it to an empty string acts as a wild card
+ // and includes all available IOs of this instance.
+ //
+ // - pad: Name of the pad the 'direct' connection should connect to.
+ // This is not required for 'muxed' and 'manual' connections.
+ //
+ // - desc: Optional description field.
+ //
+ // - attr: Manual direct IOs may specify an additional pad attr field.
+ // This is used to create the correct pad attribute CSR for that DIO channel (since the
+ // DIO is manual, there is no way to automatically infer the corresponding pad type).
+ //
+ signals: [
+ // USB
+ { instance: 'usbdev', port: 'usb_dp', connection: 'manual', pad: '' , desc: ''},
+ { instance: 'usbdev', port: 'usb_dn', connection: 'manual', pad: '' , desc: ''},
+ // SPI Host0
+ { instance: 'spi_host0', port: 'sck', connection: 'direct', pad: 'SPI_HOST_CLK' , desc: ''},
+ { instance: 'spi_host0', port: 'csb', connection: 'direct', pad: 'SPI_HOST_CS_L', desc: ''},
+ { instance: 'spi_host0', port: 'sd[0]', connection: 'direct', pad: 'SPI_HOST_D0' , desc: ''},
+ { instance: 'spi_host0', port: 'sd[1]', connection: 'direct', pad: 'SPI_HOST_D1' , desc: ''},
+ { instance: 'spi_host0', port: 'sd[2]', connection: 'direct', pad: 'SPI_HOST_D2' , desc: ''},
+ { instance: 'spi_host0', port: 'sd[3]', connection: 'direct', pad: 'SPI_HOST_D3' , desc: ''},
+ // SPI Device
+ { instance: 'spi_device', port: 'sck', connection: 'direct', pad: 'SPI_DEV_CLK' , desc: ''},
+ { instance: 'spi_device', port: 'csb', connection: 'direct', pad: 'SPI_DEV_CS_L' , desc: ''},
+ { instance: 'spi_device', port: 'sd[0]', connection: 'direct', pad: 'SPI_DEV_D0' , desc: ''},
+ { instance: 'spi_device', port: 'sd[1]', connection: 'direct', pad: 'SPI_DEV_D1' , desc: ''},
+ { instance: 'spi_device', port: 'sd[2]', connection: 'direct', pad: 'SPI_DEV_D2' , desc: ''},
+ { instance: 'spi_device', port: 'sd[3]', connection: 'direct', pad: 'SPI_DEV_D3' , desc: ''},
+
+ // MIOs
+ { instance: "gpio", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "uart0", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "uart1", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "uart2", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "smc_uart", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "i2c0", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "i2c1", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "i2c2", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "cam_i2c", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "cam_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "isp_wrapper", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "i2s0", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "pattgen", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "spi_device", port: 'tpm_csb', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "spi_host1", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "spi_host2", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sensor_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "pwm_aon", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "otp_ctrl", port: 'test[0]', connection: 'muxed' , pad: '' , desc: ''},
+ // Sysrst ctrl has both muxed and dedicated IOs
+ { instance: "sysrst_ctrl_aon", port: 'ac_present', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'key0_in', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'key1_in', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'key2_in', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'pwrb_in', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'bat_disable', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'ec_rst_l', connection: 'direct', pad: 'IOR8' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'flash_wp_l', connection: 'direct', pad: 'IOR9' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'key0_out', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'key1_out', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'key2_out', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'pwrb_out', connection: 'muxed', pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'lid_open', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sysrst_ctrl_aon", port: 'z3_wakeup', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: 'usbdev', port: 'sense', connection: 'muxed' , pad: '' , desc: ''},
+ ],
+
+ num_wkup_detect: 8
+ wkup_cnt_width: 8
+ }
+
+ // Implementation targets.
+ // This defines the configuration of the target-specific chip-levels to
+ // generate from the shared template. Each target uses the same base
+ // configuration for the pinmux and pinout as defined above, and the
+ // generated software constants for the pinmux DIF do not change among the
+ // implementation targets. However, in order to accommodate slight
+ // differences among the ASIC, FPGA emulation and simulation environments,
+ // it is possible to make very limited pinout changes below. In particular,
+ // it is possible to remove and tie-off specific pads, or add more 'manual'
+ // pads that need to be manually connected in the template. It is also possible
+ // to override the JTAG and strap locations indices, since the testing and DFT
+ // setups may differ among the targets.
+ targets: [
+ { name: 'asic',
+
+ // Pinout Changes.
+ pinout: {
+ // This is a list of port names to remove from the chip port list.
+ // The corresponding pad of a removed port will remain instantiated,
+ // and a wire net will be declared inside the chip-level hierarchy so
+ // that it can be manually connected as needed.
+ remove_ports: [],
+
+ // This is a list of pad names to remove from the base pinout defined
+ // above. Removed pads will be stubbed off such that their inputs
+ // signals are driven with zero. Output signals and output enables
+ // will be left unconnected. If no changes are needed, this list can
+ // be left empty.
+ remove_pads: [],
+
+ // This is a list of additional "manual" pads to add to the pinout.
+ // The pad entries have the same format as the pad entries in the pinout
+ // configuration above. However, the 'connection' key must always be set
+ // to 'manual' as it is not possible to connect these additional pads
+ // to the pinmux or peripherals.
+ add_pads: [
+ { name: 'AST_MISC', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Extra infrastructure pad for AST'}
+ { name: 'CLK_EXT', type: 'AnalogIn0', bank: 'VCC', connection: 'manual', desc: 'Ext clock input'}
+ { name: 'CLK_BYP', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Bypass internal clk from PLL, and use CLK_EXT for debug'}
+ { name: 'CLK_200K', type: 'AnalogIn0', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'}
+ { name: 'XTAL_IN', type: 'AnalogIn0', bank: 'VCC', connection: 'manual', desc: 'XTAL input'}
+ { name: 'XTAL_OUT', type: 'AnalogIn0', bank: 'VCC', connection: 'manual', desc: 'XTAL output'}
+ ],
+ },
+
+ pinmux: {
+ // Special signal positions. Each entry in the list below creates a
+ // target-specific pad position parameter in the chiplevel hierarchy
+ // that can be used to parameterize certain IPs like the pinmux or
+ // padring. This is mainly used to define the pad positions of special
+ // test and DFT signals such as the JTAG signals and the TAP and DFT
+ // straps. Straps in this context are special pads that get sampled at
+ // boot time during certain life cycle states in order to determine
+ // DFT modes and the TAP mux selection index (the JTAG signals can be
+ // muxed to either the lifecycle TAP, DFT TAP or RISC-V processor
+ // TAP). TODO: add more documentation to https://docs.opentitan.org/hw/ip/pinmux/doc/index.html
+ // Each entry must have the following two keys:
+ //
+ // - name: Basename for the SV parameter.
+ //
+ // - pad: The pad name that this special signal maps to. The generated
+ // parameter will be assigned the corresponding pad index.
+ //
+ // Each entry may have an optional 'desc' key for further description.
+ special_signals: [
+ // Straps
+ { name: 'tap0', pad: 'IOC8', desc: 'TAP strap signal.' },
+ { name: 'tap1', pad: 'IOC5', desc: 'TAP strap signal.' },
+ { name: 'dft0', pad: 'IOC3', desc: 'DFT strap signal.' },
+ { name: 'dft1', pad: 'IOC4', desc: 'DFT strap signal.' },
+ // JTAG
+ { name: 'tck', pad: 'IOR3', desc: 'JTAG tck signal.' },
+ { name: 'tms', pad: 'IOR0', desc: 'JTAG tms signal.' },
+ { name: 'trst_n', pad: 'IOR4', desc: 'JTAG trst_n signal.' },
+ { name: 'tdi', pad: 'IOR2', desc: 'JTAG tdi signal.' },
+ { name: 'tdo', pad: 'IOR1', desc: 'JTAG tdo signal.' },
+ ],
+ }
+ },
+ { name: 'nexus',
+
+ pinout: {
+ remove_ports: [],
+ remove_pads: [
+ 'CC1', 'CC2',
+ //'SPI_DEV_D2', 'SPI_DEV_D3'
+ 'FLASH_TEST_VOLT', 'OTP_EXT_VOLT'
+ 'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1',
+ //'IOB10', 'IOB11', 'IOB12',
+ //'IOR5', 'IOR6', 'IOR7', 'IOR8', 'IOR9', 'IOR10', 'IOR11', 'IOR12', 'IOR13'
+ ],
+
+ add_pads: [
+ // Additional infrastructure pads
+ // IO_CLK and IO_CLK_N are using AnalogIO0 now to bypass the IBUF in he prim_xilinx_pad_wrapper.sv. It use the IBUFDS in
+ // the clkgen_xilultrascaleplus.sv instead.
+ { name: 'IO_CLK', type: 'AnalogIn0', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'}
+ { name: 'IO_CLK_N', type: 'AnalogIn0', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'}
+ { name: 'POR_BUTTON_N', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Power-on reset button input'}
+ { name: 'JTAG_SRST_N', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'JTAG header SRST, triggers POR'}
+ // ChipWhisperer IO
+ { name: 'IO_CLKOUT', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual clock output for SCA setup'}
+ { name: 'IO_TRIGGER', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual trigger output for SCA setup'}
+ ],
+ },
+
+ pinmux: {
+ special_signals: [
+ // Straps
+ { name: 'tap0', pad: 'IOC8', desc: 'TAP strap signal.' },
+ { name: 'tap1', pad: 'IOC5', desc: 'TAP strap signal.' },
+ { name: 'dft0', pad: 'IOC3', desc: 'DFT strap signal.' },
+ { name: 'dft1', pad: 'IOC4', desc: 'DFT strap signal.' },
+ // JTAG
+ { name: 'tck', pad: 'IOR3', desc: 'JTAG tck signal.' },
+ { name: 'tms', pad: 'IOR0', desc: 'JTAG tms signal.' },
+ { name: 'trst_n', pad: 'IOR4', desc: 'JTAG trst_n signal.' },
+ { name: 'tdi', pad: 'IOR2', desc: 'JTAG tdi signal.' },
+ { name: 'tdo', pad: 'IOR1', desc: 'JTAG tdo signal.' },
+ ],
+ }
+ }
+ ]
+}
diff --git a/hw/top_sencha/data/xbar_dbg.hjson b/hw/top_sencha/data/xbar_dbg.hjson
new file mode 100644
index 0000000..a53131b
--- /dev/null
+++ b/hw/top_sencha/data/xbar_dbg.hjson
@@ -0,0 +1,67 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+{ name: "dbg",
+ type: "xbar",
+ clock_primary: "clk_main_i", // Main clock, used in sockets
+ reset_primary: "rst_main_ni", // Main reset, used in sockets
+ nodes: [
+ { name: "main",
+ type: "host",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ xbar: "true",
+ pipeline: true
+
+ },
+ { name: "smc",
+ type: "host",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ xbar: "true",
+ pipeline: true
+
+ },
+ { name: "rv_dm.regs",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ addr_range: [{
+ base_addr: "0x6000",
+ size_bytes: "0x1000",
+ }]
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "rv_dm.mem",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ addr_range: [{
+ base_addr: "0x4000",
+ size_bytes: "0x1000",
+ }]
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ ],
+ connections: {
+ main: [
+ "rv_dm.regs", "rv_dm.mem"
+ ],
+ smc: [
+ "rv_dm.regs", "rv_dm.mem"
+ ],
+ },
+}
diff --git a/hw/top_sencha/data/xbar_main.hjson b/hw/top_sencha/data/xbar_main.hjson
new file mode 100644
index 0000000..6886fab
--- /dev/null
+++ b/hw/top_sencha/data/xbar_main.hjson
@@ -0,0 +1,273 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+{ name: "main",
+ type: "xbar",
+ clock_primary: "clk_main_i", // Main clock, used in sockets
+ other_clock_list: [ "clk_fixed_i", "clk_spi_host0_i", "clk_spi_host1_i", "clk_usb_i", "clk_smc_i"]
+ reset_primary: "rst_main_ni", // Main reset, used in sockets
+ other_reset_list: [ "rst_fixed_ni", "rst_spi_host0_ni", "rst_spi_host1_ni", "rst_usb_ni", "rst_smc_ni"]
+
+ // Rationale for pipeline and req/rsp_fifo_pass:
+ // For host interfaces that are used during production state (corei/cored),
+ // minimize the amount of host introduced latency. This is accomplished
+ // by setting pipeline to false.
+ // For host interfaces that are only used for debug, relax the timing by
+ // inserting a register slice and not allowing passthrough (more access
+ // latency. This is accomplished by setting `req/rsp_fifo_pass` to false,
+ // and implicitly using the default of pipeline true.
+ //
+ // For device interfaces, especially configuration registers, latency is
+ // not generally a concern, thus use `req/rsp_fifo_pass` false and pipeline
+ // true.
+ // For device accesses to memories (ram / rom / flash), performance is a concern,
+ // so use pipeline false where permissible by timing. If not, find a combination
+ // that works.
+
+ nodes: [
+ { name: "rv_core_ibex_sec.corei",
+ type: "host",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ pipeline: false
+
+ },
+ { name: "rv_core_ibex_sec.cored",
+ type: "host",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ pipeline: false
+ },
+ { name: "rv_dm.sba",
+ type: "host",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "dma0.reader",
+ type: "host",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ pipeline: false
+ },
+ { name: "dma0.writer",
+ type: "host",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ pipeline: false
+ },
+ { name: "dma0",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "rom_ctrl.rom",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
+ },
+ { name: "rom_ctrl.regs",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "peri",
+ type: "device",
+ clock: "clk_fixed_i",
+ reset: "rst_fixed_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "spi_host0",
+ type: "device",
+ clock: "clk_spi_host0_i",
+ reset: "rst_spi_host0_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "spi_host1",
+ type: "device",
+ clock: "clk_spi_host1_i",
+ reset: "rst_spi_host1_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "usbdev",
+ type: "device",
+ clock: "clk_usb_i",
+ reset: "rst_usb_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "flash_ctrl.core",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "flash_ctrl.prim",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "flash_ctrl.mem",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "hmac",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "kmac"
+ type: "device"
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ }
+ { name: "aes",
+ type: "device",
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "entropy_src",
+ type: "device",
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "csrng",
+ type: "device",
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "edn0",
+ type: "device",
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "edn1",
+ type: "device",
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "rv_plic",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ inst_type: "rv_plic",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "otbn",
+ type: "device",
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "keymgr",
+ type: "device",
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "rv_core_ibex_sec.cfg",
+ type: "device",
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "sram_ctrl_main.regs",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "sram_ctrl_main.ram",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ pipeline: false
+ },
+ { name: "tlul_mailbox_sec",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ pipeline_byp: false,
+ },
+ { name: "smc",
+ type: "device",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ pipeline_byp: false,
+ xbar: "true"
+ },
+ { name: "dbg",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ pipeline_byp: false,
+ xbar: "true"
+ },
+ ],
+ connections: {
+ rv_core_ibex_sec.corei: ["rom_ctrl.rom", "dbg", "sram_ctrl_main.ram", "flash_ctrl.mem"],
+ rv_core_ibex_sec.cored: [
+ "rom_ctrl.rom", "rom_ctrl.regs", "dbg",
+ "sram_ctrl_main.ram", "peri", "spi_host0", "spi_host1", "usbdev",
+ "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem",
+ "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac",
+ "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs",
+ "rv_core_ibex_sec.cfg", "smc", "tlul_mailbox_sec", dma0
+ ],
+ rv_dm.sba: [
+ "dbg", "rom_ctrl.rom", "rom_ctrl.regs", "peri", "spi_host0", "spi_host1", "usbdev",
+ "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", "hmac", "kmac",
+ "aes", "entropy_src", "csrng", "edn0", "edn1", "rv_plic", "otbn",
+ "keymgr", "rv_core_ibex_sec.cfg", "sram_ctrl_main.regs", "sram_ctrl_main.ram", "smc", "tlul_mailbox_sec"
+ ],
+ dma0.reader: ["rom_ctrl.rom", "sram_ctrl_main.ram", "flash_ctrl.mem", "smc"],
+ dma0.writer: ["rom_ctrl.rom", "sram_ctrl_main.ram", "flash_ctrl.mem", "smc"],
+ },
+}
diff --git a/hw/top_sencha/data/xbar_peri.hjson b/hw/top_sencha/data/xbar_peri.hjson
new file mode 100644
index 0000000..e12acfb
--- /dev/null
+++ b/hw/top_sencha/data/xbar_peri.hjson
@@ -0,0 +1,205 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+{ name: "peri",
+ type: "xbar",
+ clock_primary: "clk_peri_i", // Main clock, used in sockets
+ other_clock_list: [] // Secondary clocks used by specific nodes
+ reset_primary: "rst_peri_ni", // Main reset, used in sockets
+ other_reset_list: [] // Secondary resets used by specific nodes
+
+ nodes: [
+ { name: "main",
+ type: "host",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ xbar: "true",
+ pipeline: false
+
+ },
+ { name: "uart0",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "uart1",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "uart2",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "uart3",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "i2c0",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "i2c1",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "i2c2",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "pattgen",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "pwm_aon",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "gpio",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "spi_device",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "rv_timer",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "pwrmgr_aon",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "rstmgr_aon",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "clkmgr_aon",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "pinmux_aon",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "otp_ctrl.core",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "otp_ctrl.prim",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "lc_ctrl",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "sensor_ctrl",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false,
+ },
+ { name: "alert_handler",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false,
+ },
+ { name: "sram_ctrl_ret_aon.regs",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "sram_ctrl_ret_aon.ram",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false
+ },
+ { name: "aon_timer_aon",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false,
+ },
+ { name: "sysrst_ctrl_aon",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false,
+ }
+ { name: "adc_ctrl_aon",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false,
+ }
+ { name: "ast",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: false,
+ },
+ ],
+ connections: {
+ main: [
+ "uart0", "uart1", "uart2", "uart3", "i2c0", "i2c1", "i2c2", "pattgen",
+ "gpio", "spi_device", "rv_timer",
+ "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon",
+ "otp_ctrl.core", "otp_ctrl.prim", "lc_ctrl", "sensor_ctrl",
+ "alert_handler", "ast", "sram_ctrl_ret_aon.ram", "sram_ctrl_ret_aon.regs",
+ "aon_timer_aon", "adc_ctrl_aon", "sysrst_ctrl_aon", "pwm_aon"
+ ],
+ },
+}
diff --git a/hw/top_sencha/data/xbar_smc.hjson b/hw/top_sencha/data/xbar_smc.hjson
new file mode 100644
index 0000000..b648097
--- /dev/null
+++ b/hw/top_sencha/data/xbar_smc.hjson
@@ -0,0 +1,183 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+{ name: "smc",
+ type: "xbar",
+ clock_primary: "clk_smc_i", // Main clock, used in sockets
+ other_clock_list: [ "clk_peri_i", "clk_spi_host2_i" , "clk_ml_i", "clk_video_i", "clk_audio_i", "clk_main_i"],
+ reset_primary: "rst_smc_ni", // Main reset, used in sockets
+ other_reset_list: [ "rst_peri_ni", "rst_spi_host2_ni" , "rst_ml_ni" , "rst_video_ni", "rst_audio_ni", "rst_main_ni"],
+
+ nodes: [
+ { name: "main",
+ type: "host",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ xbar: "true",
+ pipeline: "false"
+ },
+ { name: "rv_core_ibex_smc.corei",
+ type: "host",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ pipeline: "false"
+ },
+ { name: "rv_core_ibex_smc.cored",
+ type: "host",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ pipeline: "false"
+ },
+ { name: "dma_smc.reader",
+ type: "host",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ pipeline: "false"
+ },
+ { name: "dma_smc.writer",
+ type: "host",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ pipeline: "false"
+ },
+ { name: "rv_plic_smc",
+ type: "device",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ inst_type: "rv_plic",
+ pipeline_byp: "false"
+ },
+ { name: "rv_core_ibex_smc.cfg",
+ type: "device",
+ clock: "clk_smc_i"
+ reset: "rst_smc_ni"
+ pipeline_byp: "false"
+ },
+ { name: "ram_smc",
+ type: "device",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ pipeline: "false"
+ },
+ { name: "smc_uart",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "rv_timer_smc",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "tlul_mailbox_smc",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "smc_ctrl",
+ type: "device",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "cam_i2c",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "cam_ctrl",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "ml_top.dmem",
+ type: "device",
+ clock: "clk_ml_i",
+ reset: "rst_ml_ni",
+ pipeline: "false"
+ },
+ { name: "ml_top.core",
+ type: "device",
+ clock: "clk_ml_i",
+ reset: "rst_ml_ni",
+ pipeline: "false"
+ },
+ { name: "isp_wrapper",
+ type: "device",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ pipeline: "false"
+ },
+ { name: "dma_smc",
+ type: "device",
+ clock: "clk_smc_i",
+ reset: "rst_smc_ni",
+ pipeline: "false"
+ },
+ { name: "spi_host2",
+ type: "device",
+ clock: "clk_spi_host2_i",
+ reset: "rst_spi_host2_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "dbg",
+ type: "device",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
+ xbar: "true",
+ pipeline: "false"
+ },
+ { name: "rv_timer_smc2",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ { name: "i2s0",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
+ },
+ ],
+ connections: {
+ // TODO: connections from main xbar (security core) to some of the SMC subsystem peripherals,
+ // such as smc_uart, rv_timer_smc, cam_i2c, cam_ctrl, isp_wrapper are optional to
+ // allow software tests to run from the security core. They may be removed
+ // in the final silicon netlist.
+ main: ["ram_smc", "smc_ctrl", "smc_uart", "rv_timer_smc", "cam_i2c", "cam_ctrl",
+ "ml_top.dmem","ml_top.core", "isp_wrapper", "dma_smc", "spi_host2", "rv_timer_smc2", "i2s0"],
+
+ rv_core_ibex_smc.corei: ["ram_smc", "dbg"],
+ rv_core_ibex_smc.cored: [ "ram_smc", "rv_core_ibex_smc.cfg",
+ "smc_uart", "rv_timer_smc", "rv_plic_smc", "tlul_mailbox_smc", "cam_i2c", "cam_ctrl",
+ "ml_top.dmem", "ml_top.core", "isp_wrapper", "dma_smc", "spi_host2", "dbg", "rv_timer_smc2", "i2s0"],
+ dma_smc.reader: ["ram_smc", "ml_top.dmem"],
+ dma_smc.writer: ["ram_smc", "ml_top.dmem"],
+ },
+}
diff --git a/hw/top_sencha/dv/BUILD b/hw/top_sencha/dv/BUILD
new file mode 100644
index 0000000..494de42
--- /dev/null
+++ b/hw/top_sencha/dv/BUILD
@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "config",
+ srcs = [
+ "chip_rom_tests.hjson",
+ "chip_sim_cfg.hjson",
+ "chip_smoketests.hjson",
+ ],
+)
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/dv/chip_rom_tests.hjson b/hw/top_sencha/dv/chip_rom_tests.hjson
new file mode 100644
index 0000000..ebe8d5a
--- /dev/null
+++ b/hw/top_sencha/dv/chip_rom_tests.hjson
@@ -0,0 +1,99 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ # This auxiliary chip sim cfg specification focuses on chip level rom functional tests.
+ # Please see chip_sim_cfg.hjson for full setup details.
+
+ # Note: Please maintain alphabetical order.
+ tests: [
+ // ROM E2E tests.
+ {
+ name: rom_e2e_smoke
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/silicon_creator/rom/e2e:empty_test_slot_a:1:signed:ot_flash_binary"]
+ en_run_modes: ["sw_test_mode_rom"]
+ run_opts: ["+sw_test_timeout_ns=20000000"]
+ }
+ {
+ name: rom_e2e_jtag_debug_test_unlocked0
+ uvm_test_seq: chip_sw_rom_e2e_jtag_debug_vseq
+ sw_images: [
+ "//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled:4",
+ ]
+ en_run_modes: ["sw_test_mode_rom"]
+ run_opts: [
+ "+use_jtag_dmi=1",
+ "+use_otp_image=OtpTypeCustom",
+ ]
+ reseed: 1
+ run_timeout_mins: 120
+ }
+ {
+ name: rom_e2e_jtag_debug_dev
+ uvm_test_seq: chip_sw_rom_e2e_jtag_debug_vseq
+ sw_images: [
+ "//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled:4",
+ ]
+ en_run_modes: ["sw_test_mode_rom"]
+ run_opts: [
+ "+use_jtag_dmi=1",
+ "+use_otp_image=OtpTypeCustom",
+ ]
+ reseed: 1
+ run_timeout_mins: 120
+ }
+ {
+ name: rom_e2e_jtag_debug_rma
+ uvm_test_seq: chip_sw_rom_e2e_jtag_debug_vseq
+ sw_images: [
+ "//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled:4",
+ ]
+ en_run_modes: ["sw_test_mode_rom"]
+ run_opts: [
+ "+use_jtag_dmi=1",
+ "+use_otp_image=OtpTypeCustom",
+ ]
+ reseed: 1
+ run_timeout_mins: 120
+ }
+ // Signed chip-level tests to be run with ROM, instead of test ROM.
+ {
+ name: chip_sw_uart_smoketest_signed
+ uvm_test_seq: chip_sw_uart_smoke_vseq
+ sw_images: ["//sw/device/tests:uart_smoketest_signed:1:signed"]
+ en_run_modes: ["sw_test_mode_rom"]
+ run_opts: ["+sw_test_timeout_ns=20000000"]
+ run_timeout_mins: 180
+ }
+
+ // ROM func tests to be run with test ROM.
+ {
+ name: rom_keymgr_functest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/silicon_creator/lib/drivers:keymgr_functest:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=10_000_000"]
+ }
+ ]
+
+ regressions: [
+ {
+ name: rom_functests
+ tests: ["rom_keymgr_functest"]
+ }
+ {
+ name: signed
+ tests: ["chip_sw_uart_smoketest_signed"]
+ }
+ {
+ name: rom_e2e_jtag_debug
+ tests: [
+ "rom_e2e_jtag_debug_test_unlocked0",
+ "rom_e2e_jtag_debug_dev",
+ "rom_e2e_jtag_debug_rma",
+ ]
+ }
+ ]
+}
diff --git a/hw/top_sencha/dv/chip_sim_cfg.hjson b/hw/top_sencha/dv/chip_sim_cfg.hjson
new file mode 100644
index 0000000..8d65c94
--- /dev/null
+++ b/hw/top_sencha/dv/chip_sim_cfg.hjson
@@ -0,0 +1,2510 @@
+// Copyright 2022-2023 Google LLC.
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Name of the sim cfg - typically same as the name of the DUT.
+ name: chip
+
+ // Top level dut name (sv module).
+ dut: chip_sencha_asic
+
+ // Top level testbench name (sv module).
+ tb: tb
+
+ // Default simulator used to sign off.
+ tool: vcs
+
+ // Fusesoc core file used for building the file list.
+ fusesoc_core: lowrisc:dv:chip_sim:0.1
+
+ // Testplan hjson file, excluding the connectivity tests.
+ testplan: "{proj_root}/hw/top_sencha/data/chip_testplan.hjson:-conn:-no_dv"
+
+ // RAL spec - used to generate the RAL model.
+ ral_spec: "{proj_root}/hw/top_sencha/data/top_sencha.hjson"
+
+ // Add additional tops for simulation.
+ sim_tops: [// TODO: Enable SVA
+ // "clkmgr_bind",
+ // "pwrmgr_bind",
+ // "rstmgr_bind",
+ "sec_cm_prim_onehot_check_bind",
+ "sec_cm_prim_sparse_fsm_flop_bind",
+ "top_sencha_error_injection_ifs_bind",
+ // "top_sencha_bind",
+ "xbar_main_bind",
+ "xbar_peri_bind",
+ "xbar_smc_bind",
+ "xbar_dbg_bind"]
+
+ top_dv_path: "{proj_root}/hw/top_sencha/dv"
+
+ // Import additional common sim cfg files.
+ import_cfgs: [// Project wide common sim cfg file
+ "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
+ // Common CIP test lists
+ // Enable C compilation of AES model for DPI-C
+ "{titan_root}/hw/ip/aes/model/aes_model_sim_opts.hjson",
+
+ "{titan_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
+ // TODO #5484, comment these 2 lines out because spi host memory is dummy
+ // "{titan_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
+ // xbar tests
+ "{titan_root}/hw/ip/tlul/generic_dv/xbar_tests.hjson",
+ // Config files to get the correct flags for otbn_memutil and otbn_tracer
+ "{titan_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson",
+ "{titan_root}/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson",
+ "{titan_root}/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson",
+ "{top_dv_path}/chip_smoketests.hjson",
+ "{top_dv_path}/chip_rom_tests.hjson",
+ ]
+
+ // Override existing project defaults to supply chip-specific values.
+ overrides: [
+ // Chip level design is markedly different from our Comportable IPs (and so
+ // is our coverage goals). The coverage goals also differ between 'default'
+ // and the 'cover_reg_top' (used by common tests) builds. We override the
+ // variables below to swap the coverage cfg files used for the Comportable
+ // IPs with chip-specific ones. See `doc/ug/dv_methodology.md` for more
+ // details.
+
+ // Used by all chip level functional test. Collects coverage on the IO
+ // boundary of all pre-verified IPs and full coverage on non-pre-verified
+ // IPs. See `hw/dv/tools/dvsim/common_sim_cfg.hjson` for the default value.
+ {
+ name: default_vcs_cov_cfg_file
+ value: "-cm_hier {top_dv_path}/cov/chip_cover.cfg+{top_dv_path}/autogen/xbar_tgl_excl.cfg+{top_dv_path}/autogen/rstmgr_tgl_excl.cfg+{top_dv_path}/cov/clkmgr_tgl_excl.cfg+{top_dv_path}/cov/pwrmgr_tgl_excl.cfg -cm_fsmcfg {top_dv_path}/cov/chip_fsm.cfg"
+ }
+ // Used by 'cover_reg_top' only builds - we only cover the *_reg_top of
+ // the non-pre-verified modules at the chip level. See
+ // `hw/dv/tools/dvsim/common_sim_cfg.hjson` for the default value.
+ {
+ name: cover_reg_top_vcs_cov_cfg_file
+ value: "-cm_hier {top_dv_path}/cov/chip_cover_reg_top.cfg+{top_dv_path}/autogen/xbar_tgl_excl.cfg"
+ }
+ {
+ name: xbar_build_mode_vcs_cov_cfg_file
+ value: "-cm_hier {top_dv_path}/cov/chip_cover_reg_top.cfg+{top_dv_path}/autogen/xbar_tgl_excl.cfg"
+ }
+ // Used by the UNR flow.
+ {
+ name: vcs_unr_cfg_file
+ value: "{top_dv_path}/cov/unr.cfg"
+ }
+
+ // Used for xprop config.
+ {
+ name: vcs_xprop_cfg_file
+ value: "{top_dv_path}/vcs_xprop.cfg"
+ }
+ // This defaults to 'ip' in `hw/data/common_project_cfg.hjson`.
+ {
+ name: design_level
+ value: "top"
+ }
+ // The jtag agent requires the data and bytenable widths to be increased.
+ {
+ name: tl_dw
+ value: 64
+ }
+ {
+ name: tl_dbw
+ value: 8
+ }
+ ]
+
+ // exclusion files
+ vcs_cov_excl_files: ["{top_dv_path}/cov/chip_top_unr_tied_off.el",
+ "{top_dv_path}/cov/conn_ast_mem_cfg.el",
+ "{top_dv_path}/cov/conn_flash_ctrl_ast_obs_test_volt.el",
+ "{top_dv_path}/cov/conn_otp_ctrl_ast_obs_ext_volt.el",
+ "{top_dv_path}/cov/edn1_unr_tied_off_ports.el",
+ "{top_dv_path}/cov/entropy_src_tied_off_xht_port.el",
+ "{top_dv_path}/cov/lc_ctrl_hw_rev_tied_off.el",
+ "{top_dv_path}/cov/pinmux_pad_attr.el",
+ "{top_dv_path}/cov/plic_le_i_tied_off.el",
+ "{top_dv_path}/cov/plic_ip_wr_en_tied_off.el",
+ "{top_dv_path}/cov/rom_ctrl_kmac_app_tied_off_data_strb_bits.el",
+ "{top_dv_path}/cov/spi_host_device_unr_tied_off.el"
+ ]
+
+ // Default iterations for all tests - each test entry can override this.
+ reseed: 3
+
+ // Default UVM test and seq class name.
+ uvm_test: chip_base_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_build_device: sim_dv
+
+ // Add a default build option to indicate it is a top-level DV testbench.
+ build_opts: ["+define+TOP_LEVEL_DV"]
+
+ // Add build modes.
+ build_modes: [
+ {
+ name: en_ibex_tracer
+ build_opts: ["+define+RVFI=1"]
+ }
+ // Sim mode that enables build randomization. See the `build_seed` mode
+ // defined in `hw/dv/tools/dvsim/common_modes.hjson` for more details.
+ {
+ name: build_seed
+ pre_build_cmds: [
+ // TODO: find where in run phase we are using this pkg. It fails during ibex TLUL integrity
+ // check.
+ // '''cd {proj_root} && ./util/topgen.py -t {ral_spec} \
+ // -o hw/top_sencha --rnd_cnst_seed {seed}
+ // ''',
+ // Generate LC encoding
+ "cd {proj_root} && ./util/design/gen-lc-state-enc.py --seed {seed}",
+ // Generate OTP memory map and scrambling constants keys.
+ "cd {proj_root} && ./util/design/gen-otp-mmap.py --seed {seed}",
+ // Use eval_cmd to save build_seed in a file and reuse that file during run phase.
+ // Create the build directory first because eval_cmd runs before actual build phase command
+ // execution.
+ '''{eval_cmd} mkdir -p {build_dir}; echo {seed} > {build_seed_file_path}; \
+ echo "echo create file {build_seed_file_path}"
+ '''
+ ]
+ is_sim_mode: 1
+ }
+ // Build mode that disables rom integrity checks, so use it only for
+ // test development.
+ // DO NOT USE FOR NIGHTLY
+ {
+ name: fast_sim_build_dev
+ build_opts: ["+define+DISABLE_ROM_INTEGRITY_CHECK"]
+ is_sim_mode: 1
+ }
+ // This fast sim mode adds AST runtime plusargs from the fast_sim run
+ // mode on top of disabling rom integrity checks. It is the fastest way
+ // to run a test.
+ // DO NOT USE FOR NIGHTLY
+ {
+ name: fast_sim_dev
+ en_build_modes: ["fast_sim_build_dev"]
+ run_opts: ["+accelerate_cold_power_up_time=3",
+ "+accelerate_regulators_power_up_time=2"]
+ is_sim_mode: 1
+ }
+ // TODO: VCS does not support MDAs in constfiles. Most RTL ports in OpenTitan are structs, so
+ // this method currently does not work for our needs. Revisit later.
+ // {
+ // name: vcs_cov
+ // build_opts: ["-cm_constfile {top_dv_path}/cov/constfile.txt"]
+ // is_sim_mode: 1
+ // }
+ {
+ name: cover_reg_top_no_dma
+ en_build_modes: ["cover_reg_top"]
+ }
+ ]
+
+ // Add options needed to compile against otbn_memutil, otbn_tracer,
+ // memutil_dpi_scrambled, and AES C model
+ en_build_modes: ["{tool}_otbn_memutil_build_opts",
+ "{tool}_otbn_tracer_build_opts",
+ "{tool}_memutil_dpi_scrambled_build_opts",
+ "{tool}_aes_model_build_opts"]
+
+ // Setup for generating OTP images.
+ gen_otp_images_cfg_dir: "{titan_root}/hw/ip/otp_ctrl/data"
+ gen_otp_images_cmd: "{titan_root}/util/design/gen-otp-img.py"
+ gen_otp_images_cmd_opts: ["--quiet",
+ "--img-seed {seed}",
+ // Only provide `--otp-seed` argument if the file to store build_seed
+ // is found. Set this option at the end of the list to avoid `eval_cmd`
+ // take other options as eval_cmd.
+ '''{eval_cmd} file=`echo {build_seed_file_path}`; \
+ if [ -f $file ]; then \
+ while read line; do \
+ echo "--otp-seed $line --lc-seed $line"; \
+ done < $file; \
+ fi ''']
+ // Add run modes.
+ run_modes: [
+ // Generates OTP images with different LC states with canonical values,
+ // pseudo-randomized with the same test seed.
+ {
+ name: gen_otp_images_mode
+ pre_run_cmds: [
+ '''{gen_otp_images_cmd} \
+ --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_raw.hjson \
+ --out {run_dir}/otp_ctrl_img_raw.vmem \
+ {gen_otp_images_cmd_opts}
+ ''',
+ '''{gen_otp_images_cmd} \
+ --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_test_unlocked0.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_hw_cfg.hjson \
+ --out {run_dir}/otp_ctrl_img_test_unlocked0.vmem \
+ {gen_otp_images_cmd_opts}
+ ''',
+ '''{gen_otp_images_cmd} \
+ --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_test_unlocked1.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_hw_cfg.hjson \
+ --out {run_dir}/otp_ctrl_img_test_unlocked1.vmem \
+ {gen_otp_images_cmd_opts}
+ ''',
+ '''{gen_otp_images_cmd} \
+ --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_test_unlocked2.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_hw_cfg.hjson \
+ --out {run_dir}/otp_ctrl_img_test_unlocked2.vmem \
+ {gen_otp_images_cmd_opts}
+ ''',
+ '''{gen_otp_images_cmd} \
+ --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_test_locked0.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_hw_cfg.hjson \
+ --out {run_dir}/otp_ctrl_img_test_locked0.vmem \
+ {gen_otp_images_cmd_opts}
+ ''',
+ '''{gen_otp_images_cmd} \
+ --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_test_locked1.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_hw_cfg.hjson \
+ --out {run_dir}/otp_ctrl_img_test_locked1.vmem \
+ {gen_otp_images_cmd_opts}
+ ''',
+ '''{gen_otp_images_cmd} \
+ --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_dev.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_creator_sw_cfg.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_owner_sw_cfg.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_hw_cfg.hjson \
+ --out {run_dir}/otp_ctrl_img_dev.vmem \
+ {gen_otp_images_cmd_opts}
+ ''',
+ '''{gen_otp_images_cmd} \
+ --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_prod.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_creator_sw_cfg.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_owner_sw_cfg.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_hw_cfg.hjson \
+ --out {run_dir}/otp_ctrl_img_prod.vmem \
+ {gen_otp_images_cmd_opts}
+ ''',
+ '''{gen_otp_images_cmd} \
+ --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_rma.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_creator_sw_cfg.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_owner_sw_cfg.hjson \
+ --add-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_hw_cfg.hjson \
+ --out {run_dir}/otp_ctrl_img_rma.vmem \
+ {gen_otp_images_cmd_opts}
+ ''',
+ ]
+ }
+ // fast_sim mode enables public faster simulation via AST plusargs.
+ // This may be okay to use for public regressions, with the possible
+ // exception of a handful of AST tests.
+ {
+ name: fast_sim
+ run_opts: ["+accelerate_cold_power_up_time=3",
+ "+accelerate_regulators_power_up_time=2"]
+ }
+ {
+ name: sw_test_mode_common
+ run_opts: ["+sw_build_device={sw_build_device}",
+ "+stub_smc_core=1",
+ // Format SW image names (which are Bazel labels concatenated with an index
+ // and/or flags, see below) into output file names separated by commas to feed into
+ // +sw_images plusarg. For example, if the input list of SW images is
+ // ["//sw/device/tests/sim_dv:uart_tx_rx_test:1",
+ // "//sw/device/lib/testing/test_rom:test_rom:0"], then the output of this eval_cmd
+ // will be: "uart_tx_rx_test:1,test_rom:0".
+ '''+sw_images={eval_cmd} \
+ reformatted_sw_images=; \
+ for image in {sw_images}; do \
+ reformatted_sw_images="$reformatted_sw_images `echo $image | cut -d: -f2-`"; \
+ done; \
+ echo $reformatted_sw_images | sed -E 's/\s+/,/g' ''']
+ en_run_modes: ["gen_otp_images_mode"]
+ }
+ {
+ name: sw_test_mode_test_rom
+ sw_images: ["//sw/device/lib/testing/test_rom:test_rom:0"]
+ en_run_modes: ["sw_test_mode_common"]
+ }
+ {
+ name: sw_test_mode_rom
+ sw_images: ["//sw/device/silicon_creator/rom:rom_with_fake_keys:0"]
+ en_run_modes: ["sw_test_mode_common"]
+ }
+ {
+ name: stub_cpu_mode
+ // Note that the chip_base_vseq will preload a random ROM image with valid ECC and digest
+ // so that the ROM check can succeed even if no ROM image is built and supplied via Bazel.
+ en_run_modes: ["gen_otp_images_mode"]
+ run_opts: ["+stub_cpu=1"]
+ }
+ {
+ // Append stub cpu mode to csr_tests_mode.
+ name: csr_tests_mode
+ en_run_modes: ["stub_cpu_mode"]
+ }
+ {
+ // Append stub cpu mode to mem_tests_mode.
+ name: mem_tests_mode
+ en_run_modes: ["stub_cpu_mode"]
+ reseed: 20
+ }
+ {
+ name: strap_tests_mode
+ en_run_modes: ["sw_test_mode_common"]
+ // The tests using this mode only require the ROM init check to succeed.
+ // The example_test_from_rom test is sufficient.
+ sw_images: ["//sw/device/tests:example_test_from_rom:0:test_in_rom"]
+ run_opts: ["+create_jtag_riscv_map=1"]
+ reseed: 5
+ }
+ {
+ name: xbar_run_mode
+ en_run_modes: ["gen_otp_images_mode"]
+ run_opts: ["+xbar_mode=1"]
+ reseed: 100
+ }
+ {
+ name: sw_test_mode_common_with_smc
+ run_opts: ["+sw_build_device={sw_build_device}",
+ // Format SW image names (which are Bazel labels concatenated with an index
+ // and/or flags, see below) into output file names separated by commas to feed into
+ // +sw_images plusarg. For example, if the input list of SW images is
+ // ["//sw/device/tests/sim_dv:uart_tx_rx_test:1",
+ // "//sw/device/lib/testing/test_rom:test_rom:0"], then the output of this eval_cmd
+ // will be: "uart_tx_rx_test:1,test_rom:0".
+ '''+sw_images={eval_cmd} \
+ reformatted_sw_images=; \
+ for image in {sw_images}; do \
+ reformatted_sw_images="$reformatted_sw_images `echo $image | cut -d: -f2-`"; \
+ done; \
+ echo $reformatted_sw_images | sed -E 's/\s+/,/g' ''']
+ en_run_modes: ["gen_otp_images_mode"]
+ }
+ {
+ name: sw_test_mode_test_rom_with_smc
+ sw_images: ["//sw/device/lib/testing/test_rom:test_rom:0"]
+ en_run_modes: ["sw_test_mode_common_with_smc"]
+ }
+ {
+ name: sw_test_mode_test_simple_sec
+ sw_images: ["//sw/device/tests:simple_sec:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom_with_smc"]
+ }
+ ]
+
+ // List of test specifications.
+ //
+ // If you are adding a test that has been generated from a Bazel
+ // `opentitan_functest` macro, you can specify the test using its Bazel label
+ // followed by an index separated with a ':', which is used by the testbench
+ // to know what type of image is it:
+ // - 0 for Boot ROM,
+ // - 1 for SW test (loaded in flash),
+ // - 2 for OTBN test, and
+ // - 3 for OTP.
+ // This allows an arbitrary number of SW images to be supplied to the TB.
+ //
+ // For example, if the Bazel label for a test is:
+ // `//sw/device/tests:example_test_from_flash`, then you would specify this as
+ // `//sw/device/tests:example_test_from_flash:1`.
+ //
+ // To calculate the value of `+sw_test_timeout_ns` run dvsim by:
+ // $ util/dvsim/dvsim.py hw/top_sencha/dv/top_sencha_sim_cfgs.hjson \
+ // -i TEST_NAME --fixed-seed=1
+ // Run this a few times and take the worst case runtime, then increase this
+ // value by 20% and use the relationship that 5 minutes of runtime is roughly
+ // 4 milliseconds of timeout.
+ tests: [
+ {
+ name: chip_sw_smc_isp_wrapper_tpg_128_64_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_tpg_128_64_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_env_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_env_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_isp_wrapper_irq_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_irq_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_tlul_mailbox_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: [
+ "//sw/device/tests:tlul_mailbox_test:1:ot_flash_binary:matcha",
+ "//sw/device/tests/smc:smc_tlul_mailbox_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom_with_smc"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_cam_irq_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_cam_irq_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_ml_sram_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_ml_dmem_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_kelvin_hello_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: [
+ "//sw/device/tests/smc:smc_kelvin_hello_test:6:matcha",
+ "//sw/device/tests/kelvin:kelvin_hello_world:7:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_ml_top_irq_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_ml_top_irq_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_supervisor_mode_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_supervisor_mode_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_virtual_memory_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_virtual_memory_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_interrupt_boundary_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_interrupt_boundary_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_lsu_interrupt_boundary_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_lsu_interrupt_boundary_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_page_boundary_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_page_boundary_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_lsu_page_boundary_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_lsu_page_boundary_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_atomics_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_atomics_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_cam_ctrl_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:cam_ctrl_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_crt_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:crt_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_dma_main_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:dma_main_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_mem_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:mem_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_ctrl_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:smc_ctrl_test:1:ot_flash_binary:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_i2s_rx_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_i2s_rx_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_i2s_tx_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_i2s_tx_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_rv_timer_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_rv_timer_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_kelvin_checksum_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: [
+ "//sw/device/tests/smc:smc_kelvin_checksum_test:6:matcha",
+ "//sw/device/tests/kelvin:kelvin_checksum:7:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_smc_kelvin_model_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_kelvin_model_test:6:matcha",
+ "//sw/device/examples/testdata:kelvin_model_ml:7:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=160_000_000"]
+ }
+ {
+ name: chip_sw_smc_isp_wrapper_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/smc:smc_isp_wrapper_test:6:matcha"]
+ en_run_modes: ["sw_test_mode_test_simple_sec"]
+ run_opts:["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ // Reused from hw/dv/tools/dvsim/tests/csr_tests.hjson.
+ name: "chip_csr_bit_bash"
+ // Don't test over 200 randomly picked CSRs at a time.
+ run_opts: ["+test_timeout_ns=120_000_000", "+num_test_csrs=200"]
+ run_timeout_mins: 180
+ }
+ {
+ // Reused from hw/dv/tools/dvsim/tests/csr_tests.hjson.
+ name: "chip_csr_aliasing"
+ run_timeout_mins: 180
+ run_opts: ["+test_timeout_ns=120_000_000"]
+ }
+ {
+ // Reused from hw/dv/tools/dvsim/tests/csr_tests.hjson.
+ name: "chip_same_csr_outstanding"
+ run_timeout_mins: 120
+ run_opts: ["+test_timeout_ns=120_000_000"]
+ }
+ {
+ name: chip_sw_example_flash
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:example_test_from_flash:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_example_rom
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:example_test_from_rom:0:test_in_rom"]
+ en_run_modes: ["sw_test_mode_common"]
+ }
+ {
+ name: chip_sw_example_manufacturer
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["@manufacturer_test_hooks//:example_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_example_concurrency
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:example_concurrency_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_all_escalation_resets
+ uvm_test_seq: chip_sw_all_escalation_resets_vseq
+ sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1"]
+ reseed: 100
+ }
+ {
+ name: chip_sw_rstmgr_rst_cnsty_escalation
+ uvm_test_seq: chip_sw_rstmgr_cnsty_fault_vseq
+ sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1"]
+ }
+ {
+ name: chip_sw_data_integrity_escalation
+ uvm_test_seq: chip_sw_data_integrity_vseq
+ sw_images: ["//sw/device/tests/sim_dv:data_integrity_escalation_reset_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1"]
+ reseed: 6
+ }
+ {
+ name: chip_sw_sleep_pin_mio_dio_val
+ uvm_test_seq: chip_sw_sleep_pin_mio_dio_val_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sleep_pin_mio_dio_val_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ // Starting the chip in prod LC state frees up all MIOs for this test.
+ run_opts: ["+use_otp_image=OtpTypeLcStProd"]
+ }
+ {
+ name: chip_sw_sleep_pin_wake
+ uvm_test_seq: chip_sw_sleep_pin_wake_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sleep_pin_wake_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ // Starting the chip in prod LC state frees up all MIOs for this test.
+ run_opts: ["+use_otp_image=OtpTypeLcStProd"]
+ }
+ {
+ name: chip_sw_sleep_pin_retention
+ uvm_test_seq: chip_sw_sleep_pin_retention_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sleep_pin_retention_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_sleep_pwm_pulses
+ uvm_test_seq: chip_sw_pwm_pulses_vseq
+ sw_images: ["//sw/device/tests:sleep_pwm_pulses_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_pattgen_ios
+ uvm_test_seq: chip_sw_patt_ios_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pattgen_ios_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=5_000_000"]
+ }
+ {
+ name: chip_sw_uart_tx_rx
+ uvm_test_seq: chip_sw_uart_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+uart_idx=0", "+calibrate_usb_clk=1"]
+ reseed: 5
+ }
+ {
+ name: chip_sw_uart_tx_rx_lc_test
+ uvm_test_seq: chip_sw_uart_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+uart_idx=0", "+calibrate_usb_clk=1", "+raw_otp_jtag=1", "+use_otp_image=OtpTypeLcStRaw"]
+ }
+ {
+ name: chip_sw_uart_tx_rx_idx1
+ uvm_test_seq: chip_sw_uart_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+uart_idx=1", "+calibrate_usb_clk=1"]
+ reseed: 5
+ }
+ {
+ name: chip_sw_uart_tx_rx_idx2
+ uvm_test_seq: chip_sw_uart_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+uart_idx=2", "+calibrate_usb_clk=1"]
+ reseed: 5
+ }
+ {
+ name: chip_sw_uart_tx_rx_idx3
+ uvm_test_seq: chip_sw_uart_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+uart_idx=3", "+calibrate_usb_clk=1"]
+ reseed: 5
+ }
+ {
+ name: chip_sw_uart_tx_rx_bootstrap
+ uvm_test_seq: chip_sw_uart_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+use_spi_load_bootstrap=1", "+calibrate_usb_clk=1",
+ "+test_timeout_ns=80_000_000"]
+ run_timeout_mins: 180
+ }
+ {
+ name: chip_sw_inject_scramble_seed
+ uvm_test_seq: chip_sw_inject_scramble_seed_vseq
+ sw_images: ["//sw/device/tests/sim_dv:inject_scramble_seed:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+lc_at_prod=1", "+flash_program_latency=5", "+sw_test_timeout_ns=150_000_000"]
+ run_timeout_mins: 180
+ }
+ {
+ name: chip_sw_exit_test_unlocked_bootstrap
+ uvm_test_seq: chip_sw_exit_test_unlocked_bootstrap_vseq
+ sw_images: ["//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+flash_program_latency=5", "+sw_test_timeout_ns=150_000_000"]
+ run_timeout_mins: 180
+ }
+ {
+ name: chip_sw_uart_rand_baudrate
+ uvm_test_seq: chip_sw_uart_rand_baudrate_vseq
+ sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=80_000_000", "+calibrate_usb_clk=1"]
+ reseed: 20
+ }
+ {
+ name: chip_sw_uart_tx_rx_alt_clk_freq
+ uvm_test_seq: chip_sw_uart_rand_baudrate_vseq
+ sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=80_000_000",
+ "+chip_clock_source=ChipClockSourceExternal96Mhz", "+calibrate_usb_clk=1"]
+ reseed: 5
+ }
+ {
+ name: chip_sw_uart_tx_rx_alt_clk_freq_low_speed
+ uvm_test_seq: chip_sw_uart_rand_baudrate_vseq
+ sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=80_000_000", "+calibrate_usb_clk=1",
+ "+chip_clock_source=ChipClockSourceExternal48Mhz"]
+ reseed: 5
+ }
+ {
+ name: chip_sw_i2c_host_tx_rx
+ uvm_test_seq: chip_sw_i2c_host_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:i2c_host_tx_rx_test:1:matcha"]
+ run_opts: ["+i2c_idx=0"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_i2c_host_tx_rx_idx1
+ uvm_test_seq: chip_sw_i2c_host_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:i2c_host_tx_rx_test:1"]
+ run_opts: ["+i2c_idx=1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_i2c_host_tx_rx_idx2
+ uvm_test_seq: chip_sw_i2c_host_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:i2c_host_tx_rx_test:1"]
+ run_opts: ["+i2c_idx=2"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_i2c_device_tx_rx
+ uvm_test_seq: chip_sw_i2c_device_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:i2c_device_tx_rx_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_spi_device_tx_rx
+ uvm_test_seq: chip_sw_spi_device_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:spi_tx_rx_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_spi_device_tpm
+ uvm_test_seq: chip_sw_spi_device_tpm_vseq
+ sw_images: ["//sw/device/tests/sim_dv:spi_device_tpm_tx_rx_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_spi_host_tx_rx
+ uvm_test_seq: chip_sw_spi_host_tx_rx_vseq
+ sw_images: ["//sw/device/tests/sim_dv:spi_host_tx_rx_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_spi_device_pass_through
+ uvm_test_seq: chip_sw_spi_passthrough_vseq
+ sw_images: ["//sw/device/tests/sim_dv:spi_passthrough_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_spi_device_pass_through_collision
+ uvm_test_seq: chip_sw_spi_passthrough_collision_vseq
+ sw_images: ["//sw/device/tests/sim_dv:spi_passthrough_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_gpio
+ uvm_test_seq: chip_sw_gpio_vseq
+ sw_images: ["//sw/device/tests/sim_dv:gpio_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_flash_ctrl_ops
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:flash_ctrl_ops_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=14_000_000"]
+ }
+ {
+ name: chip_sw_flash_ctrl_ops_jitter_en
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:flash_ctrl_ops_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=14_000_000", "+en_jitter=1"]
+ }
+ {
+ name: chip_sw_flash_ctrl_lc_rw_en
+ uvm_test_seq: chip_sw_flash_ctrl_lc_rw_en_vseq
+ sw_images: ["//sw/device/tests/sim_dv:flash_ctrl_lc_rw_en_test:1"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_flash_ctrl_access
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:flash_ctrl_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_flash_ctrl_access_jitter_en
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:flash_ctrl_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_jitter=1"]
+ }
+ {
+ name: chip_sw_flash_ctrl_idle_low_power
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:flash_ctrl_idle_low_power_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_flash_init
+ uvm_test_seq: chip_sw_flash_init_vseq
+ sw_images: ["//sw/device/tests/sim_dv:flash_init_test:0:test_in_rom"]
+ en_run_modes: ["sw_test_mode_common"]
+ run_opts: ["+sw_test_timeout_ns=25_000_000"]
+ }
+ {
+ name: chip_sw_flash_rma_unlocked
+ uvm_test_seq: chip_sw_flash_rma_unlocked_vseq
+ sw_images: ["//sw/device/tests/sim_dv:flash_rma_unlocked_test:0:test_in_rom"]
+ en_run_modes: ["sw_test_mode_common"]
+ run_opts: ["+flash_program_latency=5", "+sw_test_timeout_ns=150_000_000"]
+ run_timeout_mins: 200
+ }
+ {
+ name: chip_sw_flash_ctrl_clock_freqs
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:flash_ctrl_clock_freqs_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_kmac_entropy
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:kmac_entropy_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_lc_ctrl_otp_hw_cfg
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:lc_ctrl_otp_hw_cfg_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_otp_ctrl_lc_signals_test_unlocked0
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"],
+ // Use the image as basis, but clear provitioning state of the SECRET2
+ // partition so that the test can make front-door accesses to that partition.
+ run_opts: ["+use_otp_image=OtpTypeLcStTestUnlocked0", "+otp_clear_secret2=1"]
+ }
+ {
+ name: chip_sw_otp_ctrl_lc_signals_dev
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"],
+ // Use the image as basis, but clear provitioning state of the SECRET2
+ // partition so that the test can make front-door accesses to that partition.
+ run_opts: ["+use_otp_image=OtpTypeLcStDev", "+otp_clear_secret2=1"]
+ }
+ {
+ name: chip_sw_otp_ctrl_lc_signals_prod
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"],
+ // Use the image as basis, but clear provitioning state of the SECRET2
+ // partition so that the test can make front-door accesses to that partition.
+ run_opts: ["+use_otp_image=OtpTypeLcStProd", "+otp_clear_secret2=1"]
+ }
+ {
+ name: chip_sw_otp_ctrl_lc_signals_rma
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"],
+ // Use the image as basis, but clear provitioning state of the SECRET2
+ // partition so that the test can make front-door accesses to that partition.
+ run_opts: ["+use_otp_image=OtpTypeLcStRma", "+otp_clear_secret2=1"]
+ }
+ {
+ name: chip_sw_otp_ctrl_vendor_test_csr_access
+ uvm_test_seq: chip_sw_otp_ctrl_vendor_test_csr_access_vseq
+ sw_images: ["//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_otp_ctrl_escalation
+ uvm_test_seq: chip_sw_otp_ctrl_escalation_vseq
+ sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1"]
+ reseed: 1
+ }
+ {
+ // Set higher reseed value to reach all kmac_data to lc_ctrl toggle coverage.
+ name: chip_sw_lc_ctrl_transition
+ uvm_test_seq: chip_sw_lc_ctrl_transition_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_transition_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ reseed: 15
+ }
+
+ {
+ name: chip_sw_lc_ctrl_rma_to_scrap
+ uvm_test_seq: chip_sw_lc_ctrl_scrap_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_scrap_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1",
+ "+src_dec_state=DecLcStRma"]
+ reseed: 1
+ }
+ {
+ name: chip_sw_lc_ctrl_raw_to_scrap
+ uvm_test_seq: chip_sw_lc_ctrl_scrap_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_scrap_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1",
+ "+src_dec_state=DecLcStRaw"]
+ reseed: 1
+ }
+ {
+ name: chip_sw_lc_ctrl_test_locked0_to_scrap
+ uvm_test_seq: chip_sw_lc_ctrl_scrap_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_scrap_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1",
+ "+src_dec_state=DecLcStTestLocked0"]
+ reseed: 1
+ }
+ {
+ name: chip_sw_lc_ctrl_rand_to_scrap
+ uvm_test_seq: chip_sw_lc_ctrl_scrap_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_scrap_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1"]
+ reseed: 3
+ }
+ {
+ name: chip_sw_lc_walkthrough_dev
+ uvm_test_seq: chip_sw_lc_walkthrough_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+flash_program_latency=5",
+ "+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStDev",
+ // The test takes long time because it will transit to RMA state
+ "+sw_test_timeout_ns=200_000_000"]
+ run_timeout_mins: 240
+ }
+ {
+ name: chip_sw_lc_walkthrough_prod
+ uvm_test_seq: chip_sw_lc_walkthrough_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+flash_program_latency=5",
+ "+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStProd",
+ // The test takes long time because it will transit to RMA state
+ "+sw_test_timeout_ns=200_000_000"]
+ run_timeout_mins: 240
+ }
+ {
+ name: chip_sw_lc_walkthrough_prodend
+ uvm_test_seq: chip_sw_lc_walkthrough_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+flash_program_latency=5",
+ "+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStProdEnd"]
+ }
+ {
+ name: chip_sw_lc_walkthrough_rma
+ uvm_test_seq: chip_sw_lc_walkthrough_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStRma",
+ "+flash_program_latency=5",
+ // The test takes long time because it will transit to RMA state
+ "+sw_test_timeout_ns=200_000_000"]
+ run_timeout_mins: 240
+ }
+ {
+ name: chip_sw_lc_walkthrough_testunlocks
+ uvm_test_seq: chip_sw_lc_walkthrough_testunlocks_vseq
+ sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStTestUnlock7"]
+ }
+ {
+ name: chip_sw_rstmgr_sw_req
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:rstmgr_sw_req_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_rstmgr_sw_rst
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:rstmgr_sw_rst_ctrl_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_rstmgr_alert_info
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:rstmgr_alert_info_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=30_000_000", "+en_scb_tl_err_chk=0"]
+ run_timeout_mins: 120
+ }
+ {
+ name: chip_sw_rstmgr_cpu_info
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:rstmgr_cpu_info_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_pwrmgr_full_aon_reset
+ uvm_test_seq: chip_sw_full_aon_reset_vseq
+ sw_images: ["//sw/device/tests:rstmgr_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_pwrmgr_main_power_glitch_reset
+ uvm_test_seq: chip_sw_main_power_glitch_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1"]
+ }
+ {
+ name: chip_sw_pwrmgr_sysrst_ctrl_reset
+ uvm_test_seq: chip_sw_sysrst_ctrl_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_sysrst_ctrl_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_pwrmgr_random_sleep_all_reset_reqs
+ uvm_test_seq: chip_sw_random_sleep_all_reset_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_random_sleep_all_reset_reqs_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=50_000_000"]
+ run_timeout_mins: 120
+ }
+ {
+ name: chip_sw_pwrmgr_deep_sleep_all_reset_reqs
+ uvm_test_seq: chip_sw_deep_sleep_all_reset_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_deep_sleep_all_reset_reqs_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=50_000_000"]
+ run_timeout_mins: 120
+ }
+ {
+ name: chip_sw_pwrmgr_normal_sleep_all_reset_reqs
+ uvm_test_seq: chip_sw_deep_sleep_all_reset_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_normal_sleep_all_reset_reqs_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_timeout_mins: 120
+ }
+ {
+ name: chip_sw_pwrmgr_sleep_power_glitch_reset
+ uvm_test_seq: chip_sw_main_power_glitch_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1"]
+ }
+ {
+ name: chip_sw_pwrmgr_deep_sleep_power_glitch_reset
+ uvm_test_seq: chip_sw_deep_power_glitch_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1"]
+ }
+ {
+ name: chip_sw_pwrmgr_random_sleep_power_glitch_reset
+ uvm_test_seq: chip_sw_random_power_glitch_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+bypass_alert_ready_to_end_check=1",
+ "+sw_test_timeout_ns=24_000_000"]
+ run_timeout_mins: 120
+ }
+ {
+ name: chip_sw_pwrmgr_sleep_disabled
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:pwrmgr_sleep_disabled_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_rv_timer_irq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:rv_timer_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_inputs
+ uvm_test_seq: chip_sw_sysrst_ctrl_inputs_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sysrst_ctrl_inputs_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_in_irq
+ uvm_test_seq: chip_sw_sysrst_ctrl_in_irq_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sysrst_ctrl_in_irq_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_ulp_z3_wakeup
+ uvm_test_seq: chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sysrst_ctrl_ulp_z3_wakeup_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_reset
+ uvm_test_seq: chip_sw_sysrst_ctrl_reset_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sysrst_ctrl_reset_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=36_000_000"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_outputs
+ uvm_test_seq: chip_sw_sysrst_ctrl_outputs_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sysrst_ctrl_outputs_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_sysrst_ctrl_ec_rst_l
+ uvm_test_seq: chip_sw_sysrst_ctrl_ec_rst_l_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sysrst_ctrl_ec_rst_l_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_aon_timer_irq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aon_timer_irq_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000"]
+ }
+ {
+ name: chip_sw_aon_timer_sleep_wdog_sleep_pause
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000"]
+ reseed: 5
+ }
+ {
+ name: chip_sw_aon_timer_wdog_bite_reset
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aon_timer_wdog_bite_reset_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000"]
+ }
+ {
+ name: chip_sw_pwrmgr_wdog_reset
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:pwrmgr_wdog_reset_reqs_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000"]
+ }
+ {
+ name: chip_sw_aon_timer_wdog_lc_escalate
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aon_timer_wdog_lc_escalate_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000"]
+ }
+ {
+ name: chip_sw_adc_ctrl_sleep_debug_cable_wakeup
+ uvm_test_seq: chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq
+ sw_images: ["//sw/device/tests/sim_dv:adc_ctrl_sleep_debug_cable_wakeup_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000"]
+ }
+ {
+ name: chip_sw_otbn_randomness
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:otbn_randomness_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000","+rng_srate_value=30"]
+ }
+ {
+ name: chip_sw_otbn_ecdsa_op_irq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=28_000_000", "+rng_srate_value=30"]
+ run_timeout_mins: 300
+ }
+ {
+ name: chip_sw_otbn_ecdsa_op_irq_jitter_en
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=33_000_000", "+rng_srate_value=30", "+en_jitter=1"]
+ run_timeout_mins: 300
+ }
+ {
+ name: chip_sw_otbn_mem_scramble
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:otbn_mem_scramble_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=15_000_000", "+en_scb_tl_err_chk=0",
+ "+bypass_alert_ready_to_end_check=1"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_rnd
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["sw/device/tests:rv_core_ibex_rnd_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ // Timeout based on a 10min dvsim runtime.
+ run_opts: ["+sw_test_timeout_ns=10_000_000"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_nmi_irq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["sw/device/tests:rv_core_ibex_nmi_irq_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=10_000_000"]
+ }
+ {
+ name: chip_sw_aes_enc
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aes_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=22_000_000"]
+ }
+ {
+ name: chip_sw_aes_enc_jitter_en
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aes_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=26_000_000", "+en_jitter=1"]
+ }
+ {
+ name: chip_sw_aes_idle
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aes_idle_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=25_000_000"]
+ }
+ {
+ name: chip_sw_aes_masking_off
+ uvm_test_seq: chip_sw_aes_masking_off_vseq
+ sw_images: ["//sw/device/tests:aes_masking_off_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_alert_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:alert_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_alert_handler_escalation
+ uvm_test_seq: chip_sw_alert_handler_escalation_vseq
+ sw_images: ["//sw/device/tests/sim_dv:alert_handler_escalation_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ // Disable scoreboard to avoid incorrect alert prediction from the alert_monitor. Due to the
+ // cross-domain alert senders and receivers, the monitor from the chip level did not support
+ // processing alerts accurately from both ends.
+ run_opts: ["+en_scb=0", "+bypass_alert_ready_to_end_check=1"]
+ }
+ {
+ name: chip_sw_alert_handler_ping_timeout
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:alert_handler_ping_timeout_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ // Disable scoreboard to avoid incorrect alert prediction from the alert_monitor. Due to the
+ // cross-domain alert senders and receivers, the monitor from the chip level did not support
+ // processing alerts accurately from both ends.
+ run_opts: ["+en_scb=0", "+sw_test_timeout_ns=24000000"]
+ }
+ {
+ name: chip_sw_alert_handler_reverse_ping_in_deep_sleep
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ // Disable scoreboard to avoid incorrect alert prediction from the alert_monitor. Due to the
+ // cross-domain alert senders and receivers, the monitor from the chip level did not support
+ // processing alerts accurately from both ends.
+ // This test takes long due to the compile time configured reverse timeout. See test plan for
+ // more details.
+ run_opts: ["+en_scb=0", "+sw_test_timeout_ns=300_000_000"]
+ run_timeout_mins: 240
+ }
+ {
+ name: chip_sw_alert_handler_lpg_sleep_mode_alerts
+ uvm_test_seq: chip_sw_all_escalation_resets_vseq
+ sw_images: ["//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_scb=0", "+sw_test_timeout_ns=3000_000_000", "+bypass_alert_ready_to_end_check=1", "+avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl"]
+ run_timeout_mins: 240
+ reseed: 90
+ }
+ {
+ name: chip_sw_alert_handler_lpg_sleep_mode_pings
+ uvm_test_seq: chip_sw_alert_handler_shorten_ping_wait_cycle_vseq
+ sw_images: ["//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_scb=0", "+sw_test_timeout_ns=3000_000_000", "+bypass_alert_ready_to_end_check=1"]
+ run_timeout_mins: 240
+ }
+ {
+ name: chip_sw_alert_handler_lpg_clkoff
+ uvm_test_seq: chip_sw_alert_handler_lpg_clkoff_vseq
+ sw_images: ["//sw/device/tests:alert_handler_lpg_clkoff_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_scb=0", "+sw_test_timeout_ns=3000_000_000"]
+ run_timeout_mins: 240
+ }
+ {
+ name: chip_sw_alert_handler_lpg_reset_toggle
+ uvm_test_seq: chip_sw_alert_handler_shorten_ping_wait_cycle_vseq
+ sw_images: ["//sw/device/tests:alert_handler_lpg_reset_toggle_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_scb=0", "+sw_test_timeout_ns=3000_000_000"]
+ run_timeout_mins: 240
+ }
+ {
+ name: chip_sw_alert_handler_entropy
+ uvm_test_seq: chip_sw_alert_handler_entropy_vseq
+ sw_images: ["//sw/device/tests/sim_dv:alert_handler_entropy_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ // Disable scoreboard to avoid incorrect alert prediction from the alert_monitor. Due to the
+ // cross-domain alert senders and receivers, the monitor from the chip level did not support
+ // processing alerts accurately from both ends.
+ run_opts: ["+en_scb=0", "+bypass_alert_ready_to_end_check=1"]
+ }
+ {
+ name: chip_sw_aes_entropy
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aes_entropy_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=15_000_000"]
+ }
+ {
+ name: chip_sw_entropy_src_fuse_en_fw_read_test
+ uvm_test_seq: chip_sw_entropy_src_fuse_vseq
+ sw_images: ["//sw/device/tests/sim_dv:entropy_src_fuse_en_fw_read_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18000000"]
+ }
+ {
+ name: chip_sw_entropy_src_kat_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:entropy_src_kat_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000"]
+ }
+ {
+ name: chip_sw_csrng_lc_hw_debug_en_test
+ uvm_test_seq: chip_sw_csrng_lc_hw_debug_en_vseq
+ sw_images: ["//sw/device/tests/sim_dv:csrng_lc_hw_debug_en_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=15_000_000", "+rng_srate_value_min=15",
+ "+use_otp_image=OtpTypeLcStTestUnlocked0"]
+ run_timeout_mins: 60
+ }
+ {
+ name: chip_sw_csrng_edn_concurrency
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:csrng_edn_concurrency_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=20_000_000", "+rng_srate_value_min=15",
+ "+rng_srate_value_max=20"]
+ run_timeout_mins: 240
+ }
+ {
+ name: chip_sw_csrng_kat_test
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:csrng_kat_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000"]
+ }
+ {
+ name: chip_sw_csrng_fuse_en_sw_app_read_test
+ uvm_test_seq: chip_sw_entropy_src_fuse_vseq
+ sw_images: ["//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=15_000_000"]
+ }
+ {
+ name: chip_sw_entropy_src_ast_rng_req
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:entropy_src_ast_rng_req_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=15_000_000"]
+ }
+ {
+ name: chip_sw_entropy_src_csrng
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:entropy_src_csrng_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000", "+rng_srate_value_min=15",
+ "+rng_srate_value_max=30"]
+ run_timeout_mins: 120
+ }
+ {
+ name: chip_sw_edn_entropy_reqs
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:entropy_src_edn_reqs_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=15000000", "+rng_srate_value_min=15",
+ "+rng_srate_value_max=30"]
+ }
+ {
+ name: chip_sw_edn_entropy_reqs_jitter
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:entropy_src_edn_reqs_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=15000000", "+rng_srate_value_min=15",
+ "+rng_srate_value_max=30", "+en_jitter=1"]
+ }
+ {
+ name: chip_sw_hmac_enc
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:hmac_enc_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_hmac_enc_jitter_en
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:hmac_enc_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_jitter=1"]
+ }
+ {
+ name: chip_sw_hmac_enc_idle
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:hmac_enc_idle_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_keymgr_key_derivation
+ uvm_test_seq: chip_sw_keymgr_key_derivation_vseq
+ sw_images: ["//sw/device/tests:keymgr_key_derivation_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=20_000_000"]
+ }
+ {
+ name: chip_sw_keymgr_key_derivation_prod
+ uvm_test_seq: chip_sw_keymgr_key_derivation_vseq
+ sw_images: ["//sw/device/tests:keymgr_key_derivation_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+lc_at_prod=1", "+sw_test_timeout_ns=20_000_000"]
+ }
+ {
+ name: chip_sw_keymgr_key_derivation_jitter_en
+ uvm_test_seq: chip_sw_keymgr_key_derivation_vseq
+ sw_images: ["//sw/device/tests:keymgr_key_derivation_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=20_000_000", "+en_jitter=1"]
+ }
+ {
+ name: chip_sw_keymgr_sideload_kmac
+ uvm_test_seq: chip_sw_keymgr_sideload_kmac_vseq
+ sw_images: ["//sw/device/tests:keymgr_sideload_kmac_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=20_000_000"]
+ }
+ {
+ name: chip_sw_keymgr_sideload_aes
+ uvm_test_seq: chip_sw_keymgr_sideload_aes_vseq
+ sw_images: ["//sw/device/tests:keymgr_sideload_aes_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=20_000_000"]
+ }
+ {
+ name: chip_sw_keymgr_sideload_otbn
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:keymgr_sideload_otbn_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=20_000_000"]
+ run_timeout_mins: 180
+ }
+ {
+ name: chip_sw_kmac_mode_cshake
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:kmac_mode_cshake_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_kmac_mode_kmac
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:kmac_mode_kmac_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_kmac_mode_kmac_jitter_en
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:kmac_mode_kmac_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_jitter=1"]
+ }
+ {
+ name: chip_sw_kmac_app_rom
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:kmac_app_rom_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_kmac_idle
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:kmac_idle_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_rom_ctrl_integrity_check
+ uvm_test_seq: chip_sw_rom_ctrl_integrity_check_vseq
+ sw_images: ["//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_sram_ctrl_scrambled_access
+ uvm_test_seq: chip_sw_sram_ctrl_scrambled_access_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=12_000_000", "+en_scb_tl_err_chk=0"]
+ }
+ {
+ name: chip_sw_sram_ctrl_scrambled_access_jitter_en
+ uvm_test_seq: chip_sw_sram_ctrl_scrambled_access_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=12_000_000",
+ "+en_jitter=1", "+en_scb_tl_err_chk=0"]
+ }
+ {
+ name: chip_sw_sram_ctrl_execution_main
+ uvm_test_seq: chip_sw_sram_ctrl_execution_main_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_execution_main_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_sleep_sram_ret_contents
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:sram_ctrl_sleep_sram_ret_contents_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=20_000_000", "+en_scb_tl_err_chk=0"]
+ }
+ {
+ name: chip_sw_sensor_ctrl_alert
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:sensor_ctrl_alert_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=40_000_000"]
+ reseed: 5
+ }
+ {
+ name: chip_sw_sensor_ctrl_status
+ uvm_test_seq: chip_sw_sensor_ctrl_status_intr_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sensor_ctrl_status_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=40_000_000"]
+ }
+ {
+ name: chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:sensor_ctrl_wakeup_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=8_000_000"]
+ }
+ {
+ name: chip_sw_coremark
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//third_party/coremark/top_sencha:coremark_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_uart_logger=1",
+ "+sw_test_timeout_ns=100_000_000"]
+ reseed: 1
+ run_timeout_mins: 180
+ }
+ {
+ name: chip_sw_pwrmgr_b2b_sleep_reset_req
+ uvm_test_seq: chip_sw_repeat_reset_wkup_vseq
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_b2b_sleep_reset_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=35_000_000"]
+ run_timeout_mins: 120
+ }
+ // The test below is from tl_access_tests.hjson, but we don't need to include tl_intg_err,
+ // which is also in tl_access_tests.hjson, as TLUL integrity is generated by design and we
+ // include this block in the data path when we stub CPU to verify TL access
+ // So copy chip_tl_errors here and append the stub_cpu_mode run mode.
+ {
+ name: chip_tl_errors
+ build_mode: "cover_reg_top"
+ uvm_test_seq: "{name}_common_vseq"
+ run_opts: ["+run_tl_errors"]
+ en_run_modes: ["stub_cpu_mode"]
+ reseed: 30
+ }
+ {
+ name: chip_prim_tl_access
+ build_mode: "cover_reg_top"
+ uvm_test_seq: "chip_prim_tl_access_vseq"
+ en_run_modes: ["stub_cpu_mode"]
+ run_opts: ["+en_scb=0", "+en_scb_tl_err_chk=0"]
+ }
+ {
+ name: chip_plic_all_irqs
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:plic_all_irqs_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_plic_sw_irq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:plic_sw_irq_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_clkmgr_off_peri
+ uvm_test_seq: chip_sw_clkmgr_off_peri_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_peri_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=30_000_000"]
+ }
+ {
+ name: chip_sw_clkmgr_off_aes_trans
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_aes_trans_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_clkmgr_off_hmac_trans
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_hmac_trans_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_clkmgr_off_kmac_trans
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_kmac_trans_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_clkmgr_off_otbn_trans
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_otbn_trans_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_clkmgr_off_smc_trans
+ uvm_test_seq: chip_sw_clkmgr_off_gateable_clk_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_smc_clk_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+clk_idx=7"]
+ }
+ {
+ name: chip_sw_clkmgr_off_ml_trans
+ uvm_test_seq: chip_sw_clkmgr_off_gateable_clk_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_ml_clk_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+clk_idx=5"]
+ }
+ {
+ name: chip_sw_clkmgr_off_video_trans
+ uvm_test_seq: chip_sw_clkmgr_off_gateable_clk_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_video_clk_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+clk_idx=4"]
+ }
+ {
+ name: chip_sw_clkmgr_off_audio_trans
+ uvm_test_seq: chip_sw_clkmgr_off_gateable_clk_vseq
+ sw_images: ["//sw/device/tests:clkmgr_off_audio_clk_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+clk_idx=6"]
+ }
+ {
+ name: chip_sw_clkmgr_external_clk_src_for_lc
+ uvm_test_seq: chip_sw_lc_ctrl_transition_vseq
+ sw_images: ["//sw/device/tests/sim_dv:clkmgr_external_clk_src_for_lc_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+chip_clock_source=ChipClockSourceExternal48Mhz", "+calibrate_usb_clk=1"]
+ }
+ {
+ name: chip_sw_clkmgr_external_clk_src_for_sw_fast
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:clkmgr_external_clk_src_for_sw_fast_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+chip_clock_source=ChipClockSourceExternal96Mhz", "+calibrate_usb_clk=1"]
+ }
+ {
+ name: chip_sw_clkmgr_external_clk_src_for_sw_slow
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:clkmgr_external_clk_src_for_sw_slow_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+chip_clock_source=ChipClockSourceExternal48Mhz", "+calibrate_usb_clk=1"]
+ }
+ {
+ name: chip_sw_clkmgr_reset_frequency
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["sw/device/tests:clkmgr_reset_frequency_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+calibrate_usb_clk=1"]
+ }
+ {
+ name: chip_sw_clkmgr_jitter
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:clkmgr_jitter_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_clkmgr_sleep_frequency
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["sw/device/tests:clkmgr_sleep_frequency_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+calibrate_usb_clk=1"]
+ }
+ {
+ name: chip_jtag_csr_rw
+ build_mode: "cover_reg_top_no_dma"
+ uvm_test_seq: "chip_jtag_csr_rw_vseq"
+ en_run_modes: ["stub_cpu_mode"]
+ run_opts: ["+en_scb=0", "+csr_rw", "+create_jtag_riscv_map=1"]
+ }
+ {
+ name: chip_jtag_mem_access
+ uvm_test_seq: "chip_jtag_mem_vseq"
+ en_run_modes: ["stub_cpu_mode"]
+ run_opts: ["+create_jtag_riscv_map=1"]
+ }
+ {
+ name: chip_sw_ast_clk_outputs
+ uvm_test_seq: chip_sw_ast_clk_outputs_vseq
+ sw_images: ["//sw/device/tests:ast_clk_outs_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+calibrate_usb_clk=1"]
+ }
+ {
+ name: chip_sw_lc_ctrl_program_error
+ uvm_test_seq: chip_sw_lc_ctrl_program_error_vseq
+ sw_images: ["sw/device/tests/sim_dv:lc_ctrl_program_error:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_scb=0", "+bypass_alert_ready_to_end_check=1"]
+ }
+ {
+ name: chip_sw_pwrmgr_normal_sleep_all_wake_ups
+ uvm_test_seq: "chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq"
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_normal_sleep_all_wake_ups:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_pwrmgr_deep_sleep_all_wake_ups
+ uvm_test_seq: "chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq"
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_deep_sleep_all_wake_ups:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000"]
+ }
+ {
+ name: chip_sw_pwrmgr_random_sleep_all_wake_ups
+ uvm_test_seq: "chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq"
+ sw_images: ["//sw/device/tests/sim_dv:pwrmgr_random_sleep_all_wake_ups:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=18_000_000", "+do_random=1"]
+ }
+ {
+ name: chip_rv_dm_ndm_reset_req
+ uvm_test_seq: "chip_rv_dm_ndm_reset_vseq"
+ sw_images: ["//sw/device/tests/sim_dv:rv_dm_ndm_reset_req:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_scb_tl_err_chk=0", "+use_jtag_dmi=1"]
+ }
+ {
+ name: chip_sw_rv_dm_ndm_reset_req_when_cpu_halted
+ uvm_test_seq: "chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq"
+ sw_images: ["//sw/device/tests/sim_dv:rv_dm_ndm_reset_req_when_cpu_halted:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+use_jtag_dmi=1"]
+ }
+ {
+ name: chip_sw_rv_dm_access_after_wakeup
+ uvm_test_seq: chip_sw_rv_dm_access_after_wakeup_vseq
+ sw_images: ["//sw/device/tests/sim_dv:rv_dm_access_after_wakeup:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+use_jtag_dmi=1"]
+ }
+ {
+ name: chip_sw_rv_dm_access_after_escalation_reset
+ uvm_test_seq: "chip_sw_rv_dm_access_after_escalation_reset_vseq"
+ sw_images: ["//sw/device/tests/sim_dv:alert_handler_escalation_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+use_jtag_dmi=1"]
+ }
+ {
+ name: chip_tap_straps_dev
+ uvm_test_seq: chip_tap_straps_vseq
+ en_run_modes: ["strap_tests_mode"]
+ run_opts: ["+use_otp_image=OtpTypeLcStDev"]
+ run_timeout_mins: 120
+ }
+ {
+ name: chip_tap_straps_rma
+ uvm_test_seq: chip_tap_straps_vseq
+ en_run_modes: ["strap_tests_mode"]
+ run_timeout_mins: 120
+ }
+ {
+ name: chip_tap_straps_prod
+ uvm_test_seq: chip_tap_straps_vseq
+ en_run_modes: ["strap_tests_mode"]
+ run_opts: ["+use_otp_image=OtpTypeLcStProd"]
+ run_timeout_mins: 120
+ }
+ {
+ name: chip_rv_dm_lc_disabled
+ build_mode: "cover_reg_top"
+ uvm_test_seq: "chip_rv_dm_lc_disabled_vseq"
+ en_run_modes: ["stub_cpu_mode"]
+ run_opts: ["+en_scb=0", "+en_scb_tl_err_chk=0", "+use_jtag_dmi=1"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_address_translation
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["sw/device/tests:rv_core_ibex_address_translation_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ // Timeout based on a ~7 minute dvsim runtime.
+ run_opts: ["+sw_test_timeout_ns=7_000_000"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_lockstep_glitch
+ uvm_test_seq: chip_sw_rv_core_ibex_lockstep_glitch_vseq
+ sw_images: ["sw/device/tests:aes_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ // This test currently stops without completing all transactions, so we
+ // have to disable the final assertions.
+ run_opts: ["+disable_assert_final_checks"]
+ }
+ {
+ name: chip_sw_rv_core_ibex_icache_invalidate
+ uvm_test_seq: chip_sw_rv_core_ibex_icache_invalidate_vseq
+ sw_images: ["//sw/device/tests:rv_core_ibex_icache_invalidate_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_usb_ast_clk_calib
+ uvm_test_seq: "chip_sw_usb_ast_clk_calib_vseq"
+ sw_images: ["//sw/device/tests/sim_dv:ast_usb_clk_calib:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+usb_max_drift=1", "+usb_fast_sof=1"]
+ reseed: 1
+ }
+ {
+ name: chip_sw_flash_crash_alert
+ uvm_test_seq: chip_sw_flash_host_gnt_err_inj_vseq
+ sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+test_timeout_ns=8_000_000", "+bypass_alert_ready_to_end_check=1"]
+ }
+ {
+ name: chip_padctrl_attributes
+ uvm_test_seq: chip_padctrl_attributes_vseq
+ en_run_modes: ["stub_cpu_mode"]
+ // Starting the chip in prod LC state frees up all MIOs for this test.
+ run_opts: ["+use_otp_image=OtpTypeLcStProd"]
+ reseed: 10
+ }
+ {
+ name: chip_sw_clkmgr_jitter_reduced_freq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:clkmgr_jitter_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+cal_sys_clk_70mhz=1"]
+ }
+ {
+ name: chip_sw_flash_ctrl_ops_jitter_en_reduced_freq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:flash_ctrl_ops_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=14_000_000", "+en_jitter=1", "+cal_sys_clk_70mhz=1"]
+ }
+ {
+ name: chip_sw_flash_ctrl_access_jitter_en_reduced_freq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:flash_ctrl_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_jitter=1", "+cal_sys_clk_70mhz=1"]
+ }
+ {
+ name: chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=33_000_000", "+rng_srate_value=30", "+en_jitter=1", "+cal_sys_clk_70mhz=1"]
+ run_timeout_mins: 1000
+ }
+ {
+ name: chip_sw_aes_enc_jitter_en_reduced_freq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aes_smoketest:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=26_000_000", "+en_jitter=1", "+cal_sys_clk_70mhz=1"]
+ }
+ {
+ name: chip_sw_hmac_enc_jitter_en_reduced_freq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:hmac_enc_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_jitter=1", "+cal_sys_clk_70mhz=1"]
+ }
+ {
+ name: chip_sw_keymgr_key_derivation_jitter_en_reduced_freq
+ uvm_test_seq: chip_sw_keymgr_key_derivation_vseq
+ sw_images: ["//sw/device/tests:keymgr_key_derivation_test:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=20_000_000", "+en_jitter=1", "+cal_sys_clk_70mhz=1"]
+ }
+ {
+ name: chip_sw_kmac_mode_kmac_jitter_en_reduced_freq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:kmac_mode_kmac_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+en_jitter=1", "+cal_sys_clk_70mhz=1"]
+ }
+ {
+ name: chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq
+ uvm_test_seq: chip_sw_sram_ctrl_scrambled_access_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+mem_sel=main",
+ "+sw_test_timeout_ns=12_000_000",
+ "+en_jitter=1", "+en_scb_tl_err_chk=0", "+cal_sys_clk_70mhz=1"]
+ }
+ {
+ name: chip_sw_flash_init_reduced_freq
+ uvm_test_seq: chip_sw_flash_init_vseq
+ sw_images: ["//sw/device/tests/sim_dv:flash_init_test:0:test_in_rom"]
+ en_run_modes: ["sw_test_mode_common"]
+ run_opts: ["+sw_test_timeout_ns=25_000_000", "+cal_sys_clk_70mhz=1"]
+ }
+ {
+ name: chip_sw_csrng_edn_concurrency_reduced_freq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:csrng_edn_concurrency_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=30_000_000", "+rng_srate_value_min=15",
+ "+rng_srate_value_max=20", "+cal_sys_clk_70mhz=1", "+en_jitter=1"]
+ run_timeout_mins: 240
+ }
+ {
+ name: chip_sw_power_idle_load
+ uvm_test_seq: chip_sw_power_idle_load_vseq
+ sw_images: ["//sw/device/tests:chip_power_idle_load:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_power_sleep_load
+ uvm_test_seq: chip_sw_power_sleep_load_vseq
+ sw_images: ["//sw/device/tests:chip_power_sleep_load:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_ast_clk_rst_inputs
+ uvm_test_seq: chip_sw_ast_clk_rst_inputs_vseq
+ sw_images: ["//sw/device/tests/sim_dv:ast_clk_rst_inputs:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=200_000_000"]
+ }
+ {
+ name: chip_sw_power_virus
+ uvm_test_seq: chip_sw_power_virus_vseq
+ sw_images: [
+ "//sw/device/tests:power_virus_systemtest:1",
+ "//sw/device/tests:power_virus_systemtest_otp_img_rma:4",
+ ]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: [
+ "+sw_test_timeout_ns=200_000_000",
+ "+use_otp_image=OtpTypeCustom",
+ ]
+ run_timeout_mins: 300
+ }
+ ]
+
+ // List of regressions.
+ // Sample command to run regression suites
+ // util/dvsim_matcha/dvsim.py hw/top_sencha/dv/chip_sim_cfg.hjson \
+ // -i edaclound_nightly
+ regressions: [
+ {
+ name: edacloud
+ tests: [
+ "chip_sw_aes_enc",
+ "chip_sw_alert_test",
+ "chip_sw_aon_timer_smoketest",
+ "chip_sw_atomics_test",
+ "chip_sw_cam_ctrl_test",
+ "chip_sw_clkmgr_smoketest",
+ "chip_sw_crt_test",
+ "chip_sw_csrng_smoketest",
+ "chip_sw_dma_main_test",
+ "chip_sw_example_flash",
+ "chip_sw_example_rom",
+ "chip_sw_gpio",
+ "chip_sw_hmac_enc",
+ "chip_sw_i2c_device_tx_rx",
+ "chip_sw_i2c_host_tx_rx",
+ "chip_sw_keymgr_key_derivation",
+ "chip_sw_mem_test",
+ "chip_sw_rom_ctrl_integrity_check",
+ "chip_sw_rstmgr_smoketest",
+ "chip_sw_rstmgr_sw_req",
+ "chip_sw_rstmgr_sw_rst",
+ "chip_sw_rv_core_ibex_rnd",
+ "chip_sw_rv_plic_smoketest",
+ "chip_sw_rv_timer_irq",
+ "chip_sw_sensor_ctrl_status",
+ "chip_sw_smc_cam_irq_test",
+ "chip_sw_smc_ctrl_test",
+ "chip_sw_smc_env_test",
+ "chip_sw_smc_i2s_rx_test",
+ "chip_sw_smc_i2s_tx_test",
+ "chip_sw_smc_interrupt_boundary_test",
+ "chip_sw_smc_isp_wrapper_irq_test",
+ "chip_sw_smc_isp_wrapper_test",
+ "chip_sw_smc_isp_wrapper_tpg_128_64_test",
+ "chip_sw_smc_lsu_interrupt_boundary_test",
+ "chip_sw_smc_lsu_page_boundary_test",
+ "chip_sw_smc_ml_sram_smoketest",
+ "chip_sw_smc_ml_top_irq_test",
+ "chip_sw_smc_page_boundary_test",
+ "chip_sw_smc_rv_timer_test",
+ "chip_sw_smc_supervisor_mode_test",
+ "chip_sw_smc_tlul_mailbox_test",
+ "chip_sw_smc_virtual_memory_test",
+ "chip_sw_spi_device_tx_rx",
+ "chip_sw_spi_host_tx_rx",
+ "chip_sw_sram_ctrl_smoketest",
+ "chip_sw_sysrst_ctrl_inputs",
+ "chip_sw_uart_smoketest",
+ "chip_sw_uart_tx_rx",
+ "chip_tap_straps_rma",
+ ]
+ }
+ {
+ // TODO(b/287644985): Track the dv tests to be implemented.
+ name: edacloud_nightly
+ tests: [
+ "chip_jtag_mem_access",
+ "chip_padctrl_attributes",
+ "chip_plic_all_irqs",
+ "chip_rv_dm_lc_disabled",
+ "chip_rv_dm_ndm_reset_req",
+ "chip_sw_aes_enc",
+ "chip_sw_aes_enc_jitter_en",
+ "chip_sw_aes_idle",
+ "chip_sw_aes_masking_off",
+ "chip_sw_aes_smoketest",
+ "chip_sw_alert_handler_escalation",
+ "chip_sw_alert_handler_ping_timeout",
+ "chip_sw_alert_test",
+ "chip_sw_aon_timer_irq",
+ "chip_sw_aon_timer_sleep_wdog_sleep_pause",
+ "chip_sw_aon_timer_smoketest",
+ "chip_sw_aon_timer_wdog_bite_reset",
+ "chip_sw_ast_clk_outputs",
+ "chip_sw_ast_clk_rst_inputs",
+ "chip_sw_atomics_test",
+ "chip_sw_cam_ctrl_test",
+ "chip_sw_clkmgr_external_clk_src_for_lc",
+ "chip_sw_clkmgr_external_clk_src_for_sw_fast",
+ "chip_sw_clkmgr_external_clk_src_for_sw_slow",
+ "chip_sw_clkmgr_off_audio_trans",
+ "chip_sw_clkmgr_off_ml_trans",
+ "chip_sw_clkmgr_off_peri",
+ "chip_sw_clkmgr_off_smc_trans",
+ "chip_sw_clkmgr_off_video_trans",
+ "chip_sw_clkmgr_reset_frequency",
+ "chip_sw_clkmgr_sleep_frequency",
+ "chip_sw_clkmgr_smoketest",
+ "chip_sw_crt_test",
+ "chip_sw_csrng_smoketest",
+ "chip_sw_dma_main_test",
+ "chip_sw_entropy_src_smoketest",
+ "chip_sw_example_flash",
+ "chip_sw_example_rom",
+ "chip_sw_exit_test_unlocked_bootstrap",
+ "chip_sw_flash_ctrl_access",
+ "chip_sw_flash_ctrl_access_jitter_en",
+ "chip_sw_flash_ctrl_access_jitter_en_reduced_freq",
+ "chip_sw_flash_ctrl_ops",
+ "chip_sw_gpio",
+ "chip_sw_hmac_enc",
+ "chip_sw_hmac_enc_idle",
+ "chip_sw_hmac_enc_jitter_en",
+ "chip_sw_hmac_smoketest",
+ "chip_sw_i2c_device_tx_rx",
+ "chip_sw_i2c_host_tx_rx",
+ "chip_sw_mem_test",
+ "chip_sw_keymgr_key_derivation",
+ "chip_sw_keymgr_key_derivation_jitter_en",
+ "chip_sw_keymgr_key_derivation_prod",
+ "chip_sw_kmac_idle",
+ "chip_sw_kmac_smoketest",
+ "chip_sw_lc_ctrl_otp_hw_cfg",
+ "chip_sw_lc_ctrl_program_error",
+ "chip_sw_lc_walkthrough_dev",
+ "chip_sw_lc_walkthrough_prod",
+ "chip_sw_lc_walkthrough_prodend",
+ "chip_sw_lc_walkthrough_rma",
+ "chip_sw_lc_walkthrough_testunlocks",
+ "chip_sw_otbn_smoketest",
+ "chip_sw_otp_ctrl_escalation",
+ "chip_sw_otp_ctrl_smoketest",
+ "chip_sw_pwrmgr_deep_sleep_power_glitch_reset",
+ "chip_sw_pwrmgr_full_aon_reset",
+ "chip_sw_pwrmgr_main_power_glitch_reset",
+ "chip_sw_pwrmgr_normal_sleep_all_wake_ups"
+ "chip_sw_pwrmgr_sleep_disabled",
+ "chip_sw_pwrmgr_sleep_power_glitch_reset",
+ "chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup",
+ "chip_sw_pwrmgr_wdog_reset",
+ "chip_sw_rom_ctrl_integrity_check",
+ "chip_sw_rstmgr_cpu_info",
+ "chip_sw_rstmgr_rst_cnsty_escalation",
+ "chip_sw_rstmgr_smoketest",
+ "chip_sw_rstmgr_sw_req",
+ "chip_sw_rstmgr_sw_rst",
+ "chip_sw_rv_core_ibex_address_translation",
+ "chip_sw_rv_core_ibex_icache_invalidate",
+ "chip_sw_rv_core_ibex_lockstep_glitch",
+ "chip_sw_rv_core_ibex_nmi_irq",
+ "chip_sw_rv_core_ibex_rnd",
+ "chip_sw_rv_dm_access_after_escalation_reset",
+ "chip_sw_rv_dm_access_after_wakeup",
+ "chip_sw_rv_dm_ndm_reset_req_when_cpu_halted",
+ "chip_sw_rv_plic_smoketest",
+ "chip_sw_rv_timer_irq",
+ "chip_sw_sensor_ctrl_alert",
+ "chip_sw_sensor_ctrl_status",
+ "chip_sw_sleep_pin_mio_dio_val",
+ "chip_sw_sleep_pin_retention",
+ "chip_sw_sleep_pin_wake",
+ "chip_sw_sleep_pwm_pulses",
+ "chip_sw_smc_cam_irq_test",
+ "chip_sw_smc_ctrl_test",
+ "chip_sw_smc_env_test",
+ "chip_sw_smc_i2s_rx_test",
+ "chip_sw_smc_i2s_tx_test",
+ "chip_sw_smc_interrupt_boundary_test",
+ "chip_sw_smc_isp_wrapper_irq_test",
+ "chip_sw_smc_isp_wrapper_test",
+ "chip_sw_smc_isp_wrapper_tpg_128_64_test",
+ "chip_sw_smc_kelvin_checksum_test",
+ "chip_sw_smc_kelvin_hello_test",
+ "chip_sw_smc_kelvin_model_test",
+ "chip_sw_smc_lsu_interrupt_boundary_test",
+ "chip_sw_smc_lsu_page_boundary_test",
+ "chip_sw_smc_ml_sram_smoketest",
+ "chip_sw_smc_ml_top_irq_test",
+ "chip_sw_smc_page_boundary_test",
+ "chip_sw_smc_rv_timer_test",
+ "chip_sw_smc_supervisor_mode_test",
+ "chip_sw_smc_tlul_mailbox_test",
+ "chip_sw_smc_virtual_memory_test",
+ "chip_sw_spi_device_pass_through",
+ "chip_sw_spi_device_tx_rx",
+ "chip_sw_spi_host_tx_rx",
+ "chip_sw_sram_ctrl_execution_main",
+ "chip_sw_sram_ctrl_scrambled_access",
+ "chip_sw_sram_ctrl_smoketest",
+ "chip_sw_sysrst_ctrl_in_irq",
+ "chip_sw_sysrst_ctrl_inputs",
+ "chip_sw_sysrst_ctrl_outputs",
+ "chip_sw_sysrst_ctrl_reset",
+ "chip_sw_sysrst_ctrl_ulp_z3_wakeup",
+ "chip_sw_uart_smoketest",
+ "chip_sw_uart_tx_rx",
+ "chip_sw_uart_tx_rx_lc_test",
+ "chip_tap_straps_dev",
+ "chip_tap_straps_rma",
+ ]
+ }
+ {
+ name: edacloud_all
+ tests: [
+ "chip_jtag_mem_access",
+ "chip_padctrl_attributes",
+ "chip_plic_all_irqs",
+ "chip_rv_dm_lc_disabled",
+ "chip_rv_dm_ndm_reset_req",
+ "chip_sw_aes_enc",
+ "chip_sw_aes_enc_jitter_en",
+ "chip_sw_aes_idle",
+ "chip_sw_aes_masking_off",
+ "chip_sw_aes_smoketest",
+ "chip_sw_alert_handler_escalation",
+ "chip_sw_alert_handler_ping_timeout",
+ "chip_sw_alert_test",
+ "chip_sw_aon_timer_irq",
+ "chip_sw_aon_timer_sleep_wdog_sleep_pause",
+ "chip_sw_aon_timer_smoketest",
+ "chip_sw_aon_timer_wdog_bite_reset",
+ "chip_sw_ast_clk_outputs",
+ "chip_sw_ast_clk_rst_inputs",
+ "chip_sw_atomics_test",
+ "chip_sw_cam_ctrl_test",
+ "chip_sw_clkmgr_external_clk_src_for_lc",
+ "chip_sw_clkmgr_external_clk_src_for_sw_fast",
+ "chip_sw_clkmgr_external_clk_src_for_sw_slow",
+ "chip_sw_clkmgr_off_audio_trans",
+ "chip_sw_clkmgr_off_ml_trans",
+ "chip_sw_clkmgr_off_peri",
+ "chip_sw_clkmgr_off_smc_trans",
+ "chip_sw_clkmgr_off_video_trans",
+ "chip_sw_clkmgr_reset_frequency",
+ "chip_sw_clkmgr_sleep_frequency",
+ "chip_sw_clkmgr_smoketest",
+ "chip_sw_crt_test",
+ "chip_sw_csrng_smoketest",
+ "chip_sw_data_integrity_escalation",
+ "chip_sw_dma_main_test",
+ "chip_sw_entropy_src_smoketest",
+ "chip_sw_example_flash",
+ "chip_sw_example_rom",
+ "chip_sw_exit_test_unlocked_bootstrap",
+ "chip_sw_flash_ctrl_access",
+ "chip_sw_flash_ctrl_access_jitter_en",
+ "chip_sw_flash_ctrl_access_jitter_en_reduced_freq",
+ "chip_sw_flash_ctrl_ops",
+ "chip_sw_gpio",
+ "chip_sw_hmac_enc",
+ "chip_sw_hmac_enc_idle",
+ "chip_sw_hmac_enc_jitter_en",
+ "chip_sw_hmac_smoketest",
+ "chip_sw_i2c_device_tx_rx",
+ "chip_sw_i2c_host_tx_rx",
+ "chip_sw_keymgr_key_derivation",
+ "chip_sw_keymgr_key_derivation_jitter_en",
+ "chip_sw_keymgr_key_derivation_jitter_en_reduced_freq",
+ "chip_sw_keymgr_key_derivation_prod",
+ "chip_sw_kmac_idle",
+ "chip_sw_kmac_smoketest",
+ "chip_sw_lc_ctrl_otp_hw_cfg",
+ "chip_sw_lc_ctrl_program_error",
+ "chip_sw_lc_walkthrough_dev",
+ "chip_sw_lc_walkthrough_prod",
+ "chip_sw_lc_walkthrough_prodend",
+ "chip_sw_lc_walkthrough_rma",
+ "chip_sw_lc_walkthrough_testunlocks",
+ "chip_sw_mem_test",
+ "chip_sw_otbn_smoketest",
+ "chip_sw_otp_ctrl_escalation",
+ "chip_sw_otp_ctrl_smoketest",
+ "chip_sw_pwrmgr_b2b_sleep_reset_req",
+ "chip_sw_pwrmgr_deep_sleep_all_reset_reqs",
+ "chip_sw_pwrmgr_deep_sleep_all_wake_ups"
+ "chip_sw_pwrmgr_deep_sleep_power_glitch_reset",
+ "chip_sw_pwrmgr_full_aon_reset",
+ "chip_sw_pwrmgr_main_power_glitch_reset",
+ "chip_sw_pwrmgr_normal_sleep_all_reset_reqs",
+ "chip_sw_pwrmgr_normal_sleep_all_wake_ups",
+ "chip_sw_pwrmgr_random_sleep_all_reset_reqs",
+ "chip_sw_pwrmgr_random_sleep_all_wake_ups",
+ "chip_sw_pwrmgr_random_sleep_power_glitch_reset",
+ "chip_sw_pwrmgr_sleep_disabled",
+ "chip_sw_pwrmgr_sleep_power_glitch_reset",
+ "chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup",
+ "chip_sw_pwrmgr_sysrst_ctrl_reset",
+ "chip_sw_pwrmgr_wdog_reset",
+ "chip_sw_rom_ctrl_integrity_check",
+ "chip_sw_rstmgr_alert_info",
+ "chip_sw_rstmgr_cpu_info",
+ "chip_sw_rstmgr_rst_cnsty_escalation",
+ "chip_sw_rstmgr_smoketest",
+ "chip_sw_rstmgr_sw_req",
+ "chip_sw_rstmgr_sw_rst",
+ "chip_sw_rv_core_ibex_address_translation",
+ "chip_sw_rv_core_ibex_icache_invalidate",
+ "chip_sw_rv_core_ibex_lockstep_glitch",
+ "chip_sw_rv_core_ibex_nmi_irq",
+ "chip_sw_rv_core_ibex_rnd",
+ "chip_sw_rv_dm_access_after_escalation_reset",
+ "chip_sw_rv_dm_access_after_wakeup",
+ "chip_sw_rv_dm_ndm_reset_req_when_cpu_halted",
+ "chip_sw_rv_plic_smoketest",
+ "chip_sw_rv_timer_irq",
+ "chip_sw_sensor_ctrl_alert",
+ "chip_sw_sensor_ctrl_status",
+ "chip_sw_sleep_pin_mio_dio_val",
+ "chip_sw_sleep_pin_retention",
+ "chip_sw_sleep_pin_wake",
+ "chip_sw_sleep_pwm_pulses",
+ "chip_sw_sleep_sram_ret_contents",
+ "chip_sw_smc_cam_irq_test",
+ "chip_sw_smc_ctrl_test",
+ "chip_sw_smc_env_test",
+ "chip_sw_smc_i2s_rx_test",
+ "chip_sw_smc_i2s_tx_test",
+ "chip_sw_smc_interrupt_boundary_test",
+ "chip_sw_smc_isp_wrapper_irq_test",
+ "chip_sw_smc_isp_wrapper_test",
+ "chip_sw_smc_isp_wrapper_tpg_128_64_test",
+ "chip_sw_smc_kelvin_checksum_test",
+ "chip_sw_smc_kelvin_hello_test",
+ "chip_sw_smc_kelvin_model_test",
+ "chip_sw_smc_lsu_interrupt_boundary_test",
+ "chip_sw_smc_lsu_page_boundary_test",
+ "chip_sw_smc_ml_sram_smoketest",
+ "chip_sw_smc_ml_top_irq_test",
+ "chip_sw_smc_page_boundary_test",
+ "chip_sw_smc_rv_timer_test",
+ "chip_sw_smc_supervisor_mode_test",
+ "chip_sw_smc_tlul_mailbox_test",
+ "chip_sw_smc_virtual_memory_test",
+ "chip_sw_spi_device_pass_through",
+ "chip_sw_spi_device_pass_through_collision",
+ "chip_sw_spi_device_tx_rx",
+ "chip_sw_spi_host_tx_rx",
+ "chip_sw_sram_ctrl_execution_main",
+ "chip_sw_sram_ctrl_scrambled_access",
+ "chip_sw_sram_ctrl_scrambled_access_jitter_en",
+ "chip_sw_sram_ctrl_smoketest",
+ "chip_sw_uart_smoketest",
+ "chip_sw_sysrst_ctrl_in_irq",
+ "chip_sw_sysrst_ctrl_inputs",
+ "chip_sw_sysrst_ctrl_outputs",
+ "chip_sw_sysrst_ctrl_reset",
+ "chip_sw_sysrst_ctrl_ulp_z3_wakeup",
+ "chip_sw_uart_tx_rx",
+ "chip_sw_uart_tx_rx_lc_test",
+ "chip_tap_straps_dev",
+ "chip_tap_straps_prod",
+ "chip_tap_straps_rma",
+ ]
+ }
+ {
+ name: scrap
+ tests: ["chip_sw_lc_ctrl_raw_to_scrap",
+ "chip_sw_lc_ctrl_rma_to_scrap",
+ "chip_sw_lc_ctrl_test_locked0_to_scrap",
+ "chip_sw_lc_ctrl_rand_to_scrap"
+ ]
+ }
+ {
+ name: smoke
+ tests: ["chip_sw_uart_tx_rx",
+ "chip_sw_spi_host_tx_rx",
+ "chip_sw_spi_device_pass_through",
+ "chip_sw_i2c_host_tx_rx",
+ "chip_sw_i2c_device_tx_rx",
+ "chip_plic_all_irqs",
+ "chip_sw_example_flash",
+ "chip_sw_example_rom",
+ "chip_sw_example_manufacturer",
+ "chip_sw_example_concurrency"]
+ // TODO: add this test after enabling HW verification: "rom_e2e_smoke"]
+ }
+ {
+ name: jitter
+ tests: ["chip_sw_clkmgr_jitter",
+ "chip_sw_flash_ctrl_ops_jitter_en",
+ "chip_sw_flash_ctrl_access_jitter_en",
+ "chip_sw_otbn_ecdsa_op_irq_jitter_en",
+ "chip_sw_aes_enc_jitter_en",
+ "chip_sw_hmac_enc_jitter_en",
+ "chip_sw_keymgr_key_derivation_jitter_en",
+ "chip_sw_kmac_mode_kmac_jitter_en",
+ "chip_sw_sram_ctrl_scrambled_access_jitter_en"]
+ }
+ {
+ name: jitter_reduced_freq
+ tests: ["chip_sw_clkmgr_jitter_reduced_freq",
+ "chip_sw_flash_ctrl_ops_jitter_en_reduced_freq",
+ "chip_sw_flash_ctrl_access_jitter_en_reduced_freq",
+ "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq",
+ "chip_sw_aes_enc_jitter_en_reduced_freq",
+ "chip_sw_hmac_enc_jitter_en_reduced_freq",
+ "chip_sw_keymgr_key_derivation_jitter_en_reduced_freq",
+ "chip_sw_kmac_mode_kmac_jitter_en_reduced_freq",
+ "chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq",
+ "chip_sw_flash_init_reduced_freq",
+ "chip_sw_csrng_edn_concurrency_reduced_freq"]
+ }
+ {
+ name: xcelium_ci_0
+ tests: ["chip_plic_all_irqs",
+ "chip_sw_kmac_app_rom",
+ "chip_sw_rstmgr_sw_rst",
+ "chip_sw_hmac_enc",
+ "chip_sw_clkmgr_jitter",
+ "chip_sw_rom_ctrl_integrity_check",
+ "chip_tap_straps_dev",
+ "chip_tap_straps_prod",
+ "chip_tap_straps_rma",
+ "chip_sw_aes_entropy",
+ "chip_sw_kmac_idle",
+ "chip_sw_kmac_mode_cshake",
+ "chip_sw_kmac_mode_kmac",
+ "chip_sw_kmac_mode_kmac_jitter_en",
+ "chip_sw_sleep_pin_mio_dio_val",
+ // TODO: uncomment when these run with Xcelium.
+ // "chip_sw_lc_walkthrough_dev",
+ // "chip_sw_lc_walkthrough_prod",
+ // "chip_sw_lc_walkthrough_prodend",
+ // "chip_sw_lc_walkthrough_rma",
+ // "chip_sw_lc_walkthrough_testunlocks",
+ "chip_prim_tl_access"]
+ }
+ {
+ name: xcelium_ci_1
+ tests: ["chip_sw_rv_core_ibex_address_translation",
+ "chip_sw_rv_timer_irq",
+ "chip_sw_spi_device_tx_rx",
+ "chip_sw_usb_ast_clk_calib",
+ "chip_sw_plic_sw_irq",
+ "chip_sw_aes_enc",
+ "chip_sw_aes_enc_jitter_en",
+ "chip_sw_sram_ctrl_scrambled_access",
+ "chip_sw_sram_ctrl_scrambled_access_jitter_en",
+ "chip_sw_all_escalation_resets",
+ "chip_rv_dm_ndm_reset_req",
+ "chip_sw_entropy_src_ast_rng_req",
+ "chip_sw_entropy_src_kat_test",
+ "chip_sw_sensor_ctrl_status",
+ "chip_sw_rstmgr_sw_req",
+ "chip_sw_aes_idle",
+ // TODO: uncomment when these run with Xcelium.
+ // "chip_sw_pwrmgr_main_power_glitch_reset",
+ // "chip_sw_pwrmgr_deep_sleep_power_glitch_reset",
+ // "chip_sw_pwrmgr_sleep_power_glitch_reset",
+ "chip_sw_pwrmgr_sleep_disabled",
+ "chip_sw_csrng_kat_test",
+ "chip_sw_sysrst_ctrl_inputs"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/dv/chip_smoketests.hjson b/hw/top_sencha/dv/chip_smoketests.hjson
new file mode 100644
index 0000000..82285cb
--- /dev/null
+++ b/hw/top_sencha/dv/chip_smoketests.hjson
@@ -0,0 +1,130 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ # This auxiliary chip sim cfg specification focuses on chip level smoke tests.
+ # Please see chip_sim_cfg.hjson for full setup details.
+
+ # Note: Please maintain alphabetical order.
+ tests: [
+ {
+ name: chip_sw_aes_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aes_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_aon_timer_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:aon_timer_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_clkmgr_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:clkmgr_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ // TODO(lowrisc/opentitan#7505): Debug CSRNG generate bits mismatch.
+ {
+ name: chip_sw_csrng_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:csrng_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ // TODO(lowrisc/opentitan#10092): Remove dependency on uncontrolled environment.
+ {
+ name: chip_sw_entropy_src_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:entropy_src_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_gpio_smoketest
+ uvm_test_seq: chip_sw_gpio_smoke_vseq
+ sw_images: ["sw/device/tests/gpio_smoketest:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_hmac_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:hmac_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_kmac_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:kmac_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_otbn_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:otbn_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_otp_ctrl_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:otp_ctrl_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_pwrmgr_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:pwrmgr_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=10000000"]
+ }
+ {
+ name: chip_sw_rstmgr_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:rstmgr_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_rv_plic_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:rv_plic_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_sram_ctrl_smoketest
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:sram_ctrl_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
+ name: chip_sw_uart_smoketest
+ uvm_test_seq: chip_sw_uart_smoke_vseq
+ sw_images: ["//sw/device/tests:uart_smoketest:1:matcha"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ ]
+ regressions: [
+ {
+ name: smoke
+ tests: ["chip_sw_pwrmgr_smoketest"]
+ }
+ {
+ name: dif
+ tests: ["chip_sw_aes_smoketest",
+ "chip_sw_aon_timer_smoketest",
+ "chip_sw_clkmgr_smoketest",
+ // TODO(lowrisc/opentitan#7505): Debug CSRNG generate bits mismatch.
+ "chip_sw_csrng_smoketest",
+ // TODO(lowrisc/opentitan#10092): Remove dependency on uncontrolled environment.
+ "chip_sw_entropy_src_smoketest",
+ "chip_sw_gpio_smoketest",
+ "chip_sw_hmac_smoketest",
+ "chip_sw_kmac_smoketest",
+ "chip_sw_otbn_smoketest",
+ "chip_sw_otp_ctrl_smoketest",
+ "chip_sw_pwrmgr_smoketest",
+ "chip_sw_rstmgr_smoketest",
+ "chip_sw_rv_plic_smoketest",
+ "chip_sw_uart_smoketest",
+ ]
+ }
+ ]
+}
diff --git a/hw/top_sencha/dv/verilator/BUILD b/hw/top_sencha/dv/verilator/BUILD
new file mode 100644
index 0000000..36beb77
--- /dev/null
+++ b/hw/top_sencha/dv/verilator/BUILD
@@ -0,0 +1,10 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/dv/verilator/chip_sim.core b/hw/top_sencha/dv/verilator/chip_sim.core
new file mode 100644
index 0000000..33fc3a7
--- /dev/null
+++ b/hw/top_sencha/dv/verilator/chip_sim.core
@@ -0,0 +1,132 @@
+CAPI=2:
+# Copyright 2024 Google LLC
+# Copyright lowRISC contributors
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:sencha_verilator_sim:0.1"
+description: "Sencha toplevel for simulation with Verilator"
+filesets:
+ files_sim_verilator:
+ depend:
+ - lowrisc:dv_dpi:uartdpi
+ - lowrisc:dv_dpi:gpiodpi
+ - lowrisc:dv_dpi:jtagdpi
+ - lowrisc:dv_dpi:dmidpi
+ - lowrisc:dv_dpi:spidpi
+ - lowrisc:dv_dpi:usbdpi
+ - lowrisc:dv_verilator:memutil_verilator
+ - lowrisc:dv_verilator:simutil_verilator
+ - lowrisc:dv:sim_sram
+ - lowrisc:dv:sw_test_status
+ - lowrisc:dv:dv_test_status
+ - lowrisc:systems:chip_sencha_verilator
+ files:
+ - chip_sim_tb.sv: { file_type: systemVerilogSource }
+ - chip_sim_tb.cc: { file_type: cppSource }
+
+parameters:
+ # For value definition, please see ip/prim/rtl/prim_pkg.sv
+ PRIM_DEFAULT_IMPL:
+ datatype: str
+ paramtype: vlogdefine
+ description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
+ RVFI:
+ datatype: bool
+ paramtype: vlogdefine
+ description: Enable the RISC-V Verification Interface and instruction tracing
+ VERILATOR_MEM_BASE:
+ datatype: int
+ paramtype: vlogdefine
+ description: Main memory mem base.
+ VERILATOR_TEST_STATUS_ADDR:
+ datatype: int
+ paramtype: vlogdefine
+ description: Verilator specific address to write to, to report the test status. This value should be at a word offset in the unmapped address space.
+ SMC_VERILATOR_TEST_STATUS_ADDR:
+ datatype: int
+ paramtype: vlogdefine
+ description: Verilator specific address for the SMC to report test status. This value should be at a word offset in the unmapped address space.
+ flashinit:
+ datatype : file
+ description : Application to load into Flash (in Verilog hex format)
+ paramtype : cmdlinearg
+ rominit:
+ datatype : file
+ description : Application to load into Boot ROM (in Verilog hex format)
+ paramtype : cmdlinearg
+ otpinit:
+ datatype : file
+ description : Image to load into the OTP (in Verilog hex format)
+ paramtype : cmdlinearg
+ DMIDirectTAP:
+ datatype: bool
+ paramtype: vlogdefine
+ default: true
+ description: Replace JTAG TAP with an OpenOCD direct connection
+ UART_LOG_uart0:
+ datatype: string
+ paramtype: plusarg
+ description: Write a log of output from uart0 to the given log file. Use "-" for stdout.
+ RV_CORE_IBEX_SIM_SRAM:
+ datatype: bool
+ paramtype: vlogdefine
+ description: Disconnect the TL data output of rv_core_ibex so that we can attach the simulation SRAM.
+
+targets:
+ default: &default_target
+ filesets:
+ - files_sim_verilator
+ toplevel: sencha_sim_tb
+
+ sim:
+ parameters:
+ - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
+ - RVFI=true
+ - VERILATOR_MEM_BASE=0x10000000
+ - VERILATOR_TEST_STATUS_ADDR=0x411f0080
+ - SMC_VERILATOR_TEST_STATUS_ADDR=0x54030080
+ - flashinit
+ - rominit
+ - otpinit
+ - DMIDirectTAP
+ - RV_CORE_IBEX_SIM_SRAM=true
+ default_tool: verilator
+ filesets:
+ - files_sim_verilator
+ toplevel: sencha_sim_tb
+ tools:
+ verilator:
+ mode: cc
+ verilator_options:
+ # Disabling tracing reduces compile times but doesn't have a
+ # huge influence on runtime performance.
+ - '--trace'
+ - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
+ # Remove FST options for VCD trace
+ - '--trace-structs'
+ - '--trace-params'
+ - '--trace-max-array 1024'
+ - '--unroll-count 512'
+ # TODO: Variable expansion depends on edalize internals. Find better solution.
+ # (Applies to LDFLAGS expansion below as well)
+ - '-CFLAGS "$(CFLAGS_FOR_BUILD) -std=c++11 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=sencha_sim_tb"'
+ - '-LDFLAGS "$(LDFLAGS_FOR_BUILD) -pthread -lutil -lelf"'
+ - '-Wall'
+ # Execute simulation with four threads by default, which works best
+ # with four physical CPU cores.
+ # Users can override this setting by appending e.g.
+ # --verilator_options '--threads 2'
+ # to the end of the fusesoc invocation when compiling the simulation.
+ - '--threads 4'
+ # XXX: Cleanup all warnings and remove this option
+ # (or make it more fine-grained at least)
+ - '-Wno-fatal'
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_sencha/dv/verilator/chip_sim_tb.cc b/hw/top_sencha/dv/verilator/chip_sim_tb.cc
new file mode 100644
index 0000000..2beb1c9
--- /dev/null
+++ b/hw/top_sencha/dv/verilator/chip_sim_tb.cc
@@ -0,0 +1,82 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <algorithm>
+#include <iostream>
+#include <string>
+#include <vector>
+
+#include "verilated_toplevel.h"
+#include "verilator_memutil.h"
+#include "verilator_sim_ctrl.h"
+
+int main(int argc, char **argv) {
+ sencha_sim_tb top;
+ VerilatorMemUtil memutil;
+ VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
+ simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
+ VerilatorSimCtrlFlags::ResetPolarityNegative);
+
+ std::string top_scope("TOP.sencha_sim_tb.u_dut.top_sencha");
+ std::string ram1p_adv_scope(
+ "u_prim_ram_1p_adv.u_mem."
+ "gen_generic.u_impl_generic");
+
+ MemArea rom(top_scope + (".u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom."
+ "u_prim_rom.gen_generic.u_impl_generic"),
+ 0x4000 / 4, 4);
+ MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4,
+ 4);
+ // Only handle the lower bank of flash for now.
+ MemArea flash(top_scope +
+ ".u_flash_ctrl.u_eflash.u_flash.gen_generic.u_impl_generic."
+ "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem."
+ "gen_generic.u_impl_generic",
+ 0x80000 / 8, 8);
+ // Start with the flash region erased. Future loads can overwrite.
+ std::vector<uint8_t> all_ones(flash.GetSizeBytes());
+ std::fill(all_ones.begin(), all_ones.end(), 0xffu);
+ flash.Write(/*word_offset=*/0, all_ones);
+
+ MemArea otp(top_scope + ".u_otp_ctrl.u_otp.gen_generic.u_impl_generic." +
+ ram1p_adv_scope,
+ 0x4000 / 4, 4);
+ MemArea ram_smc(top_scope + ".u_ram1p_ram_smc.u_mem.gen_generic.u_impl_generic",
+ 0x400000 / 4, 4);
+ MemArea ml_dmem(top_scope + ".u_ml_top.u_ml_dmem.u_ram1p_dmem.u_mem.gen_generic.u_impl_generic",
+ 0x400000 / 32, 32);
+
+ memutil.RegisterMemoryArea("rom", 0x8000, &rom);
+ memutil.RegisterMemoryArea("ram", 0x10000000u, &ram);
+ memutil.RegisterMemoryArea("flash", 0x20000000u, &flash);
+ memutil.RegisterMemoryArea("otp", 0x40000000u /* (bogus LMA) */, &otp);
+ memutil.RegisterMemoryArea("ram_smc", 0x50000000u, &ram_smc);
+ memutil.RegisterMemoryArea("ml_dmem", 0x5A000000u, &ml_dmem);
+ simctrl.RegisterExtension(&memutil);
+
+ // The initial reset delay must be long enough such that pwr/rst/clkmgr will
+ // release clocks to the entire design. This allows for synchronous resets
+ // to appropriately propagate.
+ // The reset duration must be appropriately sized to the divider for clk_aon
+ // in chip_sencha_verilator.sv. It must be at least 2 cycles of clk_aon.
+ simctrl.SetInitialResetDelay(20000);
+ simctrl.SetResetDuration(10);
+
+ std::cout << "Simulation of Shodan Sencha" << std::endl
+ << "=================================" << std::endl
+ << std::endl;
+
+ return simctrl.Exec(argc, argv).first;
+}
diff --git a/hw/top_sencha/dv/verilator/chip_sim_tb.sv b/hw/top_sencha/dv/verilator/chip_sim_tb.sv
new file mode 100644
index 0000000..80022db
--- /dev/null
+++ b/hw/top_sencha/dv/verilator/chip_sim_tb.sv
@@ -0,0 +1,327 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module sencha_sim_tb (
+ // Clock and Reset
+ input clk_i,
+ input rst_ni
+);
+
+ logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
+ logic [31:0] cio_gpio_pull_en, cio_gpio_pull_select;
+ logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
+ logic cio_smc_uart_rx_p2d, cio_smc_uart_tx_d2p;
+
+ logic cio_spi_device_sck_p2d, cio_spi_device_csb_p2d;
+ logic cio_spi_device_sdi_p2d;
+ logic cio_spi_device_sdo_d2p, cio_spi_device_sdo_en_d2p;
+
+ logic cio_usbdev_sense_p2d;
+ logic cio_usbdev_se0_d2p;
+ logic cio_usbdev_dp_pullup_d2p;
+ logic cio_usbdev_dn_pullup_d2p;
+ logic cio_usbdev_rx_enable_d2p;
+ logic cio_usbdev_tx_use_d_se0_d2p;
+ logic cio_usbdev_d_p2d, cio_usbdev_d_d2p, cio_usbdev_d_en_d2p;
+ logic cio_usbdev_dp_p2d, cio_usbdev_dp_d2p, cio_usbdev_dp_en_d2p;
+ logic cio_usbdev_dn_p2d, cio_usbdev_dn_d2p, cio_usbdev_dn_en_d2p;
+
+ chip_sencha_verilator u_dut (
+ .clk_i,
+ .rst_ni,
+
+ // communication with GPIO
+ .cio_gpio_p2d_i(cio_gpio_p2d),
+ .cio_gpio_d2p_o(cio_gpio_d2p),
+ .cio_gpio_en_d2p_o(cio_gpio_en_d2p),
+ .cio_gpio_pull_en_o(cio_gpio_pull_en),
+ .cio_gpio_pull_select_o(cio_gpio_pull_select),
+
+ // communication with UART
+ .cio_uart_rx_p2d_i(cio_uart_rx_p2d),
+ .cio_uart_tx_d2p_o(cio_uart_tx_d2p),
+
+ // communication with SMC UART
+ .cio_uart_smc_rx_p2d_i(cio_smc_uart_rx_p2d),
+ .cio_uart_smc_tx_d2p_o(cio_smc_uart_tx_d2p),
+
+ // communication with SPI
+ .cio_spi_device_sck_p2d_i(cio_spi_device_sck_p2d),
+ .cio_spi_device_csb_p2d_i(cio_spi_device_csb_p2d),
+ .cio_spi_device_sdi_p2d_i(cio_spi_device_sdi_p2d),
+ .cio_spi_device_sdo_d2p_o(cio_spi_device_sdo_d2p),
+ .cio_spi_device_sdo_en_d2p_o(cio_spi_device_sdo_en_d2p),
+
+ // communication with USB
+ .cio_usbdev_sense_p2d_i(cio_usbdev_sense_p2d),
+ .cio_usbdev_dp_pullup_d2p_o(cio_usbdev_dp_pullup_d2p),
+ .cio_usbdev_dn_pullup_d2p_o(cio_usbdev_dn_pullup_d2p),
+ .cio_usbdev_dp_p2d_i(cio_usbdev_dp_p2d),
+ .cio_usbdev_dp_d2p_o(cio_usbdev_dp_d2p),
+ .cio_usbdev_dp_en_d2p_o(cio_usbdev_dp_en_d2p),
+ .cio_usbdev_dn_p2d_i(cio_usbdev_dn_p2d),
+ .cio_usbdev_dn_d2p_o(cio_usbdev_dn_d2p),
+ .cio_usbdev_dn_en_d2p_o(cio_usbdev_dn_en_d2p),
+ .cio_usbdev_d_p2d_i(cio_usbdev_d_p2d),
+ .cio_usbdev_d_d2p_o(cio_usbdev_d_d2p),
+ .cio_usbdev_d_en_d2p_o(cio_usbdev_d_en_d2p),
+ .cio_usbdev_se0_d2p_o(cio_usbdev_se0_d2p),
+ .cio_usbdev_rx_enable_d2p_o(cio_usbdev_rx_enable_d2p),
+ .cio_usbdev_tx_use_d_se0_d2p_o(cio_usbdev_tx_use_d_se0_d2p),
+
+ //Communication with I2S
+ .cio_i2s_rx_sd_p2d_i(cio_i2s_rx_sd_p2d),
+
+ .cio_i2s_rx_sclk_d2p_o(cio_i2s_rx_sclk_d2p),
+ .cio_i2s_rx_ws_d2p_o(cio_i2s_rx_ws_d2p),
+ .cio_i2s_tx_ws_d2p_o(cio_i2s_tx_ws_d2p),
+ .cio_i2s_tx_sd_d2p_o(cio_i2s_tx_sd_d2p_o),
+ .cio_i2s_tx_sclk_d2p_o(cio_i2s_tx_sclk_d2p)
+ );
+
+ // GPIO DPI
+ gpiodpi #(.N_GPIO(32)) u_gpiodpi (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .gpio_p2d (cio_gpio_p2d),
+ .gpio_d2p (cio_gpio_d2p),
+ .gpio_en_d2p(cio_gpio_en_d2p),
+ .gpio_pull_en(cio_gpio_pull_en),
+ .gpio_pull_sel(cio_gpio_pull_select)
+ );
+
+ // UART DPI
+ // The baud rate set to match FPGA implementation; the frequency is "artificial". Both baud rate
+ // frequency must match the settings used in the on-chip software at
+ // `sw/device/lib/arch/device_sim_verilator.c`.
+ uartdpi #(
+ .BAUD('d7_200),
+ .FREQ('d500_000)
+ ) u_uart (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tx_o (cio_uart_rx_p2d),
+ .rx_i (cio_uart_tx_d2p)
+ );
+
+ uartdpi #(
+ .BAUD('d7_200),
+ .FREQ('d500_000),
+ .NAME("smc_uart")
+ ) u_smc_uart (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tx_o (cio_smc_uart_rx_p2d),
+ .rx_i (cio_smc_uart_tx_d2p)
+ );
+//////////////////////////////////
+/// I2S Temporary Test Pattern ///
+//////////////////////////////////
+ wire sd;
+ wire sclk_i;
+ reg [DATA_WIDTH-1:0] data_tx; //Oversized 1x bit
+ integer indx_tx;
+
+ reg ws_rx_lag, ws_rx_reg;
+ wire ws_rx;
+ wire data_incr;
+
+ //SCLK get from ip
+ assign sclk_i = cio_i2s_rx_sclk_d2p;
+ assign ws_rx = cio_i2s_rx_ws_d2p;
+ assign cio_i2s_rx_sd_p2d = sd;
+ assign data_incr = (ws_rx != ws_rx_reg) && rst_ni;
+ assign sd = (indx_tx >= 0) ? data_tx[indx_tx]: 0;
+
+
+ parameter int unsigned DATA_WIDTH = 16;
+
+ //Transmit data buffer then switch to sending zeros. Real mic will be HI-Z after data.
+ always @(posedge sclk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ indx_tx <= DATA_WIDTH-1;
+ ws_rx_reg <= 0;
+ end else begin
+ indx_tx <= (data_incr) ? DATA_WIDTH-1 : indx_tx - 1;
+ ws_rx_reg <= ws_rx;
+ end
+ end
+
+ always @(posedge sclk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ data_tx <= 16'hff_ff;
+ end else begin
+ if (data_incr) begin
+ data_tx <= data_tx - 1;
+ end
+ end
+ end
+//////////////////////////////////////
+/// END I2S Temporary Test Pattern ///
+//////////////////////////////////////
+
+`ifdef DMIDirectTAP
+ // OpenOCD direct DMI TAP
+ bind rv_dm dmidpi u_dmidpi (
+ .clk_i,
+ .rst_ni,
+ .dmi_req_valid,
+ .dmi_req_ready,
+ .dmi_req_addr (dmi_req.addr),
+ .dmi_req_op (dmi_req.op),
+ .dmi_req_data (dmi_req.data),
+ .dmi_rsp_valid,
+ .dmi_rsp_ready,
+ .dmi_rsp_data (dmi_rsp.data),
+ .dmi_rsp_resp (dmi_rsp.resp),
+ .dmi_rst_n (dmi_rst_n)
+ );
+`else
+ // TODO: this is currently not supported.
+ // connect this to the correct pins once pinout is final and once the
+ // verilator testbench supports DFT/Debug strap sampling.
+ // See also #5221.
+ //
+ // jtagdpi u_jtagdpi (
+ // .clk_i,
+ // .rst_ni,
+
+ // .jtag_tck (cio_jtag_tck),
+ // .jtag_tms (cio_jtag_tms),
+ // .jtag_tdi (cio_jtag_tdi),
+ // .jtag_tdo (cio_jtag_tdo),
+ // .jtag_trst_n (cio_jtag_trst_n),
+ // .jtag_srst_n (cio_jtag_srst_n)
+ // );
+`endif
+
+ // SPI DPI
+ spidpi u_spi (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .spi_device_sck_o (cio_spi_device_sck_p2d),
+ .spi_device_csb_o (cio_spi_device_csb_p2d),
+ .spi_device_sdi_o (cio_spi_device_sdi_p2d),
+ .spi_device_sdo_i (cio_spi_device_sdo_d2p),
+ .spi_device_sdo_en_i (cio_spi_device_sdo_en_d2p)
+ );
+
+ // USB DPI
+ usbdpi u_usbdpi (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clk_48MHz_i (clk_i),
+ .sense_p2d (cio_usbdev_sense_p2d),
+ .pullupdp_d2p (cio_usbdev_dp_pullup_d2p),
+ .pullupdn_d2p (cio_usbdev_dn_pullup_d2p),
+ .dp_p2d (cio_usbdev_dp_p2d),
+ .dp_d2p (cio_usbdev_dp_d2p),
+ .dp_en_d2p (cio_usbdev_dp_en_d2p),
+ .dn_p2d (cio_usbdev_dn_p2d),
+ .dn_d2p (cio_usbdev_dn_d2p),
+ .dn_en_d2p (cio_usbdev_dn_en_d2p),
+ .d_p2d (cio_usbdev_d_p2d),
+ .d_d2p (cio_usbdev_d_d2p),
+ .d_en_d2p (cio_usbdev_d_en_d2p),
+ .se0_d2p (cio_usbdev_se0_d2p),
+ .rx_enable_d2p (cio_usbdev_rx_enable_d2p),
+ .tx_use_d_se0_d2p(cio_usbdev_tx_use_d_se0_d2p)
+ );
+
+ `define RV_CORE_IBEX u_dut.top_sencha.u_rv_core_ibex_sec
+ `define RV_CORE_SMC u_dut.top_sencha.u_rv_core_ibex_smc
+ `define SIM_SRAM_IF u_sim_sram.u_sim_sram_if
+ `define TEST_DONE_SEC u_sw_test_status_if.sw_test_done
+
+ // Detect SW test termination.
+ sim_sram u_sim_sram (
+ .clk_i (`RV_CORE_IBEX.clk_i),
+ .rst_ni (`RV_CORE_IBEX.rst_ni),
+ .tl_in_i (tlul_pkg::tl_h2d_t'(`RV_CORE_IBEX.u_tlul_req_buf.out_o)),
+ .tl_in_o (),
+ .tl_out_o (),
+ .tl_out_i ()
+
+ );
+
+ // Connect the sim SRAM directly inside rv_core_ibex.
+ assign `RV_CORE_IBEX.tl_win_d2h = u_sim_sram.tl_in_o;
+
+ // Instantiate the SW test status interface & connect signals from sim_sram_if instance
+ // instantiated inside sim_sram. Bind would have worked nicely here, but Verilator segfaults
+ // when trace is enabled (#3951).
+ sw_test_status_if u_sw_test_status_if (
+ .clk_i (`SIM_SRAM_IF.clk_i),
+ .rst_ni (`SIM_SRAM_IF.rst_ni),
+ .fetch_en (1'b0),
+ .wr_valid (`SIM_SRAM_IF.wr_valid),
+ .addr (`SIM_SRAM_IF.tl_h2d.a_address),
+ .data (`SIM_SRAM_IF.tl_h2d.a_data[15:0])
+ );
+
+ // Connect the SMC SRAM directly inside rv_core_smc.
+ assign `RV_CORE_SMC.tl_win_d2h = u_dut.top_sencha.u_tl_adapter_ram_smc.tl_o;
+
+ // Instantiate an interface to the SMC wrapper to monitor SW test termination.
+ sim_sram_if #(
+ .AddrWidth(32)
+ ) u_sim_sram_smc_if (
+ .clk_i (`RV_CORE_SMC.clk_i),
+ .rst_ni (`RV_CORE_SMC.rst_ni),
+ .tl_h2d (tlul_pkg::tl_h2d_t'(`RV_CORE_SMC.u_tlul_req_buf.out_o)),
+ .tl_d2h (tlul_pkg::tl_d2h_t'(`RV_CORE_SMC.tl_win_d2h))
+ );
+
+ // Instantiate separate sw_test_status_if for the SMC since we don't use address
+ // arbitration here.
+ sw_test_status_if u_sw_test_status_smc_if (
+ .clk_i (u_sim_sram_smc_if.clk_i),
+ .rst_ni (u_sim_sram_smc_if.rst_ni),
+ .fetch_en (1'b0),
+ .wr_valid (u_sim_sram_smc_if.wr_valid),
+ .addr (u_sim_sram_smc_if.tl_h2d.a_address),
+ .data (u_sim_sram_smc_if.tl_h2d.a_data[15:0])
+ );
+
+ // Set the start address of the simulation SRAM.
+ // Use offset 0 within both sim SRAM interfaces for SW test status indication.
+ initial begin
+ `SIM_SRAM_IF.start_addr = `VERILATOR_TEST_STATUS_ADDR;
+ u_sw_test_status_if.sw_test_status_addr = `SIM_SRAM_IF.start_addr;
+
+ u_sim_sram_smc_if.start_addr = `SMC_VERILATOR_TEST_STATUS_ADDR;
+ u_sw_test_status_smc_if.sw_test_status_addr = u_sim_sram_smc_if.start_addr;
+ end
+
+ always @(posedge clk_i) begin
+ if (u_sw_test_status_if.sw_test_done || u_sw_test_status_smc_if.sw_test_done) begin
+ $display("Verilator sim termination requested");
+ $display("Your simulation wrote to 0x%h", (`TEST_DONE_SEC ?
+ u_sw_test_status_if.sw_test_status_addr :
+ u_sw_test_status_smc_if.sw_test_status_addr));
+ dv_test_status_pkg::dv_test_status((`TEST_DONE_SEC ?
+ u_sw_test_status_if.sw_test_passed :
+ u_sw_test_status_smc_if.sw_test_passed));
+ $finish;
+ end
+ end
+
+ `undef RV_CORE_IBEX
+ `undef RV_CORE_SMC
+ `undef SIM_SRAM_IF
+ `undef TEST_DONE_SEC
+
+
+endmodule // sencha_sim_tb
diff --git a/hw/top_sencha/dv/verilator/verilator_sim_cfg.hjson b/hw/top_sencha/dv/verilator/verilator_sim_cfg.hjson
new file mode 100644
index 0000000..46e0f73
--- /dev/null
+++ b/hw/top_sencha/dv/verilator/verilator_sim_cfg.hjson
@@ -0,0 +1,218 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Name of the sim cfg - typically same as the name of the DUT.
+ name: chip_sencha_verilator
+
+ // Top level dut name (sv module).
+ dut: "{name}"
+
+ // Top level testbench name (sv module).
+ tb: "{name}"
+
+ // Default simulator used to sign off.
+ tool: verilator
+
+ // Fusesoc core file used for building the file list.
+ fusesoc_core: "lowrisc:systems:{name}:0.1"
+
+ // Testplan hjson file.
+ # testplan: "{proj_root}/hw/top_sencha/data/chip_testplan.hjson"
+
+ // Import additional common sim cfg files.
+ import_cfgs: [// Project wide common sim cfg file
+ "{proj_root}/hw/dv/tools/dvsim/verilator.hjson",
+ ]
+
+ overrides: [
+ // Use FuseSoC to build the Verilator executable. Skip the SV file list
+ // generation step entirely.
+ {
+ name: sv_flist_gen_cmd
+ value: ""
+ }
+ {
+ name: sv_flist_gen_opts
+ value: []
+ }
+ {
+ name: sv_flist_gen_dir
+ value: "{build_dir}"
+ }
+ // This defaults to 'ip' in `hw/data/common_project_cfg.hjson`. Override
+ // since we are building the top level.
+ {
+ name: design_level
+ value: top
+ }
+ ]
+
+ // Common run parameters. Each test entry can override any of these as needed.
+ reseed: 1
+ sw_build_device: sim_verilator
+
+ // Add run modes.
+ run_modes: [
+ {
+ name: sw_test_mode
+ sw_images: ["//sw/device/lib/testing/test_rom:test_rom:0",
+ "//hw/ip/otp_ctrl/data:img_rma:3"]
+ run_opts: [
+ // The following shell snippet converts the SW images specification to what's
+ // needed as a run time switch to Verilator.
+ '''{eval_cmd} \
+ opts=; \
+ types=(rom flash otbn otp); \
+ exts=(scr.39.vmem elf elf vmem); \
+ images=`echo {sw_images}`; \
+ for image in $images; do \
+ basename=`echo $image | cut -d: -f 2`; \
+ index=`echo $image | cut -d: -f 3`; \
+ opts="$opts --meminit=${types[$index]},{run_dir}/$basename""_{sw_build_device}.${exts[$index]}"; \
+ done; \
+ echo "$opts"''',
+ ]
+ }
+ ]
+
+ // All tests are SW based, so enable this by default.
+ en_run_modes: ["sw_test_mode"]
+
+ // List of test specifications.
+ //
+ // If you are adding a test that has been generated from a Bazel
+ // `opentitan_functest` macro, you can specify the test using its Bazel label
+ // followed by an index separated with a ':', which is used by the testbench
+ // to know what type of image is it:
+ // - 0 for Boot ROM,
+ // - 1 for SW test (loaded in flash),
+ // - 2 for OTBN test,
+ // - 3 for OTP.
+ // This allows an arbitrary number of SW images to be supplied to the TB.
+ //
+ // For example, if the Bazel label for a test is:
+ // `//sw/device/tests:example_test_from_flash`, then you would specify this as
+ // `//sw/device/tests:example_test_from_flash:1`.
+ tests: [
+ {
+ name: aes_smoketest
+ sw_images: ["//sw/device/tests:aes_smoketest:1"]
+ }
+ {
+ name: aon_timer_smoketest
+ sw_images: ["//sw/device/tests:aon_timer_smoketest:1"]
+ }
+ {
+ name: clkmgr_smoketest
+ sw_images: ["//sw/device/tests:clkmgr_smoketest:1"]
+ }
+ // TODO(lowrisc/opentitan#7505): Debug CSRNG generate bits mismatch.
+ // {
+ // name: csrng_smoketest
+ // sw_images: ["//sw/device/tests:csrng_smoketest:1"]
+ // }
+ // TODO(lowrisc/opentitan#10092): Remove dependency on uncontrolled environment.
+ {
+ name: entropy_src_smoketest
+ sw_images: ["//sw/device/tests:entropy_src_smoketest:1"]
+ }
+ {
+ name: gpio_smoketest
+ sw_images: ["//sw/device/tests:gpio_smoketest:1"]
+ }
+ {
+ name: hmac_smoketest
+ sw_images: ["//sw/device/tests:hmac_smoketest:1"]
+ }
+ {
+ name: kmac_smoketest
+ sw_images: ["//sw/device/tests:kmac_smoketest:1"]
+ }
+ {
+ name: kmac_mode_cshake_test
+ sw_images: ["//sw/device/tests:kmac_mode_cshake_test:1"]
+ }
+ {
+ name: kmac_mode_kmac_test
+ sw_images: ["//sw/device/tests:kmac_mode_kmac_test:1"]
+ }
+ {
+ name: crt_test
+ sw_images: ["//sw/device/tests:crt_test:1"]
+ }
+ {
+ name: otbn_smoketest_rtl
+ sw_images: ["//sw/device/tests:otbn_smoketest:1"]
+ }
+ {
+ name: otp_ctrl_smoketest
+ sw_images: ["//sw/device/tests:otp_ctrl_smoketest:1"]
+ }
+ {
+ name: rv_plic_smoketest
+ sw_images: ["//sw/device/tests:rv_plic_smoketest:1"]
+ }
+ // TODO(#6656): AST is not instantiated in chip_sencha_verilator.
+ // {
+ // name: pwrmgr_smoketest
+ // sw_images: ["//sw/device/tests:pwrmgr_smoketest:1"]
+ // }
+ {
+ name: rstmgr_smoketest
+ sw_images: ["//sw/device/tests:rstmgr_smoketest:1"]
+ }
+ {
+ name: rv_timer_smoketest
+ sw_images: ["//sw/device/tests:rv_timer_smoketest:1"]
+ }
+ {
+ name: uart_smoketest
+ sw_images: ["//sw/device/tests:uart_smoketest:1"]
+ }
+ {
+ name: flash_ctrl_test
+ sw_images: ["//sw/device/tests:flash_ctrl_test:1"]
+ }
+ {
+ name: pmp_smoketest_napot
+ sw_images: ["//sw/device/tests:pmp_smoketest_napot:1"]
+ }
+ {
+ name: pmp_smoketest_tor
+ sw_images: ["//sw/device/tests:pmp_smoketest_tor:1"]
+ }
+ {
+ name: usbdev_test
+ sw_images: ["//sw/device/tests:usbdev_test:1"]
+ }
+ {
+ name: sw_silicon_creator_lib_driver_hmac_functest
+ sw_images: ["//sw/device/silicon_creator/testing:sw_silicon_creator_lib_driver_hmac_functest:1"]
+ }
+ {
+ name: sw_silicon_creator_lib_driver_uart_functest
+ sw_images: ["//sw/device/silicon_creator/testing:sw_silicon_creator_lib_driver_uart_functest:1"]
+ }
+ {
+ name: sw_silicon_creator_lib_driver_alert_functest
+ sw_images: ["//sw/device/silicon_creator/testing:sw_silicon_creator_lib_driver_alert_functest:1"]
+ }
+ {
+ name: sw_silicon_creator_lib_driver_watchdog_functest
+ sw_images: ["//sw/device/silicon_creator/testing:sw_silicon_creator_lib_driver_watchdog_functest:1"]
+ }
+ {
+ name: sw_silicon_creator_lib_boot_data_functest
+ sw_images: ["//sw/device/silicon_creator/testing:sw_silicon_creator_lib_boot_data_functest:1"]
+ }
+ ]
+
+ // List of regressions.
+ regressions: [
+ {
+ name: smoke
+ tests: []
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/BUILD b/hw/top_sencha/ip/BUILD
new file mode 100644
index 0000000..794394c
--- /dev/null
+++ b/hw/top_sencha/ip/BUILD
@@ -0,0 +1,33 @@
+# Copyright 2024 Google LLC
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+exports_files(glob(["autogen/**"]))
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/ast:all_files",
+ "//hw/top_sencha/ip/clkmgr:all_files",
+ "//hw/top_sencha/ip/flash_ctrl:all_files",
+ "//hw/top_sencha/ip/pinmux:all_files",
+ "//hw/top_sencha/ip/pwrmgr:all_files",
+ "//hw/top_sencha/ip/rstmgr:all_files",
+ "//hw/top_sencha/ip/sensor_ctrl:all_files",
+ ],
+)
+
+filegroup(
+ name = "all_hjson_files",
+ srcs = glob(["**/data/**/*.hjson"]) + [
+ "//hw/top_sencha/ip/ast/data:ast.hjson",
+ "//hw/top_sencha/ip/clkmgr/data/autogen:clkmgr.hjson",
+ "//hw/top_sencha/ip/flash_ctrl/data/autogen:flash_ctrl.hjson",
+ "//hw/top_sencha/ip/pwrmgr/data/autogen:pwrmgr.hjson",
+ "//hw/top_sencha/ip/rstmgr/data/autogen:rstmgr.hjson",
+ "//hw/top_sencha/ip/sensor_ctrl/data:sensor_ctrl.hjson",
+ ],
+)
diff --git a/hw/top_sencha/ip/ast/BUILD b/hw/top_sencha/ip/ast/BUILD
new file mode 100644
index 0000000..66b2037
--- /dev/null
+++ b/hw/top_sencha/ip/ast/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/ast/data:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/ast/ast.core b/hw/top_sencha/ip/ast/ast.core
new file mode 100644
index 0000000..ac3dadc
--- /dev/null
+++ b/hw/top_sencha/ip/ast/ast.core
@@ -0,0 +1,127 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:systems:ast:0.1"
+description: "Analog Sensor Top generic views"
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:prim:all
+ - lowrisc:prim:clock_buf
+ - lowrisc:prim:clock_div
+ - lowrisc:prim:clock_gating
+ - lowrisc:prim:clock_inv
+ - lowrisc:prim:lc_dec
+ - lowrisc:prim:lfsr
+ - lowrisc:ip:pinmux_reg
+ - lowrisc:ip:pinmux_component
+ - lowrisc:prim:prim_pkg
+ - lowrisc:prim:mubi
+ - lowrisc:ip:lc_ctrl_pkg
+ - lowrisc:ip:edn_pkg
+ - lowrisc:ip_interfaces:alert_handler_reg
+ - lowrisc:ip:rstmgr_pkg
+ - lowrisc:systems:clkmgr_pkg
+ files:
+ - rtl/ast_reg_pkg.sv
+ - rtl/ast_pkg.sv
+ - rtl/ast_bhv_pkg.sv
+ - rtl/ast.sv
+ - rtl/ast_reg_top.sv
+ - rtl/adc.sv
+ - rtl/adc_ana.sv
+ - rtl/vcc_pgd.sv
+ - rtl/vio_pgd.sv
+ - rtl/vcaon_pgd.sv
+ - rtl/vcmain_pgd.sv
+ - rtl/ast_alert.sv
+ - rtl/aon_clk.sv
+ - rtl/aon_osc.sv
+ - rtl/io_clk.sv
+ - rtl/io_osc.sv
+ - rtl/sys_clk.sv
+ - rtl/sys_osc.sv
+ - rtl/usb_clk.sv
+ - rtl/usb_osc.sv
+ - rtl/audio_clk.sv
+ - rtl/audio_osc.sv
+ - rtl/gfr_clk_mux2.sv
+ - rtl/ast_clks_byp.sv
+ - rtl/rglts_pdm_3p3v.sv
+ - rtl/ast_pulse_sync.sv
+ - rtl/ast_entropy.sv
+ - rtl/dev_entropy.sv
+ - rtl/rng.sv
+ - rtl/ast_dft.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/ast.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/ast.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+ AST_BYPASS_CLK:
+ datatype: bool
+ paramtype: vlogdefine
+ ANALOGSIM:
+ datatype: bool
+ paramtype: vlogdefine
+
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
+ toplevel: ast
+ parameters:
+ - SYNTHESIS
+ - AST_BYPASS_CLK
+ - ANALOGSIM
+
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ - AST_BYPASS_CLK=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
+ sim:
+ <<: *default_target
+ default_tool: vcs
+ filesets:
+ - files_rtl
+ tools:
+ vcs:
+ vcs_options: [-sverilog -ntb_opts uvm-1.2 -CFLAGS --std=c99 -CFLAGS -fno-extended-identifiers -CFLAGS --std=c++11 -timescale=1ns/1ps -l vcs.log]
+ toplevel: ast
diff --git a/hw/top_sencha/ip/ast/ast_pkg.core b/hw/top_sencha/ip/ast/ast_pkg.core
new file mode 100644
index 0000000..d366795
--- /dev/null
+++ b/hw/top_sencha/ip/ast/ast_pkg.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:ast_pkg"
+description: "Analog sensor top (AST) wrapper package"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:constants:top_pkg
+ - lowrisc:ip:lc_ctrl_pkg
+ files:
+ - rtl/ast_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/ast/ast_regs.html b/hw/top_sencha/ip/ast/ast_regs.html
new file mode 100644
index 0000000..0abde57
--- /dev/null
+++ b/hw/top_sencha/ip/ast/ast_regs.html
@@ -0,0 +1,52 @@
+<table class="regdef" id="Reg_revid">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.REVID @ 0x0</div>
+ <div><p>AST Revision Identification Register <br>
+Reset: TLUL Reset</p></div>
+ <div>Reset default = 0x1, mask 0xff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="unused" colspan=16> </td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="unused" colspan=8> </td>
+<td class="fname" colspan=8>REVID</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">7:0</td><td class="regperm">ro</td><td class="regrv">0x1</td><td class="regfn">REVID</td><td class="regde"><p>Revision</p></td></table>
+<br>
+<table class="regdef" id="Reg_rwtype0">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.RWTYPE0 @ 0x4</div>
+ <div><p>RW type with one field</p></div>
+ <div>Reset default = 0xbc614e, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>RWTYPE0...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...RWTYPE0</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0xbc614e</td><td class="regfn">RWTYPE0</td><td class="regde"><p>field description</p></td></table>
+<br>
+<table class="regdef" id="Reg_rwtype1">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.RWTYPE1 @ 0x8</div>
+ <div><p>RW type
+with long
+description
+and multiple fields</p></div>
+ <div>Reset default = 0x6411, mask 0xff13</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="unused" colspan=16> </td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=8>FIELD15_8</td>
+<td class="unused" colspan=3> </td>
+<td class="fname" colspan=1 style="font-size:50.0%">FIELD4</td>
+<td class="unused" colspan=2> </td>
+<td class="fname" colspan=1 style="font-size:50.0%">FIELD1</td>
+<td class="fname" colspan=1 style="font-size:50.0%">FIELD0</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">0</td><td class="regperm">rw</td><td class="regrv">0x1</td><td class="regfn">FIELD0</td><td class="regde"><p>field 0</p></td><tr><td class="regbits">1</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">FIELD1</td><td class="regde"><p>field 1</p></td><tr><td class="regbits">3:2</td><td></td><td></td><td></td><td>Reserved</td></tr><tr><td class="regbits">4</td><td class="regperm">rw</td><td class="regrv">0x1</td><td class="regfn">FIELD4</td><td class="regde"><p>field 4</p></td><tr><td class="regbits">7:5</td><td></td><td></td><td></td><td>Reserved</td></tr><tr><td class="regbits">15:8</td><td class="regperm">rw</td><td class="regrv">0x64</td><td class="regfn">FIELD15_8</td><td class="regde"><p>field [15:8]</p></td></table>
+<br>
diff --git a/hw/top_sencha/ip/ast/data/BUILD b/hw/top_sencha/ip/ast/data/BUILD
new file mode 100644
index 0000000..12f1f39
--- /dev/null
+++ b/hw/top_sencha/ip/ast/data/BUILD
@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+load("@lowrisc_opentitan//rules:autogen.bzl", "autogen_hjson_header")
+
+autogen_hjson_header(
+ name = "ast_regs",
+ srcs = [
+ "ast.hjson",
+ ],
+)
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/ip/ast/data/ast.hjson b/hw/top_sencha/ip/ast/data/ast.hjson
new file mode 100644
index 0000000..c2f52e2
--- /dev/null
+++ b/hw/top_sencha/ip/ast/data/ast.hjson
@@ -0,0 +1,619 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//#############################################################################
+// *Name: ast
+// *Module Description: Analog Sensors Top Registers
+//#############################################################################
+{ name: "ast",
+ design_spec: "../doc",
+ dv_doc: "",
+ hw_checklist: "",
+ sw_checklist: "",
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D2",
+ verification_stage: "V2S",
+ dif_stage: "",
+ clocking: [
+ { clock: "clk_ast_tlul_i", reset: "rst_ast_tlul_ni", primary: true },
+ { clock: "clk_ast_adc_i", reset: "rst_ast_adc_ni"},
+ { clock: "clk_ast_alert_i", reset: "rst_ast_alert_ni"},
+ { clock: "clk_ast_es_i", reset: "rst_ast_es_ni"},
+ { clock: "clk_ast_rng_i", reset: "rst_ast_rng_ni"},
+ { clock: "clk_ast_usb_i", reset: "rst_ast_usb_ni"},
+ ],
+ bus_interfaces: [
+ { protocol: "tlul",
+ direction: "device"
+ }
+ ],
+ no_auto_alert_regs: "True",
+ param_list: [
+ { name: "NumRegsB",
+ desc: "Number of registers in the Array-B",
+ type: "int",
+ default: "5",
+ local: "true",
+ },
+ { name: "NumUsbBeaconPulses",
+ desc: "Number of USB valid beacon pulses for clock to re-calibrate",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+ ],
+ regwidth: "32",
+ registers: [
+ { name: "REGA0",
+ desc: "AST Register 0 for OTP/ROM Write Testing",
+ swaccess: "ro",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclAll" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x00",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA1",
+ desc: "AST 1 Register for OTP/ROM Write Testing",
+ swaccess: "ro",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclAll" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x01",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA2",
+ desc: "AST 2 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x02",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA3",
+ desc: "AST 3 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x03",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA4",
+ desc: "AST 4 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x04",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA5",
+ desc: "AST 5 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x05",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA6",
+ desc: "AST 6 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x06",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA7",
+ desc: "AST 7 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x07",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA8",
+ desc: "AST 8 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x08",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA9",
+ desc: "AST 9 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x09",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA10",
+ desc: "AST 10 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x0A",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA11",
+ desc: "AST 11 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x0B",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA12",
+ desc: "AST 13 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x0C",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA13",
+ desc: "AST 13 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x0D",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA14",
+ desc: "AST 14 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x0E",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA15",
+ desc: "AST 15 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x0F",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA16",
+ desc: "AST 16 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x10",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA17",
+ desc: "AST 17 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x11",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA18",
+ desc: "AST 18 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x12",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA19",
+ desc: "AST 19 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x13",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA20",
+ desc: "AST 20 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x14",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA21",
+ desc: "AST 21 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x15",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA22",
+ desc: "AST 22 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x16",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA23",
+ desc: "AST 23 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x17",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA24",
+ desc: "AST 24 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x18",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA25",
+ desc: "AST 25 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x19",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA26",
+ desc: "AST 26 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x1A",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA27",
+ desc: "AST 27 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x1B",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA28",
+ desc: "AST 28 Register for OTP/ROM Write Testing",
+ swaccess: "ro",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x1C",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA29",
+ desc: "AST 29 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x1D",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA30",
+ desc: "AST 30 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x1E",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA31",
+ desc: "AST 31 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x1F",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA32",
+ desc: "AST 32 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x20",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA33",
+ desc: "AST 33 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x21",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA34",
+ desc: "AST 34 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x22",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA35",
+ desc: "AST 35 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x23",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA36",
+ desc: "AST 36 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x24",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGA37",
+ desc: "AST 37 Register for OTP/ROM Write Testing",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclWrite" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x25",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ { name: "REGAL",
+ desc: "AST Last Register for OTP/ROM Write Testing",
+ swaccess: "wo",
+ hwaccess: "hrw",
+ hwext: "true",
+ hwqe: "true",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclAll" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0x26",
+ },
+ ],
+ }, //----------------------------------------------------------------------
+ ///////////////////////////////////////////////////////////////////////////
+ { skipto: "0x200" }
+ ///////////////////////////////////////////////////////////////////////////
+ { multireg:
+ {
+ name: "REGB",
+ desc: "AST Registers Array-B to set address space size",
+ count: "NumRegsB",
+ cname: "REGB",
+ swaccess: "rw",
+ hwaccess: "hro",
+ tags: [ // don't write random data to any of the AST registers
+ "excl:CsrAllTests:CsrExclAll" ],
+ fields: [
+ { bits: "31:0",
+ name: "reg32",
+ desc: "32-bit Register",
+ resval: "0",
+ },
+ ],
+ },
+ }, //----------------------------------------------------------------------
+ ],
+}
diff --git a/hw/top_sencha/ip/ast/data/ast_cdc_abstract.sgdc b/hw/top_sencha/ip/ast/data/ast_cdc_abstract.sgdc
new file mode 100644
index 0000000..c8fe774
--- /dev/null
+++ b/hw/top_sencha/ip/ast/data/ast_cdc_abstract.sgdc
@@ -0,0 +1,631 @@
+################################################################################
+#
+# This file has been generated by SpyGlass:
+# File Created by: ngotliv
+# File Created on: Thu May 19 11:20:01 2022
+# Working Directory: /tanap1/proj_cd14/opentitan/ngotliv/nightly_220518/nuvoton/top/spyglass
+# File Location : ./ast_cdc/ast/cdc/cdc_abstract/spyglass_reports/abstract_view/ast_AdcChannels_2_AdcDataWidth_10_Ast2PadOutWidth_9_Entro_1_cdc_abstract.sgdc
+# SpyGlass Version : SpyGlass_vR-2020.12-1
+# Policy Name : clock-reset
+# Comment : Generated by rule Ac_abstract01
+#
+################################################################################
+if { $::sg_use_cdc_abstract_view == 1 } {
+ abstract_file -version 5.1.0 -scope cdc
+
+ current_design "ast" -def_param
+
+#################################################################
+# abstract_port constraints #
+#################################################################
+
+abstract_port -path_logic combo -ports "otp_power_seq_h_o[0]" -related_ports otp_power_seq_i[0]
+abstract_port -path_logic combo -ports "otp_power_seq_h_o[1]" -related_ports otp_power_seq_i[1]
+abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][0]" -related_ports padmux2ast_i[4]
+abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][1]" -related_ports padmux2ast_i[5]
+abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][2]" -related_ports padmux2ast_i[6]
+abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][3]" -related_ports padmux2ast_i[7]
+abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][0]" -related_ports padmux2ast_i[0]
+abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][1]" -related_ports padmux2ast_i[1]
+abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][2]" -related_ports padmux2ast_i[2]
+abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][3]" -related_ports padmux2ast_i[3]
+
+#################################################################
+# clock constraints #
+#################################################################
+
+
+# Clock constraint is not generated.
+
+
+#################################################################
+# set_case_analysis constraints #
+#################################################################
+
+set_case_analysis -name "tl_o[d_user][rsp_intg][6]" -value 0
+set_case_analysis -name "tl_o[d_sink][0]" -value 0
+set_case_analysis -name "tl_o[d_param][0]" -value 0
+set_case_analysis -name "tl_o[d_param][1]" -value 0
+set_case_analysis -name "tl_o[d_param][2]" -value 0
+set_case_analysis -name "tl_o[d_opcode][1]" -value 0
+set_case_analysis -name "tl_o[d_opcode][2]" -value 0
+
+#################################################################
+# reset constraints #
+#################################################################
+
+reset -name "tl_o[a_ready]" -value 1
+reset -name "tl_o[d_valid]" -value 0
+reset -name "ast_pwst_o[main_pok]" -value 0
+reset -name "ast_pwst_o[vcc_pok]" -value 0
+reset -name "ast_pwst_h_o[main_pok]" -value 0
+reset -name "ast_pwst_h_o[vcc_pok]" -value 0
+reset -name "flash_power_ready_h_o" -value 0
+
+# Synchronous reset constraint is not generated.
+
+
+#################################################################
+# quasi_static constraints #
+#################################################################
+
+quasi_static -name "ast2padmux_o[0]"
+quasi_static -name "ast2padmux_o[1]"
+quasi_static -name "ast2padmux_o[2]"
+quasi_static -name "ast2padmux_o[3]"
+quasi_static -name "ast2padmux_o[4]"
+quasi_static -name "ast2padmux_o[5]"
+quasi_static -name "ast2padmux_o[6]"
+quasi_static -name "ast2padmux_o[7]"
+quasi_static -name "ast2padmux_o[8]"
+quasi_static -name "ast2pad_t0_ao"
+quasi_static -name "ast2pad_t1_ao"
+quasi_static -name "dft_scan_md_o[0]"
+quasi_static -name "dft_scan_md_o[1]"
+quasi_static -name "dft_scan_md_o[2]"
+quasi_static -name "dft_scan_md_o[3]"
+
+#################################################################
+# abstract_port constraints #
+#################################################################
+
+abstract_port -ports "adc_d_o" -scope cdc -clock "clk_ast_adc_i" -related_ports "adc_pd_i" "adc_chnsel_i"
+abstract_port -ports "adc_d_val_o" -scope cdc -clock "clk_ast_adc_i" -related_ports "adc_pd_i" "adc_chnsel_i"
+abstract_port -ports "alert_req_o[alerts][0][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][0][n]" "alert_rsp_i[alerts_ack][0][n]"
+abstract_port -ports "alert_req_o[alerts][0][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][0][p]" "alert_rsp_i[alerts_ack][0][p]"
+abstract_port -ports "alert_req_o[alerts][1][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][1][n]" "alert_rsp_i[alerts_ack][1][n]"
+abstract_port -ports "alert_req_o[alerts][1][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][1][p]" "alert_rsp_i[alerts_ack][1][p]"
+abstract_port -ports "alert_req_o[alerts][2][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][2][n]" "alert_rsp_i[alerts_ack][2][n]"
+abstract_port -ports "alert_req_o[alerts][2][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][2][p]" "alert_rsp_i[alerts_ack][2][p]"
+abstract_port -ports "alert_req_o[alerts][3][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][3][n]" "alert_rsp_i[alerts_ack][3][n]"
+abstract_port -ports "alert_req_o[alerts][3][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][3][p]" "alert_rsp_i[alerts_ack][3][p]"
+abstract_port -ports "alert_req_o[alerts][4][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][4][n]" "alert_rsp_i[alerts_ack][4][n]"
+abstract_port -ports "alert_req_o[alerts][4][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][4][p]" "alert_rsp_i[alerts_ack][4][p]"
+abstract_port -ports "alert_req_o[alerts][5][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][5][n]" "alert_rsp_i[alerts_ack][5][n]"
+abstract_port -ports "alert_req_o[alerts][5][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][5][p]" "alert_rsp_i[alerts_ack][5][p]"
+abstract_port -ports "alert_req_o[alerts][6][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][6][n]" "alert_rsp_i[alerts_ack][6][n]"
+abstract_port -ports "alert_req_o[alerts][6][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][6][p]" "alert_rsp_i[alerts_ack][6][p]"
+abstract_port -ports "alert_req_o[alerts][7][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][7][n]" "alert_rsp_i[alerts_ack][7][n]"
+abstract_port -ports "alert_req_o[alerts][7][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][7][p]" "alert_rsp_i[alerts_ack][7][p]"
+abstract_port -ports "alert_req_o[alerts][8][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][8][n]" "alert_rsp_i[alerts_ack][8][n]"
+abstract_port -ports "alert_req_o[alerts][8][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][8][p]" "alert_rsp_i[alerts_ack][8][p]"
+abstract_port -ports "alert_req_o[alerts][9][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][9][n]" "alert_rsp_i[alerts_ack][9][n]"
+abstract_port -ports "alert_req_o[alerts][9][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][9][p]" "alert_rsp_i[alerts_ack][9][p]"
+abstract_port -ports "alert_req_o[alerts][10][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][10][n]" "alert_rsp_i[alerts_ack][10][n]"
+abstract_port -ports "alert_req_o[alerts][10][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][10][p]" "alert_rsp_i[alerts_ack][10][p]"
+abstract_port -ports "alert_req_o[alerts][11][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][11][n]" "alert_rsp_i[alerts_ack][11][n]"
+abstract_port -ports "alert_req_o[alerts][11][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][11][p]" "alert_rsp_i[alerts_ack][11][p]"
+abstract_port -ports "alert_req_o[alerts][12][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][12][n]" "alert_rsp_i[alerts_ack][12][n]"
+abstract_port -ports "alert_req_o[alerts][12][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][12][p]" "alert_rsp_i[alerts_ack][12][p]"
+abstract_port -ports "entropy_req_o[edn_req]" -scope cdc -clock "clk_ast_es_i" -related_ports "entropy_rsp_i[edn_ack]"
+abstract_port -ports "tl_o[a_ready]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_error]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_user][rsp_intg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_user][rsp_intg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][0]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_user][rsp_intg][4]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][1]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_user][rsp_intg][5]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_data][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_data][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_data][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_data][4]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_data][5]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][6]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]"
+abstract_port -ports "tl_o[d_data][7]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "otp_alert_src_i[n]" "otp_alert_src_i[p]"
+abstract_port -ports "tl_o[d_data][8]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][9]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][10]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][11]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][12]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][13]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][14]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][15]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][16]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][17]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][18]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][19]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][20]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][21]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][22]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][23]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][24]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][25]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][26]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][27]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][28]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][29]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][30]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_data][31]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_source][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][0]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_source][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][1]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_source][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_source][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][3]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_source][4]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][4]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_source][5]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][5]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_source][6]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][6]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_source][7]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][7]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_size][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][0]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_size][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][1]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_opcode][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_valid]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_user][data_intg][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_user][data_intg][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_user][data_intg][2]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_user][data_intg][3]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_user][data_intg][4]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_user][data_intg][5]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_user][data_intg][6]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]"
+abstract_port -ports "tl_o[d_user][rsp_intg][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "tl_o[d_user][rsp_intg][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "ast_init_done_o" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "usb_io_pu_cal_o" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obmen][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obmen][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obmen][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obmen][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obmsl][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obmsl][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obmsl][2]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obmsl][3]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obgsl][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obgsl][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obgsl][2]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "obs_ctrl_o[obgsl][3]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "flash_bist_en_o" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_b][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_b][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_b][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_b][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_en_b]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_a][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_a][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_a][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_a][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rmf_o[marg_en_a]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_b][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_b][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_b][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_b][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_en_b]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_a][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_a][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_a][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_a][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "dpram_rml_o[marg_en_a]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "spram_rm_o[marg][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "spram_rm_o[marg][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "spram_rm_o[marg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "spram_rm_o[marg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "spram_rm_o[marg_en]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprgf_rm_o[marg][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprgf_rm_o[marg][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprgf_rm_o[marg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprgf_rm_o[marg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprgf_rm_o[marg_en]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprom_rm_o[marg][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprom_rm_o[marg][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprom_rm_o[marg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprom_rm_o[marg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "sprom_rm_o[marg_en]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]"
+abstract_port -ports "ast_pwst_o[vcc_pok]" -scope cdc -clock "clk_src_aon_o"
+abstract_port -ports "ast_pwst_o[aon_pok]" -scope cdc -clock "clk_src_aon_o" -related_ports "main_pd_ni"
+abstract_port -ports "ast_pwst_o[main_pok]" -scope cdc -clock "clk_src_aon_o" -combo yes -related_ports "main_pd_ni"
+abstract_port -ports "ast_pwst_h_o[vcc_pok]" -scope cdc -clock "clk_src_aon_o"
+abstract_port -ports "ast_pwst_h_o[aon_pok]" -scope cdc -clock "clk_src_aon_o" -related_ports "main_pd_ni"
+abstract_port -ports "ast_pwst_h_o[main_pok]" -scope cdc -clock "clk_src_aon_o" -combo yes -related_ports "main_pd_ni"
+abstract_port -ports "flash_power_down_h_o" -scope cdc -clock "clk_src_aon_o"
+abstract_port -ports "otp_power_seq_h_o" -scope cdc -clock "clk_src_aon_o"
+abstract_port -ports "clk_src_aon_val_o" -scope cdc -clock SG_VIRT_OUT_20
+abstract_port -ports "clk_src_sys_val_o" -scope cdc -clock SG_VIRT_OUT_83
+abstract_port -ports "clk_src_io_val_o" -scope cdc -clock SG_VIRT_OUT_84
+abstract_port -ports "clk_src_usb_val_o" -scope cdc -clock SG_VIRT_OUT_85
+
+
+#################################################################
+#translating input constraints to abstract_port where it involves
+#a sync crossing and apending -combo no #
+#################################################################
+
+abstract_port -ports "clk_src_sys_en_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_ast_ext_i"
+abstract_port -ports "clk_src_sys_jen_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_src_sys_o"
+abstract_port -ports "clk_src_io_en_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_ast_ext_i"
+abstract_port -ports "clk_src_usb_en_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_ast_ext_i"
+abstract_port -ports "rng_en_i" -scope cdc -clock "clk_src_sys_o" -combo no -combo_ifn "clk_ast_tlul_i"
+abstract_port -ports "rng_fips_i" -scope cdc -clock "clk_src_sys_o" -combo no -combo_ifn "clk_ast_tlul_i"
+abstract_port -ports "ext_freq_is_96m_i" -scope cdc -clock "clk_ast_tlul_i" -combo no
+abstract_port -ports "all_clk_byp_req_i" -scope cdc -clock "clk_ast_tlul_i" -combo no
+abstract_port -ports "io_clk_byp_req_i" -scope cdc -clock "clk_ast_tlul_i" -combo no
+
+
+#################################################################
+#Adding -combo no to abstract_port defined at input port#
+#If it invloves a synchronized control crossing #
+#################################################################
+
+
+#################################################################
+# qualifier constraints #
+#################################################################
+
+#Port with -ignore constraint.Reason:Path is Hanging or Blocked#
+abstract_port -ports "ast_pwst_o[io_pok][0]" -scope cdc -ignore -comment "blocked or hanging path"
+######################################################
+#Port with -ignore constraint.Reason:Path is Hanging or Blocked#
+abstract_port -ports "ast_pwst_o[io_pok][1]" -scope cdc -ignore -comment "blocked or hanging path"
+######################################################
+#Port with -ignore constraint.Reason:Path is Hanging or Blocked#
+abstract_port -ports "ast_pwst_h_o[io_pok][0]" -scope cdc -ignore -comment "blocked or hanging path"
+######################################################
+
+#Port with -ignore constraint.Reason:Path is Hanging or Blocked#
+abstract_port -ports "ast_pwst_h_o[io_pok][1]" -scope cdc -ignore -comment "blocked or hanging path"
+######################################################
+#################################################################
+# virtual clock constraints #
+#################################################################
+
+clock -tag SG_VIRT_OUT_20 -domain "domain20"
+## "abstraction_new_domain_83" :: bbox_merged_domain_83
+clock -tag SG_VIRT_OUT_83 -domain "abstraction_new_domain_83"
+## "abstraction_new_domain_84" :: bbox_merged_domain_84
+clock -tag SG_VIRT_OUT_84 -domain "abstraction_new_domain_84"
+## "abstraction_new_domain_85" :: bbox_merged_domain_85
+clock -tag SG_VIRT_OUT_85 -domain "abstraction_new_domain_85"
+#################################################################
+# cdc_attribute constraints #
+#################################################################
+
+
+# cdc_attribute constraint is not generated.
+
+
+#################################################################
+# reset_filter_path constraints #
+#################################################################
+
+reset_filter_path -type rdc -from_rst "tl_o[a_ready]" -to_rst "tl_o[d_valid]" "rst_ast_tlul_ni"
+reset_filter_path -type rdc -from_rst "tl_o[d_valid]" -to_rst "tl_o[a_ready]" "rst_ast_tlul_ni"
+reset_filter_path -type rdc -from_rst "rst_ast_tlul_ni" -to_rst "tl_o[a_ready]" "tl_o[d_valid]"
+reset_filter_path -type rdc -from_rst "ast_pwst_o[main_pok]" -to_rst "ast_pwst_h_o[main_pok]" "ast_pwst_h_o[vcc_pok]"
+reset_filter_path -type rdc -from_rst "ast_pwst_h_o[main_pok]" -to_rst "ast_pwst_o[main_pok]" "ast_pwst_h_o[vcc_pok]"
+reset_filter_path -type rdc -from_rst "ast_pwst_h_o[vcc_pok]" -to_rst "ast_pwst_o[main_pok]" "ast_pwst_h_o[main_pok]"
+reset_filter_path -type rdc -from_rst "obs_ctrl_o[obmsl][3]" -to_rst "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]"
+reset_filter_path -type rdc -from_rst "ast2padmux_o[0]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]"
+reset_filter_path -type rdc -from_rst "ast2padmux_o[1]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]"
+reset_filter_path -type rdc -from_rst "ast2padmux_o[2]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]"
+reset_filter_path -type rdc -from_rst "ast2padmux_o[4]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]"
+reset_filter_path -type rdc -from_rst "ast2padmux_o[5]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]"
+reset_filter_path -type rdc -from_rst "ast2padmux_o[6]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[7]" "ast2padmux_o[8]"
+reset_filter_path -type rdc -from_rst "ast2padmux_o[7]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[8]"
+reset_filter_path -type rdc -from_rst "ast2padmux_o[8]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]"
+
+#################################################################
+# Inferred abstract_port constraints #
+#################################################################
+
+
+abstract_port -ports "por_ni" -clock "clk_src_aon_o" -start
+abstract_port -ports "fla_alert_src_i[n]" -clock "clk_ast_tlul_i" -combo no -start
+abstract_port -ports "fla_alert_src_i[p]" -clock "clk_ast_tlul_i" -combo no -start
+abstract_port -ports "otp_alert_src_i[n]" -clock "clk_ast_tlul_i" -combo no -start
+abstract_port -ports "otp_alert_src_i[p]" -clock "clk_ast_tlul_i" -combo no -start
+abstract_port -ports "sns_clks_i[clk_io_peri]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_usb_peri]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_div2_peri]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_div4_peri]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_div4_timers]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_usb_secure]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_main_secure]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_div4_secure]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_div2_infra]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_infra]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_main_infra]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_div4_infra]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_main_otbn]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_main_kmac]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_main_hmac]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_main_aes]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_aon_timers]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_aon_peri]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_aon_secure]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_aon_infra]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_div2_powerup]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_usb_powerup]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_powerup]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_main_powerup]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_aon_powerup]" -ignore -comment "hanging path"
+abstract_port -ports "sns_clks_i[clk_io_div4_powerup]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_i2c2_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_i2c2_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_i2c1_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_i2c1_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_i2c0_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_i2c0_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_usbif_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_usbif_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_usb_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_usb_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_spi_host1_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_spi_host1_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_spi_host0_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_spi_host0_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_spi_device_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_spi_device_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_sys_aon_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_sys_aon_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_sys_io_div4_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_sys_io_div4_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_sys_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_sys_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_sys_shadowed_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_sys_shadowed_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_aon_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_aon_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_io_div4_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_io_div4_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_io_div4_shadowed_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_io_div4_shadowed_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_shadowed_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_lc_shadowed_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_usb_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_usb_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_io_div4_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_io_div4_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_io_div4_shadowed_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_io_div4_shadowed_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_io_div2_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_io_div2_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_io_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_io_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_aon_n][0]" -ignore -comment "hanging path"
+abstract_port -ports "sns_rsts_i[rst_por_aon_n][1]" -ignore -comment "hanging path"
+abstract_port -ports "sns_spi_ext_clk_i" -ignore -comment "hanging path"
+abstract_port -ports "vcc_supp_i" -ignore -comment "hanging path"
+abstract_port -ports "vcaon_supp_i" -ignore -comment "hanging path"
+abstract_port -ports "vcmain_supp_i" -ignore -comment "hanging path"
+abstract_port -ports "vioa_supp_i" -ignore -comment "hanging path"
+abstract_port -ports "viob_supp_i" -ignore -comment "hanging path"
+clock -tag SG_VCLK_1
+
+#################################################################
+# cdc_filter_coherency constraints #
+#################################################################
+
+
+# cdc_filter_coherency constraint is not generated.
+
+
+
+#################################################################
+# clock_sense constraints #
+#################################################################
+
+
+#################################################################
+# reset_sense constraints #
+#################################################################
+
+# reset_sense constraint is not generated. Either no reset defined on input ports or no combinational path found from primary resets to output port.
+
+#################################################################
+# block interface constraints #
+#################################################################
+
+abstract_interface_param -name "AdcChannels" -value "2"
+abstract_interface_param -name "AdcDataWidth" -value "10"
+abstract_interface_param -name "EntropyStreams" -value "4"
+abstract_interface_param -name "UsbCalibWidth" -value "20"
+abstract_interface_param -name "Ast2PadOutWidth" -value "9"
+abstract_interface_param -name "Pad2AstInWidth" -value "9"
+abstract_interface_port -name "tl_i" -definition "input tlul_pkg :: tl_h2d_t tl_i;"
+abstract_interface_port -name "tl_o" -definition "output tlul_pkg :: tl_d2h_t tl_o;"
+abstract_interface_port -name "ast_init_done_o" -definition "output logic ast_init_done_o; "
+abstract_interface_port -name "clk_ast_adc_i" -definition "input clk_ast_adc_i; "
+abstract_interface_port -name "rst_ast_adc_ni" -definition "input rst_ast_adc_ni; "
+abstract_interface_port -name "clk_ast_alert_i" -definition "input clk_ast_alert_i; "
+abstract_interface_port -name "rst_ast_alert_ni" -definition "input rst_ast_alert_ni; "
+abstract_interface_port -name "clk_ast_es_i" -definition "input clk_ast_es_i; "
+abstract_interface_port -name "rst_ast_es_ni" -definition "input rst_ast_es_ni; "
+abstract_interface_port -name "clk_ast_rng_i" -definition "input clk_ast_rng_i; "
+abstract_interface_port -name "rst_ast_rng_ni" -definition "input rst_ast_rng_ni; "
+abstract_interface_port -name "clk_ast_tlul_i" -definition "input clk_ast_tlul_i; "
+abstract_interface_port -name "rst_ast_tlul_ni" -definition "input rst_ast_tlul_ni; "
+abstract_interface_port -name "clk_ast_usb_i" -definition "input clk_ast_usb_i; "
+abstract_interface_port -name "rst_ast_usb_ni" -definition "input rst_ast_usb_ni; "
+abstract_interface_port -name "clk_ast_ext_i" -definition "input clk_ast_ext_i; "
+abstract_interface_port -name "por_ni" -definition "input por_ni; "
+abstract_interface_port -name "sns_clks_i" -definition "input clkmgr_pkg :: clkmgr_out_t sns_clks_i;"
+abstract_interface_port -name "sns_rsts_i" -definition "input rstmgr_pkg :: rstmgr_out_t sns_rsts_i;"
+abstract_interface_port -name "sns_spi_ext_clk_i" -definition "input sns_spi_ext_clk_i; "
+abstract_interface_port -name "vcc_supp_i" -definition "input vcc_supp_i; "
+abstract_interface_port -name "vcaon_supp_i" -definition "input vcaon_supp_i; "
+abstract_interface_port -name "vcmain_supp_i" -definition "input vcmain_supp_i; "
+abstract_interface_port -name "vioa_supp_i" -definition "input vioa_supp_i; "
+abstract_interface_port -name "viob_supp_i" -definition "input viob_supp_i; "
+abstract_interface_port -name "ast_pwst_o" -definition "output ast_pkg :: ast_pwst_t ast_pwst_o;"
+abstract_interface_port -name "ast_pwst_h_o" -definition "output ast_pkg :: ast_pwst_t ast_pwst_h_o;"
+abstract_interface_port -name "main_pd_ni" -definition "input main_pd_ni; "
+abstract_interface_port -name "main_env_iso_en_i" -definition "input main_env_iso_en_i; "
+abstract_interface_port -name "flash_power_down_h_o" -definition "output logic flash_power_down_h_o; "
+abstract_interface_port -name "flash_power_ready_h_o" -definition "output logic flash_power_ready_h_o; "
+abstract_interface_port -name "otp_power_seq_i" -definition "input [1:0] otp_power_seq_i; "
+abstract_interface_port -name "otp_power_seq_h_o" -definition "output logic [1:0] otp_power_seq_h_o; "
+abstract_interface_port -name "clk_src_sys_en_i" -definition "input clk_src_sys_en_i; "
+abstract_interface_port -name "clk_src_sys_jen_i" -definition "input prim_mubi_pkg :: mubi4_t clk_src_sys_jen_i;"
+abstract_interface_port -name "clk_src_sys_o" -definition "output logic clk_src_sys_o; "
+abstract_interface_port -name "clk_src_sys_val_o" -definition "output logic clk_src_sys_val_o; "
+abstract_interface_port -name "clk_src_aon_o" -definition "output logic clk_src_aon_o; "
+abstract_interface_port -name "clk_src_aon_val_o" -definition "output logic clk_src_aon_val_o; "
+abstract_interface_port -name "clk_src_io_en_i" -definition "input clk_src_io_en_i; "
+abstract_interface_port -name "clk_src_io_o" -definition "output logic clk_src_io_o; "
+abstract_interface_port -name "clk_src_io_val_o" -definition "output logic clk_src_io_val_o; "
+abstract_interface_port -name "clk_src_io_48m_o" -definition "output prim_mubi_pkg :: mubi4_t clk_src_io_48m_o;"
+abstract_interface_port -name "usb_ref_pulse_i" -definition "input usb_ref_pulse_i; "
+abstract_interface_port -name "usb_ref_val_i" -definition "input usb_ref_val_i; "
+abstract_interface_port -name "clk_src_usb_en_i" -definition "input clk_src_usb_en_i; "
+abstract_interface_port -name "clk_src_usb_o" -definition "output logic clk_src_usb_o; "
+abstract_interface_port -name "clk_src_usb_val_o" -definition "output logic clk_src_usb_val_o; "
+abstract_interface_port -name "usb_io_pu_cal_o" -definition "output logic [(UsbCalibWidth - 1):0] usb_io_pu_cal_o; "
+abstract_interface_port -name "adc_pd_i" -definition "input adc_pd_i; "
+abstract_interface_port -name "adc_a0_ai" -definition "input ast_pkg :: awire_t adc_a0_ai;"
+abstract_interface_port -name "adc_a1_ai" -definition "input ast_pkg :: awire_t adc_a1_ai;"
+abstract_interface_port -name "adc_chnsel_i" -definition "input [(AdcChannels - 1):0] adc_chnsel_i; "
+abstract_interface_port -name "adc_d_o" -definition "output [(AdcDataWidth - 1):0] adc_d_o; "
+abstract_interface_port -name "adc_d_val_o" -definition "output adc_d_val_o; "
+abstract_interface_port -name "rng_en_i" -definition "input rng_en_i; "
+abstract_interface_port -name "rng_fips_i" -definition "input rng_fips_i; "
+abstract_interface_port -name "rng_val_o" -definition "output logic rng_val_o; "
+abstract_interface_port -name "rng_b_o" -definition "output logic [(EntropyStreams - 1):0] rng_b_o; "
+abstract_interface_port -name "entropy_rsp_i" -definition "input edn_pkg :: edn_rsp_t entropy_rsp_i;"
+abstract_interface_port -name "entropy_req_o" -definition "output edn_pkg :: edn_req_t entropy_req_o;"
+abstract_interface_port -name "fla_alert_src_i" -definition "input ast_pkg :: ast_dif_t fla_alert_src_i;"
+abstract_interface_port -name "otp_alert_src_i" -definition "input ast_pkg :: ast_dif_t otp_alert_src_i;"
+abstract_interface_port -name "alert_rsp_i" -definition "input ast_pkg :: ast_alert_rsp_t alert_rsp_i;"
+abstract_interface_port -name "alert_req_o" -definition "output ast_pkg :: ast_alert_req_t alert_req_o;"
+abstract_interface_port -name "dft_strap_test_i" -definition "input pinmux_pkg :: dft_strap_test_req_t dft_strap_test_i;"
+abstract_interface_port -name "lc_dft_en_i" -definition "input lc_ctrl_pkg :: lc_tx_t lc_dft_en_i;"
+abstract_interface_port -name "fla_obs_i" -definition "input [(8 - 1):0] fla_obs_i; "
+abstract_interface_port -name "otp_obs_i" -definition "input [(8 - 1):0] otp_obs_i; "
+abstract_interface_port -name "otm_obs_i" -definition "input [(8 - 1):0] otm_obs_i; "
+abstract_interface_port -name "usb_obs_i" -definition "input usb_obs_i; "
+abstract_interface_port -name "obs_ctrl_o" -definition "output ast_pkg :: ast_obs_ctrl_t obs_ctrl_o;"
+abstract_interface_port -name "padmux2ast_i" -definition "input [(Pad2AstInWidth - 1):0] padmux2ast_i; "
+abstract_interface_port -name "ast2padmux_o" -definition "output logic [(Ast2PadOutWidth - 1):0] ast2padmux_o; "
+abstract_interface_port -name "ast2pad_t0_ao" -definition "output ast2pad_t0_ao; "
+abstract_interface_port -name "ast2pad_t1_ao" -definition "output ast2pad_t1_ao; "
+abstract_interface_port -name "ext_freq_is_96m_i" -definition "input prim_mubi_pkg :: mubi4_t ext_freq_is_96m_i;"
+abstract_interface_port -name "all_clk_byp_req_i" -definition "input prim_mubi_pkg :: mubi4_t all_clk_byp_req_i;"
+abstract_interface_port -name "all_clk_byp_ack_o" -definition "output prim_mubi_pkg :: mubi4_t all_clk_byp_ack_o;"
+abstract_interface_port -name "io_clk_byp_req_i" -definition "input prim_mubi_pkg :: mubi4_t io_clk_byp_req_i;"
+abstract_interface_port -name "io_clk_byp_ack_o" -definition "output prim_mubi_pkg :: mubi4_t io_clk_byp_ack_o;"
+abstract_interface_port -name "flash_bist_en_o" -definition "output prim_mubi_pkg :: mubi4_t flash_bist_en_o;"
+abstract_interface_port -name "dpram_rmf_o" -definition "output ast_pkg :: dpm_rm_t dpram_rmf_o;"
+abstract_interface_port -name "dpram_rml_o" -definition "output ast_pkg :: dpm_rm_t dpram_rml_o;"
+abstract_interface_port -name "spram_rm_o" -definition "output ast_pkg :: spm_rm_t spram_rm_o;"
+abstract_interface_port -name "sprgf_rm_o" -definition "output ast_pkg :: spm_rm_t sprgf_rm_o;"
+abstract_interface_port -name "sprom_rm_o" -definition "output ast_pkg :: spm_rm_t sprom_rm_o;"
+abstract_interface_port -name "dft_scan_md_o" -definition "output prim_mubi_pkg :: mubi4_t dft_scan_md_o;"
+abstract_interface_port -name "scan_shift_en_o" -definition "output scan_shift_en_o; "
+abstract_interface_port -name "scan_reset_no" -definition "output scan_reset_no; "
+}
+
+if { $::sg_use_cdc_abstract_view == 1 } {
+
+
+ current_design "ast" -def_param
+abstract_block_violation -name Propagate_Clocks -sev WARNING -count 1
+abstract_block_violation -name Setup_check01 -sev WARNING -count 16
+abstract_block_violation -name ErrorAnalyzeBBox -sev ERROR -count 1 -is_builtin
+abstract_block_violation -name SYNTH_78 -sev WARNING -count 10 -is_builtin
+abstract_block_violation -name SYNTH_89 -sev WARNING -count 4 -is_builtin
+abstract_block_violation -name SYNTH_93 -sev WARNING -count 1 -is_builtin
+abstract_block_violation -name SYNTH_1084 -sev ERROR -count 1 -is_builtin
+abstract_block_violation -name WRN_1459 -sev WARNING -count 5 -is_builtin
+abstract_block_violation -name WRN_1470 -sev WARNING -count 5 -is_builtin
+abstract_block_violation -name checkCMD_dirfile03 -sev WARNING -count 29 -is_builtin
+abstract_block_violation -name Propagate_Resets -sev WARNING -count 4
+abstract_block_violation -name Setup_blackbox01 -sev WARNING -count 13
+abstract_block_violation -name Clock_check07 -sev WARNING -count 27
+
+
+block_file_decompiled_start
+
+ input -name "tl_i" -clock "ast.clk_ast_tlul_i"
+ input -name "ast.rst_ast_adc_ni" -clock "ast.clk_ast_adc_i"
+ input -name "ast.rst_ast_alert_ni" -clock "ast.clk_ast_alert_i"
+ input -name "ast.rst_ast_es_ni" -clock "ast.clk_ast_es_i"
+ input -name "ast.rst_ast_rng_ni" -clock "ast.clk_ast_rng_i"
+ input -name "ast.rst_ast_tlul_ni" -clock "ast.clk_ast_tlul_i"
+ input -name "ast.rst_ast_usb_ni" -clock "ast.clk_ast_usb_i"
+ input -name "ast.main_pd_ni" -clock "ast.clk_src_aon_o"
+ input -name "ast.main_env_iso_en_i" -clock "ast.clk_src_aon_o"
+ input -name "otp_power_seq_i" -clock "ast.clk_src_aon_o"
+ input -name "clk_src_sys_en_i" -clock "ast.clk_src_aon_o"
+ input -name "clk_src_sys_jen_i" -clock "ast.clk_src_aon_o"
+ input -name "clk_src_io_en_i" -clock "ast.clk_src_aon_o"
+ input -name "usb_ref_pulse_i" -clock "ast.clk_ast_usb_i"
+ input -name "usb_ref_val_i" -clock "ast.clk_ast_usb_i"
+ input -name "clk_src_usb_en_i" -clock "ast.clk_src_aon_o"
+ input -name "adc_pd_i" -clock "ast.clk_ast_adc_i"
+ input -name "adc_a0_ai" -clock "ast.clk_ast_adc_i"
+ input -name "adc_a1_ai" -clock "ast.clk_ast_adc_i"
+ input -name "adc_chnsel_i" -clock "ast.clk_ast_adc_i"
+ input -name "rng_en_i" -clock "ast.clk_src_sys_o"
+ input -name "rng_fips_i" -clock "ast.clk_src_sys_o"
+ input -name "entropy_rsp_i" -clock "ast.clk_ast_es_i"
+ input -name "alert_rsp_i" -clock "ast.clk_ast_alert_i"
+ input -name "dft_strap_test_i" -clock "ast.clk_ast_tlul_i"
+ input -name "lc_dft_en_i" -clock "ast.clk_ast_tlul_i"
+ input -name "fla_obs_i" -clock "ast.clk_ast_tlul_i"
+ input -name "otp_obs_i" -clock "ast.clk_ast_tlul_i"
+ input -name "otm_obs_i" -clock "ast.clk_ast_tlul_i"
+ input -name "usb_obs_i" -clock "ast.clk_ast_tlul_i"
+ input -name "ext_freq_is_96m_i" -clock "ast.clk_ast_tlul_i"
+ input -name "all_clk_byp_req_i" -clock "ast.clk_ast_tlul_i"
+ input -name "io_clk_byp_req_i" -clock "ast.clk_ast_tlul_i"
+ output -name "tl_o" -clock "ast.clk_ast_tlul_i"
+ output -name "ast_init_done_o" -clock "ast.clk_ast_tlul_i"
+ output -name "ast.flash_power_down_h_o" -clock "ast.clk_src_aon_o"
+ output -name "ast.flash_power_ready_h_o" -clock "ast.clk_src_aon_o"
+ output -name "ast.otp_power_seq_h_o" -clock "ast.clk_src_aon_o"
+ output -name "clk_src_sys_val_o" -clock "ast.clk_src_sys_o"
+ output -name "clk_src_aon_val_o" -clock "ast.clk_src_aon_o"
+ output -name "clk_src_io_val_o" -clock "ast.clk_src_io_o"
+ output -name "clk_src_io_48m_o" -clock "ast.clk_src_io_o"
+ output -name "clk_src_usb_val_o" -clock "ast.clk_src_usb_o"
+ output -name "usb_io_pu_cal_o" -clock "ast.clk_ast_tlul_i"
+ output -name "adc_d_o" -clock "ast.clk_ast_adc_i"
+ output -name "adc_d_val_o" -clock "ast.clk_ast_adc_i"
+ output -name "rng_val_o" -clock "ast.clk_ast_rng_i"
+ output -name "rng_b_o" -clock "ast.clk_ast_rng_i"
+ output -name "entropy_req_o" -clock "ast.clk_ast_es_i"
+ output -name "alert_req_o" -clock "ast.clk_ast_alert_i"
+ output -name "obs_ctrl_o" -clock "ast.clk_ast_tlul_i"
+ output -name "all_clk_byp_ack_o" -clock "ast.clk_src_io_o"
+ output -name "io_clk_byp_ack_o" -clock "ast.clk_src_io_o"
+ output -name "flash_bist_en_o" -clock "ast.clk_ast_tlul_i"
+ output -name "dpram_rmf_o" -clock "ast.clk_ast_tlul_i"
+ output -name "dpram_rml_o" -clock "ast.clk_ast_tlul_i"
+ output -name "spram_rm_o" -clock "ast.clk_ast_tlul_i"
+ output -name "sprgf_rm_o" -clock "ast.clk_ast_tlul_i"
+ output -name "sprom_rm_o" -clock "ast.clk_ast_tlul_i"
+ output -name "dft_scan_md_o" -clock "ast.clk_ast_tlul_i"
+ output -name "scan_shift_en_o" -clock "ast.clk_ast_tlul_i"
+ output -name "scan_reset_no" -clock "ast.clk_ast_tlul_i"
+ clock -name "clk_src_sys_o" -domain domain7 -tag SG_AUTO_TAG_7
+ clock -name "clk_src_aon_o" -domain domain8 -tag SG_AUTO_TAG_8
+ clock -name "clk_src_io_o" -domain domain_9 -tag SG_AUTO_TAG_9
+ clock -name "clk_src_usb_o" -domain domain_10 -tag SG_AUTO_TAG_10
+ reset -name "fla_alert_src_i" -value 0
+ reset -name "otp_alert_src_i" -value 0
+ quasi_static -name "padmux2ast_i"
+ quasi_static -name "ast2padmux_o"
+ quasi_static -name "ast2pad_t0_ao"
+ quasi_static -name "ast2pad_t1_ao"
+
+block_file_decompiled_end
+}
diff --git a/hw/top_sencha/ip/ast/doc/_index.md b/hw/top_sencha/ip/ast/doc/_index.md
new file mode 100644
index 0000000..854c395
--- /dev/null
+++ b/hw/top_sencha/ip/ast/doc/_index.md
@@ -0,0 +1,1060 @@
+---
+title: "Analog Sensor Top Technical Specification"
+---
+
+# Overview
+
+AST, also known as the analog sensor top, is the OpenTitan analog and
+security companion. Within AST are various analog functions (such as
+clocks, regulators, random number generators) needed to make the device
+function, as well as physical security sensors necessary to protect the
+device from physical attacks or manipulation.
+
+At a high level, AST communicates with a number of OpenTitan comportable
+modules. See diagram below.
+
+
+
+In the following sections, each family of connection is briefly
+described and explained. Note, the analog connections to AST are not
+shown in the diagram, but will be explained as well.
+
+# Interface Signals Table
+
+## Table notes
+
+### Signal naming conventions used in this document
+
+It complies with OpenTitan [<u>names
+</u>](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#naming)and
+[<u>suffixes</u>](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#suffixes)
+with some augmentations.
+
+ - Clock signals start with clk\_\*
+
+ - Inputs and outputs are marked with \*\_i/\*\_o
+
+ - Analog signals are marked with \*\_a
+
+ - Non-core level signals are marked with \*\_h
+
+ - Dual and negative polarity signals are marked with \*\_p/n
+
+### Clock domains column
+
+ - sys - system clock, mainly used for high performance and security
+ modules. Up to 100MHz
+
+ - io - peripheral clock source, mainly used for peripherals and I/O
+ related functionality. Up to 96MHz (divided by 4 by the clock
+ manager)
+
+ - susb - USB module source clock. 48MHz
+
+ - aon - Always-on domain clock. The only active clock while chip is
+ in deep-sleep power state, 200KHz
+
+ - async - when listed as async, it means it does not matter what
+ domain drives the signal
+
+ - Input clocks: Each functional interface has a dedicated clock
+ named after the interface.
+
+<table>
+<thead>
+<tr class="header">
+<th><strong>Signal Name & Affiliation</strong></th>
+<th><strong>I/O</strong></th>
+<th><strong>Width</strong></th>
+<th><strong>Clock Domain</strong></th>
+<th><strong>Description</strong></th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td><strong>Power Supplies</strong></td>
+<td></td>
+<td></td>
+<td></td>
+<td></td>
+</tr>
+<tr class="even">
+<td>VCC</td>
+<td>I</td>
+<td></td>
+<td></td>
+<td><p>VCC is the main power supply. It is driven from an external source and is used to power the internal VCMAIN and VCAON power domains.</p>
+<p>VCC must always be present when the device is functioning; VCC is also used to power a number of pads that must be always on when the device is functioning.</p></td>
+</tr>
+<tr class="odd">
+<td>AVCC</td>
+<td>I</td>
+<td></td>
+<td></td>
+<td>Analog blocks power supply. AVCC and AGND are analog supply and ground signals for the AST analog functions. They mainly serve for ADC and USB clock functionality. AVCC is expected to be driven by the same voltage regulator and have similar power availability as VCC. AVCC and AGND have dedicated package balls/pins. In the future, package pins sharing with VCC and GND may be considered based on post-silicon test results.</td>
+</tr>
+<tr class="even">
+<td>VCMAIN</td>
+<td>O</td>
+<td></td>
+<td></td>
+<td>Main core power, driven by internal capless voltage regulator</td>
+</tr>
+<tr class="odd">
+<td>VCAON</td>
+<td>O</td>
+<td></td>
+<td></td>
+<td>Core voltage power for always-on domain (same voltage range as VCMAIN)</td>
+</tr>
+<tr class="even">
+<td>VIOA</td>
+<td>I</td>
+<td></td>
+<td></td>
+<td>IO supply, powering a set of pads. Unlike VCC, the IO supplies can be turned off by external components and the device will continue to function, the unpowered pads however, become inoperable.</td>
+</tr>
+<tr class="odd">
+<td>VIOB</td>
+<td>I</td>
+<td></td>
+<td></td>
+<td>Same as VIOA, but for a different set of pads.</td>
+</tr>
+<tr class="even">
+<td>GND</td>
+<td>I</td>
+<td></td>
+<td></td>
+<td>Ground</td>
+</tr>
+<tr class="odd">
+<td>AGND</td>
+<td>I</td>
+<td></td>
+<td></td>
+<td>Analog ground (see AVCC for further details)</td>
+</tr>
+<tr class="even">
+<td><strong>Power Control and Reset</strong></td>
+<td></td>
+<td></td>
+<td></td>
+<td></td>
+</tr>
+<tr class="odd">
+<td>otp_power_seq_i</td>
+<td>I</td>
+<td>2</td>
+<td>async</td>
+<td>Contains the power sequencing signals coming from the OTP macro.</td>
+</tr>
+<tr class="even">
+<td>otp_power_seq_h_o</td>
+<td>O</td>
+<td>2</td>
+<td>async</td>
+<td>Contains the power sequencing signals going to the OTP macro (<strong>VCC domain</strong>).</td>
+</tr>
+<tr class="odd">
+<td>flash_power_down_h_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>Connected to flash (<strong>VCC domain</strong>). Used for flash power management.</td>
+</tr>
+<tr class="even">
+<td>flash_power_ready_h_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>Connected to flash (<strong>VCC domain</strong>). Used for flash power management.</td>
+</tr>
+<tr class="odd">
+<td>vcmain_pok_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>Main core power-exist indication. Used by the OpenTitan power manager to determine the state of the main digital supply during power up and power down sequencing.</td>
+</tr>
+<tr class="even">
+<td>vcaon_pok_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>Always-on power-exist indication. Used by the OpenTitan power manager for power-on reset root.</td>
+</tr>
+<tr class="odd">
+<td>vioa_pok_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>VIOA power-exist indications. Used as a power-OK status signal.</td>
+</tr>
+<tr class="even">
+<td>viob_pok_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>VIOB power-exist indication. Used as a power-OK status signal.</td>
+</tr>
+<tr class="odd">
+<td>por_ni</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td>Power on reset input signal to AST. See <a href="#resets"><u>Resets</u></a> section for further details</td>
+</tr>
+<tr class="even">
+<td>main_pd_ni</td>
+<td>I</td>
+<td>1</td>
+<td>aon</td>
+<td>Power down enable for main core power<br />
+0: main core power is down (deep-sleep state)<br />
+1: main core power is up<br />
+It may take up to 200 uS from this signal transition to power switching completion by AST (not including boot time and so). Note that flash must be prepared for power down before this signal is asserted.</td>
+</tr>
+<tr class="odd">
+<td>main_iso_en_i</td>
+<td>I</td>
+<td>1</td>
+<td>aon</td>
+<td>Isolation enable for main core power (VCMAIN). This signal is fed to AST for any local power clamping needs. This signal is only valid after aon core is available, until then, VCC / AVCC components must take appropriate steps to protect themselves.</td>
+</tr>
+<tr class="even">
+<td><strong>Clock Outputs</strong></td>
+<td></td>
+<td></td>
+<td></td>
+<td></td>
+</tr>
+<tr class="odd">
+<td>clk_src_sys_o</td>
+<td>O</td>
+<td>1</td>
+<td>sys</td>
+<td>100 MHz clock with jitter (main clock domain). Used as the main system clock.</td>
+</tr>
+<tr class="even">
+<td>clk_src_sys_val_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>System clock valid. Used as "ack" signals for the power manager (TBD - add a link)</td>
+</tr>
+<tr class="odd">
+<td>clk_src_sys_en_i</td>
+<td>I</td>
+<td>1</td>
+<td>aon</td>
+<td>System clock enable.</td>
+</tr>
+<tr class="even">
+<td>clk_src_sys_jen_i</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td>System clock jitter enable</td>
+</tr>
+<tr class="odd">
+<td>clk_src_aon_o</td>
+<td>O</td>
+<td>1</td>
+<td>aon</td>
+<td>200 KHz clock for always-on domain.</td>
+</tr>
+<tr class="even">
+<td>clk_src_aon_val_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>aon clock valid</td>
+</tr>
+<tr class="odd">
+<td>clk_src_usb_o</td>
+<td>O</td>
+<td>1</td>
+<td>susb</td>
+<td>48 MHz clock for USB. To comply with USB full speed clock specification, it supports frequency accuracy of +/-2500 ppm when usb_ref_pulse_i is available and +/-2% otherwise. It may take up to 50 ms for this clock to reach the accuracy target from the time ‘usb_ref_pulse_i’ is available. USB clock calibration interface is further detailed <a href="https://github.com/lowRISC/opentitan/blob/master/hw/ip/usbdev/doc/_index.md#clocking"><u>here</u></a>.</td>
+</tr>
+<tr class="even">
+<td>clk_src_usb_val_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>USB clock valid</td>
+</tr>
+<tr class="odd">
+<td>clk_src_usb_en_i</td>
+<td>I</td>
+<td>1</td>
+<td>aon</td>
+<td>USB clock enable</td>
+</tr>
+<tr class="even">
+<td>usb_ref_pulse_i</td>
+<td>I</td>
+<td>1</td>
+<td>usb</td>
+<td>USB reference pulse +/-500ppm. When valid, it is expected to pulse every 1ms.</td>
+</tr>
+<tr class="odd">
+<td>usb_ref_val_i</td>
+<td>I</td>
+<td>1</td>
+<td>usb</td>
+<td>USB reference valid. This bit serves as a valid signal for the usb_ref_pulse_i signal. It is set to 1 after the first valid usb_ref_pulse_i event is detected and remains high as long as usb_ref_pulse_i continues to behave as expected (per usb_ref_pulse description). Once usb_ref_pulse deviates from its expected behavior, usb_ref_val_i immediately negates to 0 and remains 0 until after the next valid usb_ref_val pulse.</td>
+</tr>
+<tr class="even">
+<td>clk_src_io_o</td>
+<td>O</td>
+<td>1</td>
+<td>io</td>
+<td>96 MHz clock with +/-2% frequency accuracy. Used for peripherals that require a fixed frequency, for example SPI and UART</td>
+</tr>
+<tr class="odd">
+<td>clk_src_io_val_o</td>
+<td>O</td>
+<td>1</td>
+<td>async</td>
+<td>I/O and timer clock valid. Used as "ack" signals for the power manager (TBD - add a link).</td>
+</tr>
+<tr class="even">
+<td>clk_src_io_en_i</td>
+<td>I</td>
+<td>1</td>
+<td>aon</td>
+<td>I/O and timer clock enable</td>
+</tr>
+<tr class="odd">
+<td><strong>Clock & Reset Inputs</strong></td>
+<td></td>
+<td></td>
+<td></td>
+<td></td>
+</tr>
+<tr class="even">
+<td>clk_ast_adc_i</td>
+<td>I</td>
+<td>1</td>
+<td>adc</td>
+<td>ADC interface clock input</td>
+</tr>
+<tr class="odd">
+<td>clk_ast_rng_i</td>
+<td>I</td>
+<td>1</td>
+<td>rng</td>
+<td>RNG interface clock input</td>
+</tr>
+<tr class="even">
+<td>clk_ast_usb_i</td>
+<td>I</td>
+<td>1</td>
+<td>usb</td>
+<td>USB reference interface clock input</td>
+</tr>
+<tr class="odd">
+<td>clk_ast_es_i</td>
+<td>I</td>
+<td>1</td>
+<td>es</td>
+<td>Entropy source interface clock input</td>
+</tr>
+<tr class="even">
+<td>clk_ast_alert_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>Alert interface clock input</td>
+</tr>
+<tr class="odd">
+<td>clk_ast_tlul_i</td>
+<td>I</td>
+<td>1</td>
+<td>tlul</td>
+<td>TLUL bus interface clock input</td>
+</tr>
+<tr class="even">
+<td>rst_ast_adc_ni</td>
+<td>I</td>
+<td>1</td>
+<td>adc</td>
+<td>ADC interface reset (active low)</td>
+</tr>
+<tr class="odd">
+<td>rst_ast_rng_ni</td>
+<td>I</td>
+<td>1</td>
+<td>rng</td>
+<td>RNG interface reset (active low)</td>
+</tr>
+<tr class="even">
+<td>rst_ast_usb_ni</td>
+<td>I</td>
+<td>1</td>
+<td>usb</td>
+<td>USB reference interface reset (active low)</td>
+</tr>
+<tr class="odd">
+<td>rst_ast_es_ni</td>
+<td>I</td>
+<td>1</td>
+<td>es</td>
+<td>Entropy source interface reset (active low)</td>
+</tr>
+<tr class="even">
+<td>rst_ast_alert_ni</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>Alert interface interface reset (active low)</td>
+</tr>
+<tr class="odd">
+<td>rst_ast_tlul_ni</td>
+<td>I</td>
+<td>1</td>
+<td>tlul</td>
+<td>TLUL bus reference interface reset (active low)</td>
+</tr>
+<tr class="even">
+<td><strong>Register Access Interface</strong></td>
+<td></td>
+<td></td>
+<td></td>
+<td></td>
+</tr>
+<tr class="odd">
+<td>tlul</td>
+<td>I/O</td>
+<td>TBD</td>
+<td>tlul</td>
+<td>TLUL bus interface. Mainly used for configuration, calibration and trimming. At boot time, data is copied from non-volatile storage into AST registers by the SW boot entity. This interface has no further use beyond this point. Runtime interaction with AST is performed by other signals as described in this document.</td>
+</tr>
+<tr class="even">
+<td><strong>Analog modules</strong></td>
+<td></td>
+<td></td>
+<td></td>
+<td></td>
+</tr>
+<tr class="odd">
+<td>adc_a0_ai</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td>ADC analog input channels 0 to be measured.<br />
+Signal type is awire (see ana_pkg.sv)</td>
+</tr>
+<tr class="even">
+<td>adc_a1_ai</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td>ADC analog input channels 1 to be measured.<br />
+Signal type is awire (see ana_pkg.sv)</td>
+</tr>
+<tr class="odd">
+<td>adc_d_o</td>
+<td>O</td>
+<td>10</td>
+<td>adc</td>
+<td>ADC digital data</td>
+</tr>
+<tr class="even">
+<td>adc_chnsel_i</td>
+<td>I</td>
+<td>2</td>
+<td>adc</td>
+<td>ADC input channel select (one hot). No more than one channel should be selected at a time. Any change in ‘adc_chnsel_i’ value must go through all ‘0’. Changing ‘adc_chnsel_i’ from ‘0’ value to non-’0’ value starts an ADC conversion.</td>
+</tr>
+<tr class="odd">
+<td>adc_d_val_o</td>
+<td>O</td>
+<td>1</td>
+<td>adc</td>
+<td>ADC digital data valid</td>
+</tr>
+<tr class="even">
+<td>adc_pd_i</td>
+<td>I</td>
+<td>1</td>
+<td>adc</td>
+<td>ADC power down - for saving power during deep-sleep state between measurements. When this signal is high, ADC module is in off state, otherwise, it is in active state. A setup time of TBD must be provided from activating ADC until performing a measurement (by asserting one of adc_cs signals)</td>
+</tr>
+<tr class="odd">
+<td>entropy_req_o</td>
+<td>O</td>
+<td>1</td>
+<td>es</td>
+<td>Request entropy from CSRNG</td>
+</tr>
+<tr class="even">
+<td>entropy_ack_i</td>
+<td>I</td>
+<td>1</td>
+<td>es</td>
+<td>CSRNG entropy request acknowledge</td>
+</tr>
+<tr class="odd">
+<td>entropy_i</td>
+<td>I</td>
+<td>1</td>
+<td>es</td>
+<td>Random input from chip level.</td>
+</tr>
+<tr class="even">
+<td>rng_en_i</td>
+<td>I</td>
+<td>1</td>
+<td>rng</td>
+<td>Input from controller to enable RNG</td>
+</tr>
+<tr class="odd">
+<td>rng_val_o</td>
+<td>O</td>
+<td>1</td>
+<td>rng</td>
+<td>RNG bit valid. This is a per-transaction valid. rng_b_o can be sampled whenever this bit is high.</td>
+</tr>
+<tr class="even">
+<td>rng_b_o</td>
+<td>O</td>
+<td>4</td>
+<td>rng</td>
+<td>RNG digital bit streams. The downstream controller of this signal should sample at the rates of 200 KHz / 100KHz / 50KHz / 25KHz / 12.5KHz (50 KHz is the target, the rest are for fallback and upside).</td>
+</tr>
+<tr class="odd">
+<td><strong>Countermeasures and Alerts</strong></td>
+<td></td>
+<td></td>
+<td></td>
+<td></td>
+</tr>
+<tr class="even">
+<td>as_alert_po/no</td>
+<td>O</td>
+<td>2</td>
+<td>alert</td>
+<td>Active shield alert</td>
+</tr>
+<tr class="odd">
+<td>as_alert_ack_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>single pulse ack, source and destination assumed to be synchronous</td>
+</tr>
+<tr class="even">
+<td>as_alert_trig_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>Alert force trigger by software - connected to a chip register</td>
+</tr>
+<tr class="odd">
+<td>cg_alert_po/no</td>
+<td>O</td>
+<td>2</td>
+<td>alert</td>
+<td>Clock glitch detector alert</td>
+</tr>
+<tr class="even">
+<td>cg_alert_ack_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>single pulse ack, source and destination assumed to be synchronous</td>
+</tr>
+<tr class="odd">
+<td>cg_alert_trig_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>Alert force trigger by software - connected to a chip register</td>
+</tr>
+<tr class="even">
+<td>gd_alert_po/no</td>
+<td>O</td>
+<td>2</td>
+<td>alert</td>
+<td>Voltage glitch detector alert</td>
+</tr>
+<tr class="odd">
+<td>gd_alert_ack_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>single pulse ack, source and destination assumed to be synchronous</td>
+</tr>
+<tr class="even">
+<td>gd_alert_trig_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>Alert force trigger by software - connected to a chip register</td>
+</tr>
+<tr class="odd">
+<td>ts_alert_hi_po/no</td>
+<td>O</td>
+<td>2</td>
+<td>alert</td>
+<td>Temperature sensor alert for high temperature band</td>
+</tr>
+<tr class="even">
+<td>ts_alert_hi_ack_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>single pulse ack, source and destination assumed to be synchronous</td>
+</tr>
+<tr class="odd">
+<td>ts_alert_hi_trig_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>Alert force trigger by software - connected to a chip register</td>
+</tr>
+<tr class="even">
+<td>ts_alert_lo_po/no</td>
+<td>O</td>
+<td>2</td>
+<td>alert</td>
+<td>Temperature sensor alert for low temperature band</td>
+</tr>
+<tr class="odd">
+<td>ts_alert_lo_ack_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>single pulse ack, source and destination assumed to be synchronous</td>
+</tr>
+<tr class="even">
+<td>ts_alert_lo_trig_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>Alert force trigger by software - connected to a chip register</td>
+</tr>
+<tr class="odd">
+<td>ls_alert_po/no</td>
+<td>O</td>
+<td>2</td>
+<td>alert</td>
+<td>Light sensor alert (TBD)</td>
+</tr>
+<tr class="even">
+<td>ls_alert_ack_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>single pulse ack, source and destination assumed to be synchronous</td>
+</tr>
+<tr class="odd">
+<td>ls_alert_trig_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>Alert force trigger by software - connected to a chip register</td>
+</tr>
+<tr class="even">
+<td>ot_alert_po/no</td>
+<td>O</td>
+<td>TBD</td>
+<td>alert</td>
+<td>Other alerts (TBD)</td>
+</tr>
+<tr class="odd">
+<td>ot_alert_ack_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>single pulse ack, source and destination assumed to be synchronous</td>
+</tr>
+<tr class="even">
+<td>ot_alert_trig_i</td>
+<td>I</td>
+<td>1</td>
+<td>alert</td>
+<td>Alert force trigger by software - connected to a chip register</td>
+</tr>
+<tr class="odd">
+<td><strong>Trimming Test and Debug</strong></td>
+<td></td>
+<td></td>
+<td></td>
+<td></td>
+</tr>
+<tr class="even">
+<td>scan_mode_i</td>
+<td>I</td>
+<td>1</td>
+<td></td>
+<td>Scan mode indication signal. Controllable only when DFT features are enabled (Test and RMA states). Otherwise, these signals are grounded to 0.</td>
+</tr>
+<tr class="odd">
+<td>scan_reset_ni</td>
+<td>I</td>
+<td>1</td>
+<td></td>
+<td>Scan reset</td>
+</tr>
+<tr class="even">
+<td>clk_ast_ext_i</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td><p>External clock. While AST generates most of its clocks on-die, it still needs an external clock for clock calibration and first flash/OTP programming.</p>
+<p>Clock calibration: AST clock sources are inaccurate by default and must be calibrated prior to use. The results of the calibration are stored in <a href="https://github.com/lowRISC/opentitan/tree/master/hw/ip/otp_ctrl"><u>OTP</u></a> and reloaded by software upon system boot.</p>
+<p>First Flash / OTP programming: AST clock sources are inaccurate by default and may be out of range for initial flash and OTP programming. In this situation, an external clock may be required for initial programming such that a software image can be loaded to calibrate clocks and advance <a href="https://docs.opentitan.org/doc/security/"><u>life cycle</u></a>.</p></td>
+</tr>
+<tr class="odd">
+<td>vcc_supp_i</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td>VCC Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant ‘1’ and will be disconnected inside the AST.</td>
+</tr>
+<tr class="even">
+<td>vcmain_supp_i</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td>VCMAIN Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant ‘1’ and will be disconnected inside the AST.</td>
+</tr>
+<tr class="odd">
+<td>vcaon_supp_i</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td>VCAON Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant ‘1’ and will be disconnected inside the AST.</td>
+</tr>
+<tr class="even">
+<td>vioa_supp_i</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td>VIOA Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant ‘1’ and will be disconnected inside the AST.</td>
+</tr>
+<tr class="odd">
+<td>viob_supp_i</td>
+<td>I</td>
+<td>1</td>
+<td>async</td>
+<td>VIOB Supply Test. (supply indication for DV purposes). In FPGA Verilog view, the respective POK signal follows this signal. In other Verilog views this signal should be connected to constant ‘1’ and will be disconnected inside the AST.</td>
+</tr>
+<tr class="even">
+<td>ast2pad_a_io</td>
+<td>I/O</td>
+<td>TBD</td>
+<td>async</td>
+<td>Analog debug signals. These signals should be connected directly to chip PADs. They can share PADs with functional signals but when they are used for their analog debug function, the functional I/O must be in tri-state.</td>
+</tr>
+<tr class="odd">
+<td>padmux2ast_i</td>
+<td>I</td>
+<td>TBD</td>
+<td>async</td>
+<td>Digital debug input signals (routed to pin mux). These signals are controllable only when DFT features are enabled (Test and RMA states). Otherwise, these signals are grounded to 0.</td>
+</tr>
+<tr class="even">
+<td>ast2padmux_o</td>
+<td>O</td>
+<td>TBD</td>
+<td>async</td>
+<td>Digital debug output signals (routed to pin mux). These signals are only outputted when DFT features are enabled (Test and RMA states). Otherwise, these signals are grounded to 0.</td>
+</tr>
+<tr class="odd">
+<td>usb_io_cal_o</td>
+<td>O</td>
+<td>32</td>
+<td>async</td>
+<td>USB I/O calibration and trimming</td>
+</tr>
+<tr class="even">
+<td>lc_root_clk_byp_i</td>
+<td>I</td>
+<td>4</td>
+<td>async</td>
+<td><p>External clock mux override for OTP bootstrap purposes. When this bit is set, clk_ast_ext_i serves as the io_clk clock root.</p>
+<p>Signal type is lc_tx_t (see lc_ctl_pkg.sv)</p>
+<p>On = 4'b1010; Off = 4'b0101</p>
+<p>Note: When ‘On’, clk_src_io_o clock max frequency is limited to 50 MHz</p></td>
+</tr>
+<tr class="odd">
+<td>lc_dft_en_i</td>
+<td>I</td>
+<td>4</td>
+<td>async</td>
+<td><p>DFT enable.</p>
+<p>Signal type is lc_tx_t (see lc_ctl_pkg.sv)</p>
+<p>On = 4'b1010; Off = 4'b0101</p></td>
+</tr>
+</tbody>
+</table>
+
+# Interfaces Description Note
+
+The information below augments the [<u>Interface Signals
+Table</u>](#interface-signals-table). For further details, see the
+corresponding signals description in the table.
+
+# Power Connectivity
+
+Note: Power signals may not appear in the verilog files, however, they
+are described for completeness.
+
+## External Supplies
+
+AST has four external power supplies VCC, AVCC, VIOA and VIOB. VCC is
+the main supply, AVCC is an analog VCC supply. VIOA and VIOB are two
+additional I/O supplies.
+
+## Core Supplies
+
+The core supplies are generated from the VCC supply. These are two core
+supply domains: VCMAIN and VCAON. VCAON, as its name implies, is the
+always on core supply used to power components that stay active during
+device low power states. VCMAIN on the other hand, powers most chip
+logic such as RISC-V processor, crypto modules and almost all memories
+and peripherals. The VCMAIN supply can be turned off when requested,
+VCAON on the other hand, is active whenever VCC is active. AST core
+logic is powered by VCAON.
+
+# Power Control and Reset
+
+## Core Power Control and Indication
+
+VCMAIN is the only supply that can be directly influenced by OpenTitan.
+The power manager can request VCMAIN to shutdown through main\_pd\_n.
+The state of VCMAIN is reflected by the vcmain\_pok\_o signal.
+
+## IO Power Indication
+
+IO power state is reflected to OpenTitan by vioa\_pok\_o and
+viob\_pok\_o signals
+
+## Main (VCC) Power Detection and Flash Protection
+
+On VCC power-down detection, ‘flash\_power\_ready\_h\_o’,
+‘vcaon\_pok\_o’ and ‘vcmain\_pok\_o’ are immediately negated. This
+means that negation of the VCC supply always triggers the flash
+brown-out (BOR) protection circuitry.
+
+When entering deep-sleep mode, ‘flash\_power\_down\_h\_o’ is asserted
+before negating VCMAIN until VCMAIN is back up.
+
+## Resets
+
+The AST supports the generation of the root reset for the reset manager.
+It is driven by ‘vcaon\_pok\_o’ which is generated inside AST. The
+‘vcaon\_pok\_o’ is activated when the following conditions are met:
+VCC is detected, internal voltage regulator is active and ‘por\_ni’
+reset input is inactive. ‘por\_ni’ is driven by an external chip reset
+pin. The following table and diagrams describe the AST sub-modules
+resets.
+
+<table>
+<thead>
+<tr class="header">
+<th><strong>Components</strong></th>
+<th><strong>Reset by</strong></th>
+<th><strong>Comments</strong></th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td>Regulators, ‘power-OK’ logic and always-on clock</td>
+<td>self-restart / tlul-reset**</td>
+<td><p>tlul-reset is driven by ‘rst_ast_tlul_ni’ signal.</p>
+<p>‘tlul-reset**’ means that in this case, it does not cause a full restart, but calibration and trimming values are lost. The affected module is designed to withstand such loss of calibration without causing harmful transition effects. However, from that point, the module is in its default uncalibrated configuration until re-calibrated by the boot code (as in regular boot).</p>
+<p>When uncalibrated, the always-on clock frequency is 200 kHz ~+/-30% (TBD)</p></td>
+</tr>
+<tr class="even">
+<td>Calibration trimming and other registers</td>
+<td>tlul-reset</td>
+<td></td>
+</tr>
+<tr class="odd">
+<td>System/USB/IO clock generators</td>
+<td>vcmain_pok_o / tlul-reset**</td>
+<td><p>vcmain_pok_o is also fed by vcaon_pok_o and por_ni.</p>
+<p>After reset, clocks are not calibrated and have no jitter until configured by the booter. Until that point, their clock frequency range is -10% ~ -60% (TBD) of the target frequency.</p></td>
+</tr>
+<tr class="even">
+<td>Other interface functions</td>
+<td>Input reset / tlul-reset**</td>
+<td>Per the corresponding interface <a href="#clock-reset-inputs"><u>clock domain reset input</u></a>.</td>
+</tr>
+</tbody>
+</table>
+
+
+
+# Clock Outputs
+
+AST generates four clocks: System clock, IO clock, USB clock and
+Always-on clock. Most clocks have ‘enable’ inputs and a corresponding
+‘valid’ output. When the enable is de-asserted, the corresponding
+clock stops and valid is dropped to 0. When the enable is asserted, the
+clocks begin outputting in a “glitchless” manner and the valid is raised
+to 1. Unless noted otherwise, clocks duty cycle is 50% +/-5%.
+
+The OpenTitan power and clock managers are responsible for manipulating
+the enables and observing the valids to know when clocks can be safely
+released to the system.
+
+## USB Clock Calibration
+
+The USB clock requires an accuracy that cannot be achieved by the AST
+clocks natively. As a result, information from USB frames are used to
+[<u>calibrate the
+clock</u>](https://github.com/lowRISC/opentitan/blob/master/hw/ip/usbdev/doc/_index.md#clocking).
+
+# Clock & Reset Inputs
+
+The root clocks and resets are generated inside AST. However, the clocks
+go through gating and optional division in the OpenTitan top level and
+propagate back into AST as feedback clocks, each with associated
+synchronized reset to ensure it can synchronize with the various
+comportable modules. The input resets are used for the different AST
+interface functions. For further details about AST resets, see
+[<u>Resets</u>](#resets) section.
+
+Note: There are several reason for routing leaf clocks back into AST
+instead of using the root clocks directly
+
+ - The leaf clocks may be divided down from the root clock and that
+ frequency is used to drive the interface. For example,
+ clk\_src\_io\_clk\_o is 96MHz, but comportable modules use either
+ 48MHz or 24MHz.
+
+ - The leaf clocks and root clocks have very different clock tree
+ depths and may be difficult for timing closure if they interacted
+ directly.
+
+ - Decouple AST internal design from OpenTitan top-level interfaces
+ clock and reset selection.
+
+# Register Access Interface
+
+AST registers can be accessed via TL-UL interface. These registers are
+used for test and calibration purposes and are not required for runtime
+operation. See the [<u>Interface Signals
+Table</u>](#interface-signals-table) for more details.
+
+# ADC
+
+AST contains an analog to digital converter that can be used to sample
+various input signals. For OpenTitan this will primarily be used for
+[<u>debug cable detection</u>](https://www.sparkfun.com/products/14746).
+To activate the ADC, the corresponding comportable module must first
+select the channel to sample, and then activate the ADC through
+\`adc\_pd\_i\`. Once activated, the ADC will produce an output
+synchronous to the adc controller.
+
+## ADC Usage Flow
+
+1. Activate the ADC by negating ‘adc\_pd\_i’
+
+2. Wait 30 uS for the ADC to wake up.
+
+3. Select an analog channel to measure by setting the corresponding
+ bit in ‘adc\_chnsel\_i’ bus. This triggers a measurement.
+
+4. Wait unitl ‘adc\_d\_val’ is set and read the result via
+ ‘adc\_d\_o’
+
+5. Clear ‘adc\_chnsel\_i’ bus to 0. Note that adc\_chnsel must be
+ cleared to 0 before a new channel is selected.
+
+6. Repeat steps 3-5 if more channels or more measurements are
+ required
+
+7. Deactivate the ADC by setting ‘adc\_pd’ to save power.
+
+{{< wavejson >}}
+{
+ signal: [
+ {node: '.a..b........', phase:0.2},
+ {name: 'adc_pd_i' , wave: '10|..|.....|....|..1'},
+ {name: 'clk_ast_adc_i', wave: 'p.|..|.....|....|...'},
+ {name: 'adc_chnsel_i' , wave: '0.|.3|..04.|....|0..'},
+ {name: 'adc_d_val_o' , wave: '0.|..|.1.0.|.1..|.0.'},
+ {name: 'adc_d_o' , wave: 'x.|..|.3.x.|.4..|.x.', data: ['ch0', 'ch1', 'ch1']},
+ ],
+
+ edge: [ 'a<->b wakeup time', ]
+}
+{{< /wavejson >}}
+
+# Random Number Generator
+
+AST contains a random number generator that outputs random number
+bitstreams whenever it is enabled. After enabled by the [<u>comportable
+controller</u>](https://github.com/lowRISC/opentitan/blob/master/hw/ip/entropy_src/doc/_index.md)
+through ‘rng\_en\_i’, the AST begins generating multiple independent
+four random bit streams. rng\_b\_o bit streams are valid and can be
+sampled whenever \`rng\_val\_o\` is asserted according to the following
+diagram.
+
+{{< wavejson >}}
+{
+ signal: [
+ {name: 'clk', wave: 'p.|......|......|......'},
+ {name: 'rng_en', wave: '01|......|......|......'},
+ {name: 'rng_valid', wave: '0.|10....|10....|10....'},
+ {name: 'rng_b', wave: 'x.|3.....|4.....|5.....', data: ['es0', 'es1', 'es2']},
+ ]
+}
+{{< /wavejson >}}
+
+The expected rng\_b\_o valid output rate is about 50KHz.
+
+# Entropy Consumption
+
+AST consumes entropy for defensive purposes. However, AST does not
+consume its raw entropy directly. Instead, AST receives entropy from the
+CSRNG. The details of this interface are still under discussion.
+
+
+{{< wavejson >}}
+{
+ signal: [
+ {name: 'clk_ast_es_i' , wave: 'p.|..........'},
+ {name: 'entropy_req_o' , wave: '01|.0.1.....0'},
+ {name: 'entropy_ack_i' , wave: '0.|10.1.01..0'},
+ {name: 'entropy_i', wave: 'xx|2x.22x222x'},
+ ]
+}
+{{< /wavejson >}}
+
+# Countermeasures and Alerts
+
+## Alert Events
+
+AST’s sensors and detectors, when triggered, output alert events to a
+sensor controller. The event signals are level until acknowledged by the
+controller. Further, the events are differentially encoded to ensure
+they cannot be hard-wired or faulted to either ‘1’ or ‘0’.
+
+Inside the sensor controller, the events are then converted into alerts
+as part of the wider [<u>OpenTitan alert handling
+system</u>](https://github.com/lowRISC/opentitan/blob/master/hw/ip/alert_handler/doc/_index.md).
+
+## Alert Signaling
+
+Outgoing alert events are level. Incoming event ack signals clear the
+alert event (similar to an interrupt). Outgoing alert events should be
+OR'd inside the sensor or power manager (depending on what level of deep
+sleep support is needed) to generate wakeup, that way AST does not need
+to do any additional handling for wakeups during low power mode.
+
+## Countermeasures
+
+Most countermeasure enablement is controlled by Nuvoton via the
+registers interface. Clock jitter is an exception because there is a
+reasoning for dynamically turning it on and off (security/performance
+tradeoff). Unless stated otherwise, countermeasures are active in all
+modes but deep-sleep.
diff --git a/hw/top_sencha/ip/ast/doc/ast_regs.html b/hw/top_sencha/ip/ast/doc/ast_regs.html
new file mode 100644
index 0000000..9b76874
--- /dev/null
+++ b/hw/top_sencha/ip/ast/doc/ast_regs.html
@@ -0,0 +1,773 @@
+<style>
+ table.regpic {
+ width: 95%;
+ border-collapse: collapse;
+ margin-left:auto;
+ margin-right:auto;
+ table-layout:fixed;
+ }
+ table.regdef {
+ border: 1px solid black;
+ width: 80%;
+ border-collapse: collapse;
+ margin-left:auto;
+ margin-right:auto;
+ table-layout:auto;
+ }
+ table.regdef th {
+ border: 1px solid black;
+ font-family: sans-serif;
+ }
+ td.bitnum {
+ font-size: 60%;
+ text-align: center;
+ }
+ td.unused {
+ border: 1px solid black;
+ background-color: gray;
+ }
+ td.fname {
+ border: 1px solid black;
+ text-align: center;
+ font-family: sans-serif;
+ }
+ td.regbits, td.regperm, td.regrv, td.regfn {
+ border: 1px solid black;
+ text-align: center;
+ font-family: sans-serif;
+ }
+ td.regde {
+ border: 1px solid black;
+ }
+ table.cfgtable {
+ border: 1px solid black;
+ width: 80%;
+ border-collapse: collapse;
+ margin-left:auto;
+ margin-right:auto;
+ table-layout:auto;
+ }
+ table.cfgtable th {
+ border: 1px solid black;
+ font-family: sans-serif;
+ font-weight: bold;
+ }
+ table.cfgtable td {
+ border: 1px solid black;
+ font-family: sans-serif;
+ }
+ p {
+ color: blue;
+ font-size: 16px;
+ }
+</style>
+<table class="regdef" id="RegSummary_{comp}">
+ <tr>
+ <th class="regdef" colspan=4> Summary </th>
+ </tr>
+ <tr>
+ <th class="regdef">Name</th> <th class="regdef">Offset</th> <th class="regdef">Length</th> <th class="regdef">Description</th> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega0">REGA0</a></td> <td class="regfn">0x0</td> <td class="regfn">4</td> <td class="regfn"><p>AST Register 0 for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega1">REGA1</a></td> <td class="regfn">0x4</td> <td class="regfn">4</td> <td class="regfn"><p>AST 1 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega2">REGA2</a></td> <td class="regfn">0x8</td> <td class="regfn">4</td> <td class="regfn"><p>AST 2 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega3">REGA3</a></td> <td class="regfn">0xc</td> <td class="regfn">4</td> <td class="regfn"><p>AST 3 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega4">REGA4</a></td> <td class="regfn">0x10</td> <td class="regfn">4</td> <td class="regfn"><p>AST 4 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega5">REGA5</a></td> <td class="regfn">0x14</td> <td class="regfn">4</td> <td class="regfn"><p>AST 5 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega6">REGA6</a></td> <td class="regfn">0x18</td> <td class="regfn">4</td> <td class="regfn"><p>AST 6 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega7">REGA7</a></td> <td class="regfn">0x1c</td> <td class="regfn">4</td> <td class="regfn"><p>AST 7 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega8">REGA8</a></td> <td class="regfn">0x20</td> <td class="regfn">4</td> <td class="regfn"><p>AST 8 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega9">REGA9</a></td> <td class="regfn">0x24</td> <td class="regfn">4</td> <td class="regfn"><p>AST 9 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega10">REGA10</a></td> <td class="regfn">0x28</td> <td class="regfn">4</td> <td class="regfn"><p>AST 10 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega11">REGA11</a></td> <td class="regfn">0x2c</td> <td class="regfn">4</td> <td class="regfn"><p>AST 11 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega12">REGA12</a></td> <td class="regfn">0x30</td> <td class="regfn">4</td> <td class="regfn"><p>AST 13 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega13">REGA13</a></td> <td class="regfn">0x34</td> <td class="regfn">4</td> <td class="regfn"><p>AST 13 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega14">REGA14</a></td> <td class="regfn">0x38</td> <td class="regfn">4</td> <td class="regfn"><p>AST 14 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega15">REGA15</a></td> <td class="regfn">0x3c</td> <td class="regfn">4</td> <td class="regfn"><p>AST 15 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega16">REGA16</a></td> <td class="regfn">0x40</td> <td class="regfn">4</td> <td class="regfn"><p>AST 16 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega17">REGA17</a></td> <td class="regfn">0x44</td> <td class="regfn">4</td> <td class="regfn"><p>AST 17 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega18">REGA18</a></td> <td class="regfn">0x48</td> <td class="regfn">4</td> <td class="regfn"><p>AST 18 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega19">REGA19</a></td> <td class="regfn">0x4c</td> <td class="regfn">4</td> <td class="regfn"><p>AST 19 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega20">REGA20</a></td> <td class="regfn">0x50</td> <td class="regfn">4</td> <td class="regfn"><p>AST 20 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega21">REGA21</a></td> <td class="regfn">0x54</td> <td class="regfn">4</td> <td class="regfn"><p>AST 21 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega22">REGA22</a></td> <td class="regfn">0x58</td> <td class="regfn">4</td> <td class="regfn"><p>AST 22 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega23">REGA23</a></td> <td class="regfn">0x5c</td> <td class="regfn">4</td> <td class="regfn"><p>AST 23 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega24">REGA24</a></td> <td class="regfn">0x60</td> <td class="regfn">4</td> <td class="regfn"><p>AST 24 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega25">REGA25</a></td> <td class="regfn">0x64</td> <td class="regfn">4</td> <td class="regfn"><p>AST 25 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega26">REGA26</a></td> <td class="regfn">0x68</td> <td class="regfn">4</td> <td class="regfn"><p>AST 26 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega27">REGA27</a></td> <td class="regfn">0x6c</td> <td class="regfn">4</td> <td class="regfn"><p>AST 27 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega28">REGA28</a></td> <td class="regfn">0x70</td> <td class="regfn">4</td> <td class="regfn"><p>AST 28 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega29">REGA29</a></td> <td class="regfn">0x74</td> <td class="regfn">4</td> <td class="regfn"><p>AST 29 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega30">REGA30</a></td> <td class="regfn">0x78</td> <td class="regfn">4</td> <td class="regfn"><p>AST 30 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega31">REGA31</a></td> <td class="regfn">0x7c</td> <td class="regfn">4</td> <td class="regfn"><p>AST 31 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega32">REGA32</a></td> <td class="regfn">0x80</td> <td class="regfn">4</td> <td class="regfn"><p>AST 32 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega33">REGA33</a></td> <td class="regfn">0x84</td> <td class="regfn">4</td> <td class="regfn"><p>AST 33 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega34">REGA34</a></td> <td class="regfn">0x88</td> <td class="regfn">4</td> <td class="regfn"><p>AST 34 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega35">REGA35</a></td> <td class="regfn">0x8c</td> <td class="regfn">4</td> <td class="regfn"><p>AST 35 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega36">REGA36</a></td> <td class="regfn">0x90</td> <td class="regfn">4</td> <td class="regfn"><p>AST 36 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_rega37">REGA37</a></td> <td class="regfn">0x94</td> <td class="regfn">4</td> <td class="regfn"><p>AST 37 Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_regal">REGAL</a></td> <td class="regfn">0x98</td> <td class="regfn">4</td> <td class="regfn"><p>AST Last Register for OTP/ROM Write Testing</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_regb_0">REGB_0</a></td> <td class="regfn">0x200</td> <td class="regfn">4</td> <td class="regfn"><p>AST Registers Array-B to set address space size</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_regb_1">REGB_1</a></td> <td class="regfn">0x204</td> <td class="regfn">4</td> <td class="regfn"><p>AST Registers Array-B to set address space size</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_regb_2">REGB_2</a></td> <td class="regfn">0x208</td> <td class="regfn">4</td> <td class="regfn"><p>AST Registers Array-B to set address space size</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_regb_3">REGB_3</a></td> <td class="regfn">0x20c</td> <td class="regfn">4</td> <td class="regfn"><p>AST Registers Array-B to set address space size</p></td> </tr>
+ <tr>
+ <td class="regfn">ast.<a href="#Reg_regb_4">REGB_4</a></td> <td class="regfn">0x210</td> <td class="regfn">4</td> <td class="regfn"><p>AST Registers Array-B to set address space size</p></td> </tr>
+</table><table class="regdef" id="Reg_rega0">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega0">REGA0</a> @ 0x0</div>
+ <div><p>AST Register 0 for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x0, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">ro</td><td class="regrv">0x0</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega1">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega1">REGA1</a> @ 0x4</div>
+ <div><p>AST 1 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x1, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">ro</td><td class="regrv">0x1</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega2">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega2">REGA2</a> @ 0x8</div>
+ <div><p>AST 2 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x2, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x2</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega3">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega3">REGA3</a> @ 0xc</div>
+ <div><p>AST 3 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x3, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x3</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega4">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega4">REGA4</a> @ 0x10</div>
+ <div><p>AST 4 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x4, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x4</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega5">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega5">REGA5</a> @ 0x14</div>
+ <div><p>AST 5 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x5, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x5</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega6">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega6">REGA6</a> @ 0x18</div>
+ <div><p>AST 6 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x6, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x6</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega7">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega7">REGA7</a> @ 0x1c</div>
+ <div><p>AST 7 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x7, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x7</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega8">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega8">REGA8</a> @ 0x20</div>
+ <div><p>AST 8 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x8, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x8</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega9">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega9">REGA9</a> @ 0x24</div>
+ <div><p>AST 9 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x9, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x9</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega10">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega10">REGA10</a> @ 0x28</div>
+ <div><p>AST 10 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0xa, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0xa</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega11">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega11">REGA11</a> @ 0x2c</div>
+ <div><p>AST 11 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0xb, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0xb</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega12">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega12">REGA12</a> @ 0x30</div>
+ <div><p>AST 13 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0xc, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0xc</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega13">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega13">REGA13</a> @ 0x34</div>
+ <div><p>AST 13 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0xd, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0xd</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega14">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega14">REGA14</a> @ 0x38</div>
+ <div><p>AST 14 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0xe, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0xe</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega15">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega15">REGA15</a> @ 0x3c</div>
+ <div><p>AST 15 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0xf, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0xf</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega16">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega16">REGA16</a> @ 0x40</div>
+ <div><p>AST 16 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x10, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x10</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega17">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega17">REGA17</a> @ 0x44</div>
+ <div><p>AST 17 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x11, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x11</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega18">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega18">REGA18</a> @ 0x48</div>
+ <div><p>AST 18 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x12, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x12</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega19">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega19">REGA19</a> @ 0x4c</div>
+ <div><p>AST 19 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x13, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x13</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega20">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega20">REGA20</a> @ 0x50</div>
+ <div><p>AST 20 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x14, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x14</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega21">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega21">REGA21</a> @ 0x54</div>
+ <div><p>AST 21 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x15, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x15</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega22">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega22">REGA22</a> @ 0x58</div>
+ <div><p>AST 22 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x16, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x16</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega23">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega23">REGA23</a> @ 0x5c</div>
+ <div><p>AST 23 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x17, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x17</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega24">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega24">REGA24</a> @ 0x60</div>
+ <div><p>AST 24 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x18, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x18</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega25">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega25">REGA25</a> @ 0x64</div>
+ <div><p>AST 25 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x19, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x19</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega26">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega26">REGA26</a> @ 0x68</div>
+ <div><p>AST 26 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x1a, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x1a</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega27">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega27">REGA27</a> @ 0x6c</div>
+ <div><p>AST 27 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x1b, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x1b</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega28">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega28">REGA28</a> @ 0x70</div>
+ <div><p>AST 28 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x1c, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">ro</td><td class="regrv">0x1c</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega29">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega29">REGA29</a> @ 0x74</div>
+ <div><p>AST 29 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x1d, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x1d</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega30">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega30">REGA30</a> @ 0x78</div>
+ <div><p>AST 30 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x1e, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x1e</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega31">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega31">REGA31</a> @ 0x7c</div>
+ <div><p>AST 31 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x1f, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x1f</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega32">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega32">REGA32</a> @ 0x80</div>
+ <div><p>AST 32 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x20, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x20</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega33">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega33">REGA33</a> @ 0x84</div>
+ <div><p>AST 33 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x21, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x21</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega34">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega34">REGA34</a> @ 0x88</div>
+ <div><p>AST 34 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x22, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x22</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega35">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega35">REGA35</a> @ 0x8c</div>
+ <div><p>AST 35 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x23, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x23</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega36">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega36">REGA36</a> @ 0x90</div>
+ <div><p>AST 36 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x24, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x24</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_rega37">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_rega37">REGA37</a> @ 0x94</div>
+ <div><p>AST 37 Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x25, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x25</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_regal">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_regal">REGAL</a> @ 0x98</div>
+ <div><p>AST Last Register for OTP/ROM Write Testing</p></div>
+ <div>Reset default = 0x26, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">wo</td><td class="regrv">0x26</td><td class="regfn">reg32</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_regb_0">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_regb_0">REGB_0</a> @ 0x200</div>
+ <div><p>AST Registers Array-B to set address space size</p></div>
+ <div>Reset default = 0x0, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32_0...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32_0</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">reg32_0</td><td class="regde"><p><p>32-bit Register</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_regb_1">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_regb_1">REGB_1</a> @ 0x204</div>
+ <div><p>AST Registers Array-B to set address space size</p></div>
+ <div>Reset default = 0x0, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32_1...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32_1</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">reg32_1</td><td class="regde"><p><p>For REGB1</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_regb_2">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_regb_2">REGB_2</a> @ 0x208</div>
+ <div><p>AST Registers Array-B to set address space size</p></div>
+ <div>Reset default = 0x0, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32_2...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32_2</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">reg32_2</td><td class="regde"><p><p>For REGB2</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_regb_3">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_regb_3">REGB_3</a> @ 0x20c</div>
+ <div><p>AST Registers Array-B to set address space size</p></div>
+ <div>Reset default = 0x0, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32_3...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32_3</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">reg32_3</td><td class="regde"><p><p>For REGB3</p></p></td></table>
+<br>
+<table class="regdef" id="Reg_regb_4">
+ <tr>
+ <th class="regdef" colspan=5>
+ <div>ast.<a href="#Reg_regb_4">REGB_4</a> @ 0x210</div>
+ <div><p>AST Registers Array-B to set address space size</p></div>
+ <div>Reset default = 0x0, mask 0xffffffff</div>
+ </th>
+ </tr>
+<tr><td colspan=5><table class="regpic"><tr><td class="bitnum">31</td><td class="bitnum">30</td><td class="bitnum">29</td><td class="bitnum">28</td><td class="bitnum">27</td><td class="bitnum">26</td><td class="bitnum">25</td><td class="bitnum">24</td><td class="bitnum">23</td><td class="bitnum">22</td><td class="bitnum">21</td><td class="bitnum">20</td><td class="bitnum">19</td><td class="bitnum">18</td><td class="bitnum">17</td><td class="bitnum">16</td></tr><tr><td class="fname" colspan=16>reg32_4...</td>
+</tr>
+<tr><td class="bitnum">15</td><td class="bitnum">14</td><td class="bitnum">13</td><td class="bitnum">12</td><td class="bitnum">11</td><td class="bitnum">10</td><td class="bitnum">9</td><td class="bitnum">8</td><td class="bitnum">7</td><td class="bitnum">6</td><td class="bitnum">5</td><td class="bitnum">4</td><td class="bitnum">3</td><td class="bitnum">2</td><td class="bitnum">1</td><td class="bitnum">0</td></tr><tr><td class="fname" colspan=16>...reg32_4</td>
+</tr></table></td></tr>
+<tr><th width=5%>Bits</th><th width=5%>Type</th><th width=5%>Reset</th><th>Name</th><th>Description</th></tr><tr><td class="regbits">31:0</td><td class="regperm">rw</td><td class="regrv">0x0</td><td class="regfn">reg32_4</td><td class="regde"><p><p>For REGB4</p></p></td></table>
+<br>
diff --git a/hw/top_sencha/ip/ast/doc/media/image4.png b/hw/top_sencha/ip/ast/doc/media/image4.png
new file mode 100644
index 0000000..2b0d5f7
--- /dev/null
+++ b/hw/top_sencha/ip/ast/doc/media/image4.png
Binary files differ
diff --git a/hw/top_sencha/ip/ast/doc/media/image5.png b/hw/top_sencha/ip/ast/doc/media/image5.png
new file mode 100644
index 0000000..6fbe3c8
--- /dev/null
+++ b/hw/top_sencha/ip/ast/doc/media/image5.png
Binary files differ
diff --git a/hw/top_sencha/ip/ast/doc/top_diagram.png b/hw/top_sencha/ip/ast/doc/top_diagram.png
new file mode 100644
index 0000000..6fbe3c8
--- /dev/null
+++ b/hw/top_sencha/ip/ast/doc/top_diagram.png
Binary files differ
diff --git a/hw/top_sencha/ip/ast/lib/ast.lib b/hw/top_sencha/ip/ast/lib/ast.lib
new file mode 100644
index 0000000..b00839d
--- /dev/null
+++ b/hw/top_sencha/ip/ast/lib/ast.lib
@@ -0,0 +1,98919 @@
+brary("ast") {
+
+ technology (cmos) ;
+ delay_model : table_lookup ;
+ library_features ( report_delay_calculation ) ;
+ date : "Mon Oct 3 13:12:25 2022" ;
+ revision : "P-2019.03-SP3" ;
+ nom_process : 1.000 ;
+ nom_voltage : 0.990 ;
+ nom_temperature : -40.000 ;
+ operating_conditions( "SSG0P99VN40C" ) {
+ process : 1.0000 ;
+ voltage : 0.9900 ;
+ temperature : -40.0000 ;
+ } /* current design opcond */
+ default_operating_conditions : "SSG0P99VN40C" ;
+ voltage_unit : "1V" ;
+ time_unit : "1ns" ;
+ capacitive_load_unit (1.000000, pf);
+ slew_derate_from_library : 0.5000 ;
+ slew_lower_threshold_pct_rise : 30.0000 ;
+ slew_lower_threshold_pct_fall : 30.0000 ;
+ slew_upper_threshold_pct_rise : 70.0000 ;
+ slew_upper_threshold_pct_fall : 70.0000 ;
+ input_threshold_pct_rise : 50.0000 ;
+ input_threshold_pct_fall : 50.0000 ;
+ output_threshold_pct_rise : 50.0000 ;
+ output_threshold_pct_fall : 50.0000 ;
+ k_process_cell_rise : 0.000000;
+ k_process_cell_fall : 0.000000;
+ k_volt_cell_rise : 0.000000;
+ k_volt_cell_fall : 0.000000;
+ k_temp_cell_rise : 0.000000;
+ k_temp_cell_fall : 0.000000;
+ k_process_rise_transition : 0.000000;
+ k_process_fall_transition : 0.000000;
+ k_volt_rise_transition : 0.000000;
+ k_volt_fall_transition : 0.000000;
+ k_temp_rise_transition : 0.000000;
+ k_temp_fall_transition : 0.000000;
+ default_fanout_load : 1.000000;
+ default_inout_pin_cap : 1.000000;
+ default_input_pin_cap : 1.000000;
+ default_output_pin_cap : 0.000000;
+ current_unit : 1mA;
+ pulling_resistance_unit : "1kohm";
+ comment : "PrimeTime extracted Model." ;
+
+ define(min_delay_flag, timing, boolean);
+ define(internal_noise_peak_time_below_high, pin, float);
+ define(internal_noise_width_above_low, pin, float);
+ define(original_pin, pin, string);
+ define(internal_noise_peak_time_above_low, pin, float);
+ define(internal_noise_width_below_high, pin, float);
+ define(internal_noise_height_above_low, pin, float);
+ define(internal_noise_height_below_high, pin, float);
+
+
+
+/* SCALAR table template is built-in */
+
+/* 2-D table template f(in_trans, out_cap) */
+lu_table_template( f_itrans_ocap ) {
+ variable_1 : input_net_transition;
+ variable_2 : total_output_net_capacitance;
+ index_1 (" 0.0000, 1.0000 ");
+ index_2 (" 0.0000, 1.0000 ");
+}
+
+/* 2-D table template f(d_trans, c_trans) */
+lu_table_template( f_dtrans_ctrans ) {
+ variable_1 : constrained_pin_transition;
+ variable_2 : related_pin_transition;
+ index_1 (" 0.0000, 1.0000 ");
+ index_2 (" 0.0000, 1.0000 ");
+}
+
+/* 3-D table template f(i_trans, o_cap, r_cap) */
+lu_table_template( f_itrans_ocap_rcap ) {
+ variable_1 : input_net_transition;
+ variable_2 : total_output_net_capacitance;
+ variable_3 : related_out_total_output_net_capacitance;
+ index_1 (" 0.0000, 1.0000 ");
+ index_2 (" 0.0000, 1.0000 ");
+ index_3 (" 0.0000, 1.0000 ");
+}
+
+type ( BUS109_type0 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 109 ;
+ bit_from : 108 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS66_type1 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 66 ;
+ bit_from : 65 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS27_type2 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 27 ;
+ bit_from : 26 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS56_type3 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 56 ;
+ bit_from : 55 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS5_type4 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 5 ;
+ bit_from : 4 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS2_type5 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 2 ;
+ bit_from : 1 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS4_type6 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 4 ;
+ bit_from : 3 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS20_type7 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 20 ;
+ bit_from : 19 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS10_type8 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 10 ;
+ bit_from : 9 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS34_type9 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 34 ;
+ bit_from : 33 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS1_type10 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 1 ;
+ bit_from : 0 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS52_type11 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 52 ;
+ bit_from : 51 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS26_type12 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 26 ;
+ bit_from : 25 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS3_type13 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 3 ;
+ bit_from : 2 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS8_type14 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 8 ;
+ bit_from : 7 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS12_type15 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 12 ;
+ bit_from : 11 ;
+ bit_to : 0 ;
+} /* end of type */
+type ( BUS9_type16 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 9 ;
+ bit_from : 8 ;
+ bit_to : 0 ;
+} /* end of type */
+
+cell( ast ) {
+ area : 751665.937500 ;
+ dont_use : true ;
+ dont_touch : true ;
+ interface_timing : true;
+ timing_model_type : "extracted";
+ is_macro_cell : true;
+
+short(tl_o[64], tl_o[63]);
+
+short(tl_o[64], tl_o[61]);
+
+short(tl_o[64], tl_o[60]);
+
+short(tl_o[64], tl_o[59]);
+
+short(tl_o[64], tl_o[48]);
+
+short(ast_pwst_o[3], ast_pwst_h_o[3]);
+
+short(ast_pwst_o[2], ast_pwst_h_o[2]);
+
+short(ast_pwst_o[1], ast_pwst_h_o[1]);
+
+short(ast_pwst_o[0], ast_pwst_h_o[0]);
+bus ( tl_i ) {
+
+ bus_type : BUS109_type0 ;
+ direction : input ;
+
+pin("tl_i[108]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001908 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[108];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.014905, 5.968750, 5.938533, 5.927176, 5.940784",\
+ "6.095888, 6.049733, 6.019516, 6.008159, 6.021767",\
+ "6.180377, 6.134222, 6.104005, 6.092648, 6.106256",\
+ "6.321913, 6.275758, 6.245541, 6.234183, 6.247791",\
+ "6.558708, 6.512553, 6.482336, 6.470979, 6.484587");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.829596, 4.783441, 4.753223, 4.741866, 4.755474",\
+ "4.919121, 4.872966, 4.842749, 4.831391, 4.844999",\
+ "5.021051, 4.974896, 4.944679, 4.933322, 4.946930",\
+ "5.203711, 5.157556, 5.127338, 5.115981, 5.129589",\
+ "5.532049, 5.485894, 5.455677, 5.444320, 5.457928");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[108]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.214260, -0.171883, -0.137304, -0.099668, 0.184188",\
+ "-0.301086, -0.258709, -0.224129, -0.186494, 0.097363",\
+ "-0.394315, -0.351937, -0.317358, -0.279723, 0.004134",\
+ "-0.557199, -0.514821, -0.480242, -0.442607, -0.158750",\
+ "-0.829713, -0.787336, -0.752757, -0.715121, -0.431265");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.264841, -0.198767, -0.140880, -0.098858, 0.121356",\
+ "-0.356827, -0.290753, -0.232866, -0.190843, 0.029370",\
+ "-0.463555, -0.397481, -0.339595, -0.297572, -0.077359",\
+ "-0.650171, -0.584097, -0.526210, -0.484188, -0.239846",\
+ "-0.884585, -0.842168, -0.807682, -0.768234, -0.461884");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[108]_hldr*/
+
+} /* end of pin tl_i[108] */
+
+pin("tl_i[107]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.005151 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[107];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.052649, 5.006495, 4.976278, 4.964921, 4.978528",\
+ "5.141132, 5.094977, 5.064761, 5.053403, 5.067011",\
+ "5.243252, 5.197097, 5.166880, 5.155523, 5.169130",\
+ "5.444744, 5.398589, 5.368372, 5.357015, 5.370623",\
+ "5.884084, 5.837929, 5.807712, 5.796355, 5.809962");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.045798, 4.999643, 4.969427, 4.958069, 4.971677",\
+ "5.140346, 5.094191, 5.063974, 5.052617, 5.066224",\
+ "5.268656, 5.222501, 5.192284, 5.180927, 5.194534",\
+ "5.518216, 5.472061, 5.441844, 5.430487, 5.444095",\
+ "5.954391, 5.908237, 5.878020, 5.866663, 5.880270");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[107]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.187805, -0.145419, -0.110860, -0.072826, 0.215981",\
+ "-0.265352, -0.222966, -0.188407, -0.150372, 0.138434",\
+ "-0.358696, -0.316325, -0.281731, -0.244378, 0.035979",\
+ "-0.536472, -0.494140, -0.459456, -0.423841, -0.165061",\
+ "-0.854036, -0.811811, -0.776879, -0.746068, -0.546918");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.171733, -0.105842, -0.048217, -0.006266, 0.214402",\
+ "-0.262898, -0.197007, -0.139383, -0.097431, 0.123236",\
+ "-0.377606, -0.311610, -0.253836, -0.211843, 0.008564",\
+ "-0.589409, -0.523083, -0.464836, -0.422715, -0.203127",\
+ "-0.959255, -0.892271, -0.833079, -0.790704, -0.572752");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[107]_hldr*/
+
+} /* end of pin tl_i[107] */
+
+pin("tl_i[106]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.004836 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[106];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.118081, 5.071926, 5.041709, 5.030352, 5.043960",\
+ "5.207886, 5.161731, 5.131514, 5.120157, 5.133764",\
+ "5.325253, 5.279098, 5.248881, 5.237524, 5.251131",\
+ "5.541330, 5.495175, 5.464959, 5.453601, 5.467209",\
+ "5.904454, 5.858299, 5.828083, 5.816725, 5.830333");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.110147, 5.063992, 5.033775, 5.022418, 5.036025",\
+ "5.198250, 5.152095, 5.121878, 5.110521, 5.124128",\
+ "5.332071, 5.285916, 5.255700, 5.244342, 5.257950",\
+ "5.577984, 5.531829, 5.501612, 5.490255, 5.503862",\
+ "5.995383, 5.949228, 5.919012, 5.907654, 5.921262");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[106]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.198447, -0.132584, -0.074998, -0.033057, 0.187678",\
+ "-0.296196, -0.230332, -0.172747, -0.130806, 0.089930",\
+ "-0.398836, -0.332973, -0.275387, -0.233446, -0.012711",\
+ "-0.579500, -0.513636, -0.456051, -0.414110, -0.193375",\
+ "-0.884380, -0.818360, -0.760550, -0.718548, -0.498201");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.292019, -0.249633, -0.215074, -0.177056, 0.111552",\
+ "-0.374431, -0.332045, -0.297485, -0.259467, 0.029140",\
+ "-0.488086, -0.445700, -0.411141, -0.373122, -0.084515",\
+ "-0.684457, -0.642085, -0.607494, -0.570100, -0.289245",\
+ "-1.001110, -0.958772, -0.924101, -0.888239, -0.626398");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[106]_hldr*/
+
+} /* end of pin tl_i[106] */
+
+pin("tl_i[105]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.003624 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[105];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.863893, 4.817738, 4.787521, 4.776164, 4.789771",\
+ "4.956792, 4.910637, 4.880420, 4.869063, 4.882670",\
+ "5.049713, 5.003558, 4.973341, 4.961984, 4.975592",\
+ "5.212534, 5.166379, 5.136162, 5.124805, 5.138412",\
+ "5.493520, 5.447365, 5.417148, 5.405791, 5.419398");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.894609, 4.848454, 4.818238, 4.806880, 4.820488",\
+ "4.991653, 4.945498, 4.915282, 4.903924, 4.917532",\
+ "5.091967, 5.045812, 5.015595, 5.004238, 5.017845",\
+ "5.268436, 5.222281, 5.192065, 5.180707, 5.194315",\
+ "5.577918, 5.531763, 5.501546, 5.490189, 5.503797");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[105]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.191328, -0.125448, -0.067841, -0.025894, 0.194803",\
+ "-0.284713, -0.218834, -0.161226, -0.119279, 0.101417",\
+ "-0.376971, -0.311091, -0.253484, -0.211536, 0.009160",\
+ "-0.536682, -0.470803, -0.413195, -0.371248, -0.150551",\
+ "-0.807364, -0.741369, -0.683595, -0.641603, -0.421195");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.219051, -0.176666, -0.142105, -0.104110, 0.184210",\
+ "-0.313450, -0.271065, -0.236504, -0.198509, 0.089812",\
+ "-0.408426, -0.366041, -0.331480, -0.293485, -0.005164",\
+ "-0.576090, -0.533704, -0.499144, -0.461149, -0.172828",\
+ "-0.853410, -0.811045, -0.776438, -0.739355, -0.462356");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[105]_hldr*/
+
+} /* end of pin tl_i[105] */
+
+pin("tl_i[104]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[104];
+} /* end of pin tl_i[104] */
+
+pin("tl_i[103]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[103];
+} /* end of pin tl_i[103] */
+
+pin("tl_i[102]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[102];
+} /* end of pin tl_i[102] */
+
+pin("tl_i[101]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002631 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[101];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.040158, 3.994009, 3.963793, 3.952436, 3.966046",\
+ "4.127818, 4.081669, 4.051453, 4.040096, 4.053706",\
+ "4.214727, 4.168579, 4.138362, 4.127005, 4.140615",\
+ "4.367462, 4.321313, 4.291097, 4.279740, 4.293350",\
+ "4.608571, 4.562422, 4.532206, 4.520849, 4.534459");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.240349, 4.194201, 4.163985, 4.152627, 4.166238",\
+ "4.323653, 4.277504, 4.247288, 4.235931, 4.249541",\
+ "4.439158, 4.393010, 4.362793, 4.351436, 4.365047",\
+ "4.634571, 4.588422, 4.558206, 4.546849, 4.560459",\
+ "4.954862, 4.908714, 4.878498, 4.867140, 4.880751");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[101]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[101]_hldr*/
+
+} /* end of pin tl_i[101] */
+
+pin("tl_i[100]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002123 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[100];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.031560, 3.985412, 3.955196, 3.943839, 3.957449",\
+ "4.118053, 4.071905, 4.041688, 4.030331, 4.043941",\
+ "4.209411, 4.163263, 4.133047, 4.121689, 4.135300",\
+ "4.373650, 4.327502, 4.297286, 4.285928, 4.299539",\
+ "4.639607, 4.593459, 4.563242, 4.551885, 4.565495");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.345016, 4.298868, 4.268651, 4.257294, 4.270905",\
+ "4.436058, 4.389909, 4.359693, 4.348336, 4.361946",\
+ "4.527231, 4.481082, 4.450866, 4.439509, 4.453119",\
+ "4.689745, 4.643597, 4.613381, 4.602024, 4.615634",\
+ "4.957426, 4.911277, 4.881061, 4.869704, 4.883314");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[100]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[100]_hldr*/
+
+} /* end of pin tl_i[100] */
+
+pin("tl_i[99]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000562 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[99];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\
+ "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\
+ "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\
+ "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\
+ "0.818496, 0.771022, 0.740703, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\
+ "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\
+ "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\
+ "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\
+ "0.940670, 0.865438, 0.797763, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[99]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[99]_hldr*/
+
+} /* end of pin tl_i[99] */
+
+pin("tl_i[98]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000562 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[98];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\
+ "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\
+ "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\
+ "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\
+ "0.818496, 0.771022, 0.740703, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\
+ "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\
+ "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\
+ "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\
+ "0.940670, 0.865438, 0.797763, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[98]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[98]_hldr*/
+
+} /* end of pin tl_i[98] */
+
+pin("tl_i[97]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000562 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[97];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\
+ "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\
+ "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\
+ "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\
+ "0.818496, 0.771022, 0.740703, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\
+ "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\
+ "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\
+ "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\
+ "0.940670, 0.865438, 0.797763, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[97]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[97]_hldr*/
+
+} /* end of pin tl_i[97] */
+
+pin("tl_i[96]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000562 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[96];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\
+ "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\
+ "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\
+ "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\
+ "0.818496, 0.771022, 0.740703, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\
+ "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\
+ "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\
+ "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\
+ "0.940670, 0.865438, 0.797763, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[96]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[96]_hldr*/
+
+} /* end of pin tl_i[96] */
+
+pin("tl_i[95]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000562 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[95];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\
+ "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\
+ "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\
+ "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\
+ "0.818496, 0.771022, 0.740703, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\
+ "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\
+ "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\
+ "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\
+ "0.940670, 0.865438, 0.797763, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[95]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[95]_hldr*/
+
+} /* end of pin tl_i[95] */
+
+pin("tl_i[94]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000562 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[94];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\
+ "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\
+ "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\
+ "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\
+ "0.818496, 0.771022, 0.740703, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\
+ "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\
+ "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\
+ "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\
+ "0.940670, 0.865438, 0.797763, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[94]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[94]_hldr*/
+
+} /* end of pin tl_i[94] */
+
+pin("tl_i[93]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000562 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[93];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\
+ "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\
+ "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\
+ "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\
+ "0.818496, 0.771022, 0.740703, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\
+ "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\
+ "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\
+ "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\
+ "0.940670, 0.865438, 0.797763, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[93]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[93]_hldr*/
+
+} /* end of pin tl_i[93] */
+
+pin("tl_i[92]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000562 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[92];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\
+ "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\
+ "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\
+ "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\
+ "0.818496, 0.771022, 0.740703, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\
+ "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\
+ "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\
+ "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\
+ "0.940670, 0.865438, 0.797763, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[92]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\
+ "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\
+ "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\
+ "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\
+ "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\
+ "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\
+ "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\
+ "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\
+ "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[92]_hldr*/
+
+} /* end of pin tl_i[92] */
+
+pin("tl_i[91]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001976 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[91];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.041809, 5.995654, 5.965437, 5.954080, 5.967688",\
+ "6.129841, 6.083686, 6.053469, 6.042112, 6.055719",\
+ "6.240180, 6.194025, 6.163808, 6.152451, 6.166058",\
+ "6.431971, 6.385816, 6.355599, 6.344242, 6.357849",\
+ "6.749926, 6.703771, 6.673554, 6.662197, 6.675805");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.036389, 5.990234, 5.960017, 5.948660, 5.962267",\
+ "6.118236, 6.072081, 6.041864, 6.030507, 6.044114",\
+ "6.243943, 6.197788, 6.167572, 6.156214, 6.169822",\
+ "6.470764, 6.424609, 6.394392, 6.383035, 6.396643",\
+ "6.863174, 6.817019, 6.786803, 6.775445, 6.789053");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[91]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.151672, -1.109295, -1.074716, -1.037080, -0.753224",\
+ "-1.243671, -1.201294, -1.166714, -1.129079, -0.845222",\
+ "-1.323829, -1.281452, -1.246872, -1.209237, -0.925380",\
+ "-1.441613, -1.399235, -1.364656, -1.327021, -1.043164",\
+ "-1.629556, -1.587178, -1.552599, -1.514964, -1.231107");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.146252, -1.103875, -1.069295, -1.031660, -0.747803",\
+ "-1.232066, -1.189688, -1.155109, -1.117473, -0.833617",\
+ "-1.316872, -1.274495, -1.239915, -1.202280, -0.918423",\
+ "-1.462124, -1.419747, -1.385167, -1.347532, -1.063675",\
+ "-1.705527, -1.663150, -1.628571, -1.590935, -1.307079");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[91]_hldr*/
+
+} /* end of pin tl_i[91] */
+
+pin("tl_i[90]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.003090 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[90];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.559815, 5.513660, 5.483444, 5.472086, 5.485694",\
+ "5.649643, 5.603488, 5.573271, 5.561914, 5.575521",\
+ "5.741996, 5.695841, 5.665624, 5.654267, 5.667874",\
+ "5.908573, 5.862418, 5.832201, 5.820844, 5.834452",\
+ "6.303185, 6.257030, 6.226814, 6.215456, 6.229064");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.570656, 5.524501, 5.494284, 5.482927, 5.496534",\
+ "5.661279, 5.615124, 5.584907, 5.573550, 5.587157",\
+ "5.780371, 5.734216, 5.703999, 5.692642, 5.706249",\
+ "6.016336, 5.970181, 5.939964, 5.928607, 5.942214",\
+ "6.443535, 6.397380, 6.367163, 6.355806, 6.369413");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[90]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.123815, -1.081437, -1.046858, -1.009223, -0.725366",\
+ "-1.217456, -1.175079, -1.140499, -1.102864, -0.819007",\
+ "-1.332136, -1.289759, -1.255179, -1.217544, -0.933687",\
+ "-1.517521, -1.475144, -1.440564, -1.402929, -1.119072",\
+ "-1.805479, -1.763102, -1.728523, -1.690887, -1.407031");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.159454, -1.117077, -1.082498, -1.044862, -0.761006",\
+ "-1.250402, -1.208025, -1.173445, -1.135810, -0.851953",\
+ "-1.352041, -1.309663, -1.275084, -1.237449, -0.953592",\
+ "-1.534891, -1.492514, -1.457935, -1.420299, -1.136443",\
+ "-1.849478, -1.807101, -1.772522, -1.734886, -1.451030");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[90]_hldr*/
+
+} /* end of pin tl_i[90] */
+
+pin("tl_i[89]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002521 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[89];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.812771, 5.766616, 5.736399, 5.725042, 5.738649",\
+ "5.898168, 5.852013, 5.821796, 5.810439, 5.824046",\
+ "5.975654, 5.929499, 5.899282, 5.887925, 5.901533",\
+ "6.119768, 6.073613, 6.043396, 6.032039, 6.045647",\
+ "6.477526, 6.431371, 6.401154, 6.389797, 6.403404");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.809771, 5.763616, 5.733399, 5.722042, 5.735649",\
+ "5.892390, 5.846235, 5.816019, 5.804661, 5.818269",\
+ "6.004417, 5.958262, 5.928046, 5.916688, 5.930296",\
+ "6.234746, 6.188591, 6.158375, 6.147017, 6.160625",\
+ "6.638525, 6.592370, 6.562153, 6.550796, 6.564404");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[89]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.029578, -0.987200, -0.952621, -0.914986, -0.631129",\
+ "-1.117165, -1.074787, -1.040208, -1.002573, -0.718716",\
+ "-1.206337, -1.163960, -1.129380, -1.091745, -0.807888",\
+ "-1.362213, -1.319836, -1.285257, -1.247621, -0.963765",\
+ "-1.590532, -1.548155, -1.513575, -1.475940, -1.192083");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.059949, -1.017572, -0.982993, -0.945357, -0.661501",\
+ "-1.159550, -1.117173, -1.082594, -1.044958, -0.761102",\
+ "-1.261636, -1.219259, -1.184679, -1.147044, -0.863187",\
+ "-1.441043, -1.398666, -1.364086, -1.326451, -1.042594",\
+ "-1.748482, -1.706105, -1.671526, -1.633890, -1.350034");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[89]_hldr*/
+
+} /* end of pin tl_i[89] */
+
+pin("tl_i[88]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001007 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[88];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.471457, 5.425303, 5.395086, 5.383729, 5.397336",\
+ "5.567654, 5.521499, 5.491282, 5.479925, 5.493532",\
+ "5.669107, 5.622952, 5.592736, 5.581378, 5.594986",\
+ "5.849272, 5.803117, 5.772900, 5.761543, 5.775150",\
+ "6.163116, 6.116961, 6.086744, 6.075387, 6.088994");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.500805, 5.454650, 5.424433, 5.413076, 5.426683",\
+ "5.598975, 5.552820, 5.522604, 5.511246, 5.524854",\
+ "5.704100, 5.657945, 5.627728, 5.616371, 5.629978",\
+ "5.884839, 5.838684, 5.808467, 5.797110, 5.810718",\
+ "6.188713, 6.142558, 6.112341, 6.100984, 6.114592");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[88]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.083938, -1.041561, -1.006981, -0.969346, -0.685489",\
+ "-1.181137, -1.138760, -1.104181, -1.066545, -0.782689",\
+ "-1.281549, -1.239172, -1.204592, -1.166957, -0.883101",\
+ "-1.453069, -1.410691, -1.376112, -1.338477, -1.054620",\
+ "-1.733325, -1.690947, -1.656368, -1.618733, -1.334876");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.081498, -1.039121, -1.004542, -0.966906, -0.683050",\
+ "-1.178693, -1.136315, -1.101736, -1.064101, -0.780244",\
+ "-1.285877, -1.243499, -1.208920, -1.171285, -0.887428",\
+ "-1.474000, -1.431623, -1.397043, -1.359408, -1.075551",\
+ "-1.791995, -1.749618, -1.715039, -1.677403, -1.393547");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[88]_hldr*/
+
+} /* end of pin tl_i[88] */
+
+pin("tl_i[87]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001007 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[87];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.100426, 6.054271, 6.024055, 6.012697, 6.026305",\
+ "6.196661, 6.150506, 6.120289, 6.108932, 6.122540",\
+ "6.301589, 6.255434, 6.225217, 6.213860, 6.227468",\
+ "6.487259, 6.441104, 6.410888, 6.399530, 6.413138",\
+ "6.807995, 6.761840, 6.731623, 6.720266, 6.733873");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.124471, 6.078316, 6.048099, 6.036742, 6.050349",\
+ "6.222617, 6.176462, 6.146245, 6.134888, 6.148495",\
+ "6.331584, 6.285429, 6.255212, 6.243855, 6.257463",\
+ "6.520377, 6.474222, 6.444005, 6.432648, 6.446256",\
+ "6.841649, 6.795494, 6.765277, 6.753920, 6.767528");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[87]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.134100, -1.091722, -1.057143, -1.019508, -0.735651",\
+ "-1.231353, -1.188975, -1.154396, -1.116761, -0.832904",\
+ "-1.331896, -1.289519, -1.254940, -1.217304, -0.933448",\
+ "-1.503641, -1.461264, -1.426684, -1.389049, -1.105192",\
+ "-1.784290, -1.741913, -1.707334, -1.669698, -1.385842");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.132025, -1.089648, -1.055068, -1.017433, -0.733576",\
+ "-1.229244, -1.186866, -1.152287, -1.114652, -0.830795",\
+ "-1.336593, -1.294216, -1.259636, -1.222001, -0.938144",\
+ "-1.525111, -1.482733, -1.448154, -1.410519, -1.126662",\
+ "-1.844292, -1.801915, -1.767335, -1.729700, -1.445843");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[87]_hldr*/
+
+} /* end of pin tl_i[87] */
+
+pin("tl_i[86]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002623 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[86];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.848853, 5.802698, 5.772481, 5.761124, 5.774731",\
+ "5.936358, 5.890203, 5.859987, 5.848629, 5.862237",\
+ "6.023653, 5.977498, 5.947281, 5.935924, 5.949532",\
+ "6.191101, 6.144946, 6.114729, 6.103372, 6.116980",\
+ "6.582396, 6.536241, 6.506024, 6.494667, 6.508274");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.843520, 5.797365, 5.767148, 5.755791, 5.769399",\
+ "5.932423, 5.886268, 5.856051, 5.844694, 5.858301",\
+ "6.047498, 6.001343, 5.971126, 5.959769, 5.973376",\
+ "6.285758, 6.239603, 6.209386, 6.198029, 6.211636",\
+ "6.722472, 6.676317, 6.646101, 6.634743, 6.648351");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[86]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.087246, -1.044869, -1.010289, -0.972654, -0.688797",\
+ "-1.172364, -1.129987, -1.095407, -1.057772, -0.773916",\
+ "-1.269076, -1.226699, -1.192120, -1.154484, -0.870628",\
+ "-1.437615, -1.395237, -1.360658, -1.323022, -1.039166",\
+ "-1.686824, -1.644446, -1.609867, -1.572232, -1.288375");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.118792, -1.076414, -1.041835, -1.004200, -0.720343",\
+ "-1.209484, -1.167107, -1.132527, -1.094892, -0.811035",\
+ "-1.302947, -1.260570, -1.225991, -1.188355, -0.904499",\
+ "-1.465349, -1.422972, -1.388392, -1.350757, -1.066900",\
+ "-1.738277, -1.695899, -1.661320, -1.623685, -1.339828");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[86]_hldr*/
+
+} /* end of pin tl_i[86] */
+
+pin("tl_i[85]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.003219 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[85];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.640028, 5.593873, 5.563656, 5.552299, 5.565907",\
+ "5.724194, 5.678039, 5.647822, 5.636465, 5.650072",\
+ "5.805078, 5.758923, 5.728706, 5.717349, 5.730957",\
+ "5.946632, 5.900477, 5.870261, 5.858903, 5.872511",\
+ "6.188352, 6.142197, 6.111980, 6.100623, 6.114231");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.625210, 5.579055, 5.548838, 5.537481, 5.551088",\
+ "5.706786, 5.660631, 5.630414, 5.619057, 5.632665",\
+ "5.812987, 5.766832, 5.736616, 5.725258, 5.738866",\
+ "6.001375, 5.955220, 5.925003, 5.913646, 5.927253",\
+ "6.317180, 6.271025, 6.240808, 6.229451, 6.243059");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[85]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.041623, -0.999245, -0.964666, -0.927031, -0.643174",\
+ "-1.126700, -1.084323, -1.049744, -1.012108, -0.728252",\
+ "-1.223403, -1.181025, -1.146446, -1.108811, -0.824954",\
+ "-1.391917, -1.349539, -1.314960, -1.277325, -0.993468",\
+ "-1.638337, -1.595960, -1.561380, -1.523745, -1.239888");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.073138, -1.030761, -0.996182, -0.958546, -0.674690",\
+ "-1.161118, -1.118740, -1.084161, -1.046526, -0.762669",\
+ "-1.257352, -1.214975, -1.180395, -1.142760, -0.858903",\
+ "-1.419670, -1.377293, -1.342714, -1.305078, -1.021222",\
+ "-1.692554, -1.650177, -1.615597, -1.577962, -1.294106");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[85]_hldr*/
+
+} /* end of pin tl_i[85] */
+
+pin("tl_i[84]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001002 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[84];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.863610, 5.817455, 5.787239, 5.775881, 5.789489",\
+ "5.963272, 5.917117, 5.886900, 5.875543, 5.889151",\
+ "6.072519, 6.026364, 5.996147, 5.984790, 5.998397",\
+ "6.263348, 6.217193, 6.186976, 6.175619, 6.189227",\
+ "6.585179, 6.539024, 6.508808, 6.497450, 6.511058");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.949015, 5.902860, 5.872643, 5.861286, 5.874893",\
+ "6.048979, 6.002824, 5.972607, 5.961250, 5.974857",\
+ "6.167165, 6.121010, 6.090793, 6.079436, 6.093043",\
+ "6.365981, 6.319826, 6.289609, 6.278252, 6.291860",\
+ "6.701097, 6.654942, 6.624725, 6.613368, 6.626975");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[84]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.056499, -1.014122, -0.979543, -0.941907, -0.658051",\
+ "-1.146680, -1.104303, -1.069723, -1.032088, -0.748231",\
+ "-1.259394, -1.217017, -1.182437, -1.144802, -0.860945",\
+ "-1.443621, -1.401244, -1.366664, -1.329029, -1.045172",\
+ "-1.712122, -1.669745, -1.635165, -1.597530, -1.313673");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.090162, -1.047785, -1.013205, -0.975570, -0.691713",\
+ "-1.180082, -1.137704, -1.103125, -1.065490, -0.781633",\
+ "-1.275585, -1.233208, -1.198629, -1.160993, -0.877137",\
+ "-1.445900, -1.403523, -1.368944, -1.331308, -1.047452",\
+ "-1.745297, -1.702920, -1.668340, -1.630705, -1.346848");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[84]_hldr*/
+
+} /* end of pin tl_i[84] */
+
+pin("tl_i[83]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.003541 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[83];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.687950, 5.641795, 5.611578, 5.600221, 5.613829",\
+ "5.774795, 5.728640, 5.698423, 5.687066, 5.700673",\
+ "5.876379, 5.830224, 5.800007, 5.788650, 5.802258",\
+ "6.080298, 6.034143, 6.003927, 5.992569, 6.006177",\
+ "6.432961, 6.386806, 6.356589, 6.345232, 6.358839");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.703408, 5.657253, 5.627037, 5.615679, 5.629287",\
+ "5.789980, 5.743825, 5.713608, 5.702251, 5.715858",\
+ "5.917695, 5.871540, 5.841323, 5.829966, 5.843574",\
+ "6.190283, 6.144128, 6.113912, 6.102554, 6.116162",\
+ "6.660905, 6.614750, 6.584533, 6.573176, 6.586783");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[83]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.867726, -0.825349, -0.790770, -0.753134, -0.469278",\
+ "-0.951320, -0.908943, -0.874363, -0.836728, -0.552871",\
+ "-1.016544, -0.974167, -0.939588, -0.901952, -0.618096",\
+ "-1.123735, -1.081358, -1.046778, -1.009143, -0.725286",\
+ "-1.291921, -1.249544, -1.214964, -1.177329, -0.893472");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.911896, -0.869519, -0.833451, -0.791428, -0.513448",\
+ "-1.012793, -0.970416, -0.921834, -0.879811, -0.614345",\
+ "-1.095336, -1.052959, -1.000425, -0.958402, -0.696888",\
+ "-1.226252, -1.183874, -1.131083, -1.089060, -0.827803",\
+ "-1.440278, -1.397901, -1.344258, -1.302235, -1.041830");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[83]_hldr*/
+
+} /* end of pin tl_i[83] */
+
+pin("tl_i[82]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002444 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[82];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.708182, 5.662027, 5.631811, 5.620453, 5.634061",\
+ "5.801434, 5.755279, 5.725062, 5.713705, 5.727312",\
+ "5.894579, 5.848424, 5.818208, 5.806850, 5.820458",\
+ "6.057735, 6.011580, 5.981363, 5.970006, 5.983613",\
+ "6.337201, 6.291046, 6.260829, 6.249472, 6.263080");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.710078, 5.663923, 5.633707, 5.622349, 5.635957",\
+ "5.807050, 5.760895, 5.730678, 5.719321, 5.732928",\
+ "5.905420, 5.859265, 5.829048, 5.817691, 5.831298",\
+ "6.075630, 6.029475, 5.999258, 5.987901, 6.001508",\
+ "6.350610, 6.304455, 6.274238, 6.262881, 6.276488");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[82]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.931103, -0.888726, -0.854147, -0.816511, -0.532655",\
+ "-1.016007, -0.973630, -0.939050, -0.901415, -0.617558",\
+ "-1.106769, -1.064392, -1.029812, -0.992177, -0.708320",\
+ "-1.260793, -1.218416, -1.183836, -1.146201, -0.862344",\
+ "-1.523812, -1.481435, -1.446856, -1.409220, -1.125364");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.978443, -0.936065, -0.901486, -0.863851, -0.579994",\
+ "-1.073078, -1.030701, -0.996121, -0.958486, -0.674629",\
+ "-1.181049, -1.138672, -1.104093, -1.066457, -0.782601",\
+ "-1.371690, -1.329313, -1.294734, -1.257098, -0.973242",\
+ "-1.704884, -1.662507, -1.627928, -1.590292, -1.306436");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[82]_hldr*/
+
+} /* end of pin tl_i[82] */
+
+pin("tl_i[81]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002980 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[81];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.772726, 5.726571, 5.696354, 5.684997, 5.698605",\
+ "5.867767, 5.821612, 5.791396, 5.780038, 5.793646",\
+ "5.991376, 5.945221, 5.915004, 5.903647, 5.917254",\
+ "6.241336, 6.195181, 6.164964, 6.153607, 6.167214",\
+ "6.709605, 6.663450, 6.633233, 6.621876, 6.635483");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.760269, 5.714114, 5.683897, 5.672540, 5.686147",\
+ "5.853128, 5.806973, 5.776756, 5.765399, 5.779006",\
+ "5.986612, 5.940457, 5.910241, 5.898883, 5.912491",\
+ "6.273496, 6.227341, 6.197124, 6.185767, 6.199374",\
+ "6.818243, 6.772088, 6.741871, 6.730514, 6.744122");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[81]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.928193, -0.885816, -0.851236, -0.813601, -0.529744",\
+ "-1.010898, -0.968521, -0.933941, -0.896306, -0.612449",\
+ "-1.110272, -1.067895, -1.033316, -0.995680, -0.711824",\
+ "-1.278434, -1.236057, -1.201477, -1.163842, -0.879985",\
+ "-1.568159, -1.525781, -1.491202, -1.453566, -1.169710");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.972769, -0.930391, -0.895812, -0.858176, -0.574320",\
+ "-1.064861, -1.022484, -0.987905, -0.950269, -0.666413",\
+ "-1.170576, -1.128199, -1.093619, -1.055984, -0.772127",\
+ "-1.359091, -1.316714, -1.282135, -1.244499, -0.960643",\
+ "-1.694739, -1.652362, -1.617782, -1.580147, -1.296290");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[81]_hldr*/
+
+} /* end of pin tl_i[81] */
+
+pin("tl_i[80]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.004096 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[80];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.423539, 5.377384, 5.347167, 5.335810, 5.349418",\
+ "5.507660, 5.461505, 5.431288, 5.419931, 5.433538",\
+ "5.588662, 5.542507, 5.512290, 5.500933, 5.514540",\
+ "5.729993, 5.683838, 5.653621, 5.642264, 5.655871",\
+ "5.971819, 5.925664, 5.895447, 5.884090, 5.897697");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.408631, 5.362476, 5.332260, 5.320902, 5.334510",\
+ "5.490341, 5.444186, 5.413970, 5.402612, 5.416220",\
+ "5.596552, 5.550397, 5.520180, 5.508823, 5.522430",\
+ "5.784794, 5.738639, 5.708422, 5.697065, 5.710672",\
+ "6.157783, 6.111628, 6.081411, 6.070054, 6.083661");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[80]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.991939, -0.949562, -0.914982, -0.877347, -0.593490",\
+ "-1.074940, -1.032563, -0.997983, -0.960348, -0.676491",\
+ "-1.172758, -1.130381, -1.095802, -1.058166, -0.774310",\
+ "-1.338347, -1.295969, -1.261390, -1.223755, -0.939898",\
+ "-1.624824, -1.582447, -1.547868, -1.510232, -1.226376");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.037009, -0.994632, -0.960053, -0.922417, -0.638561",\
+ "-1.129460, -1.087082, -1.052503, -1.014868, -0.731011",\
+ "-1.235564, -1.193187, -1.158608, -1.120972, -0.837116",\
+ "-1.410576, -1.368199, -1.333619, -1.295984, -1.012127",\
+ "-1.676313, -1.633936, -1.599356, -1.561721, -1.277864");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[80]_hldr*/
+
+} /* end of pin tl_i[80] */
+
+pin("tl_i[79]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001007 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[79];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.446656, 5.400501, 5.370284, 5.358927, 5.372534",\
+ "5.547154, 5.500999, 5.470783, 5.459425, 5.473033",\
+ "5.662600, 5.616445, 5.586228, 5.574871, 5.588478",\
+ "5.873106, 5.826951, 5.796734, 5.785377, 5.798985",\
+ "6.242186, 6.196031, 6.165814, 6.154457, 6.168064");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.480749, 5.434594, 5.404377, 5.393020, 5.406628",\
+ "5.579840, 5.533685, 5.503468, 5.492111, 5.505718",\
+ "5.703683, 5.657528, 5.627311, 5.615954, 5.629561",\
+ "5.911795, 5.865640, 5.835423, 5.824066, 5.837673",\
+ "6.265936, 6.219781, 6.189564, 6.178207, 6.191814");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[79]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.093242, -1.050865, -1.016285, -0.978650, -0.694793",\
+ "-1.195110, -1.152733, -1.118154, -1.080518, -0.796662",\
+ "-1.314294, -1.271917, -1.237338, -1.199702, -0.915846",\
+ "-1.525733, -1.483356, -1.448776, -1.411141, -1.127284",\
+ "-1.885126, -1.842748, -1.808169, -1.770533, -1.486677");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.071935, -1.029557, -0.994978, -0.957343, -0.673486",\
+ "-1.171764, -1.129387, -1.094808, -1.057172, -0.773316",\
+ "-1.298104, -1.255727, -1.221148, -1.183512, -0.899656",\
+ "-1.517193, -1.474816, -1.440237, -1.402601, -1.118745",\
+ "-1.889590, -1.847213, -1.812633, -1.774998, -1.491141");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[79]_hldr*/
+
+} /* end of pin tl_i[79] */
+
+pin("tl_i[78]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002174 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[78];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.182078, 5.135923, 5.105707, 5.094349, 5.107957",\
+ "5.277516, 5.231361, 5.201145, 5.189787, 5.203395",\
+ "5.400351, 5.354196, 5.323979, 5.312622, 5.326229",\
+ "5.638412, 5.592257, 5.562040, 5.550683, 5.564290",\
+ "6.058977, 6.012822, 5.982605, 5.971248, 5.984856");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.163897, 5.117742, 5.087525, 5.076168, 5.089776",\
+ "5.262290, 5.216135, 5.185918, 5.174561, 5.188169",\
+ "5.405017, 5.358862, 5.328645, 5.317288, 5.330895",\
+ "5.691147, 5.644992, 5.614775, 5.603418, 5.617025",\
+ "6.209457, 6.163302, 6.133085, 6.121728, 6.135335");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[78]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.808182, -0.765804, -0.731225, -0.693590, -0.409733",\
+ "-0.891099, -0.848721, -0.814142, -0.776506, -0.492650",\
+ "-0.960506, -0.918129, -0.883550, -0.845914, -0.562058",\
+ "-1.077306, -1.034929, -1.000349, -0.962714, -0.678857",\
+ "-1.260451, -1.218073, -1.183494, -1.145859, -0.862002");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.822461, -0.780084, -0.745505, -0.707869, -0.424013",\
+ "-0.907616, -0.865238, -0.830659, -0.793024, -0.509167",\
+ "-0.995187, -0.952809, -0.918230, -0.880595, -0.596738",\
+ "-1.146480, -1.104103, -1.069523, -1.031888, -0.748031",\
+ "-1.401185, -1.358808, -1.324229, -1.286593, -1.002737");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[78]_hldr*/
+
+} /* end of pin tl_i[78] */
+
+pin("tl_i[77]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001980 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[77];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.530322, 5.484167, 5.453950, 5.442593, 5.456201",\
+ "5.617828, 5.571673, 5.541456, 5.530099, 5.543706",\
+ "5.705123, 5.658968, 5.628751, 5.617394, 5.631001",\
+ "5.872606, 5.826451, 5.796235, 5.784877, 5.798485",\
+ "6.261807, 6.215652, 6.185436, 6.174078, 6.187686");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.524989, 5.478834, 5.448617, 5.437260, 5.450868",\
+ "5.613892, 5.567737, 5.537520, 5.526163, 5.539771",\
+ "5.728968, 5.682813, 5.652596, 5.641239, 5.654846",\
+ "5.967242, 5.921087, 5.890870, 5.879513, 5.893120",\
+ "6.403997, 6.357842, 6.327626, 6.316268, 6.329876");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[77]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.941463, -0.899085, -0.864506, -0.826870, -0.543014",\
+ "-1.026243, -0.983865, -0.949286, -0.911651, -0.627794",\
+ "-1.097818, -1.055441, -1.020861, -0.983226, -0.699369",\
+ "-1.219287, -1.176910, -1.142331, -1.104695, -0.820839",\
+ "-1.414036, -1.371659, -1.337079, -1.299444, -1.015587");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.962457, -0.920079, -0.885500, -0.847865, -0.564008",\
+ "-1.048641, -1.006264, -0.971684, -0.934049, -0.650192",\
+ "-1.136345, -1.093968, -1.059388, -1.021753, -0.737896",\
+ "-1.287015, -1.244637, -1.210058, -1.172423, -0.888566",\
+ "-1.540997, -1.498620, -1.464041, -1.426405, -1.142549");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[77]_hldr*/
+
+} /* end of pin tl_i[77] */
+
+pin("tl_i[76]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002121 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[76];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.188263, 5.142108, 5.111891, 5.100534, 5.114141",\
+ "5.280335, 5.234180, 5.203964, 5.192606, 5.206214",\
+ "5.390166, 5.344011, 5.313795, 5.302437, 5.316045",\
+ "5.594857, 5.548702, 5.518486, 5.507128, 5.520736",\
+ "5.971145, 5.924990, 5.894773, 5.883416, 5.897023");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.181033, 5.134878, 5.104661, 5.093304, 5.106912",\
+ "5.279116, 5.232961, 5.202744, 5.191387, 5.204994",\
+ "5.410749, 5.364594, 5.334378, 5.323020, 5.336628",\
+ "5.655250, 5.609095, 5.578878, 5.567521, 5.581128",\
+ "6.082715, 6.036560, 6.006343, 5.994986, 6.008594");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[76]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.873539, -0.831162, -0.796583, -0.758947, -0.475091",\
+ "-0.958672, -0.916295, -0.881715, -0.844080, -0.560223",\
+ "-1.055412, -1.013035, -0.978456, -0.940820, -0.656964",\
+ "-1.223937, -1.181559, -1.146980, -1.109345, -0.825488",\
+ "-1.471815, -1.429437, -1.394858, -1.357222, -1.073366");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.905092, -0.862715, -0.828135, -0.790500, -0.506643",\
+ "-0.994562, -0.952185, -0.917606, -0.879970, -0.596114",\
+ "-1.089293, -1.046916, -1.012336, -0.974701, -0.690844",\
+ "-1.251651, -1.209274, -1.174694, -1.137059, -0.853202",\
+ "-1.524578, -1.482201, -1.447622, -1.409986, -1.126130");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[76]_hldr*/
+
+} /* end of pin tl_i[76] */
+
+pin("tl_i[75]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002542 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[75];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.559262, 5.513107, 5.482891, 5.471533, 5.485141",\
+ "5.649136, 5.602981, 5.572764, 5.561407, 5.575014",\
+ "5.741644, 5.695489, 5.665273, 5.653915, 5.667523",\
+ "5.907515, 5.861360, 5.831143, 5.819786, 5.833393",\
+ "6.276364, 6.230209, 6.199993, 6.188635, 6.202243");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.570172, 5.524017, 5.493801, 5.482443, 5.496051",\
+ "5.660883, 5.614728, 5.584512, 5.573154, 5.586762",\
+ "5.779753, 5.733598, 5.703381, 5.692024, 5.705631",\
+ "6.011688, 5.965533, 5.935317, 5.923959, 5.937567",\
+ "6.423101, 6.376946, 6.346730, 6.335372, 6.348980");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[75]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.889999, -0.847622, -0.813043, -0.775407, -0.491551",\
+ "-0.980238, -0.937861, -0.903281, -0.865646, -0.581789",\
+ "-1.093020, -1.050642, -1.016063, -0.978428, -0.694571",\
+ "-1.275653, -1.233275, -1.198696, -1.161060, -0.877204",\
+ "-1.544115, -1.501738, -1.467158, -1.429523, -1.145666");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.923539, -0.881162, -0.846582, -0.808947, -0.525090",\
+ "-1.013448, -0.971071, -0.936491, -0.898856, -0.614999",\
+ "-1.108924, -1.066547, -1.031967, -0.994332, -0.710475",\
+ "-1.279292, -1.236915, -1.202336, -1.164700, -0.880844",\
+ "-1.578850, -1.536472, -1.501893, -1.464258, -1.180401");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[75]_hldr*/
+
+} /* end of pin tl_i[75] */
+
+pin("tl_i[74]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002632 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[74];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.253567, 5.207412, 5.177195, 5.165838, 5.179445",\
+ "5.349404, 5.303249, 5.273033, 5.261675, 5.275283",\
+ "5.476182, 5.430027, 5.399810, 5.388453, 5.402061",\
+ "5.733068, 5.686913, 5.656696, 5.645339, 5.658946",\
+ "6.219316, 6.173161, 6.142944, 6.131587, 6.145194");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.241081, 5.194926, 5.164710, 5.153352, 5.166960",\
+ "5.334809, 5.288654, 5.258438, 5.247080, 5.260688",\
+ "5.471406, 5.425251, 5.395034, 5.383677, 5.397285",\
+ "5.764438, 5.718283, 5.688066, 5.676709, 5.690317",\
+ "6.325636, 6.279481, 6.249264, 6.237907, 6.251514");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[74]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.935219, -0.892842, -0.858263, -0.820627, -0.536771",\
+ "-1.028860, -0.986483, -0.951903, -0.914268, -0.630411",\
+ "-1.143547, -1.101169, -1.066590, -1.028955, -0.745098",\
+ "-1.326218, -1.283841, -1.249262, -1.211626, -0.927770",\
+ "-1.614166, -1.571789, -1.537210, -1.499574, -1.215718");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.970892, -0.928514, -0.893935, -0.856300, -0.572443",\
+ "-1.061820, -1.019442, -0.984863, -0.947227, -0.663371",\
+ "-1.163435, -1.121057, -1.086478, -1.048843, -0.764986",\
+ "-1.346292, -1.303915, -1.269336, -1.231700, -0.947844",\
+ "-1.660875, -1.618498, -1.583918, -1.546283, -1.262426");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[74]_hldr*/
+
+} /* end of pin tl_i[74] */
+
+pin("tl_i[73]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002107 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[73];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.554523, 5.508368, 5.478152, 5.466794, 5.480402",\
+ "5.649414, 5.603259, 5.573042, 5.561685, 5.575293",\
+ "5.748847, 5.702692, 5.672475, 5.661118, 5.674726",\
+ "5.924383, 5.878228, 5.848011, 5.836654, 5.850262",\
+ "6.224755, 6.178600, 6.148384, 6.137026, 6.150634");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.589440, 5.543285, 5.513069, 5.501711, 5.515319",\
+ "5.687266, 5.641111, 5.610895, 5.599537, 5.613145",\
+ "5.793367, 5.747212, 5.716996, 5.705638, 5.719246",\
+ "5.973481, 5.927326, 5.897110, 5.885752, 5.899360",\
+ "6.270272, 6.224117, 6.193900, 6.182543, 6.196150");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[73]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.898724, -0.856347, -0.821768, -0.784132, -0.500276",\
+ "-0.983802, -0.941425, -0.906845, -0.869210, -0.585353",\
+ "-1.080504, -1.038127, -1.003548, -0.965912, -0.682056",\
+ "-1.249018, -1.206641, -1.172062, -1.134426, -0.850570",\
+ "-1.495438, -1.453061, -1.418482, -1.380846, -1.096990");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.930240, -0.887863, -0.853283, -0.815648, -0.531791",\
+ "-1.018219, -0.975842, -0.941263, -0.903627, -0.619771",\
+ "-1.114454, -1.072076, -1.037497, -0.999861, -0.716005",\
+ "-1.276772, -1.234395, -1.199815, -1.162180, -0.878323",\
+ "-1.549656, -1.507279, -1.472699, -1.435064, -1.151207");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[73]_hldr*/
+
+} /* end of pin tl_i[73] */
+
+pin("tl_i[72]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001514 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[72];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.995496, 4.949341, 4.919124, 4.907767, 4.921374",\
+ "5.088820, 5.042665, 5.012448, 5.001091, 5.014698",\
+ "5.200553, 5.154398, 5.124181, 5.112824, 5.126431",\
+ "5.410159, 5.364004, 5.333787, 5.322430, 5.336038",\
+ "5.770847, 5.724692, 5.694476, 5.683118, 5.696726");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.983222, 4.937068, 4.906851, 4.895494, 4.909101",\
+ "5.083534, 5.037379, 5.007162, 4.995805, 5.009412",\
+ "5.216234, 5.170079, 5.139863, 5.128505, 5.142113",\
+ "5.462753, 5.416598, 5.386382, 5.375024, 5.388632",\
+ "5.894033, 5.847878, 5.817662, 5.806304, 5.819912");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[72]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.828673, -0.786296, -0.751717, -0.714081, -0.430225",\
+ "-0.916407, -0.874030, -0.839450, -0.801815, -0.517958",\
+ "-1.009412, -0.967034, -0.932455, -0.894819, -0.610963",\
+ "-1.161535, -1.119158, -1.084578, -1.046943, -0.763086",\
+ "-1.413529, -1.371152, -1.336573, -1.298937, -1.015081");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.840436, -0.798058, -0.763479, -0.725843, -0.441987",\
+ "-0.930307, -0.887930, -0.853350, -0.815715, -0.531858",\
+ "-1.024595, -0.982218, -0.947639, -0.910003, -0.626147",\
+ "-1.178880, -1.136502, -1.101923, -1.064288, -0.780431",\
+ "-1.440355, -1.397978, -1.363399, -1.325763, -1.041907");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[72]_hldr*/
+
+} /* end of pin tl_i[72] */
+
+pin("tl_i[71]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002444 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[71];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.540210, 5.494055, 5.463838, 5.452481, 5.466088",\
+ "5.637518, 5.591363, 5.561146, 5.549789, 5.563396",\
+ "5.743839, 5.697684, 5.667468, 5.656110, 5.669718",\
+ "5.935360, 5.889205, 5.858988, 5.847631, 5.861238",\
+ "6.275519, 6.229364, 6.199148, 6.187790, 6.201398");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.544911, 5.498756, 5.468540, 5.457182, 5.470790",\
+ "5.643330, 5.597175, 5.566958, 5.555601, 5.569208",\
+ "5.758502, 5.712348, 5.682131, 5.670774, 5.684381",\
+ "5.954805, 5.908650, 5.878434, 5.867076, 5.880684",\
+ "6.290164, 6.244009, 6.213792, 6.202435, 6.216042");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[71]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.882892, -0.840514, -0.805935, -0.768299, -0.484443",\
+ "-0.976532, -0.934155, -0.899575, -0.861940, -0.578083",\
+ "-1.091232, -1.048855, -1.014276, -0.976640, -0.692784",\
+ "-1.273476, -1.231099, -1.196519, -1.158884, -0.875027",\
+ "-1.558704, -1.516327, -1.481747, -1.444112, -1.160255");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.918558, -0.876180, -0.841601, -0.803965, -0.520109",\
+ "-1.009478, -0.967101, -0.932522, -0.894886, -0.611030",\
+ "-1.111122, -1.068745, -1.034165, -0.996530, -0.712673",\
+ "-1.293967, -1.251589, -1.217010, -1.179375, -0.895518",\
+ "-1.608551, -1.566173, -1.531594, -1.493959, -1.210102");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[71]_hldr*/
+
+} /* end of pin tl_i[71] */
+
+pin("tl_i[70]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002521 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[70];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.558736, 5.512581, 5.482364, 5.471007, 5.484614",\
+ "5.646551, 5.600396, 5.570179, 5.558822, 5.572429",\
+ "5.751346, 5.705191, 5.674974, 5.663617, 5.677224",\
+ "5.931952, 5.885797, 5.855580, 5.844223, 5.857830",\
+ "6.227381, 6.181226, 6.151009, 6.139652, 6.153259");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.559927, 5.513772, 5.483556, 5.472198, 5.485806",\
+ "5.643667, 5.597512, 5.567295, 5.555938, 5.569545",\
+ "5.760825, 5.714670, 5.684453, 5.673096, 5.686704",\
+ "5.980465, 5.934310, 5.904093, 5.892736, 5.906343",\
+ "6.363138, 6.316983, 6.286767, 6.275409, 6.289017");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[70]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.108714, -1.066337, -1.031757, -0.994122, -0.710265",\
+ "-1.197711, -1.155334, -1.120755, -1.083119, -0.799263",\
+ "-1.273206, -1.230828, -1.196249, -1.158614, -0.874757",\
+ "-1.400542, -1.358165, -1.323586, -1.285950, -1.002094",\
+ "-1.588133, -1.545756, -1.511176, -1.473541, -1.189684");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.109905, -1.067528, -1.032949, -0.995313, -0.711457",\
+ "-1.194827, -1.152450, -1.117871, -1.080235, -0.796379",\
+ "-1.282685, -1.240308, -1.205728, -1.168093, -0.884236",\
+ "-1.434258, -1.391881, -1.357301, -1.319666, -1.035809",\
+ "-1.689183, -1.646805, -1.612226, -1.574591, -1.290734");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[70]_hldr*/
+
+} /* end of pin tl_i[70] */
+
+pin("tl_i[69]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.003551 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[69];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.599169, 5.553014, 5.522797, 5.511440, 5.525047",\
+ "5.692371, 5.646216, 5.615999, 5.604642, 5.618249",\
+ "5.803999, 5.757844, 5.727628, 5.716270, 5.729878",\
+ "6.013692, 5.967537, 5.937320, 5.925963, 5.939570",\
+ "6.374660, 6.328505, 6.298288, 6.286931, 6.300539");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.586902, 5.540747, 5.510530, 5.499173, 5.512780",\
+ "5.687091, 5.640936, 5.610719, 5.599362, 5.612969",\
+ "5.819899, 5.773744, 5.743527, 5.732170, 5.745778",\
+ "6.066907, 6.020752, 5.990536, 5.979178, 5.992786",\
+ "6.499193, 6.453038, 6.422822, 6.411464, 6.425072");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[69]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.320298, -0.254656, -0.197381, -0.155524, 0.065753",\
+ "-0.418767, -0.353125, -0.295851, -0.253993, -0.032716",\
+ "-0.541359, -0.475718, -0.418443, -0.376585, -0.155308",\
+ "-0.758841, -0.693200, -0.635925, -0.594067, -0.372790",\
+ "-1.125992, -1.060351, -1.003076, -0.961219, -0.690840");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.551837, -0.504668, -0.447037, -0.405084, -0.122660",\
+ "-0.642640, -0.595471, -0.537840, -0.495887, -0.213464",\
+ "-0.748319, -0.701138, -0.643507, -0.601553, -0.319143",\
+ "-0.935804, -0.888444, -0.830813, -0.788860, -0.506627",\
+ "-1.256943, -1.209575, -1.151944, -1.109991, -0.827767");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[69]_hldr*/
+
+} /* end of pin tl_i[69] */
+
+pin("tl_i[68]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.003064 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[68];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.192542, 5.146387, 5.116170, 5.104813, 5.118420",\
+ "5.290967, 5.244812, 5.214595, 5.203238, 5.216846",\
+ "5.401109, 5.354954, 5.324737, 5.313380, 5.326987",\
+ "5.601238, 5.555083, 5.524867, 5.513509, 5.527117",\
+ "5.960707, 5.914552, 5.884336, 5.872978, 5.886586");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.225666, 5.179511, 5.149294, 5.137937, 5.151545",\
+ "5.325410, 5.279255, 5.249039, 5.237681, 5.251289",\
+ "5.445796, 5.399642, 5.369425, 5.358068, 5.371675",\
+ "5.657081, 5.610926, 5.580709, 5.569352, 5.582960",\
+ "6.029737, 5.983582, 5.953365, 5.942008, 5.955616");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[68]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.383405, -0.317283, -0.259327, -0.217286, 0.002808",\
+ "-0.476585, -0.410463, -0.352507, -0.310465, -0.090372",\
+ "-0.609199, -0.543558, -0.486283, -0.444425, -0.212329",\
+ "-0.768597, -0.702956, -0.645681, -0.603824, -0.382547",\
+ "-1.029441, -0.963800, -0.906525, -0.864667, -0.643390");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.807548, -0.765101, -0.730685, -0.689878, -0.366659",\
+ "-0.886339, -0.843892, -0.809476, -0.768669, -0.445450",\
+ "-0.998027, -0.955579, -0.921164, -0.880357, -0.557138",\
+ "-1.202545, -1.160097, -1.125682, -1.084875, -0.761656",\
+ "-1.556186, -1.513738, -1.479323, -1.438516, -1.115297");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[68]_hldr*/
+
+} /* end of pin tl_i[68] */
+
+pin("tl_i[67]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.004926 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[67];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.584554, 5.538399, 5.508182, 5.496825, 5.510432",\
+ "5.677766, 5.631611, 5.601395, 5.590037, 5.603645",\
+ "5.772066, 5.725911, 5.695694, 5.684337, 5.697944",\
+ "5.938811, 5.892656, 5.862439, 5.851082, 5.864689",\
+ "6.232008, 6.185853, 6.155637, 6.144279, 6.157887");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.609763, 5.563608, 5.533391, 5.522034, 5.535642",\
+ "5.706739, 5.660584, 5.630367, 5.619010, 5.632617",\
+ "5.807685, 5.761530, 5.731313, 5.719956, 5.733563",\
+ "5.987043, 5.940888, 5.910672, 5.899314, 5.912922",\
+ "6.348396, 6.302241, 6.272024, 6.260667, 6.274274");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[67]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.485126, -0.438062, -0.380431, -0.338477, -0.011156",\
+ "-0.583825, -0.522452, -0.464496, -0.422454, -0.110899",\
+ "-0.666073, -0.599951, -0.541995, -0.499953, -0.221634",\
+ "-0.802234, -0.736112, -0.678156, -0.636114, -0.414195",\
+ "-1.028199, -0.962077, -0.904121, -0.862080, -0.641986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.387383, -0.321742, -0.264467, -0.222610, -0.001333",\
+ "-0.478290, -0.412648, -0.355373, -0.313516, -0.092239",\
+ "-0.583616, -0.517975, -0.460700, -0.418842, -0.197565",\
+ "-0.772257, -0.706615, -0.649340, -0.607483, -0.386206",\
+ "-1.096755, -1.031114, -0.973839, -0.931981, -0.710704");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[67]_hldr*/
+
+} /* end of pin tl_i[67] */
+
+pin("tl_i[66]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.005701 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[66];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.639438, 5.593283, 5.563066, 5.551709, 5.565317",\
+ "5.733038, 5.686883, 5.656666, 5.645309, 5.658916",\
+ "5.848727, 5.802572, 5.772356, 5.760998, 5.774606",\
+ "6.068509, 6.022354, 5.992137, 5.980780, 5.994387",\
+ "6.462988, 6.416833, 6.386617, 6.375259, 6.388867");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.621106, 5.574951, 5.544734, 5.533377, 5.546984",\
+ "5.717392, 5.671237, 5.641021, 5.629663, 5.643271",\
+ "5.853546, 5.807391, 5.777174, 5.765817, 5.779424",\
+ "6.124442, 6.078287, 6.048070, 6.036713, 6.050320",\
+ "6.621989, 6.575834, 6.545618, 6.534260, 6.547868");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[66]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.421962, -0.356320, -0.299045, -0.257188, -0.035911",\
+ "-0.516417, -0.450775, -0.393500, -0.351643, -0.130366",\
+ "-0.609921, -0.544280, -0.487005, -0.445147, -0.223870",\
+ "-0.772065, -0.706424, -0.649149, -0.607291, -0.386014",\
+ "-0.961881, -0.895759, -0.837803, -0.795761, -0.575668");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.486628, -0.441846, -0.402838, -0.353988, 0.043935",\
+ "-0.578095, -0.533313, -0.494305, -0.445455, -0.047532",\
+ "-0.684334, -0.639552, -0.600544, -0.551694, -0.153771",\
+ "-0.874257, -0.829475, -0.790467, -0.741616, -0.343693",\
+ "-1.203886, -1.159104, -1.120096, -1.071246, -0.673323");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[66]_hldr*/
+
+} /* end of pin tl_i[66] */
+
+pin("tl_i[65]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.005716 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[65];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.459126, 5.412971, 5.382754, 5.371397, 5.385004",\
+ "5.554200, 5.508045, 5.477829, 5.466471, 5.480079",\
+ "5.677998, 5.631843, 5.601626, 5.590269, 5.603877",\
+ "5.927989, 5.881835, 5.851618, 5.840261, 5.853868",\
+ "6.397048, 6.350893, 6.320677, 6.309319, 6.322927");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.446668, 5.400513, 5.370296, 5.358939, 5.372547",\
+ "5.539561, 5.493406, 5.463189, 5.451832, 5.465439",\
+ "5.673235, 5.627080, 5.596863, 5.585506, 5.599113",\
+ "5.960149, 5.913994, 5.883777, 5.872420, 5.886027",\
+ "6.505686, 6.459531, 6.429315, 6.417957, 6.431565");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[65]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.425878, -0.360237, -0.302962, -0.261104, -0.039827",\
+ "-0.522669, -0.457028, -0.399753, -0.357895, -0.136618",\
+ "-0.621719, -0.556077, -0.498802, -0.456945, -0.235668",\
+ "-0.791700, -0.725578, -0.667622, -0.625580, -0.405487",\
+ "-0.986124, -0.920002, -0.862046, -0.820004, -0.599911");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.460052, -0.415270, -0.376262, -0.327412, 0.070511",\
+ "-0.556623, -0.511841, -0.472833, -0.423982, -0.026060",\
+ "-0.658589, -0.613808, -0.574799, -0.525949, -0.128026",\
+ "-0.841385, -0.796603, -0.757595, -0.708745, -0.310822",\
+ "-1.144313, -1.099531, -1.060523, -1.011673, -0.613750");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[65]_hldr*/
+
+} /* end of pin tl_i[65] */
+
+pin("tl_i[64]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.004569 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[64];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.444655, 5.398500, 5.368283, 5.356926, 5.370533",\
+ "5.543582, 5.497427, 5.467211, 5.455853, 5.469461",\
+ "5.653337, 5.607182, 5.576965, 5.565608, 5.579216",\
+ "5.851637, 5.805482, 5.775266, 5.763908, 5.777516",\
+ "6.204331, 6.158176, 6.127959, 6.116602, 6.130209");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.478401, 5.432246, 5.402030, 5.390672, 5.404280",\
+ "5.578437, 5.532282, 5.502066, 5.490708, 5.504316",\
+ "5.698844, 5.652689, 5.622473, 5.611115, 5.624723",\
+ "5.908003, 5.861848, 5.831632, 5.820274, 5.833882",\
+ "6.273140, 6.226985, 6.196769, 6.185411, 6.199019");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[64]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.425314, -0.367605, -0.313198, -0.274713, -0.048281",\
+ "-0.523194, -0.465485, -0.411079, -0.372594, -0.146162",\
+ "-0.645804, -0.588095, -0.533688, -0.495204, -0.268772",\
+ "-0.855838, -0.798129, -0.743723, -0.705238, -0.478806",\
+ "-1.193156, -1.127033, -1.069077, -1.027036, -0.806943");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.376914, -0.311272, -0.253997, -0.212140, 0.059682",\
+ "-0.475849, -0.410207, -0.352932, -0.311075, -0.039253",\
+ "-0.593819, -0.528177, -0.470902, -0.429045, -0.157173",\
+ "-0.797684, -0.732042, -0.674767, -0.632910, -0.360732",\
+ "-1.142024, -1.076383, -1.019108, -0.977250, -0.703048");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[64]_hldr*/
+
+} /* end of pin tl_i[64] */
+
+pin("tl_i[63]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.005918 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[63];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.634018, 5.587863, 5.557646, 5.546289, 5.559896",\
+ "5.727260, 5.681105, 5.650888, 5.639531, 5.653139",\
+ "5.821638, 5.775483, 5.745266, 5.733909, 5.747517",\
+ "5.988543, 5.942388, 5.912171, 5.900814, 5.914422",\
+ "6.282049, 6.235894, 6.205677, 6.194320, 6.207927");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.659294, 5.613139, 5.582922, 5.571565, 5.585172",\
+ "5.756288, 5.710133, 5.679916, 5.668559, 5.682167",\
+ "5.857348, 5.811193, 5.780976, 5.769619, 5.783226",\
+ "6.036880, 5.990726, 5.960509, 5.949152, 5.962759",\
+ "6.341727, 6.295572, 6.265355, 6.253998, 6.267605");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[63]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.425078, -0.367369, -0.312962, -0.274477, -0.048046",\
+ "-0.523533, -0.465824, -0.411418, -0.372933, -0.146501",\
+ "-0.649060, -0.591351, -0.536945, -0.498460, -0.272028",\
+ "-0.863705, -0.805996, -0.751590, -0.713105, -0.486673",\
+ "-1.108760, -1.042638, -0.984682, -0.942640, -0.722547");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.375262, -0.309621, -0.252346, -0.210488, 0.061380",\
+ "-0.475435, -0.409794, -0.352519, -0.310661, -0.038785",\
+ "-0.593964, -0.528323, -0.471048, -0.429190, -0.157265",\
+ "-0.799253, -0.733611, -0.676336, -0.634479, -0.362291",\
+ "-1.146486, -1.080845, -1.023570, -0.981712, -0.707386");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[63]_hldr*/
+
+} /* end of pin tl_i[63] */
+
+pin("tl_i[62]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.005914 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[62];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.028421, 4.982266, 4.952050, 4.940692, 4.954300",\
+ "5.115734, 5.069579, 5.039362, 5.028005, 5.041612",\
+ "5.221791, 5.175636, 5.145419, 5.134062, 5.147669",\
+ "5.411152, 5.364997, 5.334780, 5.323423, 5.337030",\
+ "5.716925, 5.670770, 5.640553, 5.629196, 5.642803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.030477, 4.984322, 4.954105, 4.942748, 4.956356",\
+ "5.112976, 5.066821, 5.036604, 5.025247, 5.038854",\
+ "5.241773, 5.195618, 5.165401, 5.154044, 5.167651",\
+ "5.477729, 5.431574, 5.401357, 5.390000, 5.403607",\
+ "5.884023, 5.837868, 5.807651, 5.796294, 5.809901");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[62]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.310949, -0.245308, -0.188033, -0.146175, 0.125715",\
+ "-0.408722, -0.343080, -0.285805, -0.243948, 0.028056",\
+ "-0.525662, -0.460020, -0.402745, -0.360888, -0.087938",\
+ "-0.729867, -0.664225, -0.606950, -0.565093, -0.287448",\
+ "-1.073045, -1.007404, -0.950129, -0.908272, -0.621407");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.560733, -0.518534, -0.464760, -0.422807, -0.191354",\
+ "-0.659844, -0.617645, -0.563872, -0.521919, -0.290465",\
+ "-0.778888, -0.736689, -0.682928, -0.640975, -0.409521",\
+ "-0.986411, -0.944213, -0.890754, -0.848801, -0.617348",\
+ "-1.324035, -1.281784, -1.238624, -1.196671, -0.966234");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[62]_hldr*/
+
+} /* end of pin tl_i[62] */
+
+pin("tl_i[61]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.004650 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[61];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.050911, 5.004756, 4.974539, 4.963182, 4.976789",\
+ "5.138693, 5.092538, 5.062321, 5.050964, 5.064571",\
+ "5.242861, 5.196706, 5.166489, 5.155132, 5.168739",\
+ "5.438320, 5.392165, 5.361948, 5.350591, 5.364199",\
+ "5.753279, 5.707124, 5.676907, 5.665550, 5.679157");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.054683, 5.008528, 4.978311, 4.966954, 4.980561",\
+ "5.137789, 5.091634, 5.061417, 5.050060, 5.063667",\
+ "5.257940, 5.211785, 5.181569, 5.170211, 5.183819",\
+ "5.493972, 5.447817, 5.417600, 5.406243, 5.419850",\
+ "5.883592, 5.837437, 5.807220, 5.795863, 5.809470");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[61]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.331346, -0.288929, -0.254443, -0.214995, 0.091355",\
+ "-0.415000, -0.372583, -0.338097, -0.298649, 0.007701",\
+ "-0.498520, -0.456102, -0.421616, -0.382169, -0.075818",\
+ "-0.644671, -0.602253, -0.567767, -0.528320, -0.221969",\
+ "-0.885228, -0.842810, -0.808325, -0.768877, -0.462526");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.495414, -0.429474, -0.371779, -0.329808, -0.077326",\
+ "-0.577402, -0.511461, -0.453767, -0.411796, -0.165065",\
+ "-0.669896, -0.603956, -0.546261, -0.504290, -0.256735",\
+ "-0.831937, -0.776516, -0.718821, -0.676851, -0.409235",\
+ "-1.083366, -1.040949, -1.006463, -0.967015, -0.660665");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[61]_hldr*/
+
+} /* end of pin tl_i[61] */
+
+pin("tl_i[60]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.004493 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[60];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.075901, 5.029746, 4.999529, 4.988172, 5.001780",\
+ "5.162810, 5.116655, 5.086439, 5.075081, 5.088689",\
+ "5.262701, 5.216546, 5.186329, 5.174972, 5.188580",\
+ "5.463603, 5.417448, 5.387231, 5.375874, 5.389482",\
+ "5.887491, 5.841336, 5.811120, 5.799762, 5.813370");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.069137, 5.022982, 4.992765, 4.981408, 4.995015",\
+ "5.162019, 5.115864, 5.085647, 5.074290, 5.087897",\
+ "5.289857, 5.243702, 5.213485, 5.202128, 5.215735",\
+ "5.547719, 5.501564, 5.471347, 5.459990, 5.473598",\
+ "5.999206, 5.953051, 5.922834, 5.911477, 5.925084");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[60]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.331961, -0.289544, -0.255058, -0.215610, 0.090740",\
+ "-0.416689, -0.374271, -0.339785, -0.300337, 0.006013",\
+ "-0.501750, -0.459332, -0.424846, -0.385399, -0.079048",\
+ "-0.650840, -0.608422, -0.573936, -0.534488, -0.228138",\
+ "-0.898578, -0.856161, -0.821675, -0.782227, -0.475877");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.494855, -0.428915, -0.371220, -0.329249, -0.108704",\
+ "-0.577203, -0.511263, -0.453568, -0.411597, -0.191052",\
+ "-0.675131, -0.609191, -0.551496, -0.509525, -0.288980",\
+ "-0.848911, -0.782971, -0.725276, -0.683305, -0.462760",\
+ "-1.143176, -1.077236, -1.019541, -0.977570, -0.757025");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[60]_hldr*/
+
+} /* end of pin tl_i[60] */
+
+pin("tl_i[59]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.004673 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[59];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.018675, 4.972520, 4.942304, 4.930946, 4.944554",\
+ "5.111604, 5.065449, 5.035232, 5.023875, 5.037482",\
+ "5.204963, 5.158808, 5.128592, 5.117234, 5.130842",\
+ "5.368355, 5.322200, 5.291983, 5.280626, 5.294233",\
+ "5.654718, 5.608563, 5.578346, 5.566989, 5.580596");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.048488, 5.002333, 4.972116, 4.960759, 4.974366",\
+ "5.145526, 5.099371, 5.069155, 5.057797, 5.071405",\
+ "5.246175, 5.200020, 5.169804, 5.158446, 5.172054",\
+ "5.423032, 5.376877, 5.346661, 5.335303, 5.348911",\
+ "5.720785, 5.674630, 5.644413, 5.633056, 5.646663");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[59]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.399850, -0.333910, -0.276215, -0.234244, -0.013699",\
+ "-0.490388, -0.424448, -0.366753, -0.324782, -0.104237",\
+ "-0.591764, -0.525824, -0.468129, -0.426158, -0.205613",\
+ "-0.771660, -0.705720, -0.648025, -0.606054, -0.385509",\
+ "-1.061324, -0.995383, -0.937689, -0.895718, -0.675172");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.408211, -0.365794, -0.331308, -0.291860, 0.014490",\
+ "-0.495065, -0.452648, -0.418162, -0.378714, -0.072363",\
+ "-0.606791, -0.564374, -0.529888, -0.490440, -0.184090",\
+ "-0.793280, -0.750863, -0.716377, -0.676929, -0.370579",\
+ "-1.099378, -1.056960, -1.022474, -0.983027, -0.676676");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[59]_hldr*/
+
+} /* end of pin tl_i[59] */
+
+pin("tl_i[58]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.005086 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[58];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.907104, 4.860949, 4.830732, 4.819375, 4.832983",\
+ "4.992526, 4.946371, 4.916154, 4.904797, 4.918404",\
+ "5.070096, 5.023941, 4.993724, 4.982367, 4.995975",\
+ "5.244753, 5.198598, 5.168381, 5.157024, 5.170631",\
+ "5.599957, 5.553802, 5.523586, 5.512228, 5.525836");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.904143, 4.857988, 4.827772, 4.816414, 4.830022",\
+ "4.986795, 4.940640, 4.910424, 4.899066, 4.912674",\
+ "5.098862, 5.052707, 5.022491, 5.011133, 5.024741",\
+ "5.327568, 5.281413, 5.251196, 5.239839, 5.253446",\
+ "5.728967, 5.682812, 5.652596, 5.641238, 5.654846");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[58]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.409769, -0.343829, -0.286134, -0.244163, -0.023618",\
+ "-0.498234, -0.432294, -0.374599, -0.332628, -0.112083",\
+ "-0.599794, -0.533854, -0.476159, -0.434188, -0.213643",\
+ "-0.781831, -0.715891, -0.658196, -0.616225, -0.395680",\
+ "-1.087101, -1.021161, -0.963466, -0.921496, -0.700950");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.423427, -0.381010, -0.346524, -0.307076, -0.000726",\
+ "-0.507266, -0.464848, -0.430363, -0.390915, -0.084564",\
+ "-0.628312, -0.585894, -0.551408, -0.511960, -0.205610",\
+ "-0.825686, -0.783269, -0.748783, -0.709335, -0.402985",\
+ "-1.126419, -1.084002, -1.049516, -1.010068, -0.703718");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[58]_hldr*/
+
+} /* end of pin tl_i[58] */
+
+pin("tl_i[57]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.004084 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[57];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.853275, 4.807120, 4.776903, 4.765546, 4.779153",\
+ "4.941780, 4.895625, 4.865408, 4.854051, 4.867658",\
+ "5.043512, 4.997357, 4.967141, 4.955783, 4.969391",\
+ "5.245644, 5.199489, 5.169272, 5.157915, 5.171523",\
+ "5.684921, 5.638766, 5.608549, 5.597192, 5.610799");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.846420, 4.800265, 4.770049, 4.758691, 4.772299",\
+ "4.940993, 4.894838, 4.864621, 4.853264, 4.866871",\
+ "5.069371, 5.023216, 4.992999, 4.981642, 4.995249",\
+ "5.318837, 5.272682, 5.242465, 5.231108, 5.244716",\
+ "5.754844, 5.708689, 5.678472, 5.667115, 5.680722");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[57]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.439430, -0.373490, -0.315795, -0.273825, -0.053279",\
+ "-0.519622, -0.453682, -0.395987, -0.354016, -0.133471",\
+ "-0.597395, -0.531455, -0.473760, -0.431789, -0.211244",\
+ "-0.729801, -0.663861, -0.606166, -0.564195, -0.343650",\
+ "-0.935990, -0.870050, -0.812355, -0.770384, -0.549839");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.409353, -0.366935, -0.332449, -0.293002, 0.013349",\
+ "-0.497213, -0.454795, -0.420310, -0.380862, -0.074511",\
+ "-0.585629, -0.543211, -0.508725, -0.469278, -0.162927",\
+ "-0.741802, -0.699385, -0.664899, -0.625451, -0.319101",\
+ "-0.995469, -0.953051, -0.918565, -0.879117, -0.572767");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[57]_hldr*/
+
+} /* end of pin tl_i[57] */
+
+pin("tl_i[56]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.005633 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[56];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.771066, 4.724911, 4.694694, 4.683337, 4.696944",\
+ "4.860967, 4.814812, 4.784595, 4.773238, 4.786846",\
+ "4.953480, 4.907325, 4.877108, 4.865751, 4.879358",\
+ "5.122646, 5.076491, 5.046274, 5.034917, 5.048524",\
+ "5.508491, 5.462336, 5.432119, 5.420762, 5.434369");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.784305, 4.738150, 4.707933, 4.696576, 4.710184",\
+ "4.872721, 4.826566, 4.796349, 4.784992, 4.798599",\
+ "4.991727, 4.945572, 4.915355, 4.903998, 4.917605",\
+ "5.265233, 5.219078, 5.188861, 5.177504, 5.191111",\
+ "5.790774, 5.744619, 5.714402, 5.703045, 5.716652");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[56]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.441652, -0.375711, -0.318017, -0.276046, -0.055500",\
+ "-0.524614, -0.458674, -0.400979, -0.359008, -0.138463",\
+ "-0.607820, -0.541879, -0.484185, -0.442214, -0.221668",\
+ "-0.753165, -0.687225, -0.629530, -0.587559, -0.367014",\
+ "-0.987968, -0.922028, -0.864333, -0.822362, -0.601816");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.411476, -0.369059, -0.334573, -0.295125, 0.011225",\
+ "-0.499637, -0.457219, -0.422733, -0.383285, -0.076935",\
+ "-0.588334, -0.545917, -0.511431, -0.471983, -0.165633",\
+ "-0.746601, -0.704183, -0.669698, -0.630250, -0.323899",\
+ "-1.003694, -0.961277, -0.926791, -0.887343, -0.580993");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[56]_hldr*/
+
+} /* end of pin tl_i[56] */
+
+pin("tl_i[55]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.023564 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[55];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.825782, 5.779627, 5.749410, 5.738052, 5.751660",\
+ "5.912527, 5.866372, 5.836155, 5.824798, 5.838405",\
+ "6.021775, 5.975620, 5.945403, 5.934046, 5.947653",\
+ "6.207016, 6.160861, 6.130644, 6.119287, 6.132894",\
+ "6.502526, 6.456371, 6.426154, 6.414796, 6.428404");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.826127, 5.779972, 5.749755, 5.738398, 5.752005",\
+ "5.912270, 5.866115, 5.835897, 5.824540, 5.838148",\
+ "6.043355, 5.997200, 5.966982, 5.955625, 5.969233",\
+ "6.273898, 6.227743, 6.197526, 6.186169, 6.199776",\
+ "6.665429, 6.619274, 6.589057, 6.577700, 6.591307");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[55]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\
+ "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\
+ "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\
+ "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\
+ "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[55]_hldr*/
+
+} /* end of pin tl_i[55] */
+
+pin("tl_i[54]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.024771 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[54];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.671892, 5.625737, 5.595520, 5.584163, 5.597770",\
+ "5.766703, 5.720548, 5.690331, 5.678973, 5.692581",\
+ "5.865909, 5.819754, 5.789536, 5.778179, 5.791787",\
+ "6.041008, 5.994853, 5.964636, 5.953279, 5.966886",\
+ "6.340645, 6.294490, 6.264273, 6.252915, 6.266523");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.706592, 5.660437, 5.630219, 5.618862, 5.632470",\
+ "5.804386, 5.758231, 5.728014, 5.716657, 5.730264",\
+ "5.910204, 5.864049, 5.833832, 5.822474, 5.836082",\
+ "6.089930, 6.043775, 6.013557, 6.002200, 6.015808",\
+ "6.385911, 6.339756, 6.309539, 6.298182, 6.311790");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[54]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\
+ "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\
+ "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\
+ "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\
+ "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[54]_hldr*/
+
+} /* end of pin tl_i[54] */
+
+pin("tl_i[53]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.025984 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[53];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.405560, 5.359406, 5.329188, 5.317831, 5.331439",\
+ "5.489668, 5.443513, 5.413296, 5.401938, 5.415546",\
+ "5.570677, 5.524522, 5.494305, 5.482947, 5.496555",\
+ "5.711991, 5.665836, 5.635619, 5.624262, 5.637869",\
+ "5.953867, 5.907712, 5.877495, 5.866138, 5.879745");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.390637, 5.344482, 5.314265, 5.302907, 5.316515",\
+ "5.472354, 5.426199, 5.395982, 5.384624, 5.398232",\
+ "5.578566, 5.532411, 5.502193, 5.490836, 5.504444",\
+ "5.766796, 5.720641, 5.690423, 5.679066, 5.692674",\
+ "6.084168, 6.038013, 6.007796, 5.996439, 6.010046");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[53]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\
+ "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\
+ "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\
+ "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\
+ "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[53]_hldr*/
+
+} /* end of pin tl_i[53] */
+
+pin("tl_i[52]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.023928 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[52];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.851366, 5.805211, 5.774994, 5.763637, 5.777244",\
+ "5.940992, 5.894837, 5.864620, 5.853263, 5.866870",\
+ "6.046589, 6.000434, 5.970217, 5.958859, 5.972467",\
+ "6.242908, 6.196754, 6.166536, 6.155179, 6.168787",\
+ "6.655770, 6.609615, 6.579398, 6.568040, 6.581648");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.844427, 5.798272, 5.768054, 5.756697, 5.770305",\
+ "5.940210, 5.894055, 5.863838, 5.852481, 5.866088",\
+ "6.071230, 6.025075, 5.994858, 5.983501, 5.997108",\
+ "6.314948, 6.268793, 6.238575, 6.227218, 6.240826",\
+ "6.731011, 6.684856, 6.654639, 6.643281, 6.656889");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[52]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\
+ "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\
+ "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\
+ "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\
+ "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[52]_hldr*/
+
+} /* end of pin tl_i[52] */
+
+pin("tl_i[51]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.024747 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[51];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.766789, 5.720634, 5.690417, 5.679060, 5.692667",\
+ "5.856632, 5.810477, 5.780260, 5.768903, 5.782510",\
+ "5.949137, 5.902982, 5.872765, 5.861408, 5.875015",\
+ "6.115034, 6.068879, 6.038662, 6.027305, 6.040912",\
+ "6.488516, 6.442361, 6.412144, 6.400786, 6.414394");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.777621, 5.731466, 5.701249, 5.689892, 5.703499",\
+ "5.868374, 5.822219, 5.792002, 5.780644, 5.794252",\
+ "5.987092, 5.940937, 5.910720, 5.899363, 5.912970",\
+ "6.219129, 6.172974, 6.142756, 6.131399, 6.145007",\
+ "6.630526, 6.584371, 6.554153, 6.542796, 6.556404");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[51]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\
+ "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\
+ "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\
+ "-0.454534, -0.408918, -0.350984, -0.308948, -0.040427",\
+ "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[51]_hldr*/
+
+} /* end of pin tl_i[51] */
+
+pin("tl_i[50]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.024706 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[50];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.432938, 5.386783, 5.356565, 5.345208, 5.358816",\
+ "5.522908, 5.476753, 5.446536, 5.435179, 5.448786",\
+ "5.615422, 5.569267, 5.539050, 5.527693, 5.541300",\
+ "5.781178, 5.735023, 5.704806, 5.693449, 5.707057",\
+ "6.151173, 6.105018, 6.074801, 6.063444, 6.077051");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.443795, 5.397640, 5.367423, 5.356066, 5.369673",\
+ "5.534675, 5.488520, 5.458302, 5.446945, 5.460553",\
+ "5.653760, 5.607605, 5.577388, 5.566031, 5.579638",\
+ "5.885449, 5.839294, 5.809077, 5.797719, 5.811327",\
+ "6.297242, 6.251087, 6.220870, 6.209512, 6.223120");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[50]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\
+ "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\
+ "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\
+ "-0.454534, -0.408918, -0.350984, -0.308948, -0.040427",\
+ "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[50]_hldr*/
+
+} /* end of pin tl_i[50] */
+
+pin("tl_i[49]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.014215 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[49];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.612003, 5.565848, 5.535631, 5.524274, 5.537881",\
+ "5.697372, 5.651217, 5.621000, 5.609643, 5.623250",\
+ "5.774767, 5.728612, 5.698395, 5.687037, 5.700645",\
+ "5.943757, 5.897602, 5.867384, 5.856027, 5.869635",\
+ "6.302785, 6.256630, 6.226413, 6.215055, 6.228663");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.608959, 5.562804, 5.532587, 5.521230, 5.534837",\
+ "5.691543, 5.645388, 5.615170, 5.603813, 5.617421",\
+ "5.803527, 5.757372, 5.727155, 5.715797, 5.729405",\
+ "6.034389, 5.988234, 5.958016, 5.946659, 5.960267",\
+ "6.439312, 6.393157, 6.362939, 6.351582, 6.365190");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[49]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.042324, -0.000326, 0.287989",\
+ "-0.219595, -0.177177, -0.128664, -0.086666, 0.203312",\
+ "-0.307616, -0.265198, -0.213787, -0.171789, 0.115291",\
+ "-0.454448, -0.412253, -0.355362, -0.313364, -0.040427",\
+ "-0.692896, -0.635483, -0.577488, -0.535436, -0.297932");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[49]_hldr*/
+
+} /* end of pin tl_i[49] */
+
+pin("tl_i[48]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.015924 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[48];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.342521, 5.296366, 5.266149, 5.254791, 5.268399",\
+ "5.430000, 5.383845, 5.353628, 5.342271, 5.355878",\
+ "5.517300, 5.471145, 5.440928, 5.429570, 5.443178",\
+ "5.691890, 5.645735, 5.615518, 5.604160, 5.617768",\
+ "6.098689, 6.052534, 6.022317, 6.010960, 6.024567");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.337069, 5.290914, 5.260696, 5.249339, 5.262947",\
+ "5.426027, 5.379872, 5.349655, 5.338298, 5.351905",\
+ "5.541069, 5.494914, 5.464697, 5.453340, 5.466947",\
+ "5.778956, 5.732801, 5.702584, 5.691227, 5.704834",\
+ "6.214471, 6.168316, 6.138099, 6.126742, 6.140349");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[48]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.095389, -0.053327, -0.019395, 0.003631, 0.287989",\
+ "-0.178535, -0.136472, -0.102541, -0.079514, 0.203312",\
+ "-0.262969, -0.220876, -0.186811, -0.163726, 0.115291",\
+ "-0.399970, -0.357878, -0.323812, -0.300727, -0.040427",\
+ "-0.613644, -0.571552, -0.537486, -0.514401, -0.297932");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.127054, -0.062200, -0.008166, 0.033833, 0.254201",\
+ "-0.207506, -0.142652, -0.088847, -0.050549, 0.160177",\
+ "-0.300279, -0.235482, -0.181379, -0.142982, 0.068969",\
+ "-0.445930, -0.381133, -0.327029, -0.288632, -0.088057",\
+ "-0.677823, -0.613026, -0.558922, -0.520525, -0.325394");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[48]_hldr*/
+
+} /* end of pin tl_i[48] */
+
+pin("tl_i[47]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.015093 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[47];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.720613, 5.674458, 5.644240, 5.632883, 5.646491",\
+ "5.808302, 5.762147, 5.731930, 5.720572, 5.734180",\
+ "5.909732, 5.863577, 5.833360, 5.822003, 5.835610",\
+ "6.090167, 6.044012, 6.013794, 6.002437, 6.016045",\
+ "6.375024, 6.328869, 6.298652, 6.287294, 6.300902");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.723861, 5.677706, 5.647489, 5.636132, 5.649739",\
+ "5.806833, 5.760678, 5.730461, 5.719103, 5.732711",\
+ "5.923954, 5.877799, 5.847582, 5.836225, 5.849832",\
+ "6.142916, 6.096761, 6.066544, 6.055186, 6.068794",\
+ "6.505251, 6.459096, 6.428879, 6.417521, 6.431129");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[47]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\
+ "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\
+ "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\
+ "-0.454448, -0.412253, -0.355362, -0.313364, -0.040427",\
+ "-0.692896, -0.635483, -0.577488, -0.535436, -0.297932");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[47]_hldr*/
+
+} /* end of pin tl_i[47] */
+
+pin("tl_i[46]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.015694 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[46];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.747210, 5.701055, 5.670837, 5.659480, 5.673088",\
+ "5.834549, 5.788394, 5.758177, 5.746819, 5.760427",\
+ "5.931758, 5.885603, 5.855386, 5.844028, 5.857636",\
+ "6.119594, 6.073439, 6.043221, 6.031864, 6.045472",\
+ "6.512118, 6.465963, 6.435746, 6.424389, 6.437996");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.740419, 5.694264, 5.664047, 5.652689, 5.666297",\
+ "5.833758, 5.787603, 5.757386, 5.746029, 5.759636",\
+ "5.958529, 5.912374, 5.882157, 5.870800, 5.884408",\
+ "6.201867, 6.155712, 6.125495, 6.114138, 6.127745",\
+ "6.619649, 6.573494, 6.543277, 6.531919, 6.545527");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[46]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\
+ "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\
+ "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\
+ "-0.454448, -0.412253, -0.355362, -0.313364, -0.040427",\
+ "-0.692896, -0.635483, -0.577488, -0.535436, -0.297932");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[46]_hldr*/
+
+} /* end of pin tl_i[46] */
+
+pin("tl_i[45]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.017466 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[45];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.112432, 5.066278, 5.036060, 5.024703, 5.038311",\
+ "5.197829, 5.151674, 5.121457, 5.110100, 5.123707",\
+ "5.275316, 5.229161, 5.198944, 5.187587, 5.201194",\
+ "5.419477, 5.373322, 5.343104, 5.331747, 5.345355",\
+ "5.777201, 5.731046, 5.700829, 5.689471, 5.703079");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.109432, 5.063277, 5.033060, 5.021703, 5.035310",\
+ "5.192052, 5.145897, 5.115680, 5.104322, 5.117930",\
+ "5.304079, 5.257924, 5.227707, 5.216350, 5.229957",\
+ "5.534409, 5.488254, 5.458036, 5.446679, 5.460287",\
+ "5.938303, 5.892148, 5.861931, 5.850574, 5.864181");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[45]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.134918, -0.092500, -0.042324, -0.000326, 0.287989",\
+ "-0.219595, -0.177177, -0.128664, -0.086666, 0.203312",\
+ "-0.307616, -0.265198, -0.213787, -0.171789, 0.115291",\
+ "-0.454448, -0.408918, -0.350984, -0.308948, -0.040427",\
+ "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[45]_hldr*/
+
+} /* end of pin tl_i[45] */
+
+pin("tl_i[44]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.016255 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[44];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.787257, 5.741102, 5.710885, 5.699527, 5.713135",\
+ "5.887364, 5.841209, 5.810992, 5.799634, 5.813242",\
+ "6.003266, 5.957111, 5.926894, 5.915536, 5.929144",\
+ "6.212816, 6.166661, 6.136444, 6.125086, 6.138694",\
+ "6.574124, 6.527969, 6.497752, 6.486395, 6.500002");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.833889, 5.787734, 5.757517, 5.746160, 5.759767",\
+ "5.932858, 5.886703, 5.856485, 5.845128, 5.858736",\
+ "6.056724, 6.010569, 5.980351, 5.968994, 5.982602",\
+ "6.267234, 6.221079, 6.190862, 6.179505, 6.193112",\
+ "6.625524, 6.579369, 6.549152, 6.537795, 6.551402");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[44]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\
+ "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\
+ "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\
+ "-0.454448, -0.408918, -0.350984, -0.308948, -0.040427",\
+ "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\
+ "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\
+ "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[44]_hldr*/
+
+} /* end of pin tl_i[44] */
+
+pin("tl_i[43]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.018203 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[43];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.371556, 5.325401, 5.295184, 5.283827, 5.297434",\
+ "5.461463, 5.415308, 5.385091, 5.373734, 5.387341",\
+ "5.553976, 5.507821, 5.477604, 5.466247, 5.479854",\
+ "5.719817, 5.673662, 5.643445, 5.632088, 5.645695",\
+ "6.097318, 6.051163, 6.020946, 6.009588, 6.023196");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.382551, 5.336396, 5.306179, 5.294822, 5.308429",\
+ "5.473218, 5.427063, 5.396846, 5.385489, 5.399096",\
+ "5.592251, 5.546096, 5.515879, 5.504522, 5.518129",\
+ "5.824078, 5.777923, 5.747705, 5.736348, 5.749956",\
+ "6.235509, 6.189354, 6.159137, 6.147780, 6.161387");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[43]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\
+ "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\
+ "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\
+ "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[43]_hldr*/
+
+} /* end of pin tl_i[43] */
+
+pin("tl_i[42]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.019122 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[42];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.198272, 5.152117, 5.121900, 5.110542, 5.124150",\
+ "5.294228, 5.248073, 5.217855, 5.206498, 5.220106",\
+ "5.404464, 5.358309, 5.328092, 5.316734, 5.330342",\
+ "5.594985, 5.548830, 5.518613, 5.507256, 5.520863",\
+ "5.917032, 5.870877, 5.840660, 5.829302, 5.842910");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.190427, 5.144272, 5.114055, 5.102697, 5.116305",\
+ "5.291961, 5.245806, 5.215589, 5.204232, 5.217839",\
+ "5.417454, 5.371299, 5.341082, 5.329724, 5.343332",\
+ "5.634560, 5.588405, 5.558187, 5.546830, 5.560438",\
+ "6.000741, 5.954587, 5.924369, 5.913012, 5.926620");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[42]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\
+ "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\
+ "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\
+ "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[42]_hldr*/
+
+} /* end of pin tl_i[42] */
+
+pin("tl_i[41]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.022202 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[41];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.148859, 5.102704, 5.072487, 5.061130, 5.074737",\
+ "5.233216, 5.187061, 5.156844, 5.145487, 5.159094",\
+ "5.314116, 5.267961, 5.237743, 5.226386, 5.239994",\
+ "5.455597, 5.409442, 5.379225, 5.367867, 5.381475",\
+ "5.695938, 5.649783, 5.619565, 5.608208, 5.621816");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.134229, 5.088074, 5.057857, 5.046499, 5.060107",\
+ "5.215816, 5.169661, 5.139443, 5.128086, 5.141694",\
+ "5.322016, 5.275861, 5.245644, 5.234286, 5.247894",\
+ "5.510269, 5.464114, 5.433897, 5.422539, 5.436147",\
+ "5.825513, 5.779358, 5.749141, 5.737783, 5.751391");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[41]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\
+ "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\
+ "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\
+ "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[41]_hldr*/
+
+} /* end of pin tl_i[41] */
+
+pin("tl_i[40]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.021765 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[40];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.554589, 5.508434, 5.478217, 5.466860, 5.480467",\
+ "5.642064, 5.595909, 5.565692, 5.554335, 5.567942",\
+ "5.729364, 5.683209, 5.652992, 5.641635, 5.655242",\
+ "5.918046, 5.871891, 5.841674, 5.830317, 5.843924",\
+ "6.322921, 6.276766, 6.246549, 6.235191, 6.248799");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.549117, 5.502962, 5.472744, 5.461387, 5.474995",\
+ "5.638085, 5.591930, 5.561713, 5.550356, 5.563963",\
+ "5.753121, 5.706966, 5.676749, 5.665391, 5.678999",\
+ "5.991310, 5.945155, 5.914938, 5.903581, 5.917188",\
+ "6.427492, 6.381337, 6.351120, 6.339763, 6.353370");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[40]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\
+ "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\
+ "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\
+ "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\
+ "-0.716436, -0.659249, -0.601254, -0.559203, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[40]_hldr*/
+
+} /* end of pin tl_i[40] */
+
+pin("tl_i[39]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.017624 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[39];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.869242, 4.823087, 4.792870, 4.781513, 4.795120",\
+ "4.959149, 4.912994, 4.882777, 4.871420, 4.885027",\
+ "5.051662, 5.005507, 4.975290, 4.963933, 4.977540",\
+ "5.217504, 5.171349, 5.141131, 5.129774, 5.143382",\
+ "5.606756, 5.560601, 5.530384, 5.519027, 5.532634");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.880238, 4.834083, 4.803865, 4.792508, 4.806116",\
+ "4.970903, 4.924748, 4.894531, 4.883174, 4.896781",\
+ "5.089937, 5.043782, 5.013565, 5.002208, 5.015815",\
+ "5.321764, 5.275609, 5.245392, 5.234035, 5.247642",\
+ "5.733193, 5.687038, 5.656821, 5.645464, 5.659071");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[39]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\
+ "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\
+ "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\
+ "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[39]_hldr*/
+
+} /* end of pin tl_i[39] */
+
+pin("tl_i[38]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.020036 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[38];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.623479, 5.577324, 5.547107, 5.535749, 5.549357",\
+ "5.708911, 5.662756, 5.632539, 5.621181, 5.634789",\
+ "5.786510, 5.740355, 5.710137, 5.698780, 5.712388",\
+ "5.952927, 5.906772, 5.876554, 5.865197, 5.878805",\
+ "6.305354, 6.259199, 6.228982, 6.217625, 6.231232");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.620534, 5.574379, 5.544162, 5.532805, 5.546412",\
+ "5.703200, 5.657045, 5.626828, 5.615471, 5.629078",\
+ "5.815276, 5.769121, 5.738904, 5.727547, 5.741154",\
+ "6.045676, 5.999521, 5.969304, 5.957947, 5.971554",\
+ "6.448150, 6.401995, 6.371778, 6.360420, 6.374028");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[38]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\
+ "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\
+ "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\
+ "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[38]_hldr*/
+
+} /* end of pin tl_i[38] */
+
+pin("tl_i[37]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.020927 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[37];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.583619, 5.537464, 5.507247, 5.495890, 5.509497",\
+ "5.673532, 5.627377, 5.597160, 5.585803, 5.599410",\
+ "5.766046, 5.719891, 5.689674, 5.678317, 5.691924",\
+ "5.938797, 5.892642, 5.862425, 5.851068, 5.864676",\
+ "6.323754, 6.277599, 6.247382, 6.236025, 6.249632");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.594629, 5.548474, 5.518257, 5.506900, 5.520507",\
+ "5.685287, 5.639132, 5.608915, 5.597558, 5.611166",\
+ "5.804349, 5.758194, 5.727977, 5.716619, 5.730227",\
+ "6.036157, 5.990002, 5.959785, 5.948428, 5.962035",\
+ "6.447590, 6.401435, 6.371218, 6.359861, 6.373468");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[37]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\
+ "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\
+ "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\
+ "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[37]_hldr*/
+
+} /* end of pin tl_i[37] */
+
+pin("tl_i[36]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.022013 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[36];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.660564, 5.614409, 5.584192, 5.572835, 5.586442",\
+ "5.744962, 5.698807, 5.668590, 5.657232, 5.670840",\
+ "5.825815, 5.779660, 5.749443, 5.738086, 5.751693",\
+ "5.968822, 5.922667, 5.892449, 5.881092, 5.894700",\
+ "6.227637, 6.181482, 6.151265, 6.139908, 6.153515");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.645984, 5.599829, 5.569612, 5.558254, 5.571862",\
+ "5.727538, 5.681383, 5.651165, 5.639808, 5.653416",\
+ "5.833738, 5.787583, 5.757366, 5.746009, 5.759616",\
+ "6.023547, 5.977392, 5.947175, 5.935818, 5.949425",\
+ "6.386638, 6.340483, 6.310266, 6.298908, 6.312516");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[36]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\
+ "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\
+ "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\
+ "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[36]_hldr*/
+
+} /* end of pin tl_i[36] */
+
+pin("tl_i[35]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.023123 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[35];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.051503, 5.005348, 4.975131, 4.963773, 4.977381",\
+ "5.138166, 5.092011, 5.061794, 5.050437, 5.064044",\
+ "5.251214, 5.205059, 5.174842, 5.163485, 5.177092",\
+ "5.450928, 5.404773, 5.374556, 5.363198, 5.376806",\
+ "5.780051, 5.733896, 5.703679, 5.692322, 5.705929");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.051780, 5.005625, 4.975408, 4.964050, 4.977658",\
+ "5.133488, 5.087333, 5.057116, 5.045758, 5.059366",\
+ "5.260558, 5.214403, 5.184186, 5.172829, 5.186436",\
+ "5.487176, 5.441021, 5.410804, 5.399446, 5.413054",\
+ "5.889712, 5.843557, 5.813340, 5.801982, 5.815590");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[35]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.060002, 0.003106, 0.047821, 0.287989",\
+ "-0.211450, -0.142185, -0.078960, -0.034194, 0.203312",\
+ "-0.299321, -0.228917, -0.165692, -0.120927, 0.115291",\
+ "-0.454448, -0.386390, -0.323164, -0.278399, -0.040427",\
+ "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.117131, -0.065963, -0.008166, 0.033833, 0.413435",\
+ "-0.206406, -0.159987, -0.102190, -0.060192, 0.324160",\
+ "-0.303102, -0.251195, -0.193398, -0.151400, 0.227464",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, 0.053358",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.246898");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[35]_hldr*/
+
+} /* end of pin tl_i[35] */
+
+pin("tl_i[34]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.023475 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[34];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.659205, 5.613050, 5.582833, 5.571476, 5.585083",\
+ "5.746680, 5.700525, 5.670308, 5.658950, 5.672558",\
+ "5.833981, 5.787826, 5.757608, 5.746251, 5.759859",\
+ "6.007267, 5.961112, 5.930894, 5.919537, 5.933145",\
+ "6.412266, 6.366111, 6.335894, 6.324536, 6.338144");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.653732, 5.607577, 5.577360, 5.566003, 5.579610",\
+ "5.742702, 5.696547, 5.666329, 5.654972, 5.668580",\
+ "5.857737, 5.811582, 5.781364, 5.770007, 5.783615",\
+ "6.095998, 6.049843, 6.019626, 6.008269, 6.021876",\
+ "6.532254, 6.486099, 6.455882, 6.444524, 6.458132");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[34]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.126806, -0.060002, 0.003106, 0.047821, 0.287989",\
+ "-0.211450, -0.142185, -0.078960, -0.034194, 0.203312",\
+ "-0.299321, -0.228917, -0.165692, -0.120927, 0.115291",\
+ "-0.454448, -0.386390, -0.323164, -0.278399, -0.040427",\
+ "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.117131, -0.065963, -0.008166, 0.033833, 0.413435",\
+ "-0.206406, -0.159987, -0.102190, -0.060192, 0.324160",\
+ "-0.303102, -0.251195, -0.193398, -0.151400, 0.227464",\
+ "-0.474232, -0.408221, -0.350424, -0.308425, 0.053358",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.246898");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[34]_hldr*/
+
+} /* end of pin tl_i[34] */
+
+pin("tl_i[33]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.026365 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[33];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.415846, 5.369691, 5.339474, 5.328116, 5.341724",\
+ "5.492352, 5.446198, 5.415980, 5.404623, 5.418231",\
+ "5.597322, 5.551167, 5.520950, 5.509593, 5.523201",\
+ "5.785541, 5.739386, 5.709168, 5.697811, 5.711419",\
+ "6.094803, 6.048648, 6.018431, 6.007074, 6.020681");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.396865, 5.350710, 5.320493, 5.309135, 5.322743",\
+ "5.469503, 5.423348, 5.393131, 5.381774, 5.395381",\
+ "5.589046, 5.542892, 5.512674, 5.501317, 5.514925",\
+ "5.798637, 5.752482, 5.722265, 5.710908, 5.724515",\
+ "6.156535, 6.110380, 6.080163, 6.068806, 6.082413");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[33]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103109, -0.028958, 0.033565, 0.078027, 0.304632",\
+ "-0.177282, -0.103131, -0.040609, 0.003854, 0.230458",\
+ "-0.245176, -0.171025, -0.108503, -0.064040, 0.162564",\
+ "-0.354010, -0.279859, -0.217337, -0.172874, 0.053730",\
+ "-0.518682, -0.444530, -0.382008, -0.337546, -0.110941");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\
+ "-0.200788, -0.156050, -0.102190, -0.060192, 0.330575",\
+ "-0.289964, -0.245226, -0.193398, -0.151400, 0.241399",\
+ "-0.449371, -0.404633, -0.350424, -0.308425, 0.081992",\
+ "-0.653554, -0.594763, -0.536828, -0.494793, -0.185077");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[33]_hldr*/
+
+} /* end of pin tl_i[33] */
+
+pin("tl_i[32]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.025030 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[32];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.608686, 5.562531, 5.532314, 5.520957, 5.534564",\
+ "5.696244, 5.650089, 5.619872, 5.608514, 5.622122",\
+ "5.806668, 5.760513, 5.730296, 5.718939, 5.732546",\
+ "5.996225, 5.950070, 5.919853, 5.908495, 5.922103",\
+ "6.308736, 6.262581, 6.232364, 6.221007, 6.234614");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.604916, 5.558761, 5.528543, 5.517186, 5.530794",\
+ "5.686645, 5.640490, 5.610272, 5.598915, 5.612523",\
+ "5.804552, 5.758397, 5.728179, 5.716822, 5.730430",\
+ "6.035892, 5.989738, 5.959520, 5.948163, 5.961771",\
+ "6.435390, 6.389235, 6.359018, 6.347661, 6.361268");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[32]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103109, -0.028958, 0.033565, 0.078027, 0.315276",\
+ "-0.177282, -0.103131, -0.040609, 0.003854, 0.236790",\
+ "-0.245176, -0.171025, -0.108503, -0.064040, 0.162564",\
+ "-0.354010, -0.279859, -0.217337, -0.172874, 0.053730",\
+ "-0.518682, -0.444530, -0.382008, -0.337546, -0.110941");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\
+ "-0.200788, -0.135648, -0.078368, -0.036508, 0.330575",\
+ "-0.289964, -0.226296, -0.169017, -0.127157, 0.241399",\
+ "-0.449371, -0.387089, -0.329810, -0.287949, 0.081992",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185077");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[32]_hldr*/
+
+} /* end of pin tl_i[32] */
+
+pin("tl_i[31]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.025825 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[31];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.156651, 5.110496, 5.080278, 5.068921, 5.082529",\
+ "5.240004, 5.193849, 5.163631, 5.152274, 5.165882",\
+ "5.328885, 5.282730, 5.252513, 5.241156, 5.254763",\
+ "5.512913, 5.466758, 5.436541, 5.425183, 5.438791",\
+ "5.849318, 5.803163, 5.772945, 5.761588, 5.775196");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.160699, 5.114544, 5.084327, 5.072970, 5.086577",\
+ "5.238642, 5.192487, 5.162270, 5.150913, 5.164520",\
+ "5.344724, 5.298569, 5.268352, 5.256994, 5.270602",\
+ "5.598361, 5.552207, 5.521989, 5.510632, 5.524240",\
+ "6.070027, 6.023872, 5.993655, 5.982297, 5.995905");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[31]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\
+ "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\
+ "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\
+ "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[31]_hldr*/
+
+} /* end of pin tl_i[31] */
+
+pin("tl_i[30]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.025050 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[30];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.361538, 5.315383, 5.285166, 5.273808, 5.287416",\
+ "5.445924, 5.399769, 5.369552, 5.358194, 5.371802",\
+ "5.526791, 5.480636, 5.450418, 5.439061, 5.452669",\
+ "5.668298, 5.622143, 5.591926, 5.580568, 5.594176",\
+ "5.912872, 5.866717, 5.836500, 5.825143, 5.838750");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.346942, 5.300787, 5.270570, 5.259213, 5.272820",\
+ "5.428506, 5.382351, 5.352134, 5.340776, 5.354384",\
+ "5.534707, 5.488552, 5.458334, 5.446977, 5.460585",\
+ "5.723008, 5.676853, 5.646636, 5.635279, 5.648886",\
+ "6.057394, 6.011239, 5.981022, 5.969665, 5.983272");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[30]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\
+ "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\
+ "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\
+ "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[30]_hldr*/
+
+} /* end of pin tl_i[30] */
+
+pin("tl_i[29]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.026087 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[29];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.397203, 5.351048, 5.320831, 5.309474, 5.323081",\
+ "5.485135, 5.438980, 5.408763, 5.397406, 5.411013",\
+ "5.586405, 5.540250, 5.510033, 5.498675, 5.512283",\
+ "5.772069, 5.725914, 5.695697, 5.684340, 5.697948",\
+ "6.070103, 6.023948, 5.993731, 5.982373, 5.995981");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.401423, 5.355268, 5.325051, 5.313694, 5.327301",\
+ "5.484715, 5.438560, 5.408342, 5.396985, 5.410593",\
+ "5.608980, 5.562825, 5.532608, 5.521251, 5.534858",\
+ "5.841204, 5.795049, 5.764832, 5.753474, 5.767082",\
+ "6.247406, 6.201252, 6.171034, 6.159677, 6.173285");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[29]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\
+ "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\
+ "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\
+ "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[29]_hldr*/
+
+} /* end of pin tl_i[29] */
+
+pin("tl_i[28]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.025799 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[28];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.618461, 5.572306, 5.542089, 5.530732, 5.544339",\
+ "5.717470, 5.671315, 5.641098, 5.629741, 5.643348",\
+ "5.855001, 5.808846, 5.778629, 5.767272, 5.780879",\
+ "6.129478, 6.083323, 6.053106, 6.041749, 6.055356",\
+ "6.630586, 6.584431, 6.554214, 6.542856, 6.556464");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.605847, 5.559692, 5.529475, 5.518118, 5.531725",\
+ "5.703081, 5.656926, 5.626709, 5.615352, 5.628959",\
+ "5.850164, 5.804009, 5.773792, 5.762435, 5.776042",\
+ "6.157188, 6.111033, 6.080816, 6.069459, 6.083066",\
+ "6.726156, 6.680001, 6.649784, 6.638427, 6.652034");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[28]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.515343, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\
+ "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\
+ "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\
+ "-0.449366, -0.384569, -0.318431, -0.272351, 0.081996",\
+ "-0.607923, -0.533171, -0.467033, -0.420953, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[28]_hldr*/
+
+} /* end of pin tl_i[28] */
+
+pin("tl_i[27]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.025120 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[27];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.422370, 5.376215, 5.345998, 5.334641, 5.348248",\
+ "5.509055, 5.462900, 5.432683, 5.421326, 5.434933",\
+ "5.606899, 5.560744, 5.530527, 5.519170, 5.532777",\
+ "5.815886, 5.769731, 5.739513, 5.728156, 5.741764",\
+ "6.259951, 6.213796, 6.183579, 6.172222, 6.185829");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.415630, 5.369475, 5.339258, 5.327900, 5.341508",\
+ "5.508262, 5.462107, 5.431890, 5.420532, 5.434140",\
+ "5.634383, 5.588228, 5.558011, 5.546654, 5.560261",\
+ "5.884534, 5.838379, 5.808162, 5.796804, 5.810412",\
+ "6.321214, 6.275059, 6.244842, 6.233485, 6.247092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[27]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\
+ "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\
+ "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\
+ "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[27]_hldr*/
+
+} /* end of pin tl_i[27] */
+
+pin("tl_i[26]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.025620 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[26];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.634807, 5.588652, 5.558434, 5.547077, 5.560685",\
+ "5.726879, 5.680724, 5.650507, 5.639150, 5.652757",\
+ "5.836696, 5.790541, 5.760324, 5.748966, 5.762574",\
+ "6.041320, 5.995165, 5.964948, 5.953590, 5.967198",\
+ "6.417303, 6.371148, 6.340931, 6.329574, 6.343181");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.627578, 5.581423, 5.551206, 5.539848, 5.553456",\
+ "5.725660, 5.679505, 5.649288, 5.637930, 5.651538",\
+ "5.857279, 5.811124, 5.780907, 5.769550, 5.783157",\
+ "6.101712, 6.055557, 6.025340, 6.013983, 6.027590",\
+ "6.528873, 6.482718, 6.452501, 6.441144, 6.454751");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[26]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\
+ "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\
+ "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\
+ "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[26]_hldr*/
+
+} /* end of pin tl_i[26] */
+
+pin("tl_i[25]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.027861 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[25];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.587914, 5.541759, 5.511542, 5.500185, 5.513792",\
+ "5.685092, 5.638937, 5.608720, 5.597363, 5.610970",\
+ "5.791002, 5.744847, 5.714630, 5.703273, 5.716880",\
+ "5.984866, 5.938711, 5.908494, 5.897137, 5.910744",\
+ "6.350015, 6.303860, 6.273643, 6.262286, 6.275893");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.597159, 5.551004, 5.520787, 5.509430, 5.523037",\
+ "5.695459, 5.649304, 5.619087, 5.607729, 5.621337",\
+ "5.810205, 5.764050, 5.733832, 5.722475, 5.736083",\
+ "6.008989, 5.962834, 5.932617, 5.921260, 5.934867",\
+ "6.374745, 6.328590, 6.298373, 6.287016, 6.300623");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[25]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\
+ "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\
+ "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\
+ "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[25]_hldr*/
+
+} /* end of pin tl_i[25] */
+
+pin("tl_i[24]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.026383 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[24];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.563736, 5.517581, 5.487364, 5.476007, 5.489614",\
+ "5.661705, 5.615550, 5.585332, 5.573975, 5.587583",\
+ "5.767614, 5.721459, 5.691242, 5.679884, 5.693492",\
+ "5.957180, 5.911025, 5.880808, 5.869451, 5.883058",\
+ "6.288558, 6.242403, 6.212186, 6.200829, 6.214436");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.590299, 5.544144, 5.513927, 5.502569, 5.516177",\
+ "5.689440, 5.643285, 5.613068, 5.601710, 5.615318",\
+ "5.803774, 5.757619, 5.727402, 5.716045, 5.729652",\
+ "5.994250, 5.948095, 5.917878, 5.906520, 5.920128",\
+ "6.312450, 6.266295, 6.236078, 6.224721, 6.238328");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[24]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\
+ "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\
+ "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\
+ "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\
+ "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\
+ "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\
+ "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\
+ "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\
+ "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[24]_hldr*/
+
+} /* end of pin tl_i[24] */
+
+pin("tl_i[23]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[23];
+} /* end of pin tl_i[23] */
+
+pin("tl_i[22]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[22];
+} /* end of pin tl_i[22] */
+
+pin("tl_i[21]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[21];
+} /* end of pin tl_i[21] */
+
+pin("tl_i[20]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[20];
+} /* end of pin tl_i[20] */
+
+pin("tl_i[19]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[19];
+} /* end of pin tl_i[19] */
+
+pin("tl_i[18]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.005233 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[18];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.846815, 5.800660, 5.770443, 5.759086, 5.772694",\
+ "5.932193, 5.886038, 5.855821, 5.844464, 5.858071",\
+ "6.009590, 5.963435, 5.933218, 5.921861, 5.935469",\
+ "6.178617, 6.132463, 6.102246, 6.090889, 6.104496",\
+ "6.537492, 6.491337, 6.461120, 6.449763, 6.463370");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.843783, 5.797628, 5.767412, 5.756054, 5.769662",\
+ "5.926365, 5.880210, 5.849993, 5.838636, 5.852243",\
+ "6.038355, 5.992200, 5.961983, 5.950626, 5.964233",\
+ "6.269215, 6.223060, 6.192843, 6.181486, 6.195093",\
+ "6.674184, 6.628029, 6.597812, 6.586455, 6.600062");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[18]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.329740, -0.287323, -0.252837, -0.213389, 0.092961",\
+ "-0.415095, -0.372677, -0.338191, -0.298743, 0.007607",\
+ "-0.499351, -0.456933, -0.422448, -0.383000, -0.076649",\
+ "-0.641023, -0.598605, -0.564119, -0.524671, -0.218321",\
+ "-0.860645, -0.818228, -0.783742, -0.744294, -0.437944");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.392665, -0.350247, -0.315761, -0.276314, 0.030037",\
+ "-0.480853, -0.438436, -0.403950, -0.364502, -0.058152",\
+ "-0.581004, -0.538587, -0.504101, -0.464653, -0.158303",\
+ "-0.765285, -0.722867, -0.665898, -0.623927, -0.342583",\
+ "-1.010030, -0.967612, -0.918979, -0.877008, -0.587328");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[18]_hldr*/
+
+} /* end of pin tl_i[18] */
+
+pin("tl_i[17]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.004306 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[17];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.132060, 6.085905, 6.055688, 6.044331, 6.057939",\
+ "6.217465, 6.171310, 6.141094, 6.129736, 6.143344",\
+ "6.294953, 6.248798, 6.218582, 6.207224, 6.220832",\
+ "6.439157, 6.393003, 6.362786, 6.351429, 6.365036",\
+ "6.796788, 6.750633, 6.720417, 6.709059, 6.722667");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.129071, 6.082916, 6.052700, 6.041342, 6.054950",\
+ "6.211690, 6.165535, 6.135318, 6.123961, 6.137568",\
+ "6.323722, 6.277567, 6.247350, 6.235993, 6.249600",\
+ "6.554055, 6.507900, 6.477684, 6.466326, 6.479934",\
+ "6.957980, 6.911825, 6.881608, 6.870251, 6.883859");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[17]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.329387, -0.286969, -0.252483, -0.213035, 0.093315",\
+ "-0.413395, -0.370977, -0.336491, -0.297044, 0.009307",\
+ "-0.496847, -0.454429, -0.419944, -0.380496, -0.074145",\
+ "-0.636423, -0.594005, -0.559520, -0.520072, -0.213721",\
+ "-0.849170, -0.806753, -0.772267, -0.732819, -0.426469");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.397874, -0.355456, -0.320970, -0.281523, 0.024828",\
+ "-0.486065, -0.443648, -0.409162, -0.369714, -0.063364",\
+ "-0.585801, -0.543384, -0.506390, -0.464420, -0.163100",\
+ "-0.770163, -0.720512, -0.662817, -0.620846, -0.347461",\
+ "-1.005635, -0.963218, -0.913955, -0.871984, -0.582934");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[17]_hldr*/
+
+} /* end of pin tl_i[17] */
+
+pin("tl_i[16]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.003506 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[16];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.061040, 6.014885, 5.984668, 5.973311, 5.986918",\
+ "6.154351, 6.108196, 6.077980, 6.066622, 6.080230",\
+ "6.247583, 6.201428, 6.171212, 6.159854, 6.173462",\
+ "6.410316, 6.364161, 6.333944, 6.322587, 6.336194",\
+ "6.686312, 6.640157, 6.609940, 6.598583, 6.612190");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.018520, 5.972365, 5.942149, 5.930791, 5.944399",\
+ "6.115014, 6.068859, 6.038642, 6.027285, 6.040893",\
+ "6.214722, 6.168567, 6.138350, 6.126993, 6.140600",\
+ "6.391147, 6.344992, 6.314775, 6.303418, 6.317025",\
+ "6.683747, 6.637592, 6.607376, 6.596018, 6.609626");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[16]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.394478, -0.352061, -0.317575, -0.278127, 0.028223",\
+ "-0.483595, -0.441177, -0.404014, -0.362043, -0.060893",\
+ "-0.569978, -0.527561, -0.480614, -0.438644, -0.147277",\
+ "-0.718308, -0.666396, -0.608701, -0.566730, -0.295606",\
+ "-0.932373, -0.866433, -0.808738, -0.766767, -0.544592");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.386365, -0.343947, -0.309462, -0.270014, 0.036337",\
+ "-0.468621, -0.426203, -0.391718, -0.352270, -0.045919",\
+ "-0.564853, -0.522435, -0.487950, -0.448502, -0.142151",\
+ "-0.726358, -0.683941, -0.649455, -0.610007, -0.303657",\
+ "-0.988854, -0.946436, -0.911950, -0.872503, -0.566152");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[16]_hldr*/
+
+} /* end of pin tl_i[16] */
+
+pin("tl_i[15]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.003647 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[15];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.804135, 5.757980, 5.727764, 5.716406, 5.730014",\
+ "5.902175, 5.856020, 5.825803, 5.814446, 5.828053",\
+ "6.008589, 5.962434, 5.932217, 5.920860, 5.934467",\
+ "6.199651, 6.153496, 6.123279, 6.111922, 6.125529",\
+ "6.533928, 6.487773, 6.457556, 6.446199, 6.459806");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.811823, 5.765668, 5.735451, 5.724094, 5.737701",\
+ "5.911395, 5.865240, 5.835023, 5.823666, 5.837274",\
+ "6.026561, 5.980406, 5.950189, 5.938832, 5.952439",\
+ "6.220825, 6.174670, 6.144454, 6.133096, 6.146704",\
+ "6.548571, 6.502416, 6.472199, 6.460842, 6.474449");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[15]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.333549, -0.291131, -0.256645, -0.217198, 0.089153",\
+ "-0.416355, -0.373937, -0.339451, -0.300003, 0.006347",\
+ "-0.498092, -0.455675, -0.421189, -0.381741, -0.075391",\
+ "-0.641500, -0.599082, -0.564596, -0.525149, -0.218798",\
+ "-0.881493, -0.839075, -0.804590, -0.765142, -0.458791");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.367074, -0.324657, -0.290171, -0.250723, 0.055627",\
+ "-0.454947, -0.412529, -0.378044, -0.338596, -0.032245",\
+ "-0.540971, -0.498554, -0.464068, -0.424620, -0.118270",\
+ "-0.691009, -0.648592, -0.614106, -0.574658, -0.268308",\
+ "-0.937715, -0.895297, -0.860812, -0.821364, -0.515013");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[15]_hldr*/
+
+} /* end of pin tl_i[15] */
+
+pin("tl_i[14]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000507 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[14];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.880361, 5.834206, 5.803989, 5.792632, 5.806239",\
+ "5.967889, 5.921734, 5.891517, 5.880160, 5.893767",\
+ "6.055178, 6.009023, 5.978806, 5.967449, 5.981056",\
+ "6.230941, 6.184786, 6.154569, 6.143212, 6.156819",\
+ "6.640085, 6.593930, 6.563713, 6.552356, 6.565963");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.875138, 5.828983, 5.798766, 5.787409, 5.801016",\
+ "5.963992, 5.917837, 5.887620, 5.876263, 5.889871",\
+ "6.079109, 6.032954, 6.002738, 5.991380, 6.004988",\
+ "6.317663, 6.271508, 6.241292, 6.229934, 6.243542",\
+ "6.755099, 6.708944, 6.678727, 6.667370, 6.680977");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[14]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.456322, -1.413945, -1.379366, -1.341730, -1.057874",\
+ "-1.546534, -1.504156, -1.469577, -1.431942, -1.148085",\
+ "-1.659324, -1.616947, -1.582367, -1.544732, -1.260875",\
+ "-1.878867, -1.836490, -1.801910, -1.764275, -1.480418",\
+ "-2.185190, -2.142812, -2.108233, -2.070598, -1.786741");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.489696, -1.447319, -1.412740, -1.375104, -1.091248",\
+ "-1.579588, -1.537211, -1.502631, -1.464996, -1.181139",\
+ "-1.675047, -1.632670, -1.598091, -1.560455, -1.276599",\
+ "-1.845432, -1.803055, -1.768476, -1.730840, -1.446984",\
+ "-2.145069, -2.102692, -2.068113, -2.030477, -1.746621");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[14]_hldr*/
+
+} /* end of pin tl_i[14] */
+
+pin("tl_i[13]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000507 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[13];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.164994, 6.118839, 6.088623, 6.077265, 6.090873",\
+ "6.252498, 6.206343, 6.176126, 6.164769, 6.178376",\
+ "6.339791, 6.293636, 6.263420, 6.252062, 6.265670",\
+ "6.496986, 6.450831, 6.420614, 6.409257, 6.422864",\
+ "6.898607, 6.852452, 6.822236, 6.810878, 6.824486");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "6.159660, 6.113505, 6.083289, 6.071931, 6.085539",\
+ "6.248568, 6.202413, 6.172196, 6.160839, 6.174446",\
+ "6.363653, 6.317498, 6.287282, 6.275924, 6.289532",\
+ "6.601918, 6.555763, 6.525547, 6.514189, 6.527797",\
+ "7.038295, 6.992140, 6.961923, 6.950566, 6.964173");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[13]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.676593, -1.628499, -1.570612, -1.528590, -1.278144",\
+ "-1.766810, -1.718717, -1.660830, -1.618807, -1.368362",\
+ "-1.879585, -1.831491, -1.773605, -1.731582, -1.481137",\
+ "-2.098712, -2.050618, -1.992732, -1.950709, -1.700264",\
+ "-2.408059, -2.359965, -2.302078, -2.260055, -2.009610");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.710053, -1.661959, -1.604072, -1.562050, -1.311604",\
+ "-1.799952, -1.751858, -1.693972, -1.651949, -1.401504",\
+ "-1.895418, -1.847324, -1.789437, -1.747415, -1.496969",\
+ "-2.065788, -2.017694, -1.959808, -1.917785, -1.667340",\
+ "-2.365375, -2.317281, -2.259394, -2.217371, -1.966926");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[13]_hldr*/
+
+} /* end of pin tl_i[13] */
+
+pin("tl_i[12]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001105 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[12];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.508289, 5.462134, 5.431918, 5.420560, 5.434168",\
+ "5.592647, 5.546492, 5.516275, 5.504918, 5.518525",\
+ "5.673546, 5.627391, 5.597174, 5.585817, 5.599424",\
+ "5.815136, 5.768981, 5.738764, 5.727407, 5.741014",\
+ "6.052000, 6.005845, 5.975628, 5.964271, 5.977879");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.430960, 5.384805, 5.354588, 5.343231, 5.356838",\
+ "5.522353, 5.476198, 5.445981, 5.434624, 5.448231",\
+ "5.614760, 5.568605, 5.538389, 5.527031, 5.540639",\
+ "5.776403, 5.730248, 5.700032, 5.688674, 5.702282",\
+ "6.049640, 6.003485, 5.973268, 5.961911, 5.975518");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[12]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.265898, -1.223521, -1.188942, -1.151306, -0.867450",\
+ "-1.350510, -1.308133, -1.273553, -1.235918, -0.952061",\
+ "-1.430668, -1.388291, -1.353711, -1.316076, -1.032219",\
+ "-1.572586, -1.530209, -1.495630, -1.457994, -1.174138",\
+ "-1.810084, -1.767707, -1.733127, -1.695492, -1.411635");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.242763, -1.200386, -1.165807, -1.128171, -0.844315",\
+ "-1.334117, -1.291740, -1.257160, -1.219525, -0.935668",\
+ "-1.427063, -1.384685, -1.350106, -1.312471, -1.028614",\
+ "-1.589313, -1.546936, -1.512356, -1.474721, -1.190864",\
+ "-1.862213, -1.819836, -1.785256, -1.747621, -1.463764");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[12]_hldr*/
+
+} /* end of pin tl_i[12] */
+
+pin("tl_i[11]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000507 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[11];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.261997, 5.215842, 5.185626, 5.174268, 5.187876",\
+ "5.353421, 5.307266, 5.277050, 5.265692, 5.279300",\
+ "5.463365, 5.417210, 5.386993, 5.375636, 5.389243",\
+ "5.679752, 5.633597, 5.603381, 5.592023, 5.605631",\
+ "6.088896, 6.042741, 6.012525, 6.001167, 6.014775");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.323949, 5.277794, 5.247577, 5.236220, 5.249827",\
+ "5.412804, 5.366649, 5.336432, 5.325075, 5.338682",\
+ "5.527921, 5.481766, 5.451549, 5.440192, 5.453799",\
+ "5.766475, 5.720320, 5.690103, 5.678746, 5.692353",\
+ "6.203910, 6.157755, 6.127538, 6.116181, 6.129788");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[11]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.231498, -1.189121, -1.154542, -1.116906, -0.833050",\
+ "-1.321710, -1.279333, -1.244753, -1.207118, -0.923261",\
+ "-1.434500, -1.392123, -1.357543, -1.319908, -1.036052",\
+ "-1.654043, -1.611666, -1.577086, -1.539451, -1.255594",\
+ "-2.055035, -2.012658, -1.978078, -1.940443, -1.656586");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.277769, -1.235391, -1.200812, -1.163177, -0.879320",\
+ "-1.368203, -1.325825, -1.291246, -1.253611, -0.969754",\
+ "-1.482250, -1.439872, -1.405293, -1.367658, -1.083801",\
+ "-1.702415, -1.660038, -1.625458, -1.587823, -1.303966",\
+ "-2.095423, -2.053046, -2.018466, -1.980831, -1.696974");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[11]_hldr*/
+
+} /* end of pin tl_i[11] */
+
+pin("tl_i[10]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000507 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[10];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.688106, 5.641951, 5.611734, 5.600377, 5.613985",\
+ "5.775612, 5.729457, 5.699240, 5.687883, 5.701490",\
+ "5.862906, 5.816751, 5.786535, 5.775177, 5.788785",\
+ "6.017570, 5.971415, 5.941198, 5.929841, 5.943448",\
+ "6.285493, 6.239338, 6.209121, 6.197764, 6.211371");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.621125, 5.574970, 5.544754, 5.533396, 5.547004",\
+ "5.711027, 5.664872, 5.634655, 5.623298, 5.636906",\
+ "5.806498, 5.760343, 5.730126, 5.718769, 5.732377",\
+ "5.976879, 5.930724, 5.900507, 5.889150, 5.902758",\
+ "6.276484, 6.230330, 6.200113, 6.188756, 6.202363");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[10]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.488494, -1.446116, -1.411537, -1.373901, -1.090045",\
+ "-1.576000, -1.533622, -1.499043, -1.461408, -1.177551",\
+ "-1.663294, -1.620917, -1.586338, -1.548702, -1.264846",\
+ "-1.817957, -1.775580, -1.741001, -1.703365, -1.419509",\
+ "-2.085881, -2.043503, -2.008924, -1.971289, -1.687432");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.387740, -1.345363, -1.310783, -1.273148, -0.989291",\
+ "-1.477641, -1.435264, -1.400684, -1.363049, -1.079192",\
+ "-1.573112, -1.530735, -1.496156, -1.458520, -1.174664",\
+ "-1.743494, -1.701116, -1.666537, -1.628902, -1.345045",\
+ "-2.043099, -2.000721, -1.966142, -1.928507, -1.644650");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[10]_hldr*/
+
+} /* end of pin tl_i[10] */
+
+pin("tl_i[9]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000507 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[9];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.299526, 5.253371, 5.223155, 5.211797, 5.225405",\
+ "5.387030, 5.340875, 5.310658, 5.299301, 5.312908",\
+ "5.474324, 5.428169, 5.397952, 5.386595, 5.400202",\
+ "5.628947, 5.582792, 5.552575, 5.541218, 5.554825",\
+ "5.896894, 5.850739, 5.820522, 5.809165, 5.822773");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.267633, 5.221478, 5.191262, 5.179904, 5.193512",\
+ "5.357825, 5.311670, 5.281454, 5.270096, 5.283704",\
+ "5.453746, 5.407591, 5.377375, 5.366017, 5.379625",\
+ "5.626006, 5.579851, 5.549634, 5.538277, 5.551885",\
+ "5.922129, 5.875974, 5.845757, 5.834400, 5.848007");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[9]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.240064, -1.197687, -1.163107, -1.125472, -0.841615",\
+ "-1.327747, -1.285370, -1.250791, -1.213155, -0.929299",\
+ "-1.415402, -1.373024, -1.338445, -1.300810, -1.016953",\
+ "-1.572242, -1.529865, -1.495286, -1.457650, -1.173794",\
+ "-1.840724, -1.798346, -1.763767, -1.726132, -1.442275");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.220831, -1.178454, -1.143874, -1.106239, -0.822382",\
+ "-1.310730, -1.268353, -1.233773, -1.196138, -0.912281",\
+ "-1.406196, -1.363818, -1.329239, -1.291603, -1.007747",\
+ "-1.576566, -1.534189, -1.499609, -1.461974, -1.178117",\
+ "-1.876152, -1.833775, -1.799196, -1.761560, -1.477704");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[9]_hldr*/
+
+} /* end of pin tl_i[9] */
+
+pin("tl_i[8]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000507 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[8];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.306569, 5.260414, 5.230197, 5.218840, 5.232448",\
+ "5.394075, 5.347920, 5.317704, 5.306346, 5.319954",\
+ "5.481370, 5.435215, 5.404998, 5.393641, 5.407248",\
+ "5.636033, 5.589878, 5.559661, 5.548304, 5.561912",\
+ "5.903956, 5.857801, 5.827585, 5.816227, 5.829835");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.239589, 5.193434, 5.163217, 5.151860, 5.165467",\
+ "5.329490, 5.283335, 5.253119, 5.241761, 5.255369",\
+ "5.424961, 5.378806, 5.348589, 5.337232, 5.350840",\
+ "5.595343, 5.549188, 5.518971, 5.507614, 5.521221",\
+ "5.894948, 5.848793, 5.818576, 5.807219, 5.820827");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[8]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.339799, -1.297422, -1.262842, -1.225207, -0.941350",\
+ "-1.427305, -1.384928, -1.350348, -1.312713, -1.028856",\
+ "-1.514600, -1.472222, -1.437643, -1.400007, -1.116151",\
+ "-1.669263, -1.626886, -1.592306, -1.554671, -1.270814",\
+ "-1.937186, -1.894809, -1.860229, -1.822594, -1.538737");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.239045, -1.196668, -1.162088, -1.124453, -0.840596",\
+ "-1.328946, -1.286569, -1.251990, -1.214354, -0.930498",\
+ "-1.424418, -1.382040, -1.347461, -1.309826, -1.025969",\
+ "-1.594799, -1.552422, -1.517842, -1.480207, -1.196350",\
+ "-1.894404, -1.852027, -1.817448, -1.779812, -1.495956");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[8]_hldr*/
+
+} /* end of pin tl_i[8] */
+
+pin("tl_i[7]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000507 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[7];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.737750, 5.691595, 5.661378, 5.650021, 5.663628",\
+ "5.825280, 5.779125, 5.748908, 5.737551, 5.751158",\
+ "5.912570, 5.866415, 5.836198, 5.824841, 5.838448",\
+ "6.086271, 6.040116, 6.009899, 5.998541, 6.012149",\
+ "6.495438, 6.449283, 6.419065, 6.407708, 6.421316");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.732527, 5.686372, 5.656155, 5.644798, 5.658405",\
+ "5.821378, 5.775223, 5.745006, 5.733648, 5.747256",\
+ "5.936484, 5.890329, 5.860112, 5.848755, 5.862362",\
+ "6.175041, 6.128886, 6.098669, 6.087312, 6.100919",\
+ "6.612741, 6.566586, 6.536369, 6.525012, 6.538620");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[7]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.210458, -1.168081, -1.133501, -1.095866, -0.812009",\
+ "-1.300683, -1.258306, -1.223726, -1.186091, -0.902234",\
+ "-1.413495, -1.371118, -1.336539, -1.298903, -1.015047",\
+ "-1.594716, -1.552338, -1.517759, -1.480124, -1.196267",\
+ "-1.863199, -1.820821, -1.786242, -1.748607, -1.464750");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.243829, -1.201452, -1.166873, -1.129237, -0.845381",\
+ "-1.333722, -1.291345, -1.256766, -1.219130, -0.935274",\
+ "-1.429188, -1.386811, -1.352232, -1.314596, -1.030740",\
+ "-1.599584, -1.557206, -1.522627, -1.484991, -1.201135",\
+ "-1.899240, -1.856863, -1.822283, -1.784648, -1.500791");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[7]_hldr*/
+
+} /* end of pin tl_i[7] */
+
+pin("tl_i[6]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001034 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[6];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.368608, 5.322453, 5.292236, 5.280879, 5.294487",\
+ "5.454073, 5.407918, 5.377701, 5.366343, 5.379951",\
+ "5.531495, 5.485340, 5.455123, 5.443766, 5.457373",\
+ "5.675749, 5.629594, 5.599377, 5.588020, 5.601627",\
+ "6.027932, 5.981777, 5.951560, 5.940202, 5.953810");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.365854, 5.319699, 5.289482, 5.278125, 5.291732",\
+ "5.448556, 5.402401, 5.372184, 5.360826, 5.374434",\
+ "5.560353, 5.514198, 5.483981, 5.472623, 5.486231",\
+ "5.789183, 5.743028, 5.712811, 5.701454, 5.715061",\
+ "6.188337, 6.142182, 6.111965, 6.100607, 6.114215");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[6]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.925690, -0.883313, -0.848733, -0.811098, -0.527241",\
+ "-1.010422, -0.968045, -0.933465, -0.895830, -0.611973",\
+ "-1.117256, -1.074878, -1.040299, -1.002663, -0.718807",\
+ "-1.269870, -1.227492, -1.192913, -1.155277, -0.871421",\
+ "-1.497461, -1.455084, -1.420505, -1.382869, -1.099013");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.942127, -0.899750, -0.865171, -0.827535, -0.543679",\
+ "-1.032129, -0.989751, -0.955172, -0.917537, -0.633680",\
+ "-1.120122, -1.077745, -1.043165, -1.005530, -0.721673",\
+ "-1.275255, -1.232878, -1.198298, -1.160663, -0.876806",\
+ "-1.540632, -1.498255, -1.463676, -1.426040, -1.142184");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[6]_hldr*/
+
+} /* end of pin tl_i[6] */
+
+pin("tl_i[5]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000507 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[5];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.646876, 5.600721, 5.570504, 5.559147, 5.572754",\
+ "5.734406, 5.688251, 5.658034, 5.646677, 5.660285",\
+ "5.821696, 5.775541, 5.745324, 5.733967, 5.747574",\
+ "5.997414, 5.951259, 5.921041, 5.909684, 5.923292",\
+ "6.406565, 6.360410, 6.330193, 6.318835, 6.332443");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "5.641654, 5.595499, 5.565282, 5.553925, 5.567532",\
+ "5.730504, 5.684349, 5.654132, 5.642775, 5.656382",\
+ "5.845611, 5.799456, 5.769239, 5.757882, 5.771489",\
+ "6.084159, 6.038004, 6.007787, 5.996430, 6.010037",\
+ "6.521860, 6.475705, 6.445487, 6.434130, 6.447738");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[5]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.106780, -1.064402, -1.029823, -0.992188, -0.708331",\
+ "-1.197005, -1.154628, -1.120048, -1.082413, -0.798556",\
+ "-1.309817, -1.267440, -1.232860, -1.195225, -0.911368",\
+ "-1.491037, -1.448660, -1.414081, -1.376445, -1.092589",\
+ "-1.759520, -1.717143, -1.682564, -1.644928, -1.361072");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-1.140151, -1.097774, -1.063194, -1.025559, -0.741702",\
+ "-1.230044, -1.187667, -1.153087, -1.115452, -0.831595",\
+ "-1.325510, -1.283133, -1.248553, -1.210918, -0.927061",\
+ "-1.495905, -1.453528, -1.418948, -1.381313, -1.097456",\
+ "-1.795562, -1.753184, -1.718605, -1.680969, -1.397113");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[5]_hldr*/
+
+} /* end of pin tl_i[5] */
+
+pin("tl_i[4]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001034 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[4];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.980015, 4.933860, 4.903643, 4.892286, 4.905893",\
+ "5.065440, 5.019285, 4.989068, 4.977711, 4.991318",\
+ "5.143021, 5.096866, 5.066648, 5.055291, 5.068899",\
+ "5.322774, 5.276619, 5.246402, 5.235044, 5.248652",\
+ "5.675738, 5.629583, 5.599366, 5.588009, 5.601616");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.977059, 4.930904, 4.900687, 4.889330, 4.902937",\
+ "5.059716, 5.013561, 4.983344, 4.971986, 4.985594",\
+ "5.171787, 5.125632, 5.095415, 5.084057, 5.097665",\
+ "5.401430, 5.355275, 5.325058, 5.313701, 5.327308",\
+ "5.800714, 5.754560, 5.724342, 5.712985, 5.726593");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.891577, -0.849200, -0.814620, -0.776985, -0.493128",\
+ "-0.976303, -0.933926, -0.899346, -0.861711, -0.577854",\
+ "-1.083459, -1.041082, -1.006503, -0.968867, -0.685011",\
+ "-1.234205, -1.191828, -1.157249, -1.119613, -0.835757",\
+ "-1.461877, -1.419500, -1.384920, -1.347285, -1.063428");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.907849, -0.865472, -0.830893, -0.793257, -0.509401",\
+ "-0.997841, -0.955464, -0.920885, -0.883249, -0.599393",\
+ "-1.085765, -1.043387, -1.008808, -0.971172, -0.687316",\
+ "-1.240999, -1.198622, -1.164043, -1.126407, -0.842551",\
+ "-1.506646, -1.464268, -1.429689, -1.392054, -1.108197");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[4]_hldr*/
+
+} /* end of pin tl_i[4] */
+
+pin("tl_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000507 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.861817, 4.815662, 4.785445, 4.774088, 4.787695",\
+ "4.949495, 4.903340, 4.873123, 4.861766, 4.875373",\
+ "5.036715, 4.990560, 4.960342, 4.948985, 4.962593",\
+ "5.207161, 5.161006, 5.130789, 5.119431, 5.133039",\
+ "5.608678, 5.562523, 5.532306, 5.520948, 5.534556");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.856341, 4.810186, 4.779969, 4.768611, 4.782219",\
+ "4.945419, 4.899264, 4.869047, 4.857689, 4.871297",\
+ "5.060649, 5.014494, 4.984277, 4.972920, 4.986527",\
+ "5.297888, 5.251733, 5.221516, 5.210158, 5.223766",\
+ "5.732176, 5.686021, 5.655804, 5.644446, 5.658054");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.940665, -0.898288, -0.863709, -0.826073, -0.542217",\
+ "-1.030843, -0.988466, -0.953887, -0.916251, -0.632395",\
+ "-1.143556, -1.101179, -1.066599, -1.028964, -0.745108",\
+ "-1.327817, -1.285440, -1.250861, -1.213225, -0.929369",\
+ "-1.596320, -1.553943, -1.519363, -1.481728, -1.197871");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.974330, -0.931952, -0.897373, -0.859738, -0.575881",\
+ "-1.064250, -1.021872, -0.987293, -0.949658, -0.665801",\
+ "-1.159754, -1.117377, -1.082797, -1.045162, -0.761305",\
+ "-1.330068, -1.287690, -1.253111, -1.215476, -0.931619",\
+ "-1.629461, -1.587083, -1.552504, -1.514869, -1.231012");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[3]_hldr*/
+
+} /* end of pin tl_i[3] */
+
+pin("tl_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001034 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.870526, 4.824371, 4.794154, 4.782797, 4.796404",\
+ "4.955990, 4.909835, 4.879618, 4.868261, 4.881868",\
+ "5.033412, 4.987257, 4.957040, 4.945683, 4.959291",\
+ "5.177666, 5.131511, 5.101294, 5.089936, 5.103544",\
+ "5.529849, 5.483694, 5.453477, 5.442120, 5.455727");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.867772, 4.821617, 4.791399, 4.780042, 4.793650",\
+ "4.950474, 4.904319, 4.874102, 4.862744, 4.876352",\
+ "5.062271, 5.016116, 4.985898, 4.974541, 4.988149",\
+ "5.291101, 5.244946, 5.214728, 5.203371, 5.216979",\
+ "5.690255, 5.644100, 5.613883, 5.602525, 5.616133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.870275, -0.827898, -0.793318, -0.755683, -0.471826",\
+ "-0.955007, -0.912630, -0.878051, -0.840415, -0.556558",\
+ "-1.061841, -1.019464, -0.984884, -0.947249, -0.663392",\
+ "-1.214455, -1.172078, -1.137498, -1.099863, -0.816006",\
+ "-1.442046, -1.399669, -1.365090, -1.327454, -1.043598");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.886713, -0.844335, -0.809756, -0.772120, -0.488264",\
+ "-0.976714, -0.934337, -0.899757, -0.862122, -0.578265",\
+ "-1.064707, -1.022330, -0.987750, -0.950115, -0.666258",\
+ "-1.219840, -1.177463, -1.142883, -1.105248, -0.821391",\
+ "-1.485218, -1.442840, -1.408261, -1.370625, -1.086769");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[2]_hldr*/
+
+} /* end of pin tl_i[2] */
+
+pin("tl_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001034 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.874022, 4.827868, 4.797650, 4.786293, 4.799901",\
+ "4.959486, 4.913332, 4.883114, 4.871757, 4.885365",\
+ "5.036908, 4.990753, 4.960536, 4.949179, 4.962786",\
+ "5.181162, 5.135007, 5.104790, 5.093432, 5.107040",\
+ "5.533345, 5.487190, 5.456973, 5.445615, 5.459223");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "4.871267, 4.825112, 4.794895, 4.783538, 4.797145",\
+ "4.953969, 4.907815, 4.877597, 4.866240, 4.879848",\
+ "5.065766, 5.019611, 4.989394, 4.978037, 4.991644",\
+ "5.294597, 5.248442, 5.218225, 5.206867, 5.220475",\
+ "5.693750, 5.647595, 5.617378, 5.606021, 5.619628");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.871744, -0.829367, -0.794788, -0.757152, -0.473296",\
+ "-0.956476, -0.914099, -0.879520, -0.841884, -0.558028",\
+ "-1.063310, -1.020933, -0.986354, -0.948718, -0.664862",\
+ "-1.215924, -1.173547, -1.138968, -1.101332, -0.817476",\
+ "-1.443516, -1.401139, -1.366559, -1.328924, -1.045067");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.888182, -0.845805, -0.811225, -0.773590, -0.489733",\
+ "-0.978183, -0.935806, -0.901227, -0.863591, -0.579735",\
+ "-1.066176, -1.023799, -0.989220, -0.951584, -0.667728",\
+ "-1.221309, -1.178932, -1.144353, -1.106717, -0.822861",\
+ "-1.486687, -1.444310, -1.409730, -1.372095, -1.088238");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[1]_hldr*/
+
+} /* end of pin tl_i[1] */
+
+pin("tl_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000516 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_i[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.175613, 0.100294, 0.032151, 0.009209, 0.072356",\
+ "0.264638, 0.189339, 0.121299, 0.098527, 0.163209",\
+ "0.360287, 0.285032, 0.217232, 0.194849, 0.263068",\
+ "0.526788, 0.451609, 0.383810, 0.361643, 0.432490",\
+ "0.806358, 0.731299, 0.662593, 0.639784, 0.707364");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.201785, 0.154982, 0.124714, 0.113318, 0.126704",\
+ "0.285559, 0.238387, 0.208091, 0.196673, 0.209933",\
+ "0.386189, 0.338377, 0.307866, 0.296333, 0.309292",\
+ "0.553781, 0.505930, 0.474764, 0.462933, 0.475551",\
+ "0.832990, 0.785063, 0.752603, 0.740184, 0.752132");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.088868, -0.022902, 0.034829, 0.076810, 0.297292",\
+ "-0.178002, -0.111712, -0.053514, -0.011408, 0.208267",\
+ "-0.273901, -0.206863, -0.147593, -0.105196, 0.112621",\
+ "-0.440525, -0.372044, -0.311267, -0.268345, -0.051699",\
+ "-0.719618, -0.648392, -0.585857, -0.542000, -0.322826");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.133037, -0.090779, -0.055923, -0.023644, 0.193736",\
+ "-0.216520, -0.174329, -0.139318, -0.110044, 0.070036",\
+ "-0.315601, -0.273256, -0.237974, -0.213810, -0.097198",\
+ "-0.479066, -0.435673, -0.400366, -0.376078, -0.258082",\
+ "-0.750133, -0.704672, -0.669317, -0.644785, -0.524056");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_i[0]_hldr*/
+
+} /* end of pin tl_i[0] */
+} /* end of bus tl_i */
+bus ( tl_o ) {
+
+ bus_type : BUS66_type1 ;
+ direction : output ;
+
+pin("tl_o[65]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000991 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[65];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.044997, 0.199162, 0.375038, 0.698306, 1.344843",\
+ "0.131049, 0.286337, 0.462145, 0.785022, 1.430777",\
+ "0.213199, 0.374466, 0.550102, 0.872645, 1.517732",\
+ "0.270183, 0.438865, 0.614219, 0.936559, 1.581241",\
+ "0.564592, 0.788723, 0.964610, 1.285306, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.020343, 0.295887, 0.630096, 1.247585, 2.482563",\
+ "0.025257, 0.296852, 0.632059, 1.247585, 2.482563",\
+ "0.038535, 0.299143, 0.632095, 1.247585, 2.482563",\
+ "0.050320, 0.302473, 0.632193, 1.247585, 2.482563",\
+ "0.124837, 0.341325, 0.638465, 1.250160, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.064792, 0.171653, 0.283425, 0.487864, 0.896742",\
+ "0.152284, 0.258972, 0.370706, 0.575169, 0.984096",\
+ "0.232529, 0.339311, 0.450733, 0.655198, 1.064127",\
+ "0.289052, 0.396859, 0.508277, 0.712443, 1.120775",\
+ "0.581256, 0.700191, 0.811913, 1.015459, 1.422552");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.021933, 0.185126, 0.386052, 0.758836, 1.504404",\
+ "0.021933, 0.185264, 0.386558, 0.758836, 1.504404",\
+ "0.022969, 0.185264, 0.386558, 0.758836, 1.504404",\
+ "0.025189, 0.185264, 0.386558, 0.758836, 1.504404",\
+ "0.044032, 0.189320, 0.386558, 0.758836, 1.504684");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[65]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.044997, 0.199162, 0.375038, 0.698306, 1.344843",\
+ "0.131049, 0.286337, 0.462145, 0.785022, 1.430777",\
+ "0.213199, 0.374466, 0.550102, 0.872645, 1.517732",\
+ "0.270183, 0.438865, 0.614219, 0.936559, 1.581241",\
+ "0.564592, 0.788723, 0.964610, 1.285306, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.020343, 0.295887, 0.630096, 1.246366, 2.473547",\
+ "0.025257, 0.296852, 0.632059, 1.246366, 2.473547",\
+ "0.038535, 0.299143, 0.632095, 1.246442, 2.473547",\
+ "0.050320, 0.302473, 0.632193, 1.247184, 2.473547",\
+ "0.124837, 0.341325, 0.638465, 1.250160, 2.473547");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.064792, 0.171653, 0.283425, 0.487864, 0.896742",\
+ "0.152284, 0.258972, 0.370706, 0.575169, 0.984096",\
+ "0.232529, 0.339311, 0.450733, 0.655198, 1.064127",\
+ "0.289052, 0.396859, 0.508277, 0.712443, 1.120775",\
+ "0.581256, 0.700191, 0.811913, 1.015459, 1.422552");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.021933, 0.184336, 0.384548, 0.756608, 1.500727",\
+ "0.021933, 0.184336, 0.384548, 0.756608, 1.500727",\
+ "0.022969, 0.184336, 0.384548, 0.756608, 1.500727",\
+ "0.025189, 0.184950, 0.385003, 0.757508, 1.502518",\
+ "0.044032, 0.189320, 0.385072, 0.758276, 1.504684");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[65]_redg_min*/
+
+} /* end of pin tl_o[65] */
+
+pin("tl_o[64]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.153409 ;
+ min_capacitance : 0.000000 ;
+ max_fanout : 50.000000 ;
+ function : "0" ;
+ capacitance : 0.009004 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[64];
+} /* end of pin tl_o[64] */
+
+pin("tl_o[63]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.153409 ;
+ min_capacitance : 0.000000 ;
+ max_fanout : 50.000000 ;
+ function : "0" ;
+ capacitance : 0.009004 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[63];
+} /* end of pin tl_o[63] */
+
+pin("tl_o[62]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002088 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[62];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.048389, 0.201372, 0.376697, 0.699413, 1.344843",\
+ "0.134717, 0.288547, 0.463802, 0.786127, 1.430777",\
+ "0.217972, 0.376674, 0.551758, 0.873749, 1.517732",\
+ "0.275938, 0.441068, 0.615873, 0.937662, 1.581241",\
+ "0.576253, 0.790939, 0.966256, 1.286403, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.024378, 0.300079, 0.633266, 1.249698, 2.482563",\
+ "0.028867, 0.301069, 0.635212, 1.249698, 2.482563",\
+ "0.041784, 0.303321, 0.635248, 1.249698, 2.482563",\
+ "0.053694, 0.306596, 0.635350, 1.249698, 2.482563",\
+ "0.129380, 0.344908, 0.641605, 1.252253, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.068004, 0.173028, 0.284443, 0.488532, 0.896711",\
+ "0.155415, 0.260346, 0.371724, 0.575838, 0.984064",\
+ "0.235777, 0.340680, 0.451751, 0.655866, 1.064096",\
+ "0.292479, 0.398229, 0.509294, 0.713111, 1.120744",\
+ "0.586381, 0.701567, 0.812926, 1.016124, 1.422520");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.024753, 0.187586, 0.387908, 0.760055, 1.504347",\
+ "0.024753, 0.187732, 0.388412, 0.760055, 1.504347",\
+ "0.025828, 0.187732, 0.388412, 0.760055, 1.504347",\
+ "0.027889, 0.187732, 0.388412, 0.760055, 1.504347",\
+ "0.046464, 0.191695, 0.388412, 0.760055, 1.504627");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[62]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.048389, 0.201372, 0.376697, 0.699413, 1.344843",\
+ "0.134717, 0.288547, 0.463802, 0.786127, 1.430777",\
+ "0.217972, 0.376674, 0.551758, 0.873749, 1.517732",\
+ "0.275938, 0.441068, 0.615873, 0.937662, 1.581241",\
+ "0.576253, 0.790939, 0.966256, 1.286403, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.024378, 0.300079, 0.633266, 1.248468, 2.473548",\
+ "0.028867, 0.301069, 0.635212, 1.248468, 2.473548",\
+ "0.041784, 0.303321, 0.635248, 1.248544, 2.473548",\
+ "0.053694, 0.306596, 0.635350, 1.249288, 2.473548",\
+ "0.129380, 0.344908, 0.641605, 1.252253, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.068004, 0.173028, 0.284443, 0.488532, 0.896711",\
+ "0.155415, 0.260346, 0.371724, 0.575838, 0.984064",\
+ "0.235777, 0.340680, 0.451751, 0.655866, 1.064096",\
+ "0.292479, 0.398229, 0.509294, 0.713111, 1.120744",\
+ "0.586381, 0.701567, 0.812926, 1.016124, 1.422520");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.024753, 0.186786, 0.386401, 0.757824, 1.500670",\
+ "0.024753, 0.186786, 0.386401, 0.757824, 1.500670",\
+ "0.025828, 0.186786, 0.386401, 0.757824, 1.500670",\
+ "0.027889, 0.187397, 0.386858, 0.758726, 1.502461",\
+ "0.046464, 0.191695, 0.386930, 0.759496, 1.504627");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[62]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024378, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.218049, 0.171947, 0.141734, 0.130380, 0.144005",\
+ "0.225343, 0.179241, 0.149028, 0.137673, 0.151299",\
+ "0.298206, 0.252060, 0.221844, 0.210487, 0.224097",\
+ "0.392136, 0.345682, 0.315442, 0.304067, 0.317572",\
+ "0.819837, 0.772019, 0.741401, 0.729820, 0.742723");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.263674, 0.188357, 0.120223, 0.097297, 0.160585",\
+ "0.270643, 0.195326, 0.127193, 0.104267, 0.167554",\
+ "0.342134, 0.266818, 0.198684, 0.175758, 0.239045",\
+ "0.448695, 0.373390, 0.305321, 0.282500, 0.346742",\
+ "0.946962, 0.871764, 0.804107, 0.782042, 0.853404");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[62]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024378, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139030, -0.096614, -0.062124, -0.022751, 0.282672",\
+ "-0.146290, -0.103874, -0.069385, -0.030012, 0.275412",\
+ "-0.217578, -0.175163, -0.140673, -0.101300, 0.204124",\
+ "-0.305582, -0.263210, -0.228618, -0.191228, 0.089586",\
+ "-0.705049, -0.662905, -0.627627, -0.603487, -0.487141");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.129024, -0.063245, -0.005781, 0.036127, 0.257073",\
+ "-0.136957, -0.071178, -0.013715, 0.028194, 0.249139",\
+ "-0.213653, -0.147874, -0.090410, -0.048501, 0.172444",\
+ "-0.315404, -0.249338, -0.191464, -0.149444, 0.070790",\
+ "-0.774971, -0.707116, -0.646741, -0.604032, -0.387962");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[62]_hldr*/
+
+} /* end of pin tl_o[62] */
+
+pin("tl_o[61]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.153409 ;
+ min_capacitance : 0.000000 ;
+ max_fanout : 50.000000 ;
+ function : "0" ;
+ capacitance : 0.009004 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[61];
+} /* end of pin tl_o[61] */
+
+pin("tl_o[60]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.153409 ;
+ min_capacitance : 0.000000 ;
+ max_fanout : 50.000000 ;
+ function : "0" ;
+ capacitance : 0.009004 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[60];
+} /* end of pin tl_o[60] */
+
+pin("tl_o[59]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.153409 ;
+ min_capacitance : 0.000000 ;
+ max_fanout : 50.000000 ;
+ function : "0" ;
+ capacitance : 0.009004 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[59];
+} /* end of pin tl_o[59] */
+
+pin("tl_o[58]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003360 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[58];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.051828, 0.203934, 0.378621, 0.700695, 1.344843",\
+ "0.138345, 0.291109, 0.465724, 0.787408, 1.430777",\
+ "0.222447, 0.379233, 0.553677, 0.875029, 1.517732",\
+ "0.281266, 0.443623, 0.617791, 0.938941, 1.581241",\
+ "0.586734, 0.793508, 0.968165, 1.287675, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.028994, 0.304939, 0.636940, 1.252148, 2.482564",\
+ "0.033002, 0.305957, 0.638867, 1.252148, 2.482564",\
+ "0.045411, 0.308165, 0.638904, 1.252148, 2.482564",\
+ "0.057383, 0.311375, 0.639010, 1.252148, 2.482564",\
+ "0.134005, 0.349063, 0.645245, 1.254679, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.070957, 0.174574, 0.285576, 0.489260, 0.896627",\
+ "0.158358, 0.261892, 0.372857, 0.576565, 0.983980",\
+ "0.238767, 0.342220, 0.452884, 0.656593, 1.064012",\
+ "0.295587, 0.399770, 0.510425, 0.713837, 1.120660",\
+ "0.590723, 0.703115, 0.814054, 1.016848, 1.422437");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.027799, 0.190353, 0.389974, 0.761380, 1.504194",\
+ "0.027799, 0.190507, 0.390474, 0.761380, 1.504194",\
+ "0.028742, 0.190507, 0.390474, 0.761380, 1.504194",\
+ "0.030673, 0.190507, 0.390474, 0.761380, 1.504194",\
+ "0.048664, 0.194365, 0.390474, 0.761380, 1.504474");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[58]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.051828, 0.203934, 0.378621, 0.700695, 1.344843",\
+ "0.138345, 0.291109, 0.465724, 0.787408, 1.430777",\
+ "0.222447, 0.379233, 0.553677, 0.875029, 1.517732",\
+ "0.281266, 0.443623, 0.617791, 0.938941, 1.581241",\
+ "0.586734, 0.793508, 0.968165, 1.287675, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.028994, 0.304939, 0.636940, 1.250905, 2.473548",\
+ "0.033002, 0.305957, 0.638867, 1.250905, 2.473548",\
+ "0.045411, 0.308165, 0.638904, 1.250981, 2.473548",\
+ "0.057383, 0.311375, 0.639010, 1.251728, 2.473548",\
+ "0.134005, 0.349063, 0.645245, 1.254679, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.070957, 0.174574, 0.285576, 0.489260, 0.896627",\
+ "0.158358, 0.261892, 0.372857, 0.576565, 0.983980",\
+ "0.238767, 0.342220, 0.452884, 0.656593, 1.064012",\
+ "0.295587, 0.399770, 0.510425, 0.713837, 1.120660",\
+ "0.590723, 0.703115, 0.814054, 1.016848, 1.422437");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.027799, 0.189542, 0.388462, 0.759147, 1.500517",\
+ "0.027799, 0.189542, 0.388462, 0.759147, 1.500517",\
+ "0.028742, 0.189542, 0.388462, 0.759147, 1.500517",\
+ "0.030673, 0.190148, 0.388922, 0.760051, 1.502309",\
+ "0.048664, 0.194365, 0.388998, 0.760823, 1.504474");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[58]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028994, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.218252, 0.172323, 0.142124, 0.130780, 0.144465",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027799, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.252073, 0.176751, 0.108592, 0.085625, 0.148539",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[58]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028994, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.150180, -0.107763, -0.073276, -0.033852, 0.272195",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027799, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.165228, -0.099313, -0.041654, 0.000307, 0.220914",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[58]_hldr*/
+
+} /* end of pin tl_o[58] */
+
+pin("tl_o[57]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002160 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[57];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.048582, 0.201516, 0.376805, 0.699484, 1.344843",\
+ "0.134920, 0.288690, 0.463910, 0.786199, 1.430777",\
+ "0.218223, 0.376818, 0.551865, 0.873821, 1.517732",\
+ "0.276237, 0.441212, 0.615981, 0.937734, 1.581241",\
+ "0.576841, 0.791083, 0.966363, 1.286475, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.024637, 0.300352, 0.633472, 1.249836, 2.482563",\
+ "0.029099, 0.301343, 0.635417, 1.249836, 2.482563",\
+ "0.041988, 0.303593, 0.635453, 1.249836, 2.482563",\
+ "0.053901, 0.306864, 0.635555, 1.249836, 2.482563",\
+ "0.129639, 0.345141, 0.641809, 1.252389, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.068110, 0.173083, 0.284476, 0.488542, 0.896675",\
+ "0.155520, 0.260402, 0.371756, 0.575847, 0.984028",\
+ "0.235884, 0.340735, 0.451783, 0.655876, 1.064060",\
+ "0.292590, 0.398284, 0.509326, 0.713120, 1.120708",\
+ "0.586537, 0.701623, 0.812958, 1.016134, 1.422485");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.024862, 0.187685, 0.387967, 0.760072, 1.504282",\
+ "0.024862, 0.187831, 0.388471, 0.760072, 1.504282",\
+ "0.025932, 0.187831, 0.388471, 0.760072, 1.504282",\
+ "0.027989, 0.187831, 0.388471, 0.760072, 1.504282",\
+ "0.046543, 0.191790, 0.388471, 0.760072, 1.504562");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[57]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.048582, 0.201516, 0.376805, 0.699484, 1.344843",\
+ "0.134920, 0.288690, 0.463910, 0.786199, 1.430777",\
+ "0.218223, 0.376818, 0.551865, 0.873821, 1.517732",\
+ "0.276237, 0.441212, 0.615981, 0.937734, 1.581241",\
+ "0.576841, 0.791083, 0.966363, 1.286475, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.024637, 0.300352, 0.633472, 1.248605, 2.473548",\
+ "0.029099, 0.301343, 0.635417, 1.248605, 2.473548",\
+ "0.041988, 0.303593, 0.635453, 1.248680, 2.473548",\
+ "0.053901, 0.306864, 0.635555, 1.249425, 2.473548",\
+ "0.129639, 0.345141, 0.641809, 1.252389, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.068110, 0.173083, 0.284476, 0.488542, 0.896675",\
+ "0.155520, 0.260402, 0.371756, 0.575847, 0.984028",\
+ "0.235884, 0.340735, 0.451783, 0.655876, 1.064060",\
+ "0.292590, 0.398284, 0.509326, 0.713120, 1.120708",\
+ "0.586537, 0.701623, 0.812958, 1.016134, 1.422485");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.024862, 0.186885, 0.386460, 0.757841, 1.500604",\
+ "0.024862, 0.186885, 0.386460, 0.757841, 1.500604",\
+ "0.025932, 0.186885, 0.386460, 0.757841, 1.500604",\
+ "0.027989, 0.187495, 0.386917, 0.758743, 1.502396",\
+ "0.046543, 0.191790, 0.386989, 0.759514, 1.504562");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[57]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024637, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216235, 0.170306, 0.140106, 0.128763, 0.142448",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024862, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250736, 0.175414, 0.107255, 0.084288, 0.147202",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[57]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024637, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148162, -0.105745, -0.071258, -0.031835, 0.274212",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024862, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163891, -0.097976, -0.040317, 0.001644, 0.222251",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[57]_hldr*/
+
+} /* end of pin tl_o[57] */
+
+pin("tl_o[56]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000498 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[56];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\
+ "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\
+ "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\
+ "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\
+ "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.042695, 0.188280, 0.385754, 0.758318, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[56]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\
+ "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\
+ "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\
+ "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\
+ "0.042695, 0.188280, 0.384266, 0.757757, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[56]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[56]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[56]_hldr*/
+
+} /* end of pin tl_o[56] */
+
+pin("tl_o[55]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000498 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[55];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\
+ "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\
+ "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\
+ "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\
+ "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.042695, 0.188280, 0.385754, 0.758318, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[55]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\
+ "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\
+ "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\
+ "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\
+ "0.042695, 0.188280, 0.384266, 0.757757, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[55]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[55]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[55]_hldr*/
+
+} /* end of pin tl_o[55] */
+
+pin("tl_o[54]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000498 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[54];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\
+ "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\
+ "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\
+ "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\
+ "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.042695, 0.188280, 0.385754, 0.758318, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[54]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\
+ "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\
+ "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\
+ "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\
+ "0.042695, 0.188280, 0.384266, 0.757757, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[54]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[54]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[54]_hldr*/
+
+} /* end of pin tl_o[54] */
+
+pin("tl_o[53]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000498 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[53];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\
+ "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\
+ "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\
+ "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\
+ "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.042695, 0.188280, 0.385754, 0.758318, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[53]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\
+ "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\
+ "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\
+ "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\
+ "0.042695, 0.188280, 0.384266, 0.757757, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[53]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[53]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[53]_hldr*/
+
+} /* end of pin tl_o[53] */
+
+pin("tl_o[52]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000498 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[52];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\
+ "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\
+ "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\
+ "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\
+ "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.042695, 0.188280, 0.385754, 0.758318, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[52]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\
+ "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\
+ "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\
+ "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\
+ "0.042695, 0.188280, 0.384266, 0.757757, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[52]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[52]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[52]_hldr*/
+
+} /* end of pin tl_o[52] */
+
+pin("tl_o[51]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000498 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[51];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\
+ "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\
+ "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\
+ "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\
+ "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.042695, 0.188280, 0.385754, 0.758318, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[51]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\
+ "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\
+ "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\
+ "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\
+ "0.042695, 0.188280, 0.384266, 0.757757, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[51]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[51]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[51]_hldr*/
+
+} /* end of pin tl_o[51] */
+
+pin("tl_o[50]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000498 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[50];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\
+ "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\
+ "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\
+ "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\
+ "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.042695, 0.188280, 0.385754, 0.758318, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[50]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\
+ "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\
+ "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\
+ "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\
+ "0.042695, 0.188280, 0.384266, 0.757757, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[50]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[50]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[50]_hldr*/
+
+} /* end of pin tl_o[50] */
+
+pin("tl_o[49]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000498 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[49];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\
+ "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\
+ "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\
+ "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\
+ "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\
+ "0.042695, 0.188280, 0.385754, 0.758318, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[49]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\
+ "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\
+ "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\
+ "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\
+ "0.557497, 0.787726, 0.963869, 1.284812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\
+ "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\
+ "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\
+ "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\
+ "0.122402, 0.339712, 0.637052, 1.249217, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\
+ "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\
+ "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\
+ "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\
+ "0.578289, 0.699588, 0.811473, 1.015176, 1.422582");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011");
+ values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\
+ "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\
+ "0.042695, 0.188280, 0.384266, 0.757757, 1.504740");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[49]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[49]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[49]_hldr*/
+
+} /* end of pin tl_o[49] */
+
+pin("tl_o[48]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.153409 ;
+ min_capacitance : 0.000000 ;
+ max_fanout : 50.000000 ;
+ function : "0" ;
+ capacitance : 0.009004 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[48];
+} /* end of pin tl_o[48] */
+
+pin("tl_o[47]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002792 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[47];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.050293, 0.202790, 0.377762, 0.700122, 1.344843",\
+ "0.136725, 0.289965, 0.464866, 0.786836, 1.430777",\
+ "0.220450, 0.378091, 0.552820, 0.874457, 1.517732",\
+ "0.278888, 0.442483, 0.616935, 0.938370, 1.581241",\
+ "0.582056, 0.792362, 0.967313, 1.287108, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.026933, 0.302770, 0.635300, 1.251054, 2.482563",\
+ "0.031156, 0.303775, 0.637236, 1.251054, 2.482563",\
+ "0.043792, 0.306003, 0.637272, 1.251054, 2.482563",\
+ "0.055737, 0.309242, 0.637376, 1.251054, 2.482563",\
+ "0.131941, 0.347209, 0.643620, 1.253596, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.069683, 0.173907, 0.285093, 0.488958, 0.896688",\
+ "0.157089, 0.261225, 0.372374, 0.576263, 0.984041",\
+ "0.237477, 0.341556, 0.452401, 0.656292, 1.064073",\
+ "0.294246, 0.399105, 0.509943, 0.713536, 1.120720",\
+ "0.588850, 0.702448, 0.813573, 1.016548, 1.422497");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.026485, 0.189160, 0.389094, 0.760831, 1.504305",\
+ "0.026485, 0.189310, 0.389596, 0.760831, 1.504305",\
+ "0.027485, 0.189310, 0.389596, 0.760831, 1.504305",\
+ "0.029472, 0.189310, 0.389596, 0.760831, 1.504305",\
+ "0.047715, 0.193213, 0.389596, 0.760831, 1.504585");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[47]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.050293, 0.202790, 0.377762, 0.700122, 1.344843",\
+ "0.136725, 0.289965, 0.464866, 0.786836, 1.430777",\
+ "0.220450, 0.378091, 0.552820, 0.874457, 1.517732",\
+ "0.278888, 0.442483, 0.616935, 0.938370, 1.581241",\
+ "0.582056, 0.792362, 0.967313, 1.287108, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.026933, 0.302770, 0.635300, 1.249818, 2.473548",\
+ "0.031156, 0.303775, 0.637236, 1.249818, 2.473548",\
+ "0.043792, 0.306003, 0.637272, 1.249893, 2.473548",\
+ "0.055737, 0.309242, 0.637376, 1.250639, 2.473548",\
+ "0.131941, 0.347209, 0.643620, 1.253596, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.069683, 0.173907, 0.285093, 0.488958, 0.896688",\
+ "0.157089, 0.261225, 0.372374, 0.576263, 0.984041",\
+ "0.237477, 0.341556, 0.452401, 0.656292, 1.064073",\
+ "0.294246, 0.399105, 0.509943, 0.713536, 1.120720",\
+ "0.588850, 0.702448, 0.813573, 1.016548, 1.422497");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.026485, 0.188353, 0.387584, 0.758599, 1.500628",\
+ "0.026485, 0.188353, 0.387584, 0.758599, 1.500628",\
+ "0.027485, 0.188353, 0.387584, 0.758599, 1.500628",\
+ "0.029472, 0.188961, 0.388043, 0.759501, 1.502419",\
+ "0.047715, 0.193213, 0.388117, 0.760273, 1.504585");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[47]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026933, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.213301, 0.167430, 0.137235, 0.125895, 0.139600",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026485, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266577, 0.191265, 0.123161, 0.100283, 0.164008",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[47]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026933, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.141091, -0.098663, -0.064202, -0.024280, 0.287954",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026485, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174450, -0.108363, -0.050457, -0.008429, 0.211751",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[47]_hldr*/
+
+} /* end of pin tl_o[47] */
+
+pin("tl_o[46]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001816 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[46];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\
+ "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\
+ "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\
+ "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\
+ "0.574010, 0.790389, 0.965848, 1.286131, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.023390, 0.299039, 0.632479, 1.249174, 2.482563",\
+ "0.027983, 0.300023, 0.634430, 1.249174, 2.482563",\
+ "0.041008, 0.302285, 0.634466, 1.249174, 2.482563",\
+ "0.052904, 0.305573, 0.634567, 1.249174, 2.482563",\
+ "0.128390, 0.344019, 0.640826, 1.251733, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\
+ "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\
+ "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\
+ "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\
+ "0.585433, 0.701229, 0.812678, 1.015963, 1.422532");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.024087, 0.186982, 0.387454, 0.759758, 1.504368",\
+ "0.024087, 0.187126, 0.387958, 0.759758, 1.504368",\
+ "0.025192, 0.187126, 0.387958, 0.759758, 1.504368",\
+ "0.027281, 0.187126, 0.387958, 0.759758, 1.504368",\
+ "0.045983, 0.191111, 0.387958, 0.759758, 1.504648");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[46]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\
+ "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\
+ "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\
+ "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\
+ "0.574010, 0.790389, 0.965848, 1.286131, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.023390, 0.299039, 0.632479, 1.247947, 2.473548",\
+ "0.027983, 0.300023, 0.634430, 1.247947, 2.473548",\
+ "0.041008, 0.302285, 0.634466, 1.248022, 2.473548",\
+ "0.052904, 0.305573, 0.634567, 1.248766, 2.473548",\
+ "0.128390, 0.344019, 0.640826, 1.251733, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\
+ "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\
+ "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\
+ "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\
+ "0.585433, 0.701229, 0.812678, 1.015963, 1.422532");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\
+ "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\
+ "0.025192, 0.186184, 0.385947, 0.757528, 1.500690",\
+ "0.027281, 0.186796, 0.386404, 0.758430, 1.502482",\
+ "0.045983, 0.191111, 0.386476, 0.759200, 1.504648");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[46]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.211804, 0.165933, 0.135738, 0.124398, 0.138103",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.265681, 0.190370, 0.122265, 0.099388, 0.163112",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[46]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.139610, -0.097182, -0.062721, -0.022799, 0.289435",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173560, -0.107472, -0.049566, -0.007539, 0.212641",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[46]_hldr*/
+
+} /* end of pin tl_o[46] */
+
+pin("tl_o[45]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002729 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[45];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.050122, 0.202663, 0.377667, 0.700059, 1.344843",\
+ "0.136545, 0.289838, 0.464771, 0.786773, 1.430777",\
+ "0.220228, 0.377964, 0.552725, 0.874394, 1.517732",\
+ "0.278624, 0.442356, 0.616840, 0.938307, 1.581241",\
+ "0.581536, 0.792234, 0.967218, 1.287045, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.026704, 0.302529, 0.635118, 1.250933, 2.482563",\
+ "0.030951, 0.303532, 0.637054, 1.250933, 2.482563",\
+ "0.043612, 0.305763, 0.637091, 1.250933, 2.482563",\
+ "0.055554, 0.309005, 0.637195, 1.250933, 2.482563",\
+ "0.131711, 0.347003, 0.643440, 1.253476, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.069519, 0.173822, 0.285028, 0.488913, 0.896683",\
+ "0.156925, 0.261140, 0.372309, 0.576218, 0.984036",\
+ "0.237311, 0.341470, 0.452336, 0.656247, 1.064068",\
+ "0.294074, 0.399020, 0.509878, 0.713491, 1.120715",\
+ "0.588609, 0.702362, 0.813509, 1.016503, 1.422492");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.026316, 0.189006, 0.388975, 0.760749, 1.504296",\
+ "0.026316, 0.189156, 0.389477, 0.760749, 1.504296",\
+ "0.027323, 0.189156, 0.389477, 0.760749, 1.504296",\
+ "0.029318, 0.189156, 0.389477, 0.760749, 1.504296",\
+ "0.047593, 0.193065, 0.389477, 0.760749, 1.504576");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[45]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.050122, 0.202663, 0.377667, 0.700059, 1.344843",\
+ "0.136545, 0.289838, 0.464771, 0.786773, 1.430777",\
+ "0.220228, 0.377964, 0.552725, 0.874394, 1.517732",\
+ "0.278624, 0.442356, 0.616840, 0.938307, 1.581241",\
+ "0.581536, 0.792234, 0.967218, 1.287045, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.026704, 0.302529, 0.635118, 1.249697, 2.473548",\
+ "0.030951, 0.303532, 0.637054, 1.249697, 2.473548",\
+ "0.043612, 0.305763, 0.637091, 1.249772, 2.473548",\
+ "0.055554, 0.309005, 0.637195, 1.250518, 2.473548",\
+ "0.131711, 0.347003, 0.643440, 1.253476, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.069519, 0.173822, 0.285028, 0.488913, 0.896683",\
+ "0.156925, 0.261140, 0.372309, 0.576218, 0.984036",\
+ "0.237311, 0.341470, 0.452336, 0.656247, 1.064068",\
+ "0.294074, 0.399020, 0.509878, 0.713491, 1.120715",\
+ "0.588609, 0.702362, 0.813509, 1.016503, 1.422492");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.026316, 0.188200, 0.387466, 0.758517, 1.500619",\
+ "0.026316, 0.188200, 0.387466, 0.758517, 1.500619",\
+ "0.027323, 0.188200, 0.387466, 0.758517, 1.500619",\
+ "0.029318, 0.188809, 0.387924, 0.759419, 1.502410",\
+ "0.047593, 0.193065, 0.387998, 0.760191, 1.504576");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[45]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026704, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.213204, 0.167333, 0.137138, 0.125798, 0.139503",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026316, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266513, 0.191202, 0.123098, 0.100220, 0.163945",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[45]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026704, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140996, -0.098567, -0.064106, -0.024184, 0.288050",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026316, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174387, -0.108300, -0.050394, -0.008366, 0.211814",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[45]_hldr*/
+
+} /* end of pin tl_o[45] */
+
+pin("tl_o[44]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002742 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[44];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.050158, 0.202690, 0.377687, 0.700072, 1.344843",\
+ "0.136583, 0.289865, 0.464791, 0.786786, 1.430777",\
+ "0.220274, 0.377991, 0.552745, 0.874407, 1.517732",\
+ "0.278679, 0.442383, 0.616860, 0.938320, 1.581241",\
+ "0.581645, 0.792261, 0.967238, 1.287058, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.026752, 0.302579, 0.635156, 1.250959, 2.482563",\
+ "0.030994, 0.303583, 0.637092, 1.250959, 2.482563",\
+ "0.043650, 0.305813, 0.637129, 1.250959, 2.482563",\
+ "0.055592, 0.309055, 0.637233, 1.250959, 2.482563",\
+ "0.131760, 0.347046, 0.643478, 1.253501, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.069547, 0.173836, 0.285039, 0.488919, 0.896680",\
+ "0.156953, 0.261154, 0.372320, 0.576224, 0.984034",\
+ "0.237340, 0.341485, 0.452347, 0.656253, 1.064065",\
+ "0.294104, 0.399034, 0.509889, 0.713497, 1.120713",\
+ "0.588650, 0.702376, 0.813519, 1.016509, 1.422490");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.026345, 0.189032, 0.388994, 0.760760, 1.504292",\
+ "0.026345, 0.189182, 0.389496, 0.760760, 1.504292",\
+ "0.027351, 0.189182, 0.389496, 0.760760, 1.504292",\
+ "0.029344, 0.189182, 0.389496, 0.760760, 1.504292",\
+ "0.047614, 0.193091, 0.389496, 0.760760, 1.504572");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[44]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.050158, 0.202690, 0.377687, 0.700072, 1.344843",\
+ "0.136583, 0.289865, 0.464791, 0.786786, 1.430777",\
+ "0.220274, 0.377991, 0.552745, 0.874407, 1.517732",\
+ "0.278679, 0.442383, 0.616860, 0.938320, 1.581241",\
+ "0.581645, 0.792261, 0.967238, 1.287058, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.026752, 0.302579, 0.635156, 1.249722, 2.473548",\
+ "0.030994, 0.303583, 0.637092, 1.249722, 2.473548",\
+ "0.043650, 0.305813, 0.637129, 1.249798, 2.473548",\
+ "0.055592, 0.309055, 0.637233, 1.250543, 2.473548",\
+ "0.131760, 0.347046, 0.643478, 1.253501, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.069547, 0.173836, 0.285039, 0.488919, 0.896680",\
+ "0.156953, 0.261154, 0.372320, 0.576224, 0.984034",\
+ "0.237340, 0.341485, 0.452347, 0.656253, 1.064065",\
+ "0.294104, 0.399034, 0.509889, 0.713497, 1.120713",\
+ "0.588650, 0.702376, 0.813519, 1.016509, 1.422490");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.026345, 0.188226, 0.387484, 0.758528, 1.500614",\
+ "0.026345, 0.188226, 0.387484, 0.758528, 1.500614",\
+ "0.027351, 0.188226, 0.387484, 0.758528, 1.500614",\
+ "0.029344, 0.188835, 0.387943, 0.759431, 1.502406",\
+ "0.047614, 0.193091, 0.388017, 0.760202, 1.504572");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[44]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026752, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.213225, 0.167354, 0.137159, 0.125818, 0.139523",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026345, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266524, 0.191213, 0.123109, 0.100231, 0.163955",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[44]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026752, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.141016, -0.098588, -0.064126, -0.024204, 0.288030",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026345, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174398, -0.108311, -0.050405, -0.008377, 0.211803",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[44]_hldr*/
+
+} /* end of pin tl_o[44] */
+
+pin("tl_o[43]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002272 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[43];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.048885, 0.201742, 0.376975, 0.699598, 1.344843",\
+ "0.135240, 0.288916, 0.464080, 0.786312, 1.430777",\
+ "0.218618, 0.377044, 0.552035, 0.873934, 1.517732",\
+ "0.276707, 0.441437, 0.616150, 0.937847, 1.581241",\
+ "0.577766, 0.791310, 0.966532, 1.286587, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.025044, 0.300781, 0.633796, 1.250052, 2.482563",\
+ "0.029464, 0.301774, 0.635740, 1.250052, 2.482563",\
+ "0.042308, 0.304021, 0.635776, 1.250052, 2.482563",\
+ "0.054226, 0.307286, 0.635878, 1.250052, 2.482563",\
+ "0.130048, 0.345508, 0.642131, 1.252603, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.068436, 0.173254, 0.284610, 0.488640, 0.896702",\
+ "0.155845, 0.260572, 0.371891, 0.575945, 0.984055",\
+ "0.236214, 0.340905, 0.451917, 0.655974, 1.064087",\
+ "0.292933, 0.398454, 0.509460, 0.713218, 1.120734",\
+ "0.587016, 0.701794, 0.813092, 1.016232, 1.422511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.025198, 0.187991, 0.388212, 0.760251, 1.504330",\
+ "0.025198, 0.188138, 0.388715, 0.760251, 1.504330",\
+ "0.026254, 0.188138, 0.388715, 0.760251, 1.504330",\
+ "0.028296, 0.188138, 0.388715, 0.760251, 1.504330",\
+ "0.046785, 0.192085, 0.388715, 0.760251, 1.504610");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[43]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.048885, 0.201742, 0.376975, 0.699598, 1.344843",\
+ "0.135240, 0.288916, 0.464080, 0.786312, 1.430777",\
+ "0.218618, 0.377044, 0.552035, 0.873934, 1.517732",\
+ "0.276707, 0.441437, 0.616150, 0.937847, 1.581241",\
+ "0.577766, 0.791310, 0.966532, 1.286587, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.025044, 0.300781, 0.633796, 1.248820, 2.473548",\
+ "0.029464, 0.301774, 0.635740, 1.248820, 2.473548",\
+ "0.042308, 0.304021, 0.635776, 1.248896, 2.473548",\
+ "0.054226, 0.307286, 0.635878, 1.249640, 2.473548",\
+ "0.130048, 0.345508, 0.642131, 1.252603, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.068436, 0.173254, 0.284610, 0.488640, 0.896702",\
+ "0.155845, 0.260572, 0.371891, 0.575945, 0.984055",\
+ "0.236214, 0.340905, 0.451917, 0.655974, 1.064087",\
+ "0.292933, 0.398454, 0.509460, 0.713218, 1.120734",\
+ "0.587016, 0.701794, 0.813092, 1.016232, 1.422511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.025198, 0.187189, 0.386704, 0.758020, 1.500653",\
+ "0.025198, 0.187189, 0.386704, 0.758020, 1.500653",\
+ "0.026254, 0.187189, 0.386704, 0.758020, 1.500653",\
+ "0.028296, 0.187799, 0.387161, 0.758922, 1.502445",\
+ "0.046785, 0.192085, 0.387234, 0.759693, 1.504610");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[43]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025044, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212503, 0.166632, 0.136437, 0.125097, 0.138801",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025198, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266096, 0.190785, 0.122680, 0.099803, 0.163527",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[43]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025044, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140302, -0.097874, -0.063412, -0.023490, 0.288744",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025198, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173972, -0.107885, -0.049979, -0.007951, 0.212229",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[43]_hldr*/
+
+} /* end of pin tl_o[43] */
+
+pin("tl_o[42]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002445 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[42];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\
+ "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\
+ "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\
+ "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\
+ "0.579196, 0.791661, 0.966792, 1.286761, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.025674, 0.301444, 0.634297, 1.250386, 2.482563",\
+ "0.030028, 0.302441, 0.636238, 1.250386, 2.482563",\
+ "0.042803, 0.304681, 0.636274, 1.250386, 2.482563",\
+ "0.054730, 0.307938, 0.636378, 1.250386, 2.482563",\
+ "0.130679, 0.346075, 0.642627, 1.252934, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\
+ "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\
+ "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\
+ "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\
+ "0.587553, 0.701985, 0.813226, 1.016311, 1.422480");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.025575, 0.188333, 0.388458, 0.760397, 1.504274",\
+ "0.025575, 0.188481, 0.388961, 0.760397, 1.504274",\
+ "0.026615, 0.188481, 0.388961, 0.760397, 1.504274",\
+ "0.028641, 0.188481, 0.388961, 0.760397, 1.504274",\
+ "0.047058, 0.192416, 0.388961, 0.760397, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[42]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\
+ "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\
+ "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\
+ "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\
+ "0.579196, 0.791661, 0.966792, 1.286761, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.025674, 0.301444, 0.634297, 1.249153, 2.473548",\
+ "0.030028, 0.302441, 0.636238, 1.249153, 2.473548",\
+ "0.042803, 0.304681, 0.636274, 1.249228, 2.473548",\
+ "0.054730, 0.307938, 0.636378, 1.249973, 2.473548",\
+ "0.130679, 0.346075, 0.642627, 1.252934, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\
+ "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\
+ "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\
+ "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\
+ "0.587553, 0.701985, 0.813226, 1.016311, 1.422480");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\
+ "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\
+ "0.026615, 0.187530, 0.386950, 0.758165, 1.500597",\
+ "0.028641, 0.188139, 0.387407, 0.759068, 1.502388",\
+ "0.047058, 0.192416, 0.387481, 0.759838, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[42]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212769, 0.166898, 0.136703, 0.125363, 0.139067",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266237, 0.190925, 0.122821, 0.099943, 0.163668",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[42]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140565, -0.098137, -0.063675, -0.023754, 0.288480",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174112, -0.108025, -0.050119, -0.008091, 0.212089",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[42]_hldr*/
+
+} /* end of pin tl_o[42] */
+
+pin("tl_o[41]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002414 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[41];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\
+ "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\
+ "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\
+ "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\
+ "0.578938, 0.791597, 0.966745, 1.286729, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025560, 0.301324, 0.634207, 1.250326, 2.482563",\
+ "0.029927, 0.302321, 0.636148, 1.250326, 2.482563",\
+ "0.042713, 0.304562, 0.636184, 1.250326, 2.482563",\
+ "0.054639, 0.307820, 0.636287, 1.250326, 2.482563",\
+ "0.130565, 0.345973, 0.642537, 1.252874, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\
+ "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\
+ "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\
+ "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\
+ "0.587529, 0.701976, 0.813228, 1.016322, 1.422511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025558, 0.188317, 0.388460, 0.760417, 1.504331",\
+ "0.025558, 0.188465, 0.388963, 0.760417, 1.504331",\
+ "0.026598, 0.188465, 0.388963, 0.760417, 1.504331",\
+ "0.028625, 0.188465, 0.388963, 0.760417, 1.504331",\
+ "0.047045, 0.192400, 0.388963, 0.760417, 1.504611");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[41]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\
+ "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\
+ "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\
+ "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\
+ "0.578938, 0.791597, 0.966745, 1.286729, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025560, 0.301324, 0.634207, 1.249093, 2.473548",\
+ "0.029927, 0.302321, 0.636148, 1.249093, 2.473548",\
+ "0.042713, 0.304562, 0.636184, 1.249168, 2.473548",\
+ "0.054639, 0.307820, 0.636287, 1.249913, 2.473548",\
+ "0.130565, 0.345973, 0.642537, 1.252874, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\
+ "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\
+ "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\
+ "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\
+ "0.587529, 0.701976, 0.813228, 1.016322, 1.422511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\
+ "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\
+ "0.026598, 0.187514, 0.386952, 0.758186, 1.500654",\
+ "0.028625, 0.188124, 0.387410, 0.759088, 1.502445",\
+ "0.047045, 0.192400, 0.387483, 0.759859, 1.504611");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[41]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212721, 0.166850, 0.136655, 0.125315, 0.139019",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266230, 0.190919, 0.122815, 0.099937, 0.163661",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[41]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140517, -0.098089, -0.063628, -0.023706, 0.288528",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174106, -0.108018, -0.050112, -0.008085, 0.212095",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[41]_hldr*/
+
+} /* end of pin tl_o[41] */
+
+pin("tl_o[40]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001805 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[40];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\
+ "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\
+ "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\
+ "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\
+ "0.573921, 0.790368, 0.965832, 1.286120, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.023351, 0.298998, 0.632448, 1.249153, 2.482563",\
+ "0.027948, 0.299981, 0.634399, 1.249153, 2.482563",\
+ "0.040978, 0.302244, 0.634435, 1.249153, 2.482563",\
+ "0.052873, 0.305533, 0.634536, 1.249153, 2.482563",\
+ "0.128351, 0.343984, 0.640795, 1.251713, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\
+ "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\
+ "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\
+ "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\
+ "0.585410, 0.701221, 0.812673, 1.015961, 1.422537");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.024071, 0.186967, 0.387445, 0.759756, 1.504378",\
+ "0.024071, 0.187111, 0.387949, 0.759756, 1.504378",\
+ "0.025176, 0.187111, 0.387949, 0.759756, 1.504378",\
+ "0.027266, 0.187111, 0.387949, 0.759756, 1.504378",\
+ "0.045971, 0.191097, 0.387949, 0.759756, 1.504658");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[40]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\
+ "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\
+ "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\
+ "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\
+ "0.573921, 0.790368, 0.965832, 1.286120, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.023351, 0.298998, 0.632448, 1.247926, 2.473548",\
+ "0.027948, 0.299981, 0.634399, 1.247926, 2.473548",\
+ "0.040978, 0.302244, 0.634435, 1.248002, 2.473548",\
+ "0.052873, 0.305533, 0.634536, 1.248745, 2.473548",\
+ "0.128351, 0.343984, 0.640795, 1.251713, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\
+ "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\
+ "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\
+ "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\
+ "0.585410, 0.701221, 0.812673, 1.015961, 1.422537");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\
+ "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\
+ "0.025176, 0.186169, 0.385939, 0.757526, 1.500700",\
+ "0.027266, 0.186781, 0.386395, 0.758427, 1.502492",\
+ "0.045971, 0.191097, 0.386467, 0.759197, 1.504658");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[40]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.211788, 0.165917, 0.135722, 0.124381, 0.138086",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.265675, 0.190363, 0.122259, 0.099381, 0.163106",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[40]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.139594, -0.097166, -0.062704, -0.022783, 0.289451",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173554, -0.107466, -0.049560, -0.007532, 0.212647",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[40]_hldr*/
+
+} /* end of pin tl_o[40] */
+
+pin("tl_o[39]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002265 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[39];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.048867, 0.201728, 0.376965, 0.699591, 1.344843",\
+ "0.135221, 0.288903, 0.464069, 0.786305, 1.430777",\
+ "0.218594, 0.377030, 0.552024, 0.873927, 1.517732",\
+ "0.276679, 0.441423, 0.616140, 0.937840, 1.581241",\
+ "0.577710, 0.791296, 0.966522, 1.286580, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.025020, 0.300755, 0.633777, 1.250039, 2.482563",\
+ "0.029442, 0.301748, 0.635720, 1.250039, 2.482563",\
+ "0.042289, 0.303995, 0.635756, 1.250039, 2.482563",\
+ "0.054207, 0.307260, 0.635859, 1.250039, 2.482563",\
+ "0.130023, 0.345486, 0.642111, 1.252590, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.068420, 0.173246, 0.284604, 0.488637, 0.896702",\
+ "0.155830, 0.260564, 0.371885, 0.575942, 0.984056",\
+ "0.236199, 0.340897, 0.451912, 0.655970, 1.064088",\
+ "0.292917, 0.398446, 0.509454, 0.713215, 1.120735",\
+ "0.586994, 0.701786, 0.813086, 1.016228, 1.422512");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.025182, 0.187976, 0.388201, 0.760245, 1.504332",\
+ "0.025182, 0.188123, 0.388704, 0.760245, 1.504332",\
+ "0.026239, 0.188123, 0.388704, 0.760245, 1.504332",\
+ "0.028282, 0.188123, 0.388704, 0.760245, 1.504332",\
+ "0.046774, 0.192071, 0.388704, 0.760245, 1.504612");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[39]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.048867, 0.201728, 0.376965, 0.699591, 1.344843",\
+ "0.135221, 0.288903, 0.464069, 0.786305, 1.430777",\
+ "0.218594, 0.377030, 0.552024, 0.873927, 1.517732",\
+ "0.276679, 0.441423, 0.616140, 0.937840, 1.581241",\
+ "0.577710, 0.791296, 0.966522, 1.286580, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.025020, 0.300755, 0.633777, 1.248807, 2.473548",\
+ "0.029442, 0.301748, 0.635720, 1.248807, 2.473548",\
+ "0.042289, 0.303995, 0.635756, 1.248883, 2.473548",\
+ "0.054207, 0.307260, 0.635859, 1.249627, 2.473548",\
+ "0.130023, 0.345486, 0.642111, 1.252590, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.068420, 0.173246, 0.284604, 0.488637, 0.896702",\
+ "0.155830, 0.260564, 0.371885, 0.575942, 0.984056",\
+ "0.236199, 0.340897, 0.451912, 0.655970, 1.064088",\
+ "0.292917, 0.398446, 0.509454, 0.713215, 1.120735",\
+ "0.586994, 0.701786, 0.813086, 1.016228, 1.422512");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.025182, 0.187175, 0.386693, 0.758014, 1.500654",\
+ "0.025182, 0.187175, 0.386693, 0.758014, 1.500654",\
+ "0.026239, 0.187175, 0.386693, 0.758014, 1.500654",\
+ "0.028282, 0.187785, 0.387151, 0.758916, 1.502446",\
+ "0.046774, 0.192071, 0.387224, 0.759686, 1.504612");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[39]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025020, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212492, 0.166621, 0.136427, 0.125086, 0.138791",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025182, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266090, 0.190779, 0.122675, 0.099797, 0.163521",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[39]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025020, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140291, -0.097863, -0.063402, -0.023480, 0.288754",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025182, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173966, -0.107879, -0.049973, -0.007945, 0.212235",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[39]_hldr*/
+
+} /* end of pin tl_o[39] */
+
+pin("tl_o[38]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002414 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[38];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\
+ "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\
+ "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\
+ "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\
+ "0.578938, 0.791597, 0.966745, 1.286729, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025560, 0.301324, 0.634207, 1.250326, 2.482563",\
+ "0.029927, 0.302321, 0.636148, 1.250326, 2.482563",\
+ "0.042713, 0.304562, 0.636184, 1.250326, 2.482563",\
+ "0.054639, 0.307820, 0.636287, 1.250326, 2.482563",\
+ "0.130565, 0.345973, 0.642537, 1.252874, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\
+ "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\
+ "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\
+ "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\
+ "0.587529, 0.701976, 0.813228, 1.016322, 1.422511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025558, 0.188317, 0.388460, 0.760417, 1.504331",\
+ "0.025558, 0.188465, 0.388963, 0.760417, 1.504331",\
+ "0.026598, 0.188465, 0.388963, 0.760417, 1.504331",\
+ "0.028625, 0.188465, 0.388963, 0.760417, 1.504331",\
+ "0.047045, 0.192400, 0.388963, 0.760417, 1.504611");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[38]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\
+ "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\
+ "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\
+ "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\
+ "0.578938, 0.791597, 0.966745, 1.286729, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025560, 0.301324, 0.634207, 1.249093, 2.473548",\
+ "0.029927, 0.302321, 0.636148, 1.249093, 2.473548",\
+ "0.042713, 0.304562, 0.636184, 1.249168, 2.473548",\
+ "0.054639, 0.307820, 0.636287, 1.249913, 2.473548",\
+ "0.130565, 0.345973, 0.642537, 1.252874, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\
+ "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\
+ "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\
+ "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\
+ "0.587529, 0.701976, 0.813228, 1.016322, 1.422511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\
+ "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\
+ "0.026598, 0.187514, 0.386952, 0.758186, 1.500654",\
+ "0.028625, 0.188124, 0.387410, 0.759088, 1.502445",\
+ "0.047045, 0.192400, 0.387483, 0.759859, 1.504611");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[38]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212721, 0.166850, 0.136655, 0.125315, 0.139019",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266230, 0.190919, 0.122815, 0.099937, 0.163661",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[38]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140517, -0.098089, -0.063628, -0.023706, 0.288528",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174106, -0.108018, -0.050112, -0.008085, 0.212095",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[38]_hldr*/
+
+} /* end of pin tl_o[38] */
+
+pin("tl_o[37]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002445 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[37];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\
+ "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\
+ "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\
+ "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\
+ "0.579196, 0.791661, 0.966792, 1.286761, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.025674, 0.301444, 0.634297, 1.250386, 2.482563",\
+ "0.030028, 0.302441, 0.636238, 1.250386, 2.482563",\
+ "0.042803, 0.304681, 0.636274, 1.250386, 2.482563",\
+ "0.054730, 0.307938, 0.636378, 1.250386, 2.482563",\
+ "0.130679, 0.346075, 0.642627, 1.252934, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\
+ "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\
+ "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\
+ "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\
+ "0.587553, 0.701985, 0.813226, 1.016311, 1.422480");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.025575, 0.188333, 0.388458, 0.760397, 1.504274",\
+ "0.025575, 0.188481, 0.388961, 0.760397, 1.504274",\
+ "0.026615, 0.188481, 0.388961, 0.760397, 1.504274",\
+ "0.028641, 0.188481, 0.388961, 0.760397, 1.504274",\
+ "0.047058, 0.192416, 0.388961, 0.760397, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[37]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\
+ "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\
+ "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\
+ "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\
+ "0.579196, 0.791661, 0.966792, 1.286761, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.025674, 0.301444, 0.634297, 1.249153, 2.473548",\
+ "0.030028, 0.302441, 0.636238, 1.249153, 2.473548",\
+ "0.042803, 0.304681, 0.636274, 1.249228, 2.473548",\
+ "0.054730, 0.307938, 0.636378, 1.249973, 2.473548",\
+ "0.130679, 0.346075, 0.642627, 1.252934, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\
+ "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\
+ "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\
+ "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\
+ "0.587553, 0.701985, 0.813226, 1.016311, 1.422480");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\
+ "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\
+ "0.026615, 0.187530, 0.386950, 0.758165, 1.500597",\
+ "0.028641, 0.188139, 0.387407, 0.759068, 1.502388",\
+ "0.047058, 0.192416, 0.387481, 0.759838, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[37]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212769, 0.166898, 0.136703, 0.125363, 0.139067",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266237, 0.190925, 0.122821, 0.099943, 0.163668",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[37]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140565, -0.098137, -0.063675, -0.023754, 0.288480",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174112, -0.108025, -0.050119, -0.008091, 0.212089",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[37]_hldr*/
+
+} /* end of pin tl_o[37] */
+
+pin("tl_o[36]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001816 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[36];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\
+ "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\
+ "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\
+ "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\
+ "0.574010, 0.790389, 0.965848, 1.286131, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.023390, 0.299039, 0.632479, 1.249174, 2.482563",\
+ "0.027983, 0.300023, 0.634430, 1.249174, 2.482563",\
+ "0.041008, 0.302285, 0.634466, 1.249174, 2.482563",\
+ "0.052904, 0.305573, 0.634567, 1.249174, 2.482563",\
+ "0.128390, 0.344019, 0.640826, 1.251733, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\
+ "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\
+ "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\
+ "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\
+ "0.585433, 0.701229, 0.812678, 1.015963, 1.422532");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.024087, 0.186982, 0.387454, 0.759758, 1.504368",\
+ "0.024087, 0.187126, 0.387958, 0.759758, 1.504368",\
+ "0.025192, 0.187126, 0.387958, 0.759758, 1.504368",\
+ "0.027281, 0.187126, 0.387958, 0.759758, 1.504368",\
+ "0.045983, 0.191111, 0.387958, 0.759758, 1.504648");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[36]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\
+ "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\
+ "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\
+ "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\
+ "0.574010, 0.790389, 0.965848, 1.286131, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.023390, 0.299039, 0.632479, 1.247947, 2.473548",\
+ "0.027983, 0.300023, 0.634430, 1.247947, 2.473548",\
+ "0.041008, 0.302285, 0.634466, 1.248022, 2.473548",\
+ "0.052904, 0.305573, 0.634567, 1.248766, 2.473548",\
+ "0.128390, 0.344019, 0.640826, 1.251733, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\
+ "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\
+ "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\
+ "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\
+ "0.585433, 0.701229, 0.812678, 1.015963, 1.422532");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\
+ "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\
+ "0.025192, 0.186184, 0.385947, 0.757528, 1.500690",\
+ "0.027281, 0.186796, 0.386404, 0.758430, 1.502482",\
+ "0.045983, 0.191111, 0.386476, 0.759200, 1.504648");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[36]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.211804, 0.165933, 0.135738, 0.124398, 0.138103",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.265681, 0.190370, 0.122265, 0.099388, 0.163112",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[36]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.139610, -0.097182, -0.062721, -0.022799, 0.289435",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173560, -0.107472, -0.049566, -0.007539, 0.212641",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[36]_hldr*/
+
+} /* end of pin tl_o[36] */
+
+pin("tl_o[35]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002254 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[35];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\
+ "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\
+ "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\
+ "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\
+ "0.577621, 0.791275, 0.966506, 1.286569, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.024980, 0.300714, 0.633745, 1.250018, 2.482564",\
+ "0.029407, 0.301707, 0.635689, 1.250018, 2.482564",\
+ "0.042258, 0.303954, 0.635725, 1.250018, 2.482564",\
+ "0.054175, 0.307220, 0.635828, 1.250018, 2.482564",\
+ "0.129984, 0.345451, 0.642080, 1.252569, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\
+ "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\
+ "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\
+ "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\
+ "0.586970, 0.701777, 0.813081, 1.016227, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.025166, 0.187961, 0.388192, 0.760242, 1.504342",\
+ "0.025166, 0.188108, 0.388695, 0.760242, 1.504342",\
+ "0.026223, 0.188108, 0.388695, 0.760242, 1.504342",\
+ "0.028267, 0.188108, 0.388695, 0.760242, 1.504342",\
+ "0.046762, 0.192057, 0.388695, 0.760242, 1.504622");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[35]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\
+ "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\
+ "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\
+ "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\
+ "0.577621, 0.791275, 0.966506, 1.286569, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.024980, 0.300714, 0.633745, 1.248787, 2.473548",\
+ "0.029407, 0.301707, 0.635689, 1.248787, 2.473548",\
+ "0.042258, 0.303954, 0.635725, 1.248862, 2.473548",\
+ "0.054175, 0.307220, 0.635828, 1.249606, 2.473548",\
+ "0.129984, 0.345451, 0.642080, 1.252569, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\
+ "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\
+ "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\
+ "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\
+ "0.586970, 0.701777, 0.813081, 1.016227, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\
+ "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\
+ "0.026223, 0.187160, 0.386684, 0.758011, 1.500664",\
+ "0.028267, 0.187770, 0.387142, 0.758913, 1.502456",\
+ "0.046762, 0.192057, 0.387215, 0.759684, 1.504622");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[35]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212476, 0.166605, 0.136410, 0.125070, 0.138775",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266084, 0.190773, 0.122668, 0.099790, 0.163515",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[35]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140275, -0.097847, -0.063386, -0.023464, 0.288770",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173960, -0.107873, -0.049967, -0.007939, 0.212241",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[35]_hldr*/
+
+} /* end of pin tl_o[35] */
+
+pin("tl_o[34]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001996 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[34];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.048141, 0.201187, 0.376558, 0.699320, 1.344843",\
+ "0.134454, 0.288362, 0.463663, 0.786035, 1.430777",\
+ "0.217649, 0.376489, 0.551619, 0.873657, 1.517732",\
+ "0.275553, 0.440884, 0.615735, 0.937570, 1.581241",\
+ "0.575495, 0.790754, 0.966118, 1.286311, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.024044, 0.299728, 0.633000, 1.249521, 2.482563",\
+ "0.028569, 0.300716, 0.634948, 1.249521, 2.482563",\
+ "0.041522, 0.302971, 0.634984, 1.249521, 2.482563",\
+ "0.053427, 0.306251, 0.635086, 1.249521, 2.482563",\
+ "0.129046, 0.344608, 0.641342, 1.252077, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.067740, 0.172889, 0.284335, 0.488454, 0.896691",\
+ "0.155151, 0.260208, 0.371616, 0.575759, 0.984044",\
+ "0.235509, 0.340542, 0.451643, 0.655787, 1.064076",\
+ "0.292201, 0.398091, 0.509186, 0.713032, 1.120723",\
+ "0.585993, 0.701429, 0.812818, 1.016046, 1.422500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.024480, 0.187339, 0.387711, 0.759911, 1.504310",\
+ "0.024480, 0.187483, 0.388215, 0.759911, 1.504310",\
+ "0.025567, 0.187483, 0.388215, 0.759911, 1.504310",\
+ "0.027640, 0.187483, 0.388215, 0.759911, 1.504310",\
+ "0.046267, 0.191456, 0.388215, 0.759911, 1.504590");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[34]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.048141, 0.201187, 0.376558, 0.699320, 1.344843",\
+ "0.134454, 0.288362, 0.463663, 0.786035, 1.430777",\
+ "0.217649, 0.376489, 0.551619, 0.873657, 1.517732",\
+ "0.275553, 0.440884, 0.615735, 0.937570, 1.581241",\
+ "0.575495, 0.790754, 0.966118, 1.286311, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.024044, 0.299728, 0.633000, 1.248292, 2.473548",\
+ "0.028569, 0.300716, 0.634948, 1.248292, 2.473548",\
+ "0.041522, 0.302971, 0.634984, 1.248368, 2.473548",\
+ "0.053427, 0.306251, 0.635086, 1.249112, 2.473548",\
+ "0.129046, 0.344608, 0.641342, 1.252077, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.067740, 0.172889, 0.284335, 0.488454, 0.896691",\
+ "0.155151, 0.260208, 0.371616, 0.575759, 0.984044",\
+ "0.235509, 0.340542, 0.451643, 0.655787, 1.064076",\
+ "0.292201, 0.398091, 0.509186, 0.713032, 1.120723",\
+ "0.585993, 0.701429, 0.812818, 1.016046, 1.422500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.024480, 0.186540, 0.386204, 0.757680, 1.500633",\
+ "0.024480, 0.186540, 0.386204, 0.757680, 1.500633",\
+ "0.025567, 0.186540, 0.386204, 0.757680, 1.500633",\
+ "0.027640, 0.187150, 0.386661, 0.758582, 1.502424",\
+ "0.046267, 0.191456, 0.386733, 0.759352, 1.504590");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[34]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024044, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212080, 0.166210, 0.136015, 0.124674, 0.138379",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024480, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.265828, 0.190516, 0.122412, 0.099534, 0.163259",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[34]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024044, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.139884, -0.097456, -0.062994, -0.023072, 0.289162",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024480, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173706, -0.107618, -0.049712, -0.007684, 0.212495",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[34]_hldr*/
+
+} /* end of pin tl_o[34] */
+
+pin("tl_o[33]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002863 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[33];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\
+ "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\
+ "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\
+ "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\
+ "0.582638, 0.792504, 0.967419, 1.287178, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.027190, 0.303040, 0.635504, 1.251191, 2.482564",\
+ "0.031386, 0.304046, 0.637439, 1.251191, 2.482564",\
+ "0.043994, 0.306272, 0.637475, 1.251191, 2.482564",\
+ "0.055941, 0.309507, 0.637579, 1.251191, 2.482564",\
+ "0.132198, 0.347439, 0.643822, 1.253731, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\
+ "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\
+ "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\
+ "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\
+ "0.589089, 0.702533, 0.813636, 1.016588, 1.422492");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.026653, 0.189312, 0.389207, 0.760903, 1.504295",\
+ "0.026653, 0.189463, 0.389709, 0.760903, 1.504295",\
+ "0.027645, 0.189463, 0.389709, 0.760903, 1.504295",\
+ "0.029626, 0.189463, 0.389709, 0.760903, 1.504295",\
+ "0.047836, 0.193360, 0.389709, 0.760903, 1.504575");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[33]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\
+ "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\
+ "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\
+ "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\
+ "0.582638, 0.792504, 0.967419, 1.287178, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.027190, 0.303040, 0.635504, 1.249953, 2.473548",\
+ "0.031386, 0.304046, 0.637439, 1.249953, 2.473548",\
+ "0.043994, 0.306272, 0.637475, 1.250028, 2.473548",\
+ "0.055941, 0.309507, 0.637579, 1.250774, 2.473548",\
+ "0.132198, 0.347439, 0.643822, 1.253731, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\
+ "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\
+ "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\
+ "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\
+ "0.589089, 0.702533, 0.813636, 1.016588, 1.422492");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\
+ "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\
+ "0.027645, 0.188505, 0.387697, 0.758671, 1.500618",\
+ "0.029626, 0.189113, 0.388156, 0.759574, 1.502409",\
+ "0.047836, 0.193360, 0.388231, 0.760346, 1.504575");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[33]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.213409, 0.167538, 0.137343, 0.126003, 0.139708",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266639, 0.191328, 0.123224, 0.100346, 0.164070",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[33]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.141198, -0.098770, -0.064309, -0.024387, 0.287847",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174512, -0.108425, -0.050519, -0.008491, 0.211689",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[33]_hldr*/
+
+} /* end of pin tl_o[33] */
+
+pin("tl_o[32]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003362 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[32];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\
+ "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\
+ "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\
+ "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\
+ "0.586756, 0.793514, 0.968169, 1.287678, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.029003, 0.304950, 0.636948, 1.252153, 2.482563",\
+ "0.033010, 0.305967, 0.638875, 1.252153, 2.482563",\
+ "0.045419, 0.308176, 0.638911, 1.252153, 2.482563",\
+ "0.057391, 0.311385, 0.639017, 1.252153, 2.482563",\
+ "0.134015, 0.349072, 0.645253, 1.254684, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\
+ "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\
+ "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\
+ "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\
+ "0.590856, 0.703163, 0.814100, 1.016894, 1.422481");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.027892, 0.190438, 0.390058, 0.761463, 1.504274",\
+ "0.027892, 0.190592, 0.390558, 0.761463, 1.504274",\
+ "0.028831, 0.190592, 0.390558, 0.761463, 1.504274",\
+ "0.030758, 0.190592, 0.390558, 0.761463, 1.504274",\
+ "0.048732, 0.194447, 0.390558, 0.761463, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[32]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\
+ "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\
+ "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\
+ "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\
+ "0.586756, 0.793514, 0.968169, 1.287678, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.029003, 0.304950, 0.636948, 1.250910, 2.473548",\
+ "0.033010, 0.305967, 0.638875, 1.250910, 2.473548",\
+ "0.045419, 0.308176, 0.638911, 1.250986, 2.473548",\
+ "0.057391, 0.311385, 0.639017, 1.251733, 2.473548",\
+ "0.134015, 0.349072, 0.645253, 1.254684, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\
+ "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\
+ "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\
+ "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\
+ "0.590856, 0.703163, 0.814100, 1.016894, 1.422481");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\
+ "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\
+ "0.028831, 0.189626, 0.388546, 0.759230, 1.500597",\
+ "0.030758, 0.190232, 0.389006, 0.760134, 1.502388",\
+ "0.048732, 0.194447, 0.389083, 0.760906, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[32]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.214175, 0.168305, 0.138110, 0.126769, 0.140474",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.267102, 0.191791, 0.123687, 0.100809, 0.164534",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[32]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.141956, -0.099528, -0.065067, -0.025145, 0.287089",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174973, -0.108885, -0.050979, -0.008951, 0.211228",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[32]_hldr*/
+
+} /* end of pin tl_o[32] */
+
+pin("tl_o[31]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002343 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[31];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\
+ "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\
+ "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\
+ "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\
+ "0.578356, 0.791455, 0.966639, 1.286659, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.025304, 0.301054, 0.634003, 1.250190, 2.482563",\
+ "0.029697, 0.302049, 0.635945, 1.250190, 2.482563",\
+ "0.042512, 0.304293, 0.635981, 1.250190, 2.482563",\
+ "0.054434, 0.307555, 0.636084, 1.250190, 2.482563",\
+ "0.130308, 0.345742, 0.642335, 1.252740, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\
+ "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\
+ "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\
+ "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\
+ "0.587289, 0.701891, 0.813166, 1.016283, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.025390, 0.188165, 0.388347, 0.760345, 1.504341",\
+ "0.025390, 0.188312, 0.388850, 0.760345, 1.504341",\
+ "0.026437, 0.188312, 0.388850, 0.760345, 1.504341",\
+ "0.028472, 0.188312, 0.388850, 0.760345, 1.504341",\
+ "0.046924, 0.192253, 0.388850, 0.760345, 1.504621");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[31]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\
+ "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\
+ "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\
+ "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\
+ "0.578356, 0.791455, 0.966639, 1.286659, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.025304, 0.301054, 0.634003, 1.248957, 2.473548",\
+ "0.029697, 0.302049, 0.635945, 1.248957, 2.473548",\
+ "0.042512, 0.304293, 0.635981, 1.249033, 2.473548",\
+ "0.054434, 0.307555, 0.636084, 1.249777, 2.473548",\
+ "0.130308, 0.345742, 0.642335, 1.252740, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\
+ "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\
+ "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\
+ "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\
+ "0.587289, 0.701891, 0.813166, 1.016283, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\
+ "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\
+ "0.026437, 0.187363, 0.386838, 0.758113, 1.500664",\
+ "0.028472, 0.187972, 0.387296, 0.759016, 1.502455",\
+ "0.046924, 0.192253, 0.387369, 0.759786, 1.504621");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[31]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212613, 0.166742, 0.136547, 0.125206, 0.138911",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266167, 0.190856, 0.122752, 0.099874, 0.163599",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[31]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140410, -0.097982, -0.063521, -0.023599, 0.288635",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174043, -0.107956, -0.050050, -0.008022, 0.212157",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[31]_hldr*/
+
+} /* end of pin tl_o[31] */
+
+pin("tl_o[30]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003362 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[30];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\
+ "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\
+ "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\
+ "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\
+ "0.586756, 0.793514, 0.968169, 1.287678, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.029003, 0.304950, 0.636948, 1.252153, 2.482563",\
+ "0.033010, 0.305967, 0.638875, 1.252153, 2.482563",\
+ "0.045419, 0.308176, 0.638911, 1.252153, 2.482563",\
+ "0.057391, 0.311385, 0.639017, 1.252153, 2.482563",\
+ "0.134015, 0.349072, 0.645253, 1.254684, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\
+ "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\
+ "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\
+ "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\
+ "0.590856, 0.703163, 0.814100, 1.016894, 1.422481");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.027892, 0.190438, 0.390058, 0.761463, 1.504274",\
+ "0.027892, 0.190592, 0.390558, 0.761463, 1.504274",\
+ "0.028831, 0.190592, 0.390558, 0.761463, 1.504274",\
+ "0.030758, 0.190592, 0.390558, 0.761463, 1.504274",\
+ "0.048732, 0.194447, 0.390558, 0.761463, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[30]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\
+ "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\
+ "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\
+ "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\
+ "0.586756, 0.793514, 0.968169, 1.287678, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.029003, 0.304950, 0.636948, 1.250910, 2.473548",\
+ "0.033010, 0.305967, 0.638875, 1.250910, 2.473548",\
+ "0.045419, 0.308176, 0.638911, 1.250986, 2.473548",\
+ "0.057391, 0.311385, 0.639017, 1.251733, 2.473548",\
+ "0.134015, 0.349072, 0.645253, 1.254684, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\
+ "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\
+ "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\
+ "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\
+ "0.590856, 0.703163, 0.814100, 1.016894, 1.422481");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\
+ "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\
+ "0.028831, 0.189626, 0.388546, 0.759230, 1.500597",\
+ "0.030758, 0.190232, 0.389006, 0.760134, 1.502388",\
+ "0.048732, 0.194447, 0.389083, 0.760906, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[30]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.214175, 0.168305, 0.138110, 0.126769, 0.140474",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.267102, 0.191791, 0.123687, 0.100809, 0.164534",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[30]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.141956, -0.099528, -0.065067, -0.025145, 0.287089",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174973, -0.108885, -0.050979, -0.008951, 0.211228",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[30]_hldr*/
+
+} /* end of pin tl_o[30] */
+
+pin("tl_o[29]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002863 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[29];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\
+ "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\
+ "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\
+ "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\
+ "0.582638, 0.792504, 0.967419, 1.287178, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.027190, 0.303040, 0.635504, 1.251191, 2.482564",\
+ "0.031386, 0.304046, 0.637439, 1.251191, 2.482564",\
+ "0.043994, 0.306272, 0.637475, 1.251191, 2.482564",\
+ "0.055941, 0.309507, 0.637579, 1.251191, 2.482564",\
+ "0.132198, 0.347439, 0.643822, 1.253731, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\
+ "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\
+ "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\
+ "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\
+ "0.589089, 0.702533, 0.813636, 1.016588, 1.422492");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.026653, 0.189312, 0.389207, 0.760903, 1.504295",\
+ "0.026653, 0.189463, 0.389709, 0.760903, 1.504295",\
+ "0.027645, 0.189463, 0.389709, 0.760903, 1.504295",\
+ "0.029626, 0.189463, 0.389709, 0.760903, 1.504295",\
+ "0.047836, 0.193360, 0.389709, 0.760903, 1.504575");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[29]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\
+ "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\
+ "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\
+ "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\
+ "0.582638, 0.792504, 0.967419, 1.287178, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.027190, 0.303040, 0.635504, 1.249953, 2.473548",\
+ "0.031386, 0.304046, 0.637439, 1.249953, 2.473548",\
+ "0.043994, 0.306272, 0.637475, 1.250028, 2.473548",\
+ "0.055941, 0.309507, 0.637579, 1.250774, 2.473548",\
+ "0.132198, 0.347439, 0.643822, 1.253731, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\
+ "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\
+ "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\
+ "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\
+ "0.589089, 0.702533, 0.813636, 1.016588, 1.422492");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\
+ "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\
+ "0.027645, 0.188505, 0.387697, 0.758671, 1.500618",\
+ "0.029626, 0.189113, 0.388156, 0.759574, 1.502409",\
+ "0.047836, 0.193360, 0.388231, 0.760346, 1.504575");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[29]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.213409, 0.167538, 0.137343, 0.126003, 0.139708",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266639, 0.191328, 0.123224, 0.100346, 0.164070",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[29]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.141198, -0.098770, -0.064309, -0.024387, 0.287847",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174512, -0.108425, -0.050519, -0.008491, 0.211689",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[29]_hldr*/
+
+} /* end of pin tl_o[29] */
+
+pin("tl_o[28]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001816 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[28];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\
+ "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\
+ "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\
+ "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\
+ "0.574010, 0.790389, 0.965848, 1.286131, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.023390, 0.299039, 0.632479, 1.249174, 2.482563",\
+ "0.027983, 0.300023, 0.634430, 1.249174, 2.482563",\
+ "0.041008, 0.302285, 0.634466, 1.249174, 2.482563",\
+ "0.052904, 0.305573, 0.634567, 1.249174, 2.482563",\
+ "0.128390, 0.344019, 0.640826, 1.251733, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\
+ "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\
+ "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\
+ "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\
+ "0.585433, 0.701229, 0.812678, 1.015963, 1.422532");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.024087, 0.186982, 0.387454, 0.759758, 1.504368",\
+ "0.024087, 0.187126, 0.387958, 0.759758, 1.504368",\
+ "0.025192, 0.187126, 0.387958, 0.759758, 1.504368",\
+ "0.027281, 0.187126, 0.387958, 0.759758, 1.504368",\
+ "0.045983, 0.191111, 0.387958, 0.759758, 1.504648");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[28]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\
+ "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\
+ "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\
+ "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\
+ "0.574010, 0.790389, 0.965848, 1.286131, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.023390, 0.299039, 0.632479, 1.247947, 2.473548",\
+ "0.027983, 0.300023, 0.634430, 1.247947, 2.473548",\
+ "0.041008, 0.302285, 0.634466, 1.248022, 2.473548",\
+ "0.052904, 0.305573, 0.634567, 1.248766, 2.473548",\
+ "0.128390, 0.344019, 0.640826, 1.251733, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\
+ "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\
+ "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\
+ "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\
+ "0.585433, 0.701229, 0.812678, 1.015963, 1.422532");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\
+ "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\
+ "0.025192, 0.186184, 0.385947, 0.757528, 1.500690",\
+ "0.027281, 0.186796, 0.386404, 0.758430, 1.502482",\
+ "0.045983, 0.191111, 0.386476, 0.759200, 1.504648");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[28]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.211804, 0.165933, 0.135738, 0.124398, 0.138103",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.265681, 0.190370, 0.122265, 0.099388, 0.163112",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[28]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.139610, -0.097182, -0.062721, -0.022799, 0.289435",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173560, -0.107472, -0.049566, -0.007539, 0.212641",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[28]_hldr*/
+
+} /* end of pin tl_o[28] */
+
+pin("tl_o[27]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003525 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[27];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.052275, 0.204267, 0.378871, 0.700862, 1.344843",\
+ "0.138817, 0.291442, 0.465974, 0.787575, 1.430777",\
+ "0.223030, 0.379567, 0.553927, 0.875195, 1.517732",\
+ "0.281960, 0.443955, 0.618041, 0.939108, 1.581241",\
+ "0.588098, 0.793843, 0.968413, 1.287841, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.029595, 0.305572, 0.637418, 1.252467, 2.482563",\
+ "0.033540, 0.306593, 0.639343, 1.252467, 2.482563",\
+ "0.045883, 0.308796, 0.639379, 1.252467, 2.482563",\
+ "0.057864, 0.311997, 0.639486, 1.252467, 2.482563",\
+ "0.134607, 0.349604, 0.645719, 1.254995, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.071419, 0.174817, 0.285764, 0.489395, 0.896657",\
+ "0.158819, 0.262134, 0.373045, 0.576700, 0.984010",\
+ "0.239235, 0.342461, 0.453072, 0.656729, 1.064042",\
+ "0.296074, 0.400011, 0.510613, 0.713972, 1.120690",\
+ "0.591402, 0.703358, 0.814241, 1.016983, 1.422467");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.028276, 0.190786, 0.390316, 0.761627, 1.504248",\
+ "0.028276, 0.190941, 0.390816, 0.761627, 1.504248",\
+ "0.029198, 0.190941, 0.390816, 0.761627, 1.504248",\
+ "0.031109, 0.190941, 0.390816, 0.761627, 1.504248",\
+ "0.049009, 0.194783, 0.390816, 0.761627, 1.504528");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[27]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.052275, 0.204267, 0.378871, 0.700862, 1.344843",\
+ "0.138817, 0.291442, 0.465974, 0.787575, 1.430777",\
+ "0.223030, 0.379567, 0.553927, 0.875195, 1.517732",\
+ "0.281960, 0.443955, 0.618041, 0.939108, 1.581241",\
+ "0.588098, 0.793843, 0.968413, 1.287841, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.029595, 0.305572, 0.637418, 1.251222, 2.473548",\
+ "0.033540, 0.306593, 0.639343, 1.251222, 2.473548",\
+ "0.045883, 0.308796, 0.639379, 1.251298, 2.473548",\
+ "0.057864, 0.311997, 0.639486, 1.252045, 2.473548",\
+ "0.134607, 0.349604, 0.645719, 1.254995, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.071419, 0.174817, 0.285764, 0.489395, 0.896657",\
+ "0.158819, 0.262134, 0.373045, 0.576700, 0.984010",\
+ "0.239235, 0.342461, 0.453072, 0.656729, 1.064042",\
+ "0.296074, 0.400011, 0.510613, 0.713972, 1.120690",\
+ "0.591402, 0.703358, 0.814241, 1.016983, 1.422467");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.028276, 0.189973, 0.388804, 0.759393, 1.500571",\
+ "0.028276, 0.189973, 0.388804, 0.759393, 1.500571",\
+ "0.029198, 0.189973, 0.388804, 0.759393, 1.500571",\
+ "0.031109, 0.190579, 0.389264, 0.760297, 1.502363",\
+ "0.049009, 0.194783, 0.389341, 0.761070, 1.504528");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[27]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029595, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.214425, 0.168554, 0.138359, 0.127019, 0.140724",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028276, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.267246, 0.191934, 0.123830, 0.100952, 0.164677",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[27]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029595, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.142204, -0.099775, -0.065314, -0.025392, 0.286842",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028276, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.175115, -0.109028, -0.051122, -0.009094, 0.211086",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[27]_hldr*/
+
+} /* end of pin tl_o[27] */
+
+pin("tl_o[26]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002267 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[26];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.048874, 0.201733, 0.376968, 0.699593, 1.344843",\
+ "0.135228, 0.288908, 0.464073, 0.786308, 1.430777",\
+ "0.218603, 0.377035, 0.552028, 0.873930, 1.517732",\
+ "0.276689, 0.441428, 0.616144, 0.937843, 1.581241",\
+ "0.577730, 0.791301, 0.966525, 1.286583, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.025028, 0.300764, 0.633784, 1.250043, 2.482563",\
+ "0.029450, 0.301758, 0.635727, 1.250043, 2.482563",\
+ "0.042296, 0.304004, 0.635763, 1.250043, 2.482563",\
+ "0.054214, 0.307269, 0.635866, 1.250043, 2.482563",\
+ "0.130032, 0.345494, 0.642118, 1.252595, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.068432, 0.173252, 0.284609, 0.488641, 0.896705",\
+ "0.155842, 0.260570, 0.371890, 0.575946, 0.984059",\
+ "0.236211, 0.340904, 0.451917, 0.655975, 1.064090",\
+ "0.292930, 0.398452, 0.509460, 0.713219, 1.120738",\
+ "0.587011, 0.701792, 0.813092, 1.016233, 1.422515");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.025195, 0.187988, 0.388211, 0.760253, 1.504337",\
+ "0.025195, 0.188134, 0.388714, 0.760253, 1.504337",\
+ "0.026251, 0.188134, 0.388714, 0.760253, 1.504337",\
+ "0.028293, 0.188134, 0.388714, 0.760253, 1.504337",\
+ "0.046783, 0.192082, 0.388714, 0.760253, 1.504617");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[26]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.048874, 0.201733, 0.376968, 0.699593, 1.344843",\
+ "0.135228, 0.288908, 0.464073, 0.786308, 1.430777",\
+ "0.218603, 0.377035, 0.552028, 0.873930, 1.517732",\
+ "0.276689, 0.441428, 0.616144, 0.937843, 1.581241",\
+ "0.577730, 0.791301, 0.966525, 1.286583, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.025028, 0.300764, 0.633784, 1.248812, 2.473548",\
+ "0.029450, 0.301758, 0.635727, 1.248812, 2.473548",\
+ "0.042296, 0.304004, 0.635763, 1.248887, 2.473548",\
+ "0.054214, 0.307269, 0.635866, 1.249632, 2.473548",\
+ "0.130032, 0.345494, 0.642118, 1.252595, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.068432, 0.173252, 0.284609, 0.488641, 0.896705",\
+ "0.155842, 0.260570, 0.371890, 0.575946, 0.984059",\
+ "0.236211, 0.340904, 0.451917, 0.655975, 1.064090",\
+ "0.292930, 0.398452, 0.509460, 0.713219, 1.120738",\
+ "0.587011, 0.701792, 0.813092, 1.016233, 1.422515");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.025195, 0.187186, 0.386703, 0.758022, 1.500660",\
+ "0.025195, 0.187186, 0.386703, 0.758022, 1.500660",\
+ "0.026251, 0.187186, 0.386703, 0.758022, 1.500660",\
+ "0.028293, 0.187796, 0.387161, 0.758924, 1.502451",\
+ "0.046783, 0.192082, 0.387233, 0.759695, 1.504617");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[26]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025028, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212496, 0.166625, 0.136430, 0.125090, 0.138795",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025195, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266095, 0.190783, 0.122679, 0.099801, 0.163526",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[26]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025028, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140295, -0.097867, -0.063406, -0.023484, 0.288750",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025195, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173971, -0.107884, -0.049978, -0.007950, 0.212230",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[26]_hldr*/
+
+} /* end of pin tl_o[26] */
+
+pin("tl_o[25]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002846 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[25];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.050438, 0.202899, 0.377843, 0.700177, 1.344843",\
+ "0.136878, 0.290073, 0.464947, 0.786890, 1.430777",\
+ "0.220639, 0.378199, 0.552901, 0.874512, 1.517732",\
+ "0.279113, 0.442591, 0.617016, 0.938424, 1.581241",\
+ "0.582498, 0.792470, 0.967394, 1.287161, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.027128, 0.302975, 0.635455, 1.251158, 2.482563",\
+ "0.031331, 0.303981, 0.637390, 1.251158, 2.482563",\
+ "0.043946, 0.306208, 0.637426, 1.251158, 2.482563",\
+ "0.055892, 0.309444, 0.637531, 1.251158, 2.482563",\
+ "0.132136, 0.347384, 0.643774, 1.253699, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.069801, 0.173969, 0.285138, 0.488985, 0.896680",\
+ "0.157206, 0.261287, 0.372419, 0.576290, 0.984034",\
+ "0.237596, 0.341617, 0.452445, 0.656319, 1.064065",\
+ "0.294370, 0.399166, 0.509987, 0.713563, 1.120713",\
+ "0.589023, 0.702509, 0.813617, 1.016575, 1.422490");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.026606, 0.189270, 0.389174, 0.760880, 1.504292",\
+ "0.026606, 0.189420, 0.389676, 0.760880, 1.504292",\
+ "0.027601, 0.189420, 0.389676, 0.760880, 1.504292",\
+ "0.029583, 0.189420, 0.389676, 0.760880, 1.504292",\
+ "0.047803, 0.193320, 0.389676, 0.760880, 1.504571");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[25]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.050438, 0.202899, 0.377843, 0.700177, 1.344843",\
+ "0.136878, 0.290073, 0.464947, 0.786890, 1.430777",\
+ "0.220639, 0.378199, 0.552901, 0.874512, 1.517732",\
+ "0.279113, 0.442591, 0.617016, 0.938424, 1.581241",\
+ "0.582498, 0.792470, 0.967394, 1.287161, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.027128, 0.302975, 0.635455, 1.249921, 2.473548",\
+ "0.031331, 0.303981, 0.637390, 1.249921, 2.473548",\
+ "0.043946, 0.306208, 0.637426, 1.249996, 2.473548",\
+ "0.055892, 0.309444, 0.637531, 1.250742, 2.473548",\
+ "0.132136, 0.347384, 0.643774, 1.253699, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.069801, 0.173969, 0.285138, 0.488985, 0.896680",\
+ "0.157206, 0.261287, 0.372419, 0.576290, 0.984034",\
+ "0.237596, 0.341617, 0.452445, 0.656319, 1.064065",\
+ "0.294370, 0.399166, 0.509987, 0.713563, 1.120713",\
+ "0.589023, 0.702509, 0.813617, 1.016575, 1.422490");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.026606, 0.188463, 0.387664, 0.758648, 1.500614",\
+ "0.026606, 0.188463, 0.387664, 0.758648, 1.500614",\
+ "0.027601, 0.188463, 0.387664, 0.758648, 1.500614",\
+ "0.029583, 0.189071, 0.388123, 0.759551, 1.502406",\
+ "0.047803, 0.193320, 0.388198, 0.760322, 1.504571");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[25]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027128, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.213383, 0.167512, 0.137317, 0.125977, 0.139682",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266622, 0.191311, 0.123207, 0.100329, 0.164053",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[25]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027128, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.141173, -0.098745, -0.064283, -0.024362, 0.287872",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174495, -0.108408, -0.050502, -0.008474, 0.211706",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[25]_hldr*/
+
+} /* end of pin tl_o[25] */
+
+pin("tl_o[24]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003210 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[24];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.051424, 0.203633, 0.378395, 0.700544, 1.344843",\
+ "0.137919, 0.290808, 0.465498, 0.787258, 1.430777",\
+ "0.221922, 0.378933, 0.553452, 0.874879, 1.517732",\
+ "0.280641, 0.443323, 0.617566, 0.938791, 1.581241",\
+ "0.585504, 0.793207, 0.967941, 1.287526, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.028452, 0.304369, 0.636509, 1.251860, 2.482563",\
+ "0.032517, 0.305383, 0.638438, 1.251860, 2.482563",\
+ "0.044986, 0.307597, 0.638475, 1.251860, 2.482563",\
+ "0.056951, 0.310815, 0.638580, 1.251860, 2.482563",\
+ "0.133463, 0.348576, 0.644818, 1.254395, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.070659, 0.174419, 0.285469, 0.489200, 0.896663",\
+ "0.158062, 0.261736, 0.372750, 0.576505, 0.984016",\
+ "0.238466, 0.342065, 0.452777, 0.656534, 1.064048",\
+ "0.295275, 0.399615, 0.510318, 0.713777, 1.120695",\
+ "0.590286, 0.702959, 0.813947, 1.016789, 1.422472");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.027492, 0.190075, 0.389778, 0.761272, 1.504259",\
+ "0.027492, 0.190228, 0.390279, 0.761272, 1.504259",\
+ "0.028448, 0.190228, 0.390279, 0.761272, 1.504259",\
+ "0.030393, 0.190228, 0.390279, 0.761272, 1.504259",\
+ "0.048443, 0.194096, 0.390279, 0.761272, 1.504539");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[24]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.051424, 0.203633, 0.378395, 0.700544, 1.344843",\
+ "0.137919, 0.290808, 0.465498, 0.787258, 1.430777",\
+ "0.221922, 0.378933, 0.553452, 0.874879, 1.517732",\
+ "0.280641, 0.443323, 0.617566, 0.938791, 1.581241",\
+ "0.585504, 0.793207, 0.967941, 1.287526, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.028452, 0.304369, 0.636509, 1.250620, 2.473548",\
+ "0.032517, 0.305383, 0.638438, 1.250620, 2.473548",\
+ "0.044986, 0.307597, 0.638475, 1.250695, 2.473548",\
+ "0.056951, 0.310815, 0.638580, 1.251441, 2.473548",\
+ "0.133463, 0.348576, 0.644818, 1.254395, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.070659, 0.174419, 0.285469, 0.489200, 0.896663",\
+ "0.158062, 0.261736, 0.372750, 0.576505, 0.984016",\
+ "0.238466, 0.342065, 0.452777, 0.656534, 1.064048",\
+ "0.295275, 0.399615, 0.510318, 0.713777, 1.120695",\
+ "0.590286, 0.702959, 0.813947, 1.016789, 1.422472");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.027492, 0.189265, 0.388267, 0.759039, 1.500582",\
+ "0.027492, 0.189265, 0.388267, 0.759039, 1.500582",\
+ "0.028448, 0.189265, 0.388267, 0.759039, 1.500582",\
+ "0.030393, 0.189871, 0.388727, 0.759942, 1.502373",\
+ "0.048443, 0.194096, 0.388802, 0.760715, 1.504539");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[24]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028452, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.213943, 0.168072, 0.137877, 0.126536, 0.140241",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027492, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266953, 0.191642, 0.123538, 0.100660, 0.164384",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[24]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028452, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.141726, -0.099298, -0.064837, -0.024915, 0.287319",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027492, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174824, -0.108737, -0.050831, -0.008803, 0.211377",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[24]_hldr*/
+
+} /* end of pin tl_o[24] */
+
+pin("tl_o[23]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002308 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[23];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.048983, 0.201815, 0.377030, 0.699634, 1.344843",\
+ "0.135344, 0.288990, 0.464134, 0.786349, 1.430777",\
+ "0.218746, 0.377117, 0.552089, 0.873970, 1.517732",\
+ "0.276859, 0.441510, 0.616205, 0.937884, 1.581241",\
+ "0.578065, 0.791383, 0.966586, 1.286623, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.025176, 0.300919, 0.633901, 1.250122, 2.482564",\
+ "0.029582, 0.301914, 0.635844, 1.250122, 2.482564",\
+ "0.042411, 0.304159, 0.635880, 1.250122, 2.482564",\
+ "0.054332, 0.307422, 0.635983, 1.250122, 2.482564",\
+ "0.130180, 0.345627, 0.642234, 1.252672, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.068536, 0.173307, 0.284651, 0.488670, 0.896708",\
+ "0.155945, 0.260625, 0.371931, 0.575975, 0.984061",\
+ "0.236316, 0.340958, 0.451958, 0.656003, 1.064093",\
+ "0.293039, 0.398507, 0.509501, 0.713248, 1.120741",\
+ "0.587164, 0.701846, 0.813133, 1.016261, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.025302, 0.188085, 0.388286, 0.760305, 1.504342",\
+ "0.025302, 0.188232, 0.388789, 0.760305, 1.504342",\
+ "0.026353, 0.188232, 0.388789, 0.760305, 1.504342",\
+ "0.028391, 0.188232, 0.388789, 0.760305, 1.504342",\
+ "0.046861, 0.192176, 0.388789, 0.760305, 1.504622");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[23]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.048983, 0.201815, 0.377030, 0.699634, 1.344843",\
+ "0.135344, 0.288990, 0.464134, 0.786349, 1.430777",\
+ "0.218746, 0.377117, 0.552089, 0.873970, 1.517732",\
+ "0.276859, 0.441510, 0.616205, 0.937884, 1.581241",\
+ "0.578065, 0.791383, 0.966586, 1.286623, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.025176, 0.300919, 0.633901, 1.248890, 2.473548",\
+ "0.029582, 0.301914, 0.635844, 1.248890, 2.473548",\
+ "0.042411, 0.304159, 0.635880, 1.248965, 2.473548",\
+ "0.054332, 0.307422, 0.635983, 1.249710, 2.473548",\
+ "0.130180, 0.345627, 0.642234, 1.252672, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.068536, 0.173307, 0.284651, 0.488670, 0.896708",\
+ "0.155945, 0.260625, 0.371931, 0.575975, 0.984061",\
+ "0.236316, 0.340958, 0.451958, 0.656003, 1.064093",\
+ "0.293039, 0.398507, 0.509501, 0.713248, 1.120741",\
+ "0.587164, 0.701846, 0.813133, 1.016261, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.025302, 0.187283, 0.386778, 0.758074, 1.500664",\
+ "0.025302, 0.187283, 0.386778, 0.758074, 1.500664",\
+ "0.026353, 0.187283, 0.386778, 0.758074, 1.500664",\
+ "0.028391, 0.187893, 0.387236, 0.758976, 1.502456",\
+ "0.046861, 0.192176, 0.387309, 0.759746, 1.504622");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[23]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025176, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212558, 0.166688, 0.136493, 0.125152, 0.138857",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025302, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266135, 0.190823, 0.122719, 0.099841, 0.163566",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[23]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025176, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140357, -0.097929, -0.063467, -0.023545, 0.288689",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025302, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174011, -0.107923, -0.050017, -0.007990, 0.212190",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[23]_hldr*/
+
+} /* end of pin tl_o[23] */
+
+pin("tl_o[22]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002254 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[22];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\
+ "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\
+ "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\
+ "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\
+ "0.577621, 0.791275, 0.966506, 1.286569, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.024980, 0.300714, 0.633745, 1.250018, 2.482564",\
+ "0.029407, 0.301707, 0.635689, 1.250018, 2.482564",\
+ "0.042258, 0.303954, 0.635725, 1.250018, 2.482564",\
+ "0.054175, 0.307220, 0.635828, 1.250018, 2.482564",\
+ "0.129984, 0.345451, 0.642080, 1.252569, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\
+ "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\
+ "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\
+ "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\
+ "0.586970, 0.701777, 0.813081, 1.016227, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.025166, 0.187961, 0.388192, 0.760242, 1.504342",\
+ "0.025166, 0.188108, 0.388695, 0.760242, 1.504342",\
+ "0.026223, 0.188108, 0.388695, 0.760242, 1.504342",\
+ "0.028267, 0.188108, 0.388695, 0.760242, 1.504342",\
+ "0.046762, 0.192057, 0.388695, 0.760242, 1.504622");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[22]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\
+ "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\
+ "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\
+ "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\
+ "0.577621, 0.791275, 0.966506, 1.286569, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.024980, 0.300714, 0.633745, 1.248787, 2.473548",\
+ "0.029407, 0.301707, 0.635689, 1.248787, 2.473548",\
+ "0.042258, 0.303954, 0.635725, 1.248862, 2.473548",\
+ "0.054175, 0.307220, 0.635828, 1.249606, 2.473548",\
+ "0.129984, 0.345451, 0.642080, 1.252569, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\
+ "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\
+ "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\
+ "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\
+ "0.586970, 0.701777, 0.813081, 1.016227, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\
+ "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\
+ "0.026223, 0.187160, 0.386684, 0.758011, 1.500664",\
+ "0.028267, 0.187770, 0.387142, 0.758913, 1.502456",\
+ "0.046762, 0.192057, 0.387215, 0.759684, 1.504622");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[22]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212476, 0.166605, 0.136410, 0.125070, 0.138775",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266084, 0.190773, 0.122668, 0.099790, 0.163515",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[22]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140275, -0.097847, -0.063386, -0.023464, 0.288770",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173960, -0.107873, -0.049967, -0.007939, 0.212241",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[22]_hldr*/
+
+} /* end of pin tl_o[22] */
+
+pin("tl_o[21]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003224 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[21];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.051460, 0.203660, 0.378415, 0.700558, 1.344843",\
+ "0.137957, 0.290835, 0.465518, 0.787271, 1.430777",\
+ "0.221969, 0.378960, 0.553472, 0.874892, 1.517732",\
+ "0.280696, 0.443350, 0.617586, 0.938804, 1.581241",\
+ "0.585613, 0.793234, 0.967961, 1.287539, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.028500, 0.304420, 0.636547, 1.251886, 2.482563",\
+ "0.032560, 0.305434, 0.638476, 1.251886, 2.482563",\
+ "0.045023, 0.307647, 0.638513, 1.251886, 2.482563",\
+ "0.056989, 0.310864, 0.638618, 1.251886, 2.482563",\
+ "0.133511, 0.348619, 0.644856, 1.254420, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.070687, 0.174433, 0.285479, 0.489206, 0.896660",\
+ "0.158090, 0.261751, 0.372760, 0.576511, 0.984014",\
+ "0.238494, 0.342080, 0.452787, 0.656540, 1.064045",\
+ "0.295304, 0.399629, 0.510328, 0.713783, 1.120693",\
+ "0.590327, 0.702974, 0.813957, 1.016795, 1.422470");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.027521, 0.190101, 0.389797, 0.761283, 1.504255",\
+ "0.027521, 0.190254, 0.390298, 0.761283, 1.504255",\
+ "0.028476, 0.190254, 0.390298, 0.761283, 1.504255",\
+ "0.030419, 0.190254, 0.390298, 0.761283, 1.504255",\
+ "0.048464, 0.194122, 0.390298, 0.761283, 1.504535");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[21]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.051460, 0.203660, 0.378415, 0.700558, 1.344843",\
+ "0.137957, 0.290835, 0.465518, 0.787271, 1.430777",\
+ "0.221969, 0.378960, 0.553472, 0.874892, 1.517732",\
+ "0.280696, 0.443350, 0.617586, 0.938804, 1.581241",\
+ "0.585613, 0.793234, 0.967961, 1.287539, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.028500, 0.304420, 0.636547, 1.250645, 2.473547",\
+ "0.032560, 0.305434, 0.638476, 1.250645, 2.473547",\
+ "0.045023, 0.307647, 0.638513, 1.250720, 2.473547",\
+ "0.056989, 0.310864, 0.638618, 1.251467, 2.473547",\
+ "0.133511, 0.348619, 0.644856, 1.254420, 2.473547");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.070687, 0.174433, 0.285479, 0.489206, 0.896660",\
+ "0.158090, 0.261751, 0.372760, 0.576511, 0.984014",\
+ "0.238494, 0.342080, 0.452787, 0.656540, 1.064045",\
+ "0.295304, 0.399629, 0.510328, 0.713783, 1.120693",\
+ "0.590327, 0.702974, 0.813957, 1.016795, 1.422470");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.027521, 0.189291, 0.388286, 0.759050, 1.500578",\
+ "0.027521, 0.189291, 0.388286, 0.759050, 1.500578",\
+ "0.028476, 0.189291, 0.388286, 0.759050, 1.500578",\
+ "0.030419, 0.189897, 0.388745, 0.759953, 1.502369",\
+ "0.048464, 0.194122, 0.388821, 0.760726, 1.504535");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[21]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028500, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.213963, 0.168092, 0.137897, 0.126557, 0.140261",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027521, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266964, 0.191653, 0.123548, 0.100670, 0.164395",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[21]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028500, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.141746, -0.099318, -0.064857, -0.024935, 0.287299",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027521, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174835, -0.108748, -0.050842, -0.008814, 0.211366",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[21]_hldr*/
+
+} /* end of pin tl_o[21] */
+
+pin("tl_o[20]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001805 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[20];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\
+ "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\
+ "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\
+ "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\
+ "0.573921, 0.790368, 0.965832, 1.286120, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.023351, 0.298998, 0.632448, 1.249153, 2.482563",\
+ "0.027948, 0.299981, 0.634399, 1.249153, 2.482563",\
+ "0.040978, 0.302244, 0.634435, 1.249153, 2.482563",\
+ "0.052873, 0.305533, 0.634536, 1.249153, 2.482563",\
+ "0.128351, 0.343984, 0.640795, 1.251713, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\
+ "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\
+ "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\
+ "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\
+ "0.585410, 0.701221, 0.812673, 1.015961, 1.422537");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.024071, 0.186967, 0.387445, 0.759756, 1.504378",\
+ "0.024071, 0.187111, 0.387949, 0.759756, 1.504378",\
+ "0.025176, 0.187111, 0.387949, 0.759756, 1.504378",\
+ "0.027266, 0.187111, 0.387949, 0.759756, 1.504378",\
+ "0.045971, 0.191097, 0.387949, 0.759756, 1.504658");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[20]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\
+ "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\
+ "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\
+ "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\
+ "0.573921, 0.790368, 0.965832, 1.286120, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.023351, 0.298998, 0.632448, 1.247926, 2.473548",\
+ "0.027948, 0.299981, 0.634399, 1.247926, 2.473548",\
+ "0.040978, 0.302244, 0.634435, 1.248002, 2.473548",\
+ "0.052873, 0.305533, 0.634536, 1.248745, 2.473548",\
+ "0.128351, 0.343984, 0.640795, 1.251713, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\
+ "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\
+ "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\
+ "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\
+ "0.585410, 0.701221, 0.812673, 1.015961, 1.422537");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\
+ "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\
+ "0.025176, 0.186169, 0.385939, 0.757526, 1.500700",\
+ "0.027266, 0.186781, 0.386395, 0.758427, 1.502492",\
+ "0.045971, 0.191097, 0.386467, 0.759197, 1.504658");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[20]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.211788, 0.165917, 0.135722, 0.124381, 0.138086",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.265675, 0.190363, 0.122259, 0.099381, 0.163106",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[20]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.139594, -0.097166, -0.062704, -0.022783, 0.289451",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173554, -0.107466, -0.049560, -0.007532, 0.212647",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[20]_hldr*/
+
+} /* end of pin tl_o[20] */
+
+pin("tl_o[19]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002405 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[19];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.049247, 0.202011, 0.377177, 0.699733, 1.344843",\
+ "0.135622, 0.289186, 0.464282, 0.786447, 1.430777",\
+ "0.219089, 0.377313, 0.552236, 0.874068, 1.517732",\
+ "0.277267, 0.441706, 0.616352, 0.937981, 1.581241",\
+ "0.578868, 0.791580, 0.966732, 1.286721, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.025529, 0.301292, 0.634182, 1.250309, 2.482563",\
+ "0.029899, 0.302288, 0.636124, 1.250309, 2.482563",\
+ "0.042689, 0.304530, 0.636160, 1.250309, 2.482563",\
+ "0.054614, 0.307788, 0.636263, 1.250309, 2.482563",\
+ "0.130534, 0.345945, 0.642513, 1.252858, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.068762, 0.173425, 0.284737, 0.488725, 0.896701",\
+ "0.156170, 0.260743, 0.372018, 0.576030, 0.984055",\
+ "0.236545, 0.341075, 0.452045, 0.656059, 1.064086",\
+ "0.293277, 0.398624, 0.509587, 0.713303, 1.120734",\
+ "0.587496, 0.701965, 0.813219, 1.016316, 1.422511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.025535, 0.188296, 0.388444, 0.760406, 1.504329",\
+ "0.025535, 0.188444, 0.388947, 0.760406, 1.504329",\
+ "0.026576, 0.188444, 0.388947, 0.760406, 1.504329",\
+ "0.028604, 0.188444, 0.388947, 0.760406, 1.504329",\
+ "0.047029, 0.192380, 0.388947, 0.760406, 1.504609");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[19]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.049247, 0.202011, 0.377177, 0.699733, 1.344843",\
+ "0.135622, 0.289186, 0.464282, 0.786447, 1.430777",\
+ "0.219089, 0.377313, 0.552236, 0.874068, 1.517732",\
+ "0.277267, 0.441706, 0.616352, 0.937981, 1.581241",\
+ "0.578868, 0.791580, 0.966732, 1.286721, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.025529, 0.301292, 0.634182, 1.249076, 2.473548",\
+ "0.029899, 0.302288, 0.636124, 1.249076, 2.473548",\
+ "0.042689, 0.304530, 0.636160, 1.249152, 2.473548",\
+ "0.054614, 0.307788, 0.636263, 1.249897, 2.473548",\
+ "0.130534, 0.345945, 0.642513, 1.252858, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.068762, 0.173425, 0.284737, 0.488725, 0.896701",\
+ "0.156170, 0.260743, 0.372018, 0.576030, 0.984055",\
+ "0.236545, 0.341075, 0.452045, 0.656059, 1.064086",\
+ "0.293277, 0.398624, 0.509587, 0.713303, 1.120734",\
+ "0.587496, 0.701965, 0.813219, 1.016316, 1.422511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.025535, 0.187494, 0.386936, 0.758174, 1.500652",\
+ "0.025535, 0.187494, 0.386936, 0.758174, 1.500652",\
+ "0.026576, 0.187494, 0.386936, 0.758174, 1.500652",\
+ "0.028604, 0.188103, 0.387393, 0.759077, 1.502444",\
+ "0.047029, 0.192380, 0.387467, 0.759848, 1.504609");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[19]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025529, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212708, 0.166837, 0.136642, 0.125302, 0.139006",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025535, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266222, 0.190910, 0.122806, 0.099928, 0.163653",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[19]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025529, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140504, -0.098076, -0.063615, -0.023693, 0.288541",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025535, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174097, -0.108010, -0.050104, -0.008076, 0.212104",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[19]_hldr*/
+
+} /* end of pin tl_o[19] */
+
+pin("tl_o[18]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002343 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[18];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\
+ "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\
+ "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\
+ "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\
+ "0.578356, 0.791455, 0.966639, 1.286659, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.025304, 0.301054, 0.634003, 1.250190, 2.482563",\
+ "0.029697, 0.302049, 0.635945, 1.250190, 2.482563",\
+ "0.042512, 0.304293, 0.635981, 1.250190, 2.482563",\
+ "0.054434, 0.307555, 0.636084, 1.250190, 2.482563",\
+ "0.130308, 0.345742, 0.642335, 1.252740, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\
+ "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\
+ "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\
+ "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\
+ "0.587289, 0.701891, 0.813166, 1.016283, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.025390, 0.188165, 0.388347, 0.760345, 1.504341",\
+ "0.025390, 0.188312, 0.388850, 0.760345, 1.504341",\
+ "0.026437, 0.188312, 0.388850, 0.760345, 1.504341",\
+ "0.028472, 0.188312, 0.388850, 0.760345, 1.504341",\
+ "0.046924, 0.192253, 0.388850, 0.760345, 1.504621");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[18]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\
+ "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\
+ "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\
+ "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\
+ "0.578356, 0.791455, 0.966639, 1.286659, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.025304, 0.301054, 0.634003, 1.248957, 2.473548",\
+ "0.029697, 0.302049, 0.635945, 1.248957, 2.473548",\
+ "0.042512, 0.304293, 0.635981, 1.249033, 2.473548",\
+ "0.054434, 0.307555, 0.636084, 1.249777, 2.473548",\
+ "0.130308, 0.345742, 0.642335, 1.252740, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\
+ "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\
+ "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\
+ "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\
+ "0.587289, 0.701891, 0.813166, 1.016283, 1.422517");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\
+ "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\
+ "0.026437, 0.187363, 0.386838, 0.758113, 1.500664",\
+ "0.028472, 0.187972, 0.387296, 0.759016, 1.502455",\
+ "0.046924, 0.192253, 0.387369, 0.759786, 1.504621");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[18]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.212613, 0.166742, 0.136547, 0.125206, 0.138911",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.266167, 0.190856, 0.122752, 0.099874, 0.163599",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[18]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.140410, -0.097982, -0.063521, -0.023599, 0.288635",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.174043, -0.107956, -0.050050, -0.008022, 0.212157",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[18]_hldr*/
+
+} /* end of pin tl_o[18] */
+
+pin("tl_o[17]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001292 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[17];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.046108, 0.199767, 0.375492, 0.698609, 1.344843",\
+ "0.132284, 0.286942, 0.462599, 0.785325, 1.430777",\
+ "0.214897, 0.375071, 0.550555, 0.872948, 1.517732",\
+ "0.272255, 0.439468, 0.614671, 0.936861, 1.581241",\
+ "0.568906, 0.789330, 0.965061, 1.285606, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.021470, 0.297034, 0.630964, 1.248164, 2.482563",\
+ "0.026264, 0.298006, 0.632922, 1.248164, 2.482563",\
+ "0.039476, 0.300287, 0.632958, 1.248164, 2.482563",\
+ "0.051325, 0.303602, 0.633057, 1.248164, 2.482563",\
+ "0.126317, 0.342305, 0.639325, 1.250732, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.065928, 0.172045, 0.283720, 0.488064, 0.896750",\
+ "0.153370, 0.259364, 0.371001, 0.575369, 0.984104",\
+ "0.233677, 0.339702, 0.451028, 0.655397, 1.064135",\
+ "0.290278, 0.397250, 0.508572, 0.712642, 1.120783",\
+ "0.583192, 0.700584, 0.812206, 1.015657, 1.422559");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.022780, 0.185829, 0.386590, 0.759200, 1.504419",\
+ "0.022780, 0.185969, 0.387096, 0.759200, 1.504419",\
+ "0.023886, 0.185969, 0.387096, 0.759200, 1.504419",\
+ "0.026044, 0.185969, 0.387096, 0.759200, 1.504419",\
+ "0.044904, 0.189998, 0.387096, 0.759200, 1.504699");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[17]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.046108, 0.199767, 0.375492, 0.698609, 1.344843",\
+ "0.132284, 0.286942, 0.462599, 0.785325, 1.430777",\
+ "0.214897, 0.375071, 0.550555, 0.872948, 1.517732",\
+ "0.272255, 0.439468, 0.614671, 0.936861, 1.581241",\
+ "0.568906, 0.789330, 0.965061, 1.285606, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.021470, 0.297034, 0.630964, 1.246942, 2.473548",\
+ "0.026264, 0.298006, 0.632922, 1.246942, 2.473548",\
+ "0.039476, 0.300287, 0.632958, 1.247017, 2.473548",\
+ "0.051325, 0.303602, 0.633057, 1.247760, 2.473548",\
+ "0.126317, 0.342305, 0.639325, 1.250732, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.065928, 0.172045, 0.283720, 0.488064, 0.896750",\
+ "0.153370, 0.259364, 0.371001, 0.575369, 0.984104",\
+ "0.233677, 0.339702, 0.451028, 0.655397, 1.064135",\
+ "0.290278, 0.397250, 0.508572, 0.712642, 1.120783",\
+ "0.583192, 0.700584, 0.812206, 1.015657, 1.422559");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.022780, 0.185036, 0.385085, 0.756971, 1.500741",\
+ "0.022780, 0.185036, 0.385085, 0.756971, 1.500741",\
+ "0.023886, 0.185036, 0.385085, 0.756971, 1.500741",\
+ "0.026044, 0.185649, 0.385541, 0.757872, 1.502533",\
+ "0.044904, 0.189998, 0.385611, 0.758640, 1.504699");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[17]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.021470, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.210993, 0.165122, 0.134927, 0.123587, 0.137292",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022780, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.265192, 0.189881, 0.121777, 0.098899, 0.162623",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[17]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.021470, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.138808, -0.096380, -0.061918, -0.021997, 0.290238",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022780, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173074, -0.106987, -0.049081, -0.007053, 0.213127",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[17]_hldr*/
+
+} /* end of pin tl_o[17] */
+
+pin("tl_o[16]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001808 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[16];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.047630, 0.200806, 0.376273, 0.699130, 1.344843",\
+ "0.133916, 0.287981, 0.463378, 0.785845, 1.430777",\
+ "0.216984, 0.376109, 0.551334, 0.873467, 1.517732",\
+ "0.274762, 0.440505, 0.615450, 0.937380, 1.581241",\
+ "0.573940, 0.790372, 0.965835, 1.286123, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.023359, 0.299007, 0.632455, 1.249158, 2.482563",\
+ "0.027955, 0.299990, 0.634405, 1.249158, 2.482563",\
+ "0.040984, 0.302252, 0.634441, 1.249158, 2.482563",\
+ "0.052879, 0.305541, 0.634542, 1.249158, 2.482563",\
+ "0.128359, 0.343991, 0.640802, 1.251717, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.067337, 0.172678, 0.284185, 0.488364, 0.896721",\
+ "0.154749, 0.259997, 0.371466, 0.575669, 0.984075",\
+ "0.235101, 0.340332, 0.451493, 0.655697, 1.064106",\
+ "0.291776, 0.397881, 0.509036, 0.712942, 1.120754",\
+ "0.585400, 0.701218, 0.812669, 1.015956, 1.422531");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.024064, 0.186961, 0.387438, 0.759747, 1.504366",\
+ "0.024064, 0.187105, 0.387942, 0.759747, 1.504366",\
+ "0.025170, 0.187105, 0.387942, 0.759747, 1.504366",\
+ "0.027260, 0.187105, 0.387942, 0.759747, 1.504366",\
+ "0.045966, 0.191091, 0.387942, 0.759747, 1.504646");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[16]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.047630, 0.200806, 0.376273, 0.699130, 1.344843",\
+ "0.133916, 0.287981, 0.463378, 0.785845, 1.430777",\
+ "0.216984, 0.376109, 0.551334, 0.873467, 1.517732",\
+ "0.274762, 0.440505, 0.615450, 0.937380, 1.581241",\
+ "0.573940, 0.790372, 0.965835, 1.286123, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.023359, 0.299007, 0.632455, 1.247931, 2.473548",\
+ "0.027955, 0.299990, 0.634405, 1.247931, 2.473548",\
+ "0.040984, 0.302252, 0.634441, 1.248006, 2.473548",\
+ "0.052879, 0.305541, 0.634542, 1.248749, 2.473548",\
+ "0.128359, 0.343991, 0.640802, 1.251717, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.067337, 0.172678, 0.284185, 0.488364, 0.896721",\
+ "0.154749, 0.259997, 0.371466, 0.575669, 0.984075",\
+ "0.235101, 0.340332, 0.451493, 0.655697, 1.064106",\
+ "0.291776, 0.397881, 0.509036, 0.712942, 1.120754",\
+ "0.585400, 0.701218, 0.812669, 1.015956, 1.422531");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.024064, 0.186164, 0.385931, 0.757517, 1.500689",\
+ "0.024064, 0.186164, 0.385931, 0.757517, 1.500689",\
+ "0.025170, 0.186164, 0.385931, 0.757517, 1.500689",\
+ "0.027260, 0.186775, 0.386388, 0.758419, 1.502481",\
+ "0.045966, 0.191091, 0.386459, 0.759188, 1.504646");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[16]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\
+ "0.211791, 0.165920, 0.135725, 0.124385, 0.138090",\
+ "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\
+ "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\
+ "0.793561, 0.745754, 0.715310, 0.703809, 0.716803");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024064, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\
+ "0.265672, 0.190361, 0.122257, 0.099379, 0.163103",\
+ "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\
+ "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\
+ "0.899406, 0.824219, 0.756483, 0.734362, 0.805439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[16]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\
+ "-0.139597, -0.097169, -0.062708, -0.022786, 0.289448",\
+ "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\
+ "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\
+ "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024064, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\
+ "-0.173551, -0.107464, -0.049558, -0.007530, 0.212650",\
+ "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\
+ "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\
+ "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[16]_hldr*/
+
+} /* end of pin tl_o[16] */
+
+pin("tl_o[15]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.035370 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ function : "0" ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[15];
+} /* end of pin tl_o[15] */
+
+pin("tl_o[14]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.154883 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[14];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[62]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.487261, 0.669190, 0.852549, 1.146075, 1.714279",\
+ "0.520839, 0.702769, 0.886128, 1.179654, 1.747858",\
+ "0.591826, 0.773756, 0.957115, 1.250640, 1.818845",\
+ "0.846910, 1.028840, 1.212200, 1.505725, 2.073928",\
+ "1.772164, 1.954093, 2.137452, 2.430978, 2.999182",\
+ "0.574671, 0.756577, 0.940009, 1.233380, 1.801632",\
+ "0.608250, 0.790156, 0.973588, 1.266959, 1.835211",\
+ "0.679237, 0.861143, 1.044574, 1.337945, 1.906198",\
+ "0.934321, 1.116227, 1.299660, 1.593030, 2.161281",\
+ "1.859574, 2.041480, 2.224912, 2.518283, 3.086535",\
+ "0.655541, 0.836911, 1.020036, 1.313408, 1.881664",\
+ "0.689120, 0.870490, 1.053615, 1.346987, 1.915242",\
+ "0.760107, 0.941477, 1.124601, 1.417974, 1.986230",\
+ "1.015191, 1.196561, 1.379687, 1.673059, 2.241313",\
+ "1.940444, 2.121814, 2.304939, 2.598311, 3.166567",\
+ "0.713217, 0.894460, 1.077579, 1.370653, 1.938311",\
+ "0.746796, 0.928038, 1.111158, 1.404232, 1.971890",\
+ "0.817783, 0.999025, 1.182144, 1.475219, 2.042877",\
+ "1.072867, 1.254110, 1.437230, 1.730303, 2.297960",\
+ "1.998120, 2.179363, 2.362482, 2.655556, 3.223215",\
+ "1.015892, 1.199670, 1.381211, 1.673666, 2.240149",\
+ "1.049471, 1.233248, 1.414790, 1.707245, 2.273727",\
+ "1.120458, 1.304235, 1.485777, 1.778232, 2.344714",\
+ "1.375542, 1.559320, 1.740862, 2.033317, 2.599797",\
+ "2.300795, 2.484573, 2.666114, 2.958570, 3.525052");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\
+ "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\
+ "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\
+ "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\
+ "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\
+ "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\
+ "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\
+ "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\
+ "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\
+ "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\
+ "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\
+ "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\
+ "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\
+ "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\
+ "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\
+ "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\
+ "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\
+ "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\
+ "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\
+ "2.458885, 2.458885, 2.458885, 2.458885, 2.458885");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.570397, 0.827870, 1.084327, 1.522623, 2.399216",\
+ "0.611284, 0.868757, 1.125214, 1.563510, 2.440103",\
+ "0.671440, 0.928913, 1.185369, 1.623666, 2.500259",\
+ "0.840387, 1.097859, 1.354316, 1.792613, 2.669205",\
+ "1.423797, 1.681270, 1.937729, 2.376020, 3.252604",\
+ "0.658623, 0.915349, 1.171797, 1.609338, 2.485150",\
+ "0.699510, 0.956236, 1.212684, 1.650225, 2.526037",\
+ "0.759666, 1.016392, 1.272839, 1.710381, 2.586193",\
+ "0.928613, 1.185339, 1.441786, 1.879327, 2.755138",\
+ "1.512023, 1.768749, 2.025198, 2.462735, 3.338538",\
+ "0.747341, 1.004170, 1.259759, 1.696960, 2.572105",\
+ "0.788228, 1.045057, 1.300646, 1.737847, 2.612992",\
+ "0.848383, 1.105212, 1.360802, 1.798002, 2.673148",\
+ "1.017330, 1.274159, 1.529749, 1.966949, 2.842093",\
+ "1.600740, 1.857569, 2.113161, 2.550357, 3.425493",\
+ "0.810342, 1.069571, 1.323894, 1.760873, 2.635614",\
+ "0.851229, 1.110458, 1.364781, 1.801760, 2.676501",\
+ "0.911385, 1.170614, 1.424936, 1.861916, 2.736657",\
+ "1.080332, 1.339561, 1.593883, 2.030862, 2.905602",\
+ "1.663742, 1.922971, 2.177295, 2.614270, 3.489002",\
+ "1.142661, 1.431230, 1.675450, 2.110093, 2.981070",\
+ "1.183547, 1.472117, 1.716337, 2.150980, 3.021957",\
+ "1.243703, 1.532272, 1.776492, 2.211136, 3.082113",\
+ "1.412650, 1.701219, 1.945439, 2.380082, 3.251059",\
+ "1.996059, 2.284630, 2.528851, 2.963490, 3.834458");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\
+ "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\
+ "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\
+ "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\
+ "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\
+ "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\
+ "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\
+ "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\
+ "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\
+ "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\
+ "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\
+ "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\
+ "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\
+ "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\
+ "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\
+ "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\
+ "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\
+ "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\
+ "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\
+ "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\
+ "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\
+ "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\
+ "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\
+ "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\
+ "1.494947, 1.494947, 1.494950, 1.494958, 1.494974");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[14]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[62]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.487261, 0.668812, 0.852015, 1.145595, 1.713488",\
+ "0.520839, 0.702391, 0.885594, 1.179174, 1.747067",\
+ "0.591826, 0.773378, 0.956580, 1.250161, 1.818054",\
+ "0.846910, 1.028462, 1.211666, 1.505246, 2.073137",\
+ "1.772164, 1.953715, 2.136918, 2.430498, 2.998391",\
+ "0.574671, 0.756130, 0.939295, 1.232900, 1.800842",\
+ "0.608250, 0.789709, 0.972874, 1.266479, 1.834420",\
+ "0.679237, 0.860696, 1.043861, 1.337466, 1.905408",\
+ "0.934321, 1.115781, 1.298946, 1.592551, 2.160491",\
+ "1.859574, 2.041033, 2.224198, 2.517803, 3.085745",\
+ "0.655541, 0.836464, 1.019322, 1.312929, 1.880873",\
+ "0.689120, 0.870043, 1.052901, 1.346508, 1.914452",\
+ "0.760107, 0.941030, 1.123888, 1.417494, 1.985439",\
+ "1.015191, 1.196114, 1.378973, 1.672579, 2.240522",\
+ "1.940444, 2.121367, 2.304225, 2.597832, 3.165776",\
+ "0.713217, 0.894301, 1.077028, 1.370367, 1.937906",\
+ "0.746796, 0.927880, 1.110607, 1.403946, 1.971485",\
+ "0.817783, 0.998867, 1.181593, 1.474933, 2.042472",\
+ "1.072867, 1.253952, 1.436679, 1.730018, 2.297555",\
+ "1.998120, 2.179204, 2.361931, 2.655270, 3.222809",\
+ "1.015892, 1.199670, 1.380685, 1.673546, 2.240149",\
+ "1.049471, 1.233248, 1.414264, 1.707125, 2.273727",\
+ "1.120458, 1.304235, 1.485251, 1.778112, 2.344714",\
+ "1.375542, 1.559320, 1.740336, 2.033197, 2.599797",\
+ "2.300795, 2.484573, 2.665588, 2.958449, 3.525052");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\
+ "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\
+ "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\
+ "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\
+ "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\
+ "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\
+ "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\
+ "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\
+ "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\
+ "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\
+ "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\
+ "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\
+ "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\
+ "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\
+ "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\
+ "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\
+ "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\
+ "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\
+ "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\
+ "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\
+ "2.458656, 2.458656, 2.458656, 2.458656, 2.458656");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.570397, 0.827870, 1.084327, 1.522393, 2.397526",\
+ "0.611284, 0.868757, 1.125214, 1.563280, 2.438413",\
+ "0.671440, 0.928913, 1.185369, 1.623435, 2.498569",\
+ "0.840387, 1.097859, 1.354316, 1.792382, 2.667514",\
+ "1.423797, 1.681270, 1.937729, 2.375790, 3.250914",\
+ "0.658623, 0.915349, 1.171797, 1.609107, 2.483460",\
+ "0.699510, 0.956236, 1.212684, 1.649994, 2.524347",\
+ "0.759666, 1.016392, 1.272839, 1.710150, 2.584503",\
+ "0.928613, 1.185339, 1.441786, 1.879097, 2.753448",\
+ "1.512023, 1.768749, 2.025198, 2.462505, 3.336848",\
+ "0.747341, 1.004170, 1.259759, 1.696743, 2.570415",\
+ "0.788228, 1.045057, 1.300646, 1.737630, 2.611302",\
+ "0.848383, 1.105212, 1.360802, 1.797786, 2.671458",\
+ "1.017330, 1.274159, 1.529749, 1.966733, 2.840403",\
+ "1.600740, 1.857569, 2.113161, 2.550140, 3.423803",\
+ "0.810342, 1.069571, 1.323894, 1.760796, 2.633924",\
+ "0.851229, 1.110458, 1.364781, 1.801683, 2.674811",\
+ "0.911385, 1.170614, 1.424936, 1.861839, 2.734967",\
+ "1.080332, 1.339561, 1.593883, 2.030786, 2.903912",\
+ "1.663742, 1.922971, 2.177295, 2.614193, 3.487312",\
+ "1.142661, 1.431230, 1.675450, 2.110093, 2.979380",\
+ "1.183547, 1.472117, 1.716337, 2.150980, 3.020267",\
+ "1.243703, 1.532272, 1.776492, 2.211136, 3.080423",\
+ "1.412650, 1.701219, 1.945439, 2.380082, 3.249368",\
+ "1.996059, 2.284630, 2.528851, 2.963490, 3.832768");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\
+ "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\
+ "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\
+ "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\
+ "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\
+ "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\
+ "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\
+ "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\
+ "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\
+ "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\
+ "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\
+ "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\
+ "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\
+ "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\
+ "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\
+ "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\
+ "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\
+ "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\
+ "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\
+ "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\
+ "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\
+ "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\
+ "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\
+ "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\
+ "1.494932, 1.494932, 1.494936, 1.494948, 1.494973");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[14]_redg_min*/
+
+} /* end of pin tl_o[14] */
+
+pin("tl_o[13]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.035370 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[13];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[58]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.284540, 0.564046, 0.863617, 1.380944, 2.415600",\
+ "0.298686, 0.578104, 0.877668, 1.395235, 2.430368",\
+ "0.322356, 0.601709, 0.901313, 1.419287, 2.455237",\
+ "0.588425, 0.867068, 1.165530, 1.682108, 2.715266",\
+ "1.177776, 1.456090, 1.753734, 2.268545, 3.298168",\
+ "0.372946, 0.651675, 0.951331, 1.467657, 2.501533",\
+ "0.387092, 0.665733, 0.965383, 1.481948, 2.516302",\
+ "0.410761, 0.689337, 0.989029, 1.506001, 2.541171",\
+ "0.676826, 0.954691, 1.253242, 1.768821, 2.801200",\
+ "1.266174, 1.543712, 1.841440, 2.355258, 3.384101",\
+ "0.462897, 0.740788, 1.039296, 1.555278, 2.588488",\
+ "0.477041, 0.754844, 1.053348, 1.569568, 2.603257",\
+ "0.500709, 0.778447, 1.076994, 1.593621, 2.628126",\
+ "0.766761, 1.043790, 1.341207, 1.856442, 2.888155",\
+ "1.356101, 1.632807, 1.929405, 2.442878, 3.471056",\
+ "0.527359, 0.806612, 1.103444, 1.619190, 2.651997",\
+ "0.541500, 0.820667, 1.117496, 1.633481, 2.666766",\
+ "0.565168, 0.844269, 1.141142, 1.657534, 2.691635",\
+ "0.831207, 1.109596, 1.405354, 1.920354, 2.951664",\
+ "1.420539, 1.698606, 1.993552, 2.506791, 3.534565",\
+ "0.868940, 1.173349, 1.455796, 1.968728, 2.997453",\
+ "0.883067, 1.187384, 1.469851, 1.983020, 3.012222",\
+ "0.906732, 1.210965, 1.493501, 2.007074, 3.037091",\
+ "1.172689, 1.476110, 1.757699, 2.269889, 3.297120",\
+ "1.761970, 2.065045, 2.345879, 2.856318, 3.880022");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.185739, 0.187595, 0.200176, 0.234510, 0.303179",\
+ "0.203933, 0.205579, 0.217466, 0.250509, 0.316595",\
+ "0.237929, 0.239084, 0.249124, 0.278309, 0.336679",\
+ "0.816189, 0.816358, 0.816864, 0.818096, 0.820559",\
+ "2.192673, 2.192673, 2.192836, 2.193388, 2.194490",\
+ "0.185741, 0.187611, 0.200283, 0.234510, 0.303179",\
+ "0.203935, 0.205594, 0.217569, 0.250509, 0.316595",\
+ "0.237932, 0.239093, 0.249216, 0.278309, 0.336679",\
+ "0.816190, 0.816359, 0.816868, 0.818096, 0.820559",\
+ "2.192673, 2.192673, 2.192838, 2.193388, 2.194490",\
+ "0.185746, 0.187647, 0.200285, 0.234510, 0.303179",\
+ "0.203942, 0.205625, 0.217571, 0.250509, 0.316595",\
+ "0.237941, 0.239114, 0.249217, 0.278309, 0.336679",\
+ "0.816195, 0.816361, 0.816868, 0.818096, 0.820559",\
+ "2.192673, 2.192673, 2.192838, 2.193388, 2.194490",\
+ "0.185751, 0.187699, 0.200291, 0.234510, 0.303179",\
+ "0.203948, 0.205670, 0.217577, 0.250509, 0.316595",\
+ "0.237949, 0.239145, 0.249223, 0.278309, 0.336679",\
+ "0.816200, 0.816364, 0.816869, 0.818096, 0.820559",\
+ "2.192673, 2.192673, 2.192838, 2.193388, 2.194490",\
+ "0.185783, 0.188312, 0.200639, 0.234651, 0.303179",\
+ "0.203989, 0.206205, 0.217912, 0.250645, 0.316595",\
+ "0.238001, 0.239502, 0.249518, 0.278429, 0.336679",\
+ "0.816229, 0.816400, 0.816881, 0.818101, 0.820559",\
+ "2.192673, 2.192673, 2.192844, 2.193390, 2.194490");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.374522, 0.561124, 0.780572, 1.136359, 1.826584",\
+ "0.383805, 0.570576, 0.790645, 1.147661, 1.840366",\
+ "0.399074, 0.586082, 0.807015, 1.165645, 1.861569",\
+ "0.557633, 0.745097, 0.967701, 1.332699, 2.042731",\
+ "0.898199, 1.085553, 1.307755, 1.673592, 2.385983",\
+ "0.461924, 0.648520, 0.868125, 1.223665, 1.913938",\
+ "0.471207, 0.657972, 0.878200, 1.234966, 1.927719",\
+ "0.486476, 0.673478, 0.894572, 1.252950, 1.948923",\
+ "0.645035, 0.832494, 1.055262, 1.420004, 2.130085",\
+ "0.985600, 1.172950, 1.395316, 1.760897, 2.473337",\
+ "0.542814, 0.728848, 0.948152, 1.303693, 1.993969",\
+ "0.552097, 0.738300, 0.958227, 1.314994, 2.007751",\
+ "0.567368, 0.753806, 0.974599, 1.332979, 2.028955",\
+ "0.725929, 0.912822, 1.135289, 1.500032, 2.210116",\
+ "1.066495, 1.253278, 1.475343, 1.840926, 2.553368",\
+ "0.600620, 0.786398, 1.005694, 1.360937, 2.050617",\
+ "0.609906, 0.795850, 1.015768, 1.372238, 2.064399",\
+ "0.625179, 0.811356, 1.032140, 1.390222, 2.085602",\
+ "0.783746, 0.970371, 1.192830, 1.557276, 2.266764",\
+ "1.124310, 1.310827, 1.532884, 1.898169, 2.610016",\
+ "0.904940, 1.091713, 1.309322, 1.663948, 2.352501",\
+ "0.914244, 1.101169, 1.319397, 1.675249, 2.366283",\
+ "0.929544, 1.116681, 1.335769, 1.693234, 2.387488",\
+ "1.088161, 1.275707, 1.496459, 1.860287, 2.568655",\
+ "1.428713, 1.616160, 1.836513, 2.201180, 2.911908");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.065408, 0.068159, 0.078360, 0.098953, 0.140695",\
+ "0.068352, 0.070728, 0.079541, 0.099563, 0.141041",\
+ "0.087647, 0.089359, 0.095706, 0.112588, 0.148436",\
+ "0.381015, 0.381154, 0.381669, 0.388289, 0.403942",\
+ "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\
+ "0.065408, 0.068161, 0.078386, 0.098953, 0.140695",\
+ "0.068352, 0.070731, 0.079564, 0.099563, 0.141041",\
+ "0.087647, 0.089361, 0.095723, 0.112588, 0.148436",\
+ "0.381015, 0.381154, 0.381670, 0.388289, 0.403942",\
+ "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\
+ "0.065424, 0.068161, 0.078386, 0.098953, 0.140695",\
+ "0.068366, 0.070731, 0.079564, 0.099563, 0.141041",\
+ "0.087657, 0.089361, 0.095723, 0.112588, 0.148436",\
+ "0.381016, 0.381154, 0.381670, 0.388289, 0.403942",\
+ "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\
+ "0.065456, 0.068161, 0.078386, 0.098953, 0.140695",\
+ "0.068394, 0.070731, 0.079564, 0.099563, 0.141041",\
+ "0.087678, 0.089361, 0.095723, 0.112588, 0.148436",\
+ "0.381018, 0.381154, 0.381670, 0.388289, 0.403942",\
+ "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\
+ "0.065761, 0.068226, 0.078386, 0.098953, 0.140710",\
+ "0.068657, 0.070787, 0.079564, 0.099563, 0.141057",\
+ "0.087867, 0.089401, 0.095723, 0.112588, 0.148450",\
+ "0.381033, 0.381158, 0.381670, 0.388289, 0.403948",\
+ "1.027611, 1.027611, 1.027611, 1.028167, 1.029517");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[13]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[58]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.284540, 0.564046, 0.863617, 1.380550, 2.412738",\
+ "0.298686, 0.578104, 0.877668, 1.394840, 2.427504",\
+ "0.322356, 0.601709, 0.901313, 1.418892, 2.452366",\
+ "0.588425, 0.867068, 1.165530, 1.681715, 2.712415",\
+ "1.177776, 1.456090, 1.753734, 2.268156, 3.295343",\
+ "0.372946, 0.651675, 0.951331, 1.467263, 2.498672",\
+ "0.387092, 0.665733, 0.965383, 1.481553, 2.513437",\
+ "0.410761, 0.689337, 0.989029, 1.505605, 2.538300",\
+ "0.676826, 0.954691, 1.253242, 1.768429, 2.798349",\
+ "1.266174, 1.543712, 1.841440, 2.354868, 3.381277",\
+ "0.462897, 0.740788, 1.039296, 1.554907, 2.585627",\
+ "0.477041, 0.754844, 1.053348, 1.569197, 2.600392",\
+ "0.500709, 0.778447, 1.076994, 1.593250, 2.625255",\
+ "0.766761, 1.043790, 1.341207, 1.856073, 2.885304",\
+ "1.356101, 1.632807, 1.929405, 2.442513, 3.468232",\
+ "0.527359, 0.806612, 1.103444, 1.619057, 2.649136",\
+ "0.541500, 0.820667, 1.117496, 1.633347, 2.663901",\
+ "0.565168, 0.844269, 1.141142, 1.657400, 2.688764",\
+ "0.831207, 1.109596, 1.405354, 1.920222, 2.948813",\
+ "1.420539, 1.698606, 1.993552, 2.506659, 3.531741",\
+ "0.868940, 1.173349, 1.455796, 1.968728, 2.994592",\
+ "0.883067, 1.187384, 1.469851, 1.983020, 3.009357",\
+ "0.906732, 1.210965, 1.493501, 2.007074, 3.034220",\
+ "1.172689, 1.476110, 1.757699, 2.269889, 3.294269",\
+ "1.761970, 2.065045, 2.345879, 2.856318, 3.877197");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.185739, 0.187595, 0.200176, 0.234441, 0.302676",\
+ "0.203933, 0.205579, 0.217466, 0.250442, 0.316110",\
+ "0.237929, 0.239084, 0.249124, 0.278250, 0.336252",\
+ "0.816189, 0.816358, 0.816864, 0.818093, 0.820541",\
+ "2.191667, 2.191667, 2.191920, 2.192775, 2.194479",\
+ "0.185741, 0.187611, 0.200283, 0.234441, 0.302676",\
+ "0.203935, 0.205594, 0.217569, 0.250442, 0.316110",\
+ "0.237932, 0.239093, 0.249216, 0.278250, 0.336252",\
+ "0.816190, 0.816359, 0.816868, 0.818093, 0.820541",\
+ "2.191667, 2.191667, 2.191923, 2.192775, 2.194479",\
+ "0.185746, 0.187647, 0.200285, 0.234445, 0.302676",\
+ "0.203942, 0.205625, 0.217571, 0.250446, 0.316110",\
+ "0.237941, 0.239114, 0.249217, 0.278254, 0.336252",\
+ "0.816195, 0.816361, 0.816868, 0.818094, 0.820541",\
+ "2.191667, 2.191667, 2.191923, 2.192775, 2.194479",\
+ "0.185751, 0.187699, 0.200291, 0.234487, 0.302676",\
+ "0.203948, 0.205670, 0.217577, 0.250486, 0.316110",\
+ "0.237949, 0.239145, 0.249223, 0.278289, 0.336252",\
+ "0.816200, 0.816364, 0.816869, 0.818095, 0.820541",\
+ "2.191667, 2.191667, 2.191923, 2.192777, 2.194479",\
+ "0.185783, 0.188312, 0.200639, 0.234651, 0.302676",\
+ "0.203989, 0.206205, 0.217912, 0.250645, 0.316110",\
+ "0.238001, 0.239502, 0.249518, 0.278429, 0.336252",\
+ "0.816229, 0.816400, 0.816881, 0.818101, 0.820541",\
+ "2.191667, 2.191667, 2.191932, 2.192781, 2.194479");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.374522, 0.560710, 0.779750, 1.135509, 1.825184",\
+ "0.383805, 0.570161, 0.789818, 1.146803, 1.838953",\
+ "0.399074, 0.585665, 0.806181, 1.164778, 1.860141",\
+ "0.557633, 0.744678, 0.966854, 1.331789, 2.041233",\
+ "0.898199, 1.085135, 1.306912, 1.672675, 2.384473",\
+ "0.461924, 0.648027, 0.867031, 1.222814, 1.912538",\
+ "0.471207, 0.657479, 0.877099, 1.234108, 1.926307",\
+ "0.486476, 0.672983, 0.893462, 1.252083, 1.947495",\
+ "0.645035, 0.831996, 1.054135, 1.419094, 2.128587",\
+ "0.985600, 1.172452, 1.394193, 1.759980, 2.471827",\
+ "0.542814, 0.728355, 0.947058, 1.302843, 1.992569",\
+ "0.552097, 0.737807, 0.957126, 1.314137, 2.006338",\
+ "0.567368, 0.753311, 0.973489, 1.332111, 2.027526",\
+ "0.725929, 0.912324, 1.134162, 1.499123, 2.208618",\
+ "1.066495, 1.252781, 1.474220, 1.840009, 2.551858",\
+ "0.600620, 0.786214, 1.004849, 1.360430, 2.049899",\
+ "0.609906, 0.795666, 1.014919, 1.371727, 2.063674",\
+ "0.625179, 0.811172, 1.031284, 1.389706, 2.084870",\
+ "0.783746, 0.970186, 1.191961, 1.556734, 2.265996",\
+ "1.124310, 1.310642, 1.532018, 1.897623, 2.609242",\
+ "0.904940, 1.091713, 1.308519, 1.663736, 2.352501",\
+ "0.914244, 1.101169, 1.318589, 1.675035, 2.366283",\
+ "0.929544, 1.116681, 1.334955, 1.693017, 2.387488",\
+ "1.088161, 1.275707, 1.495632, 1.860060, 2.568655",\
+ "1.428713, 1.616160, 1.835689, 2.200952, 2.911908");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.065408, 0.068145, 0.078282, 0.097416, 0.135633",\
+ "0.068319, 0.070715, 0.079474, 0.098027, 0.135980",\
+ "0.087624, 0.089350, 0.095658, 0.111069, 0.143404",\
+ "0.381014, 0.381153, 0.381665, 0.388242, 0.403865",\
+ "1.027072, 1.027072, 1.027072, 1.027705, 1.029249",\
+ "0.065408, 0.068145, 0.078282, 0.097416, 0.135633",\
+ "0.068319, 0.070715, 0.079474, 0.098027, 0.135980",\
+ "0.087624, 0.089350, 0.095658, 0.111069, 0.143404",\
+ "0.381014, 0.381153, 0.381665, 0.388242, 0.403865",\
+ "1.027072, 1.027072, 1.027072, 1.027705, 1.029249",\
+ "0.065424, 0.068145, 0.078282, 0.097416, 0.135633",\
+ "0.068333, 0.070715, 0.079474, 0.098027, 0.135980",\
+ "0.087634, 0.089350, 0.095658, 0.111069, 0.143404",\
+ "0.381014, 0.381153, 0.381665, 0.388242, 0.403865",\
+ "1.027072, 1.027072, 1.027072, 1.027705, 1.029249",\
+ "0.065456, 0.068155, 0.078306, 0.097463, 0.135725",\
+ "0.068362, 0.070724, 0.079494, 0.098073, 0.136072",\
+ "0.087655, 0.089356, 0.095672, 0.111109, 0.143482",\
+ "0.381016, 0.381154, 0.381666, 0.388261, 0.403903",\
+ "1.027072, 1.027072, 1.027072, 1.027707, 1.029253",\
+ "0.065761, 0.068226, 0.078310, 0.097503, 0.135836",\
+ "0.068628, 0.070787, 0.079498, 0.098113, 0.136183",\
+ "0.087847, 0.089401, 0.095675, 0.111142, 0.143576",\
+ "0.381032, 0.381158, 0.381666, 0.388277, 0.403948",\
+ "1.027072, 1.027072, 1.027072, 1.027708, 1.029258");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[13]_redg_min*/
+
+} /* end of pin tl_o[13] */
+
+pin("tl_o[12]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.020161 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[12];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[57]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.475879, 0.665118, 0.888399, 1.250294, 1.951686",\
+ "0.526872, 0.716033, 0.939041, 1.300629, 2.001501",\
+ "0.604552, 0.793643, 1.016400, 1.377502, 2.077400",\
+ "0.813681, 1.002691, 1.225160, 1.585609, 2.284153",\
+ "1.367036, 1.556010, 1.778356, 2.138460, 2.836268",\
+ "0.563289, 0.752511, 0.975963, 1.337600, 2.039039",\
+ "0.614282, 0.803427, 1.026603, 1.387934, 2.088855",\
+ "0.691962, 0.881036, 1.103961, 1.464807, 2.164753",\
+ "0.901091, 1.090085, 1.312721, 1.672914, 2.371507",\
+ "1.454446, 1.643404, 1.865916, 2.225765, 2.923622",\
+ "0.644207, 0.832845, 1.055990, 1.417628, 2.119071",\
+ "0.695200, 0.883761, 1.106630, 1.467962, 2.168886",\
+ "0.772879, 0.961370, 1.183988, 1.544836, 2.244785",\
+ "0.982008, 1.170418, 1.392748, 1.752943, 2.451539",\
+ "1.535362, 1.723738, 1.945943, 2.305794, 3.003654",\
+ "0.701978, 0.890394, 1.113533, 1.474873, 2.175719",\
+ "0.752969, 0.941309, 1.164173, 1.525207, 2.225534",\
+ "0.830648, 1.018919, 1.241531, 1.602080, 2.301433",\
+ "1.039776, 1.227967, 1.450291, 1.810187, 2.508186",\
+ "1.593130, 1.781286, 2.003486, 2.363039, 3.060301",\
+ "1.005526, 1.195782, 1.417165, 1.777886, 2.477606",\
+ "1.056509, 1.246695, 1.467805, 1.828220, 2.527421",\
+ "1.134180, 1.324303, 1.545163, 1.905094, 2.603319",\
+ "1.343298, 1.533349, 1.753923, 2.113201, 2.810072",\
+ "1.896648, 2.086668, 2.307118, 2.666052, 3.362187");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.150008, 0.150413, 0.151867, 0.156224, 0.165642",\
+ "0.237388, 0.237631, 0.238503, 0.240761, 0.245540",\
+ "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\
+ "0.873945, 0.873960, 0.874011, 0.874292, 0.874933",\
+ "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\
+ "0.150008, 0.150413, 0.151871, 0.156224, 0.165642",\
+ "0.237388, 0.237631, 0.238506, 0.240761, 0.245540",\
+ "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\
+ "0.873945, 0.873960, 0.874011, 0.874292, 0.874933",\
+ "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\
+ "0.150011, 0.150413, 0.151871, 0.156224, 0.165642",\
+ "0.237390, 0.237631, 0.238506, 0.240761, 0.245540",\
+ "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\
+ "0.873945, 0.873960, 0.874011, 0.874292, 0.874933",\
+ "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\
+ "0.150016, 0.150413, 0.151871, 0.156224, 0.165642",\
+ "0.237393, 0.237631, 0.238506, 0.240761, 0.245540",\
+ "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\
+ "0.873946, 0.873960, 0.874011, 0.874292, 0.874933",\
+ "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\
+ "0.150062, 0.150423, 0.151871, 0.156224, 0.165645",\
+ "0.237420, 0.237637, 0.238506, 0.240761, 0.245542",\
+ "0.400539, 0.400554, 0.400616, 0.401193, 0.402548",\
+ "0.873947, 0.873960, 0.874011, 0.874292, 0.874933",\
+ "2.149644, 2.149644, 2.149644, 2.149724, 2.149920");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.321064, 0.601616, 0.902007, 1.418205, 2.450602",\
+ "0.356109, 0.636678, 0.937135, 1.453516, 2.486277",\
+ "0.406657, 0.687216, 0.987647, 1.504000, 2.536706",\
+ "0.536144, 0.816696, 1.117064, 1.633222, 2.665537",\
+ "0.873984, 1.154534, 1.454850, 1.970856, 3.002866",\
+ "0.409514, 0.689233, 0.989723, 1.504920, 2.536536",\
+ "0.444559, 0.724295, 1.024851, 1.540230, 2.572211",\
+ "0.495106, 0.774833, 1.075363, 1.590714, 2.622640",\
+ "0.624593, 0.904313, 1.204779, 1.719936, 2.751471",\
+ "0.962434, 1.242151, 1.542565, 2.057570, 3.088800",\
+ "0.498914, 0.778364, 1.077690, 1.592542, 2.623491",\
+ "0.533960, 0.813427, 1.112818, 1.627852, 2.659166",\
+ "0.584508, 0.863965, 1.163329, 1.678336, 2.709595",\
+ "0.713994, 0.993445, 1.292746, 1.807558, 2.838426",\
+ "1.051835, 1.331282, 1.630532, 2.145192, 3.175755",\
+ "0.562563, 0.844218, 1.141837, 1.656455, 2.687000",\
+ "0.597610, 0.879281, 1.176965, 1.691765, 2.722675",\
+ "0.648158, 0.929819, 1.227477, 1.742249, 2.773104",\
+ "0.777645, 1.059298, 1.356893, 1.871471, 2.901935",\
+ "1.115485, 1.397135, 1.694679, 2.209105, 3.239264",\
+ "0.898997, 1.211173, 1.494183, 2.005997, 3.032455",\
+ "0.934048, 1.246239, 1.529313, 2.041308, 3.068131",\
+ "0.984598, 1.296772, 1.579825, 2.091792, 3.118560",\
+ "1.114083, 1.426250, 1.709239, 2.221013, 3.247391",\
+ "1.451924, 1.764086, 2.047024, 2.558647, 3.584720");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.072029, 0.072117, 0.072944, 0.075686, 0.081171",\
+ "0.105035, 0.105045, 0.105444, 0.106815, 0.109557",\
+ "0.191067, 0.191185, 0.191447, 0.191928, 0.192889",\
+ "0.434550, 0.434818, 0.434976, 0.434976, 0.434976",\
+ "1.073490, 1.073490, 1.073593, 1.073946, 1.074653",\
+ "0.072030, 0.072117, 0.072953, 0.075686, 0.081171",\
+ "0.105035, 0.105045, 0.105449, 0.106815, 0.109557",\
+ "0.191068, 0.191185, 0.191449, 0.191928, 0.192889",\
+ "0.434555, 0.434819, 0.434976, 0.434976, 0.434976",\
+ "1.073490, 1.073490, 1.073594, 1.073946, 1.074653",\
+ "0.072035, 0.072117, 0.072953, 0.075686, 0.081171",\
+ "0.105035, 0.105045, 0.105449, 0.106815, 0.109557",\
+ "0.191071, 0.191187, 0.191449, 0.191928, 0.192889",\
+ "0.434567, 0.434821, 0.434976, 0.434976, 0.434976",\
+ "1.073490, 1.073490, 1.073594, 1.073946, 1.074653",\
+ "0.072040, 0.072118, 0.072953, 0.075686, 0.081171",\
+ "0.105036, 0.105045, 0.105449, 0.106815, 0.109557",\
+ "0.191073, 0.191190, 0.191449, 0.191928, 0.192889",\
+ "0.434578, 0.434825, 0.434976, 0.434976, 0.434976",\
+ "1.073490, 1.073490, 1.073594, 1.073946, 1.074653",\
+ "0.072068, 0.072127, 0.072981, 0.075698, 0.081171",\
+ "0.105040, 0.105046, 0.105463, 0.106821, 0.109557",\
+ "0.191088, 0.191220, 0.191454, 0.191930, 0.192889",\
+ "0.434649, 0.434864, 0.434976, 0.434976, 0.434976",\
+ "1.073490, 1.073490, 1.073597, 1.073947, 1.074653");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[12]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[57]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.475879, 0.664703, 0.887555, 1.249416, 1.950237",\
+ "0.526872, 0.715619, 0.938198, 1.299751, 2.000055",\
+ "0.604552, 0.793229, 1.015559, 1.376628, 2.075958",\
+ "0.813681, 1.002278, 1.224322, 1.584739, 2.282718",\
+ "1.367036, 1.555598, 1.777518, 2.137592, 2.834837",\
+ "0.563289, 0.752022, 0.974836, 1.336721, 2.037590",\
+ "0.614282, 0.802938, 1.025479, 1.387056, 2.087408",\
+ "0.691962, 0.880548, 1.102840, 1.463933, 2.163312",\
+ "0.901091, 1.089596, 1.311603, 1.672044, 2.370072",\
+ "1.454446, 1.642916, 1.864799, 2.224897, 2.922191",\
+ "0.644207, 0.832355, 1.054863, 1.416749, 2.117622",\
+ "0.695200, 0.883271, 1.105506, 1.467085, 2.167440",\
+ "0.772879, 0.960881, 1.182867, 1.543961, 2.243343",\
+ "0.982008, 1.169930, 1.391630, 1.752072, 2.450104",\
+ "1.535362, 1.723250, 1.944826, 2.304926, 3.002222",\
+ "0.701978, 0.890220, 1.112662, 1.474349, 2.174976",\
+ "0.752969, 0.941136, 1.163305, 1.524684, 2.224792",\
+ "0.830648, 1.018745, 1.240665, 1.601559, 2.300694",\
+ "1.039776, 1.227793, 1.449427, 1.809669, 2.507451",\
+ "1.593130, 1.781113, 2.002623, 2.362521, 3.059567",\
+ "1.005526, 1.195782, 1.416335, 1.777666, 2.477606",\
+ "1.056509, 1.246695, 1.466977, 1.828001, 2.527421",\
+ "1.134180, 1.324303, 1.544337, 1.904875, 2.603319",\
+ "1.343298, 1.533349, 1.753099, 2.112983, 2.810072",\
+ "1.896648, 2.086668, 2.306295, 2.665835, 3.362187");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.150008, 0.150411, 0.151856, 0.156196, 0.165595",\
+ "0.237385, 0.237630, 0.238497, 0.240747, 0.245517",\
+ "0.400536, 0.400554, 0.400616, 0.401188, 0.402541",\
+ "0.873945, 0.873960, 0.874011, 0.874290, 0.874930",\
+ "2.149610, 2.149610, 2.149610, 2.149694, 2.149902",\
+ "0.150008, 0.150411, 0.151856, 0.156196, 0.165595",\
+ "0.237385, 0.237630, 0.238497, 0.240747, 0.245517",\
+ "0.400536, 0.400554, 0.400616, 0.401188, 0.402541",\
+ "0.873945, 0.873960, 0.874011, 0.874290, 0.874930",\
+ "2.149610, 2.149610, 2.149610, 2.149694, 2.149902",\
+ "0.150011, 0.150411, 0.151856, 0.156196, 0.165595",\
+ "0.237387, 0.237630, 0.238497, 0.240747, 0.245517",\
+ "0.400536, 0.400554, 0.400616, 0.401188, 0.402541",\
+ "0.873945, 0.873960, 0.874011, 0.874290, 0.874930",\
+ "2.149610, 2.149610, 2.149610, 2.149694, 2.149902",\
+ "0.150016, 0.150412, 0.151859, 0.156208, 0.165618",\
+ "0.237390, 0.237631, 0.238499, 0.240753, 0.245528",\
+ "0.400537, 0.400554, 0.400616, 0.401190, 0.402544",\
+ "0.873945, 0.873960, 0.874011, 0.874290, 0.874931",\
+ "2.149610, 2.149610, 2.149610, 2.149695, 2.149903",\
+ "0.150062, 0.150423, 0.151860, 0.156217, 0.165645",\
+ "0.237418, 0.237637, 0.238499, 0.240757, 0.245542",\
+ "0.400539, 0.400554, 0.400616, 0.401192, 0.402548",\
+ "0.873947, 0.873960, 0.874011, 0.874291, 0.874933",\
+ "2.149610, 2.149610, 2.149610, 2.149695, 2.149903");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.321064, 0.601616, 0.902007, 1.417819, 2.447771",\
+ "0.356109, 0.636678, 0.937135, 1.453129, 2.483444",\
+ "0.406657, 0.687216, 0.987647, 1.503613, 2.533873",\
+ "0.536144, 0.816696, 1.117064, 1.632835, 2.662707",\
+ "0.873984, 1.154534, 1.454850, 1.970470, 3.000039",\
+ "0.409514, 0.689233, 0.989723, 1.504534, 2.533705",\
+ "0.444559, 0.724295, 1.024851, 1.539844, 2.569378",\
+ "0.495106, 0.774833, 1.075363, 1.590328, 2.619807",\
+ "0.624593, 0.904313, 1.204779, 1.719550, 2.748641",\
+ "0.962434, 1.242151, 1.542565, 2.057184, 3.085972",\
+ "0.498914, 0.778364, 1.077690, 1.592179, 2.620660",\
+ "0.533960, 0.813427, 1.112818, 1.627489, 2.656333",\
+ "0.584508, 0.863965, 1.163329, 1.677973, 2.706762",\
+ "0.713994, 0.993445, 1.292746, 1.807195, 2.835596",\
+ "1.051835, 1.331282, 1.630532, 2.144830, 3.172927",\
+ "0.562563, 0.844218, 1.141837, 1.656326, 2.684169",\
+ "0.597610, 0.879281, 1.176965, 1.691636, 2.719842",\
+ "0.648158, 0.929819, 1.227477, 1.742120, 2.770271",\
+ "0.777645, 1.059298, 1.356893, 1.871342, 2.899105",\
+ "1.115485, 1.397135, 1.694679, 2.208976, 3.236436",\
+ "0.898997, 1.211173, 1.494183, 2.005997, 3.029625",\
+ "0.934048, 1.246239, 1.529313, 2.041308, 3.065298",\
+ "0.984598, 1.296772, 1.579825, 2.091792, 3.115727",\
+ "1.114083, 1.426250, 1.709239, 2.221013, 3.244561",\
+ "1.451924, 1.764086, 2.047024, 2.558647, 3.581892");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.072029, 0.072117, 0.072944, 0.075681, 0.081131",\
+ "0.105035, 0.105045, 0.105444, 0.106813, 0.109537",\
+ "0.191067, 0.191185, 0.191447, 0.191927, 0.192882",\
+ "0.434550, 0.434688, 0.434688, 0.434688, 0.434688",\
+ "1.072978, 1.072978, 1.073125, 1.073633, 1.074646",\
+ "0.072030, 0.072117, 0.072953, 0.075681, 0.081131",\
+ "0.105035, 0.105045, 0.105449, 0.106813, 0.109537",\
+ "0.191068, 0.191185, 0.191449, 0.191927, 0.192882",\
+ "0.434554, 0.434688, 0.434688, 0.434688, 0.434688",\
+ "1.072978, 1.072978, 1.073126, 1.073633, 1.074646",\
+ "0.072035, 0.072117, 0.072953, 0.075681, 0.081131",\
+ "0.105035, 0.105045, 0.105449, 0.106813, 0.109537",\
+ "0.191071, 0.191187, 0.191449, 0.191927, 0.192882",\
+ "0.434564, 0.434688, 0.434688, 0.434688, 0.434688",\
+ "1.072978, 1.072978, 1.073126, 1.073633, 1.074646",\
+ "0.072040, 0.072118, 0.072953, 0.075685, 0.081131",\
+ "0.105036, 0.105045, 0.105449, 0.106814, 0.109537",\
+ "0.191073, 0.191190, 0.191449, 0.191928, 0.192882",\
+ "0.434574, 0.434688, 0.434688, 0.434688, 0.434688",\
+ "1.072978, 1.072978, 1.073127, 1.073634, 1.074646",\
+ "0.072068, 0.072127, 0.072981, 0.075698, 0.081131",\
+ "0.105040, 0.105046, 0.105463, 0.106821, 0.109537",\
+ "0.191088, 0.191220, 0.191454, 0.191930, 0.192882",\
+ "0.434635, 0.434688, 0.434688, 0.434688, 0.434688",\
+ "1.072978, 1.072978, 1.073132, 1.073636, 1.074646");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[12]_redg_min*/
+
+} /* end of pin tl_o[12] */
+
+pin("tl_o[11]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.154883 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[11];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.480044, 0.757907, 1.049391, 1.544816, 2.535666",\
+ "0.520846, 0.798709, 1.090193, 1.585618, 2.576470",\
+ "0.596179, 0.874043, 1.165526, 1.660950, 2.651799",\
+ "0.851223, 1.129087, 1.420574, 1.916010, 2.906884",\
+ "1.776399, 2.054266, 2.345743, 2.841143, 3.831943",\
+ "0.568493, 0.845495, 1.137043, 1.631531, 2.621600",\
+ "0.609294, 0.886297, 1.177845, 1.672334, 2.662404",\
+ "0.684628, 0.961631, 1.253178, 1.747665, 2.737732",\
+ "0.939672, 1.216675, 1.508226, 2.002726, 2.992818",\
+ "1.864848, 2.141854, 2.433396, 2.927858, 3.917876",\
+ "0.657525, 0.934585, 1.225009, 1.719154, 2.708555",\
+ "0.698327, 0.975387, 1.265811, 1.759956, 2.749359",\
+ "0.773660, 1.050721, 1.341145, 1.835288, 2.824687",\
+ "1.028704, 1.305765, 1.596192, 2.090348, 3.079773",\
+ "1.953881, 2.230944, 2.521362, 3.015481, 4.004831",\
+ "0.720671, 1.000379, 1.289153, 1.783067, 2.772064",\
+ "0.761473, 1.041181, 1.329955, 1.823870, 2.812868",\
+ "0.836807, 1.116515, 1.405289, 1.899202, 2.888196",\
+ "1.091850, 1.371559, 1.660336, 2.154262, 3.143282",\
+ "2.017027, 2.296738, 2.585506, 3.079395, 4.068340",\
+ "1.053915, 1.366570, 1.641292, 2.132528, 3.117520",\
+ "1.094717, 1.407372, 1.682094, 2.173331, 3.158324",\
+ "1.170050, 1.482705, 1.757427, 2.248662, 3.233653",\
+ "1.425094, 1.737749, 2.012475, 2.503723, 3.488738",\
+ "2.350272, 2.662929, 2.937644, 3.428855, 4.413796");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\
+ "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\
+ "2.469653, 2.469654, 2.469654, 2.469654, 2.469654",\
+ "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\
+ "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\
+ "2.469653, 2.469654, 2.469654, 2.469654, 2.469654",\
+ "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\
+ "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\
+ "2.469653, 2.469654, 2.469654, 2.469654, 2.469654",\
+ "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\
+ "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\
+ "2.469654, 2.469654, 2.469654, 2.469654, 2.469654",\
+ "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\
+ "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691575, 0.691577, 0.691578, 0.691578, 0.691578",\
+ "2.469654, 2.469654, 2.469654, 2.469654, 2.469654");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.577593, 0.759063, 0.958904, 1.285183, 1.919119",\
+ "0.619104, 0.800573, 1.000415, 1.326696, 1.960636",\
+ "0.678962, 0.860432, 1.060273, 1.386554, 2.020497",\
+ "0.847206, 1.028676, 1.228518, 1.554798, 2.188738",\
+ "1.428635, 1.610105, 1.809947, 2.136236, 2.770198",\
+ "0.665008, 0.846447, 1.046407, 1.372488, 2.006473",\
+ "0.706519, 0.887958, 1.087918, 1.414001, 2.047990",\
+ "0.766377, 0.947816, 1.147776, 1.473860, 2.107850",\
+ "0.934621, 1.116060, 1.316020, 1.642103, 2.276092",\
+ "1.516050, 1.697490, 1.897449, 2.223541, 2.857552",\
+ "0.745878, 0.926784, 1.126434, 1.452517, 2.086504",\
+ "0.787388, 0.968295, 1.167944, 1.494029, 2.128021",\
+ "0.847246, 1.028153, 1.227803, 1.553888, 2.187881",\
+ "1.015491, 1.196397, 1.396047, 1.722131, 2.356123",\
+ "1.596920, 1.777826, 1.977476, 2.303569, 2.937583",\
+ "0.803511, 0.984332, 1.183978, 1.509762, 2.143152",\
+ "0.845022, 1.025843, 1.225488, 1.551274, 2.184669",\
+ "0.904880, 1.085701, 1.285347, 1.611133, 2.244529",\
+ "1.073124, 1.253945, 1.453591, 1.779376, 2.412771",\
+ "1.654553, 1.835374, 2.035020, 2.360815, 2.994231",\
+ "1.105600, 1.289533, 1.487611, 1.812776, 2.445014",\
+ "1.147110, 1.331044, 1.529122, 1.854289, 2.486530",\
+ "1.206968, 1.390902, 1.588980, 1.914148, 2.546391",\
+ "1.375213, 1.559146, 1.757225, 2.082391, 2.714632",\
+ "1.956642, 2.140575, 2.338654, 2.663829, 3.296093");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\
+ "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\
+ "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\
+ "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\
+ "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\
+ "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\
+ "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\
+ "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\
+ "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\
+ "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\
+ "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\
+ "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\
+ "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\
+ "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\
+ "1.490308, 1.490308, 1.490308, 1.490340, 1.490420");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[11]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.480044, 0.757907, 1.049391, 1.544474, 2.533147",\
+ "0.520846, 0.798709, 1.090193, 1.585276, 2.573951",\
+ "0.596179, 0.874043, 1.165526, 1.660608, 2.649279",\
+ "0.851223, 1.129087, 1.420574, 1.915668, 2.904364",\
+ "1.776399, 2.054266, 2.345743, 2.840801, 3.829424",\
+ "0.568493, 0.845495, 1.137043, 1.631189, 2.619081",\
+ "0.609294, 0.886297, 1.177845, 1.671992, 2.659884",\
+ "0.684628, 0.961631, 1.253178, 1.747323, 2.735213",\
+ "0.939672, 1.216675, 1.508226, 2.002384, 2.990298",\
+ "1.864848, 2.141854, 2.433396, 2.927516, 3.915357",\
+ "0.657525, 0.934585, 1.225009, 1.718833, 2.706036",\
+ "0.698327, 0.975387, 1.265811, 1.759635, 2.746840",\
+ "0.773660, 1.050721, 1.341145, 1.834967, 2.822168",\
+ "1.028704, 1.305765, 1.596192, 2.090027, 3.077253",\
+ "1.953881, 2.230944, 2.521362, 3.015160, 4.002313",\
+ "0.720671, 1.000379, 1.289153, 1.782954, 2.769545",\
+ "0.761473, 1.041181, 1.329955, 1.823757, 2.810349",\
+ "0.836807, 1.116515, 1.405289, 1.899088, 2.885677",\
+ "1.091850, 1.371559, 1.660336, 2.154149, 3.140762",\
+ "2.017027, 2.296738, 2.585506, 3.079281, 4.065822",\
+ "1.053915, 1.366570, 1.641292, 2.132528, 3.115001",\
+ "1.094717, 1.407372, 1.682094, 2.173331, 3.155805",\
+ "1.170050, 1.482705, 1.757427, 2.248662, 3.231133",\
+ "1.425094, 1.737749, 2.012475, 2.503723, 3.486218",\
+ "2.350272, 2.662929, 2.937644, 3.428855, 4.411278");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\
+ "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\
+ "2.469630, 2.469654, 2.469654, 2.469654, 2.469654",\
+ "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\
+ "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\
+ "2.469631, 2.469654, 2.469654, 2.469654, 2.469654",\
+ "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\
+ "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\
+ "2.469633, 2.469654, 2.469654, 2.469654, 2.469654",\
+ "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\
+ "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\
+ "2.469634, 2.469654, 2.469654, 2.469654, 2.469654",\
+ "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\
+ "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\
+ "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\
+ "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\
+ "2.469645, 2.469654, 2.469654, 2.469654, 2.469654");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.577593, 0.758693, 0.958244, 1.284509, 1.918007",\
+ "0.619104, 0.800204, 0.999755, 1.326021, 1.959524",\
+ "0.678962, 0.860062, 1.059613, 1.385880, 2.019384",\
+ "0.847206, 1.028306, 1.227857, 1.554123, 2.187625",\
+ "1.428635, 1.609735, 1.809286, 2.135561, 2.769086",\
+ "0.665008, 0.846012, 1.045525, 1.371814, 2.005360",\
+ "0.706519, 0.887523, 1.087036, 1.413326, 2.046877",\
+ "0.766377, 0.947381, 1.146894, 1.473185, 2.106737",\
+ "0.934621, 1.115625, 1.315138, 1.641428, 2.274979",\
+ "1.516050, 1.697054, 1.896567, 2.222867, 2.856439",\
+ "0.745878, 0.926348, 1.125552, 1.451842, 2.085392",\
+ "0.787388, 0.967859, 1.167063, 1.493355, 2.126909",\
+ "0.847246, 1.027717, 1.226921, 1.553214, 2.186769",\
+ "1.015491, 1.195961, 1.395165, 1.721457, 2.355011",\
+ "1.596920, 1.777390, 1.976594, 2.302895, 2.936471",\
+ "0.803511, 0.984182, 1.183296, 1.509360, 2.142581",\
+ "0.845022, 1.025692, 1.224806, 1.550872, 2.184098",\
+ "0.904880, 1.085551, 1.284665, 1.610731, 2.243959",\
+ "1.073124, 1.253795, 1.452909, 1.778975, 2.412200",\
+ "1.654553, 1.835224, 2.034338, 2.360413, 2.993660",\
+ "1.105600, 1.289533, 1.486960, 1.812607, 2.445014",\
+ "1.147110, 1.331044, 1.528471, 1.854120, 2.486530",\
+ "1.206968, 1.390902, 1.588329, 1.913979, 2.546391",\
+ "1.375213, 1.559146, 1.756574, 2.082222, 2.714632",\
+ "1.956642, 2.140575, 2.338003, 2.663660, 3.296093");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\
+ "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\
+ "1.490306, 1.490306, 1.490306, 1.490338, 1.490419",\
+ "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\
+ "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\
+ "1.490306, 1.490306, 1.490306, 1.490338, 1.490419",\
+ "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\
+ "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\
+ "1.490306, 1.490306, 1.490306, 1.490338, 1.490419",\
+ "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\
+ "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\
+ "1.490306, 1.490306, 1.490306, 1.490339, 1.490419",\
+ "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\
+ "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\
+ "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\
+ "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\
+ "1.490306, 1.490306, 1.490306, 1.490339, 1.490420");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[11]_redg_min*/
+
+} /* end of pin tl_o[11] */
+
+pin("tl_o[10]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.020161 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[10];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.364012, 0.625791, 0.912362, 1.416686, 2.425334",\
+ "0.413794, 0.675738, 0.964329, 1.475067, 2.496546",\
+ "0.489422, 0.751529, 1.041528, 1.556366, 2.586045",\
+ "0.695293, 0.957830, 1.249004, 1.765727, 2.799173",\
+ "1.246075, 1.508922, 1.800327, 2.315899, 3.347043",\
+ "0.451427, 0.713333, 1.000043, 1.503402, 2.511267",\
+ "0.501209, 0.763281, 1.052029, 1.561783, 2.582479",\
+ "0.576836, 0.839074, 1.129242, 1.643082, 2.671978",\
+ "0.782708, 1.045378, 1.336724, 1.852442, 2.885106",\
+ "1.333490, 1.596474, 1.888044, 2.402615, 3.432977",\
+ "0.533466, 0.802315, 1.088010, 1.591024, 2.598222",\
+ "0.583252, 0.852266, 1.139997, 1.649405, 2.669434",\
+ "0.658880, 0.928062, 1.217209, 1.730705, 2.758933",\
+ "0.864753, 1.134376, 1.424692, 1.940065, 2.972061",\
+ "1.415530, 1.685480, 1.976011, 2.490237, 3.519932",\
+ "0.596367, 0.867953, 1.152155, 1.654938, 2.661731",\
+ "0.646156, 0.917908, 1.204143, 1.713319, 2.732943",\
+ "0.721785, 0.993709, 1.281356, 1.794618, 2.822442",\
+ "0.927659, 1.200036, 1.488839, 2.003978, 3.035570",\
+ "1.478432, 1.751152, 2.040158, 2.554151, 3.583441",\
+ "0.928059, 1.232317, 1.504384, 2.004435, 3.007188",\
+ "0.977868, 1.282318, 1.556437, 2.062843, 3.078399",\
+ "1.053501, 1.358177, 1.633692, 2.144160, 3.167898",\
+ "1.259380, 1.564660, 1.841193, 2.353528, 3.381027",\
+ "1.810129, 2.115913, 2.392501, 2.903695, 3.928897");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.177438, 0.178519, 0.189473, 0.223901, 0.292757",\
+ "0.251359, 0.253407, 0.263275, 0.290387, 0.344610",\
+ "0.412697, 0.412697, 0.415313, 0.424472, 0.442790",\
+ "0.885478, 0.885674, 0.886375, 0.887778, 0.890585",\
+ "2.162748, 2.162748, 2.162938, 2.163605, 2.164938",\
+ "0.177438, 0.178526, 0.189583, 0.223901, 0.292757",\
+ "0.251359, 0.253420, 0.263361, 0.290387, 0.344610",\
+ "0.412697, 0.412697, 0.415342, 0.424472, 0.442790",\
+ "0.885478, 0.885676, 0.886379, 0.887778, 0.890585",\
+ "2.162748, 2.162748, 2.162940, 2.163605, 2.164938",\
+ "0.177475, 0.178542, 0.189585, 0.223901, 0.292757",\
+ "0.251427, 0.253451, 0.263362, 0.290387, 0.344610",\
+ "0.412697, 0.412697, 0.415343, 0.424472, 0.442790",\
+ "0.885478, 0.885680, 0.886380, 0.887778, 0.890585",\
+ "2.162748, 2.162748, 2.162940, 2.163605, 2.164938",\
+ "0.177499, 0.178566, 0.189590, 0.223901, 0.292757",\
+ "0.251473, 0.253495, 0.263367, 0.290387, 0.344610",\
+ "0.412697, 0.412697, 0.415344, 0.424472, 0.442790",\
+ "0.885478, 0.885687, 0.886380, 0.887778, 0.890585",\
+ "2.162748, 2.162748, 2.162940, 2.163605, 2.164938",\
+ "0.177651, 0.178840, 0.189940, 0.224044, 0.292757",\
+ "0.251761, 0.254016, 0.263642, 0.290499, 0.344610",\
+ "0.412697, 0.412697, 0.415437, 0.424510, 0.442790",\
+ "0.885478, 0.885760, 0.886394, 0.887784, 0.890585",\
+ "2.162748, 2.162748, 2.162947, 2.163608, 2.164938");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.312852, 0.568984, 0.862555, 1.382336, 2.421899",\
+ "0.348118, 0.610654, 0.902338, 1.419180, 2.452865",\
+ "0.406005, 0.669261, 0.960734, 1.473580, 2.499271",\
+ "0.536962, 0.800144, 1.091137, 1.602535, 2.625331",\
+ "0.874185, 1.136967, 1.427801, 1.940429, 2.965686",\
+ "0.400266, 0.656542, 0.950284, 1.469051, 2.507832",\
+ "0.435533, 0.698205, 0.990058, 1.505895, 2.538798",\
+ "0.493420, 0.756819, 1.048442, 1.560295, 2.585205",\
+ "0.624377, 0.887700, 1.178840, 1.689250, 2.711264",\
+ "0.961600, 1.224520, 1.515508, 2.027145, 3.051620",\
+ "0.481136, 0.745561, 1.038252, 1.556674, 2.594787",\
+ "0.517546, 0.787210, 1.078026, 1.593518, 2.625753",\
+ "0.575445, 0.845837, 1.136409, 1.647918, 2.672160",\
+ "0.706398, 0.976717, 1.266807, 1.776872, 2.798219",\
+ "1.043615, 1.313530, 1.603475, 2.114767, 3.138575",\
+ "0.538770, 0.811253, 1.102400, 1.620588, 2.658296",\
+ "0.580430, 0.852880, 1.142173, 1.657432, 2.689262",\
+ "0.638337, 0.911526, 1.200556, 1.711832, 2.735669",\
+ "0.769288, 1.042406, 1.330954, 1.840786, 2.861728",\
+ "1.106500, 1.379207, 1.667622, 2.178681, 3.202084",\
+ "0.869562, 1.176250, 1.454786, 1.970150, 3.003752",\
+ "0.912016, 1.217620, 1.494529, 2.006981, 3.034719",\
+ "0.969972, 1.276495, 1.552871, 2.061365, 3.081125",\
+ "1.100910, 1.407358, 1.683254, 2.190313, 3.207185",\
+ "1.438092, 1.744035, 2.019935, 2.528213, 3.547540");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.081554, 0.088992, 0.106415, 0.139136, 0.204579",\
+ "0.124645, 0.129773, 0.146146, 0.179503, 0.246217",\
+ "0.203924, 0.205651, 0.213739, 0.234366, 0.275621",\
+ "0.443609, 0.443974, 0.447191, 0.457130, 0.477008",\
+ "1.100873, 1.101320, 1.101850, 1.102085, 1.102555",\
+ "0.081554, 0.089042, 0.106519, 0.139136, 0.204579",\
+ "0.124645, 0.129815, 0.146252, 0.179503, 0.246217",\
+ "0.203924, 0.205665, 0.213805, 0.234366, 0.275621",\
+ "0.443609, 0.443976, 0.447223, 0.457130, 0.477008",\
+ "1.100873, 1.101323, 1.101851, 1.102085, 1.102555",\
+ "0.081568, 0.089158, 0.106521, 0.139136, 0.204579",\
+ "0.124713, 0.129914, 0.146254, 0.179503, 0.246217",\
+ "0.203955, 0.205697, 0.213806, 0.234366, 0.275621",\
+ "0.443622, 0.443982, 0.447223, 0.457130, 0.477008",\
+ "1.100888, 1.101329, 1.101851, 1.102085, 1.102555",\
+ "0.081595, 0.089328, 0.106526, 0.139136, 0.204579",\
+ "0.124759, 0.130058, 0.146259, 0.179503, 0.246217",\
+ "0.203975, 0.205743, 0.213809, 0.234366, 0.275621",\
+ "0.443630, 0.443990, 0.447225, 0.457130, 0.477008",\
+ "1.100898, 1.101339, 1.101851, 1.102085, 1.102555",\
+ "0.082871, 0.091307, 0.106858, 0.139272, 0.204579",\
+ "0.125047, 0.131735, 0.146598, 0.179642, 0.246217",\
+ "0.204103, 0.206281, 0.214019, 0.234452, 0.275621",\
+ "0.443681, 0.444082, 0.447326, 0.457171, 0.477008",\
+ "1.100961, 1.101453, 1.101854, 1.102086, 1.102555");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_2703*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[57]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.350851, 0.591855, 0.864128, 1.320281, 2.232588",\
+ "0.400592, 0.641701, 0.915140, 1.374804, 2.294134",\
+ "0.476229, 0.717426, 0.992120, 1.455680, 2.382801",\
+ "0.682141, 0.923562, 1.199150, 1.664642, 2.595626",\
+ "1.233045, 1.474598, 1.750161, 2.214853, 3.144235",\
+ "0.438261, 0.679403, 0.951654, 1.406996, 2.318522",\
+ "0.488002, 0.729251, 1.002677, 1.461519, 2.380068",\
+ "0.563639, 0.804976, 1.079670, 1.542395, 2.468735",\
+ "0.769551, 1.011115, 1.286705, 1.751357, 2.681560",\
+ "1.320455, 1.562152, 1.837715, 2.301567, 3.230169",\
+ "0.519097, 0.768378, 1.039617, 1.494618, 2.405477",\
+ "0.568838, 0.818228, 1.090640, 1.549141, 2.467023",\
+ "0.644474, 0.893955, 1.167633, 1.630017, 2.555690",\
+ "0.850399, 1.100099, 1.374669, 1.838978, 2.768515",\
+ "1.401325, 1.651139, 1.925678, 2.389189, 3.317124",\
+ "0.576709, 0.834005, 1.103754, 1.558531, 2.468986",\
+ "0.626450, 0.883858, 1.154778, 1.613054, 2.530532",\
+ "0.702087, 0.959588, 1.231772, 1.693930, 2.619199",\
+ "0.908034, 1.165738, 1.438808, 1.902892, 2.832024",\
+ "1.459002, 1.716783, 1.989817, 2.453102, 3.380633",\
+ "0.898537, 1.198301, 1.455491, 1.907824, 2.814442",\
+ "0.948280, 1.248191, 1.506551, 1.962362, 2.875988",\
+ "1.023916, 1.323954, 1.583584, 2.043254, 2.964655",\
+ "1.229826, 1.530187, 1.790640, 2.252224, 3.177480",\
+ "1.780725, 2.081283, 2.341641, 2.802431, 3.726089");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.177532, 0.178920, 0.189751, 0.222197, 0.287089",\
+ "0.251535, 0.254167, 0.264114, 0.288993, 0.338750",\
+ "0.412948, 0.412948, 0.415205, 0.423013, 0.438629",\
+ "0.885646, 0.885671, 0.886007, 0.887039, 0.889103",\
+ "2.163153, 2.163153, 2.163261, 2.163636, 2.164385",\
+ "0.177532, 0.178929, 0.189854, 0.222197, 0.287089",\
+ "0.251535, 0.254184, 0.264193, 0.288993, 0.338750",\
+ "0.412948, 0.412948, 0.415229, 0.423013, 0.438629",\
+ "0.885646, 0.885672, 0.886011, 0.887039, 0.889103",\
+ "2.163153, 2.163153, 2.163263, 2.163636, 2.164385",\
+ "0.177534, 0.178950, 0.189855, 0.222197, 0.287089",\
+ "0.251540, 0.254224, 0.264194, 0.288993, 0.338750",\
+ "0.412948, 0.412948, 0.415230, 0.423013, 0.438629",\
+ "0.885646, 0.885672, 0.886011, 0.887039, 0.889103",\
+ "2.163153, 2.163153, 2.163263, 2.163636, 2.164385",\
+ "0.177539, 0.178981, 0.189861, 0.222197, 0.287089",\
+ "0.251549, 0.254282, 0.264198, 0.288993, 0.338750",\
+ "0.412948, 0.412948, 0.415231, 0.423013, 0.438629",\
+ "0.885646, 0.885673, 0.886011, 0.887039, 0.889103",\
+ "2.163153, 2.163153, 2.163263, 2.163636, 2.164385",\
+ "0.177778, 0.179340, 0.190190, 0.222331, 0.287089",\
+ "0.252003, 0.254964, 0.264451, 0.289096, 0.338750",\
+ "0.412948, 0.412948, 0.415310, 0.423045, 0.438629",\
+ "0.885646, 0.885682, 0.886021, 0.887043, 0.889103",\
+ "2.163153, 2.163153, 2.163266, 2.163637, 2.164385");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.307193, 0.533242, 0.809521, 1.279856, 2.220526",\
+ "0.336644, 0.576689, 0.852349, 1.318694, 2.251385",\
+ "0.393241, 0.634932, 0.911048, 1.376848, 2.308447",\
+ "0.524233, 0.765871, 1.043018, 1.512641, 2.451889",\
+ "0.861499, 1.102901, 1.379688, 1.849255, 2.788391",\
+ "0.394603, 0.620790, 0.897092, 1.366570, 2.306459",\
+ "0.424054, 0.664240, 0.939907, 1.405409, 2.337319",\
+ "0.480651, 0.722487, 0.998605, 1.463562, 2.394381",\
+ "0.611643, 0.853426, 1.130586, 1.599356, 2.537823",\
+ "0.948909, 1.190453, 1.467256, 1.935970, 2.874325",\
+ "0.475519, 0.709763, 0.985056, 1.454192, 2.393414",\
+ "0.504970, 0.753222, 1.027871, 1.493031, 2.424274",\
+ "0.561503, 0.811478, 1.086568, 1.551184, 2.481336",\
+ "0.692478, 0.942415, 1.218550, 1.686978, 2.624778",\
+ "1.029784, 1.279438, 1.555220, 2.023592, 2.961280",\
+ "0.533285, 0.775388, 1.049196, 1.518106, 2.456923",\
+ "0.562736, 0.818858, 1.092010, 1.556944, 2.487783",\
+ "0.619148, 0.877127, 1.150707, 1.615098, 2.544845",\
+ "0.750090, 1.008062, 1.282690, 1.750891, 2.688287",\
+ "1.087471, 1.345078, 1.619360, 2.087505, 3.024789",\
+ "0.839984, 1.139662, 1.401077, 1.867458, 2.802380",\
+ "0.883084, 1.183263, 1.443850, 1.906280, 2.833239",\
+ "0.940909, 1.241684, 1.502542, 1.964431, 2.890301",\
+ "1.071899, 1.372601, 1.634564, 2.100240, 3.033743",\
+ "1.409163, 1.709532, 1.971233, 2.436854, 3.370245");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.079414, 0.084257, 0.099312, 0.127519, 0.183935",\
+ "0.124385, 0.127318, 0.139681, 0.167608, 0.223461",\
+ "0.203732, 0.204755, 0.210826, 0.226691, 0.258421",\
+ "0.443641, 0.444109, 0.446299, 0.452176, 0.463930",\
+ "1.100911, 1.101486, 1.102125, 1.102253, 1.102511",\
+ "0.079414, 0.084301, 0.099401, 0.127519, 0.183935",\
+ "0.124385, 0.127346, 0.139769, 0.167608, 0.223461",\
+ "0.203732, 0.204765, 0.210876, 0.226691, 0.258421",\
+ "0.443641, 0.444112, 0.446317, 0.452176, 0.463930",\
+ "1.100911, 1.101489, 1.102125, 1.102253, 1.102511",\
+ "0.079415, 0.084402, 0.099402, 0.127519, 0.183935",\
+ "0.124385, 0.127408, 0.139771, 0.167608, 0.223461",\
+ "0.203732, 0.204786, 0.210877, 0.226691, 0.258421",\
+ "0.443642, 0.444120, 0.446318, 0.452176, 0.463930",\
+ "1.100913, 1.101498, 1.102125, 1.102253, 1.102511",\
+ "0.079417, 0.084547, 0.099407, 0.127519, 0.183935",\
+ "0.124385, 0.127499, 0.139776, 0.167608, 0.223461",\
+ "0.203733, 0.204818, 0.210879, 0.226691, 0.258421",\
+ "0.443643, 0.444130, 0.446319, 0.452176, 0.463930",\
+ "1.100914, 1.101511, 1.102125, 1.102253, 1.102511",\
+ "0.079511, 0.086252, 0.099693, 0.127636, 0.183935",\
+ "0.124397, 0.128559, 0.140059, 0.167723, 0.223461",\
+ "0.203741, 0.205184, 0.211040, 0.226757, 0.258421",\
+ "0.443724, 0.444251, 0.446378, 0.452200, 0.463930",\
+ "1.101013, 1.101659, 1.102126, 1.102254, 1.102511");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_2585*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[58]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.331228, 0.527324, 0.786001, 1.224167, 2.100501",\
+ "0.382369, 0.578501, 0.836813, 1.274472, 2.149791",\
+ "0.460186, 0.652490, 0.910342, 1.347469, 2.221725",\
+ "0.669327, 0.853217, 1.110120, 1.545833, 2.417260",\
+ "1.222502, 1.402990, 1.654377, 2.088484, 2.956696",\
+ "0.418630, 0.614835, 0.873467, 1.310880, 2.186435",\
+ "0.469770, 0.666010, 0.924278, 1.361185, 2.235725",\
+ "0.547588, 0.739998, 0.997805, 1.434183, 2.307659",\
+ "0.756729, 0.940720, 1.197578, 1.632546, 2.503194",\
+ "1.309904, 1.490380, 1.741831, 2.175197, 3.042630",\
+ "0.499484, 0.703690, 0.961427, 1.398501, 2.273390",\
+ "0.550625, 0.754862, 1.012238, 1.448806, 2.322680",\
+ "0.628442, 0.828845, 1.085765, 1.521803, 2.394614",\
+ "0.837583, 1.029560, 1.285538, 1.720167, 2.590149",\
+ "1.390758, 1.574844, 1.829791, 2.262817, 3.129585",\
+ "0.557217, 0.769141, 1.025562, 1.462414, 2.336899",\
+ "0.608358, 0.820308, 1.076372, 1.512718, 2.386189",\
+ "0.686176, 0.894284, 1.149899, 1.585716, 2.458123",\
+ "0.895316, 1.094988, 1.349672, 1.784079, 2.653658",\
+ "1.448492, 1.640260, 1.893925, 2.326730, 3.193094",\
+ "0.860852, 1.131485, 1.377112, 1.811626, 2.682355",\
+ "0.911997, 1.182598, 1.427917, 1.861928, 2.731645",\
+ "0.989815, 1.256499, 1.501439, 1.934923, 2.803579",\
+ "1.198957, 1.457069, 1.701197, 2.133281, 2.999114",\
+ "1.752135, 2.002200, 2.245434, 2.675925, 3.538550");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.247574, 0.253107, 0.265836, 0.292486, 0.345785",\
+ "0.313887, 0.316030, 0.323178, 0.341027, 0.376725",\
+ "0.435753, 0.438083, 0.443130, 0.454659, 0.477717",\
+ "0.887719, 0.887719, 0.887745, 0.887834, 0.888012",\
+ "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\
+ "0.247574, 0.253139, 0.265920, 0.292486, 0.345785",\
+ "0.313887, 0.316042, 0.323234, 0.341027, 0.376725",\
+ "0.435753, 0.438094, 0.443166, 0.454659, 0.477717",\
+ "0.887719, 0.887719, 0.887746, 0.887834, 0.888012",\
+ "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\
+ "0.247586, 0.253211, 0.265921, 0.292486, 0.345785",\
+ "0.313891, 0.316070, 0.323235, 0.341027, 0.376725",\
+ "0.435759, 0.438118, 0.443167, 0.454659, 0.477717",\
+ "0.887719, 0.887719, 0.887746, 0.887834, 0.888012",\
+ "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\
+ "0.247608, 0.253315, 0.265926, 0.292486, 0.345785",\
+ "0.313900, 0.316110, 0.323238, 0.341027, 0.376725",\
+ "0.435772, 0.438153, 0.443169, 0.454659, 0.477717",\
+ "0.887719, 0.887719, 0.887746, 0.887834, 0.888012",\
+ "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\
+ "0.247822, 0.254533, 0.266196, 0.292595, 0.345785",\
+ "0.313983, 0.316581, 0.323419, 0.341101, 0.376725",\
+ "0.435894, 0.438565, 0.443286, 0.454706, 0.477717",\
+ "0.887719, 0.887719, 0.887747, 0.887835, 0.888012",\
+ "2.165595, 2.165595, 2.165595, 2.165595, 2.165595");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.262843, 0.528242, 0.786656, 1.223429, 2.096977",\
+ "0.297860, 0.563309, 0.821748, 1.258583, 2.132253",\
+ "0.348398, 0.613835, 0.872220, 1.308997, 2.182551",\
+ "0.477894, 0.743312, 1.001644, 1.438265, 2.311508",\
+ "0.815730, 1.081145, 1.339443, 1.775996, 2.649102",\
+ "0.351215, 0.615754, 0.874118, 1.310142, 2.182910",\
+ "0.386233, 0.650820, 0.909210, 1.345296, 2.218187",\
+ "0.436771, 0.701346, 0.959682, 1.395710, 2.268485",\
+ "0.566267, 0.830823, 1.089105, 1.524978, 2.397442",\
+ "0.904103, 1.168656, 1.426904, 1.862709, 2.735036",\
+ "0.441060, 0.704611, 0.962078, 1.397763, 2.269865",\
+ "0.476082, 0.739678, 0.997171, 1.432917, 2.305142",\
+ "0.526621, 0.790203, 1.047642, 1.483330, 2.355440",\
+ "0.656116, 0.919680, 1.177066, 1.612599, 2.484397",\
+ "0.993953, 1.257513, 1.514864, 1.950330, 2.821991",\
+ "0.505420, 0.770065, 1.026212, 1.461676, 2.333374",\
+ "0.540445, 0.805132, 1.061305, 1.496829, 2.368651",\
+ "0.590985, 0.855656, 1.111776, 1.547243, 2.418949",\
+ "0.720478, 0.985133, 1.241200, 1.676511, 2.547906",\
+ "1.058316, 1.322965, 1.578998, 2.014242, 2.885500",\
+ "0.846347, 1.132446, 1.377748, 1.810882, 2.678830",\
+ "0.881392, 1.167515, 1.412841, 1.846036, 2.714107",\
+ "0.931940, 1.218030, 1.463312, 1.896449, 2.764405",\
+ "1.061427, 1.347505, 1.592734, 2.025717, 2.893362",\
+ "1.399268, 1.685334, 1.930532, 2.363448, 3.230956");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.080673, 0.084979, 0.095299, 0.118135, 0.163806",\
+ "0.121691, 0.122534, 0.126916, 0.139600, 0.164968",\
+ "0.211121, 0.211686, 0.213778, 0.219384, 0.230596",\
+ "0.447776, 0.448001, 0.448970, 0.451208, 0.455684",\
+ "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\
+ "0.080714, 0.085004, 0.095371, 0.118135, 0.163806",\
+ "0.121700, 0.122539, 0.126956, 0.139600, 0.164968",\
+ "0.211127, 0.211689, 0.213796, 0.219384, 0.230596",\
+ "0.447776, 0.448003, 0.448977, 0.451208, 0.455684",\
+ "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\
+ "0.080840, 0.085056, 0.095372, 0.118135, 0.163806",\
+ "0.121728, 0.122548, 0.126957, 0.139600, 0.164968",\
+ "0.211145, 0.211695, 0.213796, 0.219384, 0.230596",\
+ "0.447776, 0.448008, 0.448977, 0.451208, 0.455684",\
+ "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\
+ "0.080962, 0.085133, 0.095376, 0.118135, 0.163806",\
+ "0.121755, 0.122562, 0.126959, 0.139600, 0.164968",\
+ "0.211163, 0.211704, 0.213797, 0.219384, 0.230596",\
+ "0.447776, 0.448014, 0.448977, 0.451208, 0.455684",\
+ "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\
+ "0.081743, 0.086029, 0.095607, 0.118229, 0.163806",\
+ "0.121930, 0.122722, 0.127087, 0.139652, 0.164968",\
+ "0.211276, 0.211814, 0.213854, 0.219407, 0.230596",\
+ "0.447776, 0.448092, 0.449000, 0.451217, 0.455684",\
+ "1.099948, 1.099948, 1.099948, 1.099948, 1.099948");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_2468*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[62]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.515413, 0.691814, 0.891527, 1.333812, 2.218381",\
+ "0.561951, 0.738352, 0.942909, 1.385434, 2.270486",\
+ "0.647617, 0.824017, 1.044838, 1.487336, 2.372332",\
+ "0.870983, 1.047384, 1.281978, 1.724502, 2.609548",\
+ "1.434991, 1.611392, 1.857594, 2.300149, 3.185259",\
+ "0.602824, 0.779196, 0.979010, 1.420527, 2.304315",\
+ "0.649362, 0.825734, 1.030392, 1.472149, 2.356420",\
+ "0.735027, 0.911399, 1.132321, 1.574051, 2.458265",\
+ "0.958394, 1.134766, 1.369462, 1.811216, 2.695482",\
+ "1.522402, 1.698774, 1.945078, 2.386864, 3.271193",\
+ "0.683657, 0.859530, 1.066972, 1.508148, 2.391270",\
+ "0.730195, 0.906068, 1.118354, 1.559771, 2.443375",\
+ "0.815861, 0.991733, 1.220284, 1.661672, 2.545220",\
+ "1.039228, 1.215100, 1.457424, 1.898838, 2.782437",\
+ "1.603236, 1.779108, 2.033040, 2.474486, 3.358148",\
+ "0.741263, 0.917078, 1.131107, 1.572062, 2.454779",\
+ "0.787801, 0.963617, 1.182490, 1.623684, 2.506884",\
+ "0.873466, 1.049282, 1.284419, 1.725586, 2.608729",\
+ "1.096833, 1.272649, 1.521559, 1.962752, 2.845946",\
+ "1.660841, 1.842122, 2.097176, 2.538399, 3.421657",\
+ "1.043307, 1.237664, 1.482704, 1.921298, 2.800235",\
+ "1.089845, 1.288972, 1.534089, 1.972921, 2.852340",\
+ "1.175511, 1.390910, 1.636018, 2.074823, 2.954185",\
+ "1.398878, 1.628042, 1.873158, 2.311989, 3.191402",\
+ "1.962886, 2.203649, 2.448775, 2.887636, 3.767113");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\
+ "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\
+ "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\
+ "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\
+ "2.162771, 2.162771, 2.162787, 2.162833, 2.162925",\
+ "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\
+ "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\
+ "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\
+ "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\
+ "2.162771, 2.162771, 2.162787, 2.162833, 2.162925",\
+ "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\
+ "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\
+ "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\
+ "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\
+ "2.162771, 2.162771, 2.162787, 2.162833, 2.162925",\
+ "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\
+ "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\
+ "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\
+ "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\
+ "2.162771, 2.162772, 2.162787, 2.162833, 2.162925",\
+ "0.052252, 0.052255, 0.052266, 0.052296, 0.052356",\
+ "0.174387, 0.174384, 0.174376, 0.174356, 0.174314",\
+ "0.378093, 0.378087, 0.378069, 0.378020, 0.377921",\
+ "0.885671, 0.885670, 0.885660, 0.885629, 0.885567",\
+ "2.162771, 2.162773, 2.162788, 2.162833, 2.162925");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.453647, 0.675841, 0.933001, 1.375582, 2.260746",\
+ "0.507082, 0.698390, 0.955556, 1.398159, 2.283364",\
+ "0.567945, 0.744346, 0.996821, 1.439418, 2.324611",\
+ "0.702647, 0.879047, 1.118872, 1.561445, 2.446589",\
+ "1.049097, 1.225497, 1.451556, 1.894090, 2.779158",\
+ "0.541058, 0.763317, 1.020484, 1.462297, 2.346680",\
+ "0.594493, 0.785866, 1.043040, 1.484873, 2.369298",\
+ "0.655356, 0.831728, 1.084305, 1.526132, 2.410545",\
+ "0.790057, 0.966429, 1.206356, 1.648159, 2.532523",\
+ "1.136508, 1.312880, 1.539039, 1.980805, 2.865092",\
+ "0.621891, 0.852130, 1.108447, 1.549919, 2.433635",\
+ "0.675327, 0.874679, 1.131002, 1.572495, 2.456253",\
+ "0.736189, 0.915945, 1.172267, 1.613754, 2.497500",\
+ "0.870891, 1.046763, 1.294318, 1.735781, 2.619478",\
+ "1.217341, 1.393214, 1.627002, 2.068427, 2.952047",\
+ "0.679497, 0.917520, 1.172582, 1.613832, 2.497144",\
+ "0.732932, 0.940069, 1.195138, 1.636409, 2.519762",\
+ "0.793795, 0.981336, 1.236402, 1.677668, 2.561009",\
+ "0.928497, 1.104312, 1.358454, 1.799695, 2.682987",\
+ "1.274947, 1.450762, 1.691137, 2.132340, 3.015556",\
+ "0.991265, 1.279047, 1.524182, 1.963070, 2.842600",\
+ "1.034976, 1.301596, 1.546737, 1.985646, 2.865218",\
+ "1.095839, 1.342862, 1.588002, 2.026905, 2.906465",\
+ "1.230541, 1.464921, 1.710053, 2.148932, 3.028443",\
+ "1.576991, 1.797617, 2.042736, 2.481577, 3.361012");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.060254, 0.060270, 0.060353, 0.060563, 0.060983",\
+ "0.114289, 0.114310, 0.114425, 0.114712, 0.115288",\
+ "0.199967, 0.199967, 0.200091, 0.200354, 0.200879",\
+ "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\
+ "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\
+ "0.060254, 0.060270, 0.060354, 0.060563, 0.060983",\
+ "0.114289, 0.114310, 0.114425, 0.114712, 0.115288",\
+ "0.199967, 0.199967, 0.200092, 0.200354, 0.200879",\
+ "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\
+ "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\
+ "0.060254, 0.060270, 0.060354, 0.060563, 0.060983",\
+ "0.114289, 0.114311, 0.114426, 0.114712, 0.115288",\
+ "0.199967, 0.199987, 0.200092, 0.200354, 0.200879",\
+ "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\
+ "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\
+ "0.060254, 0.060271, 0.060354, 0.060563, 0.060983",\
+ "0.114289, 0.114311, 0.114426, 0.114712, 0.115288",\
+ "0.199967, 0.199988, 0.200092, 0.200354, 0.200879",\
+ "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\
+ "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\
+ "0.060254, 0.060277, 0.060356, 0.060564, 0.060983",\
+ "0.114289, 0.114319, 0.114428, 0.114714, 0.115288",\
+ "0.199967, 0.199995, 0.200095, 0.200355, 0.200879",\
+ "0.445518, 0.445521, 0.445532, 0.445561, 0.445620",\
+ "1.101422, 1.101420, 1.101415, 1.101402, 1.101375");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[10]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.248860, 0.467650, 0.646178, 0.935763, 1.497723",\
+ "0.314404, 0.533194, 0.711724, 1.001313, 1.563285",\
+ "0.400894, 0.619685, 0.798218, 1.087823, 1.649829",\
+ "0.616887, 0.835682, 1.014242, 1.303952, 1.866190",\
+ "1.171447, 1.390243, 1.568813, 1.858561, 2.420885",\
+ "0.337260, 0.554969, 0.733459, 1.023068, 1.585076",\
+ "0.402804, 0.620513, 0.799004, 1.088619, 1.650638",\
+ "0.489294, 0.707003, 0.885499, 1.175128, 1.737183",\
+ "0.705288, 0.923001, 1.101523, 1.391257, 1.953543",\
+ "1.259847, 1.477562, 1.656094, 1.945866, 2.508239",\
+ "0.426158, 0.635305, 0.813486, 1.103096, 1.665108",\
+ "0.491702, 0.700850, 0.879031, 1.168647, 1.730670",\
+ "0.578191, 0.787340, 0.965526, 1.255157, 1.817214",\
+ "0.794185, 1.003338, 1.181550, 1.471285, 2.033575",\
+ "1.348745, 1.557899, 1.736121, 2.025895, 2.588270",\
+ "0.489181, 0.693123, 0.871180, 1.160527, 1.722125",\
+ "0.554726, 0.758668, 0.936725, 1.226078, 1.787687",\
+ "0.641215, 0.845158, 1.023220, 1.312588, 1.874232",\
+ "0.857210, 1.061156, 1.239244, 1.528717, 2.090593",\
+ "1.411770, 1.615717, 1.793815, 2.083326, 2.645288",\
+ "0.817972, 0.998369, 1.174837, 1.463701, 2.024349",\
+ "0.883517, 1.063914, 1.240382, 1.529251, 2.089911",\
+ "0.970006, 1.150404, 1.326877, 1.615761, 2.176455",\
+ "1.186001, 1.366402, 1.542901, 1.831890, 2.392817",\
+ "1.740560, 1.920963, 2.097472, 2.386500, 2.947513");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.135658, 0.135697, 0.135954, 0.136439, 0.137406",\
+ "0.233360, 0.233354, 0.233337, 0.233240, 0.233017",\
+ "0.397359, 0.397363, 0.397387, 0.397480, 0.397688",\
+ "0.873501, 0.873500, 0.873498, 0.873489, 0.873469",\
+ "2.140095, 2.140101, 2.140141, 2.140298, 2.140647",\
+ "0.135659, 0.135697, 0.135954, 0.136439, 0.137406",\
+ "0.233360, 0.233354, 0.233337, 0.233240, 0.233017",\
+ "0.397359, 0.397363, 0.397387, 0.397480, 0.397688",\
+ "0.873501, 0.873500, 0.873498, 0.873489, 0.873469",\
+ "2.140095, 2.140101, 2.140141, 2.140298, 2.140647",\
+ "0.135662, 0.135697, 0.135954, 0.136439, 0.137406",\
+ "0.233359, 0.233354, 0.233337, 0.233240, 0.233017",\
+ "0.397360, 0.397363, 0.397387, 0.397480, 0.397688",\
+ "0.873500, 0.873500, 0.873498, 0.873489, 0.873469",\
+ "2.140095, 2.140101, 2.140141, 2.140298, 2.140647",\
+ "0.135665, 0.135698, 0.135954, 0.136441, 0.137409",\
+ "0.233359, 0.233354, 0.233337, 0.233240, 0.233016",\
+ "0.397360, 0.397363, 0.397387, 0.397480, 0.397689",\
+ "0.873500, 0.873500, 0.873498, 0.873489, 0.873469",\
+ "2.140096, 2.140101, 2.140141, 2.140298, 2.140648",\
+ "0.135663, 0.135699, 0.135954, 0.136442, 0.137411",\
+ "0.233359, 0.233354, 0.233337, 0.233240, 0.233016",\
+ "0.397360, 0.397363, 0.397387, 0.397480, 0.397689",\
+ "0.873500, 0.873500, 0.873498, 0.873489, 0.873469",\
+ "2.140096, 2.140101, 2.140141, 2.140299, 2.140649");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.265941, 0.478440, 0.661761, 0.953483, 1.516542",\
+ "0.295974, 0.514750, 0.693420, 0.983435, 1.546355",\
+ "0.342294, 0.561099, 0.739726, 1.029692, 1.592503",\
+ "0.466491, 0.685293, 0.863899, 1.153787, 1.716424",\
+ "0.798732, 1.017531, 1.196112, 1.485904, 2.048326",\
+ "0.354342, 0.565759, 0.749042, 1.040788, 1.603895",\
+ "0.384375, 0.602069, 0.780701, 1.070740, 1.633708",\
+ "0.430695, 0.648418, 0.827006, 1.116997, 1.679856",\
+ "0.554892, 0.772612, 0.951180, 1.241092, 1.803777",\
+ "0.887133, 1.104849, 1.283393, 1.573209, 2.135679",\
+ "0.443241, 0.646096, 0.829069, 1.120816, 1.683927",\
+ "0.473273, 0.682406, 0.860728, 1.150768, 1.713740",\
+ "0.519593, 0.728755, 0.907033, 1.197025, 1.759888",\
+ "0.643790, 0.852948, 1.031207, 1.321121, 1.883808",\
+ "0.976031, 1.185186, 1.363420, 1.653237, 2.215711",\
+ "0.506266, 0.703926, 0.886774, 1.178249, 1.740947",\
+ "0.536299, 0.740226, 0.918422, 1.208200, 1.770759",\
+ "0.582618, 0.786573, 0.964728, 1.254457, 1.816907",\
+ "0.706815, 0.910767, 1.088901, 1.378552, 1.940827",\
+ "1.039055, 1.243004, 1.421114, 1.710669, 2.272729",\
+ "0.825950, 1.009259, 1.190433, 1.481423, 2.043174",\
+ "0.864615, 1.045486, 1.222079, 1.511375, 2.072986",\
+ "0.911409, 1.091819, 1.268385, 1.557632, 2.119133",\
+ "1.035605, 1.216013, 1.392558, 1.681726, 2.243053",\
+ "1.367846, 1.548250, 1.724771, 2.013843, 2.574954");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\
+ "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\
+ "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\
+ "0.432608, 0.432613, 0.432644, 0.432766, 0.433037",\
+ "1.067886, 1.067868, 1.067749, 1.067290, 1.066264",\
+ "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\
+ "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\
+ "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\
+ "0.432608, 0.432613, 0.432644, 0.432766, 0.433037",\
+ "1.067886, 1.067868, 1.067749, 1.067290, 1.066264",\
+ "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\
+ "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\
+ "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\
+ "0.432609, 0.432613, 0.432644, 0.432766, 0.433037",\
+ "1.067884, 1.067868, 1.067749, 1.067290, 1.066264",\
+ "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\
+ "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\
+ "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\
+ "0.432609, 0.432613, 0.432644, 0.432766, 0.433038",\
+ "1.067883, 1.067868, 1.067749, 1.067289, 1.066261",\
+ "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\
+ "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\
+ "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\
+ "0.432609, 0.432613, 0.432644, 0.432766, 0.433039",\
+ "1.067883, 1.067867, 1.067749, 1.067287, 1.066258");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min_2547*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[57]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.230530, 0.471836, 0.662565, 0.965687, 1.550670",\
+ "0.296073, 0.537386, 0.728118, 1.031247, 1.616246",\
+ "0.382561, 0.623892, 0.814634, 1.117786, 1.702834",\
+ "0.598538, 0.839995, 1.030804, 1.334111, 1.919485",\
+ "1.153092, 1.394595, 1.585429, 1.888794, 2.474288",\
+ "0.318838, 0.559155, 0.749846, 1.052992, 1.638023",\
+ "0.384382, 0.624704, 0.815398, 1.118552, 1.703600",\
+ "0.470869, 0.711210, 0.901915, 1.205091, 1.790187",\
+ "0.686851, 0.927314, 1.118085, 1.421416, 2.006838",\
+ "1.241406, 1.481914, 1.672710, 1.976099, 2.561641",\
+ "0.407830, 0.639488, 0.829873, 1.133020, 1.718055",\
+ "0.473374, 0.705038, 0.895425, 1.198581, 1.783631",\
+ "0.559863, 0.791544, 0.981942, 1.285120, 1.870219",\
+ "0.775854, 1.007647, 1.198112, 1.501445, 2.086870",\
+ "1.330413, 1.562247, 1.752737, 2.056127, 2.641673",\
+ "0.471102, 0.697352, 0.887595, 1.190479, 1.775129",\
+ "0.536647, 0.762902, 0.953148, 1.256040, 1.840706",\
+ "0.623137, 0.849408, 1.039664, 1.342579, 1.927294",\
+ "0.839138, 1.065512, 1.255835, 1.558905, 2.143945",\
+ "1.393700, 1.620112, 1.810460, 2.113587, 2.698749",\
+ "0.805138, 1.002911, 1.191255, 1.493676, 2.077422",\
+ "0.870685, 1.068460, 1.256808, 1.559237, 2.142998",\
+ "0.957184, 1.154967, 1.343324, 1.645776, 2.229586",\
+ "1.173243, 1.371074, 1.559495, 1.862102, 2.446239",\
+ "1.727827, 1.925676, 2.114120, 2.416785, 3.001042");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.135507, 0.136708, 0.137351, 0.137726, 0.138133",\
+ "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\
+ "0.397345, 0.397457, 0.397518, 0.397656, 0.397948",\
+ "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\
+ "2.140071, 2.140260, 2.140361, 2.140594, 2.141085",\
+ "0.135540, 0.136708, 0.137351, 0.137726, 0.138133",\
+ "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\
+ "0.397348, 0.397457, 0.397518, 0.397656, 0.397948",\
+ "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\
+ "2.140076, 2.140260, 2.140361, 2.140594, 2.141085",\
+ "0.135636, 0.136708, 0.137351, 0.137726, 0.138133",\
+ "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\
+ "0.397357, 0.397457, 0.397518, 0.397656, 0.397948",\
+ "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\
+ "2.140091, 2.140260, 2.140361, 2.140594, 2.141085",\
+ "0.135724, 0.136712, 0.137353, 0.137727, 0.138134",\
+ "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\
+ "0.397365, 0.397458, 0.397518, 0.397657, 0.397949",\
+ "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\
+ "2.140105, 2.140261, 2.140362, 2.140594, 2.141086",\
+ "0.136284, 0.136744, 0.137353, 0.137727, 0.138135",\
+ "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\
+ "0.397418, 0.397461, 0.397518, 0.397657, 0.397950",\
+ "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\
+ "2.140193, 2.140266, 2.140362, 2.140595, 2.141087");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.247536, 0.465909, 0.655111, 0.957872, 1.542809",\
+ "0.277578, 0.504859, 0.694166, 0.997452, 1.583596",\
+ "0.323906, 0.557991, 0.747485, 1.050859, 1.637228",\
+ "0.448115, 0.688036, 0.877811, 1.181150, 1.767445",\
+ "0.780371, 1.021927, 1.212790, 1.516219, 2.101851",\
+ "0.335860, 0.553227, 0.742392, 1.045177, 1.630162",\
+ "0.365901, 0.592177, 0.781447, 1.084757, 1.670949",\
+ "0.412227, 0.645309, 0.834766, 1.138164, 1.724581",\
+ "0.536433, 0.775355, 0.965092, 1.268455, 1.854799",\
+ "0.868686, 1.109246, 1.300071, 1.603524, 2.189205",\
+ "0.424900, 0.633561, 0.822419, 1.125205, 1.710194",\
+ "0.454934, 0.672511, 0.861474, 1.164785, 1.750981",\
+ "0.501255, 0.725643, 0.914793, 1.218192, 1.804613",\
+ "0.625454, 0.855688, 1.045119, 1.348483, 1.934830",\
+ "0.957698, 1.189579, 1.380097, 1.683553, 2.269236",\
+ "0.488215, 0.691382, 0.880139, 1.182665, 1.767268",\
+ "0.518244, 0.730333, 0.919194, 1.222246, 1.808058",\
+ "0.564561, 0.783480, 0.972513, 1.275653, 1.861690",\
+ "0.688753, 0.913547, 1.102839, 1.405944, 1.991908",\
+ "1.020988, 1.247444, 1.437820, 1.741013, 2.326312",\
+ "0.816645, 0.996641, 1.183799, 1.485862, 2.069561",\
+ "0.852522, 1.035597, 1.222854, 1.525444, 2.110354",\
+ "0.898812, 1.088847, 1.276173, 1.578852, 2.163987",\
+ "1.022959, 1.219069, 1.406500, 1.709143, 2.294204",\
+ "1.355140, 1.553009, 1.741481, 2.044211, 2.628607");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.067590, 0.067613, 0.067625, 0.067653, 0.067711",\
+ "0.104758, 0.104770, 0.104776, 0.104791, 0.104822",\
+ "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\
+ "0.432590, 0.432736, 0.432815, 0.432996, 0.433377",\
+ "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\
+ "0.067591, 0.067613, 0.067625, 0.067653, 0.067711",\
+ "0.104758, 0.104770, 0.104776, 0.104791, 0.104822",\
+ "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\
+ "0.432594, 0.432736, 0.432815, 0.432996, 0.433377",\
+ "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\
+ "0.067593, 0.067613, 0.067625, 0.067653, 0.067711",\
+ "0.104759, 0.104770, 0.104776, 0.104791, 0.104822",\
+ "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\
+ "0.432605, 0.432736, 0.432815, 0.432996, 0.433377",\
+ "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\
+ "0.067594, 0.067613, 0.067625, 0.067653, 0.067711",\
+ "0.104760, 0.104770, 0.104776, 0.104791, 0.104822",\
+ "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\
+ "0.432616, 0.432737, 0.432815, 0.432996, 0.433378",\
+ "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\
+ "0.067593, 0.067614, 0.067625, 0.067653, 0.067711",\
+ "0.104766, 0.104770, 0.104776, 0.104791, 0.104822",\
+ "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\
+ "0.432685, 0.432741, 0.432815, 0.432997, 0.433379",\
+ "1.063080, 1.063080, 1.063080, 1.063080, 1.063080");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[58]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.244473, 0.505671, 0.697935, 0.998174, 1.574785",\
+ "0.300254, 0.556634, 0.748837, 1.048824, 1.624875",\
+ "0.376032, 0.633972, 0.826223, 1.125987, 1.701451",\
+ "0.578226, 0.841738, 1.034663, 1.334155, 1.908979",\
+ "1.122810, 1.385726, 1.587938, 1.887184, 2.461388",\
+ "0.332840, 0.592988, 0.785216, 1.085479, 1.662138",\
+ "0.388618, 0.643952, 0.836118, 1.136129, 1.712228",\
+ "0.464390, 0.721290, 0.913504, 1.213292, 1.788804",\
+ "0.666574, 0.929242, 1.121944, 1.421460, 1.996333",\
+ "1.211151, 1.473226, 1.675219, 1.974489, 2.548742",\
+ "0.422672, 0.673316, 0.865243, 1.165508, 1.742170",\
+ "0.478441, 0.724280, 0.916145, 1.216158, 1.792260",\
+ "0.554191, 0.801618, 0.993531, 1.293321, 1.868836",\
+ "0.756345, 1.010087, 1.201971, 1.501488, 2.076365",\
+ "1.300900, 1.562060, 1.755246, 2.054518, 2.628773",\
+ "0.487019, 0.731152, 0.922971, 1.222957, 1.799227",\
+ "0.542778, 0.782116, 0.973873, 1.273607, 1.849315",\
+ "0.618509, 0.859454, 1.051260, 1.350769, 1.925890",\
+ "0.820633, 1.067923, 1.259699, 1.558936, 2.133417",\
+ "1.365167, 1.621171, 1.812974, 2.111965, 2.685824",\
+ "0.827863, 1.036490, 1.226631, 1.526145, 2.101498",\
+ "0.883564, 1.087454, 1.277533, 1.576794, 2.151585",\
+ "0.959165, 1.164792, 1.354919, 1.653956, 2.228158",\
+ "1.161104, 1.373262, 1.563359, 1.862122, 2.435683",\
+ "1.705499, 1.926510, 2.116634, 2.415150, 2.988089");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.150101, 0.150101, 0.150101, 0.151542, 0.155060",\
+ "0.237371, 0.237371, 0.237371, 0.238239, 0.240357",\
+ "0.400588, 0.400588, 0.400588, 0.400716, 0.401031",\
+ "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\
+ "2.136242, 2.138523, 2.138971, 2.139329, 2.139329",\
+ "0.150101, 0.150101, 0.150101, 0.151542, 0.155060",\
+ "0.237371, 0.237371, 0.237371, 0.238239, 0.240357",\
+ "0.400588, 0.400588, 0.400588, 0.400716, 0.401031",\
+ "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\
+ "2.136282, 2.138528, 2.138971, 2.139329, 2.139329",\
+ "0.150101, 0.150101, 0.150101, 0.151542, 0.155060",\
+ "0.237371, 0.237371, 0.237371, 0.238239, 0.240357",\
+ "0.400588, 0.400588, 0.400588, 0.400716, 0.401031",\
+ "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\
+ "2.136409, 2.138540, 2.138971, 2.139329, 2.139329",\
+ "0.150101, 0.150101, 0.150101, 0.151547, 0.155068",\
+ "0.237371, 0.237371, 0.237371, 0.238242, 0.240362",\
+ "0.400588, 0.400588, 0.400588, 0.400717, 0.401031",\
+ "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\
+ "2.136531, 2.137884, 2.138973, 2.139329, 2.139329",\
+ "0.150101, 0.150101, 0.150101, 0.151550, 0.155079",\
+ "0.237371, 0.237371, 0.237371, 0.238244, 0.240369",\
+ "0.400588, 0.400588, 0.400588, 0.400717, 0.401032",\
+ "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\
+ "2.137311, 2.137926, 2.138974, 2.139329, 2.139329");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.243871, 0.423733, 0.615818, 0.915684, 1.491530",\
+ "0.279786, 0.459520, 0.651316, 0.952173, 1.530680",\
+ "0.334281, 0.513862, 0.705260, 1.006477, 1.586195",\
+ "0.467807, 0.647364, 0.838496, 1.139651, 1.719442",\
+ "0.802494, 0.981904, 1.172736, 1.473617, 2.052986",\
+ "0.331272, 0.511050, 0.703099, 1.002989, 1.578883",\
+ "0.367188, 0.546838, 0.738597, 1.039478, 1.618034",\
+ "0.421683, 0.601180, 0.792541, 1.093782, 1.673548",\
+ "0.555208, 0.734681, 0.925777, 1.226957, 1.806796",\
+ "0.889896, 1.069221, 1.260017, 1.560922, 2.140339",\
+ "0.412125, 0.591378, 0.783126, 1.083017, 1.658915",\
+ "0.448040, 0.627166, 0.818624, 1.119507, 1.698066",\
+ "0.502534, 0.681508, 0.872568, 1.173811, 1.753580",\
+ "0.636060, 0.815010, 1.005804, 1.306985, 1.886827",\
+ "0.970746, 1.149549, 1.340044, 1.640951, 2.220371",\
+ "0.469856, 0.649214, 0.840854, 1.140466, 1.715970",\
+ "0.505769, 0.685001, 0.876351, 1.176959, 1.755127",\
+ "0.560262, 0.739342, 0.930294, 1.231264, 1.810644",\
+ "0.693787, 0.872844, 1.063529, 1.364439, 1.943892",\
+ "1.028472, 1.207383, 1.397769, 1.698404, 2.277434",\
+ "0.773472, 0.954547, 1.144514, 1.443653, 2.018239",\
+ "0.809371, 0.990331, 1.180011, 1.480149, 2.057404",\
+ "0.863847, 1.044668, 1.233954, 1.534456, 2.112924",\
+ "0.997369, 1.178169, 1.367189, 1.667630, 2.246172",\
+ "1.332038, 1.512705, 1.701428, 2.001595, 2.579713");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.071845, 0.072069, 0.072077, 0.072933, 0.075022",\
+ "0.105010, 0.105036, 0.105037, 0.105381, 0.106219",\
+ "0.190967, 0.191120, 0.191139, 0.191258, 0.191538",\
+ "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\
+ "1.063081, 1.064842, 1.065453, 1.065643, 1.065643",\
+ "0.071845, 0.072069, 0.072077, 0.072933, 0.075022",\
+ "0.105010, 0.105036, 0.105037, 0.105381, 0.106219",\
+ "0.190967, 0.191120, 0.191139, 0.191258, 0.191538",\
+ "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\
+ "1.063081, 1.064842, 1.065453, 1.065643, 1.065643",\
+ "0.071847, 0.072069, 0.072077, 0.072933, 0.075022",\
+ "0.105010, 0.105036, 0.105037, 0.105381, 0.106219",\
+ "0.190967, 0.191120, 0.191139, 0.191258, 0.191538",\
+ "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\
+ "1.063091, 1.064842, 1.065453, 1.065643, 1.065643",\
+ "0.071849, 0.072070, 0.072077, 0.072936, 0.075027",\
+ "0.105011, 0.105036, 0.105037, 0.105382, 0.106221",\
+ "0.190969, 0.191121, 0.191139, 0.191259, 0.191539",\
+ "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\
+ "1.063112, 1.064849, 1.065454, 1.065643, 1.065643",\
+ "0.071874, 0.072076, 0.072077, 0.072938, 0.075034",\
+ "0.105014, 0.105037, 0.105037, 0.105382, 0.106223",\
+ "0.190986, 0.191125, 0.191139, 0.191259, 0.191540",\
+ "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\
+ "1.063308, 1.064895, 1.065455, 1.065643, 1.065643");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min_2493*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[62]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.377825, 0.634223, 0.868848, 1.157402, 1.717689",\
+ "0.428298, 0.684702, 0.914931, 1.203491, 1.763791",\
+ "0.530100, 0.786503, 1.000029, 1.288605, 1.848942",\
+ "0.768016, 1.024419, 1.221793, 1.510395, 2.070789",\
+ "1.340420, 1.596824, 1.783889, 2.072520, 2.632977",\
+ "0.466032, 0.721699, 0.956129, 1.244707, 1.805043",\
+ "0.516506, 0.772177, 1.002212, 1.290796, 1.851145",\
+ "0.618307, 0.873978, 1.087310, 1.375910, 1.936295",\
+ "0.856223, 1.111895, 1.309074, 1.597700, 2.158142",\
+ "1.428628, 1.684300, 1.871170, 2.159825, 2.720331",\
+ "0.554696, 0.810512, 1.036155, 1.324735, 1.885074",\
+ "0.605170, 0.860990, 1.082239, 1.370825, 1.931176",\
+ "0.706971, 0.962791, 1.167337, 1.455939, 2.016327",\
+ "0.944887, 1.200708, 1.389101, 1.677728, 2.238174",\
+ "1.517292, 1.773113, 1.951197, 2.239853, 2.800363",\
+ "0.617648, 0.875902, 1.093848, 1.382165, 1.942089",\
+ "0.668122, 0.926381, 1.139932, 1.428254, 1.988191",\
+ "0.769923, 1.028182, 1.225029, 1.513368, 2.073342",\
+ "1.007839, 1.266098, 1.446793, 1.735158, 2.295189",\
+ "1.580244, 1.831772, 2.008889, 2.297283, 2.857378",\
+ "0.949653, 1.221972, 1.397504, 1.685336, 2.244309",\
+ "1.000127, 1.268054, 1.443587, 1.731425, 2.290411",\
+ "1.101928, 1.353148, 1.528685, 1.816540, 2.375562",\
+ "1.339844, 1.574905, 1.750449, 2.038329, 2.597409",\
+ "1.912249, 2.136994, 2.312545, 2.600454, 3.159598");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.041017, 0.041026, 0.041033, 0.041274, 0.041853",\
+ "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\
+ "0.374819, 0.374818, 0.374816, 0.374779, 0.374688",\
+ "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\
+ "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\
+ "0.041017, 0.041026, 0.041033, 0.041274, 0.041853",\
+ "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\
+ "0.374819, 0.374818, 0.374816, 0.374779, 0.374688",\
+ "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\
+ "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\
+ "0.041017, 0.041026, 0.041033, 0.041274, 0.041853",\
+ "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\
+ "0.374819, 0.374817, 0.374816, 0.374779, 0.374688",\
+ "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\
+ "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\
+ "0.041017, 0.041026, 0.041033, 0.041275, 0.041855",\
+ "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\
+ "0.374819, 0.374817, 0.374816, 0.374778, 0.374688",\
+ "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\
+ "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\
+ "0.041017, 0.041017, 0.041033, 0.041276, 0.041856",\
+ "0.147926, 0.147926, 0.147928, 0.147959, 0.148034",\
+ "0.374819, 0.374819, 0.374816, 0.374778, 0.374687",\
+ "0.869171, 0.869171, 0.869169, 0.869164, 0.869153",\
+ "2.137120, 2.137120, 2.137119, 2.137116, 2.137110");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.419293, 0.629601, 0.807148, 1.095622, 1.655731",\
+ "0.441693, 0.683002, 0.860568, 1.149118, 1.709396",\
+ "0.483042, 0.739446, 0.921121, 1.209730, 1.770140",\
+ "0.605027, 0.861431, 1.052488, 1.341094, 1.901499",\
+ "0.936548, 1.192951, 1.389827, 1.678402, 2.238737",\
+ "0.507500, 0.716919, 0.894429, 1.182927, 1.743084",\
+ "0.529901, 0.770320, 0.947849, 1.236423, 1.796750",\
+ "0.571249, 0.826922, 1.008402, 1.297035, 1.857493",\
+ "0.693234, 0.948907, 1.139769, 1.428399, 1.988852",\
+ "1.024755, 1.280427, 1.477108, 1.765707, 2.326091",\
+ "0.596164, 0.797253, 0.974456, 1.262956, 1.823116",\
+ "0.618565, 0.850654, 1.027876, 1.316451, 1.876781",\
+ "0.659913, 0.911193, 1.088429, 1.377064, 1.937525",\
+ "0.781898, 1.037719, 1.219796, 1.508428, 2.068884",\
+ "1.113419, 1.369240, 1.557135, 1.845736, 2.406122",\
+ "0.659116, 0.855070, 1.032148, 1.320385, 1.880130",\
+ "0.681517, 0.908471, 1.085568, 1.373881, 1.933796",\
+ "0.722865, 0.969009, 1.146121, 1.434493, 1.994540",\
+ "0.844850, 1.100376, 1.277488, 1.565857, 2.125898",\
+ "1.176371, 1.434630, 1.614827, 1.903165, 2.463137",\
+ "0.981445, 1.160292, 1.335804, 1.623556, 2.182350",\
+ "1.013522, 1.213693, 1.389224, 1.677052, 2.236016",\
+ "1.054870, 1.274231, 1.449777, 1.737664, 2.296760",\
+ "1.176855, 1.405599, 1.581144, 1.869029, 2.428119",\
+ "1.508376, 1.742946, 1.918483, 2.206336, 2.765357");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\
+ "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\
+ "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\
+ "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\
+ "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\
+ "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\
+ "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\
+ "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\
+ "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\
+ "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\
+ "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\
+ "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\
+ "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\
+ "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\
+ "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\
+ "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\
+ "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\
+ "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\
+ "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\
+ "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\
+ "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\
+ "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\
+ "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\
+ "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\
+ "1.064249, 1.064249, 1.064249, 1.064249, 1.064250");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min_2445*/
+
+} /* end of pin tl_o[10] */
+
+pin("tl_o[9]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.020161 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[9];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.555398, 0.819461, 1.110403, 1.621818, 2.644648",\
+ "0.601280, 0.865373, 1.156432, 1.668153, 2.691596",\
+ "0.685796, 0.949972, 1.241371, 1.753978, 2.779193",\
+ "0.906647, 1.170955, 1.462887, 1.976883, 3.004877",\
+ "1.467724, 1.732179, 2.024706, 2.540253, 3.571347",\
+ "0.642813, 0.907018, 1.198106, 1.708533, 2.730582",\
+ "0.688695, 0.952929, 1.244136, 1.754869, 2.777529",\
+ "0.773211, 1.037529, 1.329078, 1.840694, 2.865127",\
+ "0.994062, 1.258512, 1.550598, 2.063599, 3.090810",\
+ "1.555139, 1.819737, 2.112422, 2.626968, 3.657281",\
+ "0.724929, 0.996034, 1.286073, 1.796156, 2.817537",\
+ "0.770813, 1.041946, 1.332103, 1.842491, 2.864485",\
+ "0.855331, 1.126547, 1.417045, 1.928316, 2.952082",\
+ "1.076186, 1.347532, 1.638566, 2.151221, 3.177765",\
+ "1.637269, 1.908760, 2.200390, 2.714591, 3.744236",\
+ "0.787882, 1.061721, 1.350220, 1.860070, 2.881046",\
+ "0.833767, 1.107633, 1.396250, 1.906405, 2.927994",\
+ "0.918287, 1.192236, 1.481192, 1.992230, 3.015591",\
+ "1.139145, 1.413225, 1.702713, 2.215135, 3.241274",\
+ "1.700230, 1.974455, 2.264537, 2.778505, 3.807745",\
+ "1.119904, 1.426659, 1.702520, 2.209597, 3.226502",\
+ "1.165792, 1.472579, 1.748554, 2.255933, 3.273450",\
+ "1.250324, 1.557204, 1.833505, 2.341762, 3.361047",\
+ "1.471201, 1.778225, 2.055039, 2.564673, 3.586730",\
+ "2.032307, 2.339493, 2.616879, 3.128049, 4.153201");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.051283, 0.051370, 0.051891, 0.053400, 0.056417",\
+ "0.173670, 0.173612, 0.173379, 0.172770, 0.171552",\
+ "0.376316, 0.376196, 0.375752, 0.374635, 0.372400",\
+ "0.881676, 0.881670, 0.881647, 0.881590, 0.881477",\
+ "2.159552, 2.159744, 2.159980, 2.159997, 2.160033",\
+ "0.051283, 0.051370, 0.051896, 0.053400, 0.056417",\
+ "0.173670, 0.173612, 0.173377, 0.172770, 0.171552",\
+ "0.376316, 0.376195, 0.375749, 0.374635, 0.372400",\
+ "0.881676, 0.881670, 0.881647, 0.881590, 0.881477",\
+ "2.159552, 2.159745, 2.159980, 2.159997, 2.160033",\
+ "0.051286, 0.051372, 0.051896, 0.053400, 0.056417",\
+ "0.173668, 0.173611, 0.173377, 0.172770, 0.171552",\
+ "0.376312, 0.376193, 0.375749, 0.374635, 0.372400",\
+ "0.881675, 0.881670, 0.881647, 0.881590, 0.881477",\
+ "2.159557, 2.159749, 2.159980, 2.159997, 2.160033",\
+ "0.051287, 0.051374, 0.051896, 0.053400, 0.056417",\
+ "0.173667, 0.173610, 0.173377, 0.172770, 0.171552",\
+ "0.376309, 0.376191, 0.375749, 0.374635, 0.372400",\
+ "0.881675, 0.881670, 0.881647, 0.881590, 0.881477",\
+ "2.159559, 2.159753, 2.159980, 2.159997, 2.160033",\
+ "0.051300, 0.051396, 0.051912, 0.053406, 0.056417",\
+ "0.173659, 0.173595, 0.173370, 0.172767, 0.171552",\
+ "0.376292, 0.376160, 0.375737, 0.374630, 0.372400",\
+ "0.881675, 0.881668, 0.881646, 0.881590, 0.881477",\
+ "2.159577, 2.159810, 2.159980, 2.159997, 2.160033");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.496610, 0.760268, 1.051112, 1.563657, 2.588749",\
+ "0.547372, 0.811417, 1.102287, 1.613514, 2.635968",\
+ "0.606137, 0.870487, 1.162590, 1.677032, 2.705914",\
+ "0.741015, 1.005340, 1.297339, 1.811510, 2.839852",\
+ "1.088533, 1.352702, 1.644074, 2.156609, 3.181679",\
+ "0.584025, 0.847822, 1.138818, 1.650373, 2.674682",\
+ "0.634786, 0.898974, 1.189989, 1.700229, 2.721902",\
+ "0.693552, 0.958046, 1.250303, 1.763747, 2.791848",\
+ "0.828430, 1.092898, 1.385051, 1.898225, 2.925786",\
+ "1.175948, 1.440259, 1.731781, 2.243324, 3.267613",\
+ "0.666128, 0.936832, 1.226786, 1.737995, 2.761637",\
+ "0.716902, 0.987989, 1.277956, 1.787852, 2.808857",\
+ "0.775678, 1.047066, 1.338270, 1.851369, 2.878803",\
+ "0.910556, 1.181918, 1.473018, 1.985848, 3.012741",\
+ "1.258068, 1.529277, 1.819748, 2.330947, 3.354568",\
+ "0.729072, 1.002510, 1.290933, 1.801909, 2.825146",\
+ "0.779855, 1.053676, 1.342103, 1.851766, 2.872366",\
+ "0.838638, 1.112759, 1.402418, 1.915283, 2.942312",\
+ "0.973515, 1.247610, 1.537165, 2.049762, 3.076250",\
+ "1.321024, 1.594967, 1.883895, 2.394861, 3.418077",\
+ "1.061036, 1.367345, 1.643245, 2.151441, 3.170603",\
+ "1.111874, 1.418610, 1.694402, 2.201292, 3.217822",\
+ "1.170700, 1.477770, 1.754749, 2.264823, 3.287768",\
+ "1.305573, 1.612615, 1.889494, 2.399300, 3.421706",\
+ "1.653060, 1.959932, 2.236207, 2.744392, 3.763533");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.056276, 0.056853, 0.059193, 0.065291, 0.077487",\
+ "0.108806, 0.109601, 0.112826, 0.121230, 0.138038",\
+ "0.194961, 0.195687, 0.198632, 0.206304, 0.221649",\
+ "0.444958, 0.445039, 0.445369, 0.446227, 0.447944",\
+ "1.101681, 1.101643, 1.101491, 1.101094, 1.100299",\
+ "0.056276, 0.056857, 0.059213, 0.065291, 0.077487",\
+ "0.108806, 0.109606, 0.112853, 0.121230, 0.138038",\
+ "0.194961, 0.195692, 0.198656, 0.206304, 0.221649",\
+ "0.444958, 0.445040, 0.445371, 0.446227, 0.447944",\
+ "1.101681, 1.101643, 1.101490, 1.101094, 1.100299",\
+ "0.056295, 0.056865, 0.059213, 0.065291, 0.077487",\
+ "0.108832, 0.109618, 0.112853, 0.121230, 0.138038",\
+ "0.194985, 0.195703, 0.198657, 0.206304, 0.221649",\
+ "0.444961, 0.445041, 0.445371, 0.446227, 0.447944",\
+ "1.101680, 1.101642, 1.101490, 1.101094, 1.100299",\
+ "0.056308, 0.056878, 0.059214, 0.065291, 0.077487",\
+ "0.108850, 0.109635, 0.112855, 0.121230, 0.138038",\
+ "0.195002, 0.195719, 0.198658, 0.206304, 0.221649",\
+ "0.444963, 0.445043, 0.445372, 0.446227, 0.447944",\
+ "1.101679, 1.101642, 1.101490, 1.101094, 1.100299",\
+ "0.056389, 0.057025, 0.059276, 0.065316, 0.077487",\
+ "0.108962, 0.109837, 0.112940, 0.121265, 0.138038",\
+ "0.195104, 0.195903, 0.198736, 0.206336, 0.221649",\
+ "0.444974, 0.445063, 0.445380, 0.446231, 0.447944",\
+ "1.101673, 1.101632, 1.101485, 1.101092, 1.100299");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_2686*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[57]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.541885, 0.785038, 1.063858, 1.534026, 2.474360",\
+ "0.587770, 0.830960, 1.109901, 1.580353, 2.521255",\
+ "0.672293, 0.915590, 1.194882, 1.666154, 2.608697",\
+ "0.893156, 1.136622, 1.416462, 1.889021, 2.834138",\
+ "1.454245, 1.697900, 1.978353, 2.452348, 3.400338",\
+ "0.629296, 0.872602, 1.151428, 1.620740, 2.560294",\
+ "0.675181, 0.918525, 1.197473, 1.667067, 2.607188",\
+ "0.759703, 1.003156, 1.282456, 1.752868, 2.694631",\
+ "0.980566, 1.224188, 1.504040, 1.975736, 2.920072",\
+ "1.541656, 1.785468, 2.065936, 2.539063, 3.486272",\
+ "0.710134, 0.961613, 1.239393, 1.708362, 2.647249",\
+ "0.756019, 1.007537, 1.285437, 1.754689, 2.694144",\
+ "0.840542, 1.092169, 1.370420, 1.840490, 2.781586",\
+ "1.061405, 1.313204, 1.592004, 2.063357, 3.007027",\
+ "1.622495, 1.874487, 2.153900, 2.626685, 3.573227",\
+ "0.767752, 1.027293, 1.303532, 1.772275, 2.710758",\
+ "0.813637, 1.073217, 1.349577, 1.818602, 2.757653",\
+ "0.898160, 1.157852, 1.434560, 1.904403, 2.845095",\
+ "1.119024, 1.378891, 1.656144, 2.127271, 3.070536",\
+ "1.680114, 1.940177, 2.218040, 2.690598, 3.636736",\
+ "1.089850, 1.392206, 1.655411, 2.121627, 3.056214",\
+ "1.135741, 1.438139, 1.701459, 2.167955, 3.103108",\
+ "1.220283, 1.522803, 1.786450, 2.253759, 3.190551",\
+ "1.441176, 1.743885, 2.008048, 2.476632, 3.415992",\
+ "2.002299, 2.305221, 2.569958, 3.039965, 3.982192");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.051290, 0.051402, 0.051767, 0.052622, 0.054331",\
+ "0.173665, 0.173591, 0.173350, 0.172786, 0.171658",\
+ "0.376306, 0.376151, 0.375734, 0.374850, 0.373082",\
+ "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\
+ "2.159523, 2.159652, 2.159853, 2.159909, 2.160021",\
+ "0.051290, 0.051403, 0.051770, 0.052622, 0.054331",\
+ "0.173665, 0.173591, 0.173349, 0.172786, 0.171658",\
+ "0.376306, 0.376150, 0.375732, 0.374850, 0.373082",\
+ "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\
+ "2.159523, 2.159653, 2.159854, 2.159909, 2.160021",\
+ "0.051290, 0.051405, 0.051770, 0.052622, 0.054331",\
+ "0.173665, 0.173589, 0.173349, 0.172786, 0.171658",\
+ "0.376305, 0.376148, 0.375732, 0.374850, 0.373082",\
+ "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\
+ "2.159523, 2.159656, 2.159854, 2.159909, 2.160021",\
+ "0.051291, 0.051407, 0.051770, 0.052622, 0.054331",\
+ "0.173665, 0.173588, 0.173348, 0.172786, 0.171658",\
+ "0.376305, 0.376145, 0.375731, 0.374850, 0.373082",\
+ "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\
+ "2.159523, 2.159659, 2.159854, 2.159909, 2.160021",\
+ "0.051310, 0.051436, 0.051779, 0.052625, 0.054331",\
+ "0.173652, 0.173569, 0.173343, 0.172784, 0.171658",\
+ "0.376278, 0.376105, 0.375722, 0.374847, 0.373082",\
+ "0.881676, 0.881672, 0.881655, 0.881609, 0.881516",\
+ "2.159524, 2.159705, 2.159854, 2.159909, 2.160021");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.483063, 0.725694, 1.002821, 1.469018, 2.401413",\
+ "0.533858, 0.776987, 1.055733, 1.525727, 2.465714",\
+ "0.592650, 0.836170, 1.116186, 1.589157, 2.535098",\
+ "0.727526, 0.971013, 1.250922, 1.723643, 2.669083",\
+ "1.075030, 1.318318, 1.597581, 2.068786, 3.011196",\
+ "0.570473, 0.813255, 1.090379, 1.555733, 2.487347",\
+ "0.621268, 0.864551, 1.143303, 1.612441, 2.551647",\
+ "0.680060, 0.923737, 1.203766, 1.675871, 2.621032",\
+ "0.814936, 1.058579, 1.338501, 1.810357, 2.755017",\
+ "1.162440, 1.405883, 1.685155, 2.155501, 3.097130",\
+ "0.651310, 0.902258, 1.178342, 1.643355, 2.574302",\
+ "0.702106, 0.953562, 1.231267, 1.700063, 2.638602",\
+ "0.760899, 1.012754, 1.291730, 1.763493, 2.707987",\
+ "0.895775, 1.147596, 1.426465, 1.897979, 2.841972",\
+ "1.243279, 1.494897, 1.773119, 2.243123, 3.184085",\
+ "0.708926, 0.967926, 1.242482, 1.707268, 2.637811",\
+ "0.759724, 1.019241, 1.295407, 1.763976, 2.702111",\
+ "0.818518, 1.078441, 1.355870, 1.827407, 2.771496",\
+ "0.953394, 1.213283, 1.490605, 1.961892, 2.905481",\
+ "1.300897, 1.560579, 1.837259, 2.307036, 3.247594",\
+ "1.030934, 1.332704, 1.594321, 2.056603, 2.983267",\
+ "1.081818, 1.384149, 1.647285, 2.113327, 3.047567",\
+ "1.140679, 1.443450, 1.707778, 2.176770, 3.116952",\
+ "1.275549, 1.578283, 1.842510, 2.311255, 3.250937",\
+ "1.623018, 1.925528, 2.189149, 2.656392, 3.593050");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.056326, 0.057067, 0.059477, 0.065125, 0.076422",\
+ "0.108874, 0.109896, 0.113217, 0.121001, 0.136571",\
+ "0.195024, 0.195957, 0.198988, 0.206096, 0.220310",\
+ "0.444965, 0.445069, 0.445409, 0.446204, 0.447794",\
+ "1.101678, 1.101629, 1.101472, 1.101105, 1.100369",\
+ "0.056326, 0.057072, 0.059494, 0.065125, 0.076422",\
+ "0.108874, 0.109903, 0.113241, 0.121001, 0.136571",\
+ "0.195024, 0.195963, 0.199011, 0.206096, 0.220310",\
+ "0.444965, 0.445070, 0.445411, 0.446204, 0.447794",\
+ "1.101678, 1.101629, 1.101471, 1.101105, 1.100369",\
+ "0.056327, 0.057083, 0.059495, 0.065125, 0.076422",\
+ "0.108876, 0.109918, 0.113242, 0.121001, 0.136571",\
+ "0.195025, 0.195977, 0.199011, 0.206096, 0.220310",\
+ "0.444965, 0.445072, 0.445411, 0.446204, 0.447794",\
+ "1.101678, 1.101628, 1.101471, 1.101105, 1.100369",\
+ "0.056330, 0.057100, 0.059496, 0.065125, 0.076422",\
+ "0.108880, 0.109941, 0.113243, 0.121001, 0.136571",\
+ "0.195029, 0.195998, 0.199012, 0.206096, 0.220310",\
+ "0.444966, 0.445074, 0.445411, 0.446204, 0.447794",\
+ "1.101677, 1.101627, 1.101471, 1.101105, 1.100369",\
+ "0.056457, 0.057292, 0.059553, 0.065149, 0.076422",\
+ "0.109056, 0.110205, 0.113322, 0.121034, 0.136571",\
+ "0.195189, 0.196239, 0.199085, 0.206125, 0.220310",\
+ "0.444983, 0.445101, 0.445419, 0.446207, 0.447794",\
+ "1.101669, 1.101615, 1.101467, 1.101103, 1.100369");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_2573*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[58]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.565069, 0.820938, 1.075987, 1.513367, 2.388129",\
+ "0.610722, 0.866590, 1.121640, 1.559020, 2.433781",\
+ "0.694431, 0.950300, 1.205350, 1.642730, 2.517491",\
+ "0.914051, 1.169920, 1.424969, 1.862349, 2.737111",\
+ "1.473307, 1.729176, 1.984225, 2.421606, 3.296367",\
+ "0.653273, 0.908426, 1.163451, 1.600080, 2.474062",\
+ "0.698926, 0.954078, 1.209104, 1.645733, 2.519715",\
+ "0.782636, 1.037788, 1.292814, 1.729443, 2.603425",\
+ "1.002255, 1.257407, 1.512433, 1.949062, 2.823044",\
+ "1.561512, 1.816664, 2.071689, 2.508319, 3.382300",\
+ "0.742600, 0.997231, 1.251411, 1.687701, 2.561017",\
+ "0.788253, 1.042883, 1.297064, 1.733354, 2.606670",\
+ "0.871963, 1.126593, 1.380774, 1.817064, 2.690380",\
+ "1.091582, 1.346213, 1.600393, 2.036683, 2.909999",\
+ "1.650838, 1.905469, 2.159649, 2.595939, 3.469255",\
+ "0.806459, 1.062609, 1.315545, 1.751614, 2.624526",\
+ "0.852112, 1.108261, 1.361198, 1.797266, 2.670179",\
+ "0.935822, 1.191971, 1.444908, 1.880976, 2.753889",\
+ "1.155441, 1.411591, 1.664527, 2.100595, 2.973508",\
+ "1.714697, 1.970847, 2.223783, 2.659852, 3.532764",\
+ "1.144184, 1.424102, 1.667087, 2.100822, 2.969982",\
+ "1.189837, 1.469755, 1.712740, 2.146475, 3.015635",\
+ "1.273547, 1.553465, 1.796450, 2.230185, 3.099345",\
+ "1.493166, 1.773084, 2.016069, 2.449804, 3.318964",\
+ "2.052423, 2.332341, 2.575326, 3.009061, 3.878221");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\
+ "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\
+ "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\
+ "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\
+ "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\
+ "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\
+ "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\
+ "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\
+ "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\
+ "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\
+ "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\
+ "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\
+ "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\
+ "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\
+ "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\
+ "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\
+ "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\
+ "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\
+ "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\
+ "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\
+ "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\
+ "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\
+ "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\
+ "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\
+ "2.159378, 2.159378, 2.159378, 2.159378, 2.159378");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.512229, 0.768098, 1.023147, 1.460527, 2.335289",\
+ "0.557112, 0.812981, 1.068030, 1.505411, 2.380172",\
+ "0.613030, 0.868899, 1.123949, 1.561329, 2.436090",\
+ "0.748455, 1.004324, 1.259373, 1.696754, 2.571515",\
+ "1.097588, 1.353456, 1.608506, 2.045886, 2.920648",\
+ "0.600433, 0.855585, 1.110611, 1.547240, 2.421222",\
+ "0.645316, 0.900469, 1.155494, 1.592124, 2.466105",\
+ "0.701235, 0.956387, 1.211413, 1.648042, 2.522024",\
+ "0.836659, 1.091812, 1.346837, 1.783467, 2.657449",\
+ "1.185792, 1.440944, 1.695970, 2.132599, 3.006581",\
+ "0.689760, 0.944391, 1.198571, 1.634861, 2.508177",\
+ "0.734643, 0.989274, 1.243454, 1.679744, 2.553061",\
+ "0.790562, 1.045192, 1.299373, 1.735663, 2.608979",\
+ "0.925986, 1.180617, 1.434798, 1.871087, 2.744404",\
+ "1.275119, 1.529750, 1.783930, 2.220220, 3.093536",\
+ "0.753619, 1.009769, 1.262705, 1.698774, 2.571686",\
+ "0.798502, 1.054652, 1.307589, 1.743657, 2.616570",\
+ "0.854421, 1.110570, 1.363507, 1.799575, 2.672488",\
+ "0.989845, 1.245995, 1.498932, 1.935000, 2.807913",\
+ "1.338978, 1.595128, 1.848064, 2.284132, 3.157045",\
+ "1.091344, 1.371262, 1.614247, 2.047982, 2.917142",\
+ "1.136228, 1.416146, 1.659131, 2.092866, 2.962026",\
+ "1.192146, 1.472064, 1.715049, 2.148784, 3.017944",\
+ "1.327571, 1.607489, 1.850474, 2.284209, 3.153369",\
+ "1.676703, 1.956621, 2.199606, 2.633341, 3.502501");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\
+ "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\
+ "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\
+ "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\
+ "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\
+ "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\
+ "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\
+ "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\
+ "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\
+ "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\
+ "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\
+ "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\
+ "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\
+ "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\
+ "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\
+ "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\
+ "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\
+ "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\
+ "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\
+ "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\
+ "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\
+ "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\
+ "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\
+ "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\
+ "1.101794, 1.101794, 1.101794, 1.101794, 1.101794");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_2453*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[62]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.405081, 0.661604, 0.918671, 1.360881, 2.245302",\
+ "0.455961, 0.712483, 0.969534, 1.411694, 2.296014",\
+ "0.533364, 0.789887, 1.046932, 1.489066, 2.373335",\
+ "0.741794, 0.998316, 1.255349, 1.697444, 2.581634",\
+ "1.295078, 1.551601, 1.808624, 2.250684, 3.134805",\
+ "0.493291, 0.749080, 1.006153, 1.447596, 2.331236",\
+ "0.544172, 0.799959, 1.057016, 1.498409, 2.381948",\
+ "0.621574, 0.877363, 1.134413, 1.575781, 2.459269",\
+ "0.830004, 1.085792, 1.342831, 1.784158, 2.667568",\
+ "1.383288, 1.639076, 1.896105, 2.337399, 3.220738",\
+ "0.581963, 0.837893, 1.094115, 1.535218, 2.418191",\
+ "0.632844, 0.888772, 1.144979, 1.586031, 2.468903",\
+ "0.710247, 0.966176, 1.222376, 1.663403, 2.546224",\
+ "0.918676, 1.174605, 1.430793, 1.871780, 2.754523",\
+ "1.471960, 1.727890, 1.984068, 2.425020, 3.307693",\
+ "0.644923, 0.903284, 1.158251, 1.599131, 2.481700",\
+ "0.695804, 0.954163, 1.209114, 1.649944, 2.532412",\
+ "0.773206, 1.031567, 1.286511, 1.727316, 2.609733",\
+ "0.981636, 1.239996, 1.494928, 1.935694, 2.818032",\
+ "1.534920, 1.793280, 2.048203, 2.488934, 3.371202",\
+ "0.976976, 1.264814, 1.509846, 1.948367, 2.827156",\
+ "1.027857, 1.315693, 1.560709, 1.999180, 2.877868",\
+ "1.105260, 1.393097, 1.638106, 2.076551, 2.955189",\
+ "1.313689, 1.601526, 1.846523, 2.284929, 3.163488",\
+ "1.866973, 2.154810, 2.399797, 2.838169, 3.716659");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.235856, 0.236036, 0.236876, 0.239059, 0.243424",\
+ "0.297458, 0.297578, 0.298135, 0.299584, 0.302483",\
+ "0.424282, 0.424361, 0.424727, 0.425678, 0.427582",\
+ "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\
+ "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\
+ "0.235857, 0.236037, 0.236883, 0.239059, 0.243424",\
+ "0.297459, 0.297578, 0.298140, 0.299584, 0.302483",\
+ "0.424283, 0.424361, 0.424730, 0.425678, 0.427582",\
+ "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\
+ "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\
+ "0.235860, 0.236040, 0.236883, 0.239059, 0.243424",\
+ "0.297461, 0.297581, 0.298140, 0.299584, 0.302483",\
+ "0.424284, 0.424363, 0.424730, 0.425678, 0.427582",\
+ "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\
+ "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\
+ "0.235863, 0.236045, 0.236883, 0.239059, 0.243424",\
+ "0.297463, 0.297583, 0.298140, 0.299584, 0.302483",\
+ "0.424285, 0.424365, 0.424730, 0.425678, 0.427582",\
+ "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\
+ "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\
+ "0.235880, 0.236097, 0.236905, 0.239068, 0.243424",\
+ "0.297474, 0.297618, 0.298155, 0.299590, 0.302483",\
+ "0.424293, 0.424387, 0.424740, 0.425682, 0.427582",\
+ "0.882507, 0.882524, 0.882582, 0.882733, 0.883038",\
+ "2.159515, 2.159528, 2.159564, 2.159647, 2.159816");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.367521, 0.579425, 0.836465, 1.278595, 2.162855",\
+ "0.401633, 0.614821, 0.871879, 1.314094, 2.198523",\
+ "0.451390, 0.668626, 0.925663, 1.367835, 2.252179",\
+ "0.579943, 0.801765, 1.058753, 1.500789, 2.384860",\
+ "0.915527, 1.146173, 1.403096, 1.844941, 2.728633",\
+ "0.454931, 0.666901, 0.923947, 1.365310, 2.248789",\
+ "0.489043, 0.702297, 0.959362, 1.400808, 2.284457",\
+ "0.538801, 0.756101, 1.013145, 1.454550, 2.338113",\
+ "0.667354, 0.889241, 1.146235, 1.587503, 2.470794",\
+ "1.002937, 1.233649, 1.490577, 1.931656, 2.814567",\
+ "0.535766, 0.755714, 1.011909, 1.452931, 2.335744",\
+ "0.569878, 0.791110, 1.047324, 1.488430, 2.371412",\
+ "0.619635, 0.844914, 1.101107, 1.542171, 2.425068",\
+ "0.748188, 0.978053, 1.234197, 1.675125, 2.557749",\
+ "1.083772, 1.322461, 1.578539, 2.019278, 2.901522",\
+ "0.593373, 0.821105, 1.076045, 1.516845, 2.399253",\
+ "0.627485, 0.856501, 1.111459, 1.552344, 2.434921",\
+ "0.677243, 0.910304, 1.165242, 1.606085, 2.488577",\
+ "0.805795, 1.043444, 1.298333, 1.739039, 2.621258",\
+ "1.141379, 1.387851, 1.642674, 2.083191, 2.965031",\
+ "0.895433, 1.182634, 1.427639, 1.866081, 2.744709",\
+ "0.930201, 1.218028, 1.463055, 1.901580, 2.780377",\
+ "0.984012, 1.271830, 1.516838, 1.955320, 2.834033",\
+ "1.117159, 1.404967, 1.649927, 2.088274, 2.966714",\
+ "1.461575, 1.749372, 1.994267, 2.432426, 3.310487");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.080902, 0.080967, 0.081775, 0.084238, 0.089162",\
+ "0.117510, 0.117523, 0.117812, 0.118746, 0.120614",\
+ "0.210641, 0.210651, 0.210781, 0.211182, 0.211986",\
+ "0.448308, 0.448315, 0.448372, 0.448536, 0.448865",\
+ "1.101372, 1.101392, 1.101478, 1.101676, 1.102071",\
+ "0.080902, 0.080968, 0.081783, 0.084238, 0.089162",\
+ "0.117510, 0.117523, 0.117815, 0.118746, 0.120614",\
+ "0.210641, 0.210651, 0.210782, 0.211182, 0.211986",\
+ "0.448308, 0.448315, 0.448373, 0.448536, 0.448865",\
+ "1.101372, 1.101392, 1.101479, 1.101676, 1.102071",\
+ "0.080902, 0.080970, 0.081783, 0.084238, 0.089162",\
+ "0.117510, 0.117523, 0.117815, 0.118746, 0.120614",\
+ "0.210641, 0.210651, 0.210782, 0.211182, 0.211986",\
+ "0.448308, 0.448315, 0.448373, 0.448536, 0.448865",\
+ "1.101372, 1.101393, 1.101479, 1.101676, 1.102071",\
+ "0.080902, 0.080972, 0.081783, 0.084238, 0.089162",\
+ "0.117510, 0.117524, 0.117815, 0.118746, 0.120614",\
+ "0.210641, 0.210651, 0.210782, 0.211182, 0.211986",\
+ "0.448308, 0.448315, 0.448373, 0.448536, 0.448865",\
+ "1.101372, 1.101393, 1.101479, 1.101676, 1.102071",\
+ "0.080902, 0.080995, 0.081808, 0.084248, 0.089162",\
+ "0.117510, 0.117529, 0.117825, 0.118750, 0.120614",\
+ "0.210641, 0.210655, 0.210786, 0.211184, 0.211986",\
+ "0.448308, 0.448318, 0.448374, 0.448537, 0.448865",\
+ "1.101372, 1.101400, 1.101481, 1.101677, 1.102071");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[9]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.350120, 0.565633, 0.746735, 1.037548, 1.600373",\
+ "0.398981, 0.614494, 0.795596, 1.086408, 1.649232",\
+ "0.501090, 0.716603, 0.897704, 1.188518, 1.751342",\
+ "0.737189, 0.952702, 1.133804, 1.424618, 1.987443",\
+ "1.308796, 1.524309, 1.705411, 1.996226, 2.559053",\
+ "0.438515, 0.652951, 0.834015, 1.124853, 1.687726",\
+ "0.487376, 0.701812, 0.882876, 1.173713, 1.736585",\
+ "0.589485, 0.803921, 0.984985, 1.275823, 1.838695",\
+ "0.825584, 1.040021, 1.221085, 1.511923, 2.074796",\
+ "1.397191, 1.611628, 1.792692, 2.083531, 2.646406",\
+ "0.527399, 0.733288, 0.914042, 1.204882, 1.767758",\
+ "0.576260, 0.782149, 0.962903, 1.253742, 1.816617",\
+ "0.678369, 0.884258, 1.065012, 1.355851, 1.918727",\
+ "0.914468, 1.120357, 1.301112, 1.591951, 2.154828",\
+ "1.486075, 1.691964, 1.872719, 2.163559, 2.726438",\
+ "0.590410, 0.791118, 0.971742, 1.262314, 1.824777",\
+ "0.639271, 0.839979, 1.020603, 1.311174, 1.873636",\
+ "0.741380, 0.942088, 1.122712, 1.413283, 1.975746",\
+ "0.977479, 1.178187, 1.358811, 1.649383, 2.211848",\
+ "1.549087, 1.749794, 1.930419, 2.220991, 2.783457",\
+ "0.913253, 1.096448, 1.275400, 1.565488, 2.127003",\
+ "0.962113, 1.145308, 1.324261, 1.614348, 2.175863",\
+ "1.064222, 1.247418, 1.426370, 1.716458, 2.277973",\
+ "1.300322, 1.483517, 1.662469, 1.952558, 2.514074",\
+ "1.871929, 2.055124, 2.234077, 2.524166, 3.085683");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\
+ "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\
+ "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\
+ "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\
+ "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\
+ "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\
+ "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\
+ "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\
+ "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\
+ "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\
+ "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\
+ "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\
+ "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\
+ "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\
+ "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\
+ "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\
+ "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\
+ "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\
+ "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\
+ "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\
+ "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\
+ "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\
+ "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\
+ "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\
+ "2.137202, 2.137202, 2.137202, 2.137203, 2.137204");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.373967, 0.592587, 0.771355, 1.061366, 1.624150",\
+ "0.409637, 0.625150, 0.806253, 1.097068, 1.659896",\
+ "0.450922, 0.666435, 0.847537, 1.138352, 1.701180",\
+ "0.573066, 0.788579, 0.969681, 1.260496, 1.823323",\
+ "0.905340, 1.120854, 1.301956, 1.592770, 2.155596",\
+ "0.462362, 0.679906, 0.858636, 1.148671, 1.711503",\
+ "0.498033, 0.712469, 0.893534, 1.184373, 1.747249",\
+ "0.539317, 0.753753, 0.934818, 1.225657, 1.788534",\
+ "0.661461, 0.875897, 1.056962, 1.347801, 1.910677",\
+ "0.993736, 1.208172, 1.389236, 1.680075, 2.242949",\
+ "0.551246, 0.760243, 0.938663, 1.228699, 1.791535",\
+ "0.586916, 0.792806, 0.973560, 1.264401, 1.827281",\
+ "0.628201, 0.834090, 1.014845, 1.305686, 1.868565",\
+ "0.750345, 0.956234, 1.136989, 1.427829, 1.990708",\
+ "1.082619, 1.288509, 1.469263, 1.760103, 2.322981",\
+ "0.614257, 0.818060, 0.996357, 1.286131, 1.848554",\
+ "0.649928, 0.850636, 1.031260, 1.321833, 1.884300",\
+ "0.691212, 0.891920, 1.072545, 1.363118, 1.925585",\
+ "0.813356, 1.014064, 1.194689, 1.485261, 2.047728",\
+ "1.145631, 1.346339, 1.526963, 1.817535, 2.380001",\
+ "0.943056, 1.123302, 1.300014, 1.589306, 2.150780",\
+ "0.972770, 1.155965, 1.334918, 1.625008, 2.186526",\
+ "1.014054, 1.197250, 1.376202, 1.666292, 2.227811",\
+ "1.136198, 1.319394, 1.498346, 1.788436, 2.349954",\
+ "1.468473, 1.651668, 1.830621, 2.120710, 2.682227");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\
+ "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\
+ "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\
+ "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\
+ "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\
+ "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\
+ "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\
+ "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\
+ "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\
+ "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\
+ "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\
+ "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\
+ "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\
+ "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\
+ "1.065140, 1.065140, 1.065140, 1.065138, 1.065135");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min_2531*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[57]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.331760, 0.553188, 0.742512, 1.045826, 1.632024",\
+ "0.380621, 0.602049, 0.791372, 1.094686, 1.680882",\
+ "0.482730, 0.704158, 0.893481, 1.196795, 1.782993",\
+ "0.718830, 0.940258, 1.129582, 1.432896, 2.019095",\
+ "1.290437, 1.511866, 1.701190, 2.004506, 2.590707",\
+ "0.420081, 0.640507, 0.829793, 1.133131, 1.719378",\
+ "0.468942, 0.689367, 0.878653, 1.181991, 1.768235",\
+ "0.571051, 0.791476, 0.980762, 1.284101, 1.870346",\
+ "0.807150, 1.027576, 1.216862, 1.520201, 2.106449",\
+ "1.378757, 1.599184, 1.788471, 2.091811, 2.678061",\
+ "0.509110, 0.720840, 0.909820, 1.213160, 1.799409",\
+ "0.557971, 0.769701, 0.958680, 1.262019, 1.848267",\
+ "0.660080, 0.871810, 1.060789, 1.364129, 1.950378",\
+ "0.896179, 1.107910, 1.296889, 1.600230, 2.186480",\
+ "1.467786, 1.679518, 1.868498, 2.171839, 2.758092",\
+ "0.572416, 0.778663, 0.967540, 1.270620, 1.856487",\
+ "0.621277, 0.827523, 1.016400, 1.319480, 1.905344",\
+ "0.723386, 0.929632, 1.118510, 1.421590, 2.007455",\
+ "0.959485, 1.165732, 1.354610, 1.657691, 2.243557",\
+ "1.531092, 1.737340, 1.926218, 2.229300, 2.815169",\
+ "0.903758, 1.083926, 1.271200, 1.573819, 2.158782",\
+ "0.952619, 1.132786, 1.320060, 1.622678, 2.207640",\
+ "1.054728, 1.234896, 1.422170, 1.724788, 2.309751",\
+ "1.290827, 1.470996, 1.658270, 1.960889, 2.545854",\
+ "1.862434, 2.042603, 2.229878, 2.532498, 3.117465");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.032790, 0.032796, 0.032799, 0.032806, 0.032822",\
+ "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\
+ "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\
+ "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\
+ "0.032790, 0.032796, 0.032799, 0.032806, 0.032822",\
+ "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\
+ "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\
+ "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\
+ "0.032791, 0.032796, 0.032799, 0.032806, 0.032822",\
+ "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\
+ "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\
+ "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\
+ "0.032791, 0.032796, 0.032799, 0.032806, 0.032822",\
+ "0.150562, 0.150560, 0.150559, 0.150556, 0.150549",\
+ "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\
+ "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\
+ "0.032791, 0.032796, 0.032799, 0.032807, 0.032822",\
+ "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\
+ "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\
+ "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137204");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.355611, 0.590269, 0.779821, 1.083137, 1.669339",\
+ "0.391278, 0.612708, 0.802032, 1.105348, 1.691551",\
+ "0.432562, 0.653992, 0.843316, 1.146633, 1.732836",\
+ "0.554706, 0.776136, 0.965460, 1.268776, 1.854978",\
+ "0.886981, 1.108410, 1.297734, 1.601049, 2.187249",\
+ "0.443930, 0.677587, 0.867102, 1.170442, 1.756692",\
+ "0.479599, 0.700026, 0.889313, 1.192653, 1.778904",\
+ "0.520883, 0.741310, 0.930597, 1.233938, 1.820189",\
+ "0.643027, 0.863454, 1.052741, 1.356081, 1.942332",\
+ "0.975302, 1.195728, 1.385015, 1.688354, 2.274603",\
+ "0.532956, 0.757921, 0.947129, 1.250471, 1.836724",\
+ "0.568627, 0.780360, 0.969340, 1.272682, 1.858936",\
+ "0.609912, 0.821644, 1.010624, 1.313967, 1.900221",\
+ "0.732056, 0.943788, 1.132768, 1.436110, 2.022363",\
+ "1.064331, 1.276062, 1.465042, 1.768383, 2.354635",\
+ "0.596259, 0.815760, 1.004849, 1.307931, 1.893801",\
+ "0.631934, 0.838182, 1.027060, 1.330143, 1.916013",\
+ "0.673218, 0.879466, 1.068345, 1.371427, 1.957298",\
+ "0.795362, 1.001610, 1.190488, 1.493571, 2.079441",\
+ "1.127637, 1.333884, 1.522762, 1.825843, 2.411712",\
+ "0.930491, 1.121142, 1.308509, 1.611130, 2.196097",\
+ "0.963275, 1.143445, 1.330720, 1.633341, 2.218309",\
+ "1.004560, 1.184730, 1.372005, 1.674626, 2.259594",\
+ "1.126704, 1.306873, 1.494148, 1.796769, 2.381737",\
+ "1.458978, 1.639148, 1.826422, 2.129042, 2.714008");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011");
+ values ( "0.047454, 0.047451, 0.047450, 0.047447, 0.047442",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\
+ "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\
+ "1.065141, 1.065139, 1.065138, 1.065135, 1.065130",\
+ "0.047453, 0.047451, 0.047450, 0.047447, 0.047442",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\
+ "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\
+ "1.065141, 1.065139, 1.065138, 1.065135, 1.065130",\
+ "0.047453, 0.047451, 0.047450, 0.047447, 0.047442",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\
+ "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\
+ "1.065140, 1.065139, 1.065138, 1.065135, 1.065130",\
+ "0.047453, 0.047451, 0.047450, 0.047447, 0.047442",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\
+ "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\
+ "1.065140, 1.065139, 1.065138, 1.065135, 1.065130",\
+ "0.047452, 0.047451, 0.047450, 0.047447, 0.047442",\
+ "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\
+ "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\
+ "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\
+ "1.065140, 1.065139, 1.065138, 1.065135, 1.065130");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[58]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.441216, 0.635561, 0.817859, 1.110553, 1.677168",\
+ "0.490035, 0.684380, 0.866679, 1.159372, 1.725988",\
+ "0.592166, 0.786511, 0.968809, 1.261503, 1.828118",\
+ "0.828311, 1.022655, 1.204954, 1.497648, 2.064263",\
+ "1.399982, 1.594326, 1.776625, 2.069319, 2.635934",\
+ "0.529420, 0.722878, 0.905140, 1.197858, 1.764521",\
+ "0.578240, 0.771698, 0.953960, 1.246678, 1.813341",\
+ "0.680371, 0.873829, 1.056091, 1.348809, 1.915472",\
+ "0.916515, 1.109973, 1.292235, 1.584953, 2.151616",\
+ "1.488186, 1.681644, 1.863906, 2.156624, 2.723287",\
+ "0.618747, 0.803206, 0.985167, 1.277887, 1.844553",\
+ "0.667567, 0.852026, 1.033987, 1.326706, 1.893373",\
+ "0.769697, 0.954157, 1.136117, 1.428837, 1.995504",\
+ "1.005842, 1.190301, 1.372262, 1.664981, 2.231648",\
+ "1.577513, 1.761972, 1.943933, 2.236652, 2.803319",\
+ "0.681460, 0.861042, 1.042871, 1.335324, 1.901586",\
+ "0.730280, 0.909862, 1.091691, 1.384144, 1.950405",\
+ "0.832411, 1.011993, 1.193822, 1.486274, 2.052536",\
+ "1.068555, 1.248137, 1.429966, 1.722419, 2.288681",\
+ "1.640226, 1.819808, 2.001637, 2.294090, 2.860352",\
+ "0.985102, 1.166382, 1.346527, 1.638502, 2.203828",\
+ "1.033922, 1.215202, 1.395347, 1.687321, 2.252647",\
+ "1.136052, 1.317332, 1.497478, 1.789452, 2.354778",\
+ "1.372197, 1.553477, 1.733622, 2.025596, 2.590923",\
+ "1.943868, 2.125148, 2.305293, 2.597268, 3.162594");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\
+ "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\
+ "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\
+ "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\
+ "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\
+ "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\
+ "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\
+ "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\
+ "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\
+ "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\
+ "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\
+ "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\
+ "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\
+ "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\
+ "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\
+ "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\
+ "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\
+ "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\
+ "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\
+ "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\
+ "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\
+ "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\
+ "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\
+ "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\
+ "2.137131, 2.137131, 2.137131, 2.137131, 2.137131");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.478632, 0.663448, 0.845746, 1.138440, 1.705055",\
+ "0.500859, 0.695203, 0.877502, 1.170196, 1.736811",\
+ "0.542150, 0.736495, 0.918793, 1.211487, 1.778102",\
+ "0.664276, 0.858621, 1.040919, 1.333613, 1.900228",\
+ "0.996499, 1.190843, 1.373142, 1.665835, 2.232451",\
+ "0.566836, 0.750765, 0.933027, 1.225745, 1.792408",\
+ "0.589063, 0.782521, 0.964783, 1.257501, 1.824164",\
+ "0.630354, 0.823812, 1.006074, 1.298792, 1.865455",\
+ "0.752480, 0.945938, 1.128200, 1.420918, 1.987581",\
+ "1.084703, 1.278161, 1.460423, 1.753141, 2.319804",\
+ "0.651614, 0.831093, 1.013054, 1.305773, 1.872440",\
+ "0.678390, 0.862849, 1.044810, 1.337529, 1.904196",\
+ "0.719681, 0.904140, 1.086101, 1.378820, 1.945487",\
+ "0.841807, 1.026266, 1.208227, 1.500947, 2.067613",\
+ "1.174030, 1.358489, 1.540450, 1.833169, 2.399836",\
+ "0.709347, 0.888930, 1.070759, 1.363211, 1.929473",\
+ "0.741103, 0.920685, 1.102514, 1.394967, 1.961228",\
+ "0.782394, 0.961976, 1.143806, 1.436258, 2.002520",\
+ "0.904520, 1.084103, 1.265932, 1.558384, 2.124646",\
+ "1.236743, 1.416325, 1.598154, 1.890607, 2.456868",\
+ "1.012989, 1.194269, 1.374414, 1.666389, 2.231715",\
+ "1.044745, 1.226025, 1.406170, 1.698144, 2.263471",\
+ "1.086036, 1.267316, 1.447461, 1.739436, 2.304762",\
+ "1.208162, 1.389442, 1.569587, 1.861562, 2.426888",\
+ "1.540385, 1.721665, 1.901810, 2.193784, 2.759110");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011");
+ values ( "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\
+ "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\
+ "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\
+ "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\
+ "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\
+ "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\
+ "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\
+ "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\
+ "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\
+ "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\
+ "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\
+ "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\
+ "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\
+ "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\
+ "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\
+ "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\
+ "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\
+ "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\
+ "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\
+ "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\
+ "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\
+ "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\
+ "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\
+ "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\
+ "1.065004, 1.065004, 1.065004, 1.065004, 1.065004");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min_2476*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[62]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.348914, 0.525100, 0.702588, 0.991299, 1.552048",\
+ "0.404496, 0.580679, 0.758142, 1.046740, 1.607235",\
+ "0.479870, 0.656050, 0.833489, 1.121981, 1.682238",\
+ "0.681478, 0.857653, 1.035056, 1.323386, 1.883276",\
+ "1.225627, 1.401797, 1.579170, 1.867368, 2.426959",\
+ "0.436324, 0.612419, 0.789869, 1.078604, 1.639402",\
+ "0.491907, 0.667998, 0.845423, 1.134045, 1.694588",\
+ "0.567281, 0.743368, 0.920770, 1.209286, 1.769591",\
+ "0.768889, 0.944971, 1.122336, 1.410691, 1.970629",\
+ "1.313037, 1.489116, 1.666451, 1.954674, 2.514312",\
+ "0.517159, 0.692753, 0.869896, 1.158633, 1.719433",\
+ "0.572742, 0.748332, 0.925450, 1.214074, 1.774620",\
+ "0.648115, 0.823702, 1.000796, 1.289315, 1.849623",\
+ "0.849723, 1.025305, 1.202363, 1.490720, 2.050661",\
+ "1.393872, 1.569450, 1.746478, 2.034702, 2.594344",\
+ "0.574766, 0.750569, 0.927588, 1.216063, 1.776449",\
+ "0.630349, 0.806149, 0.983142, 1.271503, 1.831635",\
+ "0.705722, 0.881519, 1.058488, 1.346744, 1.906637",\
+ "0.907331, 1.083122, 1.260055, 1.548149, 2.107674",\
+ "1.451479, 1.627266, 1.804170, 2.092131, 2.651357",\
+ "0.876826, 1.055796, 1.231244, 1.519234, 2.078671",\
+ "0.932408, 1.111374, 1.286798, 1.574675, 2.133856",\
+ "1.007782, 1.186745, 1.362144, 1.649915, 2.208858",\
+ "1.209389, 1.388348, 1.563711, 1.851319, 2.409893",\
+ "1.753537, 1.932492, 2.107826, 2.395301, 2.953575");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\
+ "0.243808, 0.243808, 0.243808, 0.243837, 0.243906",\
+ "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\
+ "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\
+ "2.138597, 2.138606, 2.138675, 2.138985, 2.139684",\
+ "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\
+ "0.243808, 0.243808, 0.243808, 0.243837, 0.243906",\
+ "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\
+ "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\
+ "2.138597, 2.138606, 2.138675, 2.138985, 2.139684",\
+ "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\
+ "0.243808, 0.243808, 0.243808, 0.243837, 0.243906",\
+ "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\
+ "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\
+ "2.138597, 2.138606, 2.138675, 2.138985, 2.139684",\
+ "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\
+ "0.243808, 0.243808, 0.243808, 0.243837, 0.243907",\
+ "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\
+ "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\
+ "2.138597, 2.138606, 2.138675, 2.138986, 2.139686",\
+ "0.151029, 0.151029, 0.151029, 0.151092, 0.151249",\
+ "0.243808, 0.243808, 0.243808, 0.243837, 0.243907",\
+ "0.409517, 0.409519, 0.409535, 0.409607, 0.409770",\
+ "0.874760, 0.874761, 0.874769, 0.874803, 0.874881",\
+ "2.138598, 2.138607, 2.138675, 2.138986, 2.139688");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.322905, 0.543708, 0.721197, 1.009915, 1.570680",\
+ "0.358307, 0.577820, 0.755311, 1.044036, 1.604817",\
+ "0.412119, 0.627577, 0.805068, 1.093794, 1.654579",\
+ "0.545267, 0.756130, 0.933618, 1.222334, 1.783093",\
+ "0.889685, 1.091714, 1.269206, 1.557937, 2.118731",\
+ "0.411116, 0.631026, 0.808478, 1.097220, 1.658034",\
+ "0.446518, 0.665138, 0.842591, 1.131341, 1.692170",\
+ "0.500329, 0.714895, 0.892349, 1.181100, 1.741932",\
+ "0.633477, 0.843448, 1.020899, 1.309639, 1.870447",\
+ "0.977895, 1.179032, 1.356487, 1.645242, 2.206084",\
+ "0.499788, 0.711360, 0.888505, 1.177248, 1.738065",\
+ "0.535189, 0.745472, 0.922618, 1.211369, 1.772202",\
+ "0.589001, 0.795229, 0.972376, 1.261128, 1.821964",\
+ "0.722149, 0.923782, 1.100926, 1.389667, 1.950478",\
+ "1.066566, 1.259366, 1.436514, 1.725270, 2.286115",\
+ "0.562748, 0.769177, 0.946197, 1.234678, 1.795081",\
+ "0.598149, 0.803289, 0.980311, 1.268799, 1.829218",\
+ "0.651961, 0.853046, 1.030068, 1.318558, 1.878979",\
+ "0.785108, 0.981599, 1.158618, 1.447097, 2.007494",\
+ "1.129526, 1.317183, 1.494206, 1.782700, 2.343131",\
+ "0.894800, 1.074403, 1.249853, 1.537850, 2.097302",\
+ "0.929545, 1.108515, 1.283966, 1.571971, 2.131439",\
+ "0.979303, 1.158272, 1.333724, 1.621730, 2.181201",\
+ "1.107856, 1.286825, 1.462274, 1.750269, 2.309716",\
+ "1.443439, 1.622409, 1.797862, 2.085872, 2.645353");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011");
+ values ( "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\
+ "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\
+ "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\
+ "0.432555, 0.432553, 0.432541, 0.432487, 0.432365",\
+ "1.065544, 1.065545, 1.065557, 1.065609, 1.065728",\
+ "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\
+ "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\
+ "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\
+ "0.432555, 0.432553, 0.432541, 0.432487, 0.432365",\
+ "1.065544, 1.065545, 1.065557, 1.065609, 1.065728",\
+ "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\
+ "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\
+ "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\
+ "0.432554, 0.432553, 0.432541, 0.432487, 0.432365",\
+ "1.065544, 1.065545, 1.065557, 1.065609, 1.065728",\
+ "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\
+ "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\
+ "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\
+ "0.432554, 0.432553, 0.432541, 0.432487, 0.432365",\
+ "1.065544, 1.065545, 1.065557, 1.065610, 1.065728",\
+ "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\
+ "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\
+ "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\
+ "0.432554, 0.432553, 0.432541, 0.432487, 0.432365",\
+ "1.065544, 1.065545, 1.065557, 1.065610, 1.065729");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min_2427*/
+
+} /* end of pin tl_o[9] */
+
+pin("tl_o[8]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.154883 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[8];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[17]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.373916, 0.599728, 0.894574, 1.388503, 2.376363",\
+ "0.415183, 0.640172, 0.934074, 1.428691, 2.417925",\
+ "0.491066, 0.715879, 1.009866, 1.504530, 2.493859",\
+ "0.745862, 0.970981, 1.264787, 1.759400, 2.748624",\
+ "1.670986, 1.894752, 2.189083, 2.684630, 3.675724",\
+ "0.461357, 0.687335, 0.982222, 1.475219, 2.462296",\
+ "0.502624, 0.727773, 1.021724, 1.515406, 2.503859",\
+ "0.578507, 0.803480, 1.097517, 1.591246, 2.579792",\
+ "0.833304, 1.058581, 1.352438, 1.846115, 2.834558",\
+ "1.758428, 1.982354, 2.276736, 2.771345, 3.761657",\
+ "0.542237, 0.776480, 1.070189, 1.562842, 2.549252",\
+ "0.583504, 0.816901, 1.109691, 1.603029, 2.590814",\
+ "0.659387, 0.892609, 1.185483, 1.678869, 2.666748",\
+ "0.914185, 1.147708, 1.440404, 1.933738, 2.921513",\
+ "1.839308, 2.071485, 2.364703, 2.858968, 3.848613",\
+ "0.599958, 0.842354, 1.134332, 1.626756, 2.612761",\
+ "0.641225, 0.882751, 1.173835, 1.666943, 2.654323",\
+ "0.717108, 0.958461, 1.249627, 1.742782, 2.730257",\
+ "0.971907, 1.213556, 1.504548, 1.997652, 2.985022",\
+ "1.897030, 2.137338, 2.428847, 2.922882, 3.912122",\
+ "0.902648, 1.209455, 1.486456, 1.976211, 2.958217",\
+ "0.943914, 1.249574, 1.525966, 2.016402, 2.999779",\
+ "1.019797, 1.325301, 1.601758, 2.092241, 3.075712",\
+ "1.274609, 1.580356, 1.856679, 2.347110, 3.330478",\
+ "2.199727, 2.504201, 2.780987, 3.272345, 4.257577");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.034807, 0.034870, 0.035021, 0.035342, 0.035983",\
+ "0.083278, 0.083283, 0.083326, 0.083445, 0.083683",\
+ "0.208556, 0.208575, 0.208609, 0.208619, 0.208640",\
+ "0.692765, 0.692765, 0.692980, 0.693734, 0.695242",\
+ "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\
+ "0.034807, 0.034871, 0.035022, 0.035342, 0.035983",\
+ "0.083278, 0.083283, 0.083327, 0.083445, 0.083683",\
+ "0.208556, 0.208576, 0.208609, 0.208619, 0.208640",\
+ "0.692765, 0.692765, 0.692982, 0.693734, 0.695242",\
+ "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\
+ "0.034807, 0.034872, 0.035022, 0.035342, 0.035983",\
+ "0.083278, 0.083284, 0.083327, 0.083445, 0.083683",\
+ "0.208556, 0.208576, 0.208609, 0.208619, 0.208640",\
+ "0.692765, 0.692765, 0.692982, 0.693734, 0.695242",\
+ "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\
+ "0.034808, 0.034873, 0.035022, 0.035342, 0.035983",\
+ "0.083278, 0.083284, 0.083327, 0.083445, 0.083683",\
+ "0.208556, 0.208577, 0.208609, 0.208619, 0.208640",\
+ "0.692765, 0.692765, 0.692982, 0.693734, 0.695242",\
+ "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\
+ "0.034810, 0.034887, 0.035026, 0.035343, 0.035983",\
+ "0.083278, 0.083286, 0.083328, 0.083446, 0.083683",\
+ "0.208556, 0.208584, 0.208609, 0.208619, 0.208640",\
+ "0.692765, 0.692765, 0.692990, 0.693737, 0.695242",\
+ "2.477403, 2.477403, 2.477403, 2.477403, 2.477403");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.420490, 0.645190, 0.938944, 1.432430, 2.419402",\
+ "0.461359, 0.686264, 0.979881, 1.473291, 2.460111",\
+ "0.521542, 0.746363, 1.040033, 1.533430, 2.520226",\
+ "0.690406, 0.915382, 1.209000, 1.702350, 2.689050",\
+ "1.273072, 1.496794, 1.790318, 2.283708, 3.270487",\
+ "0.507931, 0.732792, 1.026591, 1.519145, 2.505336",\
+ "0.548801, 0.773865, 1.067528, 1.560006, 2.546045",\
+ "0.608983, 0.833965, 1.127680, 1.620146, 2.606159",\
+ "0.777848, 1.002983, 1.296647, 1.789066, 2.774984",\
+ "1.360514, 1.584395, 1.877965, 2.370424, 3.356421",\
+ "0.588811, 0.821923, 1.114557, 1.606768, 2.592291",\
+ "0.629680, 0.862994, 1.155494, 1.647629, 2.633000",\
+ "0.689863, 0.923095, 1.215646, 1.707769, 2.693114",\
+ "0.858728, 1.092113, 1.384613, 1.876689, 2.861939",\
+ "1.441395, 1.673523, 1.965932, 2.458046, 3.443376",\
+ "0.646531, 0.887777, 1.178701, 1.670682, 2.655800",\
+ "0.687400, 0.928846, 1.219638, 1.711543, 2.696509",\
+ "0.747584, 0.988947, 1.279790, 1.771683, 2.756623",\
+ "0.916448, 1.157964, 1.448757, 1.940602, 2.925448",\
+ "1.499118, 1.739372, 2.030076, 2.521960, 3.506885",\
+ "0.949211, 1.254642, 1.530820, 2.020136, 3.001256",\
+ "0.990081, 1.295683, 1.571756, 2.060997, 3.041965",\
+ "1.050271, 1.355798, 1.631908, 2.121136, 3.102079",\
+ "1.219138, 1.524806, 1.800875, 2.290056, 3.270904",\
+ "1.801826, 2.106188, 2.382194, 2.871414, 3.852341");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.042658, 0.042646, 0.042619, 0.042581, 0.042505",\
+ "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\
+ "0.155293, 0.155293, 0.155279, 0.155230, 0.155132",\
+ "0.431058, 0.431058, 0.431019, 0.430882, 0.430609",\
+ "1.497229, 1.495745, 1.494360, 1.494360, 1.494360",\
+ "0.042658, 0.042646, 0.042618, 0.042581, 0.042505",\
+ "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\
+ "0.155293, 0.155293, 0.155279, 0.155230, 0.155132",\
+ "0.431058, 0.431058, 0.431018, 0.430882, 0.430609",\
+ "1.497229, 1.495736, 1.494360, 1.494360, 1.494360",\
+ "0.042658, 0.042646, 0.042618, 0.042581, 0.042505",\
+ "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\
+ "0.155293, 0.155293, 0.155279, 0.155230, 0.155132",\
+ "0.431058, 0.431058, 0.431018, 0.430882, 0.430609",\
+ "1.497225, 1.495716, 1.494360, 1.494360, 1.494360",\
+ "0.042658, 0.042646, 0.042618, 0.042581, 0.042505",\
+ "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\
+ "0.155293, 0.155293, 0.155278, 0.155230, 0.155132",\
+ "0.431058, 0.431058, 0.431018, 0.430882, 0.430609",\
+ "1.497218, 1.495687, 1.494360, 1.494360, 1.494360",\
+ "0.042658, 0.042642, 0.042618, 0.042580, 0.042505",\
+ "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\
+ "0.155293, 0.155293, 0.155278, 0.155230, 0.155132",\
+ "0.431058, 0.431058, 0.431017, 0.430882, 0.430609",\
+ "1.497153, 1.495349, 1.494360, 1.494360, 1.494360");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2694*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[18]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.746021, 1.001665, 1.285647, 1.784442, 2.782033",\
+ "0.780412, 1.036056, 1.320037, 1.818832, 2.816423",\
+ "0.851654, 1.107299, 1.391280, 1.890076, 2.887667",\
+ "1.105821, 1.361465, 1.645446, 2.144242, 3.141833",\
+ "2.030393, 2.286036, 2.570016, 3.068810, 4.066399",\
+ "0.833430, 1.089212, 1.373307, 1.871157, 2.867967",\
+ "0.867821, 1.123603, 1.407697, 1.905547, 2.902357",\
+ "0.939063, 1.194845, 1.478940, 1.976790, 2.973600",\
+ "1.193229, 1.449012, 1.733106, 2.230957, 3.227767",\
+ "2.117802, 2.373583, 2.657676, 3.155524, 4.152333",\
+ "0.914308, 1.178178, 1.461272, 1.958778, 2.954922",\
+ "0.948698, 1.212569, 1.495662, 1.993168, 2.989312",\
+ "1.019941, 1.283811, 1.566905, 2.064412, 3.060555",\
+ "1.274107, 1.537978, 1.821072, 2.318578, 3.314722",\
+ "2.198680, 2.462549, 2.745641, 3.243146, 4.239288",\
+ "0.974568, 1.243791, 1.525417, 2.022691, 3.018431",\
+ "1.008959, 1.278181, 1.559807, 2.057082, 3.052821",\
+ "1.080201, 1.349424, 1.631050, 2.128325, 3.124064",\
+ "1.334368, 1.603591, 1.885216, 2.382491, 3.378231",\
+ "2.258940, 2.528162, 2.809785, 3.307059, 4.302797",\
+ "1.309682, 1.607944, 1.877586, 2.372160, 3.363887",\
+ "1.344072, 1.642334, 1.911976, 2.406550, 3.398277",\
+ "1.415315, 1.713577, 1.983219, 2.477793, 3.469521",\
+ "1.669481, 1.967744, 2.237385, 2.731960, 3.723687",\
+ "2.594053, 2.892314, 3.161954, 3.656528, 4.648253");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\
+ "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\
+ "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\
+ "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\
+ "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\
+ "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\
+ "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\
+ "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\
+ "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\
+ "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\
+ "2.464359, 2.464359, 2.464359, 2.464359, 2.464359");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.777783, 1.033425, 1.317405, 1.816199, 2.813788",\
+ "0.819535, 1.075178, 1.359157, 1.857951, 2.855540",\
+ "0.879465, 1.135108, 1.419087, 1.917882, 2.915471",\
+ "1.047583, 1.303225, 1.587205, 2.085999, 3.083588",\
+ "1.629496, 1.885133, 2.169106, 2.667897, 3.665479",\
+ "0.865191, 1.120972, 1.405064, 1.902913, 2.899722",\
+ "0.906944, 1.162724, 1.446817, 1.944666, 2.941474",\
+ "0.966874, 1.222655, 1.506747, 2.004596, 3.001405",\
+ "1.134991, 1.390772, 1.674865, 2.172714, 3.169522",\
+ "1.716905, 1.972680, 2.256766, 2.754611, 3.751413",\
+ "0.946069, 1.209938, 1.493030, 1.990535, 2.986677",\
+ "0.987822, 1.251690, 1.534782, 2.032288, 3.028429",\
+ "1.047752, 1.311621, 1.594713, 2.092218, 3.088360",\
+ "1.215869, 1.479738, 1.762830, 2.260335, 3.256477",\
+ "1.797783, 2.061646, 2.344732, 2.842233, 3.838368",\
+ "1.006330, 1.275551, 1.557174, 2.054448, 3.050186",\
+ "1.048082, 1.317303, 1.598927, 2.096201, 3.091938",\
+ "1.108012, 1.377234, 1.658857, 2.156131, 3.151869",\
+ "1.276130, 1.545351, 1.826975, 2.324248, 3.319986",\
+ "1.858043, 2.127259, 2.408876, 2.906147, 3.901877",\
+ "1.341443, 1.639703, 1.909343, 2.403917, 3.395642",\
+ "1.383195, 1.681456, 1.951096, 2.445669, 3.437394",\
+ "1.443126, 1.741386, 2.011026, 2.505599, 3.497324",\
+ "1.611243, 1.909503, 2.179143, 2.673717, 3.665442",\
+ "2.193155, 2.491410, 2.761045, 3.255615, 4.247333");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2719*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[23]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.329434, 0.567970, 0.849310, 1.349062, 2.348564",\
+ "0.370729, 0.609110, 0.889780, 1.387186, 2.381998",\
+ "0.446657, 0.684926, 0.965184, 1.461121, 2.452996",\
+ "0.702252, 0.940104, 1.219789, 1.715647, 2.707363",\
+ "1.626635, 1.863892, 2.145200, 2.640602, 3.631406",\
+ "0.416843, 0.655497, 0.936973, 1.435776, 2.434498",\
+ "0.458138, 0.696638, 0.977436, 1.473900, 2.467931",\
+ "0.534066, 0.772454, 1.052835, 1.547836, 2.538929",\
+ "0.789661, 1.027628, 1.307440, 1.802361, 2.793297",\
+ "1.714044, 1.951428, 2.232849, 2.727316, 3.717340",\
+ "0.497703, 0.744421, 1.024939, 1.523398, 2.521453",\
+ "0.538998, 0.785561, 1.065401, 1.561522, 2.554886",\
+ "0.614927, 0.861378, 1.140800, 1.635457, 2.625884",\
+ "0.870521, 1.116544, 1.395405, 1.889983, 2.880252",\
+ "1.794904, 2.040369, 2.320814, 2.814938, 3.804295",\
+ "0.555377, 0.809972, 1.089084, 1.587311, 2.584962",\
+ "0.596671, 0.851113, 1.129546, 1.625435, 2.618395",\
+ "0.672599, 0.926930, 1.204945, 1.699371, 2.689393",\
+ "0.928193, 1.182084, 1.459549, 1.953896, 2.943761",\
+ "1.852575, 2.105947, 2.384958, 2.878851, 3.867804",\
+ "0.876916, 1.173402, 1.441262, 1.936784, 2.930418",\
+ "0.918063, 1.214545, 1.481701, 1.974898, 2.963851",\
+ "0.993829, 1.290365, 1.557085, 2.048828, 3.034849",\
+ "1.249296, 1.545383, 1.811688, 2.303353, 3.289217",\
+ "2.172819, 2.469679, 2.737093, 3.228306, 4.213260");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.035016, 0.035016, 0.035955, 0.039196, 0.045676",\
+ "0.083549, 0.083549, 0.083885, 0.085044, 0.087361",\
+ "0.208718, 0.208718, 0.208874, 0.209415, 0.210496",\
+ "0.692609, 0.692819, 0.692927, 0.693072, 0.693361",\
+ "2.477031, 2.477031, 2.477148, 2.477552, 2.478359",\
+ "0.035016, 0.035016, 0.035965, 0.039196, 0.045676",\
+ "0.083549, 0.083549, 0.083888, 0.085044, 0.087361",\
+ "0.208718, 0.208718, 0.208876, 0.209415, 0.210496",\
+ "0.692609, 0.692820, 0.692927, 0.693072, 0.693361",\
+ "2.477031, 2.477031, 2.477149, 2.477552, 2.478359",\
+ "0.035016, 0.035016, 0.035966, 0.039196, 0.045676",\
+ "0.083549, 0.083549, 0.083888, 0.085044, 0.087361",\
+ "0.208718, 0.208718, 0.208876, 0.209415, 0.210496",\
+ "0.692610, 0.692821, 0.692927, 0.693072, 0.693361",\
+ "2.477031, 2.477031, 2.477149, 2.477552, 2.478359",\
+ "0.035016, 0.035016, 0.035966, 0.039196, 0.045676",\
+ "0.083549, 0.083549, 0.083889, 0.085044, 0.087361",\
+ "0.208718, 0.208718, 0.208876, 0.209415, 0.210496",\
+ "0.692612, 0.692822, 0.692927, 0.693072, 0.693361",\
+ "2.477031, 2.477031, 2.477149, 2.477552, 2.478359",\
+ "0.035016, 0.035016, 0.035999, 0.039209, 0.045676",\
+ "0.083549, 0.083549, 0.083900, 0.085048, 0.087361",\
+ "0.208718, 0.208718, 0.208882, 0.209417, 0.210496",\
+ "0.692711, 0.692838, 0.692929, 0.693072, 0.693361",\
+ "2.477031, 2.477031, 2.477154, 2.477553, 2.478359");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.376302, 0.614890, 0.892196, 1.378119, 2.349964",\
+ "0.417201, 0.655792, 0.932845, 1.417492, 2.386786",\
+ "0.477347, 0.716035, 0.992408, 1.474614, 2.439025",\
+ "0.646325, 0.884988, 1.160689, 1.640497, 2.600112",\
+ "1.229570, 1.466407, 1.742451, 2.222424, 3.182369",\
+ "0.463711, 0.702417, 0.979816, 1.464833, 2.435898",\
+ "0.504610, 0.743320, 1.020461, 1.504206, 2.472719",\
+ "0.564756, 0.803563, 1.080016, 1.561328, 2.524959",\
+ "0.733734, 0.972517, 1.248289, 1.727211, 2.686046",\
+ "1.316979, 1.553937, 1.830052, 2.309139, 3.268303",\
+ "0.544574, 0.791340, 1.067780, 1.552455, 2.522853",\
+ "0.585473, 0.832245, 1.108425, 1.591828, 2.559674",\
+ "0.645618, 0.892489, 1.167980, 1.648950, 2.611914",\
+ "0.814594, 1.061442, 1.336253, 1.814833, 2.773001",\
+ "1.397827, 1.642867, 1.918017, 2.396760, 3.355258",\
+ "0.602253, 0.856891, 1.131923, 1.616368, 2.586362",\
+ "0.643149, 0.897798, 1.172568, 1.655741, 2.623183",\
+ "0.703295, 0.958043, 1.232122, 1.712863, 2.675423",\
+ "0.872267, 1.126997, 1.400395, 1.878746, 2.836510",\
+ "1.455475, 1.708427, 1.982158, 2.460673, 3.418767",\
+ "0.923807, 1.220314, 1.483961, 1.965784, 2.931818",\
+ "0.964736, 1.261250, 1.524593, 2.005152, 2.968639",\
+ "1.024895, 1.321501, 1.584123, 2.062263, 3.020879",\
+ "1.193870, 1.490460, 1.752371, 2.228136, 3.181966",\
+ "1.775178, 2.071965, 2.334136, 2.810064, 3.764223");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.042685, 0.042788, 0.042938, 0.042938, 0.042938",\
+ "0.078477, 0.079298, 0.079365, 0.079365, 0.079365",\
+ "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\
+ "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\
+ "0.042685, 0.042789, 0.042938, 0.042938, 0.042938",\
+ "0.078477, 0.079299, 0.079365, 0.079365, 0.079365",\
+ "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\
+ "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\
+ "0.042685, 0.042791, 0.042938, 0.042938, 0.042938",\
+ "0.078482, 0.079299, 0.079365, 0.079365, 0.079365",\
+ "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\
+ "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\
+ "0.042685, 0.042794, 0.042938, 0.042938, 0.042938",\
+ "0.078491, 0.079301, 0.079365, 0.079365, 0.079365",\
+ "0.155271, 0.155315, 0.155322, 0.155322, 0.155322",\
+ "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\
+ "0.042685, 0.042831, 0.042938, 0.042938, 0.042938",\
+ "0.078956, 0.079318, 0.079365, 0.079365, 0.079365",\
+ "0.155294, 0.155316, 0.155322, 0.155322, 0.155322",\
+ "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[24]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.731951, 0.980905, 1.256242, 1.719746, 2.646754",\
+ "0.766341, 1.015295, 1.290632, 1.754136, 2.681144",\
+ "0.837584, 1.086538, 1.361876, 1.825380, 2.752387",\
+ "1.091750, 1.340704, 1.616042, 2.079546, 3.006554",\
+ "2.016322, 2.265275, 2.540610, 3.004114, 3.931121",\
+ "0.819353, 1.068475, 1.343788, 1.806459, 2.732687",\
+ "0.853744, 1.102866, 1.378179, 1.840850, 2.767077",\
+ "0.924986, 1.174109, 1.449422, 1.912093, 2.838321",\
+ "1.179153, 1.428275, 1.703588, 2.166259, 3.092487",\
+ "2.103725, 2.352845, 2.628156, 3.090827, 4.017055",\
+ "0.900166, 1.157465, 1.431751, 1.894080, 2.819643",\
+ "0.934556, 1.191856, 1.466141, 1.928470, 2.854033",\
+ "1.005799, 1.263098, 1.537384, 1.999714, 2.925276",\
+ "1.259965, 1.517265, 1.791550, 2.253880, 3.179442",\
+ "2.184537, 2.441835, 2.716118, 3.178448, 4.104010",\
+ "0.957806, 1.223112, 1.495889, 1.957993, 2.883152",\
+ "0.992196, 1.257502, 1.530279, 1.992383, 2.917542",\
+ "1.063439, 1.328745, 1.601523, 2.063626, 2.988785",\
+ "1.317605, 1.582911, 1.855689, 2.317793, 3.242951",\
+ "2.242177, 2.507481, 2.780257, 3.242361, 4.167519",\
+ "1.292888, 1.587742, 1.847697, 2.307310, 3.228608",\
+ "1.327278, 1.622132, 1.882087, 2.341700, 3.262998",\
+ "1.398521, 1.693375, 1.953330, 2.412943, 3.334241",\
+ "1.652687, 1.947541, 2.207496, 2.667110, 3.588408",\
+ "2.577259, 2.872111, 3.132065, 3.591678, 4.512975");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\
+ "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\
+ "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\
+ "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\
+ "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\
+ "2.464354, 2.464354, 2.464354, 2.464354, 2.464354");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.763712, 1.012664, 1.287999, 1.751503, 2.678509",\
+ "0.805464, 1.054416, 1.329752, 1.793255, 2.720262",\
+ "0.865395, 1.114347, 1.389682, 1.853185, 2.780192",\
+ "1.033512, 1.282464, 1.557799, 2.021303, 2.948309",\
+ "1.615425, 1.864370, 2.139697, 2.603199, 3.530203",\
+ "0.851115, 1.100234, 1.375545, 1.838216, 2.764443",\
+ "0.892867, 1.141987, 1.417298, 1.879968, 2.806196",\
+ "0.952797, 1.201917, 1.477228, 1.939899, 2.866126",\
+ "1.120914, 1.370034, 1.645345, 2.108016, 3.034243",\
+ "1.702827, 1.951940, 2.227243, 2.689913, 3.616137",\
+ "0.931927, 1.189224, 1.463507, 1.925837, 2.851398",\
+ "0.973680, 1.230977, 1.505260, 1.967589, 2.893151",\
+ "1.033610, 1.290907, 1.565190, 2.027519, 2.953081",\
+ "1.201727, 1.459024, 1.733307, 2.195637, 3.121198",\
+ "1.783640, 2.040930, 2.315206, 2.777534, 3.703092",\
+ "0.989567, 1.254871, 1.527646, 1.989749, 2.914907",\
+ "1.031319, 1.296623, 1.569398, 2.031502, 2.956660",\
+ "1.091250, 1.356553, 1.629329, 2.091432, 3.016590",\
+ "1.259367, 1.524671, 1.797446, 2.259549, 3.184707",\
+ "1.841280, 2.106576, 2.379344, 2.841446, 3.766601",\
+ "1.324649, 1.619500, 1.879453, 2.339067, 3.260363",\
+ "1.366401, 1.661253, 1.921206, 2.380819, 3.302116",\
+ "1.426332, 1.721183, 1.981136, 2.440749, 3.362046",\
+ "1.594449, 1.889300, 2.149253, 2.608866, 3.530163",\
+ "2.176360, 2.471204, 2.731152, 3.190763, 4.112057");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2432*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[26]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.602525, 0.840752, 1.118848, 1.606867, 2.582905",\
+ "0.636915, 0.875142, 1.153247, 1.641296, 2.617393",\
+ "0.708158, 0.946386, 1.224478, 1.712482, 2.688491",\
+ "0.962324, 1.200552, 1.478688, 1.966845, 2.943158",\
+ "1.886897, 2.125118, 2.403212, 2.891220, 3.867236",\
+ "0.689934, 0.928280, 1.206475, 1.693581, 2.668839",\
+ "0.724325, 0.962670, 1.240873, 1.728010, 2.703327",\
+ "0.795567, 1.033914, 1.312104, 1.799197, 2.774425",\
+ "1.049734, 1.288080, 1.566315, 2.053559, 3.029092",\
+ "1.974307, 2.212646, 2.490838, 2.977934, 3.953170",\
+ "0.770795, 1.017206, 1.294439, 1.781203, 2.755794",\
+ "0.805185, 1.051596, 1.328838, 1.815632, 2.790282",\
+ "0.876428, 1.122840, 1.400069, 1.886818, 2.861380",\
+ "1.130594, 1.377006, 1.654280, 2.141181, 3.116047",\
+ "2.055167, 2.301572, 2.578803, 3.065556, 4.040125",\
+ "0.828465, 1.082761, 1.358582, 1.845116, 2.819303",\
+ "0.862855, 1.117151, 1.392981, 1.879545, 2.853791",\
+ "0.934098, 1.188395, 1.464212, 1.950732, 2.924889",\
+ "1.188264, 1.442561, 1.718422, 2.205094, 3.179556",\
+ "2.112837, 2.367127, 2.642946, 3.129469, 4.103634",\
+ "1.149414, 1.446227, 1.710642, 2.194541, 3.164759",\
+ "1.183804, 1.480617, 1.745041, 2.228970, 3.199247",\
+ "1.255047, 1.551860, 1.816271, 2.300156, 3.270345",\
+ "1.509214, 1.806027, 2.070484, 2.554519, 3.525012",\
+ "2.433782, 2.730593, 2.995005, 3.478894, 4.449090");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\
+ "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\
+ "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\
+ "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\
+ "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\
+ "2.464362, 2.464362, 2.464362, 2.464362, 2.464362");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.634287, 0.872507, 1.150200, 1.636823, 2.610071",\
+ "0.676039, 0.914259, 1.192001, 1.678792, 2.652375",\
+ "0.735970, 0.974190, 1.251983, 1.738955, 2.712900",\
+ "0.904087, 1.142307, 1.420172, 1.907391, 2.881829",\
+ "1.486003, 1.724197, 2.002198, 2.489875, 3.465229",\
+ "0.721696, 0.960035, 1.237821, 1.723538, 2.696005",\
+ "0.763449, 1.001787, 1.279623, 1.765507, 2.738309",\
+ "0.823379, 1.061718, 1.339606, 1.825670, 2.798834",\
+ "0.991496, 1.229835, 1.507796, 1.994106, 2.967763",\
+ "1.573412, 1.811725, 2.089823, 2.576589, 3.551162",\
+ "0.802557, 1.048961, 1.325786, 1.811159, 2.782960",\
+ "0.844309, 1.090713, 1.367588, 1.853128, 2.825264",\
+ "0.904240, 1.150644, 1.427571, 1.913292, 2.885789",\
+ "1.072357, 1.318761, 1.595761, 2.081728, 3.054718",\
+ "1.654273, 1.900651, 2.177788, 2.664211, 3.638118",\
+ "0.860227, 1.114515, 1.389929, 1.875073, 2.846469",\
+ "0.901979, 1.156268, 1.431731, 1.917042, 2.888773",\
+ "0.961910, 1.216198, 1.491714, 1.977205, 2.949298",\
+ "1.130027, 1.384316, 1.659903, 2.145641, 3.118227",\
+ "1.711942, 1.966206, 2.241930, 2.728124, 3.701627",\
+ "1.181171, 1.477981, 1.741974, 2.224492, 3.191925",\
+ "1.222923, 1.519734, 1.783778, 2.266461, 3.234229",\
+ "1.282854, 1.579664, 1.843763, 2.326625, 3.294754",\
+ "1.450971, 1.747782, 2.011955, 2.495062, 3.463683",\
+ "2.032870, 2.329673, 2.593987, 3.077547, 4.047082");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494119, 1.494120, 1.494126, 1.494136");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2526*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[28]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.555636, 0.806104, 1.084905, 1.584821, 2.584653",\
+ "0.590029, 0.840498, 1.119303, 1.619235, 2.619098",\
+ "0.661266, 0.911734, 1.190528, 1.690421, 2.690205",\
+ "0.915433, 1.165901, 1.444770, 1.944926, 2.945236",\
+ "1.840038, 2.090508, 2.369324, 2.869289, 3.869217",\
+ "0.643048, 0.893609, 1.172570, 1.671536, 2.670587",\
+ "0.677441, 0.928003, 1.206968, 1.705950, 2.705032",\
+ "0.748679, 0.999240, 1.278193, 1.777135, 2.776139",\
+ "1.002845, 1.253406, 1.532436, 2.031641, 3.031170",\
+ "1.927450, 2.178014, 2.456990, 2.956004, 3.955151",\
+ "0.723905, 0.982497, 1.260536, 1.759158, 2.757542",\
+ "0.758298, 1.016890, 1.294935, 1.793572, 2.791987",\
+ "0.829535, 1.088127, 1.366160, 1.864758, 2.863094",\
+ "1.083702, 1.342294, 1.620402, 2.119263, 3.118125",\
+ "2.008307, 2.266901, 2.544956, 3.043626, 4.042106",\
+ "0.781799, 1.047996, 1.324681, 1.823071, 2.821051",\
+ "0.816193, 1.082390, 1.359079, 1.857485, 2.855496",\
+ "0.887430, 1.153626, 1.430304, 1.928671, 2.926603",\
+ "1.141596, 1.407793, 1.684547, 2.183176, 3.181634",\
+ "2.066201, 2.332401, 2.609101, 3.107539, 4.105615",\
+ "1.114657, 1.410772, 1.676864, 2.172549, 3.166507",\
+ "1.149050, 1.445166, 1.711262, 2.206963, 3.200952",\
+ "1.220287, 1.516402, 1.782487, 2.278148, 3.272059",\
+ "1.474454, 1.770569, 2.036732, 2.532654, 3.527090",\
+ "2.399059, 2.695177, 2.961284, 3.457017, 4.451071");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\
+ "2.465173, 2.465199, 2.466091, 2.469060, 2.474999",\
+ "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\
+ "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\
+ "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\
+ "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\
+ "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\
+ "2.465173, 2.465200, 2.466101, 2.469060, 2.474999",\
+ "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083751, 0.083752, 0.083762, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692768, 0.692812, 0.692941, 0.693203",\
+ "2.465173, 2.465210, 2.466131, 2.469072, 2.474999");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.587433, 0.837905, 1.116317, 1.614875, 2.611990",\
+ "0.629185, 0.879656, 1.158119, 1.656853, 2.654322",\
+ "0.689115, 0.939586, 1.218100, 1.717010, 2.714829",\
+ "0.857231, 1.107703, 1.386286, 1.885441, 2.883749",\
+ "1.439262, 1.689742, 1.968444, 2.467987, 3.467073",\
+ "0.674846, 0.925410, 1.203978, 1.701590, 2.697924",\
+ "0.716597, 0.967161, 1.245781, 1.743568, 2.740255",\
+ "0.776528, 1.027092, 1.305762, 1.803725, 2.800763",\
+ "0.944644, 1.195208, 1.473949, 1.972156, 2.969683",\
+ "1.526675, 1.777247, 2.056108, 2.554702, 3.553007",\
+ "0.755703, 1.014297, 1.291944, 1.789212, 2.784879",\
+ "0.797454, 1.056048, 1.333747, 1.831190, 2.827210",\
+ "0.857384, 1.115979, 1.393728, 1.891347, 2.887718",\
+ "1.025501, 1.284095, 1.561916, 2.059778, 3.056638",\
+ "1.607531, 1.866135, 2.144074, 2.642324, 3.639962",\
+ "0.813597, 1.079797, 1.356089, 1.853126, 2.848388",\
+ "0.855349, 1.121548, 1.397891, 1.895104, 2.890719",\
+ "0.915279, 1.181478, 1.457873, 1.955260, 2.951227",\
+ "1.083395, 1.349595, 1.626060, 2.123692, 3.120147",\
+ "1.665427, 1.931634, 2.208219, 2.706238, 3.703471",\
+ "1.146455, 1.442573, 1.708257, 2.202597, 3.193844",\
+ "1.188207, 1.484324, 1.750062, 2.244576, 3.236176",\
+ "1.248137, 1.544255, 1.810045, 2.304733, 3.296683",\
+ "1.416253, 1.712371, 1.978235, 2.473166, 3.465603",\
+ "1.998287, 2.294412, 2.560398, 3.055713, 4.048927");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\
+ "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\
+ "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\
+ "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\
+ "0.045876, 0.045874, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155802, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2616*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[30]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.634427, 0.872697, 1.149292, 1.635475, 2.607842",\
+ "0.668851, 0.907120, 1.183712, 1.669888, 2.642240",\
+ "0.739833, 0.978100, 1.254713, 1.740957, 2.713446",\
+ "0.993985, 1.232251, 1.508868, 1.995127, 2.967646",\
+ "1.919059, 2.157313, 2.433878, 2.919960, 3.892124",\
+ "0.721829, 0.960233, 1.236908, 1.722188, 2.693776",\
+ "0.756252, 0.994656, 1.271329, 1.756601, 2.728174",\
+ "0.827235, 1.065637, 1.342330, 1.827670, 2.799379",\
+ "1.081387, 1.319787, 1.596485, 2.081840, 3.053579",\
+ "2.006460, 2.244850, 2.521494, 3.006673, 3.978058",\
+ "0.802677, 1.049143, 1.324872, 1.809809, 2.780731",\
+ "0.837101, 1.083566, 1.359292, 1.844222, 2.815129",\
+ "0.908083, 1.154546, 1.430293, 1.915291, 2.886334",\
+ "1.162235, 1.408697, 1.684448, 2.169461, 3.140534",\
+ "2.087309, 2.333760, 2.609457, 3.094293, 4.065013",\
+ "0.860401, 1.114674, 1.389014, 1.873721, 2.844240",\
+ "0.894825, 1.149096, 1.423434, 1.908134, 2.878638",\
+ "0.965807, 1.220077, 1.494435, 1.979203, 2.949843",\
+ "1.219959, 1.474228, 1.748591, 2.233373, 3.204043",\
+ "2.145033, 2.399290, 2.673600, 3.158206, 4.128522",\
+ "1.188527, 1.477957, 1.741051, 2.223131, 3.189696",\
+ "1.222950, 1.512379, 1.775471, 2.257544, 3.224094",\
+ "1.293931, 1.583360, 1.846473, 2.328613, 3.295300",\
+ "1.548083, 1.837511, 2.100628, 2.582783, 3.549500",\
+ "2.473149, 2.762573, 3.025636, 3.507615, 4.473978");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.034240, 0.034240, 0.034242, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083588, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\
+ "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\
+ "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\
+ "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\
+ "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.661467, 0.899737, 1.176348, 1.662586, 2.635063",\
+ "0.703763, 0.942033, 1.218582, 1.704611, 2.676670",\
+ "0.764325, 1.002595, 1.279082, 1.764899, 2.736534",\
+ "0.933255, 1.171525, 1.447944, 1.933534, 2.904712",\
+ "1.516509, 1.754779, 2.031088, 2.516304, 3.486737",\
+ "0.748868, 0.987273, 1.263965, 1.749299, 2.720997",\
+ "0.791164, 1.029569, 1.306198, 1.791324, 2.762603",\
+ "0.851727, 1.090131, 1.366697, 1.851612, 2.822468",\
+ "1.020657, 1.259062, 1.535559, 2.020247, 2.990646",\
+ "1.603910, 1.842315, 2.118701, 2.603017, 3.572671",\
+ "0.829717, 1.076183, 1.351928, 1.836920, 2.807952",\
+ "0.872012, 1.118479, 1.394161, 1.878945, 2.849558",\
+ "0.932575, 1.179041, 1.454660, 1.939233, 2.909423",\
+ "1.101505, 1.347972, 1.623522, 2.107867, 3.077601",\
+ "1.684759, 1.931225, 2.206665, 2.690638, 3.659626",\
+ "0.887441, 1.141714, 1.416070, 1.900832, 2.871461",\
+ "0.929737, 1.184009, 1.458303, 1.942857, 2.913067",\
+ "0.990299, 1.244572, 1.518803, 2.003145, 2.972932",\
+ "1.159229, 1.413502, 1.687665, 2.171780, 3.141110",\
+ "1.742483, 1.996755, 2.270807, 2.754550, 3.723135",\
+ "1.215567, 1.504997, 1.768108, 2.250242, 3.216917",\
+ "1.257862, 1.547292, 1.810339, 2.292266, 3.258523",\
+ "1.318425, 1.607855, 1.870836, 2.352553, 3.318388",\
+ "1.487355, 1.776785, 2.039696, 2.521187, 3.486566",\
+ "2.070609, 2.360038, 2.622834, 3.103956, 4.068591");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\
+ "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\
+ "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\
+ "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\
+ "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2722*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[36]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.584050, 0.834549, 1.112490, 1.609591, 2.603792",\
+ "0.618482, 0.868982, 1.146923, 1.644024, 2.638226",\
+ "0.689476, 0.939977, 1.217929, 1.715062, 2.709330",\
+ "0.943640, 1.194143, 1.472115, 1.969317, 2.963722",\
+ "1.868820, 2.119334, 2.397313, 2.894526, 3.888954",\
+ "0.671463, 0.922054, 1.200147, 1.696306, 2.689726",\
+ "0.705894, 0.956486, 1.234580, 1.730739, 2.724160",\
+ "0.776888, 1.027482, 1.305585, 1.801777, 2.795263",\
+ "1.031053, 1.281648, 1.559772, 2.056032, 3.049656",\
+ "1.956232, 2.206839, 2.484970, 2.981241, 3.974888",\
+ "0.752319, 1.010941, 1.288113, 1.783928, 2.776681",\
+ "0.786751, 1.045373, 1.322546, 1.818361, 2.811115",\
+ "0.857745, 1.116369, 1.393551, 1.889400, 2.882218",\
+ "1.111909, 1.370534, 1.647738, 2.143654, 3.136611",\
+ "2.037089, 2.295726, 2.572936, 3.068864, 4.061843",\
+ "0.810059, 1.076439, 1.352257, 1.847842, 2.840190",\
+ "0.844490, 1.110871, 1.386690, 1.882275, 2.874624",\
+ "0.915485, 1.181867, 1.457695, 1.953313, 2.945727",\
+ "1.169649, 1.436033, 1.711882, 2.207568, 3.200120",\
+ "2.094831, 2.361224, 2.637080, 3.132777, 4.125352",\
+ "1.143033, 1.439203, 1.704411, 2.197307, 3.185646",\
+ "1.177464, 1.473635, 1.738844, 2.231740, 3.220080",\
+ "1.248459, 1.544631, 1.809850, 2.302778, 3.291183",\
+ "1.502625, 1.798797, 2.064037, 2.557034, 3.545576",\
+ "2.427809, 2.723989, 2.989235, 3.482243, 4.470808");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\
+ "0.083583, 0.083586, 0.083606, 0.083665, 0.083782",\
+ "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470758, 2.470775, 2.471205, 2.472677, 2.475621",\
+ "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\
+ "0.083583, 0.083586, 0.083607, 0.083665, 0.083782",\
+ "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470758, 2.470775, 2.471210, 2.472677, 2.475621",\
+ "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\
+ "0.083583, 0.083586, 0.083607, 0.083665, 0.083782",\
+ "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470758, 2.470775, 2.471210, 2.472677, 2.475621",\
+ "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\
+ "0.083583, 0.083586, 0.083607, 0.083665, 0.083782",\
+ "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470760, 2.470775, 2.471210, 2.472677, 2.475621",\
+ "0.034240, 0.034242, 0.034251, 0.034278, 0.034331",\
+ "0.083584, 0.083587, 0.083607, 0.083665, 0.083782",\
+ "0.208067, 0.208070, 0.208086, 0.208132, 0.208225",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470765, 2.470777, 2.471225, 2.472683, 2.475621");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.611087, 0.861585, 1.139535, 1.636665, 2.630925",\
+ "0.653383, 0.903882, 1.181783, 1.678745, 2.672669",\
+ "0.713946, 0.964444, 1.242285, 1.739034, 2.732533",\
+ "0.882876, 1.133375, 1.411144, 1.907646, 2.900649",\
+ "1.466128, 1.716626, 1.994359, 2.490734, 3.483483",\
+ "0.698499, 0.949090, 1.227192, 1.723380, 2.716859",\
+ "0.740795, 0.991387, 1.269439, 1.765460, 2.758603",\
+ "0.801358, 1.051949, 1.329940, 1.825749, 2.818467",\
+ "0.970289, 1.220880, 1.498799, 1.994361, 2.986582",\
+ "1.553540, 1.804131, 2.082013, 2.577449, 3.569417",\
+ "0.779356, 1.037977, 1.315158, 1.811002, 2.803814",\
+ "0.821652, 1.080273, 1.357405, 1.853082, 2.845558",\
+ "0.882215, 1.140836, 1.417906, 1.913371, 2.905422",\
+ "1.051145, 1.309767, 1.586765, 2.081983, 3.073537",\
+ "1.634397, 1.893018, 2.169979, 2.665071, 3.656372",\
+ "0.837095, 1.103475, 1.379302, 1.874916, 2.867323",\
+ "0.879392, 1.145772, 1.421550, 1.916996, 2.909067",\
+ "0.939954, 1.206334, 1.482050, 1.977285, 2.968931",\
+ "1.108885, 1.375265, 1.650909, 2.145896, 3.137046",\
+ "1.692136, 1.958516, 2.234123, 2.728984, 3.719881",\
+ "1.170069, 1.466239, 1.731456, 2.224381, 3.212779",\
+ "1.212365, 1.508535, 1.773702, 2.266461, 3.254523",\
+ "1.272928, 1.569098, 1.834201, 2.326749, 3.314387",\
+ "1.441859, 1.738029, 2.003057, 2.495359, 3.482502",\
+ "2.025110, 2.321280, 2.586270, 3.078447, 4.065337");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\
+ "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\
+ "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\
+ "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\
+ "1.498064, 1.498063, 1.498061, 1.498051, 1.498033",\
+ "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\
+ "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\
+ "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\
+ "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\
+ "1.498064, 1.498063, 1.498060, 1.498051, 1.498033",\
+ "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\
+ "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\
+ "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\
+ "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\
+ "1.498064, 1.498063, 1.498060, 1.498051, 1.498033",\
+ "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\
+ "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\
+ "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\
+ "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\
+ "1.498064, 1.498063, 1.498060, 1.498051, 1.498033",\
+ "0.045858, 0.045858, 0.045856, 0.045847, 0.045830",\
+ "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\
+ "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\
+ "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\
+ "1.498063, 1.498063, 1.498060, 1.498051, 1.498033");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2499*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[38]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.576605, 0.831535, 1.088524, 1.527728, 2.406135",\
+ "0.611028, 0.865958, 1.122948, 1.562156, 2.440572",\
+ "0.682011, 0.936939, 1.193932, 1.633147, 2.511575",\
+ "0.936163, 1.191091, 1.448086, 1.887307, 2.765749",\
+ "1.861240, 2.116160, 2.373173, 2.812451, 3.691008",\
+ "0.664013, 0.919020, 1.175996, 1.614442, 2.492069",\
+ "0.698437, 0.953443, 1.210420, 1.648871, 2.526506",\
+ "0.769419, 1.024424, 1.281404, 1.719861, 2.597509",\
+ "1.023571, 1.278576, 1.535558, 1.974021, 2.851683",\
+ "1.948648, 2.203645, 2.460645, 2.899166, 3.776942",\
+ "0.751657, 1.007845, 1.263958, 1.702063, 2.579024",\
+ "0.786080, 1.042268, 1.298382, 1.736492, 2.613461",\
+ "0.857063, 1.113249, 1.369366, 1.807482, 2.684464",\
+ "1.111215, 1.367401, 1.623520, 2.061643, 2.938638",\
+ "2.036291, 2.292470, 2.548607, 2.986787, 3.863897",\
+ "0.814841, 1.073252, 1.328092, 1.765976, 2.642533",\
+ "0.849265, 1.107675, 1.362517, 1.800405, 2.676970",\
+ "0.920247, 1.178657, 1.433500, 1.871395, 2.747973",\
+ "1.174399, 1.432808, 1.687654, 2.125556, 3.002147",\
+ "2.099474, 2.357878, 2.612742, 3.050700, 3.927406",\
+ "1.148308, 1.435007, 1.679656, 2.115198, 2.987988",\
+ "1.182731, 1.469430, 1.714081, 2.149627, 3.022426",\
+ "1.253713, 1.540412, 1.785064, 2.220617, 3.093429",\
+ "1.507865, 1.794564, 2.039218, 2.474777, 3.347603",\
+ "2.432936, 2.719633, 2.964306, 3.399922, 4.272861");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208076, 0.208111, 0.208180",\
+ "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470714, 2.471298, 2.472467",\
+ "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\
+ "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470715, 2.471298, 2.472467",\
+ "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\
+ "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\
+ "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\
+ "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\
+ "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\
+ "0.693294, 0.693297, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470721, 2.471301, 2.472467");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.603644, 0.858574, 1.115563, 1.554765, 2.433169",\
+ "0.645940, 0.900870, 1.157859, 1.597061, 2.475466",\
+ "0.706502, 0.961433, 1.218421, 1.657624, 2.536028",\
+ "0.875433, 1.130363, 1.387352, 1.826554, 2.704960",\
+ "1.458686, 1.713616, 1.970605, 2.409806, 3.288209",\
+ "0.691052, 0.946059, 1.203035, 1.641479, 2.519103",\
+ "0.733348, 0.988355, 1.245331, 1.683775, 2.561400",\
+ "0.793911, 1.048918, 1.305893, 1.744338, 2.621962",\
+ "0.962841, 1.217848, 1.474824, 1.913269, 2.790894",\
+ "1.546094, 1.801101, 2.058077, 2.496521, 3.374143",\
+ "0.778696, 1.034884, 1.290997, 1.729101, 2.606058",\
+ "0.820992, 1.077180, 1.333292, 1.771397, 2.648355",\
+ "0.881555, 1.137743, 1.393855, 1.831960, 2.708917",\
+ "1.050485, 1.306673, 1.562785, 2.000890, 2.877849",\
+ "1.633738, 1.889926, 2.146038, 2.584142, 3.461098",\
+ "0.841881, 1.100292, 1.355131, 1.793014, 2.669567",\
+ "0.884176, 1.142587, 1.397427, 1.835310, 2.711864",\
+ "0.944739, 1.203150, 1.457990, 1.895873, 2.772426",\
+ "1.113669, 1.372080, 1.626920, 2.064803, 2.941358",\
+ "1.696922, 1.955333, 2.210173, 2.648055, 3.524607",\
+ "1.175348, 1.462047, 1.706695, 2.142236, 3.015023",\
+ "1.217643, 1.504343, 1.748991, 2.184532, 3.057320",\
+ "1.278206, 1.564905, 1.809554, 2.245094, 3.117882",\
+ "1.447136, 1.733835, 1.978484, 2.414025, 3.286813",\
+ "2.030389, 2.317089, 2.561737, 2.997277, 3.870063");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\
+ "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\
+ "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\
+ "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\
+ "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2578*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[43]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.703817, 0.965190, 1.250386, 1.755046, 2.764366",\
+ "0.738210, 0.999583, 1.284779, 1.789440, 2.798762",\
+ "0.809448, 1.070821, 1.356016, 1.860676, 2.869994",\
+ "1.063614, 1.324987, 1.610183, 2.114842, 3.124160",\
+ "1.988218, 2.249590, 2.534788, 3.039459, 4.048801",\
+ "0.791226, 1.052733, 1.338065, 1.841760, 2.850300",\
+ "0.825619, 1.087126, 1.372458, 1.876155, 2.884696",\
+ "0.896857, 1.158363, 1.443695, 1.947390, 2.955927",\
+ "1.151023, 1.412530, 1.697862, 2.201556, 3.210094",\
+ "2.075627, 2.337133, 2.622467, 3.126173, 4.134735",\
+ "0.874336, 1.141692, 1.426031, 1.929382, 2.937255",\
+ "0.908729, 1.176085, 1.460424, 1.963776, 2.971651",\
+ "0.979967, 1.247323, 1.531661, 2.035012, 3.042882",\
+ "1.234133, 1.501489, 1.785827, 2.289178, 3.297049",\
+ "2.158737, 2.426092, 2.710433, 3.213795, 4.221690",\
+ "0.937775, 1.207295, 1.490176, 1.993295, 3.000764",\
+ "0.972168, 1.241688, 1.524569, 2.027689, 3.035160",\
+ "1.043406, 1.312926, 1.595807, 2.098925, 3.106391",\
+ "1.297572, 1.567092, 1.849973, 2.353091, 3.360558",\
+ "2.222176, 2.491695, 2.774579, 3.277709, 4.285199",\
+ "1.272869, 1.571325, 1.842405, 2.342789, 3.346220",\
+ "1.307262, 1.605718, 1.876798, 2.377183, 3.380616",\
+ "1.378499, 1.676956, 1.948035, 2.448418, 3.451848",\
+ "1.632666, 1.931122, 2.202202, 2.702585, 3.706014",\
+ "2.557269, 2.855725, 3.126807, 3.627202, 4.630655");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\
+ "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\
+ "2.465101, 2.465101, 2.465179, 2.465445, 2.465979",\
+ "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\
+ "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\
+ "2.465101, 2.465101, 2.465179, 2.465445, 2.465979",\
+ "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\
+ "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\
+ "2.465101, 2.465101, 2.465179, 2.465445, 2.465979",\
+ "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\
+ "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\
+ "2.465101, 2.465101, 2.465180, 2.465445, 2.465979",\
+ "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\
+ "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692765, 0.692780, 0.692820, 0.692898",\
+ "2.465101, 2.465101, 2.465182, 2.465446, 2.465979");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.735613, 0.996985, 1.282184, 1.786857, 2.796203",\
+ "0.777364, 1.038737, 1.323936, 1.828608, 2.837953",\
+ "0.837295, 1.098667, 1.383866, 1.888539, 2.897883",\
+ "1.005411, 1.266784, 1.551982, 2.056655, 3.065999",\
+ "1.587437, 1.848807, 2.134015, 2.638729, 3.648157",\
+ "0.823022, 1.084528, 1.369863, 1.873571, 2.882137",\
+ "0.864774, 1.126280, 1.411614, 1.915322, 2.923887",\
+ "0.924704, 1.186210, 1.471545, 1.975253, 2.983817",\
+ "1.092821, 1.354327, 1.639661, 2.143369, 3.151933",\
+ "1.674846, 1.936350, 2.221694, 2.725443, 3.734090",\
+ "0.906132, 1.173487, 1.457829, 1.961193, 2.969092",\
+ "0.947883, 1.215239, 1.499580, 2.002944, 3.010842",\
+ "1.007814, 1.275169, 1.559510, 2.062875, 3.070772",\
+ "1.175930, 1.443286, 1.727627, 2.230991, 3.238888",\
+ "1.757956, 2.025309, 2.309659, 2.813065, 3.821045",\
+ "0.969571, 1.239090, 1.521974, 2.025106, 3.032601",\
+ "1.011322, 1.280842, 1.563726, 2.066857, 3.074351",\
+ "1.071253, 1.340772, 1.623656, 2.126788, 3.134281",\
+ "1.239369, 1.508889, 1.791773, 2.294904, 3.302397",\
+ "1.821394, 2.090912, 2.373805, 2.876978, 3.884554",\
+ "1.304665, 1.603120, 1.874203, 2.374600, 3.378057",\
+ "1.346416, 1.644871, 1.915954, 2.416351, 3.419807",\
+ "1.406347, 1.704802, 1.975885, 2.476281, 3.479737",\
+ "1.574463, 1.872918, 2.144001, 2.644397, 3.647853",\
+ "2.156488, 2.454941, 2.726034, 3.226472, 4.230011");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494123, 1.494129, 1.494143");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2448*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[44]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.689792, 0.930744, 1.201013, 1.654265, 2.560769",\
+ "0.724185, 0.965137, 1.235406, 1.688659, 2.595164",\
+ "0.795422, 1.036375, 1.306643, 1.759894, 2.666397",\
+ "1.049588, 1.290541, 1.560810, 2.014061, 2.920563",\
+ "1.974192, 2.215145, 2.485415, 2.938676, 3.845196",\
+ "0.777198, 1.018294, 1.288529, 1.740979, 2.646702",\
+ "0.811591, 1.052687, 1.322922, 1.775373, 2.681098",\
+ "0.882828, 1.123924, 1.394159, 1.846608, 2.752330",\
+ "1.136994, 1.378091, 1.648325, 2.100775, 3.006497",\
+ "2.061598, 2.302694, 2.572931, 3.025389, 3.931130",\
+ "0.858027, 1.107253, 1.376491, 1.828600, 2.733657",\
+ "0.892420, 1.141646, 1.410884, 1.862994, 2.768053",\
+ "0.963658, 1.212883, 1.482121, 1.934230, 2.839285",\
+ "1.217824, 1.467050, 1.736287, 2.188396, 3.093452",\
+ "2.142428, 2.391653, 2.660893, 3.113011, 4.018085",\
+ "0.915670, 1.172855, 1.440628, 1.892513, 2.797166",\
+ "0.950063, 1.207248, 1.475021, 1.926907, 2.831562",\
+ "1.021300, 1.278486, 1.546258, 1.998143, 2.902794",\
+ "1.275467, 1.532652, 1.800424, 2.252309, 3.156961",\
+ "2.200070, 2.457256, 2.725030, 3.176924, 4.081594",\
+ "1.241554, 1.536923, 1.792333, 2.241791, 3.142622",\
+ "1.275947, 1.571316, 1.826726, 2.276185, 3.177018",\
+ "1.347184, 1.642554, 1.897963, 2.347420, 3.248250",\
+ "1.601351, 1.896721, 2.152130, 2.601587, 3.502417",\
+ "2.525954, 2.821324, 3.076735, 3.526202, 4.427050");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692762, 0.692773, 0.692804, 0.692866",\
+ "2.465102, 2.465102, 2.465164, 2.465378, 2.465806",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692762, 0.692774, 0.692804, 0.692866",\
+ "2.465102, 2.465102, 2.465165, 2.465378, 2.465806",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692762, 0.692774, 0.692804, 0.692866",\
+ "2.465102, 2.465102, 2.465165, 2.465378, 2.465806",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692762, 0.692774, 0.692804, 0.692866",\
+ "2.465102, 2.465102, 2.465165, 2.465378, 2.465806",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692762, 0.692774, 0.692805, 0.692866",\
+ "2.465102, 2.465102, 2.465167, 2.465379, 2.465806");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.721587, 0.962540, 1.232811, 1.686073, 2.592597",\
+ "0.763339, 1.004291, 1.274563, 1.727824, 2.634348",\
+ "0.823269, 1.064222, 1.334493, 1.787755, 2.694278",\
+ "0.991386, 1.232338, 1.502609, 1.955871, 2.862394",\
+ "1.573411, 1.814363, 2.084642, 2.537936, 3.444525",\
+ "0.808993, 1.050089, 1.320327, 1.772787, 2.678531",\
+ "0.850745, 1.091841, 1.362078, 1.814538, 2.720282",\
+ "0.910675, 1.151771, 1.422008, 1.874469, 2.780212",\
+ "1.078792, 1.319888, 1.590125, 2.042585, 2.948328",\
+ "1.660817, 1.901912, 2.172157, 2.624650, 3.530459",\
+ "0.889823, 1.139049, 1.408289, 1.860408, 2.765486",\
+ "0.931575, 1.180800, 1.450040, 1.902159, 2.807237",\
+ "0.991505, 1.240730, 1.509970, 1.962090, 2.867167",\
+ "1.159622, 1.408847, 1.678087, 2.130206, 3.035283",\
+ "1.741647, 1.990871, 2.260119, 2.712271, 3.617414",\
+ "0.947466, 1.204651, 1.472426, 1.924321, 2.828995",\
+ "0.989217, 1.246402, 1.514177, 1.966072, 2.870746",\
+ "1.049147, 1.306333, 1.574107, 2.026003, 2.930676",\
+ "1.217264, 1.474449, 1.742224, 2.194119, 3.098792",\
+ "1.799289, 2.056473, 2.324256, 2.776184, 3.680923",\
+ "1.273350, 1.568719, 1.824131, 2.273599, 3.174451",\
+ "1.315101, 1.610470, 1.865882, 2.315350, 3.216202",\
+ "1.375032, 1.670401, 1.925813, 2.375281, 3.276132",\
+ "1.543148, 1.838517, 2.093929, 2.543397, 3.444248",\
+ "2.125174, 2.420541, 2.675962, 3.125462, 4.026379");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\
+ "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\
+ "1.494119, 1.494119, 1.494121, 1.494127, 1.494137",\
+ "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\
+ "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\
+ "1.494119, 1.494120, 1.494121, 1.494127, 1.494137",\
+ "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\
+ "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\
+ "1.494119, 1.494120, 1.494121, 1.494127, 1.494137",\
+ "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\
+ "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\
+ "1.494119, 1.494120, 1.494121, 1.494127, 1.494137",\
+ "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155803, 0.155801, 0.155793, 0.155779",\
+ "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\
+ "1.494119, 1.494120, 1.494121, 1.494127, 1.494137");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2742*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[47]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.554088, 0.796303, 1.062117, 1.540354, 2.496829",\
+ "0.588520, 0.830735, 1.096550, 1.574794, 2.531283",\
+ "0.659515, 0.901730, 1.167548, 1.645811, 2.602338",\
+ "0.913680, 1.155895, 1.421738, 1.900092, 2.856801",\
+ "1.838864, 2.081077, 2.346923, 2.825343, 3.782184",\
+ "0.641494, 0.883776, 1.149711, 1.627068, 2.582762",\
+ "0.675925, 0.918208, 1.184143, 1.661508, 2.617217",\
+ "0.746920, 0.989202, 1.255142, 1.732525, 2.688272",\
+ "1.001085, 1.243367, 1.509332, 1.986806, 2.942735",\
+ "1.926270, 2.168550, 2.434517, 2.912057, 3.868118",\
+ "0.722307, 0.972564, 1.237674, 1.714689, 2.669717",\
+ "0.756739, 1.006995, 1.272107, 1.749129, 2.704172",\
+ "0.827734, 1.077990, 1.343105, 1.820146, 2.775227",\
+ "1.081899, 1.332155, 1.597295, 2.074427, 3.029690",\
+ "2.007083, 2.257337, 2.522481, 2.999678, 3.955073",\
+ "0.781255, 1.037917, 1.301816, 1.778602, 2.733226",\
+ "0.815687, 1.072348, 1.336248, 1.813042, 2.767681",\
+ "0.886682, 1.143343, 1.407246, 1.884059, 2.838736",\
+ "1.140847, 1.397507, 1.661436, 2.138340, 3.093199",\
+ "2.066033, 2.322690, 2.586622, 3.063591, 4.018582",\
+ "1.116786, 1.399065, 1.653774, 2.127983, 3.078682",\
+ "1.151218, 1.433496, 1.688207, 2.162423, 3.113137",\
+ "1.222213, 1.504490, 1.759205, 2.233440, 3.184192",\
+ "1.476379, 1.758654, 2.013396, 2.487721, 3.438655",\
+ "2.401570, 2.683832, 2.938582, 3.412973, 4.364038");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.034240, 0.034243, 0.034261, 0.034303, 0.034388",\
+ "0.083583, 0.083591, 0.083624, 0.083701, 0.083855",\
+ "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470761, 2.470782, 2.471502, 2.473964, 2.478889",\
+ "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\
+ "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\
+ "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470761, 2.470782, 2.471509, 2.473964, 2.478889",\
+ "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\
+ "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\
+ "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470761, 2.470782, 2.471509, 2.473964, 2.478889",\
+ "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\
+ "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\
+ "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470764, 2.470782, 2.471510, 2.473964, 2.478889",\
+ "0.034240, 0.034245, 0.034262, 0.034304, 0.034388",\
+ "0.083583, 0.083594, 0.083625, 0.083701, 0.083855",\
+ "0.208066, 0.208075, 0.208100, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470774, 2.470782, 2.471535, 2.473974, 2.478889");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.581124, 0.823340, 1.089156, 1.567400, 2.523887",\
+ "0.623421, 0.865636, 1.131410, 1.609509, 2.565706",\
+ "0.683983, 0.926199, 1.191909, 1.669792, 2.625559",\
+ "0.852914, 1.095129, 1.360763, 1.838384, 2.793625",\
+ "1.436165, 1.678380, 1.944001, 2.421576, 3.376727",\
+ "0.668530, 0.910813, 1.176750, 1.654113, 2.609821",\
+ "0.710826, 0.953109, 1.219003, 1.696222, 2.651640",\
+ "0.771389, 1.013672, 1.279502, 1.756506, 2.711493",\
+ "0.940320, 1.182602, 1.448355, 1.925098, 2.879559",\
+ "1.523571, 1.765853, 2.031593, 2.508290, 3.462660",\
+ "0.749343, 0.999600, 1.264713, 1.741735, 2.696776",\
+ "0.791640, 1.041896, 1.306967, 1.783844, 2.738595",\
+ "0.852202, 1.102459, 1.367465, 1.844127, 2.798448",\
+ "1.021133, 1.271390, 1.536319, 2.012719, 2.966514",\
+ "1.604384, 1.854641, 2.119556, 2.595911, 3.549615",\
+ "0.808291, 1.064953, 1.328854, 1.805647, 2.760285",\
+ "0.850588, 1.107249, 1.371108, 1.847756, 2.802104",\
+ "0.911150, 1.167812, 1.431607, 1.908040, 2.861957",\
+ "1.080081, 1.336743, 1.600460, 2.076632, 3.030023",\
+ "1.663332, 1.919994, 2.183697, 2.659824, 3.613124",\
+ "1.143822, 1.426101, 1.680813, 2.155028, 3.105741",\
+ "1.186118, 1.468397, 1.723065, 2.197137, 3.147560",\
+ "1.246681, 1.528960, 1.783561, 2.257420, 3.207412",\
+ "1.415612, 1.697891, 1.952412, 2.426010, 3.375479",\
+ "1.998863, 2.281142, 2.535649, 3.009202, 3.958580");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\
+ "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\
+ "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\
+ "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\
+ "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\
+ "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\
+ "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\
+ "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\
+ "0.045859, 0.045859, 0.045871, 0.045908, 0.045983",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2612*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[17]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.306542, 0.508788, 0.717853, 1.042526, 1.663915",\
+ "0.340106, 0.542413, 0.751464, 1.076125, 1.697497",\
+ "0.411112, 0.613496, 0.822458, 1.147079, 1.768433",\
+ "0.665955, 0.868524, 1.077364, 1.401917, 2.023216",\
+ "1.591125, 1.794899, 2.003187, 2.327733, 2.949505",\
+ "0.395283, 0.596107, 0.805134, 1.129831, 1.751269",\
+ "0.428854, 0.629732, 0.838745, 1.163429, 1.784850",\
+ "0.499862, 0.700815, 0.909738, 1.234384, 1.855787",\
+ "0.754705, 0.955843, 1.164644, 1.489222, 2.110569",\
+ "1.679862, 1.882218, 2.090468, 2.415038, 3.036858",\
+ "0.484964, 0.676444, 0.885161, 1.209860, 1.831300",\
+ "0.518558, 0.710069, 0.918772, 1.243458, 1.864882",\
+ "0.589569, 0.781152, 0.989765, 1.314412, 1.935818",\
+ "0.844412, 1.036181, 1.244671, 1.569251, 2.190600",\
+ "1.769534, 1.962556, 2.170495, 2.495067, 3.116889",\
+ "0.543833, 0.734313, 0.942926, 1.267362, 1.888460",\
+ "0.577463, 0.767939, 0.976537, 1.300961, 1.922042",\
+ "0.648577, 0.839021, 1.047530, 1.371915, 1.992978",\
+ "0.903624, 1.094050, 1.302436, 1.626753, 2.247760",\
+ "1.830206, 2.020424, 2.228258, 2.552570, 3.174051",\
+ "0.846614, 1.039923, 1.246594, 1.570597, 2.190856",\
+ "0.880244, 1.073548, 1.280205, 1.604196, 2.224438",\
+ "0.951354, 1.144630, 1.351198, 1.675150, 2.295374",\
+ "1.206399, 1.399658, 1.606104, 1.929988, 2.550156",\
+ "2.132956, 2.326026, 2.531926, 2.855805, 3.476448");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.023786, 0.023786, 0.023786, 0.023810, 0.023868",\
+ "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\
+ "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\
+ "0.685151, 0.685311, 0.685321, 0.685321, 0.685321",\
+ "2.446158, 2.446158, 2.446667, 2.447885, 2.450424",\
+ "0.023786, 0.023786, 0.023786, 0.023810, 0.023868",\
+ "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\
+ "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\
+ "0.685156, 0.685311, 0.685321, 0.685321, 0.685321",\
+ "2.446158, 2.446158, 2.446667, 2.447885, 2.450424",\
+ "0.023786, 0.023786, 0.023786, 0.023810, 0.023868",\
+ "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\
+ "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\
+ "0.685169, 0.685311, 0.685321, 0.685321, 0.685321",\
+ "2.446158, 2.446158, 2.446667, 2.447885, 2.450424",\
+ "0.023786, 0.023786, 0.023786, 0.023810, 0.023869",\
+ "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\
+ "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\
+ "0.685155, 0.685312, 0.685321, 0.685321, 0.685321",\
+ "2.446158, 2.446158, 2.446668, 2.447888, 2.450430",\
+ "0.023786, 0.023786, 0.023786, 0.023810, 0.023869",\
+ "0.069294, 0.069294, 0.069294, 0.069316, 0.069370",\
+ "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\
+ "0.685173, 0.685316, 0.685321, 0.685321, 0.685321",\
+ "2.446158, 2.446158, 2.446668, 2.447891, 2.450438");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.300762, 0.504583, 0.713270, 1.038101, 1.660218",\
+ "0.333089, 0.537036, 0.745749, 1.070675, 1.693005",\
+ "0.383451, 0.587349, 0.796071, 1.121057, 1.743526",\
+ "0.544532, 0.748090, 0.956809, 1.281806, 1.904306",\
+ "1.125564, 1.330456, 1.540080, 1.865115, 2.486899",\
+ "0.389512, 0.591901, 0.800551, 1.125406, 1.747571",\
+ "0.421839, 0.624354, 0.833030, 1.157980, 1.780358",\
+ "0.472201, 0.674668, 0.883352, 1.208362, 1.830879",\
+ "0.633282, 0.835409, 1.044090, 1.369112, 1.991659",\
+ "1.214288, 1.417775, 1.627361, 1.952420, 2.574253",\
+ "0.479218, 0.672239, 0.880578, 1.205435, 1.827603",\
+ "0.511548, 0.704692, 0.913057, 1.238009, 1.860390",\
+ "0.561908, 0.755005, 0.963379, 1.288391, 1.910911",\
+ "0.722989, 0.915746, 1.124117, 1.449140, 2.071691",\
+ "1.303923, 1.498112, 1.707387, 2.032449, 2.654284",\
+ "0.539760, 0.730108, 0.938342, 1.262939, 1.884765",\
+ "0.572206, 0.762561, 0.970821, 1.295513, 1.917552",\
+ "0.622521, 0.812874, 1.021143, 1.345895, 1.968074",\
+ "0.783248, 0.973615, 1.181881, 1.506644, 2.128853",\
+ "1.365347, 1.555982, 1.765154, 2.089952, 2.711445",\
+ "0.842526, 1.035714, 1.242010, 1.566174, 2.187163",\
+ "0.874973, 1.068167, 1.274489, 1.598749, 2.219951",\
+ "0.925287, 1.118480, 1.324811, 1.649131, 2.270473",\
+ "1.086016, 1.279222, 1.485549, 1.809880, 2.431253",\
+ "1.668147, 1.861596, 2.068822, 2.393188, 3.013843");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.030099, 0.030091, 0.030091, 0.030077, 0.030045",\
+ "0.059380, 0.059246, 0.059238, 0.059238, 0.059238",\
+ "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\
+ "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\
+ "1.484352, 1.482541, 1.482428, 1.482428, 1.482428",\
+ "0.030099, 0.030091, 0.030091, 0.030077, 0.030045",\
+ "0.059376, 0.059246, 0.059238, 0.059238, 0.059238",\
+ "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\
+ "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\
+ "1.484298, 1.482541, 1.482428, 1.482428, 1.482428",\
+ "0.030098, 0.030091, 0.030091, 0.030077, 0.030045",\
+ "0.059366, 0.059246, 0.059238, 0.059238, 0.059238",\
+ "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\
+ "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\
+ "1.484152, 1.482541, 1.482428, 1.482428, 1.482428",\
+ "0.030099, 0.030091, 0.030091, 0.030077, 0.030045",\
+ "0.059378, 0.059246, 0.059238, 0.059238, 0.059238",\
+ "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\
+ "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\
+ "1.484315, 1.482534, 1.482428, 1.482428, 1.482428",\
+ "0.030098, 0.030091, 0.030091, 0.030077, 0.030045",\
+ "0.059362, 0.059242, 0.059238, 0.059238, 0.059238",\
+ "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\
+ "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\
+ "1.484105, 1.482485, 1.482428, 1.482428, 1.482428");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2559*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[18]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.534853, 0.754941, 0.932292, 1.220792, 1.781149",\
+ "0.576549, 0.796638, 0.973989, 1.262489, 1.822845",\
+ "0.652730, 0.872819, 1.050170, 1.338670, 1.899026",\
+ "0.908126, 1.128215, 1.305566, 1.594066, 2.154422",\
+ "1.832504, 2.052592, 2.229943, 2.518443, 3.078799",\
+ "0.623250, 0.842260, 1.019573, 1.308098, 1.868502",\
+ "0.664946, 0.883956, 1.061270, 1.349794, 1.910198",\
+ "0.741127, 0.960137, 1.137451, 1.425975, 1.986380",\
+ "0.996523, 1.215533, 1.392847, 1.681371, 2.241775",\
+ "1.920900, 2.139910, 2.317224, 2.605748, 3.166152",\
+ "0.712601, 0.922592, 1.099600, 1.388126, 1.948534",\
+ "0.754297, 0.964289, 1.141297, 1.429822, 1.990230",\
+ "0.830478, 1.040470, 1.217478, 1.506004, 2.066411",\
+ "1.085874, 1.295865, 1.472873, 1.761399, 2.321807",\
+ "2.010251, 2.220243, 2.397251, 2.685777, 3.246184",\
+ "0.776250, 0.980408, 1.157292, 1.445555, 2.005549",\
+ "0.817947, 1.022105, 1.198989, 1.487252, 2.047245",\
+ "0.894128, 1.098286, 1.275170, 1.563433, 2.123426",\
+ "1.149523, 1.353682, 1.530566, 1.818829, 2.378822",\
+ "2.073901, 2.278059, 2.454943, 2.743206, 3.303199",\
+ "1.107332, 1.285624, 1.460948, 1.748727, 2.307770",\
+ "1.149029, 1.327321, 1.502644, 1.790423, 2.349466",\
+ "1.225210, 1.403502, 1.578825, 1.866605, 2.425647",\
+ "1.480606, 1.658898, 1.834221, 2.122000, 2.681043",\
+ "2.404983, 2.583275, 2.758598, 3.046378, 3.605420");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.555098, 0.775186, 0.952537, 1.241037, 1.801394",\
+ "0.587348, 0.807436, 0.984787, 1.273287, 1.833643",\
+ "0.637660, 0.857748, 1.035099, 1.323599, 1.883955",\
+ "0.798324, 1.018412, 1.195763, 1.484263, 2.044619",\
+ "1.379457, 1.599546, 1.776897, 2.065397, 2.625753",\
+ "0.643495, 0.862505, 1.039818, 1.328343, 1.888747",\
+ "0.675744, 0.894754, 1.072068, 1.360592, 1.920997",\
+ "0.726057, 0.945067, 1.122380, 1.410905, 1.971309",\
+ "0.886720, 1.105730, 1.283044, 1.571568, 2.131973",\
+ "1.467854, 1.686864, 1.864178, 2.152702, 2.713106",\
+ "0.732846, 0.942837, 1.119845, 1.408371, 1.968779",\
+ "0.765095, 0.975087, 1.152095, 1.440621, 2.001028",\
+ "0.815408, 1.025399, 1.202407, 1.490933, 2.051341",\
+ "0.976071, 1.186063, 1.363071, 1.651597, 2.212004",\
+ "1.557205, 1.767197, 1.944205, 2.232730, 2.793138",\
+ "0.796495, 1.000653, 1.177537, 1.465801, 2.025794",\
+ "0.828745, 1.032903, 1.209787, 1.498050, 2.058043",\
+ "0.879057, 1.083215, 1.260099, 1.548362, 2.108356",\
+ "1.039721, 1.243879, 1.420763, 1.709026, 2.269019",\
+ "1.620855, 1.825013, 2.001897, 2.290160, 2.850153",\
+ "1.127577, 1.305869, 1.481193, 1.768972, 2.328015",\
+ "1.159827, 1.338119, 1.513443, 1.801222, 2.360265",\
+ "1.210139, 1.388431, 1.563755, 1.851534, 2.410577",\
+ "1.370803, 1.549095, 1.724418, 2.012197, 2.571240",\
+ "1.951937, 2.130229, 2.305552, 2.593331, 3.152374");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482977, 1.482977, 1.482976, 1.482976, 1.482976");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2577*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[23]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.256885, 0.492153, 0.681988, 0.987164, 1.577680",\
+ "0.290472, 0.525767, 0.715632, 1.020810, 1.611303",\
+ "0.361355, 0.596664, 0.786663, 1.091855, 1.682256",\
+ "0.616370, 0.851426, 1.041598, 1.346846, 1.937220",\
+ "1.541773, 1.775412, 1.968861, 2.274571, 2.863136",\
+ "0.345363, 0.579471, 0.769269, 1.074469, 1.665033",\
+ "0.378951, 0.613085, 0.802913, 1.108115, 1.698656",\
+ "0.449834, 0.683983, 0.873944, 1.179160, 1.769609",\
+ "0.704852, 0.938744, 1.128879, 1.434151, 2.024573",\
+ "1.630270, 1.862731, 2.056142, 2.361876, 2.950490",\
+ "0.434929, 0.659804, 0.849296, 1.154498, 1.745065",\
+ "0.468520, 0.693418, 0.882940, 1.188143, 1.778688",\
+ "0.539403, 0.764315, 0.953971, 1.259189, 1.849641",\
+ "0.794431, 1.019077, 1.208906, 1.514180, 2.104605",\
+ "1.719892, 1.943063, 2.136169, 2.441904, 3.030521",\
+ "0.498770, 0.717639, 0.907017, 1.211964, 1.802153",\
+ "0.532364, 0.751252, 0.940661, 1.245610, 1.835775",\
+ "0.603247, 0.822149, 1.011693, 1.316654, 1.906729",\
+ "0.858284, 1.076910, 1.266629, 1.571645, 2.161693",\
+ "1.783785, 2.000890, 2.193899, 2.499368, 3.087604",\
+ "0.836421, 1.022987, 1.210677, 1.515166, 2.104462",\
+ "0.870034, 1.056600, 1.244321, 1.548812, 2.138084",\
+ "0.940914, 1.127492, 1.315353, 1.619857, 2.209037",\
+ "1.196012, 1.382245, 1.570289, 1.874848, 2.464001",\
+ "2.121767, 2.306184, 2.497561, 2.802569, 3.389907");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454037, 2.454505, 2.455152",\
+ "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454037, 2.454505, 2.455152",\
+ "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454037, 2.454505, 2.455152",\
+ "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454039, 2.454505, 2.455154",\
+ "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454039, 2.454506, 2.455156");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.251684, 0.487150, 0.676755, 0.981685, 1.571796",\
+ "0.284092, 0.519474, 0.709133, 1.014097, 1.604246",\
+ "0.334486, 0.569802, 0.759438, 1.064423, 1.654643",\
+ "0.495295, 0.730692, 0.920083, 1.225063, 1.815495",\
+ "1.076466, 1.311284, 1.500832, 1.805703, 2.395659",\
+ "0.340147, 0.574468, 0.764036, 1.068990, 1.659150",\
+ "0.372555, 0.606792, 0.796414, 1.101402, 1.691600",\
+ "0.422950, 0.657120, 0.846719, 1.151728, 1.741997",\
+ "0.583764, 0.818010, 1.007364, 1.312368, 1.902848",\
+ "1.164940, 1.398602, 1.588113, 1.893008, 2.483012",\
+ "0.429671, 0.654801, 0.844063, 1.149019, 1.739182",\
+ "0.462080, 0.687125, 0.876441, 1.181431, 1.771631",\
+ "0.512476, 0.737453, 0.926746, 1.231757, 1.822028",\
+ "0.673307, 0.898343, 1.087391, 1.392396, 1.982880",\
+ "1.254498, 1.478935, 1.668140, 1.973037, 2.563044",\
+ "0.493473, 0.712635, 0.901784, 1.206484, 1.796268",\
+ "0.525883, 0.744960, 0.934162, 1.238896, 1.828718",\
+ "0.576281, 0.795287, 0.984467, 1.289223, 1.879116",\
+ "0.737126, 0.956178, 1.145111, 1.449862, 2.039968",\
+ "1.318331, 1.536764, 1.725861, 2.030502, 2.620130",\
+ "0.830874, 1.017982, 1.205444, 1.509686, 2.098576",\
+ "0.863289, 1.050307, 1.237822, 1.542099, 2.131026",\
+ "0.913697, 1.100635, 1.288127, 1.592425, 2.181424",\
+ "1.074636, 1.261533, 1.448771, 1.753065, 2.342276",\
+ "1.655932, 1.842073, 2.029521, 2.333704, 2.922437");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417990, 0.418302",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\
+ "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417990, 0.418302",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\
+ "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417990, 0.418302",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\
+ "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\
+ "0.030092, 0.030092, 0.030092, 0.030171, 0.030364",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2320*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[24]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.514526, 0.752428, 0.939979, 1.239804, 1.819405",\
+ "0.556223, 0.794124, 0.981676, 1.281500, 1.861101",\
+ "0.632404, 0.870306, 1.057857, 1.357682, 1.937282",\
+ "0.887800, 1.125701, 1.313253, 1.613077, 2.192678",\
+ "1.812177, 2.050079, 2.237630, 2.537455, 3.117055",\
+ "0.602829, 0.839746, 1.027260, 1.327109, 1.906758",\
+ "0.644526, 0.881442, 1.068957, 1.368805, 1.948454",\
+ "0.720707, 0.957623, 1.145138, 1.444987, 2.024636",\
+ "0.976103, 1.213019, 1.400534, 1.700382, 2.280031",\
+ "1.900480, 2.137396, 2.324911, 2.624760, 3.204408",\
+ "0.692380, 0.920074, 1.107287, 1.407137, 1.986790",\
+ "0.734076, 0.961771, 1.148984, 1.448834, 2.028486",\
+ "0.810257, 1.037952, 1.225165, 1.525015, 2.104667",\
+ "1.065653, 1.293347, 1.480561, 1.780411, 2.360063",\
+ "1.990030, 2.217725, 2.404938, 2.704788, 3.284440",\
+ "0.756421, 0.977914, 1.165004, 1.464591, 2.043853",\
+ "0.798118, 1.019611, 1.206700, 1.506287, 2.085550",\
+ "0.874299, 1.095792, 1.282882, 1.582469, 2.161731",\
+ "1.129694, 1.351188, 1.538277, 1.837864, 2.417127",\
+ "2.054072, 2.275565, 2.462655, 2.762241, 3.341504",\
+ "1.095322, 1.283284, 1.468662, 1.767782, 2.346133",\
+ "1.137018, 1.324980, 1.510358, 1.809478, 2.387829",\
+ "1.213199, 1.401161, 1.586540, 1.885659, 2.464011",\
+ "1.468595, 1.656557, 1.841935, 2.141055, 2.719406",\
+ "2.392972, 2.580935, 2.766313, 3.065432, 3.643783");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.534772, 0.772673, 0.960224, 1.260049, 1.839650",\
+ "0.567021, 0.804923, 0.992474, 1.292299, 1.871899",\
+ "0.617333, 0.855235, 1.042786, 1.342611, 1.922212",\
+ "0.777997, 1.015898, 1.203450, 1.503274, 2.082875",\
+ "1.359131, 1.597032, 1.784584, 2.084409, 2.664009",\
+ "0.623075, 0.859991, 1.047505, 1.347354, 1.927003",\
+ "0.655324, 0.892240, 1.079755, 1.379604, 1.959253",\
+ "0.705636, 0.942553, 1.130067, 1.429916, 2.009565",\
+ "0.866300, 1.103216, 1.290731, 1.590580, 2.170229",\
+ "1.447434, 1.684350, 1.871865, 2.171714, 2.751363",\
+ "0.712625, 0.940319, 1.127532, 1.427382, 2.007035",\
+ "0.744874, 0.972569, 1.159782, 1.459632, 2.039284",\
+ "0.795187, 1.022881, 1.210094, 1.509944, 2.089597",\
+ "0.955850, 1.183545, 1.370758, 1.670608, 2.250260",\
+ "1.536984, 1.764679, 1.951892, 2.251742, 2.831394",\
+ "0.776666, 0.998159, 1.185249, 1.484836, 2.064098",\
+ "0.808916, 1.030409, 1.217499, 1.517086, 2.096348",\
+ "0.859228, 1.080721, 1.267811, 1.567398, 2.146660",\
+ "1.019892, 1.241385, 1.428475, 1.728061, 2.307324",\
+ "1.601026, 1.822519, 2.009609, 2.309195, 2.888458",\
+ "1.115567, 1.303529, 1.488907, 1.788027, 2.366378",\
+ "1.147816, 1.335778, 1.521157, 1.820276, 2.398628",\
+ "1.198129, 1.386091, 1.571469, 1.870589, 2.448940",\
+ "1.358792, 1.546754, 1.732133, 2.031252, 2.609604",\
+ "1.939926, 2.127888, 2.313267, 2.612386, 3.190738");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2351*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[26]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.430447, 0.665884, 0.855738, 1.160934, 1.751473",\
+ "0.472143, 0.707581, 0.897435, 1.202631, 1.793169",\
+ "0.548324, 0.783762, 0.973616, 1.278812, 1.869350",\
+ "0.803720, 1.039157, 1.229011, 1.534208, 2.124746",\
+ "1.728097, 1.963542, 2.153391, 2.458586, 3.049126",\
+ "0.518928, 0.753203, 0.943019, 1.248240, 1.838826",\
+ "0.560625, 0.794899, 0.984715, 1.289936, 1.880523",\
+ "0.636806, 0.871080, 1.060897, 1.366117, 1.956704",\
+ "0.892201, 1.126475, 1.316292, 1.621513, 2.212099",\
+ "1.816579, 2.050861, 2.240672, 2.545891, 3.136479",\
+ "0.608483, 0.833536, 1.023046, 1.328268, 1.918858",\
+ "0.650179, 0.875232, 1.064742, 1.369964, 1.960554",\
+ "0.726361, 0.951413, 1.140924, 1.446146, 2.036736",\
+ "0.981756, 1.206808, 1.396319, 1.701541, 2.292131",\
+ "1.906135, 2.131194, 2.320698, 2.625919, 3.216511",\
+ "0.672303, 0.891371, 1.080767, 1.385734, 1.975946",\
+ "0.713999, 0.933067, 1.122464, 1.427431, 2.017642",\
+ "0.790181, 1.009248, 1.198645, 1.503612, 2.093823",\
+ "1.045576, 1.264643, 1.454041, 1.759007, 2.349219",\
+ "1.969955, 2.189029, 2.378420, 2.683385, 3.273599",\
+ "1.009821, 1.196720, 1.384428, 1.688937, 2.278255",\
+ "1.051517, 1.238416, 1.426124, 1.730633, 2.319951",\
+ "1.127699, 1.314597, 1.502305, 1.806814, 2.396132",\
+ "1.383094, 1.569992, 1.757701, 2.062210, 2.651528",\
+ "2.307477, 2.494378, 2.682080, 2.986588, 3.575908");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\
+ "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\
+ "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\
+ "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\
+ "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\
+ "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\
+ "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\
+ "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\
+ "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\
+ "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\
+ "2.455200, 2.455200, 2.455201, 2.455201, 2.455201");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.450692, 0.686130, 0.875983, 1.181180, 1.771718",\
+ "0.482941, 0.718379, 0.908233, 1.213429, 1.803968",\
+ "0.533254, 0.768692, 0.958545, 1.263741, 1.854280",\
+ "0.693917, 0.929356, 1.119209, 1.424405, 2.014944",\
+ "1.275051, 1.510488, 1.700342, 2.005539, 2.596077",\
+ "0.539173, 0.773448, 0.963264, 1.268485, 1.859071",\
+ "0.571423, 0.805697, 0.995514, 1.300734, 1.891321",\
+ "0.621735, 0.856010, 1.045826, 1.351047, 1.941633",\
+ "0.782399, 1.016674, 1.206490, 1.511710, 2.102297",\
+ "1.363533, 1.597806, 1.787623, 2.092844, 2.683430",\
+ "0.628728, 0.853781, 1.043291, 1.348513, 1.939103",\
+ "0.660978, 0.886030, 1.075541, 1.380763, 1.971353",\
+ "0.711290, 0.936343, 1.125853, 1.431075, 2.021665",\
+ "0.871954, 1.097007, 1.286517, 1.591739, 2.182329",\
+ "1.453087, 1.678139, 1.867650, 2.172873, 2.763462",\
+ "0.692548, 0.911616, 1.101013, 1.405979, 1.996191",\
+ "0.724798, 0.943865, 1.133262, 1.438229, 2.028440",\
+ "0.775110, 0.994178, 1.183574, 1.488541, 2.078753",\
+ "0.935774, 1.154842, 1.344238, 1.649205, 2.239417",\
+ "1.516907, 1.735974, 1.925371, 2.230339, 2.820550",\
+ "1.030066, 1.216965, 1.404673, 1.709182, 2.298500",\
+ "1.062316, 1.249214, 1.436922, 1.741432, 2.330750",\
+ "1.112628, 1.299527, 1.487235, 1.791744, 2.381062",\
+ "1.273292, 1.460191, 1.647898, 1.952407, 2.541725",\
+ "1.854424, 2.041323, 2.229032, 2.533541, 3.122859");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\
+ "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\
+ "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\
+ "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\
+ "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\
+ "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\
+ "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\
+ "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\
+ "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\
+ "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\
+ "1.482976, 1.482976, 1.482976, 1.482977, 1.482979");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2670*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[28]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.408175, 0.641513, 0.827140, 1.126924, 1.707803",\
+ "0.449871, 0.683209, 0.868836, 1.168620, 1.749499",\
+ "0.526051, 0.759389, 0.945016, 1.244800, 1.825679",\
+ "0.781441, 1.014779, 1.200407, 1.500191, 2.081069",\
+ "1.705890, 1.939226, 2.124851, 2.424636, 3.005520",\
+ "0.496580, 0.728832, 0.914421, 1.214229, 1.795156",\
+ "0.538276, 0.770527, 0.956117, 1.255925, 1.836852",\
+ "0.614456, 0.846708, 1.032297, 1.332105, 1.913032",\
+ "0.869846, 1.102098, 1.287688, 1.587496, 2.168422",\
+ "1.794296, 2.026545, 2.212132, 2.511941, 3.092873",\
+ "0.585662, 0.809167, 0.994448, 1.294258, 1.875188",\
+ "0.627357, 0.850863, 1.036144, 1.335954, 1.916884",\
+ "0.703538, 0.927043, 1.112324, 1.412134, 1.993064",\
+ "0.958928, 1.182433, 1.367714, 1.667524, 2.248454",\
+ "1.883377, 2.106880, 2.292159, 2.591970, 3.172904",\
+ "0.648932, 0.866998, 1.052159, 1.351712, 1.932252",\
+ "0.690627, 0.908694, 1.093855, 1.393408, 1.973947",\
+ "0.766807, 0.984874, 1.170035, 1.469588, 2.050128",\
+ "1.022198, 1.240264, 1.425425, 1.724978, 2.305518",\
+ "1.946647, 2.164711, 2.349869, 2.649424, 3.229968",\
+ "0.982958, 1.172329, 1.355818, 1.654905, 2.234531",\
+ "1.024654, 1.214025, 1.397514, 1.696600, 2.276227",\
+ "1.100834, 1.290205, 1.473694, 1.772781, 2.352407",\
+ "1.356225, 1.545595, 1.729084, 2.028171, 2.607797",\
+ "2.280672, 2.470042, 2.653529, 2.952617, 3.532248");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.428422, 0.661761, 0.847388, 1.147172, 1.728051",\
+ "0.460669, 0.694007, 0.879634, 1.179418, 1.760297",\
+ "0.510985, 0.744323, 0.929950, 1.229734, 1.810613",\
+ "0.671649, 0.904987, 1.090614, 1.390398, 1.971277",\
+ "1.252766, 1.486104, 1.671732, 1.971516, 2.552394",\
+ "0.516828, 0.749079, 0.934668, 1.234477, 1.815404",\
+ "0.549074, 0.781326, 0.966915, 1.266723, 1.847650",\
+ "0.599390, 0.831641, 1.017231, 1.317039, 1.897966",\
+ "0.760054, 0.992305, 1.177894, 1.477703, 2.058630",\
+ "1.341171, 1.573423, 1.759013, 2.058821, 2.639747",\
+ "0.605909, 0.829414, 1.014695, 1.314505, 1.895436",\
+ "0.638156, 0.861661, 1.046942, 1.346752, 1.927682",\
+ "0.688472, 0.911977, 1.097257, 1.397068, 1.977998",\
+ "0.849135, 1.072640, 1.257921, 1.557731, 2.138662",\
+ "1.430253, 1.653758, 1.839040, 2.138849, 2.719779",\
+ "0.669179, 0.887245, 1.072406, 1.371959, 1.952499",\
+ "0.701426, 0.919492, 1.104653, 1.404206, 1.984746",\
+ "0.751741, 0.969808, 1.154969, 1.454522, 2.035062",\
+ "0.912405, 1.130471, 1.315632, 1.615185, 2.195725",\
+ "1.493523, 1.711589, 1.896750, 2.196303, 2.776842",\
+ "1.003206, 1.192577, 1.376065, 1.675152, 2.254779",\
+ "1.035452, 1.224823, 1.408312, 1.707399, 2.287025",\
+ "1.085768, 1.275139, 1.458628, 1.757715, 2.337341",\
+ "1.246432, 1.435803, 1.619291, 1.918378, 2.498005",\
+ "1.827550, 2.016920, 2.200410, 2.499496, 3.079122");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\
+ "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\
+ "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\
+ "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\
+ "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483047");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[30]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.454515, 0.687556, 0.876637, 1.181062, 1.770586",\
+ "0.496240, 0.729281, 0.918362, 1.222787, 1.812311",\
+ "0.572297, 0.805339, 0.994419, 1.298844, 1.888368",\
+ "0.827855, 1.060896, 1.249979, 1.554404, 2.143927",\
+ "1.752113, 1.985154, 2.174236, 2.478661, 3.068184",\
+ "0.542959, 0.774874, 0.963918, 1.268367, 1.857939",\
+ "0.584684, 0.816599, 1.005643, 1.310092, 1.899664",\
+ "0.660741, 0.892656, 1.081700, 1.386149, 1.975721",\
+ "0.916299, 1.148213, 1.337260, 1.641709, 2.231281",\
+ "1.840557, 2.072472, 2.261517, 2.565966, 3.155538",\
+ "0.633029, 0.855201, 1.043945, 1.348395, 1.937971",\
+ "0.674754, 0.896927, 1.085670, 1.390121, 1.979696",\
+ "0.750812, 0.972984, 1.161727, 1.466178, 2.055753",\
+ "1.006370, 1.228541, 1.417287, 1.721738, 2.311312",\
+ "1.930628, 2.152800, 2.341543, 2.645994, 3.235569",\
+ "0.697606, 0.913035, 1.101665, 1.405861, 1.995059",\
+ "0.739331, 0.954761, 1.143391, 1.447586, 2.036784",\
+ "0.815389, 1.030818, 1.219448, 1.523643, 2.112841",\
+ "1.070947, 1.286375, 1.475007, 1.779203, 2.368400",\
+ "1.995205, 2.210634, 2.399264, 2.703460, 3.292657",\
+ "1.037719, 1.218357, 1.405324, 1.709062, 2.297368",\
+ "1.079444, 1.260083, 1.447049, 1.750787, 2.339093",\
+ "1.155501, 1.336140, 1.523106, 1.826844, 2.415150",\
+ "1.411059, 1.591697, 1.778666, 2.082405, 2.670709",\
+ "2.335317, 2.515956, 2.702923, 3.006661, 3.594966");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452470, 2.452462, 2.452462, 2.452446, 2.452406",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452470, 2.452462, 2.452462, 2.452446, 2.452406");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.477114, 0.710155, 0.899236, 1.203661, 1.793185",\
+ "0.509144, 0.742185, 0.931266, 1.235691, 1.825215",\
+ "0.559532, 0.792574, 0.981654, 1.286079, 1.875603",\
+ "0.720561, 0.953603, 1.142682, 1.447107, 2.036631",\
+ "1.300536, 1.533577, 1.722657, 2.027082, 2.616606",\
+ "0.565558, 0.797473, 0.986517, 1.290966, 1.880538",\
+ "0.597588, 0.829503, 1.018547, 1.322996, 1.912568",\
+ "0.647976, 0.879891, 1.068935, 1.373384, 1.962957",\
+ "0.809005, 1.040920, 1.229963, 1.534412, 2.123985",\
+ "1.388980, 1.620895, 1.809938, 2.114387, 2.703959",\
+ "0.655628, 0.877800, 1.066544, 1.370995, 1.960570",\
+ "0.687658, 0.909830, 1.098574, 1.403025, 1.992600",\
+ "0.738047, 0.960219, 1.148962, 1.453413, 2.042988",\
+ "0.899075, 1.121248, 1.309990, 1.614440, 2.204016",\
+ "1.479050, 1.701223, 1.889965, 2.194416, 2.783991",\
+ "0.720205, 0.935634, 1.124265, 1.428460, 2.017658",\
+ "0.752235, 0.967664, 1.156295, 1.460490, 2.049688",\
+ "0.802624, 1.018053, 1.206683, 1.510878, 2.100076",\
+ "0.963652, 1.179082, 1.367711, 1.671906, 2.261104",\
+ "1.543628, 1.759057, 1.947685, 2.251881, 2.841079",\
+ "1.060318, 1.240956, 1.427923, 1.731662, 2.319967",\
+ "1.092348, 1.272986, 1.459953, 1.763692, 2.351997",\
+ "1.142736, 1.323375, 1.510341, 1.814080, 2.402385",\
+ "1.303765, 1.484404, 1.671369, 1.975107, 2.563413",\
+ "1.883740, 2.064379, 2.251344, 2.555082, 3.143388");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484505, 1.484504, 1.484504, 1.484501, 1.484493");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2361*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[36]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.425794, 0.659396, 0.844981, 1.144718, 1.725521",\
+ "0.467517, 0.701119, 0.886704, 1.186441, 1.767244",\
+ "0.543582, 0.777185, 0.962769, 1.262506, 1.843310",\
+ "0.799075, 1.032669, 1.218262, 1.518000, 2.098799",\
+ "1.723381, 1.956982, 2.142568, 2.442305, 3.023108",\
+ "0.514202, 0.746714, 0.932262, 1.232023, 1.812875",\
+ "0.555925, 0.788437, 0.973985, 1.273746, 1.854598",\
+ "0.631990, 0.864504, 1.050050, 1.349811, 1.930663",\
+ "0.887482, 1.119988, 1.305543, 1.605305, 2.186153",\
+ "1.811789, 2.044301, 2.229849, 2.529610, 3.110461",\
+ "0.603290, 0.827050, 1.012289, 1.312051, 1.892906",\
+ "0.645013, 0.868772, 1.054012, 1.353774, 1.934629",\
+ "0.721078, 0.944839, 1.130077, 1.429839, 2.010695",\
+ "0.976570, 1.200323, 1.385570, 1.685334, 2.266185",\
+ "1.900877, 2.124636, 2.309876, 2.609639, 3.190493",\
+ "0.666566, 0.884881, 1.069999, 1.369505, 1.949970",\
+ "0.708289, 0.926604, 1.111723, 1.411228, 1.991693",\
+ "0.784354, 1.002670, 1.187788, 1.487293, 2.067758",\
+ "1.039845, 1.258154, 1.443280, 1.742788, 2.323248",\
+ "1.964153, 2.182467, 2.367587, 2.667093, 3.247556",\
+ "1.000632, 1.190214, 1.373659, 1.672698, 2.252249",\
+ "1.042355, 1.231937, 1.415382, 1.714421, 2.293972",\
+ "1.118420, 1.308003, 1.491447, 1.790486, 2.370037",\
+ "1.373908, 1.563487, 1.746940, 2.045980, 2.625527",\
+ "2.298218, 2.487800, 2.671246, 2.970286, 3.549836");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199490, 0.199485, 0.199485, 0.199485, 0.199485",\
+ "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\
+ "2.452544, 2.452522, 2.452521, 2.452511, 2.452485",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199490, 0.199485, 0.199485, 0.199485, 0.199485",\
+ "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\
+ "2.452543, 2.452522, 2.452521, 2.452511, 2.452485",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199489, 0.199485, 0.199485, 0.199485, 0.199485",\
+ "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\
+ "2.452541, 2.452522, 2.452521, 2.452511, 2.452485",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199489, 0.199485, 0.199485, 0.199485, 0.199485",\
+ "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\
+ "2.452540, 2.452522, 2.452521, 2.452511, 2.452485",\
+ "0.025353, 0.025353, 0.025353, 0.025353, 0.025353",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199487, 0.199485, 0.199485, 0.199485, 0.199485",\
+ "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\
+ "2.452530, 2.452522, 2.452521, 2.452511, 2.452485");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.448384, 0.681985, 0.867571, 1.167308, 1.748111",\
+ "0.480409, 0.714010, 0.899596, 1.199333, 1.780136",\
+ "0.530816, 0.764419, 0.950003, 1.249740, 1.830544",\
+ "0.691874, 0.925480, 1.111061, 1.410797, 1.991603",\
+ "1.271848, 1.505453, 1.691034, 1.990770, 2.571576",\
+ "0.536792, 0.769304, 0.954852, 1.254613, 1.835465",\
+ "0.568817, 0.801328, 0.986877, 1.286638, 1.867489",\
+ "0.619224, 0.851737, 1.037284, 1.337045, 1.917897",\
+ "0.780282, 1.012799, 1.198342, 1.498102, 2.078956",\
+ "1.360255, 1.592772, 1.778315, 2.078075, 2.658929",\
+ "0.625880, 0.849639, 1.034879, 1.334642, 1.915496",\
+ "0.657905, 0.881663, 1.066904, 1.366667, 1.947521",\
+ "0.708312, 0.932072, 1.117311, 1.417073, 1.997929",\
+ "0.869371, 1.093134, 1.278369, 1.578131, 2.158988",\
+ "1.449344, 1.673107, 1.858342, 2.158104, 2.738961",\
+ "0.689156, 0.907470, 1.092590, 1.392096, 1.972560",\
+ "0.721181, 0.939495, 1.124615, 1.424121, 2.004584",\
+ "0.771588, 0.989904, 1.175022, 1.474527, 2.054992",\
+ "0.932647, 1.150965, 1.336080, 1.635585, 2.216051",\
+ "1.512620, 1.730939, 1.916053, 2.215558, 2.796025",\
+ "1.023221, 1.212804, 1.396249, 1.695289, 2.274839",\
+ "1.055246, 1.244828, 1.428274, 1.727314, 2.306864",\
+ "1.105654, 1.295237, 1.478681, 1.777720, 2.357271",\
+ "1.266715, 1.456299, 1.639739, 1.938777, 2.518331",\
+ "1.846688, 2.036272, 2.219712, 2.518751, 3.098304");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\
+ "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417810, 0.417803, 0.417803, 0.417799, 0.417790",\
+ "1.484519, 1.484515, 1.484514, 1.484513, 1.484508",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\
+ "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417810, 0.417803, 0.417803, 0.417799, 0.417790",\
+ "1.484518, 1.484515, 1.484514, 1.484513, 1.484508",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\
+ "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417810, 0.417803, 0.417803, 0.417799, 0.417790",\
+ "1.484518, 1.484515, 1.484514, 1.484513, 1.484508",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\
+ "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417809, 0.417803, 0.417803, 0.417799, 0.417790",\
+ "1.484518, 1.484515, 1.484514, 1.484513, 1.484508",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417806, 0.417803, 0.417803, 0.417799, 0.417790",\
+ "1.484516, 1.484515, 1.484514, 1.484513, 1.484508");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2707*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[38]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.411437, 0.641763, 0.827440, 1.121826, 1.689429",\
+ "0.453163, 0.683488, 0.869165, 1.163551, 1.731154",\
+ "0.529220, 0.759545, 0.945221, 1.239608, 1.807211",\
+ "0.784777, 1.015107, 1.200787, 1.495173, 2.062773",\
+ "1.709036, 1.939362, 2.125040, 2.419426, 2.987028",\
+ "0.499750, 0.729081, 0.914721, 1.209131, 1.776782",\
+ "0.541475, 0.770807, 0.956446, 1.250857, 1.818508",\
+ "0.617533, 0.846863, 1.032502, 1.326913, 1.894564",\
+ "0.873090, 1.102426, 1.288068, 1.582478, 2.150126",\
+ "1.797349, 2.026680, 2.212321, 2.506731, 3.074381",\
+ "0.588895, 0.809414, 0.994747, 1.289160, 1.856814",\
+ "0.630620, 0.851139, 1.036473, 1.330885, 1.898539",\
+ "0.706677, 0.927196, 1.112529, 1.406941, 1.974596",\
+ "0.962234, 1.182758, 1.368095, 1.662507, 2.230158",\
+ "1.886493, 2.107013, 2.292347, 2.586760, 3.154413",\
+ "0.652369, 0.867238, 1.052459, 1.346598, 1.913847",\
+ "0.694094, 0.908963, 1.094185, 1.388323, 1.955572",\
+ "0.770151, 0.985020, 1.170241, 1.464380, 2.031629",\
+ "1.025709, 1.240582, 1.425807, 1.719945, 2.287190",\
+ "1.949967, 2.164837, 2.350059, 2.644198, 3.211446",\
+ "0.987682, 1.172511, 1.356118, 1.649777, 2.216089",\
+ "1.029408, 1.214237, 1.397843, 1.691502, 2.257815",\
+ "1.105465, 1.290294, 1.473899, 1.767559, 2.333871",\
+ "1.361025, 1.545856, 1.729465, 2.023124, 2.589433",\
+ "2.285281, 2.470111, 2.653718, 2.947377, 3.513689");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686585, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452422");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.434036, 0.664363, 0.850040, 1.144426, 1.712028",\
+ "0.466066, 0.696393, 0.882070, 1.176457, 1.744059",\
+ "0.516455, 0.746780, 0.932457, 1.226843, 1.794446",\
+ "0.677484, 0.907807, 1.093482, 1.387868, 1.955473",\
+ "1.257459, 1.487782, 1.673457, 1.967843, 2.535448",\
+ "0.522349, 0.751681, 0.937321, 1.231731, 1.799382",\
+ "0.554379, 0.783711, 0.969351, 1.263762, 1.831412",\
+ "0.604768, 0.834099, 1.019738, 1.314148, 1.881800",\
+ "0.765797, 0.995125, 1.180763, 1.475173, 2.042827",\
+ "1.345772, 1.575100, 1.760738, 2.055148, 2.622802",\
+ "0.611494, 0.832013, 1.017348, 1.311760, 1.879413",\
+ "0.643524, 0.864044, 1.049378, 1.343790, 1.911444",\
+ "0.693912, 0.914431, 1.099764, 1.394177, 1.961831",\
+ "0.854941, 1.075458, 1.260790, 1.555202, 2.122858",\
+ "1.434916, 1.655433, 1.840765, 2.135177, 2.702833",\
+ "0.674968, 0.889838, 1.075059, 1.369198, 1.936446",\
+ "0.706998, 0.921868, 1.107090, 1.401229, 1.968477",\
+ "0.757386, 0.972255, 1.157476, 1.451615, 2.018864",\
+ "0.918415, 1.133282, 1.318501, 1.612640, 2.179891",\
+ "1.498390, 1.713257, 1.898476, 2.192615, 2.759866",\
+ "1.010282, 1.195111, 1.378718, 1.672377, 2.238689",\
+ "1.042312, 1.227141, 1.410748, 1.704407, 2.270719",\
+ "1.092700, 1.277529, 1.461135, 1.754794, 2.321106",\
+ "1.253727, 1.438555, 1.622160, 1.915819, 2.482133",\
+ "1.833702, 2.018530, 2.202135, 2.495794, 3.062109");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2292*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[43]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.506400, 0.723405, 0.901534, 1.190767, 1.752239",\
+ "0.548095, 0.765101, 0.943229, 1.232462, 1.793935",\
+ "0.624275, 0.841281, 1.019409, 1.308642, 1.870115",\
+ "0.879665, 1.096670, 1.274799, 1.564032, 2.125504",\
+ "1.804122, 2.021127, 2.199255, 2.488489, 3.049961",\
+ "0.594776, 0.810723, 0.988814, 1.278072, 1.839592",\
+ "0.636472, 0.852419, 1.030510, 1.319767, 1.881288",\
+ "0.712652, 0.928599, 1.106690, 1.395947, 1.957468",\
+ "0.968041, 1.183989, 1.362080, 1.651337, 2.212858",\
+ "1.892498, 2.108445, 2.286536, 2.575794, 3.137315",\
+ "0.684027, 0.891056, 1.068841, 1.358100, 1.919624",\
+ "0.725722, 0.932752, 1.110537, 1.399796, 1.961320",\
+ "0.801902, 1.008932, 1.186717, 1.475976, 2.037500",\
+ "1.057292, 1.264322, 1.442107, 1.731366, 2.292889",\
+ "1.981749, 2.188778, 2.366563, 2.655822, 3.217346",\
+ "0.747566, 0.948873, 1.126535, 1.415531, 1.976642",\
+ "0.789261, 0.990569, 1.168231, 1.457227, 2.018338",\
+ "0.865441, 1.066749, 1.244411, 1.533407, 2.094518",\
+ "1.120831, 1.322138, 1.499801, 1.788796, 2.349907",\
+ "2.045288, 2.246595, 2.424257, 2.713253, 3.274364",\
+ "1.075492, 1.254095, 1.430191, 1.718704, 2.278866",\
+ "1.117188, 1.295791, 1.471887, 1.760399, 2.320562",\
+ "1.193368, 1.371971, 1.548067, 1.836579, 2.396742",\
+ "1.448757, 1.627361, 1.803456, 2.091969, 2.652131",\
+ "2.373214, 2.551817, 2.727913, 3.016426, 3.576588");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.526648, 0.743653, 0.921781, 1.211015, 1.772487",\
+ "0.558894, 0.775899, 0.954027, 1.243261, 1.804733",\
+ "0.609210, 0.826215, 1.004344, 1.293577, 1.855049",\
+ "0.769874, 0.986879, 1.165008, 1.454241, 2.015713",\
+ "1.350989, 1.567995, 1.746123, 2.035356, 2.596828",\
+ "0.615024, 0.830971, 1.009062, 1.298320, 1.859840",\
+ "0.647270, 0.863217, 1.041308, 1.330566, 1.892087",\
+ "0.697586, 0.913533, 1.091625, 1.380882, 1.942403",\
+ "0.858250, 1.074197, 1.252288, 1.541546, 2.103066",\
+ "1.439366, 1.655313, 1.833404, 2.122661, 2.684182",\
+ "0.704275, 0.911304, 1.089089, 1.378348, 1.939872",\
+ "0.736521, 0.943550, 1.121335, 1.410594, 1.972118",\
+ "0.786837, 0.993866, 1.171651, 1.460910, 2.022434",\
+ "0.947501, 1.154530, 1.332315, 1.621574, 2.183098",\
+ "1.528616, 1.735646, 1.913431, 2.202690, 2.764214",\
+ "0.767814, 0.969121, 1.146783, 1.435779, 1.996890",\
+ "0.800060, 1.001367, 1.179029, 1.468025, 2.029136",\
+ "0.850376, 1.051683, 1.229346, 1.518341, 2.079452",\
+ "1.011040, 1.212347, 1.390009, 1.679005, 2.240116",\
+ "1.592155, 1.793463, 1.971125, 2.260120, 2.821231",\
+ "1.095740, 1.274343, 1.450439, 1.738951, 2.299114",\
+ "1.127986, 1.306589, 1.482685, 1.771198, 2.331360",\
+ "1.178302, 1.356906, 1.533001, 1.821514, 2.381676",\
+ "1.338966, 1.517570, 1.693665, 1.982178, 2.542340",\
+ "1.920082, 2.098685, 2.274781, 2.563293, 3.123456");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2480*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[44]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.487215, 0.727664, 0.917972, 1.220770, 1.805421",\
+ "0.528910, 0.769360, 0.959668, 1.262466, 1.847117",\
+ "0.605090, 0.845540, 1.035848, 1.338646, 1.923296",\
+ "0.860480, 1.100929, 1.291238, 1.594035, 2.178686",\
+ "1.784937, 2.025386, 2.215694, 2.518492, 3.103143",\
+ "0.575514, 0.814982, 1.005253, 1.308075, 1.892774",\
+ "0.617210, 0.856678, 1.046949, 1.349771, 1.934470",\
+ "0.693390, 0.932858, 1.123129, 1.425951, 2.010650",\
+ "0.948779, 1.188247, 1.378519, 1.681340, 2.266040",\
+ "1.873236, 2.112704, 2.302975, 2.605797, 3.190496",\
+ "0.664798, 0.895313, 1.085280, 1.388104, 1.972806",\
+ "0.706493, 0.937009, 1.126976, 1.429799, 2.014502",\
+ "0.782673, 1.013189, 1.203156, 1.505979, 2.090682",\
+ "1.038063, 1.268578, 1.458545, 1.761369, 2.346071",\
+ "1.962520, 2.193035, 2.383002, 2.685826, 3.270528",\
+ "0.728479, 0.953177, 1.143002, 1.445563, 2.029881",\
+ "0.770175, 0.994873, 1.184698, 1.487259, 2.071577",\
+ "0.846355, 1.071053, 1.260878, 1.563439, 2.147756",\
+ "1.101744, 1.326442, 1.516268, 1.818828, 2.403146",\
+ "2.026201, 2.250899, 2.440724, 2.743285, 3.327603",\
+ "1.065102, 1.258723, 1.446662, 1.748759, 2.332174",\
+ "1.106798, 1.300419, 1.488358, 1.790455, 2.373869",\
+ "1.182978, 1.376599, 1.564538, 1.866635, 2.450049",\
+ "1.438367, 1.631989, 1.819927, 2.122025, 2.705439",\
+ "2.362824, 2.556445, 2.744384, 3.046481, 3.629896");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199409, 0.199409, 0.199409, 0.199410, 0.199412",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.507462, 0.747912, 0.938220, 1.241018, 1.825669",\
+ "0.539708, 0.780158, 0.970466, 1.273264, 1.857915",\
+ "0.590025, 0.830474, 1.020782, 1.323580, 1.908231",\
+ "0.750689, 0.991138, 1.181446, 1.484244, 2.068895",\
+ "1.331804, 1.572254, 1.762562, 2.065360, 2.650010",\
+ "0.595762, 0.835230, 1.025501, 1.328323, 1.913022",\
+ "0.628008, 0.867476, 1.057747, 1.360569, 1.945268",\
+ "0.678324, 0.917792, 1.108063, 1.410885, 1.995584",\
+ "0.838988, 1.078456, 1.268727, 1.571549, 2.156248",\
+ "1.420103, 1.659572, 1.849843, 2.152665, 2.737364",\
+ "0.685045, 0.915561, 1.105528, 1.408352, 1.993054",\
+ "0.717292, 0.947807, 1.137774, 1.440598, 2.025300",\
+ "0.767608, 0.998123, 1.188090, 1.490914, 2.075616",\
+ "0.928272, 1.158787, 1.348754, 1.651578, 2.236280",\
+ "1.509387, 1.739902, 1.929870, 2.232693, 2.817395",\
+ "0.748727, 0.973425, 1.163250, 1.465811, 2.050128",\
+ "0.780973, 1.005671, 1.195496, 1.498057, 2.082375",\
+ "0.831289, 1.055987, 1.245812, 1.548373, 2.132691",\
+ "0.991953, 1.216651, 1.406476, 1.709037, 2.293355",\
+ "1.573069, 1.797767, 1.987592, 2.290153, 2.874470",\
+ "1.085350, 1.278971, 1.466910, 1.769007, 2.352422",\
+ "1.117596, 1.311217, 1.499156, 1.801253, 2.384668",\
+ "1.167912, 1.361534, 1.549472, 1.851569, 2.434984",\
+ "1.328576, 1.522197, 1.710136, 2.012233, 2.595648",\
+ "1.909692, 2.103313, 2.291251, 2.593349, 3.176763");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419484, 0.419484, 0.419483, 0.419481, 0.419478",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2458*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[47]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.401855, 0.617772, 0.797138, 1.086913, 1.648811",\
+ "0.443578, 0.659495, 0.838861, 1.128636, 1.690534",\
+ "0.519643, 0.735561, 0.914927, 1.204702, 1.766600",\
+ "0.775133, 0.991049, 1.170417, 1.460191, 2.022084",\
+ "1.699442, 1.915359, 2.094725, 2.384500, 2.946397",\
+ "0.490138, 0.705090, 0.884419, 1.174218, 1.736165",\
+ "0.531861, 0.746813, 0.926142, 1.215941, 1.777887",\
+ "0.607927, 0.822879, 1.002208, 1.292007, 1.853954",\
+ "0.863417, 1.078367, 1.257698, 1.547496, 2.109437",\
+ "1.787725, 2.002677, 2.182006, 2.471805, 3.033750",\
+ "0.579402, 0.785421, 0.964446, 1.254247, 1.816196",\
+ "0.621125, 0.827144, 1.006169, 1.295970, 1.857919",\
+ "0.697191, 0.903209, 1.082235, 1.372035, 1.933985",\
+ "0.952680, 1.158697, 1.337725, 1.627524, 2.189469",\
+ "1.876989, 2.083007, 2.262033, 2.551833, 3.113782",\
+ "0.643076, 0.843251, 1.022143, 1.311678, 1.873216",\
+ "0.684799, 0.884974, 1.063866, 1.353401, 1.914939",\
+ "0.760865, 0.961040, 1.139932, 1.429467, 1.991005",\
+ "1.016354, 1.216527, 1.395422, 1.684956, 2.246489",\
+ "1.940663, 2.140838, 2.319730, 2.609265, 3.170802",\
+ "0.967710, 1.148559, 1.325799, 1.614851, 2.175443",\
+ "1.009433, 1.190282, 1.367522, 1.656574, 2.217166",\
+ "1.085498, 1.266348, 1.443587, 1.732640, 2.293232",\
+ "1.340988, 1.521835, 1.699077, 1.988128, 2.548716",\
+ "2.265296, 2.446146, 2.623385, 2.912438, 3.473029");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.424445, 0.640362, 0.819728, 1.109503, 1.671400",\
+ "0.456469, 0.672387, 0.851753, 1.141528, 1.703424",\
+ "0.506877, 0.722795, 0.902161, 1.191936, 1.753834",\
+ "0.667936, 0.883855, 1.063220, 1.352995, 1.914896",\
+ "1.247909, 1.463828, 1.643193, 1.932969, 2.494869",\
+ "0.512729, 0.727680, 0.907009, 1.196808, 1.758754",\
+ "0.544753, 0.759704, 0.939034, 1.228833, 1.790778",\
+ "0.595161, 0.810113, 0.989442, 1.279241, 1.841187",\
+ "0.756220, 0.971173, 1.150501, 1.440300, 2.002249",\
+ "1.336193, 1.551146, 1.730474, 2.020274, 2.582222",\
+ "0.601992, 0.808011, 0.987036, 1.276837, 1.838785",\
+ "0.634017, 0.840035, 1.019061, 1.308861, 1.870810",\
+ "0.684425, 0.890443, 1.069469, 1.359269, 1.921219",\
+ "0.845484, 1.051504, 1.230528, 1.520329, 2.082281",\
+ "1.425457, 1.631477, 1.810501, 2.100302, 2.662254",\
+ "0.665666, 0.865841, 1.044734, 1.334268, 1.895805",\
+ "0.697691, 0.897865, 1.076758, 1.366293, 1.927830",\
+ "0.748099, 0.948274, 1.127166, 1.416701, 1.978239",\
+ "0.909158, 1.109334, 1.288225, 1.577760, 2.139301",\
+ "1.489131, 1.689307, 1.868198, 2.157734, 2.719274",\
+ "0.990300, 1.171149, 1.348389, 1.637441, 2.198032",\
+ "1.022324, 1.203173, 1.380413, 1.669466, 2.230056",\
+ "1.072732, 1.253582, 1.430821, 1.719874, 2.280466",\
+ "1.233791, 1.414642, 1.591880, 1.880933, 2.441528",\
+ "1.813765, 1.994615, 2.171854, 2.460907, 3.021501");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2440*/
+
+} /* end of pin tl_o[8] */
+
+pin("tl_o[7]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.035370 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[7];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[18]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.763083, 1.005361, 1.270323, 1.744250, 2.692104",\
+ "0.776922, 1.019201, 1.284163, 1.758090, 2.705944",\
+ "0.800433, 1.042711, 1.307673, 1.781600, 2.729455",\
+ "1.069305, 1.311583, 1.576544, 2.050472, 2.998326",\
+ "1.663833, 1.906111, 2.171072, 2.644999, 3.592854",\
+ "0.850491, 1.092832, 1.357904, 1.830964, 2.778038",\
+ "0.864331, 1.106672, 1.371744, 1.844804, 2.791878",\
+ "0.887842, 1.130182, 1.395254, 1.868315, 2.815388",\
+ "1.156713, 1.399054, 1.664126, 2.137186, 3.084260",\
+ "1.751242, 1.993582, 2.258653, 2.731714, 3.678787",\
+ "0.931306, 1.181626, 1.445868, 1.918586, 2.864993",\
+ "0.945146, 1.195466, 1.459708, 1.932426, 2.878833",\
+ "0.968656, 1.218976, 1.483218, 1.955936, 2.902343",\
+ "1.237528, 1.487848, 1.752090, 2.224808, 3.171215",\
+ "1.832057, 2.082376, 2.346617, 2.819335, 3.765743",\
+ "0.989274, 1.246989, 1.510009, 1.982499, 2.928502",\
+ "1.003114, 1.260829, 1.523849, 1.996339, 2.942342",\
+ "1.026624, 1.284340, 1.547359, 2.019849, 2.965852",\
+ "1.295496, 1.553211, 1.816230, 2.288721, 3.234724",\
+ "1.890025, 2.147739, 2.410758, 2.883248, 3.829252",\
+ "1.322822, 1.608220, 1.861925, 2.331865, 3.273958",\
+ "1.336662, 1.622059, 1.875765, 2.345705, 3.287798",\
+ "1.360173, 1.645570, 1.899276, 2.369215, 3.311308",\
+ "1.629045, 1.914441, 2.168147, 2.638086, 3.580180",\
+ "2.223573, 2.508969, 2.762674, 3.232614, 4.174707");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\
+ "0.157856, 0.157859, 0.157877, 0.157917, 0.157996",\
+ "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\
+ "0.157856, 0.157859, 0.157877, 0.157917, 0.157996",\
+ "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\
+ "0.157856, 0.157860, 0.157877, 0.157917, 0.157996",\
+ "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\
+ "0.157856, 0.157860, 0.157877, 0.157917, 0.157996",\
+ "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129963, 0.129972, 0.129996, 0.130055, 0.130175",\
+ "0.157856, 0.157861, 0.157877, 0.157917, 0.157996",\
+ "0.203046, 0.203048, 0.203055, 0.203071, 0.203103",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.698169, 0.940449, 1.205412, 1.679339, 2.627193",\
+ "0.711314, 0.953594, 1.218557, 1.692484, 2.640338",\
+ "0.732465, 0.974745, 1.239707, 1.713634, 2.661488",\
+ "0.908675, 1.150953, 1.415913, 1.889840, 2.837695",\
+ "1.242989, 1.485267, 1.750227, 2.224154, 3.172009",\
+ "0.785578, 1.027920, 1.292994, 1.766054, 2.713127",\
+ "0.798723, 1.041065, 1.306139, 1.779198, 2.726272",\
+ "0.819874, 1.062215, 1.327289, 1.800348, 2.747422",\
+ "0.996084, 1.238424, 1.503495, 1.976555, 2.923629",\
+ "1.330398, 1.572737, 1.837808, 2.310869, 3.257943",\
+ "0.866392, 1.116714, 1.380958, 1.853675, 2.800082",\
+ "0.879538, 1.129859, 1.394103, 1.866820, 2.813227",\
+ "0.900689, 1.151010, 1.415252, 1.887970, 2.834377",\
+ "1.076899, 1.327218, 1.591458, 2.064176, 3.010584",\
+ "1.411212, 1.661532, 1.925772, 2.398490, 3.344898",\
+ "0.924360, 1.182077, 1.445098, 1.917589, 2.863591",\
+ "0.937505, 1.195222, 1.458243, 1.930733, 2.876736",\
+ "0.958657, 1.216373, 1.479393, 1.951883, 2.897886",\
+ "1.134866, 1.392581, 1.655599, 2.128089, 3.074093",\
+ "1.469180, 1.726895, 1.989913, 2.462403, 3.408407",\
+ "1.257909, 1.543308, 1.797015, 2.266954, 3.209047",\
+ "1.271054, 1.556453, 1.810160, 2.280099, 3.222192",\
+ "1.292205, 1.577603, 1.831310, 2.301249, 3.243342",\
+ "1.468415, 1.753811, 2.007515, 2.477455, 3.419549",\
+ "1.802729, 2.088125, 2.341829, 2.811769, 3.753863");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\
+ "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\
+ "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\
+ "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\
+ "1.026303, 1.026303, 1.026304, 1.026307, 1.026312",\
+ "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\
+ "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\
+ "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\
+ "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\
+ "1.026303, 1.026303, 1.026305, 1.026307, 1.026312",\
+ "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\
+ "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\
+ "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\
+ "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\
+ "1.026303, 1.026303, 1.026305, 1.026307, 1.026312",\
+ "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\
+ "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\
+ "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\
+ "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\
+ "1.026303, 1.026303, 1.026305, 1.026307, 1.026312",\
+ "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\
+ "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\
+ "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\
+ "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\
+ "1.026303, 1.026303, 1.026305, 1.026307, 1.026312");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2625*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[19]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.787208, 1.042240, 1.299016, 1.737737, 2.615179",\
+ "0.801048, 1.056080, 1.312856, 1.751576, 2.629018",\
+ "0.824558, 1.079590, 1.336366, 1.775087, 2.652528",\
+ "1.093430, 1.348462, 1.605238, 2.043957, 2.921395",\
+ "1.687959, 1.942991, 2.199766, 2.638483, 3.515917",\
+ "0.874617, 1.129725, 1.386486, 1.824451, 2.701113",\
+ "0.888456, 1.143564, 1.400326, 1.838291, 2.714952",\
+ "0.911967, 1.167075, 1.423836, 1.861801, 2.738462",\
+ "1.180839, 1.435947, 1.692708, 2.130671, 3.007329",\
+ "1.775367, 2.030476, 2.287236, 2.725197, 3.601851",\
+ "0.962301, 1.218548, 1.474448, 1.912073, 2.788068",\
+ "0.976141, 1.232388, 1.488288, 1.925912, 2.801907",\
+ "0.999652, 1.255898, 1.511798, 1.949423, 2.825417",\
+ "1.268523, 1.524770, 1.780670, 2.218293, 3.094284",\
+ "1.863052, 2.119299, 2.375198, 2.812819, 3.688806",\
+ "1.025488, 1.283954, 1.538583, 1.975986, 2.851577",\
+ "1.039328, 1.297794, 1.552423, 1.989825, 2.865416",\
+ "1.062838, 1.321304, 1.575933, 2.013336, 2.888926",\
+ "1.331710, 1.590176, 1.844805, 2.282206, 3.157793",\
+ "1.926239, 2.184705, 2.439332, 2.876732, 3.752315",\
+ "1.358969, 1.645690, 1.890142, 2.325206, 3.197033",\
+ "1.372809, 1.659530, 1.903982, 2.339045, 3.210872",\
+ "1.396320, 1.683041, 1.927492, 2.362556, 3.234382",\
+ "1.665192, 1.951913, 2.196364, 2.631425, 3.503249",\
+ "2.259720, 2.546442, 2.790892, 3.225951, 4.097771");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\
+ "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\
+ "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\
+ "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\
+ "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\
+ "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\
+ "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\
+ "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\
+ "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\
+ "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\
+ "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.722294, 0.977326, 1.234104, 1.672832, 2.550288",\
+ "0.735440, 0.990472, 1.247249, 1.685975, 2.563427",\
+ "0.756591, 1.011623, 1.268399, 1.707123, 2.584570",\
+ "0.932801, 1.187833, 1.444607, 1.883322, 2.760752",\
+ "1.267115, 1.522147, 1.778921, 2.217637, 3.095068",\
+ "0.809702, 1.064811, 1.321574, 1.759546, 2.636222",\
+ "0.822848, 1.077956, 1.334719, 1.772689, 2.649361",\
+ "0.843999, 1.099107, 1.355870, 1.793837, 2.670504",\
+ "1.020210, 1.275318, 1.532078, 1.970036, 2.846686",\
+ "1.354523, 1.609631, 1.866392, 2.304351, 3.181002",\
+ "0.897387, 1.153634, 1.409536, 1.847168, 2.723177",\
+ "0.910533, 1.166780, 1.422681, 1.860311, 2.736316",\
+ "0.931684, 1.187931, 1.443832, 1.881459, 2.757459",\
+ "1.107894, 1.364141, 1.620039, 2.057658, 2.933641",\
+ "1.442208, 1.698455, 1.954353, 2.391973, 3.267957",\
+ "0.960574, 1.219040, 1.473671, 1.911081, 2.786686",\
+ "0.973719, 1.232186, 1.486816, 1.924224, 2.799825",\
+ "0.994870, 1.253337, 1.507966, 1.945372, 2.820968",\
+ "1.171081, 1.429547, 1.684174, 2.121571, 2.997150",\
+ "1.505394, 1.763861, 2.018488, 2.455886, 3.331466",\
+ "1.294055, 1.580776, 1.825230, 2.260301, 3.132142",\
+ "1.307201, 1.593922, 1.838375, 2.273444, 3.145281",\
+ "1.328352, 1.615073, 1.859525, 2.294591, 3.166424",\
+ "1.504562, 1.791284, 2.035733, 2.470791, 3.342606",\
+ "1.838876, 2.125597, 2.370047, 2.805105, 3.676922");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\
+ "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\
+ "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\
+ "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\
+ "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\
+ "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\
+ "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\
+ "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\
+ "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\
+ "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\
+ "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\
+ "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\
+ "0.086495, 0.086495, 0.086489, 0.086470, 0.086430",\
+ "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\
+ "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026303, 1.026305, 1.026307");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2692*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[22]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.841286, 1.079720, 1.357044, 1.842422, 2.813178",\
+ "0.855126, 1.093560, 1.370884, 1.856262, 2.827017",\
+ "0.878637, 1.117071, 1.394394, 1.879772, 2.850528",\
+ "1.147509, 1.385943, 1.663266, 2.148643, 3.119398",\
+ "1.742037, 1.980471, 2.257795, 2.743171, 3.713924",\
+ "0.928696, 1.167248, 1.444662, 1.929136, 2.899111",\
+ "0.942536, 1.181088, 1.458502, 1.942976, 2.912951",\
+ "0.966046, 1.204598, 1.482012, 1.966486, 2.936461",\
+ "1.234918, 1.473470, 1.750884, 2.235358, 3.205331",\
+ "1.829447, 2.067999, 2.345412, 2.829885, 3.799858",\
+ "1.009558, 1.256174, 1.532627, 2.016758, 2.986066",\
+ "1.023398, 1.270014, 1.546467, 2.030598, 2.999906",\
+ "1.046908, 1.293524, 1.569977, 2.054108, 3.023416",\
+ "1.315780, 1.562396, 1.838849, 2.322979, 3.292286",\
+ "1.910309, 2.156925, 2.433377, 2.917507, 3.886813",\
+ "1.067230, 1.321729, 1.596769, 2.080671, 3.049575",\
+ "1.081070, 1.335569, 1.610609, 2.094511, 3.063415",\
+ "1.104580, 1.359079, 1.634119, 2.118021, 3.086925",\
+ "1.373452, 1.627951, 1.902991, 2.386893, 3.355795",\
+ "1.967981, 2.222480, 2.497520, 2.981421, 3.950322",\
+ "1.388249, 1.685192, 1.948802, 2.430085, 3.395031",\
+ "1.402089, 1.699032, 1.962642, 2.443925, 3.408871",\
+ "1.425600, 1.722542, 1.986153, 2.467435, 3.432381",\
+ "1.694472, 1.991414, 2.255024, 2.736306, 3.701252",\
+ "2.289001, 2.585943, 2.849553, 3.330834, 4.295778");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\
+ "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\
+ "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\
+ "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\
+ "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\
+ "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\
+ "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\
+ "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\
+ "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129963, 0.129963, 0.129966, 0.129977, 0.129998",\
+ "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\
+ "0.203046, 0.203046, 0.203047, 0.203049, 0.203055",\
+ "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.776372, 1.014807, 1.292131, 1.777511, 2.748272",\
+ "0.789518, 1.027952, 1.305276, 1.790656, 2.761415",\
+ "0.810669, 1.049103, 1.326427, 1.811806, 2.782563",\
+ "0.986879, 1.225313, 1.502636, 1.988012, 2.958764",\
+ "1.321193, 1.559627, 1.836950, 2.322326, 3.293078",\
+ "0.863782, 1.102334, 1.379749, 1.864226, 2.834206",\
+ "0.876927, 1.115480, 1.392894, 1.877370, 2.847349",\
+ "0.898079, 1.136631, 1.414045, 1.898520, 2.868497",\
+ "1.074289, 1.312841, 1.590254, 2.074727, 3.044697",\
+ "1.408602, 1.647155, 1.924568, 2.409040, 3.379012",\
+ "0.944644, 1.191260, 1.467714, 1.951848, 2.921161",\
+ "0.957790, 1.204406, 1.480859, 1.964992, 2.934304",\
+ "0.978941, 1.225557, 1.502010, 1.986142, 2.955452",\
+ "1.155151, 1.401767, 1.678219, 2.162348, 3.131652",\
+ "1.489465, 1.736081, 2.012533, 2.496662, 3.465967",\
+ "1.002316, 1.256815, 1.531856, 2.015761, 2.984670",\
+ "1.015462, 1.269960, 1.545001, 2.028905, 2.997813",\
+ "1.036613, 1.291111, 1.566152, 2.050055, 3.018961",\
+ "1.212823, 1.467322, 1.742362, 2.226262, 3.195161",\
+ "1.547137, 1.801636, 2.076675, 2.560575, 3.529476",\
+ "1.323336, 1.620278, 1.883889, 2.365174, 3.330126",\
+ "1.336481, 1.633424, 1.897034, 2.378319, 3.343269",\
+ "1.357632, 1.654575, 1.918185, 2.399469, 3.364417",\
+ "1.533842, 1.830785, 2.094395, 2.575675, 3.540617",\
+ "1.868156, 2.165099, 2.428709, 2.909989, 3.874932");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\
+ "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\
+ "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\
+ "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\
+ "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\
+ "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\
+ "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\
+ "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\
+ "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\
+ "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\
+ "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\
+ "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\
+ "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\
+ "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\
+ "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\
+ "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\
+ "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\
+ "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\
+ "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\
+ "1.026303, 1.026303, 1.026303, 1.026304, 1.026305");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[25]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.798247, 1.048384, 1.323795, 1.814843, 2.796940",\
+ "0.812087, 1.062224, 1.337635, 1.828683, 2.810778",\
+ "0.835598, 1.085734, 1.361145, 1.852193, 2.834289",\
+ "1.104470, 1.354606, 1.630016, 2.121061, 3.103152",\
+ "1.698998, 1.949135, 2.224544, 2.715585, 3.697667",\
+ "0.885653, 1.135896, 1.411429, 1.901557, 2.882874",\
+ "0.899493, 1.149736, 1.425268, 1.915396, 2.896712",\
+ "0.923003, 1.173246, 1.448779, 1.938907, 2.920223",\
+ "1.191875, 1.442118, 1.717650, 2.207775, 3.189086",\
+ "1.786403, 2.036647, 2.312177, 2.802298, 3.783601",\
+ "0.966497, 1.224769, 1.499393, 1.989178, 2.969829",\
+ "0.980337, 1.238609, 1.513233, 2.003017, 2.983667",\
+ "1.003847, 1.262119, 1.536743, 2.026528, 3.007178",\
+ "1.272719, 1.530991, 1.805614, 2.295396, 3.276041",\
+ "1.867248, 2.125520, 2.400141, 2.889919, 3.870556",\
+ "1.026473, 1.290246, 1.563536, 2.053091, 3.033338",\
+ "1.040313, 1.304086, 1.577376, 2.066930, 3.047176",\
+ "1.063823, 1.327596, 1.600886, 2.090441, 3.070687",\
+ "1.332695, 1.596468, 1.869757, 2.359309, 3.339550",\
+ "1.927224, 2.190996, 2.464285, 2.953832, 3.934065",\
+ "1.363781, 1.652852, 1.915624, 2.402524, 3.378794",\
+ "1.377621, 1.666692, 1.929464, 2.416363, 3.392632",\
+ "1.401132, 1.690202, 1.952974, 2.439874, 3.416142",\
+ "1.670003, 1.959074, 2.221846, 2.708742, 3.685006",\
+ "2.264532, 2.553603, 2.816373, 3.303265, 4.279521");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.129964, 0.129964, 0.129977, 0.130025, 0.130119",\
+ "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\
+ "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\
+ "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\
+ "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\
+ "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\
+ "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\
+ "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\
+ "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\
+ "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\
+ "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\
+ "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\
+ "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\
+ "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\
+ "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\
+ "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\
+ "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\
+ "2.222145, 2.222145, 2.222145, 2.222145, 2.222145");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.733334, 0.983470, 1.258885, 1.749946, 2.732069",\
+ "0.746479, 0.996616, 1.272029, 1.763087, 2.745203",\
+ "0.767630, 1.017767, 1.293179, 1.784232, 2.766337",\
+ "0.943840, 1.193977, 1.469384, 1.960422, 2.942497",\
+ "1.278154, 1.528290, 1.803698, 2.294737, 3.276814",\
+ "0.820739, 1.070982, 1.346519, 1.836660, 2.818002",\
+ "0.833884, 1.084128, 1.359663, 1.849801, 2.831136",\
+ "0.855036, 1.105279, 1.380813, 1.870946, 2.852271",\
+ "1.031245, 1.281489, 1.557018, 2.047136, 3.028431",\
+ "1.365559, 1.615803, 1.891332, 2.381451, 3.362748",\
+ "0.901583, 1.159855, 1.434483, 1.924281, 2.904958",\
+ "0.914729, 1.173001, 1.447627, 1.937422, 2.918091",\
+ "0.935880, 1.194152, 1.468777, 1.958567, 2.939226",\
+ "1.112090, 1.370362, 1.644982, 2.134757, 3.115386",\
+ "1.446404, 1.704675, 1.979296, 2.469072, 3.449703",\
+ "0.961559, 1.225332, 1.498626, 1.988194, 2.968467",\
+ "0.974705, 1.238478, 1.511771, 2.001335, 2.981600",\
+ "0.995856, 1.259629, 1.532920, 2.022480, 3.002735",\
+ "1.172065, 1.435838, 1.709126, 2.198669, 3.178895",\
+ "1.506379, 1.770152, 2.043440, 2.532985, 3.513212",\
+ "1.298868, 1.587939, 1.850715, 2.337627, 3.313922",\
+ "1.312013, 1.601084, 1.863859, 2.350768, 3.327056",\
+ "1.333164, 1.622235, 1.885009, 2.371913, 3.348191",\
+ "1.509374, 1.798445, 2.061214, 2.548103, 3.524351",\
+ "1.843688, 2.132759, 2.395528, 2.882418, 3.858668");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\
+ "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\
+ "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\
+ "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\
+ "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\
+ "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\
+ "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\
+ "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\
+ "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\
+ "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\
+ "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\
+ "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\
+ "0.086494, 0.086494, 0.086483, 0.086447, 0.086375",\
+ "0.090876, 0.090876, 0.090866, 0.090834, 0.090768",\
+ "0.110244, 0.110244, 0.110234, 0.110204, 0.110143",\
+ "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\
+ "1.026303, 1.026303, 1.026304, 1.026306, 1.026310");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2506*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[29]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.669029, 0.924047, 1.180422, 1.619320, 2.497118",\
+ "0.682742, 0.937760, 1.194134, 1.633031, 2.510826",\
+ "0.706267, 0.961286, 1.217660, 1.656557, 2.534352",\
+ "0.974450, 1.229468, 1.485840, 1.924731, 2.802514",\
+ "1.567911, 1.822930, 2.079299, 2.518181, 3.395944",\
+ "0.756434, 1.011535, 1.267892, 1.706034, 2.583051",\
+ "0.770147, 1.025247, 1.281604, 1.719745, 2.596760",\
+ "0.793673, 1.048773, 1.305130, 1.743271, 2.620286",\
+ "1.061855, 1.316955, 1.573310, 2.011445, 2.888448",\
+ "1.655316, 1.910417, 2.166769, 2.604894, 3.481877",\
+ "0.844902, 1.100352, 1.355853, 1.793655, 2.670006",\
+ "0.858615, 1.114065, 1.369565, 1.807366, 2.683715",\
+ "0.882141, 1.137591, 1.393091, 1.830892, 2.707241",\
+ "1.150323, 1.405773, 1.661271, 2.099066, 2.975403",\
+ "1.743784, 1.999234, 2.254730, 2.692515, 3.568832",\
+ "0.908398, 1.165749, 1.419987, 1.857568, 2.733515",\
+ "0.922111, 1.179461, 1.433699, 1.871279, 2.747224",\
+ "0.945637, 1.202987, 1.457225, 1.894805, 2.770750",\
+ "1.213819, 1.471169, 1.725405, 2.162979, 3.038912",\
+ "1.807280, 2.064631, 2.318864, 2.756428, 3.632341",\
+ "1.243831, 1.527415, 1.771546, 2.206786, 3.078971",\
+ "1.257544, 1.541128, 1.785259, 2.220497, 3.092680",\
+ "1.281070, 1.564654, 1.808785, 2.244023, 3.116206",\
+ "1.549252, 1.832836, 2.076965, 2.512197, 3.384368",\
+ "2.142714, 2.426297, 2.670424, 3.105646, 3.977798");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\
+ "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\
+ "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\
+ "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\
+ "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\
+ "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\
+ "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\
+ "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\
+ "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\
+ "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\
+ "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.607434, 0.862452, 1.118835, 1.557764, 2.435622",\
+ "0.619657, 0.874676, 1.131056, 1.569977, 2.447818",\
+ "0.639561, 0.894580, 1.150957, 1.589866, 2.467684",\
+ "0.811812, 1.066830, 1.323197, 1.762070, 2.639816",\
+ "1.146382, 1.401400, 1.657768, 2.096643, 2.974393",\
+ "0.694839, 0.949939, 1.206305, 1.644478, 2.521555",\
+ "0.707062, 0.962163, 1.218526, 1.656691, 2.533751",\
+ "0.726967, 0.982067, 1.238427, 1.676580, 2.553618",\
+ "0.899217, 1.154317, 1.410667, 1.848784, 2.725749",\
+ "1.233787, 1.488888, 1.745238, 2.183357, 3.060327",\
+ "0.783307, 1.038757, 1.294266, 1.732099, 2.608510",\
+ "0.795531, 1.050981, 1.306487, 1.744312, 2.620707",\
+ "0.815435, 1.070885, 1.326388, 1.764201, 2.640573",\
+ "0.987685, 1.243135, 1.498628, 1.936405, 2.812705",\
+ "1.322255, 1.577705, 1.833199, 2.270978, 3.147282",\
+ "0.846803, 1.104153, 1.358401, 1.796012, 2.672019",\
+ "0.859026, 1.116377, 1.370622, 1.808224, 2.684216",\
+ "0.878930, 1.136281, 1.390523, 1.828114, 2.704082",\
+ "1.051181, 1.308532, 1.562762, 2.000318, 2.876214",\
+ "1.385751, 1.643102, 1.897333, 2.334891, 3.210791",\
+ "1.182236, 1.465820, 1.709960, 2.145230, 3.017476",\
+ "1.194460, 1.478043, 1.722182, 2.157442, 3.029672",\
+ "1.214364, 1.497947, 1.742082, 2.177332, 3.049538",\
+ "1.386614, 1.670198, 1.914322, 2.349535, 3.221670",\
+ "1.721184, 2.004768, 2.248892, 2.684108, 3.556247");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.077163, 0.077163, 0.077138, 0.077052, 0.076882",\
+ "0.082420, 0.082420, 0.082398, 0.082320, 0.082166",\
+ "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\
+ "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\
+ "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\
+ "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\
+ "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\
+ "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\
+ "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\
+ "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\
+ "0.102329, 0.102329, 0.102307, 0.102236, 0.102091",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2663*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[30]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.646825, 0.888812, 1.155481, 1.637557, 2.601710",\
+ "0.660538, 0.902524, 1.169192, 1.651265, 2.615411",\
+ "0.684064, 0.926050, 1.192718, 1.674791, 2.638938",\
+ "0.952246, 1.194231, 1.460892, 1.942948, 2.907060",\
+ "1.545707, 1.787690, 2.054341, 2.536369, 3.500427",\
+ "0.734227, 0.976289, 1.243085, 1.724270, 2.687644",\
+ "0.747939, 0.990001, 1.256796, 1.737978, 2.701345",\
+ "0.771465, 1.013527, 1.280322, 1.761504, 2.724872",\
+ "1.039647, 1.281708, 1.548496, 2.029661, 2.992994",\
+ "1.633109, 1.875167, 2.141944, 2.623083, 3.586361",\
+ "0.815033, 1.065071, 1.331047, 1.811891, 2.774599",\
+ "0.828746, 1.078784, 1.344759, 1.825599, 2.788300",\
+ "0.852272, 1.102309, 1.368284, 1.849125, 2.811827",\
+ "1.120454, 1.370490, 1.636458, 2.117281, 3.079949",\
+ "1.713915, 1.963950, 2.229907, 2.710703, 3.673316",\
+ "0.875218, 1.130416, 1.395189, 1.875803, 2.838108",\
+ "0.888931, 1.144128, 1.408900, 1.889511, 2.851809",\
+ "0.912457, 1.167654, 1.432426, 1.913038, 2.875336",\
+ "1.180639, 1.435834, 1.700600, 2.181194, 3.143458",\
+ "1.774100, 2.029294, 2.294049, 2.774616, 3.736825",\
+ "1.213104, 1.491515, 1.747184, 2.225196, 3.183564",\
+ "1.226817, 1.505228, 1.760895, 2.238904, 3.197265",\
+ "1.250343, 1.528753, 1.784421, 2.262430, 3.220792",\
+ "1.518525, 1.796934, 2.052595, 2.530586, 3.488914",\
+ "2.111986, 2.390392, 2.646044, 3.124008, 4.082281");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\
+ "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\
+ "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\
+ "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\
+ "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\
+ "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\
+ "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\
+ "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\
+ "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\
+ "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\
+ "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\
+ "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\
+ "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\
+ "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\
+ "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\
+ "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.585231, 0.827223, 1.093925, 1.576086, 2.540408",\
+ "0.597454, 0.839445, 1.106138, 1.588275, 2.552550",\
+ "0.617358, 0.859347, 1.126027, 1.608132, 2.572344",\
+ "0.789607, 1.031589, 1.298230, 1.780235, 2.744245",\
+ "1.124177, 1.366160, 1.632803, 2.114814, 3.078838",\
+ "0.672632, 0.914701, 1.181530, 1.662799, 2.626341",\
+ "0.684856, 0.926922, 1.193742, 1.674988, 2.638484",\
+ "0.704759, 0.946824, 1.213631, 1.694846, 2.658278",\
+ "0.877009, 1.119066, 1.385834, 1.866948, 2.830179",\
+ "1.211579, 1.453637, 1.720407, 2.201528, 3.164772",\
+ "0.753439, 1.003483, 1.269492, 1.750420, 2.713296",\
+ "0.765663, 1.015705, 1.281705, 1.762609, 2.725439",\
+ "0.785566, 1.035606, 1.301594, 1.782466, 2.745233",\
+ "0.957816, 1.207848, 1.473796, 1.954568, 2.917134",\
+ "1.292386, 1.542419, 1.808370, 2.289148, 3.251727",\
+ "0.813624, 1.068828, 1.333634, 1.814332, 2.776805",\
+ "0.825847, 1.081049, 1.345847, 1.826521, 2.788948",\
+ "0.845751, 1.100950, 1.365736, 1.846379, 2.808742",\
+ "1.018000, 1.273192, 1.537938, 2.018481, 2.980643",\
+ "1.352571, 1.607763, 1.872511, 2.353061, 3.315236",\
+ "1.151510, 1.429929, 1.685630, 2.163725, 3.122262",\
+ "1.163733, 1.442150, 1.697842, 2.175914, 3.134404",\
+ "1.183637, 1.462051, 1.717731, 2.195772, 3.154198",\
+ "1.355886, 1.634290, 1.889933, 2.367873, 3.326099",\
+ "1.690457, 1.968861, 2.224506, 2.702453, 3.660692");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.077160, 0.077143, 0.077050, 0.076813, 0.076339",\
+ "0.082418, 0.082403, 0.082319, 0.082104, 0.081674",\
+ "0.102327, 0.102313, 0.102234, 0.102033, 0.101631",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\
+ "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\
+ "0.077160, 0.077143, 0.077050, 0.076813, 0.076339",\
+ "0.082418, 0.082403, 0.082318, 0.082104, 0.081674",\
+ "0.102327, 0.102313, 0.102234, 0.102033, 0.101631",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\
+ "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\
+ "0.077160, 0.077143, 0.077050, 0.076813, 0.076339",\
+ "0.082418, 0.082402, 0.082318, 0.082104, 0.081674",\
+ "0.102327, 0.102313, 0.102234, 0.102033, 0.101631",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\
+ "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\
+ "0.077160, 0.077142, 0.077050, 0.076813, 0.076339",\
+ "0.082418, 0.082402, 0.082318, 0.082104, 0.081674",\
+ "0.102327, 0.102312, 0.102234, 0.102033, 0.101631",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\
+ "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\
+ "0.077160, 0.077137, 0.077047, 0.076812, 0.076339",\
+ "0.082418, 0.082397, 0.082316, 0.082103, 0.081674",\
+ "0.102327, 0.102307, 0.102232, 0.102032, 0.101631",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\
+ "1.026132, 1.026132, 1.026131, 1.026130, 1.026129");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2738*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[34]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.837009, 1.103664, 1.394023, 1.889858, 2.881526",\
+ "0.850722, 1.117377, 1.407736, 1.903570, 2.895239",\
+ "0.874247, 1.140903, 1.431262, 1.927096, 2.918765",\
+ "1.142429, 1.409085, 1.699444, 2.195278, 3.186947",\
+ "1.735891, 2.002547, 2.292906, 2.788740, 3.780409",\
+ "0.924420, 1.191252, 1.481675, 1.976572, 2.967460",\
+ "0.938133, 1.204965, 1.495388, 1.990285, 2.981173",\
+ "0.961659, 1.228491, 1.518914, 2.013811, 3.004699",\
+ "1.229841, 1.496673, 1.787096, 2.281993, 3.272881",\
+ "1.823303, 2.090135, 2.380557, 2.875455, 3.866343",\
+ "1.005339, 1.280324, 1.569641, 2.064194, 3.054415",\
+ "1.019052, 1.294036, 1.583354, 2.077907, 3.068128",\
+ "1.042578, 1.317562, 1.606879, 2.101433, 3.091654",\
+ "1.310760, 1.585744, 1.875061, 2.369615, 3.359836",\
+ "1.904221, 2.179206, 2.468523, 2.963077, 3.953298",\
+ "1.066406, 1.346091, 1.633785, 2.128108, 3.117924",\
+ "1.080119, 1.359803, 1.647498, 2.141821, 3.131637",\
+ "1.103644, 1.383329, 1.671023, 2.165346, 3.155163",\
+ "1.371826, 1.651511, 1.939205, 2.433528, 3.423345",\
+ "1.965288, 2.244973, 2.532667, 3.026990, 4.016807",\
+ "1.402561, 1.712010, 1.985925, 2.477567, 3.463380",\
+ "1.416273, 1.725723, 1.999638, 2.491279, 3.477093",\
+ "1.439799, 1.749248, 2.023164, 2.514805, 3.500619",\
+ "1.707981, 2.017431, 2.291346, 2.782987, 3.768801",\
+ "2.301443, 2.610892, 2.884808, 3.376449, 4.362263");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.775414, 1.042069, 1.332428, 1.828263, 2.819932",\
+ "0.787637, 1.054293, 1.344652, 1.840486, 2.832155",\
+ "0.807541, 1.074197, 1.364556, 1.860390, 2.852059",\
+ "0.979792, 1.246447, 1.536806, 2.032640, 3.024309",\
+ "1.314362, 1.581017, 1.871376, 2.367211, 3.358880",\
+ "0.862825, 1.129657, 1.420080, 1.914977, 2.905865",\
+ "0.875049, 1.141881, 1.432303, 1.927201, 2.918089",\
+ "0.894953, 1.161785, 1.452208, 1.947105, 2.937993",\
+ "1.067203, 1.334035, 1.624458, 2.119355, 3.110243",\
+ "1.401773, 1.668605, 1.959028, 2.453925, 3.444813",\
+ "0.943744, 1.218729, 1.508046, 2.002599, 2.992820",\
+ "0.955968, 1.230952, 1.520269, 2.014823, 3.005044",\
+ "0.975872, 1.250856, 1.540173, 2.034727, 3.024948",\
+ "1.148122, 1.423107, 1.712424, 2.206977, 3.197198",\
+ "1.482692, 1.757677, 2.046994, 2.541547, 3.531768",\
+ "1.004811, 1.284495, 1.572190, 2.066513, 3.056329",\
+ "1.017034, 1.296719, 1.584413, 2.078736, 3.068553",\
+ "1.036938, 1.316623, 1.604317, 2.098640, 3.088457",\
+ "1.209189, 1.488873, 1.776568, 2.270891, 3.260707",\
+ "1.543759, 1.823443, 2.111138, 2.605461, 3.595277",\
+ "1.340966, 1.650415, 1.924330, 2.415972, 3.401785",\
+ "1.353189, 1.662638, 1.936553, 2.428195, 3.414009",\
+ "1.373093, 1.682542, 1.956458, 2.448099, 3.433913",\
+ "1.545344, 1.854793, 2.128708, 2.620349, 3.606163",\
+ "1.879914, 2.189363, 2.463278, 2.954920, 3.940733");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2382*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[35]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.820636, 1.072596, 1.352895, 1.817949, 2.748057",\
+ "0.834349, 1.086309, 1.366608, 1.831662, 2.761770",\
+ "0.857874, 1.109835, 1.390133, 1.855188, 2.785295",\
+ "1.126056, 1.378017, 1.658316, 2.123370, 3.053478",\
+ "1.719518, 1.971479, 2.251777, 2.716831, 3.646940",\
+ "0.908045, 1.160181, 1.440449, 1.904663, 2.833991",\
+ "0.921758, 1.173894, 1.454162, 1.918376, 2.847703",\
+ "0.945284, 1.197419, 1.477687, 1.941902, 2.871229",\
+ "1.213466, 1.465601, 1.745869, 2.210084, 3.139411",\
+ "1.806928, 2.059063, 2.339331, 2.803546, 3.732873",\
+ "0.988950, 1.249236, 1.528412, 1.992285, 2.920946",\
+ "1.002662, 1.262948, 1.542125, 2.005998, 2.934659",\
+ "1.026188, 1.286474, 1.565651, 2.029524, 2.958184",\
+ "1.294370, 1.554656, 1.833833, 2.297706, 3.226367",\
+ "1.887832, 2.148118, 2.427295, 2.891167, 3.819828",\
+ "1.046704, 1.314977, 1.592551, 2.056198, 2.984455",\
+ "1.060416, 1.328690, 1.606264, 2.069911, 2.998168",\
+ "1.083942, 1.352216, 1.629790, 2.093437, 3.021693",\
+ "1.352124, 1.620398, 1.897972, 2.361619, 3.289876",\
+ "1.945586, 2.213860, 2.491434, 2.955081, 3.883337",\
+ "1.375818, 1.680630, 1.944378, 2.405528, 3.329911",\
+ "1.389531, 1.694343, 1.958091, 2.419240, 3.343624",\
+ "1.413056, 1.717869, 1.981617, 2.442766, 3.367149",\
+ "1.681239, 1.986051, 2.249799, 2.710948, 3.635332",\
+ "2.274700, 2.579513, 2.843261, 3.304410, 4.228793");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\
+ "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\
+ "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.759041, 1.011001, 1.291300, 1.756354, 2.686462",\
+ "0.771264, 1.023225, 1.303523, 1.768578, 2.698686",\
+ "0.791168, 1.043129, 1.323427, 1.788481, 2.718590",\
+ "0.963419, 1.215379, 1.495678, 1.960732, 2.890840",\
+ "1.297989, 1.549949, 1.830248, 2.295302, 3.225410",\
+ "0.846450, 1.098586, 1.378854, 1.843068, 2.772396",\
+ "0.858674, 1.110809, 1.391077, 1.855292, 2.784619",\
+ "0.878578, 1.130713, 1.410981, 1.875196, 2.804523",\
+ "1.050828, 1.302964, 1.583232, 2.047446, 2.976774",\
+ "1.385398, 1.637534, 1.917802, 2.382016, 3.311344",\
+ "0.927355, 1.187640, 1.466817, 1.930690, 2.859351",\
+ "0.939578, 1.199864, 1.479041, 1.942914, 2.871574",\
+ "0.959482, 1.219768, 1.498945, 1.962818, 2.891478",\
+ "1.131733, 1.392018, 1.671195, 2.135068, 3.063729",\
+ "1.466303, 1.726588, 2.005765, 2.469638, 3.398299",\
+ "0.985108, 1.253382, 1.530956, 1.994603, 2.922860",\
+ "0.997332, 1.265606, 1.543180, 2.006827, 2.935083",\
+ "1.017236, 1.285510, 1.563084, 2.026731, 2.954987",\
+ "1.189487, 1.457760, 1.735334, 2.198981, 3.127238",\
+ "1.524057, 1.792330, 2.069904, 2.533551, 3.461808",\
+ "1.314223, 1.619035, 1.882783, 2.343933, 3.268316",\
+ "1.326446, 1.631259, 1.895007, 2.356156, 3.280540",\
+ "1.346350, 1.651163, 1.914911, 2.376060, 3.300443",\
+ "1.518601, 1.823413, 2.087161, 2.548311, 3.472694",\
+ "1.853171, 2.157983, 2.421731, 2.882881, 3.807264");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\
+ "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\
+ "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\
+ "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026132");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2443*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[38]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.834699, 1.095622, 1.384637, 1.885838, 2.888237",\
+ "0.848411, 1.109334, 1.398350, 1.899550, 2.901949",\
+ "0.871937, 1.132860, 1.421876, 1.923076, 2.925475",\
+ "1.140119, 1.401042, 1.690057, 2.191256, 3.193652",\
+ "1.733580, 1.994503, 2.283517, 2.784714, 3.787106",\
+ "0.922107, 1.183198, 1.472305, 1.972552, 2.974171",\
+ "0.935819, 1.196910, 1.486017, 1.986264, 2.987883",\
+ "0.959345, 1.220436, 1.509543, 2.009790, 3.011409",\
+ "1.227527, 1.488618, 1.777724, 2.277970, 3.279586",\
+ "1.820988, 2.082079, 2.371185, 2.871428, 3.873040",\
+ "1.002997, 1.272227, 1.560270, 2.060173, 3.061126",\
+ "1.016710, 1.285939, 1.573983, 2.073886, 3.074838",\
+ "1.040236, 1.309465, 1.597508, 2.097411, 3.098364",\
+ "1.308417, 1.577647, 1.865690, 2.365591, 3.366541",\
+ "1.901878, 2.171108, 2.459150, 2.959049, 3.959995",\
+ "1.063922, 1.337931, 1.624415, 2.124086, 3.124635",\
+ "1.077635, 1.351643, 1.638128, 2.137799, 3.138347",\
+ "1.101161, 1.375169, 1.661654, 2.161325, 3.161873",\
+ "1.369342, 1.643351, 1.929835, 2.429504, 3.430050",\
+ "1.962803, 2.236812, 2.523295, 3.022963, 4.023504",\
+ "1.400271, 1.703161, 1.976608, 2.473565, 3.470091",\
+ "1.413984, 1.716874, 1.990321, 2.487277, 3.483803",\
+ "1.437509, 1.740399, 2.013846, 2.510803, 3.507329",\
+ "1.705691, 2.008581, 2.282028, 2.778982, 3.775506",\
+ "2.299152, 2.602042, 2.875488, 3.372441, 4.368960");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.773106, 1.034029, 1.323047, 1.824254, 2.826667",\
+ "0.785329, 1.046252, 1.335269, 1.836474, 2.838884",\
+ "0.805232, 1.066155, 1.355171, 1.856374, 2.858778",\
+ "0.977479, 1.238403, 1.527417, 2.028611, 3.031000",\
+ "1.312050, 1.572973, 1.861987, 2.363182, 3.365571",\
+ "0.860514, 1.121605, 1.410714, 1.910968, 2.912601",\
+ "0.872737, 1.133828, 1.422936, 1.923188, 2.924818",\
+ "0.892640, 1.153731, 1.442839, 1.943088, 2.944712",\
+ "1.064888, 1.325979, 1.615084, 2.115325, 3.116933",\
+ "1.399458, 1.660549, 1.949654, 2.449896, 3.451505",\
+ "0.941405, 1.210634, 1.498679, 1.998589, 2.999556",\
+ "0.953628, 1.222857, 1.510902, 2.010810, 3.011773",\
+ "0.973531, 1.242760, 1.530804, 2.030710, 3.031667",\
+ "1.145778, 1.415007, 1.703049, 2.202947, 3.203888",\
+ "1.480349, 1.749578, 2.037620, 2.537518, 3.538460",\
+ "1.002329, 1.276338, 1.562824, 2.062502, 3.063065",\
+ "1.014552, 1.288561, 1.575047, 2.074723, 3.075282",\
+ "1.034455, 1.308464, 1.594949, 2.094623, 3.095176",\
+ "1.206703, 1.480712, 1.767194, 2.266860, 3.267397",\
+ "1.541273, 1.815282, 2.101765, 2.601431, 3.601969",\
+ "1.338678, 1.641568, 1.915017, 2.411981, 3.408521",\
+ "1.350901, 1.653791, 1.927240, 2.424201, 3.420738",\
+ "1.370804, 1.673694, 1.947142, 2.444101, 3.440632",\
+ "1.543052, 1.845942, 2.119387, 2.616338, 3.612854",\
+ "1.877622, 2.180512, 2.453958, 2.950909, 3.947425");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\
+ "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\
+ "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\
+ "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\
+ "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\
+ "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\
+ "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\
+ "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\
+ "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\
+ "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\
+ "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\
+ "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\
+ "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\
+ "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\
+ "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2590*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[39]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.813664, 1.067787, 1.348972, 1.815159, 2.747532",\
+ "0.827376, 1.081499, 1.362685, 1.828871, 2.761244",\
+ "0.850902, 1.105025, 1.386211, 1.852397, 2.784770",\
+ "1.119084, 1.373207, 1.654392, 2.120577, 3.052948",\
+ "1.712545, 1.966668, 2.247853, 2.714036, 3.646404",\
+ "0.901073, 1.155375, 1.436530, 1.901873, 2.833466",\
+ "0.914786, 1.169088, 1.450242, 1.915586, 2.847178",\
+ "0.938311, 1.192614, 1.473768, 1.939111, 2.870703",\
+ "1.206493, 1.460795, 1.741949, 2.207292, 3.138882",\
+ "1.799954, 2.054256, 2.335410, 2.800751, 3.732338",\
+ "0.981887, 1.244438, 1.524493, 1.989495, 2.920421",\
+ "0.995600, 1.258151, 1.538206, 2.003207, 2.934133",\
+ "1.019126, 1.281676, 1.561732, 2.026733, 2.957659",\
+ "1.287307, 1.549858, 1.829913, 2.294913, 3.225837",\
+ "1.880768, 2.143319, 2.423373, 2.888372, 3.819293",\
+ "1.039467, 1.310192, 1.588632, 2.053408, 2.983930",\
+ "1.053180, 1.323904, 1.602345, 2.067121, 2.997642",\
+ "1.076705, 1.347430, 1.625871, 2.090646, 3.021168",\
+ "1.344887, 1.615612, 1.894052, 2.358827, 3.289346",\
+ "1.938348, 2.209073, 2.487513, 2.952286, 3.882802",\
+ "1.371275, 1.675984, 1.940471, 2.402742, 3.329386",\
+ "1.384988, 1.689697, 1.954183, 2.416455, 3.343098",\
+ "1.408514, 1.713222, 1.977709, 2.439981, 3.366623",\
+ "1.676695, 1.981404, 2.245890, 2.708161, 3.634802",\
+ "2.270156, 2.574865, 2.839351, 3.301620, 4.228258");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\
+ "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\
+ "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\
+ "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\
+ "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\
+ "2.222140, 2.222140, 2.222140, 2.222140, 2.222140");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.752071, 1.006194, 1.287381, 1.753572, 2.685955",\
+ "0.764294, 1.018417, 1.299603, 1.765793, 2.698174",\
+ "0.784197, 1.038320, 1.319506, 1.785694, 2.718071",\
+ "0.956445, 1.210568, 1.491752, 1.957934, 2.890299",\
+ "1.291015, 1.545138, 1.826322, 2.292505, 3.224871",\
+ "0.839480, 1.093783, 1.374938, 1.840287, 2.771889",\
+ "0.851703, 1.106005, 1.387161, 1.852508, 2.784107",\
+ "0.871606, 1.125909, 1.407063, 1.872409, 2.804004",\
+ "1.043854, 1.298156, 1.579309, 2.044649, 2.976233",\
+ "1.378424, 1.632726, 1.913880, 2.379220, 3.310805",\
+ "0.920294, 1.182845, 1.462902, 1.927908, 2.858844",\
+ "0.932517, 1.195068, 1.475124, 1.940130, 2.871062",\
+ "0.952420, 1.214971, 1.495027, 1.960030, 2.890960",\
+ "1.124668, 1.387219, 1.667273, 2.132271, 3.063188",\
+ "1.459238, 1.721789, 2.001843, 2.466841, 3.397760",\
+ "0.977874, 1.248599, 1.527041, 1.991822, 2.922353",\
+ "0.990097, 1.260822, 1.539264, 2.004043, 2.934571",\
+ "1.010000, 1.280725, 1.559166, 2.023944, 2.954468",\
+ "1.182248, 1.452972, 1.731412, 2.196184, 3.126697",\
+ "1.516818, 1.787543, 2.065982, 2.530755, 3.461269",\
+ "1.309683, 1.614391, 1.878880, 2.341156, 3.267809",\
+ "1.321906, 1.626614, 1.891102, 2.353377, 3.280027",\
+ "1.341809, 1.646517, 1.911005, 2.373278, 3.299924",\
+ "1.514056, 1.818765, 2.083251, 2.545518, 3.472153",\
+ "1.848626, 2.153335, 2.417821, 2.880089, 3.806725");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\
+ "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\
+ "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\
+ "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\
+ "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\
+ "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\
+ "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\
+ "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\
+ "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\
+ "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\
+ "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\
+ "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\
+ "0.077156, 0.077156, 0.077151, 0.077138, 0.077112",\
+ "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\
+ "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\
+ "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\
+ "1.026132, 1.026132, 1.026132, 1.026132, 1.026131");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2633*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[40]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.689280, 0.957537, 1.249948, 1.745707, 2.737226",\
+ "0.703254, 0.971515, 1.263950, 1.759776, 2.751428",\
+ "0.726748, 0.995009, 1.287441, 1.783259, 2.774894",\
+ "0.996345, 1.264632, 1.557197, 2.053374, 3.045727",\
+ "1.591995, 1.860324, 2.153094, 2.649826, 3.643289",\
+ "0.776693, 1.045135, 1.337600, 1.832422, 2.823160",\
+ "0.790666, 1.059113, 1.351603, 1.846491, 2.837361",\
+ "0.814160, 1.082607, 1.375093, 1.869974, 2.860828",\
+ "1.083757, 1.352230, 1.644851, 2.140089, 3.131661",\
+ "1.679408, 1.947922, 2.240750, 2.736541, 3.729223",\
+ "0.857617, 1.134236, 1.425566, 1.920044, 2.910115",\
+ "0.871591, 1.148215, 1.439569, 1.934113, 2.924316",\
+ "0.895085, 1.171708, 1.463060, 1.957596, 2.947783",\
+ "1.164682, 1.441333, 1.732817, 2.227711, 3.218616",\
+ "1.760333, 2.037025, 2.328716, 2.824163, 3.816178",\
+ "0.918265, 1.200047, 1.489710, 1.983958, 2.973624",\
+ "0.932239, 1.214026, 1.503713, 1.998027, 2.987825",\
+ "0.955733, 1.237519, 1.527204, 2.021510, 3.011292",\
+ "1.225332, 1.507144, 1.796961, 2.291625, 3.282125",\
+ "1.820984, 2.102838, 2.392860, 2.888076, 3.879687",\
+ "1.253788, 1.566464, 1.841850, 2.333418, 3.319080",\
+ "1.267763, 1.580444, 1.855854, 2.347487, 3.333282",\
+ "1.291257, 1.603937, 1.879344, 2.370970, 3.356748",\
+ "1.560858, 1.873569, 2.149106, 2.641086, 3.627581",\
+ "2.156515, 2.469274, 2.745010, 3.237540, 4.225142");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.130558, 0.130764, 0.132053, 0.135744, 0.143126",\
+ "0.158251, 0.158388, 0.159397, 0.162380, 0.168346",\
+ "0.203206, 0.203261, 0.203904, 0.205928, 0.209976",\
+ "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\
+ "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\
+ "0.130558, 0.130766, 0.132065, 0.135744, 0.143126",\
+ "0.158251, 0.158389, 0.159406, 0.162380, 0.168346",\
+ "0.203206, 0.203262, 0.203910, 0.205928, 0.209976",\
+ "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\
+ "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\
+ "0.130559, 0.130769, 0.132065, 0.135744, 0.143126",\
+ "0.158251, 0.158391, 0.159406, 0.162380, 0.168346",\
+ "0.203206, 0.203262, 0.203910, 0.205928, 0.209976",\
+ "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\
+ "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\
+ "0.130568, 0.130774, 0.132066, 0.135744, 0.143126",\
+ "0.158257, 0.158394, 0.159407, 0.162380, 0.168346",\
+ "0.203208, 0.203264, 0.203911, 0.205928, 0.209976",\
+ "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\
+ "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\
+ "0.130591, 0.130830, 0.132103, 0.135759, 0.143126",\
+ "0.158273, 0.158432, 0.159437, 0.162392, 0.168346",\
+ "0.203215, 0.203279, 0.203931, 0.205936, 0.209976",\
+ "0.823780, 0.823783, 0.823793, 0.823822, 0.823881",\
+ "2.222146, 2.222146, 2.222146, 2.222146, 2.222146");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.620877, 0.889007, 1.180779, 1.674812, 2.662879",\
+ "0.634992, 0.903157, 1.195106, 1.689619, 2.678645",\
+ "0.657454, 0.925667, 1.217856, 1.713018, 2.703341",\
+ "0.837827, 1.106191, 1.399143, 1.896364, 2.890807",\
+ "1.171871, 1.440226, 1.733128, 2.230216, 3.224392",\
+ "0.708289, 0.976604, 1.268425, 1.761527, 2.748812",\
+ "0.722404, 0.990754, 1.282755, 1.776334, 2.764579",\
+ "0.744867, 1.013264, 1.305507, 1.799733, 2.789275",\
+ "0.925240, 1.193790, 1.486800, 1.983079, 2.976740",\
+ "1.259284, 1.527824, 1.820785, 2.316931, 3.310326",\
+ "0.789214, 1.065703, 1.356391, 1.849149, 2.835768",\
+ "0.803329, 1.079854, 1.370721, 1.863956, 2.851534",\
+ "0.825791, 1.102365, 1.393473, 1.887355, 2.876230",\
+ "1.006165, 1.282894, 1.574766, 2.070702, 3.063695",\
+ "1.340209, 1.616928, 1.908751, 2.404553, 3.397281",\
+ "0.849857, 1.131511, 1.420535, 1.913063, 2.899276",\
+ "0.863973, 1.145663, 1.434865, 1.927870, 2.915043",\
+ "0.886438, 1.168175, 1.457617, 1.951269, 2.939739",\
+ "1.066817, 1.348707, 1.638911, 2.134615, 3.127204",\
+ "1.400861, 1.682741, 1.972895, 2.468467, 3.460790",\
+ "1.185366, 1.497892, 1.772658, 2.262515, 3.244732",\
+ "1.199486, 1.512054, 1.786992, 2.277325, 3.260499",\
+ "1.221956, 1.534580, 1.809751, 2.300726, 3.285195",\
+ "1.402352, 1.715153, 1.991066, 2.484081, 3.472661",\
+ "1.736395, 2.049184, 2.325049, 2.817932, 3.806246");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.096307, 0.096664, 0.098460, 0.103314, 0.113023",\
+ "0.099768, 0.100091, 0.101719, 0.106118, 0.114915",\
+ "0.118566, 0.118869, 0.120392, 0.124509, 0.132743",\
+ "0.380772, 0.380786, 0.381010, 0.381719, 0.383137",\
+ "1.026329, 1.026338, 1.026379, 1.026486, 1.026699",\
+ "0.096307, 0.096666, 0.098476, 0.103314, 0.113023",\
+ "0.099768, 0.100093, 0.101733, 0.106118, 0.114915",\
+ "0.118566, 0.118871, 0.120405, 0.124509, 0.132743",\
+ "0.380772, 0.380786, 0.381012, 0.381719, 0.383137",\
+ "1.026329, 1.026338, 1.026379, 1.026486, 1.026699",\
+ "0.096307, 0.096672, 0.098476, 0.103314, 0.113023",\
+ "0.099768, 0.100099, 0.101733, 0.106118, 0.114915",\
+ "0.118566, 0.118876, 0.120406, 0.124509, 0.132743",\
+ "0.380772, 0.380786, 0.381012, 0.381719, 0.383137",\
+ "1.026329, 1.026339, 1.026379, 1.026486, 1.026699",\
+ "0.096322, 0.096680, 0.098477, 0.103314, 0.113023",\
+ "0.099782, 0.100106, 0.101734, 0.106118, 0.114915",\
+ "0.118579, 0.118883, 0.120406, 0.124509, 0.132743",\
+ "0.380772, 0.380787, 0.381012, 0.381719, 0.383137",\
+ "1.026330, 1.026339, 1.026379, 1.026486, 1.026699",\
+ "0.096361, 0.096780, 0.098526, 0.103335, 0.113023",\
+ "0.099817, 0.100196, 0.101779, 0.106136, 0.114915",\
+ "0.118612, 0.118967, 0.120448, 0.124526, 0.132743",\
+ "0.380772, 0.380792, 0.381019, 0.381722, 0.383137",\
+ "1.026331, 1.026341, 1.026381, 1.026486, 1.026699");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2683*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[42]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.195231, 0.463005, 0.734474, 1.195010, 2.116083",\
+ "0.209369, 0.477311, 0.748785, 1.209873, 2.132048",\
+ "0.233103, 0.501280, 0.772498, 1.233725, 2.156177",\
+ "0.505445, 0.772942, 1.041862, 1.499718, 2.415430",\
+ "1.101330, 1.368410, 1.636340, 2.092443, 3.004649",\
+ "0.282639, 0.550544, 0.822013, 1.281725, 2.202017",\
+ "0.296777, 0.564849, 0.836326, 1.296587, 2.217982",\
+ "0.320749, 0.588817, 0.860040, 1.320439, 2.242111",\
+ "0.593808, 0.860470, 1.129393, 1.586432, 2.501364",\
+ "1.189691, 1.455935, 1.723865, 2.179157, 3.090583",\
+ "0.371453, 0.639490, 0.909976, 1.369346, 2.288972",\
+ "0.385884, 0.653793, 0.924289, 1.384209, 2.304937",\
+ "0.410095, 0.677755, 0.948003, 1.408060, 2.329066",\
+ "0.683117, 0.949390, 1.217355, 1.674054, 2.588319",\
+ "1.278993, 1.544848, 1.811828, 2.266779, 3.177538",\
+ "0.435127, 0.705073, 0.974115, 1.433259, 2.352481",\
+ "0.449557, 0.719372, 0.988428, 1.448122, 2.368446",\
+ "0.473764, 0.743329, 1.012141, 1.471974, 2.392575",\
+ "0.746751, 1.014935, 1.281493, 1.737967, 2.651828",\
+ "1.342621, 1.610383, 1.875965, 2.330692, 3.241047",\
+ "0.771711, 1.068883, 1.325895, 1.782569, 2.697937",\
+ "0.786132, 1.083144, 1.340213, 1.797434, 2.713902",\
+ "0.810321, 1.107028, 1.363928, 1.821286, 2.738031",\
+ "1.083085, 1.378307, 1.633246, 2.087266, 2.997284",\
+ "1.678917, 1.973635, 2.227701, 2.679984, 3.586503");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.185659, 0.236480, 0.332306, 0.503768, 0.846690",\
+ "0.203762, 0.251201, 0.346416, 0.519962, 0.867054",\
+ "0.237818, 0.275998, 0.366817, 0.542132, 0.892761",\
+ "0.823305, 0.824108, 0.854501, 0.958291, 1.165871",\
+ "2.222180, 2.222247, 2.228687, 2.250859, 2.295203",\
+ "0.185659, 0.236778, 0.332846, 0.503768, 0.846690",\
+ "0.203762, 0.251491, 0.346963, 0.519962, 0.867054",\
+ "0.238090, 0.276257, 0.367369, 0.542132, 0.892761",\
+ "0.823322, 0.824110, 0.854828, 0.958291, 1.165871",\
+ "2.222181, 2.222247, 2.228756, 2.250859, 2.295203",\
+ "0.187582, 0.237448, 0.332856, 0.503768, 0.846690",\
+ "0.205428, 0.252143, 0.346973, 0.519962, 0.867054",\
+ "0.238891, 0.276838, 0.367379, 0.542132, 0.892761",\
+ "0.823369, 0.824113, 0.854835, 0.958291, 1.165871",\
+ "2.222186, 2.222247, 2.228758, 2.250859, 2.295203",\
+ "0.188921, 0.238422, 0.332885, 0.503768, 0.846690",\
+ "0.206588, 0.253091, 0.347002, 0.519962, 0.867054",\
+ "0.239638, 0.277682, 0.367409, 0.542132, 0.892761",\
+ "0.823414, 0.824119, 0.854852, 0.958291, 1.165871",\
+ "2.222191, 2.222247, 2.228761, 2.250859, 2.295203",\
+ "0.197449, 0.249827, 0.334624, 0.504477, 0.846690",\
+ "0.213977, 0.264195, 0.348763, 0.520680, 0.867054",\
+ "0.244398, 0.287568, 0.369187, 0.542857, 0.892761",\
+ "0.823697, 0.824180, 0.855905, 0.958721, 1.165871",\
+ "2.222221, 2.222247, 2.228986, 2.250950, 2.295203");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.199835, 0.394068, 0.663502, 1.119151, 2.030450",\
+ "0.208748, 0.404375, 0.677456, 1.139816, 2.064535",\
+ "0.223610, 0.421071, 0.699454, 1.171923, 2.116862",\
+ "0.380613, 0.582386, 0.880612, 1.405667, 2.455778",\
+ "0.716679, 0.922290, 1.228480, 1.784735, 2.897244",\
+ "0.287243, 0.481603, 0.751025, 1.205865, 2.116384",\
+ "0.296156, 0.491921, 0.765001, 1.226530, 2.150469",\
+ "0.311018, 0.508632, 0.787030, 1.258637, 2.202796",\
+ "0.468021, 0.669977, 0.968355, 1.492382, 2.541712",\
+ "0.804087, 1.009874, 1.316321, 1.871449, 2.983178",\
+ "0.368115, 0.570540, 0.838988, 1.293487, 2.203339",\
+ "0.377029, 0.580882, 0.852964, 1.314152, 2.237424",\
+ "0.391890, 0.597628, 0.874994, 1.346259, 2.289751",\
+ "0.548893, 0.759039, 1.056321, 1.580003, 2.628667",\
+ "0.884959, 1.098920, 1.404289, 1.959070, 3.070133",\
+ "0.425818, 0.636109, 0.903125, 1.357400, 2.266848",\
+ "0.434733, 0.646488, 0.917102, 1.378065, 2.300933",\
+ "0.449593, 0.663284, 0.939134, 1.410172, 2.353260",\
+ "0.606596, 0.824792, 1.120470, 1.643916, 2.692176",\
+ "0.942662, 1.164649, 1.468444, 2.022984, 3.133642",\
+ "0.728861, 0.999767, 1.254856, 1.706689, 2.612304",\
+ "0.737784, 1.010567, 1.268901, 1.727382, 2.646389",\
+ "0.752638, 1.027949, 1.291036, 1.759531, 2.698716",\
+ "0.909639, 1.190589, 1.472905, 1.993493, 3.037632",\
+ "1.245701, 1.530174, 1.821195, 2.372689, 3.479098");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.051713, 0.082206, 0.146667, 0.272496, 0.524154",\
+ "0.059242, 0.084148, 0.146833, 0.273232, 0.526032",\
+ "0.082676, 0.098099, 0.151707, 0.276480, 0.526025",\
+ "0.382075, 0.382564, 0.407345, 0.490228, 0.655996",\
+ "1.027888, 1.027888, 1.042321, 1.092011, 1.191392",\
+ "0.051713, 0.082387, 0.147063, 0.272496, 0.524154",\
+ "0.059242, 0.084316, 0.147231, 0.273232, 0.526032",\
+ "0.082676, 0.098212, 0.152100, 0.276480, 0.526025",\
+ "0.382075, 0.382568, 0.407606, 0.490228, 0.655996",\
+ "1.027888, 1.027888, 1.042477, 1.092011, 1.191392",\
+ "0.051782, 0.082793, 0.147071, 0.272496, 0.524154",\
+ "0.059284, 0.084694, 0.147238, 0.273232, 0.526032",\
+ "0.082697, 0.098465, 0.152108, 0.276480, 0.526025",\
+ "0.382075, 0.382579, 0.407611, 0.490228, 0.655996",\
+ "1.027888, 1.027888, 1.042480, 1.092011, 1.191392",\
+ "0.051916, 0.083384, 0.147092, 0.272496, 0.524154",\
+ "0.059368, 0.085243, 0.147259, 0.273232, 0.526032",\
+ "0.082738, 0.098832, 0.152128, 0.276480, 0.526025",\
+ "0.382075, 0.382594, 0.407625, 0.490228, 0.655996",\
+ "1.027888, 1.027888, 1.042489, 1.092011, 1.191392",\
+ "0.053133, 0.090301, 0.148368, 0.273016, 0.524154",\
+ "0.060124, 0.091679, 0.148542, 0.273755, 0.526032",\
+ "0.083110, 0.103136, 0.153394, 0.276996, 0.526025",\
+ "0.382075, 0.382769, 0.408465, 0.490571, 0.655996",\
+ "1.027888, 1.027888, 1.042993, 1.092217, 1.191392");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2504*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[43]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.107724, 0.368276, 0.625542, 1.061117, 1.932266",\
+ "0.118290, 0.379979, 0.639987, 1.079831, 1.959519",\
+ "0.141262, 0.402747, 0.664893, 1.109231, 1.997905",\
+ "0.466405, 0.694370, 0.967258, 1.421195, 2.329069",\
+ "1.080370, 1.299790, 1.592495, 2.085614, 3.071851",\
+ "0.196001, 0.455768, 0.713003, 1.147831, 2.018200",\
+ "0.206570, 0.467481, 0.727462, 1.166545, 2.045453",\
+ "0.229522, 0.490254, 0.752382, 1.195945, 2.083839",\
+ "0.553814, 0.781928, 1.054777, 1.507910, 2.415003",\
+ "1.167779, 1.387403, 1.680137, 2.172328, 3.157785",\
+ "0.284966, 0.544612, 0.800965, 1.235453, 2.105155",\
+ "0.295543, 0.556347, 0.815424, 1.254167, 2.132408",\
+ "0.318436, 0.579132, 0.840344, 1.283567, 2.170794",\
+ "0.634637, 0.870922, 1.142740, 1.595531, 2.501958",\
+ "1.248620, 1.476519, 1.768103, 2.259950, 3.244740",\
+ "0.348239, 0.610047, 0.865099, 1.299366, 2.168664",\
+ "0.358823, 0.621814, 0.879558, 1.318080, 2.195917",\
+ "0.381662, 0.644617, 0.904480, 1.347480, 2.234303",\
+ "0.692234, 0.936575, 1.206877, 1.659445, 2.565467",\
+ "1.306252, 1.542352, 1.832246, 2.323863, 3.308249",\
+ "0.682278, 0.972118, 1.216627, 1.648574, 2.514120",\
+ "0.692910, 0.984256, 1.231130, 1.667306, 2.541373",\
+ "0.715403, 1.007266, 1.256096, 1.696724, 2.579759",\
+ "1.001252, 1.301193, 1.558591, 2.008728, 2.910923",\
+ "1.608596, 1.909065, 2.184358, 2.673309, 3.653705");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.074735, 0.092677, 0.146088, 0.239899, 0.427522",\
+ "0.102638, 0.120071, 0.176792, 0.284601, 0.500219",\
+ "0.161882, 0.174744, 0.229174, 0.352169, 0.598157",\
+ "0.823637, 0.823637, 0.866367, 1.013938, 1.309078",\
+ "2.221941, 2.221941, 2.244685, 2.323231, 2.480325",\
+ "0.074735, 0.092846, 0.146384, 0.239899, 0.427522",\
+ "0.102638, 0.120235, 0.177132, 0.284601, 0.500219",\
+ "0.161882, 0.174865, 0.229562, 0.352169, 0.598157",\
+ "0.823637, 0.823637, 0.866833, 1.013938, 1.309078",\
+ "2.221941, 2.221941, 2.244933, 2.323231, 2.480325",\
+ "0.074735, 0.093227, 0.146389, 0.239899, 0.427522",\
+ "0.102638, 0.120606, 0.177138, 0.284601, 0.500219",\
+ "0.161882, 0.175138, 0.229569, 0.352169, 0.598157",\
+ "0.823637, 0.823637, 0.866841, 1.013938, 1.309078",\
+ "2.221941, 2.221941, 2.244937, 2.323231, 2.480325",\
+ "0.074735, 0.093782, 0.146405, 0.239899, 0.427522",\
+ "0.102638, 0.121144, 0.177156, 0.284601, 0.500219",\
+ "0.161882, 0.175536, 0.229590, 0.352169, 0.598157",\
+ "0.823637, 0.823637, 0.866866, 1.013938, 1.309078",\
+ "2.221941, 2.221941, 2.244950, 2.323231, 2.480325",\
+ "0.074735, 0.100272, 0.147356, 0.240288, 0.427522",\
+ "0.102638, 0.127451, 0.178250, 0.285047, 0.500219",\
+ "0.161882, 0.180189, 0.230838, 0.352678, 0.598157",\
+ "0.823637, 0.823637, 0.868363, 1.014548, 1.309078",\
+ "2.221941, 2.221941, 2.245747, 2.323557, 2.480325");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.140111, 0.321611, 0.507696, 0.851050, 1.569056",\
+ "0.146136, 0.328572, 0.525511, 0.902870, 1.657587",\
+ "0.156561, 0.339884, 0.570480, 0.970939, 1.771856",\
+ "0.297184, 0.522021, 0.807737, 1.302651, 2.292479",\
+ "0.634484, 0.861679, 1.151767, 1.684827, 2.750947",\
+ "0.227520, 0.408999, 0.595163, 0.937764, 1.654990",\
+ "0.233545, 0.415960, 0.612788, 0.989584, 1.743521",\
+ "0.243970, 0.427273, 0.657830, 1.057653, 1.857790",\
+ "0.384593, 0.609585, 0.895385, 1.389365, 2.378412",\
+ "0.721893, 0.949200, 1.239535, 1.771541, 2.836881",\
+ "0.308387, 0.489332, 0.675190, 1.025386, 1.741945",\
+ "0.314418, 0.496293, 0.700747, 1.077206, 1.830476",\
+ "0.324849, 0.509849, 0.745789, 1.145275, 1.944745",\
+ "0.465472, 0.698592, 0.983351, 1.476987, 2.465368",\
+ "0.802748, 1.038111, 1.327502, 1.859163, 2.923836",\
+ "0.366068, 0.546880, 0.732732, 1.089299, 1.805454",\
+ "0.372111, 0.553842, 0.764871, 1.141119, 1.893985",\
+ "0.382553, 0.575066, 0.809918, 1.209188, 2.008254",\
+ "0.523176, 0.764266, 1.047495, 1.540900, 2.528877",\
+ "0.860406, 1.103644, 1.391653, 1.923076, 2.987345",\
+ "0.668860, 0.879530, 1.082095, 1.438189, 2.150910",\
+ "0.675009, 0.902838, 1.115808, 1.490086, 2.239441",\
+ "0.685552, 0.934577, 1.161089, 1.558250, 2.353710",\
+ "0.829810, 1.129123, 1.399624, 1.890354, 2.874332",\
+ "1.174406, 1.466850, 1.744170, 2.272687, 3.332801");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.063168, 0.063168, 0.086358, 0.196253, 0.354186",\
+ "0.068741, 0.068741, 0.139035, 0.228534, 0.407534",\
+ "0.084603, 0.084603, 0.170977, 0.272661, 0.476028",\
+ "0.381099, 0.384014, 0.432690, 0.586065, 0.892815",\
+ "1.028844, 1.028844, 1.069535, 1.210064, 1.491123",\
+ "0.063168, 0.063168, 0.086418, 0.196253, 0.354186",\
+ "0.068741, 0.068741, 0.139317, 0.228534, 0.407534",\
+ "0.084603, 0.084603, 0.171298, 0.272661, 0.476028",\
+ "0.381099, 0.384041, 0.433173, 0.586065, 0.892815",\
+ "1.028844, 1.028844, 1.069978, 1.210064, 1.491123",\
+ "0.063168, 0.063168, 0.086418, 0.196253, 0.354186",\
+ "0.068741, 0.068741, 0.139322, 0.228534, 0.407534",\
+ "0.084603, 0.108427, 0.171304, 0.272661, 0.476028",\
+ "0.381099, 0.384103, 0.433182, 0.586065, 0.892815",\
+ "1.028844, 1.028844, 1.069987, 1.210064, 1.491123",\
+ "0.063168, 0.063168, 0.086418, 0.196253, 0.354186",\
+ "0.068741, 0.068741, 0.139337, 0.228534, 0.407534",\
+ "0.084603, 0.109141, 0.171320, 0.272661, 0.476028",\
+ "0.381099, 0.384193, 0.433208, 0.586065, 0.892815",\
+ "1.028844, 1.028844, 1.070010, 1.210064, 1.491123",\
+ "0.063168, 0.081229, 0.118354, 0.196580, 0.354186",\
+ "0.068741, 0.094387, 0.140245, 0.228905, 0.407534",\
+ "0.084603, 0.117503, 0.172352, 0.273082, 0.476028",\
+ "0.381099, 0.385248, 0.434764, 0.586700, 0.892815",\
+ "1.028844, 1.028844, 1.071436, 1.210646, 1.491123");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2464*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[45]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.666340, 0.928130, 1.212847, 1.689620, 2.643166",\
+ "0.680315, 0.942109, 1.226845, 1.703665, 2.657306",\
+ "0.703809, 0.965603, 1.250336, 1.727151, 2.680780",\
+ "0.973410, 1.235228, 1.520067, 1.997139, 2.951283",\
+ "1.569066, 1.830922, 2.115924, 2.593394, 3.548335",\
+ "0.753746, 1.015729, 1.300436, 1.776334, 2.729100",\
+ "0.767721, 1.029708, 1.314434, 1.790379, 2.743240",\
+ "0.791215, 1.053202, 1.337926, 1.813865, 2.766714",\
+ "1.060816, 1.322827, 1.607657, 2.083853, 3.037217",\
+ "1.656472, 1.918522, 2.203516, 2.680108, 3.634269",\
+ "0.834559, 1.104799, 1.388400, 1.863955, 2.816055",\
+ "0.848533, 1.118778, 1.402398, 1.878000, 2.830195",\
+ "0.872027, 1.142272, 1.425889, 1.901486, 2.853669",\
+ "1.141628, 1.411898, 1.695621, 2.171474, 3.124172",\
+ "1.737284, 2.007593, 2.291479, 2.767729, 3.721224",\
+ "0.896255, 1.170562, 1.452541, 1.927868, 2.879564",\
+ "0.910230, 1.184541, 1.466539, 1.941913, 2.893704",\
+ "0.933724, 1.208035, 1.490030, 1.965399, 2.917178",\
+ "1.203325, 1.477661, 1.759762, 2.235387, 3.187681",\
+ "1.798983, 2.073358, 2.355620, 2.831642, 3.784733",\
+ "1.233218, 1.536514, 1.804484, 2.277243, 3.225020",\
+ "1.247192, 1.550495, 1.818483, 2.291289, 3.239160",\
+ "1.270686, 1.573988, 1.841974, 2.314774, 3.262634",\
+ "1.540289, 1.843622, 2.111709, 2.584763, 3.533137",\
+ "2.135948, 2.439330, 2.707571, 3.181020, 4.130188");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.130524, 0.130598, 0.131270, 0.133249, 0.137207",\
+ "0.158228, 0.158278, 0.158724, 0.160039, 0.162669",\
+ "0.203197, 0.203217, 0.203397, 0.203929, 0.204993",\
+ "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\
+ "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\
+ "0.130524, 0.130599, 0.131276, 0.133249, 0.137207",\
+ "0.158228, 0.158278, 0.158728, 0.160039, 0.162669",\
+ "0.203197, 0.203217, 0.203399, 0.203929, 0.204993",\
+ "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\
+ "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\
+ "0.130525, 0.130600, 0.131276, 0.133249, 0.137207",\
+ "0.158229, 0.158279, 0.158728, 0.160039, 0.162669",\
+ "0.203197, 0.203217, 0.203399, 0.203929, 0.204993",\
+ "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\
+ "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\
+ "0.130526, 0.130602, 0.131276, 0.133249, 0.137207",\
+ "0.158229, 0.158280, 0.158728, 0.160039, 0.162669",\
+ "0.203197, 0.203218, 0.203399, 0.203929, 0.204993",\
+ "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\
+ "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\
+ "0.130530, 0.130626, 0.131296, 0.133257, 0.137207",\
+ "0.158232, 0.158296, 0.158741, 0.160044, 0.162669",\
+ "0.203198, 0.203224, 0.203404, 0.203931, 0.204993",\
+ "0.823780, 0.823783, 0.823791, 0.823812, 0.823854",\
+ "2.222146, 2.222146, 2.222146, 2.222149, 2.222153");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.597919, 0.859592, 1.143801, 1.619336, 2.570405",\
+ "0.612039, 0.873744, 1.158095, 1.633973, 2.585731",\
+ "0.634508, 0.896258, 1.180798, 1.657142, 2.609831",\
+ "0.814903, 1.076792, 1.361938, 1.839759, 2.795403",\
+ "1.148946, 1.410826, 1.695932, 2.173658, 3.129110",\
+ "0.685326, 0.947190, 1.231387, 1.706050, 2.656339",\
+ "0.699445, 0.961343, 1.245681, 1.720687, 2.671665",\
+ "0.721914, 0.983856, 1.268386, 1.743856, 2.695765",\
+ "0.902309, 1.164392, 1.449531, 1.926473, 2.881336",\
+ "1.236352, 1.498426, 1.783525, 2.260372, 3.215044",\
+ "0.766138, 1.036258, 1.319350, 1.793671, 2.743294",\
+ "0.780258, 1.050411, 1.333645, 1.808309, 2.758620",\
+ "0.802727, 1.072925, 1.356350, 1.831478, 2.782720",\
+ "0.983121, 1.253464, 1.537494, 2.014095, 2.968292",\
+ "1.317164, 1.587497, 1.871488, 2.347994, 3.301999",\
+ "0.827832, 1.102018, 1.383491, 1.857584, 2.806803",\
+ "0.841953, 1.116172, 1.397786, 1.872221, 2.822129",\
+ "0.864423, 1.138688, 1.420491, 1.895391, 2.846229",\
+ "1.044820, 1.319229, 1.601635, 2.078008, 3.031801",\
+ "1.378863, 1.653263, 1.935629, 2.411906, 3.365508",\
+ "1.164787, 1.467934, 1.735422, 2.206954, 3.152259",\
+ "1.178910, 1.482098, 1.749720, 2.221593, 3.167585",\
+ "1.201382, 1.504627, 1.772430, 2.244764, 3.191684",\
+ "1.381788, 1.685212, 1.953590, 2.427387, 3.377256",\
+ "1.715830, 2.019242, 2.287583, 2.761285, 3.710964");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.096357, 0.096687, 0.098113, 0.101595, 0.108560",\
+ "0.099813, 0.100112, 0.101404, 0.104560, 0.110871",\
+ "0.118608, 0.118888, 0.120098, 0.123051, 0.128958",\
+ "0.380772, 0.380788, 0.380959, 0.381468, 0.382485",\
+ "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\
+ "0.096357, 0.096690, 0.098124, 0.101595, 0.108560",\
+ "0.099813, 0.100115, 0.101414, 0.104560, 0.110871",\
+ "0.118608, 0.118891, 0.120107, 0.123051, 0.128958",\
+ "0.380772, 0.380788, 0.380960, 0.381468, 0.382485",\
+ "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\
+ "0.096357, 0.096696, 0.098124, 0.101595, 0.108560",\
+ "0.099813, 0.100120, 0.101415, 0.104560, 0.110871",\
+ "0.118609, 0.118896, 0.120107, 0.123051, 0.128958",\
+ "0.380772, 0.380788, 0.380960, 0.381468, 0.382485",\
+ "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\
+ "0.096364, 0.096704, 0.098125, 0.101595, 0.108560",\
+ "0.099820, 0.100128, 0.101415, 0.104560, 0.110871",\
+ "0.118615, 0.118903, 0.120108, 0.123051, 0.128958",\
+ "0.380772, 0.380789, 0.380961, 0.381468, 0.382485",\
+ "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\
+ "0.096383, 0.096806, 0.098160, 0.101610, 0.108560",\
+ "0.099837, 0.100220, 0.101447, 0.104573, 0.110871",\
+ "0.118631, 0.118989, 0.120138, 0.123064, 0.128958",\
+ "0.380772, 0.380794, 0.380966, 0.381470, 0.382485",\
+ "1.026328, 1.026332, 1.026362, 1.026448, 1.026622");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2715*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[18]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.476785, 0.693340, 0.873015, 1.163119, 1.725535",\
+ "0.496002, 0.712556, 0.892232, 1.182336, 1.744752",\
+ "0.527650, 0.744204, 0.923880, 1.213984, 1.776400",\
+ "0.818239, 1.034793, 1.214469, 1.504573, 2.066989",\
+ "1.412242, 1.628797, 1.808472, 2.098576, 2.660992",\
+ "0.565076, 0.780658, 0.960296, 1.250424, 1.812889",\
+ "0.584292, 0.799874, 0.979512, 1.269641, 1.832105",\
+ "0.615941, 0.831523, 1.011161, 1.301289, 1.863753",\
+ "0.906530, 1.122112, 1.301750, 1.591878, 2.154342",\
+ "1.500533, 1.716115, 1.895753, 2.185881, 2.748345",\
+ "0.654117, 0.860991, 1.040323, 1.330453, 1.892920",\
+ "0.673334, 0.880207, 1.059539, 1.349669, 1.912137",\
+ "0.704982, 0.911855, 1.091188, 1.381318, 1.943785",\
+ "0.995571, 1.202444, 1.381777, 1.671907, 2.234374",\
+ "1.589574, 1.796447, 1.975780, 2.265910, 2.828377",\
+ "0.717479, 0.918821, 1.098020, 1.387885, 1.949940",\
+ "0.736695, 0.938038, 1.117237, 1.407101, 1.969157",\
+ "0.768343, 0.969686, 1.148885, 1.438750, 2.000805",\
+ "1.058932, 1.260275, 1.439474, 1.729339, 2.291394",\
+ "1.652935, 1.854278, 2.033477, 2.323342, 2.885397",\
+ "1.042371, 1.224140, 1.401676, 1.691058, 2.252168",\
+ "1.061587, 1.243356, 1.420893, 1.710275, 2.271384",\
+ "1.093235, 1.275004, 1.452541, 1.741923, 2.303032",\
+ "1.383824, 1.565593, 1.743130, 2.032512, 2.593621",\
+ "1.977827, 2.159596, 2.337133, 2.626515, 3.187624");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.489199, 0.705753, 0.885429, 1.175533, 1.737949",\
+ "0.497006, 0.713560, 0.893235, 1.183340, 1.745756",\
+ "0.510387, 0.726941, 0.906617, 1.196721, 1.759137",\
+ "0.662333, 0.878887, 1.058563, 1.348667, 1.911083",\
+ "0.995767, 1.212322, 1.391997, 1.682102, 2.244518",\
+ "0.577490, 0.793071, 0.972710, 1.262838, 1.825302",\
+ "0.585296, 0.800878, 0.980516, 1.270645, 1.833109",\
+ "0.598678, 0.814260, 0.993898, 1.284026, 1.846490",\
+ "0.750624, 0.966205, 1.145844, 1.435972, 1.998436",\
+ "1.084058, 1.299640, 1.479278, 1.769407, 2.331871",\
+ "0.666531, 0.873404, 1.052737, 1.342866, 1.905334",\
+ "0.674337, 0.881211, 1.060543, 1.350673, 1.913141",\
+ "0.687719, 0.894592, 1.073925, 1.364055, 1.926522",\
+ "0.839665, 1.046538, 1.225871, 1.516001, 2.078468",\
+ "1.173099, 1.379973, 1.559305, 1.849435, 2.411902",\
+ "0.729892, 0.931235, 1.110434, 1.400298, 1.962354",\
+ "0.737699, 0.939041, 1.118240, 1.408105, 1.970161",\
+ "0.751080, 0.952423, 1.131622, 1.421487, 1.983542",\
+ "0.903026, 1.104369, 1.283568, 1.573432, 2.135488",\
+ "1.236461, 1.437803, 1.617002, 1.906867, 2.468923",\
+ "1.054784, 1.236553, 1.414090, 1.703472, 2.264581",\
+ "1.062591, 1.244360, 1.421896, 1.711279, 2.272388",\
+ "1.075972, 1.257741, 1.435278, 1.724660, 2.285769",\
+ "1.227918, 1.409687, 1.587224, 1.876606, 2.437715",\
+ "1.561353, 1.743122, 1.920659, 2.210041, 2.771150");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2568*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[19]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.486016, 0.718373, 0.902601, 1.196441, 1.764052",\
+ "0.505233, 0.737590, 0.921817, 1.215657, 1.783269",\
+ "0.536881, 0.769238, 0.953465, 1.247305, 1.814917",\
+ "0.827470, 1.059827, 1.244054, 1.537894, 2.105506",\
+ "1.421473, 1.653830, 1.838057, 2.131897, 2.699509",\
+ "0.574330, 0.805691, 0.989882, 1.283746, 1.851406",\
+ "0.593546, 0.824908, 1.009098, 1.302962, 1.870622",\
+ "0.625194, 0.856556, 1.040746, 1.334610, 1.902271",\
+ "0.915783, 1.147145, 1.331335, 1.625199, 2.192860",\
+ "1.509786, 1.741148, 1.925338, 2.219203, 2.786862",\
+ "0.663471, 0.886024, 1.069909, 1.363774, 1.931437",\
+ "0.682687, 0.905240, 1.089125, 1.382991, 1.950654",\
+ "0.714335, 0.936888, 1.120773, 1.414639, 1.982302",\
+ "1.004924, 1.227477, 1.411362, 1.705228, 2.272891",\
+ "1.598927, 1.821480, 2.005365, 2.299231, 2.866894",\
+ "0.726940, 0.943856, 1.127617, 1.421213, 1.988470",\
+ "0.746156, 0.963072, 1.146833, 1.440429, 2.007687",\
+ "0.777804, 0.994720, 1.178482, 1.472077, 2.039335",\
+ "1.068393, 1.285309, 1.469070, 1.762666, 2.329924",\
+ "1.662396, 1.879312, 2.063073, 2.356669, 2.923927",\
+ "1.062221, 1.249183, 1.431275, 1.724391, 2.290713",\
+ "1.081437, 1.268400, 1.450491, 1.743608, 2.309929",\
+ "1.113086, 1.300048, 1.482139, 1.775256, 2.341578",\
+ "1.403675, 1.590637, 1.772728, 2.065845, 2.632166",\
+ "1.997678, 2.184640, 2.366731, 2.659848, 3.226169");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.498430, 0.730787, 0.915014, 1.208854, 1.776466",\
+ "0.506236, 0.738593, 0.922821, 1.216661, 1.784272",\
+ "0.519618, 0.751975, 0.936202, 1.230042, 1.797654",\
+ "0.671564, 0.903921, 1.088148, 1.381988, 1.949600",\
+ "1.004998, 1.237355, 1.421583, 1.715423, 2.283034",\
+ "0.586743, 0.818105, 1.002295, 1.296159, 1.863819",\
+ "0.594550, 0.825911, 1.010102, 1.303966, 1.871626",\
+ "0.607931, 0.839293, 1.023483, 1.317347, 1.885008",\
+ "0.759877, 0.991239, 1.175429, 1.469293, 2.036953",\
+ "1.093312, 1.324673, 1.508864, 1.802728, 2.370388",\
+ "0.675884, 0.898437, 1.082322, 1.376188, 1.943851",\
+ "0.683691, 0.906244, 1.090129, 1.383994, 1.951658",\
+ "0.697072, 0.919625, 1.103510, 1.397376, 1.965039",\
+ "0.849018, 1.071571, 1.255456, 1.549322, 2.116985",\
+ "1.182453, 1.405006, 1.588891, 1.882756, 2.450419",\
+ "0.739353, 0.956269, 1.140030, 1.433626, 2.000884",\
+ "0.747160, 0.964076, 1.147837, 1.441433, 2.008690",\
+ "0.760541, 0.977457, 1.161218, 1.454814, 2.022072",\
+ "0.912487, 1.129403, 1.313164, 1.606760, 2.174018",\
+ "1.245922, 1.462838, 1.646599, 1.940195, 2.507452",\
+ "1.074634, 1.261597, 1.443688, 1.736805, 2.303126",\
+ "1.082441, 1.269403, 1.451495, 1.744612, 2.310933",\
+ "1.095823, 1.282785, 1.464876, 1.757993, 2.324314",\
+ "1.247769, 1.434731, 1.616822, 1.909939, 2.476260",\
+ "1.581203, 1.768166, 1.950257, 2.243373, 2.809695");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2617*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[22]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.524148, 0.759556, 0.949466, 1.254683, 1.845217",\
+ "0.543365, 0.778772, 0.968683, 1.273899, 1.864433",\
+ "0.575013, 0.810420, 1.000331, 1.305547, 1.896082",\
+ "0.865602, 1.101009, 1.290920, 1.596136, 2.186671",\
+ "1.459605, 1.695012, 1.884923, 2.190139, 2.780674",\
+ "0.612629, 0.846874, 1.036747, 1.341988, 1.932570",\
+ "0.631845, 0.866090, 1.055964, 1.361204, 1.951787",\
+ "0.663493, 0.897739, 1.087612, 1.392852, 1.983435",\
+ "0.954082, 1.188328, 1.378201, 1.683442, 2.274024",\
+ "1.548085, 1.782331, 1.972204, 2.277444, 2.868027",\
+ "0.702172, 0.927207, 1.116774, 1.422016, 2.012602",\
+ "0.721389, 0.946423, 1.135991, 1.441233, 2.031818",\
+ "0.753037, 0.978072, 1.167639, 1.472881, 2.063467",\
+ "1.043626, 1.268661, 1.458228, 1.763470, 2.354056",\
+ "1.637629, 1.862664, 2.052231, 2.357473, 2.948059",\
+ "0.765979, 0.985042, 1.174496, 1.479482, 2.069690",\
+ "0.785195, 1.004258, 1.193712, 1.498699, 2.088906",\
+ "0.816843, 1.035906, 1.225360, 1.530347, 2.120554",\
+ "1.107432, 1.326495, 1.515949, 1.820936, 2.411143",\
+ "1.701435, 1.920498, 2.109952, 2.414939, 3.005147",\
+ "1.103410, 1.290390, 1.478156, 1.782685, 2.371999",\
+ "1.122626, 1.309606, 1.497372, 1.801901, 2.391215",\
+ "1.154274, 1.341254, 1.529020, 1.833550, 2.422863",\
+ "1.444863, 1.631843, 1.819609, 2.124139, 2.713452",\
+ "2.038866, 2.225846, 2.413612, 2.718142, 3.307455");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.536562, 0.771969, 0.961880, 1.267096, 1.857630",\
+ "0.544368, 0.779776, 0.969686, 1.274903, 1.865437",\
+ "0.557750, 0.793157, 0.983068, 1.288284, 1.878819",\
+ "0.709696, 0.945103, 1.135014, 1.440230, 2.030764",\
+ "1.043130, 1.278538, 1.468448, 1.773665, 2.364199",\
+ "0.625042, 0.859287, 1.049161, 1.354401, 1.944984",\
+ "0.632849, 0.867094, 1.056967, 1.362208, 1.952790",\
+ "0.646230, 0.880476, 1.070349, 1.375589, 1.966172",\
+ "0.798176, 1.032422, 1.222295, 1.527535, 2.118118",\
+ "1.131611, 1.365856, 1.555729, 1.860970, 2.451552",\
+ "0.714586, 0.939620, 1.129188, 1.434430, 2.025015",\
+ "0.722392, 0.947427, 1.136994, 1.442236, 2.032822",\
+ "0.735774, 0.960809, 1.150376, 1.455618, 2.046204",\
+ "0.887720, 1.112755, 1.302322, 1.607564, 2.198149",\
+ "1.221154, 1.446189, 1.635756, 1.940998, 2.531584",\
+ "0.778392, 0.997455, 1.186909, 1.491896, 2.082103",\
+ "0.786199, 1.005262, 1.194716, 1.499702, 2.089910",\
+ "0.799580, 1.018643, 1.208097, 1.513084, 2.103292",\
+ "0.951526, 1.170589, 1.360043, 1.665030, 2.255237",\
+ "1.284961, 1.504024, 1.693478, 1.998464, 2.588672",\
+ "1.115823, 1.302803, 1.490569, 1.795098, 2.384412",\
+ "1.123630, 1.310610, 1.498376, 1.802905, 2.392219",\
+ "1.137011, 1.323991, 1.511757, 1.816287, 2.405600",\
+ "1.288957, 1.475937, 1.663703, 1.968233, 2.557546",\
+ "1.622392, 1.809372, 1.997138, 2.301667, 2.890981");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[25]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.507236, 0.738300, 0.923184, 1.222269, 1.802199",\
+ "0.526452, 0.757517, 0.942400, 1.241485, 1.821415",\
+ "0.558100, 0.789165, 0.974048, 1.273133, 1.853063",\
+ "0.848689, 1.079754, 1.264637, 1.563722, 2.143652",\
+ "1.442692, 1.673757, 1.858641, 2.157725, 2.737655",\
+ "0.595614, 0.825618, 1.010465, 1.309574, 1.889552",\
+ "0.614831, 0.844835, 1.029681, 1.328790, 1.908768",\
+ "0.646479, 0.876483, 1.061329, 1.360438, 1.940417",\
+ "0.937068, 1.167072, 1.351918, 1.651027, 2.231006",\
+ "1.531071, 1.761075, 1.945922, 2.245030, 2.825009",\
+ "0.685193, 0.905949, 1.090492, 1.389602, 1.969584",\
+ "0.704409, 0.925165, 1.109708, 1.408819, 1.988800",\
+ "0.736058, 0.956813, 1.141356, 1.440467, 2.020448",\
+ "1.026647, 1.247402, 1.431945, 1.731056, 2.311038",\
+ "1.620650, 1.841405, 2.025949, 2.325059, 2.905041",\
+ "0.749178, 0.963779, 1.148202, 1.447056, 2.026647",\
+ "0.768394, 0.982995, 1.167418, 1.466272, 2.045864",\
+ "0.800042, 1.014643, 1.199067, 1.497920, 2.077512",\
+ "1.090631, 1.305233, 1.489656, 1.788509, 2.368101",\
+ "1.684634, 1.899235, 2.083659, 2.382513, 2.962104",\
+ "1.087729, 1.269086, 1.451859, 1.750247, 2.328927",\
+ "1.106946, 1.288302, 1.471076, 1.769464, 2.348143",\
+ "1.138594, 1.319950, 1.502724, 1.801112, 2.379791",\
+ "1.429183, 1.610539, 1.793313, 2.091701, 2.670381",\
+ "2.023186, 2.204542, 2.387316, 2.685704, 3.264384");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\
+ "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\
+ "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\
+ "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\
+ "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\
+ "2.193353, 2.193353, 2.193353, 2.193353, 2.193353");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.519649, 0.750714, 0.935597, 1.234682, 1.814612",\
+ "0.527456, 0.758521, 0.943404, 1.242489, 1.822419",\
+ "0.540837, 0.771902, 0.956786, 1.255870, 1.835800",\
+ "0.692783, 0.923848, 1.108731, 1.407816, 1.987746",\
+ "1.026218, 1.257282, 1.442166, 1.741251, 2.321181",\
+ "0.608028, 0.838032, 1.022878, 1.321987, 1.901966",\
+ "0.615835, 0.845838, 1.030685, 1.329794, 1.909772",\
+ "0.629216, 0.859220, 1.044067, 1.343176, 1.923154",\
+ "0.781162, 1.011166, 1.196012, 1.495121, 2.075100",\
+ "1.114597, 1.344600, 1.529447, 1.828556, 2.408534",\
+ "0.697607, 0.918362, 1.102905, 1.402016, 1.981997",\
+ "0.705413, 0.926169, 1.110712, 1.409823, 1.989804",\
+ "0.718795, 0.939550, 1.124094, 1.423204, 2.003186",\
+ "0.870741, 1.091496, 1.276039, 1.575150, 2.155131",\
+ "1.204175, 1.424931, 1.609474, 1.908584, 2.488566",\
+ "0.761591, 0.976192, 1.160616, 1.459469, 2.039061",\
+ "0.769398, 0.983999, 1.168422, 1.467276, 2.046868",\
+ "0.782779, 0.997381, 1.181804, 1.480658, 2.060249",\
+ "0.934725, 1.149326, 1.333750, 1.632603, 2.212195",\
+ "1.268160, 1.482761, 1.667184, 1.966038, 2.545630",\
+ "1.100143, 1.281499, 1.464273, 1.762661, 2.341341",\
+ "1.107950, 1.289306, 1.472080, 1.770468, 2.349147",\
+ "1.121331, 1.302687, 1.485461, 1.783849, 2.362529",\
+ "1.273277, 1.454633, 1.637407, 1.935795, 2.514474",\
+ "1.606712, 1.788068, 1.970841, 2.269229, 2.847909");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\
+ "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\
+ "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\
+ "1.002262, 1.002262, 1.002262, 1.002262, 1.002262");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2419*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[29]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.424754, 0.655573, 0.839933, 1.133631, 1.700828",\
+ "0.443986, 0.674805, 0.859165, 1.152863, 1.720060",\
+ "0.475654, 0.706473, 0.890833, 1.184531, 1.751728",\
+ "0.765910, 0.996730, 1.181089, 1.474787, 2.041985",\
+ "1.359893, 1.590712, 1.775072, 2.068770, 2.635967",\
+ "0.513060, 0.742891, 0.927214, 1.220936, 1.788182",\
+ "0.532291, 0.762123, 0.946446, 1.240168, 1.807413",\
+ "0.563959, 0.793791, 0.978114, 1.271836, 1.839081",\
+ "0.854216, 1.084048, 1.268370, 1.562092, 2.129338",\
+ "1.448198, 1.678030, 1.862353, 2.156075, 2.723320",\
+ "0.602427, 0.823222, 1.007241, 1.300965, 1.868213",\
+ "0.621658, 0.842453, 1.026473, 1.320196, 1.887445",\
+ "0.653326, 0.874121, 1.058141, 1.351864, 1.919113",\
+ "0.943583, 1.164378, 1.348397, 1.642121, 2.209370",\
+ "1.537565, 1.758360, 1.942380, 2.236103, 2.803352",\
+ "0.666215, 0.881051, 1.064950, 1.358403, 1.925246",\
+ "0.685446, 0.900283, 1.084182, 1.377634, 1.944478",\
+ "0.717114, 0.931951, 1.115850, 1.409302, 1.976146",\
+ "1.007371, 1.222207, 1.406106, 1.699559, 2.266402",\
+ "1.601353, 1.816190, 2.000089, 2.293541, 2.860385",\
+ "1.003512, 1.186351, 1.368608, 1.661581, 2.227489",\
+ "1.022744, 1.205583, 1.387839, 1.680812, 2.246720",\
+ "1.054412, 1.237251, 1.419507, 1.712481, 2.278388",\
+ "1.344668, 1.527507, 1.709764, 2.002737, 2.568645",\
+ "1.938651, 2.121490, 2.303746, 2.596720, 3.162627");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.436529, 0.667348, 0.851708, 1.145406, 1.712603",\
+ "0.444331, 0.675151, 0.859510, 1.153208, 1.720405",\
+ "0.457727, 0.688547, 0.872906, 1.166604, 1.733801",\
+ "0.609942, 0.840761, 1.025121, 1.318819, 1.886016",\
+ "0.943575, 1.174394, 1.358754, 1.652452, 2.219649",\
+ "0.524834, 0.754666, 0.938989, 1.232711, 1.799956",\
+ "0.532637, 0.762468, 0.946791, 1.240513, 1.807759",\
+ "0.546033, 0.775864, 0.960187, 1.253909, 1.821155",\
+ "0.698247, 0.928079, 1.112402, 1.406124, 1.973369",\
+ "1.031881, 1.261712, 1.446035, 1.739757, 2.307003",\
+ "0.614201, 0.834996, 1.019016, 1.312739, 1.879988",\
+ "0.622004, 0.842799, 1.026818, 1.320542, 1.887790",\
+ "0.635400, 0.856195, 1.040214, 1.333938, 1.901186",\
+ "0.787614, 1.008409, 1.192429, 1.486152, 2.053401",\
+ "1.121248, 1.342043, 1.526062, 1.819786, 2.387034",\
+ "0.677989, 0.892826, 1.076725, 1.370177, 1.937021",\
+ "0.685792, 0.900628, 1.084527, 1.377980, 1.944823",\
+ "0.699188, 0.914024, 1.097923, 1.391376, 1.958219",\
+ "0.851402, 1.066239, 1.250138, 1.543590, 2.110434",\
+ "1.185036, 1.399872, 1.583771, 1.877224, 2.444067",\
+ "1.015287, 1.198126, 1.380382, 1.673356, 2.239263",\
+ "1.023089, 1.205928, 1.388185, 1.681158, 2.247066",\
+ "1.036485, 1.219324, 1.401581, 1.694554, 2.260462",\
+ "1.188700, 1.371539, 1.553795, 1.846768, 2.412676",\
+ "1.522333, 1.705172, 1.887429, 2.180402, 2.746310");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2319*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[30]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.417176, 0.631777, 0.810666, 1.100090, 1.661570",\
+ "0.436407, 0.651008, 0.829897, 1.119321, 1.680801",\
+ "0.468075, 0.682676, 0.861565, 1.150989, 1.712470",\
+ "0.758331, 0.972932, 1.151822, 1.441245, 2.002726",\
+ "1.352314, 1.566915, 1.745804, 2.035228, 2.596708",\
+ "0.505449, 0.719094, 0.897947, 1.187395, 1.748923",\
+ "0.524681, 0.738326, 0.917178, 1.206626, 1.768155",\
+ "0.556349, 0.769994, 0.948847, 1.238294, 1.799823",\
+ "0.846605, 1.060250, 1.239103, 1.528551, 2.090079",\
+ "1.440588, 1.654232, 1.833085, 2.122533, 2.684062",\
+ "0.594993, 0.799422, 0.977974, 1.267423, 1.828955",\
+ "0.614224, 0.818654, 0.997205, 1.286655, 1.848186",\
+ "0.645892, 0.850322, 1.028873, 1.318323, 1.879855",\
+ "0.936148, 1.140578, 1.319129, 1.608579, 2.170111",\
+ "1.530131, 1.734560, 1.913112, 2.202561, 2.764093",\
+ "0.659061, 0.857252, 1.035670, 1.324854, 1.885975",\
+ "0.678293, 0.876483, 1.054902, 1.344086, 1.905207",\
+ "0.709961, 0.908151, 1.086570, 1.375754, 1.936875",\
+ "1.000217, 1.198407, 1.376826, 1.666010, 2.227131",\
+ "1.594199, 1.792390, 1.970809, 2.259993, 2.821113",\
+ "0.982918, 1.162544, 1.339325, 1.628026, 2.188202",\
+ "1.002150, 1.181776, 1.358556, 1.647258, 2.207434",\
+ "1.033818, 1.213444, 1.390224, 1.678926, 2.239102",\
+ "1.324074, 1.503700, 1.680480, 1.969182, 2.529358",\
+ "1.918056, 2.097682, 2.274463, 2.563165, 3.123341");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.428949, 0.643550, 0.822439, 1.111863, 1.673344",\
+ "0.436752, 0.651353, 0.830242, 1.119666, 1.681146",\
+ "0.450148, 0.664749, 0.843638, 1.133062, 1.694542",\
+ "0.602363, 0.816964, 0.995853, 1.285277, 1.846757",\
+ "0.935996, 1.150597, 1.329487, 1.618910, 2.180391",\
+ "0.517223, 0.730868, 0.909721, 1.199168, 1.760697",\
+ "0.525026, 0.738670, 0.917523, 1.206971, 1.768500",\
+ "0.538422, 0.752066, 0.930919, 1.220367, 1.781896",\
+ "0.690637, 0.904281, 1.083134, 1.372582, 1.934110",\
+ "1.024270, 1.237915, 1.416768, 1.706216, 2.267744",\
+ "0.606766, 0.811196, 0.989747, 1.279197, 1.840729",\
+ "0.614569, 0.818998, 0.997550, 1.286999, 1.848531",\
+ "0.627965, 0.832394, 1.010946, 1.300395, 1.861927",\
+ "0.780180, 0.984609, 1.163161, 1.452610, 2.014142",\
+ "1.113814, 1.318243, 1.496794, 1.786244, 2.347776",\
+ "0.670835, 0.869025, 1.047444, 1.336628, 1.897749",\
+ "0.678637, 0.876828, 1.055247, 1.344431, 1.905551",\
+ "0.692033, 0.890224, 1.068643, 1.357827, 1.918947",\
+ "0.844248, 1.042439, 1.220857, 1.510042, 2.071162",\
+ "1.177882, 1.376072, 1.554491, 1.843675, 2.404796",\
+ "0.994692, 1.174318, 1.351099, 1.639800, 2.199976",\
+ "1.002494, 1.182121, 1.358901, 1.647603, 2.207778",\
+ "1.015890, 1.195517, 1.372297, 1.660999, 2.221174",\
+ "1.168105, 1.347732, 1.524512, 1.813214, 2.373389",\
+ "1.501739, 1.681365, 1.858145, 2.146847, 2.707023");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2377*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[34]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.566889, 0.778471, 0.964383, 1.255517, 1.814850",\
+ "0.586120, 0.797703, 0.983615, 1.274748, 1.834081",\
+ "0.617788, 0.829371, 1.015283, 1.306417, 1.865749",\
+ "0.908045, 1.119627, 1.305539, 1.596673, 2.156006",\
+ "1.502027, 1.713610, 1.899522, 2.190655, 2.749988",\
+ "0.655251, 0.865790, 1.051664, 1.342822, 1.902203",\
+ "0.674483, 0.885021, 1.070896, 1.362054, 1.921435",\
+ "0.706151, 0.916689, 1.102564, 1.393722, 1.953103",\
+ "0.996407, 1.206946, 1.392820, 1.683978, 2.243359",\
+ "1.590390, 1.800928, 1.986803, 2.277961, 2.837342",\
+ "0.744310, 0.946124, 1.131691, 1.422850, 1.982235",\
+ "0.763542, 0.965355, 1.150923, 1.442082, 2.001466",\
+ "0.795210, 0.997024, 1.182591, 1.473750, 2.033134",\
+ "1.085467, 1.287280, 1.472847, 1.764007, 2.323391",\
+ "1.679449, 1.881263, 2.066830, 2.357989, 2.917373",\
+ "0.807605, 1.003952, 1.189403, 1.480278, 2.039247",\
+ "0.826837, 1.023183, 1.208634, 1.499510, 2.058478",\
+ "0.858505, 1.054851, 1.240302, 1.531178, 2.090147",\
+ "1.148761, 1.345108, 1.530559, 1.821435, 2.380403",\
+ "1.742744, 1.939090, 2.124541, 2.415417, 2.974385",\
+ "1.127529, 1.309255, 1.493062, 1.783449, 2.341464",\
+ "1.146761, 1.328487, 1.512293, 1.802681, 2.360695",\
+ "1.178429, 1.360155, 1.543962, 1.834349, 2.392364",\
+ "1.468686, 1.650411, 1.834218, 2.124605, 2.682620",\
+ "2.062668, 2.244394, 2.428200, 2.718588, 3.276602");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.578663, 0.790246, 0.976158, 1.267292, 1.826624",\
+ "0.586466, 0.798048, 0.983960, 1.275094, 1.834427",\
+ "0.599862, 0.811444, 0.997356, 1.288490, 1.847823",\
+ "0.752076, 0.963659, 1.149571, 1.440704, 2.000037",\
+ "1.085710, 1.297292, 1.483204, 1.774338, 2.333671",\
+ "0.667026, 0.877564, 1.063439, 1.354597, 1.913978",\
+ "0.674828, 0.885367, 1.071241, 1.362399, 1.921780",\
+ "0.688224, 0.898763, 1.084637, 1.375795, 1.935176",\
+ "0.840439, 1.050977, 1.236852, 1.528010, 2.087391",\
+ "1.174072, 1.384611, 1.570485, 1.861643, 2.421024",\
+ "0.756085, 0.957898, 1.143466, 1.434625, 1.994009",\
+ "0.763888, 0.965701, 1.151268, 1.442428, 2.001812",\
+ "0.777284, 0.979097, 1.164664, 1.455824, 2.015208",\
+ "0.929498, 1.131311, 1.316879, 1.608038, 2.167422",\
+ "1.263131, 1.464945, 1.650512, 1.941671, 2.501056",\
+ "0.819380, 1.015726, 1.201177, 1.492053, 2.051021",\
+ "0.827182, 1.023529, 1.208980, 1.499856, 2.058824",\
+ "0.840578, 1.036925, 1.222376, 1.513252, 2.072220",\
+ "0.992793, 1.189139, 1.374590, 1.665466, 2.224434",\
+ "1.326426, 1.522773, 1.708224, 1.999099, 2.558068",\
+ "1.139304, 1.321030, 1.504837, 1.795224, 2.353239",\
+ "1.147106, 1.328832, 1.512639, 1.803026, 2.361041",\
+ "1.160502, 1.342228, 1.526035, 1.816422, 2.374437",\
+ "1.312717, 1.494443, 1.678249, 1.968637, 2.526651",\
+ "1.646350, 1.828076, 2.011883, 2.302270, 2.860285");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2596*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[35]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.541408, 0.751703, 0.928714, 1.212888, 1.762989",\
+ "0.560640, 0.770935, 0.947946, 1.232119, 1.782221",\
+ "0.592308, 0.802603, 0.979614, 1.263787, 1.813889",\
+ "0.882565, 1.092860, 1.269870, 1.554044, 2.104145",\
+ "1.476547, 1.686842, 1.863853, 2.148026, 2.698128",\
+ "0.629685, 0.839022, 1.015995, 1.300193, 1.850343",\
+ "0.648917, 0.858253, 1.035227, 1.319424, 1.869574",\
+ "0.680585, 0.889921, 1.066895, 1.351092, 1.901242",\
+ "0.970842, 1.180178, 1.357151, 1.641349, 2.191499",\
+ "1.564824, 1.774160, 1.951134, 2.235331, 2.785481",\
+ "0.718639, 0.919355, 1.096022, 1.380221, 1.930374",\
+ "0.737870, 0.938586, 1.115254, 1.399453, 1.949606",\
+ "0.769538, 0.970254, 1.146922, 1.431121, 1.981274",\
+ "1.059795, 1.260511, 1.437178, 1.721377, 2.271530",\
+ "1.653777, 1.854493, 2.031161, 2.315360, 2.865513",\
+ "0.781897, 0.977177, 1.153713, 1.437638, 1.987364",\
+ "0.801129, 0.996408, 1.172945, 1.456870, 2.006596",\
+ "0.832797, 1.028076, 1.204613, 1.488538, 2.038264",\
+ "1.123053, 1.318333, 1.494869, 1.778794, 2.328521",\
+ "1.717036, 1.912315, 2.088852, 2.372777, 2.922503",\
+ "1.102548, 1.282436, 1.457368, 1.740799, 2.289555",\
+ "1.121780, 1.301668, 1.476600, 1.760030, 2.308787",\
+ "1.153448, 1.333336, 1.508268, 1.791698, 2.340455",\
+ "1.443705, 1.623593, 1.798525, 2.081955, 2.630712",\
+ "2.037687, 2.217575, 2.392507, 2.675937, 3.224694");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\
+ "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194227, 2.194227, 2.194227, 2.194227, 2.194227");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.553183, 0.763478, 0.940489, 1.224662, 1.774764",\
+ "0.560986, 0.771280, 0.948291, 1.232465, 1.782566",\
+ "0.574382, 0.784676, 0.961687, 1.245861, 1.795962",\
+ "0.726596, 0.936891, 1.113902, 1.398075, 1.948177",\
+ "1.060230, 1.270525, 1.447535, 1.731709, 2.281810",\
+ "0.641460, 0.850796, 1.027770, 1.311967, 1.862117",\
+ "0.649263, 0.858599, 1.035572, 1.319770, 1.869920",\
+ "0.662659, 0.871995, 1.048968, 1.333166, 1.883316",\
+ "0.814873, 1.024209, 1.201183, 1.485380, 2.035530",\
+ "1.148507, 1.357843, 1.534816, 1.819014, 2.369164",\
+ "0.730413, 0.931129, 1.107797, 1.391996, 1.942149",\
+ "0.738216, 0.938932, 1.115599, 1.399798, 1.949951",\
+ "0.751612, 0.952328, 1.128995, 1.413194, 1.963347",\
+ "0.903826, 1.104542, 1.281210, 1.565409, 2.115561",\
+ "1.237460, 1.438176, 1.614843, 1.899042, 2.449195",\
+ "0.793672, 0.988951, 1.165488, 1.449413, 1.999139",\
+ "0.801474, 0.996754, 1.173290, 1.457215, 2.006941",\
+ "0.814870, 1.010150, 1.186686, 1.470611, 2.020338",\
+ "0.967085, 1.162364, 1.338901, 1.622826, 2.172552",\
+ "1.300718, 1.495998, 1.672534, 1.956459, 2.506185",\
+ "1.114323, 1.294211, 1.469143, 1.752573, 2.301330",\
+ "1.122126, 1.302013, 1.476946, 1.760376, 2.309132",\
+ "1.135522, 1.315410, 1.490342, 1.773772, 2.322528",\
+ "1.287736, 1.467624, 1.642556, 1.925986, 2.474743",\
+ "1.621369, 1.801257, 1.976189, 2.259620, 2.808376");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2653*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[38]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.563785, 0.784261, 0.961831, 1.250241, 1.810232",\
+ "0.583017, 0.803492, 0.981063, 1.269472, 1.829463",\
+ "0.614685, 0.835161, 1.012731, 1.301141, 1.861132",\
+ "0.904941, 1.125417, 1.302987, 1.591397, 2.151388",\
+ "1.498924, 1.719399, 1.896969, 2.185379, 2.745370",\
+ "0.652174, 0.871579, 1.049112, 1.337546, 1.897585",\
+ "0.671405, 0.890811, 1.068343, 1.356778, 1.916817",\
+ "0.703073, 0.922479, 1.100012, 1.388446, 1.948485",\
+ "0.993330, 1.212735, 1.390268, 1.678702, 2.238741",\
+ "1.587312, 1.806717, 1.984250, 2.272684, 2.832724",\
+ "0.741539, 0.951911, 1.129139, 1.417575, 1.977617",\
+ "0.760771, 0.971143, 1.148370, 1.436806, 1.996849",\
+ "0.792439, 1.002811, 1.180039, 1.468474, 2.028517",\
+ "1.082695, 1.293067, 1.470295, 1.758730, 2.318773",\
+ "1.676677, 1.887050, 2.064277, 2.352713, 2.912755",\
+ "0.805219, 1.009732, 1.186831, 1.475004, 2.034631",\
+ "0.824451, 1.028963, 1.206063, 1.494235, 2.053863",\
+ "0.856119, 1.060631, 1.237731, 1.525903, 2.085531",\
+ "1.146375, 1.350887, 1.527987, 1.816159, 2.375787",\
+ "1.740357, 1.944870, 2.121970, 2.410142, 2.969770",\
+ "1.135828, 1.314976, 1.490487, 1.778174, 2.336852",\
+ "1.155060, 1.334207, 1.509718, 1.797406, 2.356083",\
+ "1.186728, 1.365875, 1.541386, 1.829074, 2.387752",\
+ "1.476984, 1.656131, 1.831642, 2.119330, 2.678008",\
+ "2.070967, 2.250114, 2.425625, 2.713313, 3.271990");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.575559, 0.796035, 0.973605, 1.262015, 1.822006",\
+ "0.583362, 0.803837, 0.981407, 1.269817, 1.829808",\
+ "0.596758, 0.817233, 0.994803, 1.283213, 1.843204",\
+ "0.748972, 0.969448, 1.147018, 1.435428, 1.995419",\
+ "1.082606, 1.303082, 1.480652, 1.769062, 2.329053",\
+ "0.663947, 0.883353, 1.060886, 1.349320, 1.909359",\
+ "0.671750, 0.891155, 1.068688, 1.357122, 1.917162",\
+ "0.685146, 0.904551, 1.082084, 1.370518, 1.930558",\
+ "0.837361, 1.056766, 1.234299, 1.522733, 2.082772",\
+ "1.170995, 1.390400, 1.567933, 1.856367, 2.416406",\
+ "0.753313, 0.963685, 1.140913, 1.429348, 1.989391",\
+ "0.761115, 0.971488, 1.148715, 1.437151, 1.997193",\
+ "0.774511, 0.984884, 1.162111, 1.450547, 2.010589",\
+ "0.926726, 1.137099, 1.314326, 1.602762, 2.162804",\
+ "1.260360, 1.470732, 1.647960, 1.936395, 2.496438",\
+ "0.816993, 1.021505, 1.198605, 1.486777, 2.046405",\
+ "0.824796, 1.029308, 1.206408, 1.494580, 2.054208",\
+ "0.838192, 1.042704, 1.219804, 1.507976, 2.067604",\
+ "0.990406, 1.194919, 1.372019, 1.660191, 2.219819",\
+ "1.324040, 1.528552, 1.705652, 1.993824, 2.553452",\
+ "1.147602, 1.326749, 1.502260, 1.789948, 2.348625",\
+ "1.155405, 1.334552, 1.510063, 1.797751, 2.356428",\
+ "1.168801, 1.347948, 1.523459, 1.811147, 2.369824",\
+ "1.321016, 1.500163, 1.675674, 1.963362, 2.522039",\
+ "1.654649, 1.833796, 2.009307, 2.296995, 2.855672");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2304*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[39]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.537611, 0.765413, 0.949557, 1.244019, 1.813116",\
+ "0.556843, 0.784645, 0.968788, 1.263250, 1.832347",\
+ "0.588511, 0.816313, 1.000457, 1.294918, 1.864016",\
+ "0.878767, 1.106569, 1.290713, 1.585174, 2.154272",\
+ "1.472749, 1.700552, 1.884695, 2.179157, 2.748254",\
+ "0.625940, 0.852732, 1.036838, 1.331324, 1.900469",\
+ "0.645171, 0.871963, 1.056069, 1.350555, 1.919701",\
+ "0.676839, 0.903631, 1.087738, 1.382223, 1.951369",\
+ "0.967095, 1.193887, 1.377994, 1.672480, 2.241625",\
+ "1.561078, 1.787870, 1.971976, 2.266462, 2.835608",\
+ "0.715049, 0.933065, 1.116865, 1.411352, 1.980501",\
+ "0.734280, 0.952296, 1.136096, 1.430584, 1.999732",\
+ "0.765948, 0.983964, 1.167764, 1.462252, 2.031401",\
+ "1.056204, 1.274220, 1.458020, 1.752508, 2.321657",\
+ "1.650187, 1.868203, 2.052003, 2.346490, 2.915639",\
+ "0.778454, 0.990889, 1.174573, 1.468792, 2.037537",\
+ "0.797686, 1.010120, 1.193804, 1.488024, 2.056769",\
+ "0.829354, 1.041789, 1.225472, 1.519692, 2.088437",\
+ "1.119610, 1.332045, 1.515728, 1.809948, 2.378693",\
+ "1.713592, 1.926027, 2.109711, 2.403930, 2.972675",\
+ "1.113336, 1.296163, 1.478231, 1.771973, 2.339783",\
+ "1.132567, 1.315395, 1.497462, 1.791204, 2.359015",\
+ "1.164236, 1.347063, 1.529130, 1.822872, 2.390683",\
+ "1.454492, 1.637319, 1.819386, 2.113128, 2.680939",\
+ "2.048474, 2.231302, 2.413369, 2.707111, 3.274921");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\
+ "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\
+ "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\
+ "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\
+ "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\
+ "2.194229, 2.194229, 2.194229, 2.194229, 2.194229");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.549385, 0.777187, 0.961331, 1.255792, 1.824890",\
+ "0.557187, 0.784990, 0.969133, 1.263595, 1.832692",\
+ "0.570583, 0.798386, 0.982529, 1.276991, 1.846088",\
+ "0.722798, 0.950600, 1.134744, 1.429206, 1.998303",\
+ "1.056432, 1.284234, 1.468378, 1.762839, 2.331937",\
+ "0.637713, 0.864505, 1.048611, 1.343097, 1.912243",\
+ "0.645516, 0.872308, 1.056414, 1.350900, 1.920045",\
+ "0.658912, 0.885704, 1.069810, 1.364296, 1.933442",\
+ "0.811127, 1.037919, 1.222025, 1.516511, 2.085656",\
+ "1.144760, 1.371552, 1.555659, 1.850145, 2.419290",\
+ "0.726822, 0.944838, 1.128638, 1.423126, 1.992275",\
+ "0.734625, 0.952641, 1.136441, 1.430928, 2.000077",\
+ "0.748021, 0.966037, 1.149837, 1.444324, 2.013473",\
+ "0.900236, 1.118252, 1.302052, 1.596539, 2.165688",\
+ "1.233869, 1.451885, 1.635685, 1.930173, 2.499322",\
+ "0.790228, 1.002663, 1.186347, 1.480566, 2.049311",\
+ "0.798030, 1.010465, 1.194149, 1.488369, 2.057113",\
+ "0.811427, 1.023861, 1.207545, 1.501765, 2.070509",\
+ "0.963641, 1.176076, 1.359760, 1.653979, 2.222724",\
+ "1.297275, 1.509710, 1.693393, 1.987613, 2.556358",\
+ "1.125110, 1.307937, 1.490004, 1.783746, 2.351557",\
+ "1.132912, 1.315740, 1.497807, 1.791549, 2.359360",\
+ "1.146308, 1.329136, 1.511203, 1.804945, 2.372756",\
+ "1.298523, 1.481350, 1.663418, 1.957160, 2.524971",\
+ "1.632157, 1.814984, 1.997051, 2.290793, 2.858604");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\
+ "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\
+ "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\
+ "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\
+ "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\
+ "1.002321, 1.002321, 1.002321, 1.002321, 1.002321");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2347*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[40]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.452626, 0.644345, 0.833940, 1.131261, 1.702487",\
+ "0.471843, 0.663562, 0.853157, 1.150478, 1.721704",\
+ "0.503492, 0.695211, 0.884806, 1.182126, 1.753352",\
+ "0.794073, 0.985792, 1.175388, 1.472708, 2.043935",\
+ "1.388076, 1.579795, 1.769390, 2.066711, 2.637938",\
+ "0.540843, 0.731664, 0.921221, 1.218566, 1.789840",\
+ "0.560059, 0.750880, 0.940438, 1.237783, 1.809057",\
+ "0.591708, 0.782529, 0.972087, 1.269431, 1.840706",\
+ "0.882290, 1.073111, 1.262668, 1.560013, 2.131288",\
+ "1.476292, 1.667113, 1.856671, 2.154016, 2.725291",\
+ "0.629383, 0.811999, 1.001248, 1.298594, 1.869872",\
+ "0.648600, 0.831216, 1.020465, 1.317811, 1.889089",\
+ "0.680249, 0.862864, 1.052114, 1.349460, 1.920737",\
+ "0.970830, 1.153446, 1.342695, 1.640042, 2.211320",\
+ "1.564833, 1.747448, 1.936698, 2.234045, 2.805323",\
+ "0.690888, 0.869827, 1.058969, 1.356037, 1.926912",\
+ "0.710105, 0.889043, 1.078185, 1.375254, 1.946129",\
+ "0.741754, 0.920692, 1.109834, 1.406902, 1.977778",\
+ "1.032335, 1.211274, 1.400416, 1.697484, 2.268360",\
+ "1.626338, 1.805276, 1.994418, 2.291487, 2.862363",\
+ "0.993056, 1.175134, 1.362629, 1.659220, 2.229164",\
+ "1.012272, 1.194351, 1.381846, 1.678436, 2.248380",\
+ "1.043921, 1.226000, 1.413495, 1.710085, 2.280029",\
+ "1.334502, 1.516581, 1.704077, 2.000667, 2.570611",\
+ "1.928505, 2.110584, 2.298079, 2.594670, 3.164614");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\
+ "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\
+ "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\
+ "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\
+ "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\
+ "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\
+ "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\
+ "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\
+ "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\
+ "2.193373, 2.193373, 2.193373, 2.193372, 2.193370");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.465025, 0.656744, 0.846340, 1.143661, 1.714888",\
+ "0.472832, 0.664551, 0.854146, 1.151467, 1.722695",\
+ "0.486213, 0.677933, 0.867528, 1.164849, 1.736077",\
+ "0.638165, 0.829885, 1.019480, 1.316801, 1.888028",\
+ "0.971605, 1.163324, 1.352919, 1.650240, 2.221466",\
+ "0.553242, 0.744063, 0.933621, 1.230966, 1.802242",\
+ "0.561048, 0.751869, 0.941427, 1.238772, 1.810048",\
+ "0.574430, 0.765251, 0.954809, 1.252154, 1.823430",\
+ "0.726382, 0.917203, 1.106761, 1.404106, 1.975381",\
+ "1.059821, 1.250642, 1.440200, 1.737545, 2.308820",\
+ "0.641782, 0.824398, 1.013648, 1.310994, 1.882273",\
+ "0.649589, 0.832204, 1.021454, 1.318801, 1.890080",\
+ "0.662971, 0.845586, 1.034836, 1.332183, 1.903462",\
+ "0.814923, 0.997538, 1.186788, 1.484134, 2.055413",\
+ "1.148362, 1.330977, 1.520227, 1.817573, 2.388851",\
+ "0.703287, 0.882226, 1.071368, 1.368437, 1.939313",\
+ "0.711094, 0.890032, 1.079175, 1.376243, 1.947120",\
+ "0.724476, 0.903414, 1.092556, 1.389625, 1.960502",\
+ "0.876427, 1.055366, 1.244508, 1.541577, 2.112453",\
+ "1.209867, 1.388805, 1.577947, 1.875016, 2.445891",\
+ "1.005455, 1.187533, 1.375029, 1.671620, 2.241565",\
+ "1.013261, 1.195340, 1.382835, 1.679426, 2.249371",\
+ "1.026643, 1.208722, 1.396217, 1.692808, 2.262753",\
+ "1.178595, 1.360674, 1.548169, 1.844760, 2.414704",\
+ "1.512034, 1.694113, 1.881608, 2.178198, 2.748142");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\
+ "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\
+ "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\
+ "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\
+ "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2394*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[42]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.181258, 0.362750, 0.559584, 0.877059, 1.491654",\
+ "0.196091, 0.377154, 0.575199, 0.895881, 1.517263",\
+ "0.221299, 0.401436, 0.600771, 0.925894, 1.556997",\
+ "0.494050, 0.669272, 0.865120, 1.207435, 1.883536",\
+ "1.086888, 1.260498, 1.453339, 1.802428, 2.497703",\
+ "0.268666, 0.450068, 0.646865, 0.964364, 1.579007",\
+ "0.283499, 0.464472, 0.662480, 0.983186, 1.604617",\
+ "0.308707, 0.488754, 0.688052, 1.013199, 1.644350",\
+ "0.581459, 0.756590, 0.952401, 1.294740, 1.970890",\
+ "1.174296, 1.347816, 1.540620, 1.889733, 2.585056",\
+ "0.349534, 0.530400, 0.726892, 1.044393, 1.659039",\
+ "0.364365, 0.544804, 0.742507, 1.063215, 1.684648",\
+ "0.389566, 0.569086, 0.768079, 1.093227, 1.724382",\
+ "0.662286, 0.836922, 1.032428, 1.374768, 2.050921",\
+ "1.255114, 1.428148, 1.620646, 1.969761, 2.665088",\
+ "0.407230, 0.588238, 0.784630, 1.101888, 1.716185",\
+ "0.422055, 0.602641, 0.800248, 1.120718, 1.741811",\
+ "0.447245, 0.626919, 0.825823, 1.150743, 1.781568",\
+ "0.719903, 0.894737, 1.090165, 1.432339, 2.108216",\
+ "1.312710, 1.485957, 1.678376, 2.027355, 2.722429",\
+ "0.710204, 0.893608, 1.088293, 1.405116, 2.018565",\
+ "0.724980, 0.907999, 1.103911, 1.423953, 2.044210",\
+ "0.750065, 0.932253, 1.129487, 1.453987, 2.083996",\
+ "1.022164, 1.199940, 1.393827, 1.735630, 2.410775",\
+ "1.614788, 1.791118, 1.982037, 2.330666, 3.025044");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\
+ "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\
+ "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\
+ "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\
+ "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\
+ "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\
+ "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\
+ "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\
+ "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\
+ "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\
+ "0.126849, 0.127605, 0.133435, 0.151631, 0.191178",\
+ "0.149775, 0.150309, 0.154650, 0.170542, 0.205735",\
+ "0.195028, 0.195582, 0.198470, 0.210618, 0.237900",\
+ "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\
+ "2.194129, 2.194405, 2.194418, 2.195894, 2.199512",\
+ "0.126859, 0.127607, 0.133449, 0.151680, 0.191274",\
+ "0.149782, 0.150311, 0.154660, 0.170585, 0.205820",\
+ "0.195035, 0.195584, 0.198477, 0.210651, 0.237965",\
+ "0.816155, 0.816256, 0.816260, 0.817810, 0.821601",\
+ "2.194133, 2.194406, 2.194418, 2.195898, 2.199521",\
+ "0.126945, 0.127627, 0.133451, 0.151721, 0.191389",\
+ "0.149843, 0.150326, 0.154662, 0.170622, 0.205922",\
+ "0.195098, 0.195599, 0.198478, 0.210679, 0.238045",\
+ "0.816166, 0.816259, 0.816260, 0.817813, 0.821612",\
+ "2.194165, 2.194413, 2.194418, 2.195902, 2.199532");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.117102, 0.379947, 0.573156, 0.882174, 1.479232",\
+ "0.126091, 0.389068, 0.582472, 0.892519, 1.491929",\
+ "0.141699, 0.404157, 0.597820, 0.909153, 1.511489",\
+ "0.306945, 0.562483, 0.755606, 1.068523, 1.675209",\
+ "0.649757, 0.897030, 1.089718, 1.401787, 2.006775",\
+ "0.205481, 0.467265, 0.660437, 0.969479, 1.566586",\
+ "0.214473, 0.476386, 0.669753, 0.979824, 1.579283",\
+ "0.230076, 0.491475, 0.685100, 0.996458, 1.598842",\
+ "0.395245, 0.649801, 0.842887, 1.155828, 1.762562",\
+ "0.738017, 0.984348, 1.176999, 1.489092, 2.094129",\
+ "0.294834, 0.547598, 0.740463, 1.049507, 1.646617",\
+ "0.303840, 0.556719, 0.749780, 1.059852, 1.659314",\
+ "0.319425, 0.571807, 0.765127, 1.076486, 1.678874",\
+ "0.484368, 0.730134, 0.922914, 1.235856, 1.842594",\
+ "0.827025, 1.064680, 1.257025, 1.569121, 2.174160",\
+ "0.358511, 0.605438, 0.798193, 1.106982, 1.703722",\
+ "0.367529, 0.614560, 0.807510, 1.117329, 1.716424",\
+ "0.383098, 0.629648, 0.822858, 1.133967, 1.735991",\
+ "0.547830, 0.787974, 0.980643, 1.293342, 1.899721",\
+ "0.890379, 1.122520, 1.314754, 1.626604, 2.231284",\
+ "0.695115, 0.910825, 1.101854, 1.410191, 2.006050",\
+ "0.704209, 0.919948, 1.111171, 1.420541, 2.018759",\
+ "0.719674, 0.935035, 1.126519, 1.437182, 2.038335",\
+ "0.883062, 1.093358, 1.284304, 1.596561, 2.202077",\
+ "1.224926, 1.427904, 1.618415, 1.929822, 2.533635");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.044794, 0.049393, 0.054601, 0.068665, 0.098782",\
+ "0.053408, 0.055750, 0.059102, 0.072238, 0.101610",\
+ "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\
+ "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\
+ "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\
+ "0.044917, 0.049393, 0.054601, 0.068665, 0.098782",\
+ "0.053471, 0.055750, 0.059102, 0.072238, 0.101610",\
+ "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\
+ "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\
+ "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\
+ "0.045280, 0.049393, 0.054601, 0.068665, 0.098782",\
+ "0.053656, 0.055750, 0.059102, 0.072238, 0.101610",\
+ "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\
+ "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\
+ "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\
+ "0.045619, 0.049410, 0.054613, 0.068702, 0.098855",\
+ "0.053828, 0.055759, 0.059110, 0.072274, 0.101681",\
+ "0.075784, 0.075784, 0.078001, 0.088634, 0.112740",\
+ "0.368045, 0.368045, 0.368835, 0.370660, 0.374443",\
+ "1.001402, 1.001402, 1.001777, 1.002639, 1.004426",\
+ "0.047777, 0.049532, 0.054615, 0.068733, 0.098943",\
+ "0.054927, 0.055821, 0.059111, 0.072304, 0.101766",\
+ "0.075784, 0.075784, 0.078002, 0.088659, 0.112810",\
+ "0.368045, 0.368045, 0.368835, 0.370664, 0.374454",\
+ "1.001402, 1.001402, 1.001777, 1.002641, 1.004432");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2316*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[43]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.098350, 0.258117, 0.412724, 0.663632, 1.151052",\
+ "0.111306, 0.279646, 0.445289, 0.710490, 1.223646",\
+ "0.138089, 0.311436, 0.490658, 0.774246, 1.320793",\
+ "0.424991, 0.637508, 0.825514, 1.153509, 1.801342",\
+ "1.020536, 1.249709, 1.439386, 1.764952, 2.405506",\
+ "0.185759, 0.345435, 0.500005, 0.750937, 1.238405",\
+ "0.198715, 0.366964, 0.532570, 0.797795, 1.310999",\
+ "0.225498, 0.398754, 0.577939, 0.861551, 1.408146",\
+ "0.513280, 0.724826, 0.912795, 1.240814, 1.888696",\
+ "1.108868, 1.337027, 1.526667, 1.852257, 2.492859",\
+ "0.266486, 0.425768, 0.580032, 0.830966, 1.318437",\
+ "0.279498, 0.447297, 0.612597, 0.877824, 1.391031",\
+ "0.306314, 0.479087, 0.657966, 0.941579, 1.488178",\
+ "0.602279, 0.805159, 0.992822, 1.320843, 1.968727",\
+ "1.197992, 1.417360, 1.606694, 1.932286, 2.572891",\
+ "0.323899, 0.483524, 0.637672, 0.888307, 1.375276",\
+ "0.337018, 0.505085, 0.670262, 0.935196, 1.447932",\
+ "0.363897, 0.536894, 0.715662, 0.998992, 1.545160",\
+ "0.665584, 0.862970, 1.050539, 1.378378, 2.025954",\
+ "1.261413, 1.475185, 1.664415, 1.989812, 2.630099",\
+ "0.624253, 0.788317, 0.941319, 1.191402, 1.677284",\
+ "0.638351, 0.810106, 0.973913, 1.238318, 1.750015",\
+ "0.665802, 0.842047, 1.019319, 1.302149, 1.847340",\
+ "0.990853, 1.168154, 1.354199, 1.681640, 2.328429",\
+ "1.596393, 1.780461, 1.968075, 2.293067, 2.932554");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.028418, 0.053830, 0.061535, 0.076150, 0.106328",\
+ "0.053925, 0.080459, 0.084933, 0.098494, 0.128975",\
+ "0.117469, 0.123739, 0.136658, 0.151484, 0.176772",\
+ "0.813025, 0.813025, 0.813025, 0.814972, 0.819748",\
+ "2.191689, 2.192946, 2.194005, 2.200700, 2.216248",\
+ "0.028418, 0.053830, 0.061535, 0.076150, 0.106328",\
+ "0.053925, 0.080459, 0.084933, 0.098494, 0.128975",\
+ "0.117469, 0.123739, 0.136658, 0.151484, 0.176772",\
+ "0.813025, 0.813025, 0.813025, 0.814972, 0.819748",\
+ "2.191723, 2.192946, 2.194005, 2.200700, 2.216248",\
+ "0.028584, 0.053830, 0.061535, 0.076150, 0.106328",\
+ "0.054098, 0.080459, 0.084933, 0.098494, 0.128975",\
+ "0.117510, 0.123739, 0.136658, 0.151484, 0.176772",\
+ "0.813025, 0.813025, 0.813025, 0.814972, 0.819748",\
+ "2.191823, 2.192946, 2.194005, 2.200700, 2.216248",\
+ "0.028905, 0.053925, 0.061551, 0.076187, 0.106401",\
+ "0.054433, 0.080559, 0.084941, 0.098531, 0.129049",\
+ "0.117589, 0.123763, 0.136688, 0.151514, 0.176833",\
+ "0.813025, 0.813025, 0.813025, 0.814978, 0.819760",\
+ "2.191915, 2.192951, 2.194008, 2.200718, 2.216285",\
+ "0.031805, 0.054598, 0.061553, 0.076218, 0.106489",\
+ "0.057461, 0.081261, 0.084942, 0.098563, 0.129138",\
+ "0.118304, 0.123929, 0.136693, 0.151541, 0.176907",\
+ "0.813025, 0.813025, 0.813025, 0.814982, 0.819773",\
+ "2.192503, 2.192984, 2.194008, 2.200735, 2.216331");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.069370, 0.283193, 0.491815, 0.800919, 1.367462",\
+ "0.075632, 0.304498, 0.517002, 0.813952, 1.385072",\
+ "0.088234, 0.333476, 0.530104, 0.830255, 1.407585",\
+ "0.254611, 0.476253, 0.671078, 0.977854, 1.568006",\
+ "0.593217, 0.801399, 0.995520, 1.304053, 1.898975",\
+ "0.156902, 0.370515, 0.579033, 0.888224, 1.454816",\
+ "0.163435, 0.391863, 0.604283, 0.901257, 1.472425",\
+ "0.176298, 0.420901, 0.617385, 0.917560, 1.494938",\
+ "0.342791, 0.563572, 0.758359, 1.065159, 1.655359",\
+ "0.681370, 0.888717, 1.082801, 1.391358, 1.986328",\
+ "0.243698, 0.458976, 0.666990, 0.968253, 1.534847",\
+ "0.251018, 0.480422, 0.684310, 0.981285, 1.552457",\
+ "0.264645, 0.506852, 0.697412, 0.997588, 1.574970",\
+ "0.431471, 0.643905, 0.838386, 1.145188, 1.735391",\
+ "0.769972, 0.969050, 1.162828, 1.471387, 2.066360",\
+ "0.304960, 0.523854, 0.731112, 1.025689, 1.591878",\
+ "0.313009, 0.545444, 0.742029, 1.038728, 1.609498",\
+ "0.327344, 0.564695, 0.755135, 1.055038, 1.632026",\
+ "0.494481, 0.701749, 0.896119, 1.202653, 1.792478",\
+ "0.832908, 1.026881, 1.220559, 1.528858, 2.123458",\
+ "0.626203, 0.851949, 1.035624, 1.328867, 1.894116",\
+ "0.638895, 0.858887, 1.045689, 1.341910, 1.911750",\
+ "0.657734, 0.870103, 1.058796, 1.358227, 1.934296",\
+ "0.821978, 1.007166, 1.199781, 1.505856, 2.094786",\
+ "1.150367, 1.332198, 1.524221, 1.832065, 2.425780");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.013843, 0.057624, 0.075770, 0.080313, 0.107471",\
+ "0.025205, 0.064739, 0.067587, 0.083073, 0.115488",\
+ "0.053856, 0.083413, 0.086593, 0.102413, 0.134994",\
+ "0.368605, 0.368605, 0.369807, 0.373448, 0.381327",\
+ "1.000406, 1.000406, 1.002130, 1.003829, 1.006481",\
+ "0.014774, 0.057698, 0.075841, 0.080313, 0.107471",\
+ "0.026141, 0.064772, 0.067587, 0.083073, 0.115488",\
+ "0.054523, 0.083449, 0.086593, 0.102413, 0.134994",\
+ "0.368605, 0.368605, 0.369807, 0.373448, 0.381327",\
+ "1.000406, 1.000406, 1.002130, 1.003829, 1.006481",\
+ "0.017481, 0.057867, 0.075842, 0.080313, 0.107471",\
+ "0.028863, 0.064847, 0.067587, 0.083073, 0.115488",\
+ "0.056460, 0.078305, 0.086593, 0.102413, 0.134994",\
+ "0.368605, 0.368605, 0.369807, 0.373448, 0.381327",\
+ "1.000406, 1.000406, 1.002130, 1.003829, 1.006481",\
+ "0.019992, 0.058113, 0.075846, 0.080346, 0.107536",\
+ "0.031388, 0.064955, 0.067602, 0.083112, 0.115566",\
+ "0.058257, 0.078397, 0.086610, 0.102452, 0.135073",\
+ "0.368605, 0.368605, 0.369809, 0.373458, 0.381346",\
+ "1.000406, 1.000406, 1.002134, 1.003832, 1.006488",\
+ "0.035969, 0.049040, 0.064123, 0.080374, 0.107616",\
+ "0.047452, 0.060595, 0.067604, 0.083146, 0.115661",\
+ "0.069690, 0.079044, 0.086613, 0.102486, 0.135168",\
+ "0.368605, 0.368605, 0.369810, 0.373466, 0.381369",\
+ "1.000406, 1.000406, 1.002134, 1.003835, 1.006495");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2285*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[45]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.431291, 0.619330, 0.796158, 1.080125, 1.629897",\
+ "0.450507, 0.638547, 0.815375, 1.099342, 1.649114",\
+ "0.482156, 0.670196, 0.847024, 1.130990, 1.680763",\
+ "0.772737, 0.960778, 1.137606, 1.421573, 1.971346",\
+ "1.366740, 1.554780, 1.731609, 2.015576, 2.565349",\
+ "0.519710, 0.706648, 0.883439, 1.167430, 1.717251",\
+ "0.538927, 0.725865, 0.902656, 1.186647, 1.736468",\
+ "0.570576, 0.757514, 0.934305, 1.218296, 1.768116",\
+ "0.861157, 1.048096, 1.224887, 1.508878, 2.058700",\
+ "1.455159, 1.642098, 1.818890, 2.102881, 2.652703",\
+ "0.609345, 0.786979, 0.963466, 1.247459, 1.797282",\
+ "0.628561, 0.806196, 0.982683, 1.266675, 1.816499",\
+ "0.660210, 0.837845, 1.014332, 1.298324, 1.848148",\
+ "0.950791, 1.128427, 1.304914, 1.588907, 2.138731",\
+ "1.544794, 1.722429, 1.898916, 2.182909, 2.732734",\
+ "0.668670, 0.844800, 1.021158, 1.304875, 1.854273",\
+ "0.687887, 0.864017, 1.040374, 1.324092, 1.873490",\
+ "0.719535, 0.895665, 1.072023, 1.355741, 1.905138",\
+ "1.010116, 1.186247, 1.362605, 1.646324, 2.195722",\
+ "1.604119, 1.780250, 1.956608, 2.240326, 2.789725",\
+ "0.971362, 1.150042, 1.324812, 1.608036, 2.156464",\
+ "0.990578, 1.169258, 1.344029, 1.627252, 2.175681",\
+ "1.022227, 1.200907, 1.375677, 1.658901, 2.207329",\
+ "1.312808, 1.491489, 1.666260, 1.949484, 2.497913",\
+ "1.906811, 2.085492, 2.260262, 2.543486, 3.091916");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\
+ "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\
+ "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\
+ "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\
+ "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\
+ "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\
+ "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\
+ "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\
+ "0.115195, 0.115202, 0.115205, 0.115209, 0.115217",\
+ "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\
+ "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\
+ "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\
+ "2.193374, 2.193372, 2.193371, 2.193370, 2.193367");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.443689, 0.631730, 0.808559, 1.092526, 1.642300",\
+ "0.451495, 0.639537, 0.816365, 1.100333, 1.650107",\
+ "0.464877, 0.652918, 0.829747, 1.113715, 1.663489",\
+ "0.616830, 0.804870, 0.981699, 1.265666, 1.815439",\
+ "0.950269, 1.138309, 1.315137, 1.599104, 2.148877",\
+ "0.532108, 0.719048, 0.895840, 1.179832, 1.729654",\
+ "0.539915, 0.726855, 0.903646, 1.187638, 1.737461",\
+ "0.553297, 0.740236, 0.917028, 1.201020, 1.750842",\
+ "0.705249, 0.892188, 1.068980, 1.352971, 1.902793",\
+ "1.038688, 1.225627, 1.402418, 1.686409, 2.236230",\
+ "0.621743, 0.799379, 0.975867, 1.259860, 1.809685",\
+ "0.629550, 0.807186, 0.983673, 1.267667, 1.817492",\
+ "0.642931, 0.820567, 0.997055, 1.281049, 1.830874",\
+ "0.794884, 0.972519, 1.149006, 1.432999, 1.982824",\
+ "1.128323, 1.305958, 1.482445, 1.766438, 2.316262",\
+ "0.681068, 0.857200, 1.033558, 1.317277, 1.866676",\
+ "0.688875, 0.865006, 1.041365, 1.325083, 1.874483",\
+ "0.702257, 0.878388, 1.054746, 1.338465, 1.887864",\
+ "0.854209, 1.030340, 1.206698, 1.490416, 2.039815",\
+ "1.187648, 1.363779, 1.540136, 1.823854, 2.373252",\
+ "0.983760, 1.162441, 1.337212, 1.620437, 2.168867",\
+ "0.991567, 1.170248, 1.345019, 1.628244, 2.176674",\
+ "1.004948, 1.183630, 1.358401, 1.641625, 2.190056",\
+ "1.156901, 1.335582, 1.510352, 1.793576, 2.342006",\
+ "1.490340, 1.669020, 1.843791, 2.127015, 2.675444");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\
+ "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\
+ "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\
+ "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\
+ "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\
+ "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\
+ "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\
+ "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\
+ "1.002263, 1.002263, 1.002263, 1.002263, 1.002263");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2529*/
+
+} /* end of pin tl_o[7] */
+
+pin("tl_o[6]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.154883 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[6];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[16]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.555603, 0.806076, 1.084885, 1.584808, 2.584653",\
+ "0.589996, 0.840470, 1.119283, 1.619221, 2.619098",\
+ "0.661233, 0.911707, 1.190508, 1.690407, 2.690205",\
+ "0.915400, 1.165873, 1.444750, 1.944912, 2.945236",\
+ "1.840005, 2.090481, 2.369305, 2.869275, 3.869217",\
+ "0.643016, 0.893581, 1.172550, 1.671522, 2.670587",\
+ "0.677409, 0.927975, 1.206949, 1.705936, 2.705032",\
+ "0.748646, 0.999212, 1.278174, 1.777122, 2.776139",\
+ "1.002812, 1.253378, 1.532416, 2.031627, 3.031170",\
+ "1.927417, 2.177986, 2.456970, 2.955990, 3.955151",\
+ "0.723872, 0.982469, 1.260517, 1.759145, 2.757542",\
+ "0.758265, 1.016862, 1.294915, 1.793559, 2.791987",\
+ "0.829503, 1.088099, 1.366140, 1.864744, 2.863094",\
+ "1.083669, 1.342266, 1.620383, 2.119249, 3.118125",\
+ "2.008274, 2.266873, 2.544936, 3.043612, 4.042106",\
+ "0.781752, 1.047969, 1.324661, 1.823058, 2.821051",\
+ "0.816145, 1.082362, 1.359060, 1.857472, 2.855496",\
+ "0.887382, 1.153599, 1.430285, 1.928658, 2.926603",\
+ "1.141549, 1.407765, 1.684527, 2.183163, 3.181634",\
+ "2.066154, 2.332373, 2.609081, 3.107526, 4.105615",\
+ "1.114573, 1.410746, 1.676844, 2.172535, 3.166507",\
+ "1.148966, 1.445139, 1.711242, 2.206949, 3.200952",\
+ "1.220203, 1.516376, 1.782467, 2.278135, 3.272059",\
+ "1.474370, 1.770542, 2.036712, 2.532641, 3.527090",\
+ "2.398975, 2.695150, 2.961264, 3.457003, 4.451071");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\
+ "2.465173, 2.465199, 2.466091, 2.469060, 2.474999",\
+ "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\
+ "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\
+ "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\
+ "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\
+ "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\
+ "2.465173, 2.465200, 2.466101, 2.469060, 2.474999",\
+ "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\
+ "0.083751, 0.083752, 0.083761, 0.083790, 0.083849",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692761, 0.692768, 0.692812, 0.692941, 0.693203",\
+ "2.465173, 2.465210, 2.466131, 2.469072, 2.474999");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.587400, 0.837877, 1.116297, 1.614862, 2.611990",\
+ "0.629152, 0.879628, 1.158099, 1.656840, 2.654322",\
+ "0.689082, 0.939558, 1.218080, 1.716996, 2.714829",\
+ "0.857199, 1.107675, 1.386266, 1.885427, 2.883749",\
+ "1.439229, 1.689714, 1.968424, 2.467974, 3.467073",\
+ "0.674813, 0.925382, 1.203958, 1.701576, 2.697924",\
+ "0.716564, 0.967133, 1.245761, 1.743555, 2.740255",\
+ "0.776495, 1.027063, 1.305742, 1.803711, 2.800763",\
+ "0.944611, 1.195180, 1.473930, 1.972142, 2.969683",\
+ "1.526642, 1.777219, 2.056088, 2.554689, 3.553007",\
+ "0.755670, 1.014269, 1.291924, 1.789199, 2.784879",\
+ "0.797421, 1.056020, 1.333727, 1.831177, 2.827210",\
+ "0.857352, 1.115951, 1.393708, 1.891333, 2.887718",\
+ "1.025468, 1.284067, 1.561896, 2.059765, 3.056638",\
+ "1.607499, 1.866107, 2.144055, 2.642311, 3.639962",\
+ "0.813550, 1.079769, 1.356069, 1.853112, 2.848388",\
+ "0.855301, 1.121520, 1.397871, 1.895091, 2.890719",\
+ "0.915231, 1.181451, 1.457853, 1.955247, 2.951227",\
+ "1.083348, 1.349567, 1.626040, 2.123678, 3.120147",\
+ "1.665379, 1.931606, 2.208199, 2.706225, 3.703471",\
+ "1.146371, 1.442547, 1.708238, 2.202584, 3.193844",\
+ "1.188122, 1.484298, 1.750042, 2.244563, 3.236176",\
+ "1.248053, 1.544228, 1.810025, 2.304720, 3.296683",\
+ "1.416169, 1.712345, 1.978215, 2.473152, 3.465603",\
+ "1.998202, 2.294386, 2.560378, 3.055700, 4.048927");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\
+ "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\
+ "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\
+ "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\
+ "0.045876, 0.045874, 0.045861, 0.045821, 0.045741",\
+ "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\
+ "0.155804, 0.155802, 0.155792, 0.155761, 0.155698",\
+ "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\
+ "1.494119, 1.494120, 1.494128, 1.494150, 1.494195");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2615*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[17]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.674108, 0.912583, 1.208888, 1.707377, 2.704357",\
+ "0.708540, 0.947015, 1.243320, 1.741811, 2.738792",\
+ "0.779534, 1.018009, 1.314315, 1.812807, 2.809791",\
+ "1.033699, 1.272174, 1.568481, 2.066974, 3.063961",\
+ "1.958883, 2.197359, 2.493670, 2.992175, 3.989184",\
+ "0.761549, 1.000192, 1.296551, 1.794093, 2.790291",\
+ "0.795981, 1.034624, 1.330983, 1.828526, 2.824726",\
+ "0.866976, 1.105618, 1.401978, 1.899523, 2.895725",\
+ "1.121141, 1.359783, 1.656144, 2.153690, 3.149894",\
+ "2.046324, 2.284967, 2.581333, 3.078891, 4.075118",\
+ "0.842432, 1.089339, 1.384517, 1.881716, 2.877246",\
+ "0.876864, 1.123771, 1.418950, 1.916149, 2.911681",\
+ "0.947859, 1.194765, 1.489945, 1.987146, 2.982680",\
+ "1.202024, 1.448930, 1.744111, 2.241313, 3.236850",\
+ "2.127208, 2.374115, 2.669300, 3.166513, 4.162073",\
+ "0.900159, 1.155216, 1.448662, 1.945630, 2.940755",\
+ "0.934591, 1.189648, 1.483094, 1.980063, 2.975190",\
+ "1.005585, 1.260643, 1.554090, 2.051059, 3.046189",\
+ "1.259750, 1.514808, 1.808255, 2.305226, 3.300359",\
+ "2.184934, 2.439992, 2.733444, 3.230427, 4.225582",\
+ "1.202901, 1.522357, 1.800832, 2.295105, 3.286211",\
+ "1.237333, 1.556789, 1.835264, 2.329538, 3.320646",\
+ "1.308327, 1.627784, 1.906260, 2.400534, 3.391645",\
+ "1.562492, 1.881949, 2.160425, 2.654701, 3.645814",\
+ "2.487676, 2.807133, 3.085615, 3.579902, 4.571038");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\
+ "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\
+ "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\
+ "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\
+ "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\
+ "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\
+ "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\
+ "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\
+ "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\
+ "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\
+ "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\
+ "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\
+ "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\
+ "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\
+ "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\
+ "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\
+ "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\
+ "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\
+ "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\
+ "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\
+ "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\
+ "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\
+ "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\
+ "0.693279, 0.693283, 0.693285, 0.693285, 0.693285",\
+ "2.470759, 2.470762, 2.470771, 2.470795, 2.470844");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.701144, 0.939619, 1.235924, 1.734413, 2.731392",\
+ "0.743441, 0.981916, 1.278220, 1.776710, 2.773689",\
+ "0.804003, 1.042478, 1.338783, 1.837273, 2.834251",\
+ "0.972934, 1.211409, 1.507714, 2.006203, 3.003182",\
+ "1.556185, 1.794660, 2.090965, 2.589454, 3.586433",\
+ "0.788586, 1.027228, 1.323587, 1.821129, 2.817326",\
+ "0.830882, 1.069525, 1.365883, 1.863425, 2.859622",\
+ "0.891445, 1.130087, 1.426446, 1.923988, 2.920185",\
+ "1.060375, 1.299018, 1.595377, 2.092919, 3.089116",\
+ "1.643626, 1.882269, 2.178628, 2.676170, 3.672367",\
+ "0.869469, 1.116375, 1.411554, 1.908752, 2.904281",\
+ "0.911765, 1.158672, 1.453850, 1.951048, 2.946578",\
+ "0.972328, 1.219234, 1.514413, 2.011611, 3.007140",\
+ "1.141259, 1.388165, 1.683344, 2.180542, 3.176071",\
+ "1.724510, 1.971416, 2.266594, 2.763793, 3.759322",\
+ "0.927195, 1.182252, 1.475698, 1.972666, 2.967790",\
+ "0.969492, 1.224549, 1.517995, 2.014962, 3.010087",\
+ "1.030054, 1.285111, 1.578557, 2.075525, 3.070649",\
+ "1.198985, 1.454042, 1.747488, 2.244456, 3.239580",\
+ "1.782236, 2.037293, 2.330739, 2.827706, 3.822831",\
+ "1.229937, 1.549393, 1.827868, 2.322140, 3.313246",\
+ "1.272233, 1.591690, 1.870165, 2.364437, 3.355543",\
+ "1.332796, 1.652252, 1.930727, 2.424999, 3.416105",\
+ "1.501727, 1.821183, 2.099658, 2.593930, 3.585036",\
+ "2.084978, 2.404434, 2.682909, 3.177181, 4.168287");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\
+ "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\
+ "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\
+ "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\
+ "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498063, 1.498063, 1.498063, 1.498062");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2662*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[19]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.445529, 0.709512, 0.994214, 1.487610, 2.474404",\
+ "0.486774, 0.750744, 1.035473, 1.529006, 2.516072",\
+ "0.562671, 0.826637, 1.111362, 1.604919, 2.592032",\
+ "0.817960, 1.082041, 1.366717, 1.860078, 2.846800",\
+ "1.742890, 2.007130, 2.292228, 2.786041, 3.773666",\
+ "0.532938, 0.797075, 1.081856, 1.574325, 2.560338",\
+ "0.574183, 0.838307, 1.123116, 1.615720, 2.602005",\
+ "0.650079, 0.914199, 1.199006, 1.691633, 2.677966",\
+ "0.905369, 1.169603, 1.454359, 1.946792, 2.932734",\
+ "1.830298, 2.094694, 2.379872, 2.872755, 3.859600",\
+ "0.616182, 0.886074, 1.169821, 1.661946, 2.647293",\
+ "0.657426, 0.927306, 1.211081, 1.703342, 2.688961",\
+ "0.733323, 1.003198, 1.286970, 1.779255, 2.764921",\
+ "0.988623, 1.258602, 1.542324, 2.034413, 3.019689",\
+ "1.913549, 2.183697, 2.467836, 2.960376, 3.946555",\
+ "0.679766, 0.951735, 1.233965, 1.725859, 2.710802",\
+ "0.721010, 0.992966, 1.275225, 1.767255, 2.752470",\
+ "0.796907, 1.068859, 1.351114, 1.843168, 2.828430",\
+ "1.052215, 1.324263, 1.606468, 2.098326, 3.083198",\
+ "1.977138, 2.249364, 2.531980, 3.024289, 4.010064",\
+ "1.015779, 1.316457, 1.586079, 2.075305, 3.056258",\
+ "1.057021, 1.357686, 1.627340, 2.116701, 3.097925",\
+ "1.132920, 1.433575, 1.703230, 2.192614, 3.173886",\
+ "1.388277, 1.688981, 1.958581, 2.447772, 3.428654",\
+ "2.313181, 2.614154, 2.884099, 3.373737, 4.355520");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.034901, 0.034921, 0.035051, 0.035499, 0.036393",\
+ "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\
+ "0.208547, 0.208578, 0.208621, 0.208624, 0.208631",\
+ "0.692555, 0.692580, 0.692833, 0.693579, 0.695072",\
+ "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\
+ "0.034901, 0.034921, 0.035053, 0.035499, 0.036393",\
+ "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\
+ "0.208547, 0.208579, 0.208621, 0.208624, 0.208631",\
+ "0.692555, 0.692580, 0.692835, 0.693579, 0.695072",\
+ "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\
+ "0.034903, 0.034921, 0.035053, 0.035499, 0.036393",\
+ "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\
+ "0.208547, 0.208579, 0.208621, 0.208624, 0.208631",\
+ "0.692555, 0.692581, 0.692835, 0.693579, 0.695072",\
+ "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\
+ "0.034905, 0.034921, 0.035053, 0.035499, 0.036393",\
+ "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\
+ "0.208547, 0.208580, 0.208621, 0.208624, 0.208631",\
+ "0.692555, 0.692581, 0.692835, 0.693579, 0.695072",\
+ "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\
+ "0.034914, 0.034921, 0.035057, 0.035500, 0.036393",\
+ "0.083289, 0.083291, 0.083339, 0.083496, 0.083813",\
+ "0.208549, 0.208590, 0.208621, 0.208624, 0.208631",\
+ "0.692555, 0.692590, 0.692843, 0.693582, 0.695072",\
+ "2.479533, 2.479533, 2.479533, 2.479533, 2.479533");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.491807, 0.755750, 1.040134, 1.532324, 2.516704",\
+ "0.532692, 0.796638, 1.081002, 1.573128, 2.557379",\
+ "0.593088, 0.857084, 1.141423, 1.633441, 2.617476",\
+ "0.762034, 1.026038, 1.310351, 1.802328, 2.786283",\
+ "1.345402, 1.609523, 1.893616, 2.385030, 3.367858",\
+ "0.579215, 0.843313, 1.127773, 1.619038, 2.602638",\
+ "0.620100, 0.884201, 1.168641, 1.659842, 2.643312",\
+ "0.680497, 0.944646, 1.229061, 1.720155, 2.703410",\
+ "0.849443, 1.113601, 1.397989, 1.889042, 2.872216",\
+ "1.432811, 1.697085, 1.981253, 2.471745, 3.453792",\
+ "0.662453, 0.932313, 1.215738, 1.706660, 2.689593",\
+ "0.703338, 0.973200, 1.256606, 1.747463, 2.730268",\
+ "0.763739, 1.033646, 1.317026, 1.807776, 2.790365",\
+ "0.932687, 1.202600, 1.485954, 1.976664, 2.959171",\
+ "1.516071, 1.786084, 2.069218, 2.559366, 3.540747",\
+ "0.726033, 0.997974, 1.279881, 1.770573, 2.753102",\
+ "0.766918, 1.038862, 1.320749, 1.811376, 2.793777",\
+ "0.827322, 1.099308, 1.381169, 1.871690, 2.853874",\
+ "0.996272, 1.268262, 1.550097, 2.040577, 3.022680",\
+ "1.579666, 1.851744, 2.133361, 2.623279, 3.604256",\
+ "1.062019, 1.362705, 1.631983, 2.120014, 3.098558",\
+ "1.102906, 1.403592, 1.672850, 2.160817, 3.139233",\
+ "1.163330, 1.464039, 1.733269, 2.221130, 3.199330",\
+ "1.332287, 1.632990, 1.902197, 2.390017, 3.368136",\
+ "1.915751, 2.216458, 2.485455, 2.972717, 3.949712");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\
+ "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\
+ "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\
+ "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\
+ "1.494840, 1.494148, 1.493909, 1.493909, 1.493909",\
+ "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\
+ "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\
+ "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\
+ "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\
+ "1.494840, 1.494147, 1.493909, 1.493909, 1.493909",\
+ "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\
+ "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\
+ "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\
+ "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\
+ "1.494787, 1.494143, 1.493909, 1.493909, 1.493909",\
+ "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\
+ "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\
+ "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\
+ "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\
+ "1.494750, 1.494138, 1.493909, 1.493909, 1.493909",\
+ "0.042675, 0.042675, 0.042651, 0.042574, 0.042419",\
+ "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\
+ "0.155291, 0.155291, 0.155276, 0.155229, 0.155132",\
+ "0.431055, 0.431055, 0.431009, 0.430858, 0.430555",\
+ "1.494514, 1.494079, 1.493909, 1.493909, 1.493909");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2660*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[20]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.327672, 0.566275, 0.848132, 1.348276, 2.348564",\
+ "0.368967, 0.607415, 0.888608, 1.386404, 2.381997",\
+ "0.444897, 0.683231, 0.964015, 1.460342, 2.452995",\
+ "0.700493, 0.938416, 1.218620, 1.714868, 2.707363",\
+ "1.624950, 1.862182, 2.144032, 2.639823, 3.631406",\
+ "0.415085, 0.653799, 0.935798, 1.434991, 2.434498",\
+ "0.456380, 0.694939, 0.976266, 1.473119, 2.467931",\
+ "0.532309, 0.770755, 1.051669, 1.547057, 2.538929",\
+ "0.787906, 1.025936, 1.306274, 1.801582, 2.793297",\
+ "1.712363, 1.949714, 2.231684, 2.726538, 3.717340",\
+ "0.495952, 0.742730, 1.023765, 1.522613, 2.521453",\
+ "0.537247, 0.783870, 1.064233, 1.560741, 2.554886",\
+ "0.613176, 0.859686, 1.139635, 1.634679, 2.625884",\
+ "0.868772, 1.114859, 1.394240, 1.889205, 2.880252",\
+ "1.793228, 2.038663, 2.319650, 2.814160, 3.804295",\
+ "0.553602, 0.808292, 1.087909, 1.586527, 2.584962",\
+ "0.594896, 0.849433, 1.128377, 1.624655, 2.618395",\
+ "0.670825, 0.925249, 1.203779, 1.698593, 2.689393",\
+ "0.926420, 1.180411, 1.458384, 1.953118, 2.943761",\
+ "1.850875, 2.104251, 2.383794, 2.878074, 3.867804",\
+ "0.871915, 1.171803, 1.440094, 1.936005, 2.930418",\
+ "0.913062, 1.212946, 1.480538, 1.974123, 2.963851",\
+ "0.988827, 1.288766, 1.555925, 2.048055, 3.034849",\
+ "1.244293, 1.543790, 1.810529, 2.302580, 3.289217",\
+ "2.167832, 2.468068, 2.735935, 3.227534, 4.213260");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.035017, 0.035017, 0.035948, 0.039191, 0.045676",\
+ "0.083549, 0.083549, 0.083882, 0.085042, 0.087361",\
+ "0.208718, 0.208718, 0.208873, 0.209414, 0.210496",\
+ "0.692609, 0.692819, 0.692927, 0.693071, 0.693361",\
+ "2.477031, 2.477031, 2.477147, 2.477551, 2.478359",\
+ "0.035017, 0.035017, 0.035958, 0.039191, 0.045676",\
+ "0.083549, 0.083549, 0.083886, 0.085042, 0.087361",\
+ "0.208718, 0.208718, 0.208875, 0.209414, 0.210496",\
+ "0.692609, 0.692819, 0.692927, 0.693071, 0.693361",\
+ "2.477031, 2.477031, 2.477149, 2.477551, 2.478359",\
+ "0.035017, 0.035017, 0.035958, 0.039191, 0.045676",\
+ "0.083549, 0.083549, 0.083886, 0.085042, 0.087361",\
+ "0.208718, 0.208718, 0.208875, 0.209414, 0.210496",\
+ "0.692610, 0.692820, 0.692927, 0.693071, 0.693361",\
+ "2.477031, 2.477031, 2.477149, 2.477551, 2.478359",\
+ "0.035017, 0.035017, 0.035959, 0.039191, 0.045676",\
+ "0.083549, 0.083549, 0.083886, 0.085042, 0.087361",\
+ "0.208718, 0.208718, 0.208875, 0.209414, 0.210496",\
+ "0.692612, 0.692821, 0.692927, 0.693071, 0.693361",\
+ "2.477031, 2.477031, 2.477149, 2.477551, 2.478359",\
+ "0.035017, 0.035017, 0.035992, 0.039204, 0.045676",\
+ "0.083549, 0.083549, 0.083898, 0.085047, 0.087361",\
+ "0.208718, 0.208718, 0.208880, 0.209416, 0.210496",\
+ "0.692710, 0.692838, 0.692928, 0.693072, 0.693361",\
+ "2.477031, 2.477031, 2.477153, 2.477553, 2.478359");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.374541, 0.613195, 0.891051, 1.377355, 2.349964",\
+ "0.415440, 0.654096, 0.931703, 1.416730, 2.386785",\
+ "0.475586, 0.714339, 0.991271, 1.473856, 2.439025",\
+ "0.644564, 0.883292, 1.159558, 1.639742, 2.600112",\
+ "1.227810, 1.464706, 1.741320, 2.221670, 3.182369",\
+ "0.461954, 0.700719, 0.978673, 1.464070, 2.435898",\
+ "0.502853, 0.741620, 1.019321, 1.503445, 2.472719",\
+ "0.562998, 0.801863, 1.078882, 1.560571, 2.524959",\
+ "0.731977, 0.970816, 1.247161, 1.726457, 2.686046",\
+ "1.315223, 1.552233, 1.828923, 2.308385, 3.268303",\
+ "0.542824, 0.789649, 1.066638, 1.551692, 2.522853",\
+ "0.583722, 0.830553, 1.107287, 1.591067, 2.559674",\
+ "0.643867, 0.890796, 1.166847, 1.648193, 2.611914",\
+ "0.812844, 1.059749, 1.335126, 1.814080, 2.773001",\
+ "1.396076, 1.641170, 1.916889, 2.396007, 3.355258",\
+ "0.600479, 0.855211, 1.130781, 1.615606, 2.586362",\
+ "0.641375, 0.896117, 1.171429, 1.654981, 2.623183",\
+ "0.701520, 0.956361, 1.230989, 1.712107, 2.675423",\
+ "0.870493, 1.125315, 1.399267, 1.877993, 2.836510",\
+ "1.453700, 1.706742, 1.981030, 2.459920, 3.418767",\
+ "0.918806, 1.218716, 1.482825, 1.965026, 2.931818",\
+ "0.959736, 1.259650, 1.523460, 2.004396, 2.968639",\
+ "1.019894, 1.319901, 1.582996, 2.061512, 3.020879",\
+ "1.188870, 1.488860, 1.751250, 2.227388, 3.181966",\
+ "1.770179, 2.070362, 2.333014, 2.809316, 3.764223");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.042685, 0.042786, 0.042938, 0.042938, 0.042938",\
+ "0.078477, 0.079297, 0.079365, 0.079365, 0.079365",\
+ "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\
+ "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\
+ "0.042685, 0.042787, 0.042938, 0.042938, 0.042938",\
+ "0.078477, 0.079298, 0.079365, 0.079365, 0.079365",\
+ "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\
+ "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\
+ "0.042685, 0.042789, 0.042938, 0.042938, 0.042938",\
+ "0.078482, 0.079299, 0.079365, 0.079365, 0.079365",\
+ "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\
+ "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\
+ "0.042685, 0.042792, 0.042938, 0.042938, 0.042938",\
+ "0.078491, 0.079300, 0.079365, 0.079365, 0.079365",\
+ "0.155271, 0.155314, 0.155322, 0.155322, 0.155322",\
+ "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\
+ "0.042685, 0.042830, 0.042938, 0.042938, 0.042938",\
+ "0.078951, 0.079317, 0.079365, 0.079365, 0.079365",\
+ "0.155294, 0.155316, 0.155322, 0.155322, 0.155322",\
+ "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\
+ "1.494069, 1.494069, 1.494069, 1.494069, 1.494069");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2717*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[21]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.430110, 0.674363, 0.945987, 1.398684, 2.304079",\
+ "0.471359, 0.715604, 0.987211, 1.439891, 2.345252",\
+ "0.547252, 0.791500, 1.063102, 1.515754, 2.421058",\
+ "0.802426, 1.046828, 1.318547, 1.770909, 2.675633",\
+ "1.727400, 1.971804, 2.243712, 2.696691, 3.602648",\
+ "0.517512, 0.761931, 1.033499, 1.485397, 2.390012",\
+ "0.558762, 0.803171, 1.074723, 1.526605, 2.431185",\
+ "0.634655, 0.879067, 1.150614, 1.602467, 2.506991",\
+ "0.889829, 1.134397, 1.406058, 1.857622, 2.761567",\
+ "1.814803, 2.059373, 2.331226, 2.783404, 3.688582",\
+ "0.598336, 0.850913, 1.121461, 1.573018, 2.476967",\
+ "0.639585, 0.892153, 1.162685, 1.614225, 2.518140",\
+ "0.715478, 0.968049, 1.238575, 1.690088, 2.593946",\
+ "0.970652, 1.223382, 1.494019, 1.945243, 2.848522",\
+ "1.895626, 2.148358, 2.419187, 2.871025, 3.775537",\
+ "0.655998, 0.916548, 1.185597, 1.636931, 2.540476",\
+ "0.697247, 0.957788, 1.226822, 1.678138, 2.581649",\
+ "0.773140, 1.033684, 1.302712, 1.754000, 2.657455",\
+ "1.028314, 1.289021, 1.558156, 2.009156, 2.912031",\
+ "1.953288, 2.213997, 2.483324, 2.934937, 3.839046",\
+ "0.986976, 1.281046, 1.537295, 1.986203, 2.885932",\
+ "1.028225, 1.322284, 1.578519, 2.027411, 2.927105",\
+ "1.104119, 1.398180, 1.654409, 2.103273, 3.002912",\
+ "1.359298, 1.653568, 1.909851, 2.358427, 3.257487",\
+ "2.284269, 2.578546, 2.835025, 3.284211, 4.184502");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.034880, 0.034905, 0.035033, 0.035354, 0.035995",\
+ "0.083283, 0.083287, 0.083329, 0.083448, 0.083687",\
+ "0.208545, 0.208582, 0.208618, 0.208622, 0.208628",\
+ "0.692606, 0.692606, 0.692841, 0.693640, 0.695237",\
+ "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\
+ "0.034880, 0.034906, 0.035034, 0.035354, 0.035995",\
+ "0.083283, 0.083287, 0.083329, 0.083448, 0.083687",\
+ "0.208545, 0.208582, 0.208618, 0.208622, 0.208628",\
+ "0.692606, 0.692606, 0.692844, 0.693640, 0.695237",\
+ "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\
+ "0.034880, 0.034906, 0.035034, 0.035354, 0.035995",\
+ "0.083283, 0.083288, 0.083329, 0.083448, 0.083687",\
+ "0.208545, 0.208582, 0.208618, 0.208622, 0.208628",\
+ "0.692606, 0.692606, 0.692844, 0.693640, 0.695237",\
+ "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\
+ "0.034880, 0.034907, 0.035034, 0.035354, 0.035995",\
+ "0.083283, 0.083288, 0.083329, 0.083448, 0.083687",\
+ "0.208546, 0.208583, 0.208618, 0.208622, 0.208628",\
+ "0.692606, 0.692606, 0.692844, 0.693640, 0.695237",\
+ "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\
+ "0.034881, 0.034915, 0.035037, 0.035355, 0.035995",\
+ "0.083283, 0.083289, 0.083330, 0.083449, 0.083687",\
+ "0.208552, 0.208592, 0.208618, 0.208622, 0.208628",\
+ "0.692606, 0.692606, 0.692852, 0.693643, 0.695237",\
+ "2.479823, 2.479823, 2.479823, 2.479823, 2.479823");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.476452, 0.720627, 0.992222, 1.445174, 2.351079",\
+ "0.517334, 0.761513, 1.033104, 1.486024, 2.391864",\
+ "0.577683, 0.821926, 1.093569, 1.546380, 2.452001",\
+ "0.746610, 0.990875, 1.262519, 1.715235, 2.620666",\
+ "1.329814, 1.574285, 1.846012, 2.298098, 3.202269",\
+ "0.563855, 0.808193, 1.079735, 1.531888, 2.437013",\
+ "0.604736, 0.849079, 1.120617, 1.572738, 2.477798",\
+ "0.665086, 0.909493, 1.181081, 1.633093, 2.537935",\
+ "0.834013, 1.078442, 1.350031, 1.801948, 2.706600",\
+ "1.417216, 1.661854, 1.933522, 2.384811, 3.288203",\
+ "0.644678, 0.897174, 1.167696, 1.619509, 2.523968",\
+ "0.685559, 0.938060, 1.208579, 1.660358, 2.564753",\
+ "0.745909, 0.998475, 1.269043, 1.720713, 2.624890",\
+ "0.914836, 1.167425, 1.437993, 1.889569, 2.793555",\
+ "1.498040, 1.750840, 2.021483, 2.472431, 3.375158",\
+ "0.702340, 0.962807, 1.231833, 1.683421, 2.587477",\
+ "0.743221, 1.003693, 1.272716, 1.724271, 2.628262",\
+ "0.803571, 1.064109, 1.333179, 1.784626, 2.688399",\
+ "0.972498, 1.233060, 1.502129, 1.953481, 2.857064",\
+ "1.555702, 1.816481, 2.085620, 2.536344, 3.438667",\
+ "1.033316, 1.327279, 1.583534, 2.032695, 2.932933",\
+ "1.074197, 1.368167, 1.624416, 2.073545, 2.973718",\
+ "1.134549, 1.428604, 1.684879, 2.133899, 3.033855",\
+ "1.303477, 1.597562, 1.853827, 2.302754, 3.202520",\
+ "1.886688, 2.181050, 2.437312, 2.885614, 3.784123");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\
+ "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\
+ "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\
+ "0.431084, 0.431084, 0.431042, 0.430897, 0.430607",\
+ "1.495395, 1.494888, 1.494241, 1.494241, 1.494241",\
+ "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\
+ "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\
+ "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\
+ "0.431084, 0.431084, 0.431041, 0.430897, 0.430607",\
+ "1.495395, 1.494883, 1.494241, 1.494241, 1.494241",\
+ "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\
+ "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\
+ "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\
+ "0.431084, 0.431084, 0.431041, 0.430897, 0.430607",\
+ "1.495394, 1.494874, 1.494241, 1.494241, 1.494241",\
+ "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\
+ "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\
+ "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\
+ "0.431084, 0.431084, 0.431041, 0.430897, 0.430607",\
+ "1.495394, 1.494860, 1.494241, 1.494241, 1.494241",\
+ "0.042687, 0.042687, 0.042668, 0.042607, 0.042485",\
+ "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\
+ "0.155296, 0.155296, 0.155280, 0.155231, 0.155132",\
+ "0.431084, 0.431084, 0.431040, 0.430896, 0.430607",\
+ "1.495370, 1.494698, 1.494241, 1.494241, 1.494241");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[25]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.554256, 0.796472, 1.062238, 1.540435, 2.496829",\
+ "0.588688, 0.830904, 1.096670, 1.574875, 2.531283",\
+ "0.659682, 0.901899, 1.167669, 1.645892, 2.602338",\
+ "0.913848, 1.156064, 1.421858, 1.900173, 2.856801",\
+ "1.839032, 2.081247, 2.347044, 2.825424, 3.782184",\
+ "0.641661, 0.883946, 1.149831, 1.627148, 2.582762",\
+ "0.676093, 0.918377, 1.184264, 1.661588, 2.617217",\
+ "0.747088, 0.989372, 1.255262, 1.732605, 2.688272",\
+ "1.001253, 1.243537, 1.509452, 1.986886, 2.942735",\
+ "1.926437, 2.168720, 2.434638, 2.912138, 3.868118",\
+ "0.722474, 0.972733, 1.237795, 1.714769, 2.669717",\
+ "0.756906, 1.007164, 1.272227, 1.749209, 2.704172",\
+ "0.827901, 1.078159, 1.343225, 1.820227, 2.775227",\
+ "1.082066, 1.332324, 1.597415, 2.074507, 3.029690",\
+ "2.007250, 2.257506, 2.522601, 2.999759, 3.955073",\
+ "0.781555, 1.038084, 1.301936, 1.778682, 2.733226",\
+ "0.815987, 1.072516, 1.336368, 1.813122, 2.767681",\
+ "0.886982, 1.143511, 1.407367, 1.884140, 2.838736",\
+ "1.141147, 1.397675, 1.661557, 2.138420, 3.093199",\
+ "2.066333, 2.322857, 2.586742, 3.063672, 4.018582",\
+ "1.117315, 1.399225, 1.653894, 2.128062, 3.078682",\
+ "1.151748, 1.433656, 1.688326, 2.162502, 3.113137",\
+ "1.222743, 1.504651, 1.759325, 2.233520, 3.184192",\
+ "1.476909, 1.758815, 2.013515, 2.487801, 3.438655",\
+ "2.402100, 2.683993, 2.938702, 3.413052, 4.364038");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.034240, 0.034243, 0.034261, 0.034303, 0.034388",\
+ "0.083583, 0.083591, 0.083624, 0.083701, 0.083855",\
+ "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470761, 2.470782, 2.471502, 2.473964, 2.478889",\
+ "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\
+ "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\
+ "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470761, 2.470782, 2.471510, 2.473964, 2.478889",\
+ "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\
+ "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\
+ "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470761, 2.470782, 2.471510, 2.473964, 2.478889",\
+ "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\
+ "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\
+ "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470764, 2.470782, 2.471510, 2.473964, 2.478889",\
+ "0.034240, 0.034245, 0.034262, 0.034304, 0.034388",\
+ "0.083583, 0.083594, 0.083625, 0.083701, 0.083855",\
+ "0.208066, 0.208075, 0.208100, 0.208159, 0.208278",\
+ "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\
+ "2.470774, 2.470782, 2.471535, 2.473975, 2.478889");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.581292, 0.823509, 1.089276, 1.567480, 2.523887",\
+ "0.623589, 0.865805, 1.131530, 1.609589, 2.565706",\
+ "0.684151, 0.926368, 1.192030, 1.669873, 2.625559",\
+ "0.853082, 1.095299, 1.360884, 1.838464, 2.793625",\
+ "1.436333, 1.678550, 1.944122, 2.421657, 3.376727",\
+ "0.668697, 0.910982, 1.176870, 1.654194, 2.609821",\
+ "0.710994, 0.953278, 1.219123, 1.696303, 2.651640",\
+ "0.771556, 1.013841, 1.279622, 1.756587, 2.711493",\
+ "0.940487, 1.182772, 1.448475, 1.925178, 2.879559",\
+ "1.523738, 1.766023, 2.031713, 2.508370, 3.462660",\
+ "0.749510, 0.999769, 1.264833, 1.741815, 2.696776",\
+ "0.791807, 1.042065, 1.307087, 1.783924, 2.738595",\
+ "0.852369, 1.102628, 1.367586, 1.844208, 2.798448",\
+ "1.021300, 1.271559, 1.536439, 2.012799, 2.966514",\
+ "1.604551, 1.854810, 2.119677, 2.595992, 3.549615",\
+ "0.808591, 1.065121, 1.328974, 1.805728, 2.760285",\
+ "0.850888, 1.107417, 1.371228, 1.847837, 2.802104",\
+ "0.911450, 1.167980, 1.431727, 1.908121, 2.861957",\
+ "1.080381, 1.336911, 1.600580, 2.076712, 3.030023",\
+ "1.663632, 1.920162, 2.183818, 2.659904, 3.613124",\
+ "1.144351, 1.426262, 1.680932, 2.155108, 3.105741",\
+ "1.186648, 1.468558, 1.723184, 2.197216, 3.147560",\
+ "1.247211, 1.529121, 1.783681, 2.257499, 3.207412",\
+ "1.416141, 1.698051, 1.952531, 2.426090, 3.375479",\
+ "1.999392, 2.281302, 2.535769, 3.009282, 3.958580");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\
+ "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\
+ "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\
+ "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\
+ "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\
+ "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\
+ "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\
+ "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\
+ "0.045859, 0.045859, 0.045871, 0.045908, 0.045983",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498064, 1.498064, 1.498064, 1.498064, 1.498064");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2473*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[28]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.778393, 1.030571, 1.315131, 1.821345, 2.833774",\
+ "0.812784, 1.064961, 1.349521, 1.855736, 2.868164",\
+ "0.884026, 1.136204, 1.420765, 1.926979, 2.939408",\
+ "1.138193, 1.390371, 1.674931, 2.181146, 3.193574",\
+ "2.062764, 2.314940, 2.599499, 3.105713, 4.118140",\
+ "0.865806, 1.118101, 1.402816, 1.908060, 2.919708",\
+ "0.900196, 1.152491, 1.437207, 1.942451, 2.954098",\
+ "0.971439, 1.223734, 1.508450, 2.013694, 3.025342",\
+ "1.225605, 1.477901, 1.762616, 2.267860, 3.279508",\
+ "2.150177, 2.402470, 2.687184, 3.192428, 4.204074",\
+ "0.946677, 1.207046, 1.490783, 1.995683, 3.006663",\
+ "0.981067, 1.241436, 1.525173, 2.030073, 3.041053",\
+ "1.052310, 1.312679, 1.596416, 2.101316, 3.112297",\
+ "1.306477, 1.566845, 1.850583, 2.355483, 3.366463",\
+ "2.231048, 2.491415, 2.775151, 3.280050, 4.291029",\
+ "1.005325, 1.272628, 1.554929, 2.059596, 3.070172",\
+ "1.039716, 1.307018, 1.589319, 2.093987, 3.104562",\
+ "1.110958, 1.378261, 1.660562, 2.165230, 3.175806",\
+ "1.365125, 1.632428, 1.914729, 2.419396, 3.429972",\
+ "2.289696, 2.556998, 2.839297, 3.343963, 4.354538",\
+ "1.337288, 1.636376, 1.907175, 2.409100, 3.415628",\
+ "1.371678, 1.670766, 1.941566, 2.443490, 3.450018",\
+ "1.442921, 1.742009, 2.012809, 2.514733, 3.521262",\
+ "1.697088, 1.996176, 2.266975, 2.768899, 3.775428",\
+ "2.621658, 2.920745, 3.191543, 3.693467, 4.699994");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\
+ "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\
+ "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\
+ "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\
+ "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\
+ "2.464329, 2.464329, 2.464329, 2.464329, 2.464329");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.810153, 1.062330, 1.346888, 1.853102, 2.865529",\
+ "0.851906, 1.104082, 1.388641, 1.894854, 2.907281",\
+ "0.911836, 1.164013, 1.448571, 1.954785, 2.967211",\
+ "1.079953, 1.332130, 1.616688, 2.122902, 3.135329",\
+ "1.661862, 1.914034, 2.198587, 2.704797, 3.717218",\
+ "0.897566, 1.149860, 1.434573, 1.939816, 2.951462",\
+ "0.939318, 1.191612, 1.476326, 1.981569, 2.993215",\
+ "0.999249, 1.251543, 1.536256, 2.041499, 3.053145",\
+ "1.167366, 1.419660, 1.704374, 2.209617, 3.221262",\
+ "1.749275, 2.001564, 2.286272, 2.791512, 3.803152",\
+ "0.978437, 1.238804, 1.522540, 2.027439, 3.038417",\
+ "1.020190, 1.280557, 1.564292, 2.069191, 3.080170",\
+ "1.080120, 1.340487, 1.624223, 2.129122, 3.140100",\
+ "1.248237, 1.508604, 1.792340, 2.297239, 3.308218",\
+ "1.830146, 2.090508, 2.374238, 2.879134, 3.890107",\
+ "1.037085, 1.304387, 1.586686, 2.091352, 3.101926",\
+ "1.078838, 1.346139, 1.628438, 2.133105, 3.143679",\
+ "1.138768, 1.406070, 1.688369, 2.193035, 3.203609",\
+ "1.306885, 1.574187, 1.856486, 2.361152, 3.371727",\
+ "1.888794, 2.156091, 2.438385, 2.943048, 3.953616",\
+ "1.369048, 1.668134, 1.938932, 2.440856, 3.447382",\
+ "1.410800, 1.709887, 1.980685, 2.482608, 3.489135",\
+ "1.470731, 1.769817, 2.040615, 2.542538, 3.549065",\
+ "1.638848, 1.937934, 2.208732, 2.710656, 3.717183",\
+ "2.220756, 2.519837, 2.790631, 3.292551, 4.299072");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\
+ "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494120");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2603*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[29]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.769218, 1.013990, 1.288183, 1.753076, 2.682863",\
+ "0.803608, 1.048380, 1.322573, 1.787467, 2.717253",\
+ "0.874851, 1.119623, 1.393816, 1.858710, 2.788497",\
+ "1.129017, 1.373789, 1.647983, 2.112876, 3.042663",\
+ "2.053588, 2.298358, 2.572550, 3.037443, 3.967230",\
+ "0.856623, 1.101544, 1.375734, 1.839790, 2.768797",\
+ "0.891013, 1.135935, 1.410125, 1.874180, 2.803187",\
+ "0.962256, 1.207178, 1.481368, 1.945424, 2.874431",\
+ "1.216422, 1.461344, 1.735534, 2.199590, 3.128597",\
+ "2.140993, 2.385913, 2.660101, 3.124157, 4.053164",\
+ "0.937445, 1.190511, 1.463697, 1.927411, 2.855752",\
+ "0.971835, 1.224902, 1.498087, 1.961801, 2.890142",\
+ "1.043078, 1.296145, 1.569331, 2.033045, 2.961386",\
+ "1.297244, 1.550311, 1.823497, 2.287211, 3.215552",\
+ "2.221816, 2.474880, 2.748064, 3.211778, 4.140119",\
+ "0.995080, 1.256125, 1.527836, 1.991324, 2.919261",\
+ "1.029471, 1.290515, 1.562226, 2.025714, 2.953651",\
+ "1.100714, 1.361758, 1.633469, 2.096957, 3.024895",\
+ "1.354880, 1.615925, 1.887636, 2.351124, 3.279061",\
+ "2.279451, 2.540493, 2.812203, 3.275691, 4.203628",\
+ "1.324766, 1.620334, 1.879659, 2.340649, 3.264717",\
+ "1.359156, 1.654725, 1.914049, 2.375039, 3.299107",\
+ "1.430399, 1.725968, 1.985292, 2.446283, 3.370351",\
+ "1.684566, 1.980134, 2.239459, 2.700449, 3.624517",\
+ "2.609136, 2.904703, 3.164026, 3.625016, 4.549084");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\
+ "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\
+ "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\
+ "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\
+ "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\
+ "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\
+ "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\
+ "2.464326, 2.464326, 2.464326, 2.464326, 2.464326");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.800978, 1.045748, 1.319939, 1.784832, 2.714618",\
+ "0.842730, 1.087500, 1.361691, 1.826584, 2.756371",\
+ "0.902660, 1.147430, 1.421622, 1.886515, 2.816301",\
+ "1.070778, 1.315548, 1.589739, 2.054632, 2.984419",\
+ "1.652686, 1.897449, 2.171633, 2.636526, 3.566311",\
+ "0.888383, 1.133302, 1.407490, 1.871546, 2.800552",\
+ "0.930135, 1.175055, 1.449243, 1.913298, 2.842305",\
+ "0.990066, 1.234985, 1.509173, 1.973228, 2.902235",\
+ "1.158183, 1.403102, 1.677290, 2.141346, 3.070352",\
+ "1.740091, 1.985004, 2.259185, 2.723239, 3.652244",\
+ "0.969205, 1.222269, 1.495453, 1.959167, 2.887507",\
+ "1.010957, 1.264022, 1.537205, 2.000919, 2.929260",\
+ "1.070888, 1.323952, 1.597136, 2.060850, 2.989190",\
+ "1.239005, 1.492069, 1.765253, 2.228967, 3.157307",\
+ "1.820914, 2.073971, 2.347147, 2.810860, 3.739199",\
+ "1.026840, 1.287883, 1.559592, 2.023079, 2.951016",\
+ "1.068593, 1.329635, 1.601344, 2.064832, 2.992769",\
+ "1.128523, 1.389565, 1.661275, 2.124762, 3.052699",\
+ "1.296640, 1.557683, 1.829392, 2.292880, 3.220816",\
+ "1.878549, 2.139584, 2.411286, 2.874773, 3.802708",\
+ "1.356526, 1.652092, 1.911415, 2.372405, 3.296472",\
+ "1.398278, 1.693844, 1.953167, 2.414157, 3.338225",\
+ "1.458209, 1.753775, 2.013098, 2.474087, 3.398155",\
+ "1.626326, 1.921892, 2.181215, 2.642205, 3.566272",\
+ "2.208233, 2.503792, 2.763109, 3.224098, 4.148165");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\
+ "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\
+ "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\
+ "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\
+ "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494119, 1.494119, 1.494119, 1.494121");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2649*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[32]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.634427, 0.872697, 1.149292, 1.635475, 2.607842",\
+ "0.668851, 0.907120, 1.183712, 1.669888, 2.642240",\
+ "0.739833, 0.978100, 1.254713, 1.740957, 2.713446",\
+ "0.993985, 1.232251, 1.508868, 1.995127, 2.967646",\
+ "1.919059, 2.157313, 2.433878, 2.919960, 3.892124",\
+ "0.721829, 0.960233, 1.236908, 1.722188, 2.693776",\
+ "0.756252, 0.994656, 1.271329, 1.756601, 2.728174",\
+ "0.827235, 1.065637, 1.342330, 1.827670, 2.799379",\
+ "1.081387, 1.319787, 1.596485, 2.081840, 3.053579",\
+ "2.006460, 2.244850, 2.521494, 3.006673, 3.978058",\
+ "0.802677, 1.049143, 1.324872, 1.809809, 2.780731",\
+ "0.837101, 1.083566, 1.359292, 1.844222, 2.815129",\
+ "0.908083, 1.154546, 1.430293, 1.915291, 2.886334",\
+ "1.162235, 1.408697, 1.684448, 2.169461, 3.140534",\
+ "2.087309, 2.333760, 2.609457, 3.094293, 4.065013",\
+ "0.860401, 1.114674, 1.389014, 1.873721, 2.844240",\
+ "0.894825, 1.149096, 1.423434, 1.908134, 2.878638",\
+ "0.965807, 1.220077, 1.494435, 1.979203, 2.949843",\
+ "1.219959, 1.474228, 1.748591, 2.233373, 3.204043",\
+ "2.145033, 2.399290, 2.673600, 3.158206, 4.128522",\
+ "1.188527, 1.477957, 1.741051, 2.223131, 3.189696",\
+ "1.222950, 1.512379, 1.775471, 2.257544, 3.224094",\
+ "1.293931, 1.583360, 1.846473, 2.328613, 3.295300",\
+ "1.548083, 1.837511, 2.100628, 2.582783, 3.549500",\
+ "2.473149, 2.762573, 3.025636, 3.507615, 4.473978");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.034240, 0.034240, 0.034242, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083588, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\
+ "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\
+ "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\
+ "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\
+ "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\
+ "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\
+ "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\
+ "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\
+ "2.470530, 2.470530, 2.470531, 2.470531, 2.470532");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.661467, 0.899737, 1.176348, 1.662586, 2.635063",\
+ "0.703763, 0.942033, 1.218582, 1.704611, 2.676670",\
+ "0.764325, 1.002595, 1.279082, 1.764899, 2.736534",\
+ "0.933255, 1.171525, 1.447944, 1.933534, 2.904712",\
+ "1.516509, 1.754779, 2.031088, 2.516304, 3.486737",\
+ "0.748868, 0.987273, 1.263965, 1.749299, 2.720997",\
+ "0.791164, 1.029569, 1.306198, 1.791324, 2.762603",\
+ "0.851727, 1.090131, 1.366697, 1.851612, 2.822468",\
+ "1.020657, 1.259062, 1.535559, 2.020247, 2.990646",\
+ "1.603910, 1.842315, 2.118701, 2.603017, 3.572671",\
+ "0.829717, 1.076183, 1.351928, 1.836920, 2.807952",\
+ "0.872012, 1.118479, 1.394161, 1.878945, 2.849558",\
+ "0.932575, 1.179041, 1.454660, 1.939233, 2.909423",\
+ "1.101505, 1.347972, 1.623522, 2.107867, 3.077601",\
+ "1.684759, 1.931225, 2.206665, 2.690638, 3.659626",\
+ "0.887441, 1.141714, 1.416070, 1.900832, 2.871461",\
+ "0.929737, 1.184009, 1.458303, 1.942857, 2.913067",\
+ "0.990299, 1.244572, 1.518803, 2.003145, 2.972932",\
+ "1.159229, 1.413502, 1.687665, 2.171780, 3.141110",\
+ "1.742483, 1.996755, 2.270807, 2.754550, 3.723135",\
+ "1.215567, 1.504997, 1.768108, 2.250242, 3.216917",\
+ "1.257862, 1.547292, 1.810339, 2.292266, 3.258523",\
+ "1.318425, 1.607855, 1.870836, 2.352553, 3.318388",\
+ "1.487355, 1.776785, 2.039696, 2.521187, 3.486566",\
+ "2.070609, 2.360038, 2.622834, 3.103956, 4.068591");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\
+ "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\
+ "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\
+ "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\
+ "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\
+ "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\
+ "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498067, 1.498067, 1.498067");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2302*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[38]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.679396, 0.938967, 1.226201, 1.725937, 2.725407",\
+ "0.713789, 0.973360, 1.260594, 1.760331, 2.759802",\
+ "0.785026, 1.044598, 1.331832, 1.831566, 2.831035",\
+ "1.039193, 1.298764, 1.585998, 2.085732, 3.085201",\
+ "1.963796, 2.223368, 2.510604, 3.010348, 4.009837",\
+ "0.766804, 1.026534, 1.313864, 1.812651, 2.811341",\
+ "0.801197, 1.060927, 1.348257, 1.847045, 2.845736",\
+ "0.872434, 1.132165, 1.419494, 1.918280, 2.916969",\
+ "1.126601, 1.386331, 1.673661, 2.172447, 3.171135",\
+ "2.051204, 2.310935, 2.598267, 3.097062, 4.095771",\
+ "0.847692, 1.115543, 1.401829, 1.900272, 2.898296",\
+ "0.882085, 1.149936, 1.436222, 1.934666, 2.932691",\
+ "0.953322, 1.221174, 1.507460, 2.005902, 3.003924",\
+ "1.207489, 1.475340, 1.761626, 2.260068, 3.258090",\
+ "2.132092, 2.399944, 2.686232, 3.184684, 4.182726",\
+ "0.908548, 1.181219, 1.465974, 1.964185, 2.961805",\
+ "0.942941, 1.215612, 1.500367, 1.998580, 2.996200",\
+ "1.014178, 1.286850, 1.571604, 2.069815, 3.067433",\
+ "1.268345, 1.541016, 1.825771, 2.323982, 3.321599",\
+ "2.192948, 2.465620, 2.750377, 3.248597, 4.246235",\
+ "1.244710, 1.546113, 1.818152, 2.313658, 3.307261",\
+ "1.279103, 1.580506, 1.852545, 2.348052, 3.341656",\
+ "1.350341, 1.651744, 1.923782, 2.419287, 3.412889",\
+ "1.604507, 1.905910, 2.177949, 2.673453, 3.667055",\
+ "2.529111, 2.830513, 3.102555, 3.598069, 4.591691");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\
+ "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\
+ "2.465102, 2.465102, 2.465169, 2.465398, 2.465856",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\
+ "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\
+ "2.465102, 2.465102, 2.465170, 2.465398, 2.465856",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\
+ "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\
+ "2.465102, 2.465102, 2.465170, 2.465398, 2.465856",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\
+ "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\
+ "2.465102, 2.465102, 2.465170, 2.465398, 2.465856",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\
+ "0.083750, 0.083751, 0.083754, 0.083761, 0.083776",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692763, 0.692776, 0.692814, 0.692889",\
+ "2.465102, 2.465102, 2.465172, 2.465399, 2.465856");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.711192, 0.970763, 1.257999, 1.757746, 2.757238",\
+ "0.752943, 1.012514, 1.299751, 1.799497, 2.798988",\
+ "0.812873, 1.072445, 1.359681, 1.859427, 2.858919",\
+ "0.980990, 1.240561, 1.527798, 2.027544, 3.027034",\
+ "1.563015, 1.822585, 2.109830, 2.609611, 3.609173",\
+ "0.798600, 1.058330, 1.345662, 1.844460, 2.843172",\
+ "0.840351, 1.100081, 1.387414, 1.886211, 2.884922",\
+ "0.900282, 1.160012, 1.447344, 1.946141, 2.944853",\
+ "1.068398, 1.328128, 1.615461, 2.114258, 3.112968",\
+ "1.650424, 1.910152, 2.197493, 2.696325, 3.695107",\
+ "0.879488, 1.147339, 1.433627, 1.932081, 2.930127",\
+ "0.921239, 1.189090, 1.475379, 1.973832, 2.971877",\
+ "0.981170, 1.249021, 1.535309, 2.033763, 3.031808",\
+ "1.149286, 1.417137, 1.703426, 2.201879, 3.199923",\
+ "1.731312, 1.999161, 2.285458, 2.783947, 3.782062",\
+ "0.940344, 1.213015, 1.497772, 1.995995, 2.993636",\
+ "0.982095, 1.254766, 1.539524, 2.037745, 3.035386",\
+ "1.042026, 1.314697, 1.599454, 2.097676, 3.095317",\
+ "1.210142, 1.482813, 1.767570, 2.265792, 3.263432",\
+ "1.792167, 2.064837, 2.349603, 2.847860, 3.845571",\
+ "1.276506, 1.577909, 1.849950, 2.345467, 3.339092",\
+ "1.318258, 1.619660, 1.891702, 2.387218, 3.380842",\
+ "1.378188, 1.679591, 1.951632, 2.447148, 3.440773",\
+ "1.546304, 1.847707, 2.119749, 2.615264, 3.608888",\
+ "2.128330, 2.429730, 2.701782, 3.197332, 4.191027");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\
+ "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494119, 1.494120, 1.494122, 1.494128, 1.494141");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2566*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[39]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.658633, 0.912014, 1.190716, 1.652421, 2.575833",\
+ "0.693026, 0.946407, 1.225109, 1.686815, 2.610227",\
+ "0.764264, 1.017644, 1.296346, 1.758051, 2.681462",\
+ "1.018430, 1.271811, 1.550512, 2.012218, 2.935628",\
+ "1.943034, 2.196414, 2.475117, 2.936828, 3.860250",\
+ "0.746043, 0.999594, 1.278259, 1.739136, 2.661767",\
+ "0.780436, 1.033988, 1.312652, 1.773529, 2.696161",\
+ "0.851673, 1.105225, 1.383889, 1.844766, 2.767396",\
+ "1.105840, 1.359391, 1.638056, 2.098932, 3.021562",\
+ "2.030443, 2.283995, 2.562661, 3.023543, 3.946184",\
+ "0.826857, 1.088640, 1.366222, 1.826758, 2.748722",\
+ "0.861250, 1.123033, 1.400615, 1.861151, 2.783116",\
+ "0.932488, 1.194270, 1.471853, 1.932387, 2.854351",\
+ "1.186654, 1.448437, 1.726019, 2.186554, 3.108517",\
+ "2.111258, 2.373040, 2.650624, 3.111165, 4.033139",\
+ "0.884438, 1.154368, 1.430361, 1.890671, 2.812231",\
+ "0.918831, 1.188761, 1.464754, 1.925064, 2.846625",\
+ "0.990068, 1.259999, 1.535991, 1.996301, 2.917860",\
+ "1.244235, 1.514165, 1.790157, 2.250467, 3.172026",\
+ "2.168839, 2.438769, 2.714763, 3.175078, 4.096648",\
+ "1.216287, 1.519868, 1.782153, 2.239986, 3.157687",\
+ "1.250680, 1.554260, 1.816547, 2.274380, 3.192081",\
+ "1.321917, 1.625498, 1.887784, 2.345616, 3.263316",\
+ "1.576084, 1.879665, 2.141950, 2.599783, 3.517482",\
+ "2.500688, 2.804268, 3.066556, 3.524393, 4.442104");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692760, 0.692769, 0.692798, 0.692856",\
+ "2.465103, 2.465103, 2.465140, 2.465270, 2.465530",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692760, 0.692770, 0.692798, 0.692856",\
+ "2.465103, 2.465103, 2.465141, 2.465270, 2.465530",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692760, 0.692770, 0.692798, 0.692856",\
+ "2.465103, 2.465103, 2.465141, 2.465270, 2.465530",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692760, 0.692770, 0.692798, 0.692856",\
+ "2.465103, 2.465103, 2.465141, 2.465270, 2.465530",\
+ "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\
+ "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\
+ "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\
+ "0.692760, 0.692761, 0.692770, 0.692799, 0.692856",\
+ "2.465103, 2.465103, 2.465142, 2.465271, 2.465530");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.690429, 0.943810, 1.222513, 1.684225, 2.607649",\
+ "0.732181, 0.985561, 1.264264, 1.725976, 2.649400",\
+ "0.792111, 1.045491, 1.324195, 1.785906, 2.709330",\
+ "0.960228, 1.213608, 1.492311, 1.954023, 2.877446",\
+ "1.542253, 1.795633, 2.074341, 2.536073, 3.459536",\
+ "0.777839, 1.031390, 1.310056, 1.770939, 2.693583",\
+ "0.819590, 1.073142, 1.351808, 1.812690, 2.735333",\
+ "0.879520, 1.133072, 1.411738, 1.872621, 2.795264",\
+ "1.047637, 1.301189, 1.579854, 2.040737, 2.963380",\
+ "1.629662, 1.883214, 2.161885, 2.622787, 3.545470",\
+ "0.858653, 1.120436, 1.398020, 1.858561, 2.780538",\
+ "0.900405, 1.162187, 1.439771, 1.900312, 2.822289",\
+ "0.960335, 1.222118, 1.499701, 1.960243, 2.882219",\
+ "1.128451, 1.390234, 1.667818, 2.128359, 3.050335",\
+ "1.710477, 1.972259, 2.249848, 2.710409, 3.632425",\
+ "0.916234, 1.186164, 1.462158, 1.922474, 2.844047",\
+ "0.957985, 1.227916, 1.503910, 1.964226, 2.885798",\
+ "1.017915, 1.287846, 1.563840, 2.024156, 2.945728",\
+ "1.186032, 1.455963, 1.731956, 2.192272, 3.113844",\
+ "1.768058, 2.037988, 2.313987, 2.774323, 3.695934",\
+ "1.248083, 1.551663, 1.813951, 2.271790, 3.189503",\
+ "1.289834, 1.593415, 1.855702, 2.313541, 3.231254",\
+ "1.349765, 1.653345, 1.915633, 2.373471, 3.291184",\
+ "1.517881, 1.821462, 2.083749, 2.541588, 3.459300",\
+ "2.099906, 2.403486, 2.665780, 3.123638, 4.041390");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\
+ "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\
+ "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\
+ "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\
+ "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\
+ "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\
+ "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\
+ "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\
+ "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\
+ "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\
+ "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\
+ "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\
+ "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\
+ "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\
+ "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\
+ "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\
+ "1.494119, 1.494119, 1.494121, 1.494126, 1.494135");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2608*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[41]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.576605, 0.831535, 1.088524, 1.527728, 2.406135",\
+ "0.611028, 0.865958, 1.122948, 1.562156, 2.440572",\
+ "0.682011, 0.936939, 1.193932, 1.633147, 2.511575",\
+ "0.936163, 1.191091, 1.448086, 1.887307, 2.765749",\
+ "1.861240, 2.116160, 2.373173, 2.812451, 3.691008",\
+ "0.664013, 0.919020, 1.175996, 1.614442, 2.492069",\
+ "0.698437, 0.953443, 1.210420, 1.648871, 2.526506",\
+ "0.769419, 1.024424, 1.281404, 1.719861, 2.597509",\
+ "1.023571, 1.278576, 1.535558, 1.974021, 2.851683",\
+ "1.948648, 2.203645, 2.460645, 2.899166, 3.776942",\
+ "0.751657, 1.007845, 1.263958, 1.702063, 2.579024",\
+ "0.786080, 1.042268, 1.298382, 1.736492, 2.613461",\
+ "0.857063, 1.113249, 1.369366, 1.807482, 2.684464",\
+ "1.111215, 1.367401, 1.623520, 2.061643, 2.938638",\
+ "2.036291, 2.292470, 2.548607, 2.986787, 3.863897",\
+ "0.814841, 1.073252, 1.328092, 1.765976, 2.642533",\
+ "0.849265, 1.107675, 1.362517, 1.800405, 2.676970",\
+ "0.920247, 1.178657, 1.433500, 1.871395, 2.747973",\
+ "1.174399, 1.432808, 1.687654, 2.125556, 3.002147",\
+ "2.099474, 2.357878, 2.612742, 3.050700, 3.927406",\
+ "1.148308, 1.435007, 1.679656, 2.115198, 2.987988",\
+ "1.182731, 1.469430, 1.714081, 2.149627, 3.022426",\
+ "1.253713, 1.540412, 1.785064, 2.220617, 3.093429",\
+ "1.507865, 1.794564, 2.039218, 2.474777, 3.347603",\
+ "2.432936, 2.719633, 2.964306, 3.399922, 4.272861");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208076, 0.208111, 0.208180",\
+ "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470714, 2.471298, 2.472467",\
+ "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\
+ "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470715, 2.471298, 2.472467",\
+ "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\
+ "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\
+ "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\
+ "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\
+ "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\
+ "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\
+ "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\
+ "0.693294, 0.693297, 0.693300, 0.693300, 0.693300",\
+ "2.470544, 2.470544, 2.470721, 2.471301, 2.472467");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.603644, 0.858574, 1.115563, 1.554765, 2.433169",\
+ "0.645940, 0.900870, 1.157859, 1.597061, 2.475466",\
+ "0.706502, 0.961433, 1.218421, 1.657624, 2.536028",\
+ "0.875433, 1.130363, 1.387352, 1.826554, 2.704960",\
+ "1.458686, 1.713616, 1.970605, 2.409806, 3.288209",\
+ "0.691052, 0.946059, 1.203035, 1.641479, 2.519103",\
+ "0.733348, 0.988355, 1.245331, 1.683775, 2.561400",\
+ "0.793911, 1.048918, 1.305893, 1.744338, 2.621962",\
+ "0.962841, 1.217848, 1.474824, 1.913269, 2.790894",\
+ "1.546094, 1.801101, 2.058077, 2.496521, 3.374143",\
+ "0.778696, 1.034884, 1.290997, 1.729101, 2.606058",\
+ "0.820992, 1.077180, 1.333292, 1.771397, 2.648355",\
+ "0.881555, 1.137743, 1.393855, 1.831960, 2.708917",\
+ "1.050485, 1.306673, 1.562785, 2.000890, 2.877849",\
+ "1.633738, 1.889926, 2.146038, 2.584142, 3.461098",\
+ "0.841881, 1.100292, 1.355131, 1.793014, 2.669567",\
+ "0.884176, 1.142587, 1.397427, 1.835310, 2.711864",\
+ "0.944739, 1.203150, 1.457990, 1.895873, 2.772426",\
+ "1.113669, 1.372080, 1.626920, 2.064803, 2.941358",\
+ "1.696922, 1.955333, 2.210173, 2.648055, 3.524607",\
+ "1.175348, 1.462047, 1.706695, 2.142236, 3.015023",\
+ "1.217643, 1.504343, 1.748991, 2.184532, 3.057320",\
+ "1.278206, 1.564905, 1.809554, 2.245094, 3.117882",\
+ "1.447136, 1.733835, 1.978484, 2.414025, 3.286813",\
+ "2.030389, 2.317089, 2.561737, 2.997277, 3.870063");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\
+ "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\
+ "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\
+ "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\
+ "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\
+ "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\
+ "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\
+ "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\
+ "1.498067, 1.498067, 1.498066, 1.498065, 1.498061");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2536*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[46]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.746778, 1.007936, 1.300121, 1.808548, 2.825403",\
+ "0.781168, 1.042326, 1.334511, 1.842939, 2.859794",\
+ "0.852412, 1.113570, 1.405754, 1.914182, 2.931037",\
+ "1.106578, 1.367736, 1.659921, 2.168348, 3.185203",\
+ "2.031144, 2.292302, 2.584487, 3.092916, 4.109773",\
+ "0.834191, 1.095510, 1.387813, 1.895263, 2.911337",\
+ "0.868581, 1.129900, 1.422203, 1.929654, 2.945728",\
+ "0.939824, 1.201144, 1.493447, 2.000897, 3.016971",\
+ "1.193991, 1.455310, 1.747613, 2.255063, 3.271137",\
+ "2.118557, 2.379876, 2.672179, 3.179631, 4.195706",\
+ "0.915090, 1.184556, 1.475780, 1.982886, 2.998292",\
+ "0.949480, 1.218946, 1.510170, 2.017276, 3.032683",\
+ "1.020724, 1.290190, 1.581414, 2.088519, 3.103926",\
+ "1.274890, 1.544356, 1.835580, 2.342686, 3.358092",\
+ "2.199456, 2.468922, 2.760146, 3.267253, 4.282661",\
+ "0.974724, 1.250286, 1.539926, 2.046799, 3.061801",\
+ "1.009114, 1.284676, 1.574316, 2.081189, 3.096192",\
+ "1.080358, 1.355919, 1.645560, 2.152433, 3.167435",\
+ "1.334524, 1.610085, 1.899726, 2.406599, 3.421601",\
+ "2.259090, 2.534652, 2.824292, 3.331166, 4.346170",\
+ "1.308449, 1.615752, 1.892195, 2.396312, 3.407257",\
+ "1.342839, 1.650142, 1.926585, 2.430702, 3.441648",\
+ "1.414083, 1.721386, 1.997829, 2.501945, 3.512891",\
+ "1.668249, 1.975552, 2.251995, 2.756112, 3.767057",\
+ "2.592815, 2.900118, 3.176561, 3.680679, 4.691627");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\
+ "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\
+ "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\
+ "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\
+ "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\
+ "2.464216, 2.464216, 2.464223, 2.464247, 2.464295");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.778533, 1.039691, 1.331875, 1.840304, 2.857162",\
+ "0.820286, 1.081443, 1.373628, 1.882057, 2.898914",\
+ "0.880216, 1.141374, 1.433558, 1.941987, 2.958845",\
+ "1.048333, 1.309491, 1.601676, 2.110105, 3.126962",\
+ "1.630225, 1.891381, 2.183566, 2.692000, 3.708866",\
+ "0.865946, 1.127265, 1.419568, 1.927019, 2.943096",\
+ "0.907698, 1.169017, 1.461320, 1.968772, 2.984848",\
+ "0.967629, 1.228948, 1.521251, 2.028702, 3.044779",\
+ "1.135746, 1.397065, 1.689368, 2.196820, 3.212896",\
+ "1.717638, 1.978955, 2.271259, 2.778715, 3.794800",\
+ "0.946845, 1.216310, 1.507534, 2.014642, 3.030051",\
+ "0.988598, 1.258063, 1.549287, 2.056394, 3.071803",\
+ "1.048528, 1.317993, 1.609217, 2.116324, 3.131734",\
+ "1.216645, 1.486111, 1.777335, 2.284442, 3.299851",\
+ "1.798537, 2.068001, 2.359225, 2.866337, 3.881755",\
+ "1.006479, 1.282040, 1.571681, 2.078555, 3.093560",\
+ "1.048231, 1.323793, 1.613433, 2.120307, 3.135312",\
+ "1.108162, 1.383723, 1.673364, 2.180238, 3.195243",\
+ "1.276279, 1.551840, 1.841481, 2.348355, 3.363360",\
+ "1.858171, 2.133730, 2.423372, 2.930250, 3.945264",\
+ "1.340204, 1.647506, 1.923949, 2.428067, 3.439016",\
+ "1.381956, 1.689259, 1.965702, 2.469820, 3.480768",\
+ "1.441887, 1.749189, 2.025632, 2.529750, 3.540699",\
+ "1.610004, 1.917307, 2.193750, 2.697868, 3.708816",\
+ "2.191895, 2.499197, 2.775640, 3.279763, 4.290720");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2630*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[47]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.730000, 0.984087, 1.265833, 1.734427, 2.671616",\
+ "0.764390, 1.018477, 1.300223, 1.768817, 2.706006",\
+ "0.835634, 1.089720, 1.371467, 1.840061, 2.777249",\
+ "1.089800, 1.343887, 1.625633, 2.094227, 3.031415",\
+ "2.014367, 2.268453, 2.550199, 3.018794, 3.955984",\
+ "0.817406, 1.071683, 1.353396, 1.821141, 2.757549",\
+ "0.851796, 1.106073, 1.387787, 1.855531, 2.791939",\
+ "0.923039, 1.177317, 1.459030, 1.926775, 2.863183",\
+ "1.177206, 1.431483, 1.713197, 2.180941, 3.117349",\
+ "2.101773, 2.356050, 2.637762, 3.105508, 4.041918",\
+ "0.898242, 1.160744, 1.441359, 1.908762, 2.844504",\
+ "0.932632, 1.195135, 1.475749, 1.943152, 2.878895",\
+ "1.003876, 1.266378, 1.546993, 2.014396, 2.950138",\
+ "1.258042, 1.520545, 1.801159, 2.268562, 3.204304",\
+ "2.182609, 2.445111, 2.725725, 3.193129, 4.128873",\
+ "0.955902, 1.226495, 1.505499, 1.972675, 2.908013",\
+ "0.990292, 1.260885, 1.539889, 2.007065, 2.942404",\
+ "1.061535, 1.332129, 1.611133, 2.078309, 3.013647",\
+ "1.315702, 1.586295, 1.865299, 2.332475, 3.267813",\
+ "2.240268, 2.510862, 2.789865, 3.257042, 4.192382",\
+ "1.290536, 1.592309, 1.857360, 2.322016, 3.253469",\
+ "1.324926, 1.626699, 1.891750, 2.356406, 3.287859",\
+ "1.396169, 1.697943, 1.962993, 2.427649, 3.359103",\
+ "1.650336, 1.952109, 2.217160, 2.681816, 3.613269",\
+ "2.574903, 2.876675, 3.141726, 3.606383, 4.537838");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\
+ "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\
+ "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\
+ "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\
+ "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\
+ "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\
+ "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\
+ "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\
+ "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\
+ "2.464221, 2.464222, 2.464226, 2.464241, 2.464270");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.761755, 1.015841, 1.297587, 1.766182, 2.703373",\
+ "0.803508, 1.057594, 1.339340, 1.807935, 2.745125",\
+ "0.863438, 1.117525, 1.399270, 1.867865, 2.805056",\
+ "1.031556, 1.285642, 1.567388, 2.035983, 2.973173",\
+ "1.613449, 1.867533, 2.149277, 2.617876, 3.555073",\
+ "0.849161, 1.103438, 1.385151, 1.852896, 2.789307",\
+ "0.890914, 1.145190, 1.426903, 1.894649, 2.831059",\
+ "0.950844, 1.205121, 1.486834, 1.954579, 2.890990",\
+ "1.118961, 1.373238, 1.654951, 2.122696, 3.059107",\
+ "1.700854, 1.955129, 2.236841, 2.704590, 3.641007",\
+ "0.929998, 1.192499, 1.473114, 1.940517, 2.876262",\
+ "0.971750, 1.234252, 1.514866, 1.982270, 2.918014",\
+ "1.031680, 1.294182, 1.574797, 2.042201, 2.977945",\
+ "1.199798, 1.462299, 1.742914, 2.210318, 3.146062",\
+ "1.781691, 2.044191, 2.324804, 2.792211, 3.727962",\
+ "0.987657, 1.258250, 1.537253, 2.004430, 2.939771",\
+ "1.029410, 1.300003, 1.579006, 2.046183, 2.981523",\
+ "1.089340, 1.359933, 1.638936, 2.106113, 3.041454",\
+ "1.257457, 1.528050, 1.807054, 2.274230, 3.209571",\
+ "1.839350, 2.109941, 2.388943, 2.856124, 3.791471",\
+ "1.322291, 1.624063, 1.889114, 2.353771, 3.285227",\
+ "1.364043, 1.665816, 1.930866, 2.395524, 3.326979",\
+ "1.423974, 1.725746, 1.990797, 2.455454, 3.386910",\
+ "1.592091, 1.893864, 2.158914, 2.623571, 3.555027",\
+ "2.173984, 2.475754, 2.740804, 3.205465, 4.136927");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\
+ "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\
+ "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\
+ "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\
+ "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\
+ "1.494118, 1.494118, 1.494119, 1.494119, 1.494119");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2588*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[16]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.408137, 0.641492, 0.827125, 1.126915, 1.707802",\
+ "0.449833, 0.683188, 0.868821, 1.168611, 1.749498",\
+ "0.526013, 0.759368, 0.945001, 1.244791, 1.825678",\
+ "0.781403, 1.014758, 1.200392, 1.500182, 2.081068",\
+ "1.705853, 1.939205, 2.124836, 2.424627, 3.005518",\
+ "0.496543, 0.728810, 0.914406, 1.214220, 1.795155",\
+ "0.538239, 0.770506, 0.956102, 1.255916, 1.836851",\
+ "0.614419, 0.846686, 1.032282, 1.332096, 1.913031",\
+ "0.869809, 1.102077, 1.287673, 1.587487, 2.168421",\
+ "1.794258, 2.026523, 2.212117, 2.511932, 3.092872",\
+ "0.585620, 0.809145, 0.994433, 1.294249, 1.875187",\
+ "0.627316, 0.850841, 1.036129, 1.335945, 1.916883",\
+ "0.703496, 0.927021, 1.112309, 1.412125, 1.993063",\
+ "0.958887, 1.182412, 1.367700, 1.667515, 2.248453",\
+ "1.883336, 2.106858, 2.292144, 2.591961, 3.172904",\
+ "0.648884, 0.866977, 1.052144, 1.351703, 1.932250",\
+ "0.690580, 0.908672, 1.093840, 1.393399, 1.973946",\
+ "0.766760, 0.984852, 1.170020, 1.469579, 2.050126",\
+ "1.022151, 1.240243, 1.425410, 1.724970, 2.305516",\
+ "1.946599, 2.164690, 2.349855, 2.649415, 3.229967",\
+ "0.982874, 1.172308, 1.355803, 1.654896, 2.234530",\
+ "1.024570, 1.214004, 1.397499, 1.696592, 2.276226",\
+ "1.100750, 1.290184, 1.473679, 1.772772, 2.352406",\
+ "1.356140, 1.545574, 1.729069, 2.028162, 2.607796",\
+ "2.280588, 2.470021, 2.653514, 2.952608, 3.532247");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\
+ "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\
+ "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.428385, 0.661739, 0.847373, 1.147163, 1.728050",\
+ "0.460631, 0.693986, 0.879619, 1.179409, 1.760296",\
+ "0.510947, 0.744302, 0.929935, 1.229725, 1.810612",\
+ "0.671611, 0.904965, 1.090599, 1.390389, 1.971276",\
+ "1.252728, 1.486083, 1.671717, 1.971507, 2.552392",\
+ "0.516791, 0.749058, 0.934654, 1.234468, 1.815403",\
+ "0.549037, 0.781304, 0.966900, 1.266714, 1.847649",\
+ "0.599353, 0.831620, 1.017216, 1.317030, 1.897965",\
+ "0.760017, 0.992284, 1.177880, 1.477694, 2.058629",\
+ "1.341134, 1.573402, 1.758998, 2.058812, 2.639746",\
+ "0.605868, 0.829393, 1.014680, 1.314497, 1.895434",\
+ "0.638114, 0.861639, 1.046927, 1.346743, 1.927681",\
+ "0.688430, 0.911955, 1.097243, 1.397059, 1.977997",\
+ "0.849094, 1.072619, 1.257906, 1.557723, 2.138661",\
+ "1.430211, 1.653737, 1.839025, 2.138841, 2.719778",\
+ "0.669132, 0.887224, 1.072391, 1.371951, 1.952498",\
+ "0.701378, 0.919471, 1.104638, 1.404197, 1.984744",\
+ "0.751694, 0.969786, 1.154953, 1.454513, 2.035060",\
+ "0.912358, 1.130450, 1.315617, 1.615177, 2.195724",\
+ "1.493475, 1.711568, 1.896736, 2.196295, 2.776841",\
+ "1.003122, 1.192555, 1.376050, 1.675143, 2.254777",\
+ "1.035368, 1.224802, 1.408297, 1.707390, 2.287024",\
+ "1.085684, 1.275118, 1.458613, 1.757706, 2.337340",\
+ "1.246348, 1.435782, 1.619277, 1.918369, 2.498003",\
+ "1.827465, 2.016899, 2.200395, 2.499487, 3.079121");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\
+ "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\
+ "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\
+ "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\
+ "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\
+ "1.483040, 1.483040, 1.483040, 1.483042, 1.483047");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2478*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[17]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.516812, 0.720433, 0.930283, 1.259401, 1.891051",\
+ "0.558535, 0.762156, 0.972006, 1.301124, 1.932775",\
+ "0.634601, 0.838222, 1.048072, 1.377190, 2.008840",\
+ "0.890090, 1.093710, 1.303558, 1.632676, 2.264330",\
+ "1.814399, 2.018020, 2.227869, 2.556987, 3.188638",\
+ "0.605540, 0.807752, 1.017564, 1.346706, 1.978405",\
+ "0.647263, 0.849475, 1.059287, 1.388429, 2.020128",\
+ "0.723329, 0.925541, 1.135353, 1.464495, 2.096194",\
+ "0.978818, 1.181028, 1.390838, 1.719981, 2.351683",\
+ "1.903127, 2.105338, 2.315150, 2.644292, 3.275992",\
+ "0.695187, 0.888089, 1.097591, 1.426734, 2.058436",\
+ "0.736910, 0.929812, 1.139314, 1.468457, 2.100160",\
+ "0.812976, 1.005878, 1.215380, 1.544523, 2.176225",\
+ "1.068465, 1.261366, 1.470865, 1.800010, 2.431715",\
+ "1.992774, 2.185676, 2.395177, 2.724321, 3.356023",\
+ "0.755223, 0.945959, 1.155358, 1.484250, 2.115621",\
+ "0.796946, 0.987682, 1.197081, 1.525973, 2.157344",\
+ "0.873011, 1.063748, 1.273147, 1.602039, 2.233410",\
+ "1.128500, 1.319236, 1.528632, 1.857525, 2.488900",\
+ "2.052809, 2.243546, 2.452944, 2.781836, 3.413208",\
+ "1.058034, 1.251576, 1.459026, 1.787495, 2.418047",\
+ "1.099757, 1.293299, 1.500749, 1.829218, 2.459770",\
+ "1.175823, 1.369365, 1.576815, 1.905284, 2.535836",\
+ "1.431312, 1.624853, 1.832301, 2.160770, 2.791326",\
+ "2.355621, 2.549163, 2.756612, 3.085082, 3.715634");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\
+ "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\
+ "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\
+ "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\
+ "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\
+ "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\
+ "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\
+ "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\
+ "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\
+ "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\
+ "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\
+ "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\
+ "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\
+ "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\
+ "2.452500, 2.452500, 2.452512, 2.452522, 2.452533");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.539402, 0.743023, 0.952873, 1.281991, 1.913641",\
+ "0.571427, 0.775047, 0.984897, 1.314015, 1.945666",\
+ "0.621835, 0.825456, 1.035306, 1.364424, 1.996074",\
+ "0.782894, 0.986516, 1.196367, 1.525485, 2.157133",\
+ "1.362868, 1.566489, 1.776340, 2.105458, 2.737106",\
+ "0.628130, 0.830342, 1.040154, 1.369296, 2.000995",\
+ "0.660155, 0.862366, 1.072178, 1.401320, 2.033020",\
+ "0.710563, 0.912774, 1.122587, 1.451729, 2.083427",\
+ "0.871623, 1.073835, 1.283648, 1.612790, 2.244487",\
+ "1.451596, 1.653808, 1.863621, 2.192763, 2.824460",\
+ "0.717777, 0.910679, 1.120180, 1.449324, 2.081027",\
+ "0.749802, 0.942704, 1.152205, 1.481349, 2.113051",\
+ "0.800210, 0.993112, 1.202614, 1.531757, 2.163459",\
+ "0.961270, 1.154172, 1.363675, 1.692818, 2.324518",\
+ "1.541243, 1.734145, 1.943648, 2.272791, 2.904491",\
+ "0.777813, 0.968549, 1.177947, 1.506840, 2.138211",\
+ "0.809837, 1.000574, 1.209971, 1.538864, 2.170236",\
+ "0.860245, 1.050982, 1.260381, 1.589273, 2.220644",\
+ "1.021305, 1.212042, 1.421442, 1.750333, 2.381703",\
+ "1.601278, 1.792015, 2.001415, 2.330307, 2.961676",\
+ "1.080624, 1.274166, 1.481616, 1.810085, 2.440637",\
+ "1.112649, 1.306190, 1.513640, 1.842109, 2.472662",\
+ "1.163057, 1.356599, 1.564049, 1.892518, 2.523069",\
+ "1.324117, 1.517659, 1.725110, 2.053579, 2.684129",\
+ "1.904090, 2.097632, 2.305083, 2.633552, 3.264102");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\
+ "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\
+ "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\
+ "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\
+ "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\
+ "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\
+ "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\
+ "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\
+ "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\
+ "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\
+ "1.484511, 1.484511, 1.484513, 1.484514, 1.484517");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2528*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[19]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.343347, 0.560733, 0.738878, 1.027873, 1.588767",\
+ "0.376901, 0.594286, 0.772429, 1.061825, 1.623703",\
+ "0.447931, 0.665317, 0.843465, 1.132863, 1.694739",\
+ "0.702775, 0.920161, 1.098308, 1.387706, 1.949584",\
+ "1.627697, 1.845075, 2.023177, 2.312590, 2.874544",\
+ "0.431725, 0.648051, 0.826159, 1.115178, 1.676121",\
+ "0.465279, 0.681604, 0.859710, 1.149130, 1.711057",\
+ "0.536309, 0.752636, 0.930746, 1.220168, 1.782093",\
+ "0.791152, 1.007479, 1.185589, 1.475011, 2.036938",\
+ "1.716075, 1.932394, 2.110458, 2.399895, 2.961898",\
+ "0.521054, 0.728383, 0.906186, 1.195207, 1.756152",\
+ "0.554608, 0.761937, 0.939737, 1.229159, 1.791088",\
+ "0.625638, 0.832968, 1.010773, 1.300196, 1.862124",\
+ "0.880482, 1.087811, 1.265616, 1.555040, 2.116970",\
+ "1.805404, 2.012726, 2.190485, 2.479923, 3.041929",\
+ "0.584699, 0.786201, 0.963880, 1.252637, 1.813169",\
+ "0.618252, 0.819754, 0.997431, 1.286590, 1.848107",\
+ "0.689283, 0.890786, 1.068467, 1.357627, 1.919143",\
+ "0.944126, 1.145629, 1.323310, 1.612471, 2.173989",\
+ "1.869048, 2.070544, 2.248179, 2.537354, 3.098948",\
+ "0.912898, 1.091426, 1.267535, 1.555809, 2.115392",\
+ "0.946452, 1.124980, 1.301087, 1.589763, 2.150333",\
+ "1.017482, 1.196011, 1.372123, 1.660800, 2.221369",\
+ "1.272326, 1.450854, 1.626966, 1.915644, 2.476214",\
+ "2.197247, 2.375769, 2.551834, 2.840528, 3.401175");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\
+ "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\
+ "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\
+ "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\
+ "2.446888, 2.446896, 2.446897, 2.446897, 2.446897",\
+ "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\
+ "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\
+ "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\
+ "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\
+ "2.446888, 2.446896, 2.446897, 2.446897, 2.446897",\
+ "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\
+ "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\
+ "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\
+ "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\
+ "2.446889, 2.446896, 2.446897, 2.446897, 2.446897",\
+ "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\
+ "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\
+ "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\
+ "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\
+ "2.446889, 2.446896, 2.446897, 2.446897, 2.446897",\
+ "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\
+ "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\
+ "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\
+ "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\
+ "2.446889, 2.446896, 2.446897, 2.446897, 2.446897");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.337578, 0.554964, 0.733111, 1.022508, 1.584385",\
+ "0.369918, 0.587304, 0.765454, 1.054853, 1.616734",\
+ "0.420270, 0.637656, 0.815804, 1.105202, 1.667081",\
+ "0.581348, 0.798734, 0.976881, 1.266279, 1.828157",\
+ "1.161863, 1.379232, 1.557282, 1.846629, 2.408468",\
+ "0.425956, 0.642282, 0.820392, 1.109813, 1.671738",\
+ "0.458296, 0.674622, 0.852735, 1.142159, 1.704088",\
+ "0.508648, 0.724974, 0.903085, 1.192507, 1.754434",\
+ "0.669726, 0.886052, 1.064162, 1.353584, 1.915510",\
+ "1.250240, 1.466550, 1.644563, 1.933934, 2.495822",\
+ "0.515285, 0.722614, 0.900419, 1.189842, 1.751770",\
+ "0.547625, 0.754955, 0.932762, 1.222187, 1.784119",\
+ "0.597977, 0.805307, 0.983111, 1.272535, 1.834466",\
+ "0.759055, 0.966385, 1.144189, 1.433612, 1.995542",\
+ "1.339568, 1.546883, 1.724590, 2.013963, 2.575853",\
+ "0.578929, 0.780432, 0.958113, 1.247273, 1.808789",\
+ "0.611270, 0.812772, 0.990456, 1.279618, 1.841138",\
+ "0.661622, 0.863124, 1.040806, 1.329967, 1.891485",\
+ "0.822700, 1.024202, 1.201883, 1.491044, 2.052561",\
+ "1.403211, 1.604700, 1.782284, 2.071394, 2.632872",\
+ "0.907129, 1.085657, 1.261768, 1.550446, 2.111014",\
+ "0.939469, 1.117998, 1.294111, 1.582791, 2.143364",\
+ "0.989821, 1.168350, 1.344461, 1.633139, 2.193710",\
+ "1.150899, 1.329427, 1.505538, 1.794216, 2.354787",\
+ "1.731412, 1.909925, 2.085939, 2.374567, 2.935098");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\
+ "0.059305, 0.059302, 0.059288, 0.059276, 0.059261",\
+ "0.131696, 0.131694, 0.131680, 0.131669, 0.131651",\
+ "0.419114, 0.419122, 0.419145, 0.419266, 0.419546",\
+ "1.483332, 1.483297, 1.483098, 1.482941, 1.482729",\
+ "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\
+ "0.059305, 0.059302, 0.059288, 0.059276, 0.059261",\
+ "0.131696, 0.131694, 0.131680, 0.131669, 0.131651",\
+ "0.419115, 0.419122, 0.419145, 0.419266, 0.419546",\
+ "1.483331, 1.483297, 1.483098, 1.482941, 1.482729",\
+ "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\
+ "0.059305, 0.059302, 0.059288, 0.059276, 0.059261",\
+ "0.131696, 0.131694, 0.131680, 0.131669, 0.131651",\
+ "0.419115, 0.419122, 0.419145, 0.419266, 0.419546",\
+ "1.483328, 1.483297, 1.483098, 1.482941, 1.482729",\
+ "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\
+ "0.059304, 0.059302, 0.059288, 0.059276, 0.059261",\
+ "0.131695, 0.131694, 0.131680, 0.131668, 0.131651",\
+ "0.419116, 0.419122, 0.419145, 0.419267, 0.419547",\
+ "1.483325, 1.483297, 1.483097, 1.482941, 1.482729",\
+ "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\
+ "0.059305, 0.059302, 0.059288, 0.059276, 0.059260",\
+ "0.131696, 0.131694, 0.131680, 0.131668, 0.131651",\
+ "0.419115, 0.419122, 0.419145, 0.419267, 0.419548",\
+ "1.483327, 1.483296, 1.483097, 1.482941, 1.482728");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2593*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[20]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.254656, 0.491006, 0.681199, 0.986728, 1.577708",\
+ "0.288244, 0.524620, 0.714843, 1.020374, 1.611331",\
+ "0.359123, 0.595519, 0.785873, 1.091419, 1.682284",\
+ "0.614167, 0.850282, 1.040808, 1.346411, 1.937248",\
+ "1.539512, 1.774279, 1.968056, 2.274137, 2.863164",\
+ "0.343150, 0.578325, 0.768480, 1.074033, 1.665062",\
+ "0.376740, 0.611939, 0.802124, 1.107679, 1.698684",\
+ "0.447618, 0.682838, 0.873154, 1.178725, 1.769638",\
+ "0.702665, 0.937601, 1.128089, 1.433716, 2.024602",\
+ "1.628026, 1.861597, 2.055336, 2.361442, 2.950518",\
+ "0.432477, 0.658660, 0.848507, 1.154062, 1.745093",\
+ "0.466070, 0.692274, 0.882150, 1.187708, 1.778716",\
+ "0.536949, 0.763173, 0.953181, 1.258753, 1.849669",\
+ "0.792003, 1.017936, 1.208116, 1.513744, 2.104633",\
+ "1.717412, 1.941932, 2.135364, 2.441470, 3.030550",\
+ "0.495969, 0.716495, 0.906228, 1.211528, 1.802181",\
+ "0.529564, 0.750109, 0.939872, 1.245174, 1.835804",\
+ "0.600443, 0.821007, 1.010903, 1.316219, 1.906757",\
+ "0.855505, 1.075769, 1.265838, 1.571210, 2.161721",\
+ "1.780957, 1.999760, 2.193094, 2.498934, 3.087633",\
+ "0.831401, 1.021856, 1.209889, 1.514732, 2.104490",\
+ "0.865014, 1.055469, 1.243533, 1.548377, 2.138113",\
+ "0.935893, 1.126362, 1.314564, 1.619422, 2.209066",\
+ "1.191001, 1.381117, 1.569499, 1.874413, 2.464029",\
+ "2.116730, 2.305066, 2.496756, 2.802135, 3.389936");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069342, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685011, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454035, 2.454504, 2.455152",\
+ "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069342, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685011, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454035, 2.454504, 2.455152",\
+ "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069342, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685011, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454035, 2.454504, 2.455152",\
+ "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454036, 2.454505, 2.455154",\
+ "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\
+ "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\
+ "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\
+ "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\
+ "2.453468, 2.453468, 2.454036, 2.454506, 2.455156");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.249454, 0.486004, 0.675967, 0.981250, 1.571825",\
+ "0.281865, 0.518328, 0.708344, 1.013662, 1.604275",\
+ "0.332260, 0.568655, 0.758650, 1.063988, 1.654672",\
+ "0.493098, 0.729544, 0.919296, 1.224627, 1.815523",\
+ "1.073988, 1.310152, 1.500044, 1.805268, 2.395687",\
+ "0.337933, 0.573322, 0.763248, 1.068555, 1.659178",\
+ "0.370344, 0.605646, 0.795625, 1.100967, 1.691628",\
+ "0.420740, 0.655974, 0.845931, 1.151293, 1.742025",\
+ "0.581582, 0.816862, 1.006577, 1.311932, 1.902877",\
+ "1.162485, 1.397470, 1.587325, 1.892573, 2.483041",\
+ "0.427218, 0.653657, 0.843275, 1.148583, 1.739210",\
+ "0.459630, 0.685981, 0.875652, 1.180995, 1.771660",\
+ "0.510027, 0.736309, 0.925958, 1.231322, 1.822057",\
+ "0.670883, 0.897197, 1.086604, 1.391961, 1.982908",\
+ "1.251823, 1.477805, 1.667352, 1.972602, 2.563072",\
+ "0.490671, 0.711493, 0.900996, 1.206049, 1.796297",\
+ "0.523083, 0.743816, 0.933373, 1.238461, 1.828747",\
+ "0.573482, 0.794144, 0.983679, 1.288787, 1.879144",\
+ "0.734351, 0.955034, 1.144324, 1.449427, 2.039996",\
+ "1.315324, 1.535635, 1.725073, 2.030067, 2.620159",\
+ "0.825858, 1.016851, 1.204656, 1.509252, 2.098604",\
+ "0.858274, 1.049176, 1.237034, 1.541664, 2.131054",\
+ "0.908682, 1.099504, 1.287340, 1.591990, 2.181452",\
+ "1.069631, 1.260400, 1.447985, 1.752630, 2.342305",\
+ "1.650816, 1.840953, 2.028734, 2.333270, 2.922466");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417989, 0.418302",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\
+ "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417989, 0.418302",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\
+ "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417989, 0.418302",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\
+ "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\
+ "0.030092, 0.030092, 0.030092, 0.030170, 0.030364",\
+ "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\
+ "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\
+ "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\
+ "1.478309, 1.478309, 1.478309, 1.478309, 1.478309");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2636*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[21]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.325472, 0.549886, 0.736679, 1.035269, 1.612348",\
+ "0.359026, 0.583502, 0.770294, 1.068882, 1.645956",\
+ "0.430054, 0.654527, 0.841316, 1.139890, 1.716933",\
+ "0.684897, 0.909477, 1.096261, 1.394816, 1.971817",\
+ "1.609849, 1.835494, 2.022258, 2.320729, 2.897541",\
+ "0.413759, 0.637204, 0.823960, 1.122574, 1.699702",\
+ "0.447318, 0.670820, 0.857575, 1.156187, 1.733310",\
+ "0.518346, 0.741845, 0.928597, 1.227195, 1.804287",\
+ "0.773189, 0.996795, 1.183542, 1.482121, 2.059171",\
+ "1.698136, 1.922812, 2.109539, 2.408034, 2.984894",\
+ "0.503271, 0.717533, 0.903987, 1.202602, 1.779733",\
+ "0.536839, 0.751148, 0.937602, 1.236216, 1.813341",\
+ "0.607869, 0.822173, 1.008624, 1.307223, 1.884319",\
+ "0.862712, 1.077123, 1.263569, 1.562150, 2.139202",\
+ "1.787644, 2.003140, 2.189566, 2.488062, 3.064926",\
+ "0.567278, 0.775354, 0.961702, 1.260053, 1.836791",\
+ "0.600857, 0.808970, 0.995318, 1.293666, 1.870399",\
+ "0.671888, 0.879995, 1.066339, 1.364674, 1.941376",\
+ "0.926731, 1.134945, 1.321284, 1.619600, 2.196259",\
+ "1.851648, 2.060962, 2.247281, 2.545512, 3.121983",\
+ "0.902611, 1.080594, 1.265360, 1.563241, 2.139063",\
+ "0.936228, 1.114210, 1.298975, 1.596854, 2.172671",\
+ "1.007260, 1.185235, 1.369997, 1.667862, 2.243648",\
+ "1.262219, 1.440184, 1.624942, 1.922788, 2.498532",\
+ "2.188276, 2.366200, 2.550939, 2.848700, 3.424254");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\
+ "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\
+ "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\
+ "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\
+ "2.446848, 2.446711, 2.446702, 2.446700, 2.446699",\
+ "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\
+ "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\
+ "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\
+ "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\
+ "2.446844, 2.446711, 2.446702, 2.446700, 2.446699",\
+ "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\
+ "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\
+ "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\
+ "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\
+ "2.446834, 2.446711, 2.446702, 2.446700, 2.446699",\
+ "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\
+ "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\
+ "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\
+ "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\
+ "2.446823, 2.446710, 2.446702, 2.446700, 2.446699",\
+ "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\
+ "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\
+ "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\
+ "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\
+ "2.446830, 2.446707, 2.446702, 2.446700, 2.446699");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.319701, 0.545442, 0.732220, 1.030751, 1.607697",\
+ "0.352039, 0.577906, 0.764685, 1.063221, 1.640180",\
+ "0.402393, 0.628225, 0.815004, 1.113542, 1.690503",\
+ "0.563471, 0.788964, 0.975744, 1.274281, 1.851241",\
+ "1.144048, 1.371915, 1.558729, 1.857404, 2.434677",\
+ "0.407993, 0.632759, 0.819501, 1.118056, 1.695051",\
+ "0.440331, 0.665224, 0.851966, 1.150527, 1.727533",\
+ "0.490684, 0.715542, 0.902285, 1.200847, 1.777857",\
+ "0.651763, 0.876282, 1.063025, 1.361586, 1.938595",\
+ "1.232329, 1.459233, 1.646010, 1.944710, 2.522030",\
+ "0.497516, 0.713088, 0.899528, 1.198085, 1.775082",\
+ "0.529855, 0.745552, 0.931993, 1.230555, 1.807565",\
+ "0.580208, 0.795871, 0.982312, 1.280875, 1.857888",\
+ "0.741286, 0.956611, 1.143052, 1.441614, 2.018626",\
+ "1.321819, 1.539562, 1.726037, 2.024738, 2.602062",\
+ "0.561534, 0.770909, 0.957244, 1.255535, 1.832140",\
+ "0.593874, 0.803374, 0.989709, 1.288005, 1.864622",\
+ "0.644226, 0.853692, 1.040028, 1.338326, 1.914946",\
+ "0.805304, 1.014432, 1.200767, 1.499064, 2.075684",\
+ "1.385806, 1.597383, 1.783752, 2.082189, 2.659120",\
+ "0.898194, 1.076148, 1.260901, 1.558723, 2.134412",\
+ "0.930657, 1.108613, 1.293366, 1.591193, 2.166894",\
+ "0.980975, 1.158931, 1.343685, 1.641514, 2.217218",\
+ "1.141715, 1.319671, 1.504425, 1.802253, 2.377955",\
+ "1.724358, 1.902624, 2.087410, 2.385377, 2.961392");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\
+ "0.059314, 0.059250, 0.059241, 0.059238, 0.059238",\
+ "0.131704, 0.131646, 0.131637, 0.131633, 0.131629",\
+ "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\
+ "1.483458, 1.482592, 1.482500, 1.482470, 1.482449",\
+ "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\
+ "0.059313, 0.059250, 0.059241, 0.059238, 0.059238",\
+ "0.131703, 0.131646, 0.131637, 0.131633, 0.131629",\
+ "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\
+ "1.483437, 1.482592, 1.482500, 1.482470, 1.482449",\
+ "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\
+ "0.059308, 0.059250, 0.059241, 0.059238, 0.059238",\
+ "0.131698, 0.131646, 0.131637, 0.131633, 0.131629",\
+ "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\
+ "1.483369, 1.482592, 1.482500, 1.482470, 1.482449",\
+ "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\
+ "0.059303, 0.059250, 0.059241, 0.059238, 0.059238",\
+ "0.131694, 0.131646, 0.131637, 0.131633, 0.131629",\
+ "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\
+ "1.483305, 1.482589, 1.482500, 1.482470, 1.482449",\
+ "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\
+ "0.059306, 0.059248, 0.059241, 0.059238, 0.059238",\
+ "0.131697, 0.131645, 0.131637, 0.131633, 0.131629",\
+ "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\
+ "1.482893, 1.482566, 1.482500, 1.482470, 1.482448");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2688*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[25]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.402084, 0.617885, 0.797210, 1.086950, 1.648801",\
+ "0.443807, 0.659608, 0.838933, 1.128673, 1.690524",\
+ "0.519872, 0.735673, 0.914998, 1.204739, 1.766590",\
+ "0.775363, 0.991161, 1.170488, 1.460228, 2.022074",\
+ "1.699671, 1.915471, 2.094797, 2.384537, 2.946387",\
+ "0.490367, 0.705202, 0.884491, 1.174255, 1.736155",\
+ "0.532090, 0.746925, 0.926214, 1.215978, 1.777877",\
+ "0.608155, 0.822991, 1.002279, 1.292044, 1.853944",\
+ "0.863645, 1.078479, 1.257769, 1.547533, 2.109427",\
+ "1.787954, 2.002789, 2.182077, 2.471842, 3.033741",\
+ "0.579657, 0.785533, 0.964518, 1.254284, 1.816186",\
+ "0.621380, 0.827256, 1.006241, 1.296007, 1.857909",\
+ "0.697445, 0.903322, 1.082306, 1.372073, 1.933975",\
+ "0.952935, 1.158809, 1.337796, 1.627561, 2.189459",\
+ "1.877244, 2.083119, 2.262105, 2.551871, 3.113772",\
+ "0.643368, 0.843363, 1.022215, 1.311715, 1.873206",\
+ "0.685091, 0.885086, 1.063938, 1.353438, 1.914929",\
+ "0.761157, 0.961152, 1.140003, 1.429504, 1.990995",\
+ "1.016647, 1.216639, 1.395493, 1.684993, 2.246479",\
+ "1.940955, 2.140950, 2.319802, 2.609302, 3.170792",\
+ "0.967924, 1.148670, 1.325870, 1.614888, 2.175433",\
+ "1.009647, 1.190393, 1.367593, 1.656611, 2.217156",\
+ "1.085713, 1.266459, 1.443658, 1.732677, 2.293222",\
+ "1.341202, 1.521946, 1.699148, 1.988165, 2.548706",\
+ "2.265511, 2.446256, 2.623457, 2.912475, 3.473019");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\
+ "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\
+ "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\
+ "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\
+ "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\
+ "2.452523, 2.452519, 2.452519, 2.452513, 2.452498");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.424674, 0.640474, 0.819800, 1.109540, 1.671391",\
+ "0.456699, 0.672499, 0.851824, 1.141565, 1.703415",\
+ "0.507106, 0.722907, 0.902232, 1.191973, 1.753824",\
+ "0.668165, 0.883968, 1.063291, 1.353033, 1.914886",\
+ "1.248139, 1.463941, 1.643265, 1.933006, 2.494859",\
+ "0.512957, 0.727792, 0.907081, 1.196846, 1.758744",\
+ "0.544981, 0.759817, 0.939105, 1.228870, 1.790768",\
+ "0.595389, 0.810225, 0.989513, 1.279278, 1.841177",\
+ "0.756448, 0.971285, 1.150572, 1.440338, 2.002240",\
+ "1.336421, 1.551259, 1.730546, 2.020311, 2.582213",\
+ "0.602247, 0.808123, 0.987108, 1.276874, 1.838776",\
+ "0.634272, 0.840147, 1.019132, 1.308898, 1.870800",\
+ "0.684679, 0.890556, 1.069540, 1.359307, 1.921209",\
+ "0.845739, 1.051616, 1.230599, 1.520366, 2.082271",\
+ "1.425712, 1.631589, 1.810572, 2.100339, 2.662244",\
+ "0.665958, 0.865953, 1.044805, 1.334306, 1.895796",\
+ "0.697983, 0.897977, 1.076829, 1.366330, 1.927820",\
+ "0.748391, 0.948386, 1.127237, 1.416738, 1.978229",\
+ "0.909450, 1.109446, 1.288296, 1.577798, 2.139291",\
+ "1.489423, 1.689419, 1.868270, 2.157771, 2.719264",\
+ "0.990514, 1.171260, 1.348460, 1.637478, 2.198022",\
+ "1.022539, 1.203284, 1.380485, 1.669502, 2.230046",\
+ "1.072946, 1.253692, 1.430892, 1.719911, 2.280456",\
+ "1.234006, 1.414753, 1.591951, 1.880970, 2.441518",\
+ "1.813979, 1.994726, 2.171925, 2.460944, 3.021491");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\
+ "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\
+ "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\
+ "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\
+ "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\
+ "1.484515, 1.484514, 1.484514, 1.484513, 1.484510");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2386*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[28]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.556345, 0.776897, 0.954428, 1.243066, 1.803585",\
+ "0.598041, 0.818593, 0.996124, 1.284762, 1.845281",\
+ "0.674223, 0.894775, 1.072306, 1.360943, 1.921462",\
+ "0.929618, 1.150170, 1.327701, 1.616339, 2.176858",\
+ "1.853996, 2.074548, 2.252079, 2.540716, 3.101235",\
+ "0.644757, 0.864215, 1.041709, 1.330371, 1.890938",\
+ "0.686453, 0.905912, 1.083405, 1.372067, 1.932634",\
+ "0.762635, 0.982093, 1.159587, 1.448249, 2.008816",\
+ "1.018030, 1.237489, 1.414982, 1.703644, 2.264211",\
+ "1.942408, 2.161866, 2.339360, 2.628021, 3.188588",\
+ "0.733857, 0.944551, 1.121736, 1.410399, 1.970970",\
+ "0.775553, 0.986247, 1.163432, 1.452096, 2.012666",\
+ "0.851735, 1.062428, 1.239614, 1.528277, 2.088847",\
+ "1.107130, 1.317824, 1.495009, 1.783673, 2.344243",\
+ "2.031507, 2.242201, 2.419386, 2.708050, 3.268620",\
+ "0.797144, 1.002367, 1.179428, 1.467829, 2.027984",\
+ "0.838840, 1.044064, 1.221124, 1.509525, 2.069680",\
+ "0.915021, 1.120245, 1.297306, 1.585706, 2.145862",\
+ "1.170417, 1.375641, 1.552701, 1.841102, 2.401258",\
+ "2.094794, 2.300018, 2.477078, 2.765479, 3.325634",\
+ "1.128157, 1.307597, 1.483084, 1.771000, 2.330204",\
+ "1.169853, 1.349293, 1.524780, 1.812697, 2.371901",\
+ "1.246035, 1.425474, 1.600962, 1.888878, 2.448082",\
+ "1.501431, 1.680870, 1.856357, 2.144274, 2.703477",\
+ "2.425808, 2.605247, 2.780735, 3.068651, 3.627855");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.576590, 0.797142, 0.974673, 1.263311, 1.823830",\
+ "0.608840, 0.829392, 1.006923, 1.295561, 1.856079",\
+ "0.659152, 0.879704, 1.057235, 1.345873, 1.906392",\
+ "0.819816, 1.040368, 1.217899, 1.506536, 2.067055",\
+ "1.400950, 1.621502, 1.799033, 2.087670, 2.648189",\
+ "0.665002, 0.884461, 1.061954, 1.350616, 1.911183",\
+ "0.697252, 0.916710, 1.094204, 1.382866, 1.943433",\
+ "0.747564, 0.967022, 1.144516, 1.433178, 1.993745",\
+ "0.908228, 1.127686, 1.305180, 1.593842, 2.154409",\
+ "1.489362, 1.708820, 1.886313, 2.174975, 2.735543",\
+ "0.754102, 0.964796, 1.141981, 1.430644, 1.991215",\
+ "0.786352, 0.997045, 1.174231, 1.462894, 2.023464",\
+ "0.836664, 1.047358, 1.224543, 1.513206, 2.073777",\
+ "0.997328, 1.208021, 1.385207, 1.673870, 2.234440",\
+ "1.578462, 1.789155, 1.966340, 2.255004, 2.815574",\
+ "0.817389, 1.022612, 1.199673, 1.488074, 2.048229",\
+ "0.849638, 1.054862, 1.231923, 1.520324, 2.080479",\
+ "0.899951, 1.105174, 1.282235, 1.570636, 2.130791",\
+ "1.060614, 1.265838, 1.442899, 1.731299, 2.291455",\
+ "1.641748, 1.846972, 2.024032, 2.312433, 2.872589",\
+ "1.148402, 1.327842, 1.503329, 1.791245, 2.350449",\
+ "1.180652, 1.360092, 1.535579, 1.823495, 2.382699",\
+ "1.230964, 1.410404, 1.585891, 1.873807, 2.433011",\
+ "1.391628, 1.571068, 1.746555, 2.034471, 2.593675",\
+ "1.972762, 2.152201, 2.327689, 2.615605, 3.174809");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[29]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.538673, 0.779387, 0.972430, 1.279750, 1.873102",\
+ "0.580369, 0.821084, 1.014127, 1.321447, 1.914798",\
+ "0.656550, 0.897265, 1.090308, 1.397628, 1.990980",\
+ "0.911946, 1.152661, 1.345703, 1.653024, 2.246375",\
+ "1.836323, 2.077038, 2.270081, 2.577401, 3.170752",\
+ "0.626961, 0.866705, 1.059711, 1.367055, 1.960455",\
+ "0.668657, 0.908401, 1.101408, 1.408752, 2.002152",\
+ "0.744839, 0.984583, 1.177589, 1.484933, 2.078333",\
+ "1.000234, 1.239979, 1.432984, 1.740329, 2.333729",\
+ "1.924612, 2.164356, 2.357362, 2.664706, 3.258105",\
+ "0.716276, 0.947035, 1.139738, 1.447084, 2.040487",\
+ "0.757973, 0.988732, 1.181434, 1.488780, 2.082183",\
+ "0.834154, 1.064913, 1.257616, 1.564962, 2.158365",\
+ "1.089550, 1.320309, 1.513011, 1.820357, 2.413760",\
+ "2.013927, 2.244686, 2.437389, 2.744734, 3.338137",\
+ "0.780015, 1.004896, 1.197467, 1.504554, 2.097583",\
+ "0.821712, 1.046593, 1.239163, 1.546250, 2.139279",\
+ "0.897893, 1.122774, 1.315345, 1.622432, 2.215461",\
+ "1.153289, 1.378170, 1.570740, 1.877827, 2.470857",\
+ "2.077666, 2.302547, 2.495118, 2.802204, 3.395233",\
+ "1.117001, 1.310416, 1.501127, 1.807759, 2.399902",\
+ "1.158697, 1.352113, 1.542824, 1.849456, 2.441598",\
+ "1.234879, 1.428294, 1.619005, 1.925637, 2.517779",\
+ "1.490274, 1.683690, 1.874401, 2.181033, 2.773175",\
+ "2.414652, 2.608067, 2.798778, 3.105409, 3.697551");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\
+ "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\
+ "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455201");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.558918, 0.799632, 0.992675, 1.299995, 1.893347",\
+ "0.591168, 0.831882, 1.024925, 1.332245, 1.925597",\
+ "0.641480, 0.882194, 1.075237, 1.382557, 1.975909",\
+ "0.802143, 1.042858, 1.235901, 1.543221, 2.136573",\
+ "1.383277, 1.623992, 1.817035, 2.124355, 2.717707",\
+ "0.647206, 0.886950, 1.079956, 1.387300, 1.980700",\
+ "0.679456, 0.919200, 1.112206, 1.419550, 2.012950",\
+ "0.729768, 0.969512, 1.162518, 1.469862, 2.063262",\
+ "0.890432, 1.130176, 1.323182, 1.630526, 2.223926",\
+ "1.471565, 1.711310, 1.904316, 2.211660, 2.805060",\
+ "0.736521, 0.967281, 1.159983, 1.467329, 2.060732",\
+ "0.768771, 0.999530, 1.192233, 1.499579, 2.092982",\
+ "0.819083, 1.049842, 1.242545, 1.549891, 2.143294",\
+ "0.979747, 1.210506, 1.403209, 1.710555, 2.303958",\
+ "1.560881, 1.791640, 1.984343, 2.291688, 2.885092",\
+ "0.800261, 1.025141, 1.217712, 1.524799, 2.117828",\
+ "0.832510, 1.057391, 1.249962, 1.557049, 2.150078",\
+ "0.882822, 1.107703, 1.300274, 1.607361, 2.200390",\
+ "1.043486, 1.268367, 1.460938, 1.768024, 2.361054",\
+ "1.624620, 1.849501, 2.042072, 2.349159, 2.942188",\
+ "1.137246, 1.330662, 1.521373, 1.828004, 2.420147",\
+ "1.169496, 1.362911, 1.553622, 1.860254, 2.452396",\
+ "1.219808, 1.413224, 1.603935, 1.910566, 2.502709",\
+ "1.380472, 1.573887, 1.764598, 2.071230, 2.663373",\
+ "1.961606, 2.155021, 2.345732, 2.652364, 3.244506");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\
+ "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\
+ "1.482976, 1.482976, 1.482976, 1.482976, 1.482976");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2306*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[32]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.454515, 0.687556, 0.876637, 1.181062, 1.770586",\
+ "0.496240, 0.729281, 0.918362, 1.222787, 1.812311",\
+ "0.572297, 0.805339, 0.994419, 1.298844, 1.888368",\
+ "0.827855, 1.060896, 1.249979, 1.554404, 2.143927",\
+ "1.752113, 1.985154, 2.174236, 2.478661, 3.068184",\
+ "0.542959, 0.774874, 0.963918, 1.268367, 1.857939",\
+ "0.584684, 0.816599, 1.005643, 1.310092, 1.899664",\
+ "0.660741, 0.892656, 1.081700, 1.386149, 1.975721",\
+ "0.916299, 1.148213, 1.337260, 1.641709, 2.231281",\
+ "1.840557, 2.072472, 2.261517, 2.565966, 3.155538",\
+ "0.633029, 0.855201, 1.043945, 1.348395, 1.937971",\
+ "0.674754, 0.896927, 1.085670, 1.390121, 1.979696",\
+ "0.750812, 0.972984, 1.161727, 1.466178, 2.055753",\
+ "1.006370, 1.228541, 1.417287, 1.721738, 2.311312",\
+ "1.930628, 2.152800, 2.341543, 2.645994, 3.235569",\
+ "0.697606, 0.913035, 1.101665, 1.405861, 1.995059",\
+ "0.739331, 0.954761, 1.143391, 1.447586, 2.036784",\
+ "0.815389, 1.030818, 1.219448, 1.523643, 2.112841",\
+ "1.070947, 1.286375, 1.475007, 1.779203, 2.368400",\
+ "1.995205, 2.210634, 2.399264, 2.703460, 3.292657",\
+ "1.037719, 1.218357, 1.405324, 1.709062, 2.297368",\
+ "1.079444, 1.260083, 1.447049, 1.750787, 2.339093",\
+ "1.155501, 1.336140, 1.523106, 1.826844, 2.415150",\
+ "1.411059, 1.591697, 1.778666, 2.082405, 2.670709",\
+ "2.335317, 2.515956, 2.702923, 3.006661, 3.594966");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452470, 2.452462, 2.452462, 2.452446, 2.452406",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\
+ "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\
+ "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\
+ "2.452470, 2.452462, 2.452462, 2.452446, 2.452406");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.477114, 0.710155, 0.899236, 1.203661, 1.793185",\
+ "0.509144, 0.742185, 0.931266, 1.235691, 1.825215",\
+ "0.559532, 0.792574, 0.981654, 1.286079, 1.875603",\
+ "0.720561, 0.953603, 1.142682, 1.447107, 2.036631",\
+ "1.300536, 1.533577, 1.722657, 2.027082, 2.616606",\
+ "0.565558, 0.797473, 0.986517, 1.290966, 1.880538",\
+ "0.597588, 0.829503, 1.018547, 1.322996, 1.912568",\
+ "0.647976, 0.879891, 1.068935, 1.373384, 1.962957",\
+ "0.809005, 1.040920, 1.229963, 1.534412, 2.123985",\
+ "1.388980, 1.620895, 1.809938, 2.114387, 2.703959",\
+ "0.655628, 0.877800, 1.066544, 1.370995, 1.960570",\
+ "0.687658, 0.909830, 1.098574, 1.403025, 1.992600",\
+ "0.738047, 0.960219, 1.148962, 1.453413, 2.042988",\
+ "0.899075, 1.121248, 1.309990, 1.614440, 2.204016",\
+ "1.479050, 1.701223, 1.889965, 2.194416, 2.783991",\
+ "0.720205, 0.935634, 1.124265, 1.428460, 2.017658",\
+ "0.752235, 0.967664, 1.156295, 1.460490, 2.049688",\
+ "0.802624, 1.018053, 1.206683, 1.510878, 2.100076",\
+ "0.963652, 1.179082, 1.367711, 1.671906, 2.261104",\
+ "1.543628, 1.759057, 1.947685, 2.251881, 2.841079",\
+ "1.060318, 1.240956, 1.427923, 1.731662, 2.319967",\
+ "1.092348, 1.272986, 1.459953, 1.763692, 2.351997",\
+ "1.142736, 1.323375, 1.510341, 1.814080, 2.402385",\
+ "1.303765, 1.484404, 1.671369, 1.975107, 2.563413",\
+ "1.883740, 2.064379, 2.251344, 2.555082, 3.143388");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\
+ "1.484505, 1.484504, 1.484504, 1.484501, 1.484493");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2463*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[38]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.490508, 0.711036, 0.888618, 1.176984, 1.736809",\
+ "0.532203, 0.752732, 0.930314, 1.218679, 1.778504",\
+ "0.608383, 0.828912, 1.006494, 1.294859, 1.854684",\
+ "0.863773, 1.084302, 1.261884, 1.550249, 2.110074",\
+ "1.788229, 2.008758, 2.186340, 2.474705, 3.034531",\
+ "0.578896, 0.798355, 0.975899, 1.264289, 1.824162",\
+ "0.620592, 0.840050, 1.017595, 1.305984, 1.865858",\
+ "0.696772, 0.916230, 1.093775, 1.382164, 1.942038",\
+ "0.952161, 1.171620, 1.349165, 1.637554, 2.197427",\
+ "1.876618, 2.096076, 2.273621, 2.562011, 3.121884",\
+ "0.668261, 0.878687, 1.055926, 1.344317, 1.904194",\
+ "0.709957, 0.920382, 1.097622, 1.386013, 1.945889",\
+ "0.786137, 0.996562, 1.173802, 1.462193, 2.022069",\
+ "1.041527, 1.251952, 1.429191, 1.717583, 2.277459",\
+ "1.965983, 2.176409, 2.353648, 2.642039, 3.201916",\
+ "0.731942, 0.936503, 1.113619, 1.401746, 1.961208",\
+ "0.773637, 0.978198, 1.155315, 1.443442, 2.002903",\
+ "0.849817, 1.054379, 1.231495, 1.519622, 2.079083",\
+ "1.105207, 1.309768, 1.486884, 1.775012, 2.334473",\
+ "2.029663, 2.234225, 2.411341, 2.699468, 3.258930",\
+ "1.063585, 1.241717, 1.417274, 1.704917, 2.263427",\
+ "1.105281, 1.283412, 1.458970, 1.746613, 2.305123",\
+ "1.181460, 1.359592, 1.535150, 1.822793, 2.381303",\
+ "1.436850, 1.614982, 1.790540, 2.078182, 2.636693",\
+ "2.361307, 2.539439, 2.714996, 3.002639, 3.561149");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.510756, 0.731284, 0.908866, 1.197232, 1.757056",\
+ "0.543002, 0.763530, 0.941112, 1.229478, 1.789302",\
+ "0.593318, 0.813846, 0.991428, 1.279794, 1.839619",\
+ "0.753982, 0.974510, 1.152092, 1.440458, 2.000283",\
+ "1.335097, 1.555626, 1.733208, 2.021573, 2.581398",\
+ "0.599144, 0.818602, 0.996147, 1.284537, 1.844410",\
+ "0.631390, 0.850848, 1.028393, 1.316783, 1.876656",\
+ "0.681706, 0.901165, 1.078709, 1.367099, 1.926972",\
+ "0.842370, 1.061828, 1.239373, 1.527763, 2.087636",\
+ "1.423486, 1.642944, 1.820489, 2.108878, 2.668751",\
+ "0.688509, 0.898935, 1.076174, 1.364565, 1.924441",\
+ "0.720755, 0.931181, 1.108420, 1.396811, 1.956687",\
+ "0.771071, 0.981497, 1.158736, 1.447127, 2.007004",\
+ "0.931735, 1.142161, 1.319400, 1.607791, 2.167668",\
+ "1.512851, 1.723276, 1.900516, 2.188907, 2.748783",\
+ "0.752190, 0.956751, 1.133867, 1.421994, 1.981456",\
+ "0.784436, 0.988997, 1.166113, 1.454240, 2.013701",\
+ "0.834752, 1.039313, 1.216429, 1.504556, 2.064018",\
+ "0.995416, 1.199977, 1.377093, 1.665220, 2.224682",\
+ "1.576531, 1.781092, 1.958208, 2.246336, 2.805797",\
+ "1.083833, 1.261965, 1.437522, 1.725165, 2.283675",\
+ "1.116079, 1.294211, 1.469768, 1.757411, 2.315921",\
+ "1.166395, 1.344527, 1.520084, 1.807727, 2.366237",\
+ "1.327059, 1.505191, 1.680748, 1.968391, 2.526901",\
+ "1.908174, 2.086306, 2.261864, 2.549506, 3.108017");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2279*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[39]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.464141, 0.703934, 0.888128, 1.182401, 1.751067",\
+ "0.505836, 0.745630, 0.929824, 1.224097, 1.792763",\
+ "0.582016, 0.821810, 1.006004, 1.300277, 1.868943",\
+ "0.837406, 1.077200, 1.261394, 1.555666, 2.124333",\
+ "1.761863, 2.001656, 2.185850, 2.480123, 3.048789",\
+ "0.552479, 0.791253, 0.975409, 1.269706, 1.838421",\
+ "0.594175, 0.832948, 1.017105, 1.311402, 1.880116",\
+ "0.670355, 0.909128, 1.093285, 1.387582, 1.956296",\
+ "0.925745, 1.164518, 1.348675, 1.642971, 2.211686",\
+ "1.850201, 2.088974, 2.273131, 2.567428, 3.136143",\
+ "0.641618, 0.871586, 1.055436, 1.349735, 1.918452",\
+ "0.683313, 0.913281, 1.097132, 1.391430, 1.960148",\
+ "0.759493, 0.989461, 1.173312, 1.467610, 2.036328",\
+ "1.014883, 1.244851, 1.428701, 1.723000, 2.291718",\
+ "1.939340, 2.169307, 2.353158, 2.647456, 3.216174",\
+ "0.705051, 0.929417, 1.113144, 1.407174, 1.975487",\
+ "0.746746, 0.971112, 1.154840, 1.448870, 2.017183",\
+ "0.822926, 1.047292, 1.231020, 1.525050, 2.093363",\
+ "1.078316, 1.302682, 1.486409, 1.780439, 2.348753",\
+ "2.002773, 2.227139, 2.410866, 2.704896, 3.273209",\
+ "1.040106, 1.234739, 1.416802, 1.710354, 2.277733",\
+ "1.081802, 1.276435, 1.458498, 1.752050, 2.319428",\
+ "1.157982, 1.352615, 1.534678, 1.828230, 2.395608",\
+ "1.413371, 1.608004, 1.790067, 2.083619, 2.650998",\
+ "2.337828, 2.532461, 2.714524, 3.008076, 3.575455");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\
+ "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\
+ "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\
+ "2.455194, 2.455194, 2.455194, 2.455194, 2.455194");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.484389, 0.724182, 0.908376, 1.202649, 1.771315",\
+ "0.516635, 0.756428, 0.940622, 1.234895, 1.803561",\
+ "0.566951, 0.806745, 0.990938, 1.285211, 1.853878",\
+ "0.727615, 0.967409, 1.151602, 1.445875, 2.014541",\
+ "1.308730, 1.548524, 1.732718, 2.026990, 2.595657",\
+ "0.572727, 0.811501, 0.995657, 1.289954, 1.858669",\
+ "0.604973, 0.843747, 1.027903, 1.322200, 1.890915",\
+ "0.655290, 0.894063, 1.078219, 1.372516, 1.941231",\
+ "0.815953, 1.054727, 1.238883, 1.533180, 2.101895",\
+ "1.397069, 1.635842, 1.819999, 2.114295, 2.683010",\
+ "0.661866, 0.891834, 1.075684, 1.369982, 1.938700",\
+ "0.694112, 0.924080, 1.107930, 1.402228, 1.970946",\
+ "0.744428, 0.974396, 1.158246, 1.452545, 2.021263",\
+ "0.905092, 1.135060, 1.318910, 1.613209, 2.181926",\
+ "1.486207, 1.716175, 1.900026, 2.194324, 2.763042",\
+ "0.725299, 0.949665, 1.133392, 1.427422, 1.995735",\
+ "0.757545, 0.981911, 1.165638, 1.459668, 2.027981",\
+ "0.807861, 1.032227, 1.215954, 1.509984, 2.078298",\
+ "0.968525, 1.192891, 1.376618, 1.670648, 2.238961",\
+ "1.549640, 1.774006, 1.957734, 2.251764, 2.820077",\
+ "1.060354, 1.254987, 1.437050, 1.730602, 2.297981",\
+ "1.092600, 1.287233, 1.469296, 1.762848, 2.330226",\
+ "1.142916, 1.337549, 1.519612, 1.813164, 2.380543",\
+ "1.303580, 1.498213, 1.680276, 1.973828, 2.541207",\
+ "1.884696, 2.079328, 2.261392, 2.554944, 3.122322");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\
+ "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\
+ "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\
+ "1.483052, 1.483052, 1.483052, 1.483052, 1.483052");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2323*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[41]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.411437, 0.641763, 0.827440, 1.121826, 1.689429",\
+ "0.453163, 0.683488, 0.869165, 1.163551, 1.731154",\
+ "0.529220, 0.759545, 0.945221, 1.239608, 1.807211",\
+ "0.784777, 1.015107, 1.200787, 1.495173, 2.062773",\
+ "1.709036, 1.939362, 2.125040, 2.419426, 2.987028",\
+ "0.499750, 0.729081, 0.914721, 1.209131, 1.776782",\
+ "0.541475, 0.770807, 0.956446, 1.250857, 1.818508",\
+ "0.617533, 0.846863, 1.032502, 1.326913, 1.894564",\
+ "0.873090, 1.102426, 1.288068, 1.582478, 2.150126",\
+ "1.797349, 2.026680, 2.212321, 2.506731, 3.074381",\
+ "0.588895, 0.809414, 0.994747, 1.289160, 1.856814",\
+ "0.630620, 0.851139, 1.036473, 1.330885, 1.898539",\
+ "0.706677, 0.927196, 1.112529, 1.406941, 1.974596",\
+ "0.962234, 1.182758, 1.368095, 1.662507, 2.230158",\
+ "1.886493, 2.107013, 2.292347, 2.586760, 3.154413",\
+ "0.652369, 0.867238, 1.052459, 1.346598, 1.913847",\
+ "0.694094, 0.908963, 1.094185, 1.388323, 1.955572",\
+ "0.770151, 0.985020, 1.170241, 1.464380, 2.031629",\
+ "1.025709, 1.240582, 1.425807, 1.719945, 2.287190",\
+ "1.949967, 2.164837, 2.350059, 2.644198, 3.211446",\
+ "0.987682, 1.172511, 1.356118, 1.649777, 2.216089",\
+ "1.029408, 1.214237, 1.397843, 1.691502, 2.257815",\
+ "1.105465, 1.290294, 1.473899, 1.767559, 2.333871",\
+ "1.361025, 1.545856, 1.729465, 2.023124, 2.589433",\
+ "2.285281, 2.470111, 2.653718, 2.947377, 3.513689");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\
+ "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\
+ "0.070222, 0.070222, 0.070221, 0.070221, 0.070221",\
+ "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\
+ "0.686585, 0.686583, 0.686578, 0.686576, 0.686576",\
+ "2.452462, 2.452462, 2.452462, 2.452450, 2.452422");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.434036, 0.664363, 0.850040, 1.144426, 1.712028",\
+ "0.466066, 0.696393, 0.882070, 1.176457, 1.744059",\
+ "0.516455, 0.746780, 0.932457, 1.226843, 1.794446",\
+ "0.677484, 0.907807, 1.093482, 1.387868, 1.955473",\
+ "1.257459, 1.487782, 1.673457, 1.967843, 2.535448",\
+ "0.522349, 0.751681, 0.937321, 1.231731, 1.799382",\
+ "0.554379, 0.783711, 0.969351, 1.263762, 1.831412",\
+ "0.604768, 0.834099, 1.019738, 1.314148, 1.881800",\
+ "0.765797, 0.995125, 1.180763, 1.475173, 2.042827",\
+ "1.345772, 1.575100, 1.760738, 2.055148, 2.622802",\
+ "0.611494, 0.832013, 1.017348, 1.311760, 1.879413",\
+ "0.643524, 0.864044, 1.049378, 1.343790, 1.911444",\
+ "0.693912, 0.914431, 1.099764, 1.394177, 1.961831",\
+ "0.854941, 1.075458, 1.260790, 1.555202, 2.122858",\
+ "1.434916, 1.655433, 1.840765, 2.135177, 2.702833",\
+ "0.674968, 0.889838, 1.075059, 1.369198, 1.936446",\
+ "0.706998, 0.921868, 1.107090, 1.401229, 1.968477",\
+ "0.757386, 0.972255, 1.157476, 1.451615, 2.018864",\
+ "0.918415, 1.133282, 1.318501, 1.612640, 2.179891",\
+ "1.498390, 1.713257, 1.898476, 2.192615, 2.759866",\
+ "1.010282, 1.195111, 1.378718, 1.672377, 2.238689",\
+ "1.042312, 1.227141, 1.410748, 1.704407, 2.270719",\
+ "1.092700, 1.277529, 1.461135, 1.754794, 2.321106",\
+ "1.253727, 1.438555, 1.622160, 1.915819, 2.482133",\
+ "1.833702, 2.018530, 2.202135, 2.495794, 3.062109");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\
+ "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\
+ "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\
+ "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\
+ "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\
+ "1.484504, 1.484504, 1.484504, 1.484501, 1.484496");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2346*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[46]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.554942, 0.776691, 0.954630, 1.243547, 1.804386",\
+ "0.596638, 0.818387, 0.996327, 1.285244, 1.846083",\
+ "0.672820, 0.894569, 1.072508, 1.361425, 1.922264",\
+ "0.928215, 1.149964, 1.327903, 1.616820, 2.177659",\
+ "1.852598, 2.074347, 2.252286, 2.541204, 3.102043",\
+ "0.643350, 0.864010, 1.041911, 1.330852, 1.891740",\
+ "0.685047, 0.905706, 1.083608, 1.372549, 1.933436",\
+ "0.761228, 0.981887, 1.159789, 1.448730, 2.009617",\
+ "1.016623, 1.237282, 1.415184, 1.704125, 2.265012",\
+ "1.941007, 2.161666, 2.339567, 2.628509, 3.189397",\
+ "0.732441, 0.944345, 1.121938, 1.410881, 1.971771",\
+ "0.774137, 0.986041, 1.163634, 1.452577, 2.013468",\
+ "0.850318, 1.062222, 1.239816, 1.528758, 2.089649",\
+ "1.105714, 1.317617, 1.495211, 1.784153, 2.345044",\
+ "2.030097, 2.242001, 2.419594, 2.708537, 3.269428",\
+ "0.795719, 1.002162, 1.179631, 1.468310, 2.028787",\
+ "0.837415, 1.043858, 1.221328, 1.510007, 2.070483",\
+ "0.913596, 1.120039, 1.297509, 1.586188, 2.146664",\
+ "1.168992, 1.375434, 1.552904, 1.841583, 2.402059",\
+ "2.093375, 2.299818, 2.477287, 2.765967, 3.326444",\
+ "1.127968, 1.307390, 1.483287, 1.771482, 2.331008",\
+ "1.169664, 1.349087, 1.524984, 1.813179, 2.372704",\
+ "1.245846, 1.425268, 1.601165, 1.889360, 2.448885",\
+ "1.501241, 1.680663, 1.856560, 2.144755, 2.704280",\
+ "2.425624, 2.605047, 2.780944, 3.069139, 3.628665");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\
+ "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\
+ "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\
+ "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\
+ "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\
+ "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.575187, 0.796936, 0.974876, 1.263793, 1.824632",\
+ "0.607437, 0.829186, 1.007125, 1.296042, 1.856881",\
+ "0.657749, 0.879498, 1.057438, 1.346354, 1.907194",\
+ "0.818413, 1.040162, 1.218101, 1.507018, 2.067857",\
+ "1.399546, 1.621294, 1.799234, 2.088151, 2.648989",\
+ "0.663596, 0.884255, 1.062156, 1.351098, 1.911985",\
+ "0.695845, 0.916504, 1.094406, 1.383347, 1.944234",\
+ "0.746158, 0.966817, 1.144718, 1.433660, 1.994547",\
+ "0.906821, 1.127481, 1.305382, 1.594323, 2.155211",\
+ "1.487954, 1.708613, 1.886515, 2.175456, 2.736343",\
+ "0.752686, 0.964590, 1.142183, 1.431126, 1.992017",\
+ "0.784936, 0.996840, 1.174433, 1.463375, 2.024266",\
+ "0.835248, 1.047152, 1.224745, 1.513688, 2.074579",\
+ "0.995912, 1.207816, 1.385409, 1.674352, 2.235242",\
+ "1.577044, 1.788948, 1.966541, 2.255484, 2.816375",\
+ "0.815964, 1.022407, 1.199876, 1.488556, 2.049032",\
+ "0.848214, 1.054656, 1.232126, 1.520805, 2.081281",\
+ "0.898526, 1.104969, 1.282438, 1.571118, 2.131594",\
+ "1.059190, 1.265632, 1.443102, 1.731781, 2.292258",\
+ "1.640322, 1.846765, 2.024235, 2.312914, 2.873390",\
+ "1.148213, 1.327636, 1.503533, 1.791728, 2.351253",\
+ "1.180463, 1.359885, 1.535782, 1.823977, 2.383502",\
+ "1.230775, 1.410198, 1.586095, 1.874290, 2.433815",\
+ "1.391439, 1.570861, 1.746758, 2.034954, 2.594479",\
+ "1.972571, 2.151994, 2.327891, 2.616086, 3.175611");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2465*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[47]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.533753, 0.762081, 0.946644, 1.241934, 1.812791",\
+ "0.575449, 0.803777, 0.988340, 1.283630, 1.854487",\
+ "0.651630, 0.879958, 1.064522, 1.359811, 1.930668",\
+ "0.907026, 1.135353, 1.319917, 1.615206, 2.186064",\
+ "1.831408, 2.059737, 2.244300, 2.539591, 3.110448",\
+ "0.622078, 0.849399, 1.033925, 1.329239, 1.900144",\
+ "0.663775, 0.891095, 1.075621, 1.370935, 1.941841",\
+ "0.739956, 0.967276, 1.151803, 1.447117, 2.018022",\
+ "0.995351, 1.222671, 1.407198, 1.702512, 2.273417",\
+ "1.919734, 2.147055, 2.331581, 2.626896, 3.197802",\
+ "0.711467, 0.929729, 1.113952, 1.409267, 1.980176",\
+ "0.753164, 0.971426, 1.155648, 1.450964, 2.021872",\
+ "0.829345, 1.047607, 1.231829, 1.527145, 2.098053",\
+ "1.084740, 1.303002, 1.487225, 1.782540, 2.353448",\
+ "2.009123, 2.227385, 2.411608, 2.706924, 3.277833",\
+ "0.775260, 0.987553, 1.171661, 1.466710, 2.037218",\
+ "0.816956, 1.029250, 1.213358, 1.508406, 2.078914",\
+ "0.893137, 1.105431, 1.289539, 1.584587, 2.155095",\
+ "1.148533, 1.360826, 1.544934, 1.839983, 2.410490",\
+ "2.072916, 2.285210, 2.469318, 2.764367, 3.334875",\
+ "1.112589, 1.292819, 1.475319, 1.769892, 2.339470",\
+ "1.154285, 1.334515, 1.517015, 1.811588, 2.381167",\
+ "1.230466, 1.410696, 1.593196, 1.887769, 2.457348",\
+ "1.485862, 1.666091, 1.848592, 2.143165, 2.712743",\
+ "2.410245, 2.590475, 2.772975, 3.067549, 3.637128");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\
+ "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\
+ "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\
+ "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\
+ "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\
+ "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\
+ "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\
+ "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\
+ "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\
+ "2.455201, 2.455201, 2.455201, 2.455201, 2.455200");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.553998, 0.782326, 0.966889, 1.262179, 1.833036",\
+ "0.586248, 0.814575, 0.999139, 1.294429, 1.865286",\
+ "0.636560, 0.864888, 1.049451, 1.344741, 1.915598",\
+ "0.797224, 1.025552, 1.210115, 1.505405, 2.076262",\
+ "1.378356, 1.606684, 1.791247, 2.086537, 2.657394",\
+ "0.642324, 0.869644, 1.054170, 1.349484, 1.920390",\
+ "0.674573, 0.901893, 1.086420, 1.381734, 1.952639",\
+ "0.724886, 0.952206, 1.136732, 1.432046, 2.002952",\
+ "0.885549, 1.112870, 1.297396, 1.592710, 2.163615",\
+ "1.466682, 1.694002, 1.878528, 2.173842, 2.744748",\
+ "0.731713, 0.949975, 1.134197, 1.429513, 2.000421",\
+ "0.763962, 0.982224, 1.166447, 1.461762, 2.032670",\
+ "0.814275, 1.032536, 1.216759, 1.512075, 2.082983",\
+ "0.974938, 1.193200, 1.377423, 1.672738, 2.243647",\
+ "1.556071, 1.774333, 1.958555, 2.253871, 2.824779",\
+ "0.795505, 1.007799, 1.191907, 1.486955, 2.057463",\
+ "0.827755, 1.040048, 1.224156, 1.519205, 2.089712",\
+ "0.878067, 1.090361, 1.274469, 1.569517, 2.140025",\
+ "1.038731, 1.251024, 1.435133, 1.730181, 2.300689",\
+ "1.619863, 1.832157, 2.016265, 2.311313, 2.881821",\
+ "1.132834, 1.313064, 1.495564, 1.790137, 2.359716",\
+ "1.165084, 1.345313, 1.527814, 1.822387, 2.391965",\
+ "1.215396, 1.395626, 1.578126, 1.872699, 2.442278",\
+ "1.376060, 1.556290, 1.738790, 2.033363, 2.602942",\
+ "1.957192, 2.137422, 2.319922, 2.614495, 3.184073");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\
+ "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\
+ "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\
+ "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\
+ "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\
+ "1.482982, 1.482982, 1.482982, 1.482983, 1.482983");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2401*/
+
+} /* end of pin tl_o[6] */
+
+pin("tl_o[5]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.035370 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[5];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[16]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.586415, 0.856406, 1.147453, 1.645288, 2.640958",\
+ "0.600096, 0.870093, 1.161170, 1.659087, 2.654921",\
+ "0.623625, 0.893621, 1.184696, 1.682603, 2.678417",\
+ "0.891636, 1.161662, 1.452904, 1.951255, 2.947956",\
+ "1.484832, 1.754906, 2.046407, 2.545443, 3.543516",\
+ "0.673827, 0.943991, 1.235112, 1.732003, 2.726892",\
+ "0.687508, 0.957678, 1.248830, 1.745802, 2.740855",\
+ "0.711038, 0.981207, 1.272355, 1.769318, 2.764350",\
+ "0.979048, 1.249249, 1.540565, 2.037970, 3.033889",\
+ "1.572245, 1.842492, 2.134070, 2.632158, 3.629450",\
+ "0.756613, 1.033065, 1.323078, 1.819625, 2.813847",\
+ "0.770294, 1.046752, 1.336796, 1.833425, 2.827810",\
+ "0.793824, 1.070281, 1.360321, 1.856940, 2.851305",\
+ "1.061835, 1.338323, 1.628531, 2.125592, 3.120844",\
+ "1.655032, 1.931567, 2.222036, 2.719780, 3.716405",\
+ "0.819991, 1.098835, 1.387222, 1.883539, 2.877356",\
+ "0.833672, 1.112521, 1.400940, 1.897338, 2.891319",\
+ "0.857202, 1.136050, 1.424465, 1.920853, 2.914814",\
+ "1.125213, 1.404093, 1.692675, 2.189505, 3.184353",\
+ "1.718410, 1.997339, 2.286180, 2.783694, 3.779914",\
+ "1.154701, 1.464769, 1.739384, 2.233007, 3.222812",\
+ "1.168382, 1.478458, 1.753102, 2.246807, 3.236775",\
+ "1.191912, 1.501987, 1.776627, 2.270322, 3.260271",\
+ "1.459925, 1.770039, 2.044842, 2.538976, 3.529809",\
+ "2.053125, 2.363301, 2.638354, 3.133168, 4.125370");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.122235, 0.122284, 0.123237, 0.126336, 0.132533",\
+ "0.151847, 0.152077, 0.152973, 0.155170, 0.159564",\
+ "0.201011, 0.201013, 0.201253, 0.202081, 0.203737",\
+ "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\
+ "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\
+ "0.122235, 0.122284, 0.123247, 0.126336, 0.132533",\
+ "0.151847, 0.152079, 0.152980, 0.155170, 0.159564",\
+ "0.201011, 0.201013, 0.201256, 0.202081, 0.203737",\
+ "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\
+ "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\
+ "0.122236, 0.122285, 0.123247, 0.126336, 0.132533",\
+ "0.151853, 0.152082, 0.152980, 0.155170, 0.159564",\
+ "0.201011, 0.201013, 0.201256, 0.202081, 0.203737",\
+ "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\
+ "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\
+ "0.122236, 0.122286, 0.123248, 0.126336, 0.132533",\
+ "0.151856, 0.152088, 0.152981, 0.155170, 0.159564",\
+ "0.201011, 0.201013, 0.201256, 0.202081, 0.203737",\
+ "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\
+ "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\
+ "0.122239, 0.122302, 0.123279, 0.126348, 0.132533",\
+ "0.151880, 0.152153, 0.153003, 0.155179, 0.159564",\
+ "0.201011, 0.201014, 0.201264, 0.202084, 0.203737",\
+ "0.823651, 0.823654, 0.823667, 0.823703, 0.823775",\
+ "2.222134, 2.222135, 2.222136, 2.222140, 2.222148");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.525645, 0.795489, 1.085730, 1.581432, 2.572836",\
+ "0.537639, 0.807524, 1.097989, 1.594284, 2.586873",\
+ "0.557233, 0.827173, 1.117941, 1.615037, 2.609230",\
+ "0.728499, 0.998614, 1.290344, 1.789985, 2.789268",\
+ "1.063132, 1.333237, 1.624904, 2.124381, 3.123334",\
+ "0.613058, 0.883074, 1.173382, 1.668147, 2.658770",\
+ "0.625052, 0.895109, 1.185643, 1.680999, 2.672807",\
+ "0.644646, 0.914759, 1.205598, 1.701752, 2.695163",\
+ "0.815911, 1.086201, 1.378008, 1.876700, 2.875202",\
+ "1.150545, 1.420823, 1.712568, 2.211096, 3.209268",\
+ "0.695842, 0.972144, 1.261348, 1.755769, 2.745725",\
+ "0.707837, 0.984180, 1.273609, 1.768621, 2.759762",\
+ "0.727431, 1.003831, 1.293564, 1.789375, 2.782119",\
+ "0.898699, 1.175277, 1.465974, 1.964322, 2.962157",\
+ "1.233333, 1.509899, 1.800534, 2.298718, 3.296223",\
+ "0.759218, 1.037910, 1.325492, 1.819683, 2.809234",\
+ "0.771213, 1.049947, 1.337753, 1.832534, 2.823271",\
+ "0.790808, 1.069599, 1.357708, 1.853288, 2.845628",\
+ "0.962077, 1.241050, 1.530119, 2.028236, 3.025666",\
+ "1.296711, 1.575672, 1.864679, 2.362631, 3.359732",\
+ "1.093920, 1.403797, 1.677632, 2.169142, 3.154690",\
+ "1.105917, 1.415847, 1.689899, 2.181997, 3.168727",\
+ "1.125515, 1.435517, 1.709862, 2.202754, 3.191083",\
+ "1.296794, 1.607024, 1.882299, 2.377712, 3.371122",\
+ "1.631427, 1.941643, 2.216857, 2.712107, 3.705188");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.074841, 0.075254, 0.077521, 0.083520, 0.095518",\
+ "0.080316, 0.080691, 0.082745, 0.088181, 0.099053",\
+ "0.100360, 0.100711, 0.102633, 0.107721, 0.117897",\
+ "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\
+ "1.025905, 1.025920, 1.025979, 1.026125, 1.026416",\
+ "0.074841, 0.075258, 0.077540, 0.083520, 0.095518",\
+ "0.080316, 0.080694, 0.082762, 0.088181, 0.099053",\
+ "0.100360, 0.100714, 0.102649, 0.107721, 0.117897",\
+ "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\
+ "1.025905, 1.025920, 1.025980, 1.026125, 1.026416",\
+ "0.074846, 0.075266, 0.077540, 0.083520, 0.095518",\
+ "0.080321, 0.080701, 0.082762, 0.088181, 0.099053",\
+ "0.100365, 0.100721, 0.102650, 0.107721, 0.117897",\
+ "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\
+ "1.025905, 1.025920, 1.025980, 1.026125, 1.026416",\
+ "0.074850, 0.075277, 0.077541, 0.083520, 0.095518",\
+ "0.080324, 0.080712, 0.082763, 0.088181, 0.099053",\
+ "0.100368, 0.100730, 0.102651, 0.107721, 0.117897",\
+ "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\
+ "1.025905, 1.025921, 1.025980, 1.026125, 1.026416",\
+ "0.074873, 0.075411, 0.077602, 0.083545, 0.095518",\
+ "0.080345, 0.080833, 0.082819, 0.088203, 0.099053",\
+ "0.100387, 0.100844, 0.102702, 0.107742, 0.117897",\
+ "0.380688, 0.380692, 0.380703, 0.380732, 0.380789",\
+ "1.025907, 1.025925, 1.025981, 1.026126, 1.026416");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2627*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[20]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.792764, 1.054507, 1.346593, 1.853632, 2.867709",\
+ "0.806316, 1.068059, 1.360145, 1.867184, 2.881261",\
+ "0.829846, 1.091589, 1.383675, 1.890714, 2.904791",\
+ "1.097219, 1.358962, 1.651048, 2.158087, 3.172164",\
+ "1.691027, 1.952770, 2.244857, 2.751895, 3.765972",\
+ "0.880176, 1.142082, 1.434281, 1.940346, 2.953642",\
+ "0.893728, 1.155634, 1.447833, 1.953899, 2.967195",\
+ "0.917258, 1.179164, 1.471363, 1.977429, 2.990725",\
+ "1.184632, 1.446538, 1.738737, 2.244802, 3.258098",\
+ "1.778440, 2.040346, 2.332545, 2.838610, 3.851906",\
+ "0.961078, 1.231132, 1.522248, 2.027969, 3.040597",\
+ "0.974630, 1.244684, 1.535800, 2.041521, 3.054150",\
+ "0.998160, 1.268215, 1.559330, 2.065051, 3.077680",\
+ "1.265533, 1.535588, 1.826703, 2.332424, 3.345053",\
+ "1.859341, 2.129396, 2.420511, 2.926232, 3.938861",\
+ "1.020773, 1.296868, 1.586394, 2.091882, 3.104106",\
+ "1.034325, 1.310420, 1.599946, 2.105434, 3.117659",\
+ "1.057855, 1.333951, 1.623476, 2.128964, 3.141189",\
+ "1.325228, 1.601324, 1.890849, 2.396338, 3.408562",\
+ "1.919036, 2.195132, 2.484657, 2.990146, 4.002370",\
+ "1.354614, 1.662408, 1.938648, 2.441389, 3.449563",\
+ "1.368166, 1.675960, 1.952201, 2.454941, 3.463115",\
+ "1.391696, 1.699491, 1.975731, 2.478471, 3.486645",\
+ "1.659069, 1.966864, 2.243104, 2.745844, 3.754018",\
+ "2.252877, 2.560672, 2.836912, 3.339653, 4.347826");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.760378, 1.022121, 1.314208, 1.821246, 2.835323",\
+ "0.768321, 1.030064, 1.322150, 1.829189, 2.843266",\
+ "0.781801, 1.043544, 1.335630, 1.842669, 2.856746",\
+ "0.935753, 1.197497, 1.489583, 1.996622, 3.010698",\
+ "1.275653, 1.537396, 1.829482, 2.336521, 3.350598",\
+ "0.847791, 1.109697, 1.401896, 1.907961, 2.921257",\
+ "0.855733, 1.117639, 1.409838, 1.915904, 2.929199",\
+ "0.869213, 1.131119, 1.423318, 1.929384, 2.942679",\
+ "1.023166, 1.285072, 1.577271, 2.083336, 3.096632",\
+ "1.363066, 1.624972, 1.917171, 2.423236, 3.436532",\
+ "0.928693, 1.198747, 1.489862, 1.995583, 3.008212",\
+ "0.936635, 1.206689, 1.497805, 2.003526, 3.016155",\
+ "0.950115, 1.220170, 1.511285, 2.017006, 3.029634",\
+ "1.104068, 1.374122, 1.665238, 2.170959, 3.183587",\
+ "1.443967, 1.714022, 2.005137, 2.510858, 3.523487",\
+ "0.988388, 1.264483, 1.554008, 2.059497, 3.071721",\
+ "0.996330, 1.272425, 1.561951, 2.067439, 3.079664",\
+ "1.009810, 1.285905, 1.575431, 2.080919, 3.093143",\
+ "1.163763, 1.439858, 1.729384, 2.234872, 3.247096",\
+ "1.503662, 1.779758, 2.069283, 2.574772, 3.586996",\
+ "1.322228, 1.630023, 1.906263, 2.409003, 3.417177",\
+ "1.330171, 1.637965, 1.914206, 2.416946, 3.425119",\
+ "1.343651, 1.651445, 1.927685, 2.430426, 3.438600",\
+ "1.497604, 1.805398, 2.081638, 2.584379, 3.592552",\
+ "1.837503, 2.145298, 2.421538, 2.924278, 3.932452");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\
+ "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\
+ "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\
+ "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\
+ "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2734*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[22]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.773575, 1.028253, 1.310824, 1.779371, 2.716465",\
+ "0.787127, 1.041805, 1.324376, 1.792923, 2.730017",\
+ "0.810657, 1.065335, 1.347906, 1.816453, 2.753547",\
+ "1.078030, 1.332708, 1.615279, 2.083826, 3.020920",\
+ "1.671839, 1.926517, 2.209088, 2.677635, 3.614729",\
+ "0.860984, 1.115846, 1.398389, 1.866085, 2.802399",\
+ "0.874536, 1.129398, 1.411941, 1.879637, 2.815951",\
+ "0.898067, 1.152928, 1.435471, 1.903167, 2.839481",\
+ "1.165440, 1.420301, 1.702844, 2.170541, 3.106854",\
+ "1.759248, 2.014110, 2.296653, 2.764349, 3.700663",\
+ "0.941840, 1.204919, 1.486352, 1.953707, 2.889354",\
+ "0.955392, 1.218471, 1.499904, 1.967259, 2.902906",\
+ "0.978923, 1.242001, 1.523435, 1.990789, 2.926436",\
+ "1.246296, 1.509374, 1.790808, 2.258162, 3.193809",\
+ "1.840104, 2.103183, 2.384616, 2.851971, 3.787618",\
+ "0.999500, 1.270687, 1.550492, 2.017620, 2.952863",\
+ "1.013052, 1.284239, 1.564044, 2.031172, 2.966415",\
+ "1.036583, 1.307769, 1.587574, 2.054702, 2.989945",\
+ "1.303956, 1.575142, 1.854947, 2.322075, 3.257318",\
+ "1.897764, 2.168951, 2.448756, 2.915884, 3.851127",\
+ "1.331207, 1.636652, 1.902354, 2.366964, 3.298319",\
+ "1.344759, 1.650204, 1.915906, 2.380516, 3.311871",\
+ "1.368289, 1.673734, 1.939437, 2.404047, 3.335401",\
+ "1.635662, 1.941107, 2.206810, 2.671420, 3.602774",\
+ "2.229471, 2.534916, 2.800618, 3.265228, 4.196583");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\
+ "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\
+ "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.741190, 0.995868, 1.278439, 1.746986, 2.684080",\
+ "0.749133, 1.003811, 1.286381, 1.754929, 2.692023",\
+ "0.762613, 1.017291, 1.299861, 1.768409, 2.705503",\
+ "0.916565, 1.171243, 1.453814, 1.922361, 2.859455",\
+ "1.256465, 1.511143, 1.793714, 2.262261, 3.199355",\
+ "0.828600, 1.083461, 1.366004, 1.833700, 2.770014",\
+ "0.836542, 1.091403, 1.373946, 1.841643, 2.777956",\
+ "0.850022, 1.104883, 1.387426, 1.855123, 2.791436",\
+ "1.003975, 1.258836, 1.541379, 2.009076, 2.945389",\
+ "1.343874, 1.598736, 1.881279, 2.348975, 3.285289",\
+ "0.909456, 1.172534, 1.453968, 1.921322, 2.856969",\
+ "0.917398, 1.180476, 1.461910, 1.929265, 2.864911",\
+ "0.930878, 1.193956, 1.475390, 1.942744, 2.878391",\
+ "1.084831, 1.347909, 1.629343, 2.096697, 3.032344",\
+ "1.424730, 1.687809, 1.969242, 2.436597, 3.372244",\
+ "0.967116, 1.238302, 1.518107, 1.985235, 2.920478",\
+ "0.975058, 1.246245, 1.526050, 1.993178, 2.928420",\
+ "0.988538, 1.259725, 1.539530, 2.006658, 2.941900",\
+ "1.142491, 1.413677, 1.693483, 2.160611, 3.095853",\
+ "1.482390, 1.753577, 2.033382, 2.500510, 3.435753",\
+ "1.298822, 1.604267, 1.869970, 2.334579, 3.265934",\
+ "1.306764, 1.612210, 1.877912, 2.342522, 3.273876",\
+ "1.320244, 1.625690, 1.891392, 2.356002, 3.287356",\
+ "1.474197, 1.779642, 2.045345, 2.509955, 3.441309",\
+ "1.814097, 2.119542, 2.385244, 2.849854, 3.781209");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\
+ "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\
+ "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\
+ "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\
+ "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\
+ "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\
+ "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025895");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[23]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.741012, 0.979467, 1.257014, 1.743332, 2.715968",\
+ "0.754606, 0.993061, 1.270608, 1.756926, 2.729561",\
+ "0.778146, 1.016601, 1.294148, 1.780466, 2.753102",\
+ "1.045683, 1.284138, 1.561685, 2.048002, 3.020638",\
+ "1.638147, 1.876602, 2.154149, 2.640466, 3.613101",\
+ "0.828421, 1.066996, 1.344635, 1.830046, 2.801901",\
+ "0.842015, 1.080589, 1.358228, 1.843640, 2.815495",\
+ "0.865555, 1.104130, 1.381769, 1.867180, 2.839035",\
+ "1.133092, 1.371667, 1.649306, 2.134717, 3.106571",\
+ "1.725556, 1.964131, 2.241770, 2.727180, 3.699034",\
+ "0.909283, 1.155921, 1.432599, 1.917668, 2.888856",\
+ "0.922877, 1.169514, 1.446193, 1.931262, 2.902450",\
+ "0.946417, 1.193055, 1.469733, 1.954802, 2.925990",\
+ "1.213954, 1.460592, 1.737270, 2.222339, 3.193527",\
+ "1.806418, 2.053056, 2.329734, 2.814802, 3.785990",\
+ "0.966958, 1.221474, 1.496742, 1.981581, 2.952365",\
+ "0.980552, 1.235068, 1.510336, 1.995175, 2.965959",\
+ "1.004092, 1.258608, 1.533876, 2.018715, 2.989499",\
+ "1.271629, 1.526145, 1.801413, 2.286252, 3.257035",\
+ "1.864093, 2.118609, 2.393877, 2.878715, 3.849499",\
+ "1.288363, 1.584928, 1.848784, 2.330998, 3.297822",\
+ "1.301956, 1.598522, 1.862378, 2.344592, 3.311415",\
+ "1.325497, 1.622062, 1.885918, 2.368132, 3.334955",\
+ "1.593034, 1.889599, 2.153455, 2.635669, 3.602492",\
+ "2.185498, 2.482063, 2.745919, 3.228132, 4.194955");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\
+ "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\
+ "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\
+ "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\
+ "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\
+ "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.682520, 0.920976, 1.198522, 1.684841, 2.657480",\
+ "0.693882, 0.932337, 1.209884, 1.696203, 2.668840",\
+ "0.712620, 0.951075, 1.228621, 1.714940, 2.687577",\
+ "0.881167, 1.119623, 1.397169, 1.883486, 2.856120",\
+ "1.215977, 1.454432, 1.731979, 2.218296, 3.190930",\
+ "0.769929, 1.008504, 1.286143, 1.771556, 2.743413",\
+ "0.781291, 1.019865, 1.297505, 1.782917, 2.754774",\
+ "0.800029, 1.038603, 1.316242, 1.801654, 2.773510",\
+ "0.968576, 1.207151, 1.484790, 1.970200, 2.942054",\
+ "1.303386, 1.541960, 1.819599, 2.305010, 3.276864",\
+ "0.850791, 1.097429, 1.374108, 1.859177, 2.830368",\
+ "0.862152, 1.108790, 1.385469, 1.870539, 2.841729",\
+ "0.880890, 1.127528, 1.404207, 1.889276, 2.860465",\
+ "1.049438, 1.296076, 1.572754, 2.057822, 3.029009",\
+ "1.384248, 1.630886, 1.907564, 2.392632, 3.363819",\
+ "0.908466, 1.162982, 1.438250, 1.923091, 2.893877",\
+ "0.919828, 1.174344, 1.449612, 1.934452, 2.905238",\
+ "0.938565, 1.193082, 1.468349, 1.953189, 2.923974",\
+ "1.107113, 1.361629, 1.636897, 2.121735, 3.092518",\
+ "1.441923, 1.696439, 1.971707, 2.456545, 3.427328",\
+ "1.229871, 1.526436, 1.790293, 2.272508, 3.239333",\
+ "1.241232, 1.537798, 1.801654, 2.283869, 3.250694",\
+ "1.259970, 1.556535, 1.820392, 2.302606, 3.269430",\
+ "1.428518, 1.725083, 1.988939, 2.471152, 3.437974",\
+ "1.763328, 2.059893, 2.323749, 2.805962, 3.772784");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\
+ "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\
+ "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\
+ "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\
+ "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\
+ "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\
+ "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\
+ "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\
+ "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\
+ "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\
+ "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\
+ "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\
+ "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\
+ "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\
+ "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025917");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2374*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[25]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.697898, 0.947965, 1.225734, 1.724852, 2.723087",\
+ "0.711492, 0.961559, 1.239327, 1.738445, 2.736680",\
+ "0.735032, 0.985099, 1.262868, 1.761985, 2.760221",\
+ "1.002569, 1.252636, 1.530404, 2.029521, 3.027754",\
+ "1.595033, 1.845100, 2.122868, 2.621982, 3.620212",\
+ "0.785303, 1.035477, 1.313393, 1.811565, 2.809021",\
+ "0.798897, 1.049071, 1.326987, 1.825159, 2.822614",\
+ "0.822437, 1.072611, 1.350527, 1.848699, 2.846154",\
+ "1.089974, 1.340148, 1.618063, 2.116235, 3.113688",\
+ "1.682438, 1.932612, 2.210527, 2.708696, 3.706145",\
+ "0.866148, 1.124350, 1.401358, 1.899186, 2.895976",\
+ "0.879741, 1.137944, 1.414951, 1.912780, 2.909569",\
+ "0.903282, 1.161484, 1.438491, 1.936320, 2.933109",\
+ "1.170819, 1.429021, 1.706028, 2.203856, 3.200643",\
+ "1.763283, 2.021485, 2.298491, 2.796317, 3.793100",\
+ "0.926036, 1.189827, 1.465502, 1.963099, 2.959485",\
+ "0.939630, 1.203421, 1.479096, 1.976693, 2.973078",\
+ "0.963170, 1.226961, 1.502636, 2.000233, 2.996618",\
+ "1.230707, 1.494498, 1.770173, 2.267768, 3.264152",\
+ "1.823171, 2.086962, 2.362636, 2.860230, 3.856609",\
+ "1.263356, 1.552433, 1.817672, 2.312566, 3.304941",\
+ "1.276949, 1.566026, 1.831266, 2.326159, 3.318534",\
+ "1.300490, 1.589567, 1.854806, 2.349699, 3.342074",\
+ "1.568027, 1.857104, 2.122343, 2.617235, 3.609608",\
+ "2.160491, 2.449568, 2.714806, 3.209696, 4.202065");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\
+ "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\
+ "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\
+ "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\
+ "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\
+ "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.639406, 0.889474, 1.167244, 1.666367, 2.664614",\
+ "0.650768, 0.900835, 1.178605, 1.677727, 2.675971",\
+ "0.669506, 0.919573, 1.197342, 1.696462, 2.694701",\
+ "0.838053, 1.088120, 1.365887, 1.865001, 2.863227",\
+ "1.172863, 1.422930, 1.700697, 2.199811, 3.198038",\
+ "0.726812, 0.976986, 1.254903, 1.753081, 2.750548",\
+ "0.738173, 0.988347, 1.266264, 1.764440, 2.761904",\
+ "0.756911, 1.007085, 1.285001, 1.783175, 2.780635",\
+ "0.925458, 1.175632, 1.453547, 1.951714, 2.949161",\
+ "1.260268, 1.510442, 1.788356, 2.286525, 3.283972",\
+ "0.807656, 1.065858, 1.342867, 1.840702, 2.837503",\
+ "0.819017, 1.077220, 1.354228, 1.852061, 2.848859",\
+ "0.837755, 1.095958, 1.372966, 1.870796, 2.867590",\
+ "1.006303, 1.264505, 1.541511, 2.039335, 3.036116",\
+ "1.341113, 1.599315, 1.876321, 2.374146, 3.370927",\
+ "0.867545, 1.131335, 1.407012, 1.904615, 2.901012",\
+ "0.878906, 1.142697, 1.418373, 1.915974, 2.912368",\
+ "0.897644, 1.161434, 1.437110, 1.934709, 2.931099",\
+ "1.066191, 1.329982, 1.605656, 2.103248, 3.099625",\
+ "1.401001, 1.664792, 1.940466, 2.438058, 3.434436",\
+ "1.204864, 1.493941, 1.759182, 2.254081, 3.246468",\
+ "1.216225, 1.505302, 1.770543, 2.265441, 3.257824",\
+ "1.234963, 1.524040, 1.789280, 2.284176, 3.276555",\
+ "1.403511, 1.692588, 1.957826, 2.452714, 3.445081",\
+ "1.738321, 2.027398, 2.292636, 2.787525, 3.779892");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\
+ "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\
+ "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\
+ "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\
+ "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\
+ "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\
+ "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\
+ "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\
+ "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\
+ "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\
+ "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\
+ "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\
+ "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\
+ "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\
+ "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\
+ "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\
+ "0.068435, 0.068435, 0.068430, 0.068415, 0.068383",\
+ "0.074512, 0.074512, 0.074507, 0.074493, 0.074464",\
+ "0.094928, 0.094928, 0.094923, 0.094910, 0.094883",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\
+ "1.025917, 1.025917, 1.025917, 1.025918, 1.025919");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2490*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[26]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.564894, 0.815791, 1.094396, 1.559341, 2.489231",\
+ "0.578576, 0.829479, 1.108111, 1.573121, 2.503140",\
+ "0.602105, 0.853007, 1.131636, 1.596638, 2.526642",\
+ "0.870117, 1.121053, 1.399829, 1.865184, 2.795893",\
+ "1.463316, 1.714304, 1.993307, 2.459207, 3.391007",\
+ "0.652304, 0.903365, 1.181950, 1.646055, 2.575164",\
+ "0.665985, 0.917053, 1.195665, 1.659835, 2.589074",\
+ "0.689515, 0.940582, 1.219190, 1.683353, 2.612576",\
+ "0.957527, 1.208627, 1.487384, 1.951898, 2.881827",\
+ "1.550725, 1.801879, 2.080863, 2.545921, 3.476941",\
+ "0.733136, 0.992396, 1.269913, 1.733677, 2.662119",\
+ "0.746817, 1.006083, 1.283628, 1.747457, 2.676029",\
+ "0.770346, 1.029612, 1.307153, 1.770974, 2.699531",\
+ "1.038358, 1.297659, 1.575347, 2.039520, 2.968782",\
+ "1.631557, 1.890911, 2.168827, 2.633543, 3.563896",\
+ "0.790750, 1.058102, 1.334052, 1.797590, 2.725628",\
+ "0.804431, 1.071790, 1.347767, 1.811370, 2.739538",\
+ "0.827961, 1.095319, 1.371293, 1.834888, 2.763040",\
+ "1.095973, 1.363366, 1.639486, 2.103433, 3.032291",\
+ "1.689171, 1.956620, 2.232966, 2.697456, 3.627405",\
+ "1.120458, 1.423346, 1.685878, 2.146919, 3.071084",\
+ "1.134140, 1.437036, 1.699593, 2.160699, 3.084994",\
+ "1.157669, 1.460564, 1.723119, 2.184217, 3.108496",\
+ "1.425683, 1.728623, 1.991316, 2.452764, 3.377747",\
+ "2.018884, 2.321894, 2.584802, 3.046790, 3.972861");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.122237, 0.122291, 0.122948, 0.124971, 0.129018",\
+ "0.151797, 0.151880, 0.152446, 0.154040, 0.157229",\
+ "0.201011, 0.201013, 0.201172, 0.201712, 0.202792",\
+ "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\
+ "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\
+ "0.122237, 0.122291, 0.122954, 0.124971, 0.129018",\
+ "0.151797, 0.151881, 0.152451, 0.154040, 0.157229",\
+ "0.201011, 0.201013, 0.201174, 0.201712, 0.202792",\
+ "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\
+ "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\
+ "0.122237, 0.122292, 0.122954, 0.124971, 0.129018",\
+ "0.151797, 0.151883, 0.152451, 0.154040, 0.157229",\
+ "0.201011, 0.201013, 0.201174, 0.201712, 0.202792",\
+ "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\
+ "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\
+ "0.122238, 0.122294, 0.122955, 0.124971, 0.129018",\
+ "0.151797, 0.151885, 0.152452, 0.154040, 0.157229",\
+ "0.201011, 0.201013, 0.201174, 0.201712, 0.202792",\
+ "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\
+ "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\
+ "0.122241, 0.122311, 0.122975, 0.124980, 0.129018",\
+ "0.151805, 0.151911, 0.152468, 0.154047, 0.157229",\
+ "0.201012, 0.201014, 0.201180, 0.201714, 0.202792",\
+ "0.823651, 0.823654, 0.823666, 0.823694, 0.823752",\
+ "2.222134, 2.222134, 2.222135, 2.222138, 2.222144");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.504118, 0.754852, 1.032751, 1.495998, 2.422494",\
+ "0.516114, 0.766894, 1.044988, 1.508707, 2.436146",\
+ "0.535711, 0.786551, 1.064911, 1.529268, 2.457982",\
+ "0.706984, 0.958018, 1.237222, 1.703603, 2.636367",\
+ "1.041617, 1.292639, 1.571788, 2.038038, 2.970540",\
+ "0.591527, 0.842425, 1.120299, 1.582713, 2.508428",\
+ "0.603524, 0.854467, 1.132538, 1.595422, 2.522079",\
+ "0.623120, 0.874125, 1.152463, 1.615983, 2.543916",\
+ "0.794393, 1.045593, 1.324780, 1.790318, 2.722301",\
+ "1.129027, 1.380214, 1.659346, 2.124753, 3.056474",\
+ "0.672359, 0.931452, 1.208262, 1.670335, 2.595383",\
+ "0.684355, 0.943495, 1.220501, 1.683044, 2.609035",\
+ "0.703952, 0.963154, 1.240426, 1.703604, 2.630871",\
+ "0.875225, 1.134627, 1.412743, 1.877940, 2.809256",\
+ "1.209858, 1.469247, 1.747309, 2.212375, 3.143429",\
+ "0.729973, 0.997154, 1.272401, 1.734248, 2.658892",\
+ "0.741969, 1.009198, 1.284640, 1.746957, 2.672544",\
+ "0.761566, 1.028859, 1.304565, 1.767518, 2.694380",\
+ "0.932840, 1.200337, 1.476882, 1.941853, 2.872765",\
+ "1.267473, 1.534957, 1.811448, 2.276288, 3.206938",\
+ "1.059672, 1.362345, 1.624210, 2.083570, 3.004348",\
+ "1.071671, 1.374403, 1.636453, 2.096281, 3.018000",\
+ "1.091271, 1.394084, 1.656385, 2.116844, 3.039836",\
+ "1.262555, 1.565626, 1.828723, 2.291188, 3.218221",\
+ "1.597188, 1.900242, 2.163287, 2.625622, 3.552394");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.074860, 0.075317, 0.077304, 0.082076, 0.091621",\
+ "0.080333, 0.080747, 0.082548, 0.086873, 0.095522",\
+ "0.100376, 0.100764, 0.102449, 0.106497, 0.114592",\
+ "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\
+ "1.025901, 1.025907, 1.025944, 1.026050, 1.026262",\
+ "0.074860, 0.075320, 0.077319, 0.082076, 0.091621",\
+ "0.080333, 0.080751, 0.082562, 0.086873, 0.095522",\
+ "0.100376, 0.100767, 0.102462, 0.106497, 0.114592",\
+ "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\
+ "1.025901, 1.025907, 1.025945, 1.026050, 1.026262",\
+ "0.074860, 0.075329, 0.077319, 0.082076, 0.091621",\
+ "0.080334, 0.080759, 0.082562, 0.086873, 0.095522",\
+ "0.100376, 0.100774, 0.102462, 0.106497, 0.114592",\
+ "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\
+ "1.025901, 1.025907, 1.025945, 1.026050, 1.026262",\
+ "0.074860, 0.075342, 0.077320, 0.082076, 0.091621",\
+ "0.080334, 0.080770, 0.082563, 0.086873, 0.095522",\
+ "0.100377, 0.100785, 0.102463, 0.106497, 0.114592",\
+ "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\
+ "1.025901, 1.025907, 1.025945, 1.026050, 1.026262",\
+ "0.074886, 0.075492, 0.077368, 0.082096, 0.091621",\
+ "0.080357, 0.080906, 0.082607, 0.086890, 0.095522",\
+ "0.100399, 0.100912, 0.102504, 0.106513, 0.114592",\
+ "0.380687, 0.380689, 0.380696, 0.380717, 0.380759",\
+ "1.025902, 1.025909, 1.025946, 1.026050, 1.026262");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2519*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[27]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.601589, 0.856514, 1.112604, 1.552662, 2.432779",\
+ "0.615142, 0.870066, 1.126156, 1.566215, 2.446333",\
+ "0.638672, 0.893596, 1.149686, 1.589744, 2.469861",\
+ "0.906045, 1.160969, 1.417061, 1.857126, 2.737255",\
+ "1.499860, 1.754785, 2.010744, 2.450359, 3.329590",\
+ "0.689139, 0.944005, 1.200076, 1.639375, 2.518713",\
+ "0.702691, 0.957558, 1.213628, 1.652928, 2.532267",\
+ "0.726222, 0.981088, 1.237158, 1.676457, 2.555795",\
+ "0.993595, 1.248461, 1.504533, 1.943839, 2.823189",\
+ "1.587410, 1.842276, 2.098214, 2.537072, 3.415524",\
+ "0.778517, 1.032815, 1.288036, 1.726995, 2.605668",\
+ "0.792069, 1.046367, 1.301588, 1.740548, 2.619222",\
+ "0.815599, 1.069897, 1.325118, 1.764078, 2.642750",\
+ "1.082972, 1.337270, 1.592493, 2.031459, 2.910144",\
+ "1.676788, 1.931085, 2.186174, 2.624692, 3.502479",\
+ "0.842460, 1.098198, 1.352170, 1.790908, 2.669177",\
+ "0.856012, 1.111750, 1.365723, 1.804461, 2.682731",\
+ "0.879542, 1.135280, 1.389253, 1.827990, 2.706259",\
+ "1.146915, 1.402653, 1.656628, 2.095372, 2.973653",\
+ "1.740730, 1.996469, 2.250309, 2.688605, 3.565988",\
+ "1.180709, 1.459770, 1.703739, 2.140127, 3.014633",\
+ "1.194261, 1.473322, 1.717291, 2.153680, 3.028187",\
+ "1.217791, 1.496852, 1.740821, 2.177209, 3.051715",\
+ "1.485164, 1.764225, 2.008196, 2.444591, 3.319109",\
+ "2.078980, 2.358040, 2.601873, 3.037822, 3.911444");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\
+ "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\
+ "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\
+ "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\
+ "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\
+ "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\
+ "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\
+ "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\
+ "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\
+ "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\
+ "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\
+ "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\
+ "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\
+ "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\
+ "0.201129, 0.201129, 0.201131, 0.201137, 0.201149",\
+ "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.569211, 0.824136, 1.079695, 1.517959, 2.394488",\
+ "0.577154, 0.832078, 1.087637, 1.525902, 2.402431",\
+ "0.590634, 0.845558, 1.101117, 1.539382, 2.415911",\
+ "0.744587, 0.999511, 1.255305, 1.694361, 2.572475",\
+ "1.084486, 1.339411, 1.594970, 2.033235, 2.909765",\
+ "0.656761, 0.911627, 1.167161, 1.604672, 2.480422",\
+ "0.664704, 0.919570, 1.175103, 1.612615, 2.488365",\
+ "0.678184, 0.933050, 1.188583, 1.626095, 2.501845",\
+ "0.832137, 1.087003, 1.342773, 1.781074, 2.658409",\
+ "1.172036, 1.426902, 1.682436, 2.119948, 2.995698",\
+ "0.746139, 1.000437, 1.255121, 1.692293, 2.567377",\
+ "0.754081, 1.008379, 1.263063, 1.700235, 2.575320",\
+ "0.767561, 1.021859, 1.276543, 1.713715, 2.588800",\
+ "0.921514, 1.175812, 1.430733, 1.868695, 2.745364",\
+ "1.261414, 1.515711, 1.770396, 2.207568, 3.082654",\
+ "0.810081, 1.065820, 1.319255, 1.756205, 2.630886",\
+ "0.818024, 1.073762, 1.327198, 1.764148, 2.638829",\
+ "0.831504, 1.087242, 1.340678, 1.777627, 2.652309",\
+ "0.985457, 1.241195, 1.494868, 1.932607, 2.808873",\
+ "1.325356, 1.581095, 1.834530, 2.271481, 3.146163",\
+ "1.148331, 1.427392, 1.670806, 2.105417, 2.976342",\
+ "1.156273, 1.435334, 1.678748, 2.113359, 2.984285",\
+ "1.169753, 1.448814, 1.692228, 2.126839, 2.997765",\
+ "1.323706, 1.602767, 1.846426, 2.281822, 3.154329",\
+ "1.663605, 1.942666, 2.186081, 2.620692, 3.491619");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\
+ "0.068571, 0.068571, 0.068550, 0.068476, 0.068328",\
+ "0.090396, 0.090396, 0.090388, 0.090358, 0.090299",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\
+ "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\
+ "0.068571, 0.068571, 0.068549, 0.068476, 0.068328",\
+ "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\
+ "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\
+ "0.068571, 0.068571, 0.068549, 0.068476, 0.068328",\
+ "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\
+ "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\
+ "0.068571, 0.068571, 0.068549, 0.068476, 0.068328",\
+ "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\
+ "0.061223, 0.061223, 0.061190, 0.061084, 0.060871",\
+ "0.068571, 0.068571, 0.068549, 0.068475, 0.068328",\
+ "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025895, 1.025895, 1.025895, 1.025895, 1.025894");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2575*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[30]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.577162, 0.819115, 1.086143, 1.569512, 2.536249",\
+ "0.590714, 0.832667, 1.099696, 1.583067, 2.549807",\
+ "0.614244, 0.856197, 1.123226, 1.606594, 2.573331",\
+ "0.881617, 1.123572, 1.390607, 1.873991, 2.840761",\
+ "1.475569, 1.717569, 1.984519, 2.467402, 3.433167",\
+ "0.664563, 0.906592, 1.173751, 1.656225, 2.622182",\
+ "0.678115, 0.920144, 1.187304, 1.669780, 2.635741",\
+ "0.701645, 0.943674, 1.210834, 1.693307, 2.659265",\
+ "0.969019, 1.211049, 1.478215, 1.960705, 2.926694",\
+ "1.562970, 1.805047, 2.072125, 2.554115, 3.519101",\
+ "0.745370, 0.995374, 1.261714, 1.743845, 2.709137",\
+ "0.758922, 1.008926, 1.275267, 1.757400, 2.722696",\
+ "0.782452, 1.032456, 1.298797, 1.780928, 2.746220",\
+ "1.049826, 1.299831, 1.566178, 2.048325, 3.013649",\
+ "1.643777, 1.893830, 2.160089, 2.641735, 3.606056",\
+ "0.805541, 1.060718, 1.325856, 1.807758, 2.772646",\
+ "0.819093, 1.074270, 1.339409, 1.821313, 2.786205",\
+ "0.842623, 1.097800, 1.362939, 1.844840, 2.809729",\
+ "1.109996, 1.365175, 1.630320, 2.112238, 3.077158",\
+ "1.703948, 1.959175, 2.224230, 2.705648, 3.669565",\
+ "1.143425, 1.421812, 1.677865, 2.157156, 3.118103",\
+ "1.156977, 1.435364, 1.691418, 2.170711, 3.131661",\
+ "1.180507, 1.458894, 1.714947, 2.194238, 3.155185",\
+ "1.447880, 1.726269, 1.982328, 2.461636, 3.422615",\
+ "2.041832, 2.320285, 2.576234, 3.055044, 4.015021");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\
+ "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\
+ "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\
+ "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\
+ "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\
+ "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\
+ "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\
+ "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\
+ "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121333, 0.121337, 0.121351, 0.121386, 0.121458",\
+ "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\
+ "0.201129, 0.201130, 0.201137, 0.201152, 0.201184",\
+ "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.544918, 0.786919, 1.051943, 1.528303, 2.481022",\
+ "0.552861, 0.794861, 1.060131, 1.537319, 2.491697",\
+ "0.566341, 0.808341, 1.074013, 1.552566, 2.509672",\
+ "0.720294, 0.962295, 1.229085, 1.711427, 2.676111",\
+ "1.060194, 1.302195, 1.568545, 2.049397, 3.011100",\
+ "0.632320, 0.874396, 1.139529, 1.615016, 2.566956",\
+ "0.640262, 0.882339, 1.147719, 1.624032, 2.577631",\
+ "0.653742, 0.895819, 1.161606, 1.639279, 2.595606",\
+ "0.807696, 1.049772, 1.316690, 1.798140, 2.762045",\
+ "1.147596, 1.389672, 1.656145, 2.136110, 3.097034",\
+ "0.713127, 0.963179, 1.227492, 1.702637, 2.653911",\
+ "0.721069, 0.971121, 1.235682, 1.711653, 2.664586",\
+ "0.734549, 0.984601, 1.249569, 1.726900, 2.682561",\
+ "0.888502, 1.138555, 1.404653, 1.885761, 2.849000",\
+ "1.228403, 1.478455, 1.744108, 2.223730, 3.183989",\
+ "0.773297, 1.028524, 1.291633, 1.766549, 2.717420",\
+ "0.781240, 1.036467, 1.299823, 1.775565, 2.728095",\
+ "0.794720, 1.049947, 1.313710, 1.790812, 2.746070",\
+ "0.948673, 1.203900, 1.468795, 1.949673, 2.912509",\
+ "1.288574, 1.543800, 1.808250, 2.287643, 3.247498",\
+ "1.111181, 1.389635, 1.643570, 2.115918, 3.062876",\
+ "1.119124, 1.397577, 1.651768, 2.124938, 3.073550",\
+ "1.132604, 1.411057, 1.665669, 2.140191, 3.091526",\
+ "1.286557, 1.565011, 1.820792, 2.299067, 3.257965",\
+ "1.626457, 1.904911, 2.160232, 2.637031, 3.592954");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.061220, 0.061199, 0.061091, 0.060821, 0.060280",\
+ "0.068569, 0.068555, 0.068480, 0.068293, 0.067919",\
+ "0.090395, 0.090390, 0.090360, 0.090285, 0.090136",\
+ "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\
+ "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\
+ "0.061220, 0.061199, 0.061090, 0.060821, 0.060280",\
+ "0.068569, 0.068555, 0.068480, 0.068293, 0.067919",\
+ "0.090395, 0.090390, 0.090360, 0.090285, 0.090136",\
+ "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\
+ "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\
+ "0.061220, 0.061198, 0.061090, 0.060821, 0.060280",\
+ "0.068569, 0.068554, 0.068480, 0.068293, 0.067919",\
+ "0.090395, 0.090390, 0.090360, 0.090285, 0.090136",\
+ "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\
+ "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\
+ "0.061220, 0.061198, 0.061090, 0.060821, 0.060280",\
+ "0.068569, 0.068554, 0.068479, 0.068293, 0.067919",\
+ "0.090395, 0.090389, 0.090360, 0.090285, 0.090136",\
+ "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\
+ "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\
+ "0.061220, 0.061191, 0.061087, 0.060819, 0.060280",\
+ "0.068569, 0.068549, 0.068478, 0.068292, 0.067919",\
+ "0.090395, 0.090387, 0.090359, 0.090285, 0.090136",\
+ "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\
+ "1.025895, 1.025895, 1.025894, 1.025891, 1.025886");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2704*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[32]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.666137, 0.908208, 1.174611, 1.656033, 2.618876",\
+ "0.679731, 0.921802, 1.188205, 1.669626, 2.632469",\
+ "0.703271, 0.945343, 1.211745, 1.693166, 2.656009",\
+ "0.970809, 1.212879, 1.479281, 1.960701, 2.923540",\
+ "1.563272, 1.805343, 2.071744, 2.553161, 3.515995",\
+ "0.753539, 0.995685, 1.262213, 1.742746, 2.704810",\
+ "0.767133, 1.009279, 1.275807, 1.756339, 2.718403",\
+ "0.790673, 1.032819, 1.299347, 1.779880, 2.741943",\
+ "1.058210, 1.300356, 1.566883, 2.047414, 3.009474",\
+ "1.650674, 1.892820, 2.159346, 2.639874, 3.601928",\
+ "0.834346, 1.084466, 1.350176, 1.830367, 2.791765",\
+ "0.847940, 1.098060, 1.363770, 1.843960, 2.805358",\
+ "0.871480, 1.121600, 1.387310, 1.867500, 2.828898",\
+ "1.139017, 1.389137, 1.654846, 2.135035, 3.096429",\
+ "1.731481, 1.981601, 2.247309, 2.727494, 3.688883",\
+ "0.894640, 1.149809, 1.414318, 1.894279, 2.855274",\
+ "0.908234, 1.163403, 1.427911, 1.907872, 2.868867",\
+ "0.931774, 1.186943, 1.451452, 1.931413, 2.892407",\
+ "1.199311, 1.454480, 1.718988, 2.198947, 3.159938",\
+ "1.791775, 2.046944, 2.311450, 2.791407, 3.752392",\
+ "1.232542, 1.510890, 1.766306, 2.243669, 3.200730",\
+ "1.246135, 1.524484, 1.779900, 2.257262, 3.214323",\
+ "1.269676, 1.548024, 1.803440, 2.280803, 3.237863",\
+ "1.537213, 1.815561, 2.070976, 2.548337, 3.505394",\
+ "2.129677, 2.408025, 2.663439, 3.140797, 4.097848");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\
+ "0.152032, 0.152032, 0.152043, 0.152082, 0.152158",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\
+ "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\
+ "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\
+ "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\
+ "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\
+ "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\
+ "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\
+ "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\
+ "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222135");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.607646, 0.849717, 1.116124, 1.597554, 2.560414",\
+ "0.619007, 0.861079, 1.127484, 1.608912, 2.571767",\
+ "0.637745, 0.879816, 1.146220, 1.627645, 2.590494",\
+ "0.806293, 1.048363, 1.314763, 1.796177, 2.759006",\
+ "1.141102, 1.383173, 1.649573, 2.130988, 3.093818",\
+ "0.695047, 0.937194, 1.203726, 1.684267, 2.646348",\
+ "0.706409, 0.948555, 1.215086, 1.695625, 2.657701",\
+ "0.725146, 0.967293, 1.233822, 1.714358, 2.676428",\
+ "0.893694, 1.135840, 1.402365, 1.882890, 2.844940",\
+ "1.228504, 1.470650, 1.737175, 2.217701, 3.179752",\
+ "0.775854, 1.025975, 1.291688, 1.771888, 2.733303",\
+ "0.787216, 1.037337, 1.303049, 1.783245, 2.744656",\
+ "0.805953, 1.056074, 1.321785, 1.801978, 2.763383",\
+ "0.974501, 1.224621, 1.490328, 1.970511, 2.931895",\
+ "1.309311, 1.559431, 1.825138, 2.305322, 3.266707",\
+ "0.836149, 1.091318, 1.355830, 1.835800, 2.796812",\
+ "0.847510, 1.102679, 1.367190, 1.847158, 2.808165",\
+ "0.866248, 1.121417, 1.385927, 1.865891, 2.826892",\
+ "1.034796, 1.289964, 1.554469, 2.034424, 2.995404",\
+ "1.369605, 1.624774, 1.889280, 2.369234, 3.330216",\
+ "1.174050, 1.452400, 1.707819, 2.185190, 3.142268",\
+ "1.185411, 1.463761, 1.719179, 2.196548, 3.153621",\
+ "1.204149, 1.482498, 1.737915, 2.215281, 3.172348",\
+ "1.372697, 1.651045, 1.906458, 2.383814, 3.340860",\
+ "1.707507, 1.985855, 2.241268, 2.718624, 3.675672");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\
+ "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\
+ "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\
+ "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\
+ "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\
+ "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\
+ "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\
+ "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\
+ "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\
+ "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\
+ "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\
+ "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\
+ "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\
+ "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\
+ "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\
+ "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\
+ "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\
+ "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\
+ "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\
+ "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\
+ "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\
+ "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\
+ "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\
+ "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\
+ "1.025917, 1.025917, 1.025918, 1.025920, 1.025925");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2327*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[33]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.688394, 0.943298, 1.199532, 1.637805, 2.514353",\
+ "0.701988, 0.956891, 1.213125, 1.651399, 2.527946",\
+ "0.725528, 0.980432, 1.236665, 1.674939, 2.551486",\
+ "0.993065, 1.247969, 1.504202, 1.942475, 2.819022",\
+ "1.585529, 1.840433, 2.096666, 2.534938, 3.411482",\
+ "0.775799, 1.030785, 1.286999, 1.724519, 2.600287",\
+ "0.789393, 1.044379, 1.300593, 1.738113, 2.613880",\
+ "0.812933, 1.067919, 1.324133, 1.761653, 2.637420",\
+ "1.080470, 1.335456, 1.591670, 2.029189, 2.904955",\
+ "1.672934, 1.927920, 2.184134, 2.621652, 3.497416",\
+ "0.864143, 1.119604, 1.374960, 1.812140, 2.687242",\
+ "0.877736, 1.133197, 1.388554, 1.825734, 2.700835",\
+ "0.901277, 1.156737, 1.412094, 1.849274, 2.724375",\
+ "1.168814, 1.424274, 1.679631, 2.116810, 2.991910",\
+ "1.761278, 2.016739, 2.272095, 2.709273, 3.584371",\
+ "0.927637, 1.185001, 1.439095, 1.876053, 2.750751",\
+ "0.941231, 1.198595, 1.452689, 1.889647, 2.764344",\
+ "0.964771, 1.222135, 1.476229, 1.913187, 2.787884",\
+ "1.232308, 1.489672, 1.743766, 2.180723, 3.055419",\
+ "1.824772, 2.082136, 2.336229, 2.773186, 3.647880",\
+ "1.263060, 1.546678, 1.790648, 2.225268, 3.096207",\
+ "1.276654, 1.560272, 1.804242, 2.238862, 3.109800",\
+ "1.300194, 1.583812, 1.827782, 2.262402, 3.133340",\
+ "1.567731, 1.851349, 2.095319, 2.529938, 3.400876",\
+ "2.160195, 2.443813, 2.687783, 3.122401, 3.993336");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\
+ "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\
+ "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\
+ "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\
+ "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\
+ "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\
+ "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\
+ "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.629902, 0.884806, 1.141041, 1.579317, 2.455871",\
+ "0.641263, 0.896167, 1.152402, 1.590678, 2.467230",\
+ "0.660001, 0.914905, 1.171139, 1.609414, 2.485964",\
+ "0.828549, 1.083453, 1.339686, 1.777957, 2.654500",\
+ "1.163359, 1.418263, 1.674496, 2.112767, 2.989310",\
+ "0.717307, 0.972293, 1.228508, 1.666031, 2.541805",\
+ "0.728669, 0.983655, 1.239870, 1.677392, 2.553164",\
+ "0.747406, 1.002393, 1.258607, 1.696128, 2.571898",\
+ "0.915954, 1.170941, 1.427154, 1.864671, 2.740433",\
+ "1.250764, 1.505750, 1.761964, 2.199481, 3.075244",\
+ "0.805651, 1.061112, 1.316469, 1.753652, 2.628760",\
+ "0.817012, 1.072473, 1.327831, 1.765013, 2.640119",\
+ "0.835750, 1.091211, 1.346568, 1.783749, 2.658853",\
+ "1.004298, 1.259759, 1.515115, 1.952292, 2.827389",\
+ "1.339108, 1.594568, 1.849925, 2.287102, 3.162199",\
+ "0.869145, 1.126509, 1.380604, 1.817565, 2.692269",\
+ "0.880507, 1.137871, 1.391965, 1.828925, 2.703628",\
+ "0.899244, 1.156608, 1.410703, 1.847662, 2.722362",\
+ "1.067792, 1.325156, 1.579249, 2.016205, 2.890898",\
+ "1.402602, 1.659966, 1.914059, 2.351015, 3.225708",\
+ "1.204568, 1.488186, 1.732157, 2.166780, 3.037725",\
+ "1.215930, 1.499547, 1.743518, 2.178141, 3.049084",\
+ "1.234668, 1.518285, 1.762256, 2.196877, 3.067818",\
+ "1.403215, 1.686833, 1.930802, 2.365420, 3.236354",\
+ "1.738025, 2.021643, 2.265612, 2.700230, 3.571164");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\
+ "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\
+ "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\
+ "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\
+ "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\
+ "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\
+ "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\
+ "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\
+ "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\
+ "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\
+ "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\
+ "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\
+ "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\
+ "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\
+ "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\
+ "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\
+ "1.025917, 1.025917, 1.025917, 1.025917, 1.025916");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2344*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[37]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.195231, 0.463005, 0.734474, 1.195010, 2.116083",\
+ "0.209369, 0.477311, 0.748785, 1.209873, 2.132048",\
+ "0.233103, 0.501280, 0.772498, 1.233725, 2.156177",\
+ "0.505445, 0.772942, 1.041862, 1.499718, 2.415430",\
+ "1.101330, 1.368410, 1.636340, 2.092443, 3.004649",\
+ "0.282639, 0.550544, 0.822013, 1.281725, 2.202017",\
+ "0.296777, 0.564849, 0.836326, 1.296587, 2.217982",\
+ "0.320749, 0.588817, 0.860040, 1.320439, 2.242111",\
+ "0.593808, 0.860470, 1.129393, 1.586432, 2.501364",\
+ "1.189691, 1.455935, 1.723865, 2.179157, 3.090583",\
+ "0.371453, 0.639490, 0.909976, 1.369346, 2.288972",\
+ "0.385884, 0.653793, 0.924289, 1.384209, 2.304937",\
+ "0.410095, 0.677755, 0.948003, 1.408060, 2.329066",\
+ "0.683117, 0.949390, 1.217355, 1.674054, 2.588319",\
+ "1.278993, 1.544848, 1.811828, 2.266779, 3.177538",\
+ "0.435127, 0.705073, 0.974115, 1.433259, 2.352481",\
+ "0.449557, 0.719372, 0.988428, 1.448122, 2.368446",\
+ "0.473764, 0.743329, 1.012141, 1.471974, 2.392575",\
+ "0.746751, 1.014935, 1.281493, 1.737967, 2.651828",\
+ "1.342621, 1.610383, 1.875965, 2.330692, 3.241047",\
+ "0.771711, 1.068883, 1.325895, 1.782569, 2.697937",\
+ "0.786132, 1.083144, 1.340213, 1.797434, 2.713902",\
+ "0.810321, 1.107028, 1.363928, 1.821286, 2.738031",\
+ "1.083085, 1.378307, 1.633246, 2.087266, 2.997284",\
+ "1.678917, 1.973635, 2.227701, 2.679984, 3.586503");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.185659, 0.236480, 0.332306, 0.503768, 0.846690",\
+ "0.203762, 0.251201, 0.346416, 0.519962, 0.867054",\
+ "0.237818, 0.275998, 0.366817, 0.542132, 0.892761",\
+ "0.823305, 0.824108, 0.854501, 0.958291, 1.165871",\
+ "2.222180, 2.222247, 2.228687, 2.250859, 2.295203",\
+ "0.185659, 0.236778, 0.332846, 0.503768, 0.846690",\
+ "0.203762, 0.251491, 0.346963, 0.519962, 0.867054",\
+ "0.238090, 0.276257, 0.367369, 0.542132, 0.892761",\
+ "0.823322, 0.824110, 0.854828, 0.958291, 1.165871",\
+ "2.222181, 2.222247, 2.228756, 2.250859, 2.295203",\
+ "0.187582, 0.237448, 0.332856, 0.503768, 0.846690",\
+ "0.205428, 0.252143, 0.346973, 0.519962, 0.867054",\
+ "0.238891, 0.276838, 0.367379, 0.542132, 0.892761",\
+ "0.823369, 0.824113, 0.854835, 0.958291, 1.165871",\
+ "2.222186, 2.222247, 2.228758, 2.250859, 2.295203",\
+ "0.188921, 0.238422, 0.332885, 0.503768, 0.846690",\
+ "0.206588, 0.253091, 0.347002, 0.519962, 0.867054",\
+ "0.239638, 0.277682, 0.367409, 0.542132, 0.892761",\
+ "0.823414, 0.824119, 0.854852, 0.958291, 1.165871",\
+ "2.222191, 2.222247, 2.228761, 2.250859, 2.295203",\
+ "0.197449, 0.249827, 0.334624, 0.504477, 0.846690",\
+ "0.213977, 0.264195, 0.348763, 0.520680, 0.867054",\
+ "0.244398, 0.287568, 0.369187, 0.542857, 0.892761",\
+ "0.823697, 0.824180, 0.855905, 0.958721, 1.165871",\
+ "2.222221, 2.222247, 2.228986, 2.250950, 2.295203");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.199835, 0.394068, 0.663502, 1.119151, 2.030450",\
+ "0.208748, 0.404375, 0.677456, 1.139816, 2.064535",\
+ "0.223610, 0.421071, 0.699454, 1.171923, 2.116862",\
+ "0.380613, 0.582386, 0.880612, 1.405667, 2.455778",\
+ "0.716679, 0.922290, 1.228480, 1.784735, 2.897244",\
+ "0.287243, 0.481603, 0.751025, 1.205865, 2.116384",\
+ "0.296156, 0.491921, 0.765001, 1.226530, 2.150469",\
+ "0.311018, 0.508632, 0.787030, 1.258637, 2.202796",\
+ "0.468021, 0.669977, 0.968355, 1.492382, 2.541712",\
+ "0.804087, 1.009874, 1.316321, 1.871449, 2.983178",\
+ "0.368115, 0.570540, 0.838988, 1.293487, 2.203339",\
+ "0.377029, 0.580882, 0.852964, 1.314152, 2.237424",\
+ "0.391890, 0.597628, 0.874994, 1.346259, 2.289751",\
+ "0.548893, 0.759039, 1.056321, 1.580003, 2.628667",\
+ "0.884959, 1.098920, 1.404289, 1.959070, 3.070133",\
+ "0.425818, 0.636109, 0.903125, 1.357400, 2.266848",\
+ "0.434733, 0.646488, 0.917102, 1.378065, 2.300933",\
+ "0.449593, 0.663284, 0.939134, 1.410172, 2.353260",\
+ "0.606596, 0.824792, 1.120470, 1.643916, 2.692176",\
+ "0.942662, 1.164649, 1.468444, 2.022984, 3.133642",\
+ "0.728861, 0.999767, 1.254856, 1.706689, 2.612304",\
+ "0.737784, 1.010567, 1.268901, 1.727382, 2.646389",\
+ "0.752638, 1.027949, 1.291036, 1.759531, 2.698716",\
+ "0.909639, 1.190589, 1.472905, 1.993493, 3.037632",\
+ "1.245701, 1.530174, 1.821195, 2.372689, 3.479098");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.051713, 0.082206, 0.146667, 0.272496, 0.524154",\
+ "0.059242, 0.084148, 0.146833, 0.273232, 0.526032",\
+ "0.082676, 0.098099, 0.151707, 0.276480, 0.526025",\
+ "0.382075, 0.382564, 0.407345, 0.490228, 0.655996",\
+ "1.027888, 1.027888, 1.042321, 1.092011, 1.191392",\
+ "0.051713, 0.082387, 0.147063, 0.272496, 0.524154",\
+ "0.059242, 0.084316, 0.147231, 0.273232, 0.526032",\
+ "0.082676, 0.098212, 0.152100, 0.276480, 0.526025",\
+ "0.382075, 0.382568, 0.407606, 0.490228, 0.655996",\
+ "1.027888, 1.027888, 1.042477, 1.092011, 1.191392",\
+ "0.051782, 0.082793, 0.147071, 0.272496, 0.524154",\
+ "0.059284, 0.084694, 0.147238, 0.273232, 0.526032",\
+ "0.082697, 0.098465, 0.152108, 0.276480, 0.526025",\
+ "0.382075, 0.382579, 0.407611, 0.490228, 0.655996",\
+ "1.027888, 1.027888, 1.042480, 1.092011, 1.191392",\
+ "0.051916, 0.083384, 0.147092, 0.272496, 0.524154",\
+ "0.059368, 0.085243, 0.147259, 0.273232, 0.526032",\
+ "0.082738, 0.098832, 0.152128, 0.276480, 0.526025",\
+ "0.382075, 0.382594, 0.407625, 0.490228, 0.655996",\
+ "1.027888, 1.027888, 1.042489, 1.092011, 1.191392",\
+ "0.053133, 0.090301, 0.148368, 0.273016, 0.524154",\
+ "0.060124, 0.091679, 0.148542, 0.273755, 0.526032",\
+ "0.083110, 0.103136, 0.153394, 0.276996, 0.526025",\
+ "0.382075, 0.382769, 0.408465, 0.490571, 0.655996",\
+ "1.027888, 1.027888, 1.042993, 1.092217, 1.191392");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2530*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[40]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.737863, 1.003362, 1.291646, 1.782380, 2.763848",\
+ "0.751415, 1.016914, 1.305198, 1.795933, 2.777400",\
+ "0.774946, 1.040444, 1.328728, 1.819463, 2.800930",\
+ "1.042319, 1.307818, 1.596103, 2.086838, 3.068308",\
+ "1.636291, 1.901789, 2.190096, 2.680906, 3.662528",\
+ "0.825276, 1.090943, 1.379283, 1.869095, 2.849782",\
+ "0.838828, 1.104495, 1.392835, 1.882647, 2.863334",\
+ "0.862358, 1.128025, 1.416365, 1.906177, 2.886864",\
+ "1.129732, 1.395399, 1.683739, 2.173553, 3.154242",\
+ "1.723704, 1.989370, 2.277732, 2.767621, 3.748461",\
+ "0.906195, 1.180006, 1.467248, 1.956717, 2.936737",\
+ "0.919747, 1.193558, 1.480801, 1.970270, 2.950289",\
+ "0.943277, 1.217088, 1.504331, 1.993800, 2.973819",\
+ "1.210651, 1.484462, 1.771705, 2.261175, 3.241197",\
+ "1.804622, 2.078433, 2.365698, 2.855243, 3.835416",\
+ "0.966681, 1.245760, 1.531392, 2.020631, 3.000246",\
+ "0.980233, 1.259312, 1.544944, 2.034183, 3.013798",\
+ "1.003763, 1.282842, 1.568474, 2.057713, 3.037328",\
+ "1.271137, 1.550216, 1.835848, 2.325089, 3.304706",\
+ "1.865109, 2.144188, 2.429842, 2.919157, 3.898925",\
+ "1.301775, 1.611517, 1.883481, 2.370070, 3.345702",\
+ "1.315328, 1.625069, 1.897033, 2.383622, 3.359254",\
+ "1.338858, 1.648599, 1.920563, 2.407152, 3.382784",\
+ "1.606231, 1.915973, 2.187937, 2.674527, 3.650162",\
+ "2.200203, 2.509944, 2.781931, 3.268596, 4.244381");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\
+ "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\
+ "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\
+ "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\
+ "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\
+ "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\
+ "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\
+ "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\
+ "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\
+ "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\
+ "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\
+ "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\
+ "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\
+ "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\
+ "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\
+ "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.705640, 0.971139, 1.259445, 1.750256, 2.731876",\
+ "0.713583, 0.979081, 1.267388, 1.758198, 2.739818",\
+ "0.727063, 0.992561, 1.280868, 1.771678, 2.753298",\
+ "0.881016, 1.146515, 1.434821, 1.925632, 2.907252",\
+ "1.220917, 1.486415, 1.774721, 2.265532, 3.247153",\
+ "0.793053, 1.058720, 1.347082, 1.836970, 2.817810",\
+ "0.800995, 1.066662, 1.355024, 1.844913, 2.825752",\
+ "0.814475, 1.080142, 1.368504, 1.858393, 2.839232",\
+ "0.968429, 1.234096, 1.522458, 2.012346, 2.993186",\
+ "1.308329, 1.573996, 1.862358, 2.352247, 3.333086",\
+ "0.873972, 1.147783, 1.435048, 1.924593, 2.904765",\
+ "0.881914, 1.155725, 1.442990, 1.932535, 2.912707",\
+ "0.895394, 1.169205, 1.456470, 1.946015, 2.926187",\
+ "1.049348, 1.323159, 1.610423, 2.099968, 3.080141",\
+ "1.389248, 1.663059, 1.950324, 2.439869, 3.420042",\
+ "0.934458, 1.213537, 1.499191, 1.988506, 2.968274",\
+ "0.942401, 1.221480, 1.507133, 1.996449, 2.976216",\
+ "0.955880, 1.234959, 1.520613, 2.009929, 2.989696",\
+ "1.109834, 1.388913, 1.674567, 2.163882, 3.143650",\
+ "1.449734, 1.728813, 2.014467, 2.503783, 3.483551",\
+ "1.269552, 1.579294, 1.851281, 2.337945, 3.313730",\
+ "1.277495, 1.587236, 1.859223, 2.345888, 3.321672",\
+ "1.290975, 1.600716, 1.872703, 2.359368, 3.335152",\
+ "1.444928, 1.754670, 2.026657, 2.513321, 3.489106",\
+ "1.784829, 2.094570, 2.366557, 2.853222, 3.829007");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.061214, 0.061214, 0.061208, 0.061187, 0.061144",\
+ "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\
+ "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\
+ "0.061214, 0.061214, 0.061207, 0.061187, 0.061144",\
+ "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\
+ "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\
+ "0.061214, 0.061214, 0.061207, 0.061187, 0.061144",\
+ "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\
+ "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\
+ "0.061214, 0.061214, 0.061207, 0.061187, 0.061144",\
+ "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\
+ "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\
+ "0.061214, 0.061214, 0.061207, 0.061186, 0.061144",\
+ "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\
+ "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2668*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[44]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.109772, 0.369798, 0.626503, 1.061758, 1.932266",\
+ "0.120352, 0.381519, 0.640958, 1.080478, 1.959519",\
+ "0.143356, 0.404296, 0.665874, 1.109884, 1.997905",\
+ "0.467994, 0.696012, 0.968260, 1.421863, 2.329069",\
+ "1.081974, 1.301531, 1.593583, 2.086339, 3.071851",\
+ "0.198042, 0.457293, 0.713962, 1.148472, 2.018200",\
+ "0.208624, 0.469024, 0.728430, 1.167192, 2.045453",\
+ "0.231607, 0.491807, 0.753360, 1.196598, 2.083839",\
+ "0.555400, 0.783574, 1.055776, 1.508577, 2.415003",\
+ "1.169380, 1.389148, 1.681223, 2.173053, 3.157785",\
+ "0.287235, 0.546131, 0.801923, 1.236093, 2.105155",\
+ "0.297824, 0.557883, 0.816391, 1.254813, 2.132408",\
+ "0.320747, 0.580678, 0.841322, 1.284219, 2.170794",\
+ "0.636219, 0.872561, 1.143739, 1.596198, 2.501958",\
+ "1.250216, 1.478256, 1.769187, 2.260674, 3.244740",\
+ "0.350832, 0.611557, 0.866057, 1.300006, 2.168664",\
+ "0.361428, 0.623341, 0.880526, 1.318726, 2.195917",\
+ "0.384293, 0.646153, 0.905457, 1.348132, 2.234303",\
+ "0.693839, 0.938203, 1.207876, 1.660111, 2.565467",\
+ "1.307871, 1.544076, 1.833331, 2.324587, 3.308249",\
+ "0.686914, 0.973559, 1.217580, 1.649209, 2.514120",\
+ "0.697552, 0.985713, 1.232092, 1.667947, 2.541373",\
+ "0.720052, 1.008731, 1.257069, 1.697372, 2.579759",\
+ "1.005905, 1.302737, 1.559584, 2.009390, 2.910923",\
+ "1.610583, 1.910693, 2.185437, 2.674028, 3.653705");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.074635, 0.092924, 0.146295, 0.240037, 0.427522",\
+ "0.102546, 0.120314, 0.177030, 0.284760, 0.500219",\
+ "0.161902, 0.174975, 0.229446, 0.352350, 0.598157",\
+ "0.823637, 0.823637, 0.866693, 1.014155, 1.309078",\
+ "2.221941, 2.221941, 2.244858, 2.323347, 2.480325",\
+ "0.074635, 0.093094, 0.146590, 0.240037, 0.427522",\
+ "0.102546, 0.120480, 0.177368, 0.284760, 0.500219",\
+ "0.161902, 0.175097, 0.229832, 0.352350, 0.598157",\
+ "0.823637, 0.823637, 0.867157, 1.014155, 1.309078",\
+ "2.221941, 2.221941, 2.245105, 2.323347, 2.480325",\
+ "0.074635, 0.093474, 0.146595, 0.240037, 0.427522",\
+ "0.102546, 0.120849, 0.177375, 0.284760, 0.500219",\
+ "0.161902, 0.175368, 0.229839, 0.352350, 0.598157",\
+ "0.823637, 0.823637, 0.867165, 1.014155, 1.309078",\
+ "2.221941, 2.221941, 2.245110, 2.323347, 2.480325",\
+ "0.074635, 0.094026, 0.146611, 0.240037, 0.427522",\
+ "0.102546, 0.121384, 0.177393, 0.284760, 0.500219",\
+ "0.161902, 0.175763, 0.229860, 0.352350, 0.598157",\
+ "0.823637, 0.823637, 0.867190, 1.014155, 1.309078",\
+ "2.221941, 2.221941, 2.245123, 2.323347, 2.480325",\
+ "0.074635, 0.100491, 0.147562, 0.240424, 0.427522",\
+ "0.102546, 0.127666, 0.178485, 0.285204, 0.500219",\
+ "0.161902, 0.180384, 0.231107, 0.352857, 0.598157",\
+ "0.823637, 0.823637, 0.868686, 1.014764, 1.309078",\
+ "2.221941, 2.221941, 2.245919, 2.323671, 2.480325");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.141728, 0.322683, 0.508414, 0.851578, 1.569056",\
+ "0.147760, 0.329649, 0.526344, 0.903425, 1.657587",\
+ "0.158195, 0.340967, 0.571363, 0.971528, 1.771856",\
+ "0.298823, 0.523674, 0.808829, 1.303379, 2.292479",\
+ "0.636132, 0.863255, 1.152943, 1.685611, 2.750947",\
+ "0.229134, 0.410071, 0.595881, 0.938291, 1.654990",\
+ "0.235166, 0.417039, 0.613620, 0.990139, 1.743521",\
+ "0.245601, 0.428357, 0.658712, 1.058241, 1.857790",\
+ "0.386229, 0.611242, 0.896475, 1.390093, 2.378412",\
+ "0.723538, 0.950780, 1.240708, 1.772325, 2.836881",\
+ "0.309995, 0.490402, 0.675907, 1.025913, 1.741945",\
+ "0.316032, 0.497370, 0.701577, 1.077760, 1.830476",\
+ "0.326472, 0.511248, 0.746671, 1.145863, 1.944745",\
+ "0.467101, 0.700242, 0.984439, 1.477714, 2.465368",\
+ "0.804387, 1.039684, 1.328675, 1.859946, 2.923836",\
+ "0.367698, 0.547951, 0.733450, 1.089826, 1.805454",\
+ "0.373747, 0.554919, 0.765701, 1.141673, 1.893985",\
+ "0.384198, 0.576458, 0.810799, 1.209776, 2.008254",\
+ "0.524826, 0.765905, 1.048583, 1.541627, 2.528877",\
+ "0.862067, 1.105206, 1.392825, 1.923859, 2.987345",\
+ "0.670854, 0.880709, 1.082881, 1.438713, 2.150910",\
+ "0.677008, 0.904085, 1.116634, 1.490636, 2.239441",\
+ "0.687558, 0.935916, 1.161966, 1.558834, 2.353710",\
+ "0.834408, 1.130676, 1.400707, 1.891076, 2.874332",\
+ "1.178988, 1.468337, 1.745336, 2.273465, 3.332801");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.063168, 0.063168, 0.086452, 0.196369, 0.354186",\
+ "0.068741, 0.068741, 0.139232, 0.228666, 0.407534",\
+ "0.084603, 0.084603, 0.171201, 0.272810, 0.476028",\
+ "0.381099, 0.384063, 0.433028, 0.586290, 0.892815",\
+ "1.028844, 1.028844, 1.069845, 1.210271, 1.491123",\
+ "0.063168, 0.063168, 0.086512, 0.196369, 0.354186",\
+ "0.068741, 0.068741, 0.139513, 0.228666, 0.407534",\
+ "0.084603, 0.084603, 0.171521, 0.272810, 0.476028",\
+ "0.381099, 0.384091, 0.433510, 0.586290, 0.892815",\
+ "1.028844, 1.028844, 1.070287, 1.210271, 1.491123",\
+ "0.063168, 0.063168, 0.086512, 0.196369, 0.354186",\
+ "0.068741, 0.068741, 0.139518, 0.228666, 0.407534",\
+ "0.084603, 0.108819, 0.171527, 0.272810, 0.476028",\
+ "0.381099, 0.384153, 0.433519, 0.586290, 0.892815",\
+ "1.028844, 1.028844, 1.070295, 1.210271, 1.491123",\
+ "0.063168, 0.063168, 0.086512, 0.196369, 0.354186",\
+ "0.068741, 0.068741, 0.139534, 0.228666, 0.407534",\
+ "0.084603, 0.109528, 0.171544, 0.272810, 0.476028",\
+ "0.381099, 0.384242, 0.433545, 0.586290, 0.892815",\
+ "1.028844, 1.028844, 1.070319, 1.210271, 1.491123",\
+ "0.063168, 0.081414, 0.118527, 0.196695, 0.354186",\
+ "0.068741, 0.094649, 0.140441, 0.229035, 0.407534",\
+ "0.084603, 0.117839, 0.172574, 0.273230, 0.476028",\
+ "0.381099, 0.385290, 0.435099, 0.586923, 0.892815",\
+ "1.028844, 1.028844, 1.071743, 1.210851, 1.491123");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2709*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[45]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.715344, 0.975445, 1.253880, 1.716396, 2.641427",\
+ "0.728896, 0.988997, 1.267432, 1.729948, 2.654979",\
+ "0.752427, 1.012527, 1.290962, 1.753478, 2.678509",\
+ "1.019800, 1.279901, 1.558336, 2.020853, 2.945885",\
+ "1.613771, 1.873872, 2.152319, 2.614874, 3.539985",\
+ "0.802750, 1.063030, 1.341425, 1.803109, 2.727360",\
+ "0.816303, 1.076582, 1.354977, 1.816662, 2.740913",\
+ "0.839833, 1.100112, 1.378507, 1.840192, 2.764443",\
+ "1.107206, 1.367486, 1.645881, 2.107566, 3.031819",\
+ "1.701178, 1.961458, 2.239864, 2.701588, 3.625918",\
+ "0.883600, 1.152069, 1.429387, 1.890731, 2.814316",\
+ "0.897153, 1.165621, 1.442940, 1.904283, 2.827868",\
+ "0.920683, 1.189151, 1.466470, 1.927813, 2.851398",\
+ "1.188056, 1.456525, 1.733844, 2.195188, 3.118774",\
+ "1.782027, 2.050497, 2.327826, 2.789209, 3.712873",\
+ "0.945225, 1.217787, 1.493526, 1.954644, 2.877825",\
+ "0.958777, 1.231339, 1.507078, 1.968196, 2.891377",\
+ "0.982307, 1.254869, 1.530608, 1.991726, 2.914907",\
+ "1.249681, 1.522243, 1.797982, 2.259101, 3.182283",\
+ "1.843652, 2.116215, 2.391965, 2.853122, 3.776382",\
+ "1.282097, 1.583212, 1.845325, 2.303960, 3.223280",\
+ "1.295649, 1.596764, 1.858877, 2.317512, 3.236833",\
+ "1.319179, 1.620294, 1.882407, 2.341042, 3.260363",\
+ "1.586553, 1.887668, 2.149781, 2.608417, 3.527739",\
+ "2.180524, 2.481639, 2.743765, 3.202439, 4.121839");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\
+ "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\
+ "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\
+ "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\
+ "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\
+ "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\
+ "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\
+ "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\
+ "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\
+ "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\
+ "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\
+ "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\
+ "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\
+ "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\
+ "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\
+ "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\
+ "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\
+ "2.222134, 2.222134, 2.222134, 2.222134, 2.222134");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.683121, 0.943222, 1.221668, 1.684223, 2.609334",\
+ "0.691063, 0.951164, 1.229611, 1.692166, 2.617276",\
+ "0.704543, 0.964644, 1.243091, 1.705646, 2.630756",\
+ "0.858497, 1.118598, 1.397044, 1.859599, 2.784709",\
+ "1.198397, 1.458498, 1.736945, 2.199500, 3.124610",\
+ "0.770527, 1.030807, 1.309213, 1.770937, 2.695267",\
+ "0.778469, 1.038749, 1.317156, 1.778880, 2.703210",\
+ "0.791949, 1.052229, 1.330636, 1.792360, 2.716690",\
+ "0.945903, 1.206183, 1.484589, 1.946313, 2.870643",\
+ "1.285803, 1.546083, 1.824489, 2.286213, 3.210544",\
+ "0.851377, 1.119846, 1.397176, 1.858559, 2.782223",\
+ "0.859320, 1.127788, 1.405118, 1.866501, 2.790165",\
+ "0.872799, 1.141268, 1.418598, 1.879981, 2.803645",\
+ "1.026753, 1.295222, 1.572552, 2.033935, 2.957598",\
+ "1.366653, 1.635122, 1.912452, 2.373835, 3.297499",\
+ "0.913002, 1.185564, 1.461314, 1.922472, 2.845731",\
+ "0.920944, 1.193506, 1.469257, 1.930414, 2.853674",\
+ "0.934424, 1.206986, 1.482737, 1.943894, 2.867154",\
+ "1.088378, 1.360940, 1.636690, 2.097847, 3.021107",\
+ "1.428278, 1.700840, 1.976590, 2.437748, 3.361008",\
+ "1.249874, 1.550989, 1.813114, 2.271788, 3.191187",\
+ "1.257816, 1.558931, 1.821056, 2.279730, 3.199130",\
+ "1.271296, 1.572411, 1.834536, 2.293210, 3.212610",\
+ "1.425250, 1.726365, 1.988490, 2.447164, 3.366563",\
+ "1.765150, 2.066265, 2.328390, 2.787064, 3.706464");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\
+ "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\
+ "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\
+ "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\
+ "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\
+ "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\
+ "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\
+ "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\
+ "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\
+ "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\
+ "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\
+ "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\
+ "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\
+ "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\
+ "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\
+ "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\
+ "1.025894, 1.025894, 1.025894, 1.025894, 1.025894");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2681*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[16]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.385362, 0.574573, 0.765319, 1.061205, 1.627908",\
+ "0.404628, 0.593839, 0.784585, 1.080471, 1.647174",\
+ "0.436306, 0.625517, 0.816263, 1.112149, 1.678852",\
+ "0.725958, 0.915169, 1.105914, 1.401800, 1.968502",\
+ "1.319903, 1.509114, 1.699858, 1.995744, 2.562446",\
+ "0.473615, 0.661891, 0.852600, 1.148510, 1.715261",\
+ "0.492881, 0.681157, 0.871866, 1.167776, 1.734527",\
+ "0.524560, 0.712836, 0.903544, 1.199454, 1.766205",\
+ "0.814212, 1.002488, 1.193195, 1.489105, 2.055855",\
+ "1.408156, 1.596432, 1.787139, 2.083049, 2.649799",\
+ "0.562261, 0.742226, 0.932626, 1.228538, 1.795292",\
+ "0.581527, 0.761492, 0.951893, 1.247805, 1.814559",\
+ "0.613206, 0.793171, 0.983571, 1.279483, 1.846237",\
+ "0.902858, 1.082823, 1.273222, 1.569133, 2.135887",\
+ "1.496802, 1.676767, 1.867166, 2.163077, 2.729831",\
+ "0.620370, 0.800057, 0.990350, 1.285975, 1.852322",\
+ "0.639636, 0.819323, 1.009616, 1.305241, 1.871588",\
+ "0.671315, 0.851002, 1.041294, 1.336920, 1.903266",\
+ "0.960967, 1.140654, 1.330945, 1.626570, 2.192916",\
+ "1.554911, 1.734598, 1.924889, 2.220514, 2.786860",\
+ "0.922623, 1.105385, 1.294011, 1.589153, 2.154560",\
+ "0.941889, 1.124651, 1.313277, 1.608420, 2.173826",\
+ "0.973567, 1.156330, 1.344955, 1.640098, 2.205504",\
+ "1.263219, 1.445982, 1.634606, 1.929748, 2.495154",\
+ "1.857164, 2.039926, 2.228550, 2.523692, 3.089098");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\
+ "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\
+ "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\
+ "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\
+ "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\
+ "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\
+ "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\
+ "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\
+ "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\
+ "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\
+ "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\
+ "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\
+ "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\
+ "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\
+ "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195570, 2.195570, 2.195569, 2.195569, 2.195568");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.395642, 0.585187, 0.775931, 1.071620, 1.637841",\
+ "0.403773, 0.592984, 0.783728, 1.079613, 1.646315",\
+ "0.417192, 0.606403, 0.797147, 1.093032, 1.659734",\
+ "0.569868, 0.759079, 0.949823, 1.245708, 1.812411",\
+ "0.903831, 1.093042, 1.283787, 1.579672, 2.146375",\
+ "0.483904, 0.672505, 0.863212, 1.158925, 1.725194",\
+ "0.492026, 0.680302, 0.871009, 1.166918, 1.733668",\
+ "0.505446, 0.693722, 0.884428, 1.180337, 1.747088",\
+ "0.658121, 0.846397, 1.037104, 1.333013, 1.899764",\
+ "0.992085, 1.180361, 1.371068, 1.666977, 2.233728",\
+ "0.572576, 0.752841, 0.943239, 1.238954, 1.805226",\
+ "0.580672, 0.760637, 0.951036, 1.246946, 1.813700",\
+ "0.594092, 0.774057, 0.964455, 1.260366, 1.827119",\
+ "0.746767, 0.926732, 1.117131, 1.413042, 1.979796",\
+ "1.080731, 1.260696, 1.451095, 1.747006, 2.313760",\
+ "0.630984, 0.810671, 1.000962, 1.296390, 1.862254",\
+ "0.638781, 0.818468, 1.008759, 1.304383, 1.870729",\
+ "0.652200, 0.831887, 1.022178, 1.317803, 1.884149",\
+ "0.804876, 0.984563, 1.174854, 1.470479, 2.036825",\
+ "1.138840, 1.318527, 1.508818, 1.804443, 2.370789",\
+ "0.933237, 1.115999, 1.304623, 1.599568, 2.164490",\
+ "0.941034, 1.123796, 1.312420, 1.607561, 2.172967",\
+ "0.954453, 1.137215, 1.325839, 1.620981, 2.186387",\
+ "1.107129, 1.289891, 1.478515, 1.773657, 2.339063",\
+ "1.441092, 1.623855, 1.812479, 2.107621, 2.673027");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\
+ "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\
+ "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\
+ "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\
+ "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2495*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[20]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.535388, 0.757178, 0.935245, 1.224116, 1.784806",\
+ "0.554760, 0.776550, 0.954617, 1.243488, 1.804178",\
+ "0.586214, 0.808003, 0.986070, 1.274942, 1.835631",\
+ "0.875148, 1.096938, 1.275005, 1.563877, 2.124566",\
+ "1.469041, 1.690830, 1.868897, 2.157769, 2.718458",\
+ "0.623792, 0.844496, 1.022526, 1.311421, 1.872159",\
+ "0.643164, 0.863868, 1.041898, 1.330793, 1.891531",\
+ "0.674618, 0.895322, 1.073351, 1.362247, 1.922985",\
+ "0.963552, 1.184257, 1.362286, 1.651182, 2.211919",\
+ "1.557444, 1.778149, 1.956178, 2.245074, 2.805811",\
+ "0.712864, 0.924832, 1.102553, 1.391450, 1.952191",\
+ "0.732236, 0.944203, 1.121924, 1.410822, 1.971563",\
+ "0.763690, 0.975657, 1.153378, 1.442276, 2.003016",\
+ "1.052624, 1.264592, 1.442313, 1.731210, 2.291951",\
+ "1.646516, 1.858484, 2.036205, 2.325102, 2.885843",\
+ "0.776122, 0.982654, 1.160246, 1.448879, 2.009206",\
+ "0.795494, 1.002026, 1.179617, 1.468251, 2.028577",\
+ "0.826948, 1.033479, 1.211071, 1.499705, 2.060031",\
+ "1.115882, 1.322414, 1.500006, 1.788640, 2.348966",\
+ "1.709774, 1.916306, 2.093898, 2.382532, 2.942858",\
+ "1.107140, 1.287923, 1.463902, 1.752051, 2.311426",\
+ "1.126512, 1.307295, 1.483274, 1.771423, 2.330798",\
+ "1.157965, 1.338748, 1.514728, 1.802877, 2.362252",\
+ "1.446900, 1.627683, 1.803662, 2.091812, 2.651186",\
+ "2.040792, 2.221575, 2.397554, 2.685704, 3.245078");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.544632, 0.766422, 0.944489, 1.233360, 1.794050",\
+ "0.552443, 0.774232, 0.952299, 1.241171, 1.801860",\
+ "0.565862, 0.787651, 0.965718, 1.254590, 1.815279",\
+ "0.718832, 0.940622, 1.118689, 1.407560, 1.968250",\
+ "1.052901, 1.274690, 1.452757, 1.741629, 2.302318",\
+ "0.633036, 0.853740, 1.031770, 1.320665, 1.881403",\
+ "0.640847, 0.861551, 1.039580, 1.328476, 1.889213",\
+ "0.654266, 0.874970, 1.052999, 1.341895, 1.902633",\
+ "0.807236, 1.027940, 1.205970, 1.494865, 2.055603",\
+ "1.141305, 1.362009, 1.540038, 1.828934, 2.389672",\
+ "0.722108, 0.934075, 1.111796, 1.400694, 1.961435",\
+ "0.729918, 0.941886, 1.119607, 1.408504, 1.969245",\
+ "0.743338, 0.955305, 1.133026, 1.421923, 1.982664",\
+ "0.896308, 1.108276, 1.285997, 1.574894, 2.135635",\
+ "1.230376, 1.442344, 1.620065, 1.908962, 2.469703",\
+ "0.785366, 0.991898, 1.169490, 1.458123, 2.018450",\
+ "0.793177, 0.999708, 1.177300, 1.465934, 2.026260",\
+ "0.806596, 1.013127, 1.190719, 1.479353, 2.039679",\
+ "0.959566, 1.166098, 1.343690, 1.632324, 2.192650",\
+ "1.293635, 1.500166, 1.677758, 1.966392, 2.526718",\
+ "1.116384, 1.297167, 1.473146, 1.761295, 2.320670",\
+ "1.124194, 1.304977, 1.480956, 1.769106, 2.328480",\
+ "1.137613, 1.318397, 1.494376, 1.782525, 2.341900",\
+ "1.290584, 1.471367, 1.647346, 1.935495, 2.494870",\
+ "1.624652, 1.805435, 1.981414, 2.269564, 2.828938");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2650*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[22]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.511815, 0.739156, 0.923211, 1.217666, 1.786831",\
+ "0.531187, 0.758528, 0.942583, 1.237038, 1.806203",\
+ "0.562641, 0.789981, 0.974037, 1.268491, 1.837657",\
+ "0.851575, 1.078916, 1.262971, 1.557426, 2.126591",\
+ "1.445467, 1.672808, 1.856863, 2.151318, 2.720483",\
+ "0.600144, 0.826474, 1.010492, 1.304971, 1.874184",\
+ "0.619516, 0.845846, 1.029864, 1.324343, 1.893556",\
+ "0.650970, 0.877300, 1.061317, 1.355796, 1.925010",\
+ "0.939904, 1.166234, 1.350252, 1.644731, 2.213945",\
+ "1.533796, 1.760126, 1.944144, 2.238623, 2.807837",\
+ "0.689248, 0.906807, 1.090519, 1.384999, 1.954216",\
+ "0.708620, 0.926179, 1.109891, 1.404371, 1.973588",\
+ "0.740074, 0.957633, 1.141344, 1.435825, 2.005042",\
+ "1.029009, 1.246567, 1.430279, 1.724759, 2.293976",\
+ "1.622900, 1.840459, 2.024171, 2.318651, 2.887868",\
+ "0.752647, 0.964632, 1.148227, 1.442439, 2.011252",\
+ "0.772019, 0.984004, 1.167598, 1.461811, 2.030624",\
+ "0.803473, 1.015458, 1.199052, 1.493265, 2.062078",\
+ "1.092407, 1.304392, 1.487987, 1.782200, 2.351013",\
+ "1.686299, 1.898284, 2.081879, 2.376091, 2.944905",\
+ "1.087484, 1.269911, 1.451885, 1.745620, 2.313499",\
+ "1.106856, 1.289283, 1.471256, 1.764992, 2.332871",\
+ "1.138310, 1.320737, 1.502710, 1.796445, 2.364325",\
+ "1.427244, 1.609671, 1.791645, 2.085380, 2.653259",\
+ "2.021136, 2.203563, 2.385537, 2.679272, 3.247151");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.521059, 0.748400, 0.932455, 1.226910, 1.796075",\
+ "0.528870, 0.756210, 0.940265, 1.234720, 1.803885",\
+ "0.542289, 0.769629, 0.953685, 1.248139, 1.817305",\
+ "0.695259, 0.922600, 1.106655, 1.401110, 1.970275",\
+ "1.029328, 1.256668, 1.440723, 1.735178, 2.304343",\
+ "0.609388, 0.835718, 1.019736, 1.314215, 1.883428",\
+ "0.617199, 0.843528, 1.027546, 1.322025, 1.891239",\
+ "0.630618, 0.856948, 1.040965, 1.335444, 1.904658",\
+ "0.783588, 1.009918, 1.193936, 1.488415, 2.057629",\
+ "1.117657, 1.343987, 1.528004, 1.822483, 2.391697",\
+ "0.698492, 0.916051, 1.099763, 1.394243, 1.963460",\
+ "0.706303, 0.923862, 1.107573, 1.402054, 1.971270",\
+ "0.719722, 0.937281, 1.120992, 1.415473, 1.984690",\
+ "0.872692, 1.090251, 1.273963, 1.568443, 2.137660",\
+ "1.206761, 1.424320, 1.608031, 1.902512, 2.471728",\
+ "0.761891, 0.973876, 1.157471, 1.451683, 2.020496",\
+ "0.769701, 0.981686, 1.165281, 1.459494, 2.028307",\
+ "0.783120, 0.995106, 1.178700, 1.472913, 2.041726",\
+ "0.936091, 1.148076, 1.331671, 1.625883, 2.194696",\
+ "1.270159, 1.482144, 1.665739, 1.959952, 2.528765",\
+ "1.096728, 1.279155, 1.461128, 1.754864, 2.322743",\
+ "1.104538, 1.286965, 1.468939, 1.762674, 2.330553",\
+ "1.117958, 1.300385, 1.482358, 1.776093, 2.343972",\
+ "1.270928, 1.453355, 1.635329, 1.929064, 2.496943",\
+ "1.604996, 1.787423, 1.969397, 2.263132, 2.831011");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2744*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[23]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.459602, 0.694897, 0.884768, 1.189946, 1.780432",\
+ "0.478889, 0.714184, 0.904055, 1.209233, 1.799719",\
+ "0.510523, 0.745818, 0.935689, 1.240867, 1.831353",\
+ "0.800033, 1.035329, 1.225199, 1.530377, 2.120863",\
+ "1.393967, 1.629262, 1.819133, 2.124311, 2.714797",\
+ "0.548080, 0.782215, 0.972049, 1.277251, 1.867785",\
+ "0.567367, 0.801502, 0.991336, 1.296538, 1.887073",\
+ "0.599001, 0.833136, 1.022970, 1.328172, 1.918707",\
+ "0.888512, 1.122647, 1.312480, 1.617682, 2.208217",\
+ "1.482446, 1.716581, 1.906414, 2.211616, 2.802151",\
+ "0.637650, 0.862548, 1.052076, 1.357279, 1.947817",\
+ "0.656937, 0.881835, 1.071363, 1.376566, 1.967104",\
+ "0.688571, 0.913469, 1.102997, 1.408201, 1.998738",\
+ "0.978081, 1.202980, 1.392507, 1.697711, 2.288249",\
+ "1.572015, 1.796914, 1.986441, 2.291645, 2.882183",\
+ "0.701494, 0.920383, 1.109797, 1.414745, 2.004905",\
+ "0.720781, 0.939670, 1.129084, 1.434032, 2.024192",\
+ "0.752415, 0.971304, 1.160718, 1.465667, 2.055826",\
+ "1.041925, 1.260814, 1.450228, 1.755177, 2.345336",\
+ "1.635859, 1.854748, 2.044163, 2.349111, 2.939270",\
+ "1.039162, 1.225730, 1.413457, 1.717948, 2.307214",\
+ "1.058449, 1.245017, 1.432744, 1.737235, 2.326501",\
+ "1.090083, 1.276651, 1.464378, 1.768869, 2.358135",\
+ "1.379594, 1.566161, 1.753889, 2.058379, 2.647645",\
+ "1.973528, 2.160095, 2.347823, 2.652313, 3.241579");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.469945, 0.705240, 0.895111, 1.200289, 1.790776",\
+ "0.477744, 0.713040, 0.902911, 1.208089, 1.798575",\
+ "0.491164, 0.726459, 0.916330, 1.221508, 1.811994",\
+ "0.643898, 0.879193, 1.069064, 1.374242, 1.964728",\
+ "0.977882, 1.213178, 1.403048, 1.708226, 2.298713",\
+ "0.558424, 0.792559, 0.982392, 1.287594, 1.878129",\
+ "0.566223, 0.800358, 0.990192, 1.295394, 1.885928",\
+ "0.579643, 0.813778, 1.003611, 1.308813, 1.899348",\
+ "0.732376, 0.966511, 1.156345, 1.461547, 2.052081",\
+ "1.066361, 1.300496, 1.490329, 1.795531, 2.386066",\
+ "0.647993, 0.872891, 1.062419, 1.367623, 1.958161",\
+ "0.655793, 0.880691, 1.070219, 1.375422, 1.965960",\
+ "0.669212, 0.894110, 1.083638, 1.388842, 1.979379",\
+ "0.821946, 1.046844, 1.236372, 1.541575, 2.132113",\
+ "1.155930, 1.380829, 1.570356, 1.875560, 2.466098",\
+ "0.711837, 0.930726, 1.120141, 1.425089, 2.015248",\
+ "0.719636, 0.938526, 1.127940, 1.432888, 2.023048",\
+ "0.733056, 0.951945, 1.141359, 1.446308, 2.036467",\
+ "0.885790, 1.104679, 1.294093, 1.599041, 2.189201",\
+ "1.219774, 1.438663, 1.628078, 1.933026, 2.523185",\
+ "1.049506, 1.236073, 1.423800, 1.728291, 2.317557",\
+ "1.057305, 1.243873, 1.431600, 1.736091, 2.325356",\
+ "1.070724, 1.257292, 1.445019, 1.749510, 2.338776",\
+ "1.223458, 1.410026, 1.597753, 1.902244, 2.491510",\
+ "1.557443, 1.744010, 1.931738, 2.236228, 2.825494");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[25]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.443166, 0.674145, 0.859025, 1.158118, 1.738072",\
+ "0.462453, 0.693432, 0.878312, 1.177405, 1.757359",\
+ "0.494087, 0.725066, 0.909946, 1.209039, 1.788993",\
+ "0.783598, 1.014576, 1.199456, 1.498549, 2.078503",\
+ "1.377531, 1.608510, 1.793390, 2.092483, 2.672437",\
+ "0.531545, 0.761463, 0.946306, 1.245423, 1.825425",\
+ "0.550832, 0.780750, 0.965593, 1.264710, 1.844712",\
+ "0.582466, 0.812384, 0.997227, 1.296344, 1.876346",\
+ "0.871976, 1.101894, 1.286737, 1.585854, 2.165856",\
+ "1.465910, 1.695828, 1.880671, 2.179788, 2.759790",\
+ "0.621124, 0.841793, 1.026333, 1.325452, 1.905457",\
+ "0.640411, 0.861080, 1.045620, 1.344739, 1.924744",\
+ "0.672045, 0.892714, 1.077254, 1.376373, 1.956378",\
+ "0.961555, 1.182224, 1.366764, 1.665883, 2.245888",\
+ "1.555489, 1.776158, 1.960698, 2.259817, 2.839822",\
+ "0.685109, 0.899623, 1.084043, 1.382905, 1.962520",\
+ "0.704396, 0.918910, 1.103330, 1.402192, 1.981807",\
+ "0.736030, 0.950545, 1.134964, 1.433826, 2.013442",\
+ "1.025540, 1.240054, 1.424474, 1.723336, 2.302952",\
+ "1.619474, 1.833988, 2.018408, 2.317270, 2.896885",\
+ "1.023662, 1.204930, 1.387700, 1.686096, 2.264800",\
+ "1.042949, 1.224217, 1.406987, 1.705384, 2.284087",\
+ "1.074583, 1.255852, 1.438621, 1.737018, 2.315721",\
+ "1.364093, 1.545362, 1.728131, 2.026528, 2.605231",\
+ "1.958027, 2.139296, 2.322065, 2.620461, 3.199165");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.453509, 0.684488, 0.869368, 1.168461, 1.748415",\
+ "0.461309, 0.692287, 0.877167, 1.176260, 1.756214",\
+ "0.474728, 0.705707, 0.890586, 1.189680, 1.769634",\
+ "0.627462, 0.858441, 1.043320, 1.342414, 1.922367",\
+ "0.961447, 1.192425, 1.377305, 1.676398, 2.256352",\
+ "0.541888, 0.771806, 0.956649, 1.255766, 1.835768",\
+ "0.549688, 0.779605, 0.964448, 1.263565, 1.843568",\
+ "0.563107, 0.793025, 0.977867, 1.276985, 1.856987",\
+ "0.715841, 0.945758, 1.130601, 1.429719, 2.009721",\
+ "1.049826, 1.279743, 1.464586, 1.763703, 2.343705",\
+ "0.631467, 0.852136, 1.036675, 1.335794, 1.915800",\
+ "0.639266, 0.859936, 1.044475, 1.343594, 1.923599",\
+ "0.652686, 0.873355, 1.057894, 1.357013, 1.937019",\
+ "0.805420, 1.026089, 1.210628, 1.509747, 2.089752",\
+ "1.139404, 1.360074, 1.544613, 1.843732, 2.423737",\
+ "0.695451, 0.909966, 1.094386, 1.393248, 1.972863",\
+ "0.703251, 0.917766, 1.102185, 1.401047, 1.980663",\
+ "0.716670, 0.931185, 1.115605, 1.414467, 1.994082",\
+ "0.869404, 1.083919, 1.268338, 1.567201, 2.146816",\
+ "1.203389, 1.417904, 1.602323, 1.901185, 2.480801",\
+ "1.034004, 1.215273, 1.398043, 1.696439, 2.275143",\
+ "1.041804, 1.223073, 1.405843, 1.704239, 2.282942",\
+ "1.055223, 1.236492, 1.419262, 1.717658, 2.296362",\
+ "1.207957, 1.389226, 1.571996, 1.870392, 2.449096",\
+ "1.541942, 1.723211, 1.905981, 2.204377, 2.783080");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011");
+ values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2400*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[26]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.356883, 0.553789, 0.735718, 1.027079, 1.590482",\
+ "0.376149, 0.573056, 0.754984, 1.046346, 1.609749",\
+ "0.407828, 0.604733, 0.786661, 1.078023, 1.641427",\
+ "0.697481, 0.894382, 1.076308, 1.367671, 1.931077",\
+ "1.291425, 1.488327, 1.670252, 1.961614, 2.525021",\
+ "0.445232, 0.641107, 0.822999, 1.114385, 1.677836",\
+ "0.464498, 0.660374, 0.842265, 1.133651, 1.697102",\
+ "0.496176, 0.692052, 0.873942, 1.165328, 1.728780",\
+ "0.785829, 0.981701, 1.163589, 1.454976, 2.018430",\
+ "1.379774, 1.575645, 1.757533, 2.048919, 2.612374",\
+ "0.534400, 0.721441, 0.903025, 1.194413, 1.757867",\
+ "0.553666, 0.740707, 0.922292, 1.213680, 1.777134",\
+ "0.585345, 0.772385, 0.953969, 1.245357, 1.808812",\
+ "0.874998, 1.062034, 1.243616, 1.535004, 2.098462",\
+ "1.468942, 1.655978, 1.837560, 2.128948, 2.692406",\
+ "0.597862, 0.779261, 0.960728, 1.251846, 1.814890",\
+ "0.617128, 0.798528, 0.979995, 1.271113, 1.834156",\
+ "0.648807, 0.830206, 1.011672, 1.302790, 1.865834",\
+ "0.938459, 1.119855, 1.301319, 1.592437, 2.155484",\
+ "1.532403, 1.713799, 1.895263, 2.186381, 2.749428",\
+ "0.904924, 1.084513, 1.264385, 1.555021, 2.117120",\
+ "0.924190, 1.103779, 1.283652, 1.574288, 2.136386",\
+ "0.955869, 1.135457, 1.315329, 1.605965, 2.168064",\
+ "1.245522, 1.425106, 1.604976, 1.895612, 2.457714",\
+ "1.839466, 2.019050, 2.198920, 2.489556, 3.051658");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\
+ "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\
+ "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195571, 2.195567, 2.195565, 2.195564, 2.195564",\
+ "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\
+ "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\
+ "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195571, 2.195567, 2.195565, 2.195564, 2.195564",\
+ "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\
+ "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\
+ "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195571, 2.195567, 2.195565, 2.195564, 2.195564",\
+ "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\
+ "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\
+ "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195570, 2.195567, 2.195565, 2.195564, 2.195564",\
+ "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\
+ "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\
+ "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\
+ "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\
+ "2.195571, 2.195567, 2.195565, 2.195564, 2.195564");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.367499, 0.564398, 0.746322, 1.037684, 1.601092",\
+ "0.375296, 0.572195, 0.754119, 1.045481, 1.608889",\
+ "0.388715, 0.585614, 0.767538, 1.058901, 1.622309",\
+ "0.541390, 0.738291, 0.920216, 1.211578, 1.774985",\
+ "0.875354, 1.072255, 1.254180, 1.545543, 2.108949",\
+ "0.455848, 0.651716, 0.833603, 1.124989, 1.688446",\
+ "0.463644, 0.659513, 0.841400, 1.132786, 1.696243",\
+ "0.477064, 0.672932, 0.854819, 1.146206, 1.709662",\
+ "0.629739, 0.825609, 1.007497, 1.298883, 1.862338",\
+ "0.963703, 1.159573, 1.341461, 1.632848, 2.196303",\
+ "0.545016, 0.732049, 0.913630, 1.205018, 1.768477",\
+ "0.552812, 0.739846, 0.921427, 1.212815, 1.776274",\
+ "0.566232, 0.753265, 0.934846, 1.226234, 1.789694",\
+ "0.718907, 0.905942, 1.087524, 1.378912, 1.942370",\
+ "1.052871, 1.239906, 1.421488, 1.712876, 2.276334",\
+ "0.608477, 0.789870, 0.971332, 1.262451, 1.825500",\
+ "0.616274, 0.797667, 0.979129, 1.270248, 1.833297",\
+ "0.629693, 0.811086, 0.992549, 1.283667, 1.846716",\
+ "0.782368, 0.963763, 1.145226, 1.436345, 1.999392",\
+ "1.116332, 1.297727, 1.479191, 1.770309, 2.333357",\
+ "0.915539, 1.095121, 1.274990, 1.565626, 2.127729",\
+ "0.923336, 1.102918, 1.282787, 1.573422, 2.135526",\
+ "0.936756, 1.116337, 1.296206, 1.586842, 2.148946",\
+ "1.089431, 1.269014, 1.448884, 1.739519, 2.301622",\
+ "1.423395, 1.602978, 1.782848, 2.073484, 2.635586");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\
+ "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\
+ "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\
+ "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\
+ "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\
+ "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\
+ "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\
+ "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\
+ "1.002200, 1.002200, 1.002200, 1.002200, 1.002201");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2447*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[27]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.379724, 0.609078, 0.793072, 1.086354, 1.652961",\
+ "0.399096, 0.628450, 0.812444, 1.105726, 1.672333",\
+ "0.430550, 0.659904, 0.843898, 1.137180, 1.703787",\
+ "0.719484, 0.948838, 1.132833, 1.426114, 1.992722",\
+ "1.313376, 1.542730, 1.726725, 2.020006, 2.586613",\
+ "0.468018, 0.696395, 0.880353, 1.173659, 1.740315",\
+ "0.487390, 0.715767, 0.899725, 1.193031, 1.759686",\
+ "0.518844, 0.747221, 0.931179, 1.224485, 1.791140",\
+ "0.807778, 1.036156, 1.220114, 1.513419, 2.080075",\
+ "1.401670, 1.630048, 1.814005, 2.107311, 2.673967",\
+ "0.557713, 0.776723, 0.960380, 1.253688, 1.820346",\
+ "0.577085, 0.796095, 0.979752, 1.273059, 1.839718",\
+ "0.608539, 0.827548, 1.011206, 1.304513, 1.871172",\
+ "0.897473, 1.116483, 1.300140, 1.593448, 2.160107",\
+ "1.491365, 1.710375, 1.894032, 2.187340, 2.753998",\
+ "0.621964, 0.834551, 1.018089, 1.311125, 1.877379",\
+ "0.641336, 0.853923, 1.037461, 1.330497, 1.896751",\
+ "0.672790, 0.885376, 1.068915, 1.361951, 1.928205",\
+ "0.961724, 1.174311, 1.357849, 1.650886, 2.217139",\
+ "1.555616, 1.768203, 1.951741, 2.244777, 2.811031",\
+ "0.960843, 1.139831, 1.321745, 1.614302, 2.179622",\
+ "0.980214, 1.159203, 1.341117, 1.633674, 2.198994",\
+ "1.011668, 1.190656, 1.372571, 1.665128, 2.230447",\
+ "1.300603, 1.479591, 1.661506, 1.954063, 2.519382",\
+ "1.894495, 2.073483, 2.255398, 2.547955, 3.113274");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\
+ "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194880, 2.194880, 2.194880, 2.194880, 2.194880");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.388968, 0.618322, 0.802316, 1.095598, 1.662205",\
+ "0.396778, 0.626132, 0.810127, 1.103408, 1.670016",\
+ "0.410197, 0.639552, 0.823546, 1.116827, 1.683435",\
+ "0.563168, 0.792522, 0.976516, 1.269798, 1.836405",\
+ "0.897236, 1.126590, 1.310585, 1.603866, 2.170474",\
+ "0.477262, 0.705639, 0.889597, 1.182903, 1.749559",\
+ "0.485072, 0.713450, 0.897408, 1.190713, 1.757369",\
+ "0.498491, 0.726869, 0.910827, 1.204133, 1.770788",\
+ "0.651462, 0.879839, 1.063797, 1.357103, 1.923759",\
+ "0.985530, 1.213908, 1.397866, 1.691172, 2.257827",\
+ "0.566957, 0.785967, 0.969624, 1.262932, 1.829590",\
+ "0.574767, 0.793777, 0.977435, 1.270742, 1.837401",\
+ "0.588187, 0.807196, 0.990854, 1.284161, 1.850820",\
+ "0.741157, 0.960167, 1.143824, 1.437132, 2.003790",\
+ "1.075225, 1.294235, 1.477893, 1.771200, 2.337859",\
+ "0.631208, 0.843795, 1.027333, 1.320369, 1.886623",\
+ "0.639018, 0.851605, 1.035143, 1.328180, 1.894433",\
+ "0.652438, 0.865024, 1.048563, 1.341599, 1.907853",\
+ "0.805408, 1.017995, 1.201533, 1.494569, 2.060823",\
+ "1.139476, 1.352063, 1.535602, 1.828638, 2.394892",\
+ "0.970087, 1.149075, 1.330989, 1.623546, 2.188866",\
+ "0.977897, 1.156885, 1.338800, 1.631357, 2.196676",\
+ "0.991316, 1.170304, 1.352219, 1.644776, 2.210095",\
+ "1.144287, 1.323275, 1.505189, 1.797747, 2.363066",\
+ "1.478355, 1.657343, 1.839258, 2.131815, 2.697134");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\
+ "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2729*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[30]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.369185, 0.583807, 0.762700, 1.052121, 1.613591",\
+ "0.388557, 0.603178, 0.782071, 1.071493, 1.632963",\
+ "0.420011, 0.634632, 0.813526, 1.102947, 1.664417",\
+ "0.708947, 0.923568, 1.102462, 1.391883, 1.953353",\
+ "1.302839, 1.517461, 1.696354, 1.985775, 2.547245",\
+ "0.457459, 0.671124, 0.849981, 1.139426, 1.700945",\
+ "0.476830, 0.690496, 0.869353, 1.158798, 1.720316",\
+ "0.508285, 0.721950, 0.900807, 1.190252, 1.751771",\
+ "0.797221, 1.010886, 1.189743, 1.479188, 2.040707",\
+ "1.391113, 1.604778, 1.783635, 2.073080, 2.634599",\
+ "0.547002, 0.751452, 0.930008, 1.219455, 1.780976",\
+ "0.566373, 0.770824, 0.949379, 1.238826, 1.800348",\
+ "0.597828, 0.802278, 0.980834, 1.270281, 1.831802",\
+ "0.886764, 1.091214, 1.269770, 1.559216, 2.120738",\
+ "1.480656, 1.685106, 1.863662, 2.153109, 2.714630",\
+ "0.611070, 0.809282, 0.987704, 1.276886, 1.837996",\
+ "0.630442, 0.828653, 1.007076, 1.296257, 1.857368",\
+ "0.661896, 0.860107, 1.038530, 1.327712, 1.888822",\
+ "0.950832, 1.149043, 1.327466, 1.616648, 2.177758",\
+ "1.544724, 1.742936, 1.921358, 2.210540, 2.771650",\
+ "0.934949, 1.114574, 1.291359, 1.580058, 2.140224",\
+ "0.954320, 1.133946, 1.310730, 1.599430, 2.159595",\
+ "0.985774, 1.165400, 1.342185, 1.630884, 2.191050",\
+ "1.274710, 1.454336, 1.631121, 1.919820, 2.479985",\
+ "1.868603, 2.048229, 2.225013, 2.513712, 3.073878");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.378431, 0.593053, 0.771946, 1.061368, 1.622838",\
+ "0.386242, 0.600863, 0.779757, 1.069178, 1.630648",\
+ "0.399661, 0.614283, 0.793176, 1.082597, 1.644067",\
+ "0.552631, 0.767253, 0.946146, 1.235567, 1.797037",\
+ "0.886699, 1.101321, 1.280214, 1.569635, 2.131105",\
+ "0.466705, 0.680371, 0.859227, 1.148673, 1.710191",\
+ "0.474516, 0.688181, 0.867038, 1.156483, 1.718002",\
+ "0.487935, 0.701600, 0.880457, 1.169902, 1.731421",\
+ "0.640905, 0.854570, 1.033427, 1.322872, 1.884391",\
+ "0.974973, 1.188638, 1.367495, 1.656940, 2.218459",\
+ "0.556248, 0.760699, 0.939254, 1.228701, 1.790223",\
+ "0.564059, 0.768509, 0.947065, 1.236512, 1.798033",\
+ "0.577478, 0.781928, 0.960484, 1.249931, 1.811453",\
+ "0.730448, 0.934898, 1.113454, 1.402901, 1.964422",\
+ "1.064516, 1.268966, 1.447522, 1.736969, 2.298491",\
+ "0.620317, 0.818528, 0.996951, 1.286133, 1.847243",\
+ "0.628127, 0.826339, 1.004761, 1.293943, 1.855053",\
+ "0.641546, 0.839758, 1.018181, 1.307362, 1.868473",\
+ "0.794516, 0.992728, 1.171150, 1.460332, 2.021443",\
+ "1.128584, 1.326796, 1.505219, 1.794400, 2.355511",\
+ "0.944195, 1.123821, 1.300605, 1.589304, 2.149470",\
+ "0.952006, 1.131631, 1.308416, 1.597115, 2.157280",\
+ "0.965425, 1.145051, 1.321835, 1.610534, 2.170700",\
+ "1.118395, 1.298021, 1.474805, 1.763504, 2.323670",\
+ "1.452463, 1.632089, 1.808873, 2.097572, 2.657738");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\
+ "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\
+ "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\
+ "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\
+ "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\
+ "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2349*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[32]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.417064, 0.631505, 0.810363, 1.099808, 1.661366",\
+ "0.436351, 0.650792, 0.829650, 1.119095, 1.680653",\
+ "0.467985, 0.682426, 0.861284, 1.150729, 1.712287",\
+ "0.757495, 0.971936, 1.150794, 1.440239, 2.001797",\
+ "1.351429, 1.565870, 1.744728, 2.034173, 2.595731",\
+ "0.505338, 0.718823, 0.897644, 1.187113, 1.748719",\
+ "0.524625, 0.738110, 0.916931, 1.206400, 1.768006",\
+ "0.556259, 0.769744, 0.948565, 1.238034, 1.799640",\
+ "0.845769, 1.059254, 1.238075, 1.527544, 2.089150",\
+ "1.439703, 1.653188, 1.832009, 2.121478, 2.683084",\
+ "0.594882, 0.799151, 0.977671, 1.267141, 1.828751",\
+ "0.614169, 0.818438, 0.996958, 1.286428, 1.848038",\
+ "0.645804, 0.850072, 1.028592, 1.318063, 1.879672",\
+ "0.935313, 1.139582, 1.318102, 1.607573, 2.169182",\
+ "1.529247, 1.733516, 1.912036, 2.201506, 2.763116",\
+ "0.658952, 0.856980, 1.035367, 1.324573, 1.885771",\
+ "0.678239, 0.876267, 1.054654, 1.343860, 1.905058",\
+ "0.709873, 0.907901, 1.086289, 1.375494, 1.936692",\
+ "0.999383, 1.197411, 1.375799, 1.665004, 2.226202",\
+ "1.593317, 1.791345, 1.969732, 2.258938, 2.820136",\
+ "0.982644, 1.162273, 1.339022, 1.627745, 2.187998",\
+ "1.001931, 1.181560, 1.358309, 1.647032, 2.207285",\
+ "1.033565, 1.213194, 1.389943, 1.678666, 2.238919",\
+ "1.323075, 1.502704, 1.679453, 1.968176, 2.528430",\
+ "1.917009, 2.096638, 2.273387, 2.562110, 3.122364");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.427407, 0.641848, 0.820706, 1.110151, 1.671709",\
+ "0.435207, 0.649648, 0.828505, 1.117950, 1.679508",\
+ "0.448626, 0.663067, 0.841925, 1.131369, 1.692927",\
+ "0.601360, 0.815801, 0.994659, 1.284103, 1.845661",\
+ "0.935344, 1.149785, 1.328643, 1.618088, 2.179646",\
+ "0.515681, 0.729166, 0.907987, 1.197456, 1.759062",\
+ "0.523481, 0.736965, 0.915786, 1.205255, 1.766862",\
+ "0.536900, 0.750385, 0.929206, 1.218675, 1.780281",\
+ "0.689634, 0.903118, 1.081940, 1.371408, 1.933015",\
+ "1.023618, 1.237103, 1.415924, 1.705393, 2.266999",\
+ "0.605225, 0.809494, 0.988014, 1.277484, 1.839094",\
+ "0.613025, 0.817293, 0.995813, 1.285284, 1.846893",\
+ "0.626444, 0.830712, 1.009233, 1.298703, 1.860313",\
+ "0.779178, 0.983446, 1.161967, 1.451437, 2.013046",\
+ "1.113163, 1.317431, 1.495951, 1.785421, 2.347031",\
+ "0.669295, 0.867323, 1.045710, 1.334916, 1.896114",\
+ "0.677094, 0.875123, 1.053510, 1.342715, 1.903913",\
+ "0.690513, 0.888542, 1.066929, 1.356135, 1.917333",\
+ "0.843247, 1.041276, 1.219663, 1.508868, 2.070067",\
+ "1.177232, 1.375260, 1.553648, 1.842853, 2.404051",\
+ "0.992987, 1.172616, 1.349365, 1.638088, 2.198341",\
+ "1.000786, 1.180416, 1.357164, 1.645887, 2.206141",\
+ "1.014206, 1.193835, 1.370584, 1.659307, 2.219560",\
+ "1.166939, 1.346569, 1.523317, 1.812040, 2.372294",\
+ "1.500924, 1.680553, 1.857302, 2.146025, 2.706279");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2494*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[33]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.423145, 0.655225, 0.838651, 1.132010, 1.699224",\
+ "0.442432, 0.674512, 0.857938, 1.151296, 1.718511",\
+ "0.474066, 0.706146, 0.889572, 1.182931, 1.750145",\
+ "0.763577, 0.995656, 1.179082, 1.472441, 2.039655",\
+ "1.357510, 1.589590, 1.773016, 2.066375, 2.633589",\
+ "0.511451, 0.742543, 0.925932, 1.219315, 1.786577",\
+ "0.530738, 0.761829, 0.945219, 1.238602, 1.805864",\
+ "0.562372, 0.793464, 0.976853, 1.270236, 1.837498",\
+ "0.851883, 1.082974, 1.266363, 1.559746, 2.127008",\
+ "1.445816, 1.676908, 1.860297, 2.153680, 2.720942",\
+ "0.600820, 0.822873, 1.005959, 1.299343, 1.866609",\
+ "0.620107, 0.842160, 1.025246, 1.318630, 1.885896",\
+ "0.651741, 0.873794, 1.056880, 1.350264, 1.917530",\
+ "0.941251, 1.163304, 1.346390, 1.639775, 2.207040",\
+ "1.535185, 1.757238, 1.940324, 2.233708, 2.800974",\
+ "0.664609, 0.880707, 1.063666, 1.356781, 1.923642",\
+ "0.683896, 0.899994, 1.082952, 1.376068, 1.942929",\
+ "0.715530, 0.931628, 1.114587, 1.407702, 1.974563",\
+ "1.005041, 1.221138, 1.404097, 1.697213, 2.264073",\
+ "1.598974, 1.815072, 1.998031, 2.291147, 2.858007",\
+ "1.001916, 1.186040, 1.367322, 1.659959, 2.225884",\
+ "1.021203, 1.205327, 1.386609, 1.679246, 2.245171",\
+ "1.052837, 1.236961, 1.418243, 1.710881, 2.276805",\
+ "1.342347, 1.526471, 1.707754, 2.000391, 2.566315",\
+ "1.936281, 2.120405, 2.301688, 2.594325, 3.160249");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\
+ "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\
+ "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\
+ "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\
+ "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\
+ "2.195434, 2.195434, 2.195434, 2.195434, 2.195434");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.433489, 0.665568, 0.848994, 1.142353, 1.709567",\
+ "0.441288, 0.673367, 0.856794, 1.150152, 1.717367",\
+ "0.454707, 0.686787, 0.870213, 1.163572, 1.730786",\
+ "0.607441, 0.839521, 1.022947, 1.316305, 1.883520",\
+ "0.941426, 1.173505, 1.356931, 1.650290, 2.217504",\
+ "0.521794, 0.752886, 0.936275, 1.229658, 1.796920",\
+ "0.529594, 0.760685, 0.944075, 1.237458, 1.804720",\
+ "0.543013, 0.774105, 0.957494, 1.250877, 1.818139",\
+ "0.695747, 0.926838, 1.110228, 1.403611, 1.970873",\
+ "1.029732, 1.260823, 1.444212, 1.737595, 2.304857",\
+ "0.611163, 0.833216, 1.016302, 1.309687, 1.876952",\
+ "0.618962, 0.841016, 1.024101, 1.317486, 1.884752",\
+ "0.632382, 0.854435, 1.037521, 1.330905, 1.898171",\
+ "0.785116, 1.007169, 1.190255, 1.483639, 2.050905",\
+ "1.119100, 1.341153, 1.524239, 1.817624, 2.384889",\
+ "0.674952, 0.891050, 1.074009, 1.367125, 1.933985",\
+ "0.682752, 0.898850, 1.081808, 1.374924, 1.941785",\
+ "0.696171, 0.912269, 1.095228, 1.388343, 1.955204",\
+ "0.848905, 1.065003, 1.247962, 1.541077, 2.107938",\
+ "1.182890, 1.398987, 1.581946, 1.875062, 2.441922",\
+ "1.012259, 1.196383, 1.377666, 1.670303, 2.236228",\
+ "1.020059, 1.204182, 1.385465, 1.678102, 2.244027",\
+ "1.033478, 1.217602, 1.398885, 1.691522, 2.257446",\
+ "1.186212, 1.370336, 1.551618, 1.844255, 2.410180",\
+ "1.520197, 1.704320, 1.885603, 2.178240, 2.744164");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\
+ "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\
+ "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\
+ "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\
+ "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\
+ "1.002182, 1.002182, 1.002182, 1.002182, 1.002182");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2512*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[37]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.181258, 0.362750, 0.559584, 0.877059, 1.491654",\
+ "0.196091, 0.377154, 0.575199, 0.895881, 1.517263",\
+ "0.221299, 0.401436, 0.600771, 0.925894, 1.556997",\
+ "0.494050, 0.669272, 0.865120, 1.207435, 1.883536",\
+ "1.086888, 1.260498, 1.453339, 1.802428, 2.497703",\
+ "0.268666, 0.450068, 0.646865, 0.964364, 1.579007",\
+ "0.283499, 0.464472, 0.662480, 0.983186, 1.604617",\
+ "0.308707, 0.488754, 0.688052, 1.013199, 1.644350",\
+ "0.581459, 0.756590, 0.952401, 1.294740, 1.970890",\
+ "1.174296, 1.347816, 1.540620, 1.889733, 2.585056",\
+ "0.349534, 0.530400, 0.726892, 1.044393, 1.659039",\
+ "0.364365, 0.544804, 0.742507, 1.063215, 1.684648",\
+ "0.389566, 0.569086, 0.768079, 1.093227, 1.724382",\
+ "0.662286, 0.836922, 1.032428, 1.374768, 2.050921",\
+ "1.255114, 1.428148, 1.620646, 1.969761, 2.665088",\
+ "0.407230, 0.588238, 0.784630, 1.101888, 1.716185",\
+ "0.422055, 0.602641, 0.800248, 1.120718, 1.741811",\
+ "0.447245, 0.626919, 0.825823, 1.150743, 1.781568",\
+ "0.719903, 0.894737, 1.090165, 1.432339, 2.108216",\
+ "1.312710, 1.485957, 1.678376, 2.027355, 2.722429",\
+ "0.710204, 0.893608, 1.088293, 1.405116, 2.018565",\
+ "0.724980, 0.907999, 1.103911, 1.423953, 2.044210",\
+ "0.750065, 0.932253, 1.129487, 1.453987, 2.083996",\
+ "1.022164, 1.199940, 1.393827, 1.735630, 2.410775",\
+ "1.614788, 1.791118, 1.982037, 2.330666, 3.025044");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\
+ "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\
+ "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\
+ "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\
+ "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\
+ "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\
+ "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\
+ "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\
+ "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\
+ "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\
+ "0.126849, 0.127605, 0.133435, 0.151631, 0.191178",\
+ "0.149775, 0.150309, 0.154650, 0.170542, 0.205735",\
+ "0.195028, 0.195582, 0.198470, 0.210618, 0.237900",\
+ "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\
+ "2.194129, 2.194405, 2.194418, 2.195894, 2.199512",\
+ "0.126859, 0.127607, 0.133449, 0.151680, 0.191274",\
+ "0.149782, 0.150311, 0.154660, 0.170585, 0.205820",\
+ "0.195035, 0.195584, 0.198477, 0.210651, 0.237965",\
+ "0.816155, 0.816256, 0.816260, 0.817810, 0.821601",\
+ "2.194133, 2.194406, 2.194418, 2.195898, 2.199521",\
+ "0.126945, 0.127627, 0.133451, 0.151721, 0.191389",\
+ "0.149843, 0.150326, 0.154662, 0.170622, 0.205922",\
+ "0.195098, 0.195599, 0.198478, 0.210679, 0.238045",\
+ "0.816166, 0.816259, 0.816260, 0.817813, 0.821612",\
+ "2.194165, 2.194413, 2.194418, 2.195902, 2.199532");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.117102, 0.379947, 0.573156, 0.882174, 1.479232",\
+ "0.126091, 0.389068, 0.582472, 0.892519, 1.491929",\
+ "0.141699, 0.404157, 0.597820, 0.909153, 1.511489",\
+ "0.306945, 0.562483, 0.755606, 1.068523, 1.675209",\
+ "0.649757, 0.897030, 1.089718, 1.401787, 2.006775",\
+ "0.205481, 0.467265, 0.660437, 0.969479, 1.566586",\
+ "0.214473, 0.476386, 0.669753, 0.979824, 1.579283",\
+ "0.230076, 0.491475, 0.685100, 0.996458, 1.598842",\
+ "0.395245, 0.649801, 0.842887, 1.155828, 1.762562",\
+ "0.738017, 0.984348, 1.176999, 1.489092, 2.094129",\
+ "0.294834, 0.547598, 0.740463, 1.049507, 1.646617",\
+ "0.303840, 0.556719, 0.749780, 1.059852, 1.659314",\
+ "0.319425, 0.571807, 0.765127, 1.076486, 1.678874",\
+ "0.484368, 0.730134, 0.922914, 1.235856, 1.842594",\
+ "0.827025, 1.064680, 1.257025, 1.569121, 2.174160",\
+ "0.358511, 0.605438, 0.798193, 1.106982, 1.703722",\
+ "0.367529, 0.614560, 0.807510, 1.117329, 1.716424",\
+ "0.383098, 0.629648, 0.822858, 1.133967, 1.735991",\
+ "0.547830, 0.787974, 0.980643, 1.293342, 1.899721",\
+ "0.890379, 1.122520, 1.314754, 1.626604, 2.231284",\
+ "0.695115, 0.910825, 1.101854, 1.410191, 2.006050",\
+ "0.704209, 0.919948, 1.111171, 1.420541, 2.018759",\
+ "0.719674, 0.935035, 1.126519, 1.437182, 2.038335",\
+ "0.883062, 1.093358, 1.284304, 1.596561, 2.202077",\
+ "1.224926, 1.427904, 1.618415, 1.929822, 2.533635");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.044794, 0.049393, 0.054601, 0.068665, 0.098782",\
+ "0.053408, 0.055750, 0.059102, 0.072238, 0.101610",\
+ "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\
+ "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\
+ "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\
+ "0.044917, 0.049393, 0.054601, 0.068665, 0.098782",\
+ "0.053471, 0.055750, 0.059102, 0.072238, 0.101610",\
+ "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\
+ "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\
+ "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\
+ "0.045280, 0.049393, 0.054601, 0.068665, 0.098782",\
+ "0.053656, 0.055750, 0.059102, 0.072238, 0.101610",\
+ "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\
+ "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\
+ "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\
+ "0.045619, 0.049410, 0.054613, 0.068702, 0.098855",\
+ "0.053828, 0.055759, 0.059110, 0.072274, 0.101681",\
+ "0.075784, 0.075784, 0.078001, 0.088634, 0.112740",\
+ "0.368045, 0.368045, 0.368835, 0.370660, 0.374443",\
+ "1.001402, 1.001402, 1.001777, 1.002639, 1.004426",\
+ "0.047777, 0.049532, 0.054615, 0.068733, 0.098943",\
+ "0.054927, 0.055821, 0.059111, 0.072304, 0.101766",\
+ "0.075784, 0.075784, 0.078002, 0.088659, 0.112810",\
+ "0.368045, 0.368045, 0.368835, 0.370664, 0.374454",\
+ "1.001402, 1.001402, 1.001777, 1.002641, 1.004432");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2747*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[40]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.496413, 0.709649, 0.894786, 1.185670, 1.745053",\
+ "0.515784, 0.729021, 0.914158, 1.205042, 1.764425",\
+ "0.547238, 0.760475, 0.945612, 1.236496, 1.795879",\
+ "0.836174, 1.049411, 1.234548, 1.525432, 2.084815",\
+ "1.430066, 1.643303, 1.828440, 2.119324, 2.678707",\
+ "0.584781, 0.796968, 0.982067, 1.272975, 1.832407",\
+ "0.604153, 0.816339, 1.001439, 1.292347, 1.851778",\
+ "0.635607, 0.847793, 1.032893, 1.323801, 1.883232",\
+ "0.924543, 1.136729, 1.321829, 1.612737, 2.172168",\
+ "1.518435, 1.730622, 1.915721, 2.206629, 2.766061",\
+ "0.673752, 0.877303, 1.062094, 1.353004, 1.912438",\
+ "0.693124, 0.896674, 1.081466, 1.372375, 1.931810",\
+ "0.724578, 0.928128, 1.112920, 1.403829, 1.963264",\
+ "1.013514, 1.217064, 1.401856, 1.692765, 2.252200",\
+ "1.607406, 1.810957, 1.995748, 2.286657, 2.846092",\
+ "0.736919, 0.935130, 1.119804, 1.410431, 1.969450",\
+ "0.756291, 0.954502, 1.139176, 1.429803, 1.988822",\
+ "0.787745, 0.985956, 1.170630, 1.461257, 2.020276",\
+ "1.076681, 1.274892, 1.459566, 1.750193, 2.309212",\
+ "1.670573, 1.868784, 2.053458, 2.344085, 2.903104",\
+ "1.058360, 1.240438, 1.423463, 1.713602, 2.271667",\
+ "1.077731, 1.259810, 1.442835, 1.732974, 2.291038",\
+ "1.109185, 1.291264, 1.474289, 1.764428, 2.322492",\
+ "1.398121, 1.580200, 1.763225, 2.053364, 2.611428",\
+ "1.992013, 2.174092, 2.357117, 2.647256, 3.205320");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.505659, 0.718896, 0.904033, 1.194916, 1.754300",\
+ "0.513469, 0.726706, 0.911843, 1.202727, 1.762110",\
+ "0.526889, 0.740125, 0.925263, 1.216146, 1.775529",\
+ "0.679859, 0.893095, 1.078233, 1.369116, 1.928499",\
+ "1.013927, 1.227163, 1.412301, 1.703184, 2.262567",\
+ "0.594028, 0.806214, 0.991314, 1.282222, 1.841653",\
+ "0.601838, 0.814024, 0.999124, 1.290032, 1.849463",\
+ "0.615257, 0.827444, 1.012543, 1.303451, 1.862883",\
+ "0.768227, 0.980414, 1.165513, 1.456421, 2.015853",\
+ "1.102295, 1.314482, 1.499582, 1.790489, 2.349921",\
+ "0.682999, 0.886549, 1.071341, 1.362250, 1.921685",\
+ "0.690809, 0.894360, 1.079151, 1.370060, 1.929495",\
+ "0.704229, 0.907779, 1.092570, 1.383480, 1.942914",\
+ "0.857199, 1.060749, 1.245540, 1.536450, 2.095884",\
+ "1.191267, 1.394817, 1.579608, 1.870518, 2.429952",\
+ "0.746166, 0.944377, 1.129050, 1.419678, 1.978696",\
+ "0.753976, 0.952187, 1.136861, 1.427488, 1.986507",\
+ "0.767395, 0.965607, 1.150280, 1.440908, 1.999926",\
+ "0.920365, 1.118577, 1.303250, 1.593878, 2.152896",\
+ "1.254433, 1.452645, 1.637318, 1.927946, 2.486964",\
+ "1.067606, 1.249685, 1.432710, 1.722849, 2.280913",\
+ "1.075416, 1.257495, 1.440520, 1.730659, 2.288723",\
+ "1.088836, 1.270914, 1.453939, 1.744078, 2.302143",\
+ "1.241806, 1.423884, 1.606909, 1.897048, 2.455113",\
+ "1.575874, 1.757952, 1.940977, 2.231116, 2.789181");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2380*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[44]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.099932, 0.259054, 0.413318, 0.663965, 1.151026",\
+ "0.112861, 0.280635, 0.445926, 0.710841, 1.223619",\
+ "0.139635, 0.312455, 0.491350, 0.774619, 1.320764",\
+ "0.427093, 0.638536, 0.826241, 1.153952, 1.801309",\
+ "1.022612, 1.250759, 1.440120, 1.765390, 2.405472",\
+ "0.187338, 0.346372, 0.500599, 0.751271, 1.238380",\
+ "0.200267, 0.367953, 0.533207, 0.798146, 1.310972",\
+ "0.227041, 0.399773, 0.578631, 0.861924, 1.408118",\
+ "0.515372, 0.725854, 0.913522, 1.241257, 1.888662",\
+ "1.110934, 1.338077, 1.527401, 1.852695, 2.492826",\
+ "0.268065, 0.426703, 0.580626, 0.831299, 1.318411",\
+ "0.281048, 0.448284, 0.613234, 0.878174, 1.391004",\
+ "0.307853, 0.480104, 0.658657, 0.941953, 1.488149",\
+ "0.604596, 0.806184, 0.993549, 1.321285, 1.968694",\
+ "1.200284, 1.418408, 1.607428, 1.932723, 2.572857",\
+ "0.325504, 0.484459, 0.638266, 0.888640, 1.375251",\
+ "0.338594, 0.506071, 0.670899, 0.935546, 1.447905",\
+ "0.365461, 0.537910, 0.716354, 0.999365, 1.545131",\
+ "0.668221, 0.863995, 1.051266, 1.378821, 2.025920",\
+ "1.264029, 1.476232, 1.665149, 1.990250, 2.630066",\
+ "0.626239, 0.789242, 0.941912, 1.191734, 1.677259",\
+ "0.640305, 0.811082, 0.974549, 1.238668, 1.749989",\
+ "0.667742, 0.843054, 1.020009, 1.302522, 1.847312",\
+ "0.992829, 1.169169, 1.354925, 1.682082, 2.328396",\
+ "1.601053, 1.781498, 1.968808, 2.293504, 2.932521");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.028418, 0.053985, 0.061562, 0.076171, 0.106327",\
+ "0.053853, 0.080619, 0.084946, 0.098515, 0.128974",\
+ "0.117398, 0.123775, 0.136709, 0.151501, 0.176771",\
+ "0.813025, 0.813025, 0.813025, 0.814975, 0.819748",\
+ "2.191540, 2.192948, 2.194009, 2.200710, 2.216247",\
+ "0.028418, 0.053985, 0.061562, 0.076171, 0.106327",\
+ "0.053853, 0.080619, 0.084946, 0.098515, 0.128974",\
+ "0.117398, 0.123775, 0.136709, 0.151501, 0.176771",\
+ "0.813025, 0.813025, 0.813025, 0.814975, 0.819748",\
+ "2.191577, 2.192948, 2.194009, 2.200710, 2.216247",\
+ "0.028577, 0.053985, 0.061562, 0.076171, 0.106327",\
+ "0.054019, 0.080619, 0.084946, 0.098515, 0.128974",\
+ "0.117437, 0.123775, 0.136709, 0.151501, 0.176771",\
+ "0.813025, 0.813025, 0.813025, 0.814975, 0.819748",\
+ "2.191688, 2.192948, 2.194009, 2.200710, 2.216247",\
+ "0.028892, 0.054081, 0.061577, 0.076207, 0.106399",\
+ "0.054349, 0.080719, 0.084954, 0.098552, 0.129047",\
+ "0.117516, 0.123799, 0.136740, 0.151532, 0.176832",\
+ "0.813025, 0.813025, 0.813025, 0.814981, 0.819759",\
+ "2.191792, 2.192953, 2.194012, 2.200729, 2.216285",\
+ "0.031778, 0.054753, 0.061580, 0.076239, 0.106487",\
+ "0.057369, 0.081423, 0.084955, 0.098584, 0.129136",\
+ "0.118236, 0.123966, 0.136744, 0.151558, 0.176905",\
+ "0.813025, 0.813025, 0.813025, 0.814986, 0.819773",\
+ "2.192455, 2.192990, 2.194012, 2.200745, 2.216330");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.071387, 0.284408, 0.492606, 0.801306, 1.367433",\
+ "0.077667, 0.305792, 0.517732, 0.814342, 1.385042",\
+ "0.090238, 0.334877, 0.530841, 0.830649, 1.407555",\
+ "0.256635, 0.477338, 0.671832, 0.978257, 1.567975",\
+ "0.595228, 0.802461, 0.996271, 1.304460, 1.898944",\
+ "0.158934, 0.371732, 0.579823, 0.888611, 1.454786",\
+ "0.165476, 0.393159, 0.605013, 0.901647, 1.472395",\
+ "0.178302, 0.422304, 0.618122, 0.917954, 1.494908",\
+ "0.344810, 0.564656, 0.759113, 1.065562, 1.655329",\
+ "0.683378, 0.889779, 1.083552, 1.391765, 1.986297",\
+ "0.245972, 0.460189, 0.667780, 0.968640, 1.534818",\
+ "0.253296, 0.481714, 0.685040, 0.981676, 1.552427",\
+ "0.266884, 0.507931, 0.698149, 0.997983, 1.574940",\
+ "0.433723, 0.644987, 0.839140, 1.145591, 1.735360",\
+ "0.772213, 0.970110, 1.163579, 1.471793, 2.066329",\
+ "0.307535, 0.525062, 0.731901, 1.026077, 1.591848",\
+ "0.315597, 0.546729, 0.742759, 1.039118, 1.609468",\
+ "0.329903, 0.565774, 0.755873, 1.055433, 1.631996",\
+ "0.497055, 0.702831, 0.896872, 1.203056, 1.792447",\
+ "0.835472, 1.027940, 1.221311, 1.529264, 2.123427",\
+ "0.630646, 0.853005, 1.036340, 1.329254, 1.894087",\
+ "0.643411, 0.859949, 1.046418, 1.342300, 1.911721",\
+ "0.662302, 0.871170, 1.059532, 1.358621, 1.934267",\
+ "0.824001, 1.008235, 1.200534, 1.506258, 2.094755",\
+ "1.152404, 1.333245, 1.524972, 1.832471, 2.425749");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.014090, 0.057759, 0.075820, 0.080331, 0.107469",\
+ "0.025180, 0.064799, 0.067612, 0.083095, 0.115487",\
+ "0.053782, 0.083479, 0.086622, 0.102435, 0.134993",\
+ "0.368605, 0.368605, 0.369812, 0.373454, 0.381327",\
+ "1.000406, 1.000406, 1.002137, 1.003830, 1.006481",\
+ "0.014987, 0.057834, 0.075890, 0.080331, 0.107469",\
+ "0.026088, 0.064832, 0.067612, 0.083095, 0.115487",\
+ "0.054430, 0.083516, 0.086622, 0.102435, 0.134993",\
+ "0.368605, 0.368605, 0.369812, 0.373454, 0.381327",\
+ "1.000406, 1.000406, 1.002137, 1.003830, 1.006481",\
+ "0.017662, 0.058002, 0.075892, 0.080331, 0.107469",\
+ "0.028799, 0.064906, 0.067612, 0.083095, 0.115487",\
+ "0.056363, 0.078451, 0.086622, 0.102435, 0.134993",\
+ "0.368605, 0.368605, 0.369812, 0.373454, 0.381327",\
+ "1.000406, 1.000406, 1.002137, 1.003830, 1.006481",\
+ "0.020186, 0.058246, 0.075896, 0.080364, 0.107535",\
+ "0.031356, 0.065014, 0.067628, 0.083134, 0.115565",\
+ "0.058188, 0.078544, 0.086639, 0.102475, 0.135071",\
+ "0.368605, 0.368605, 0.369814, 0.373463, 0.381346",\
+ "1.000406, 1.000406, 1.002141, 1.003834, 1.006488",\
+ "0.036287, 0.049252, 0.064182, 0.080393, 0.107614",\
+ "0.047669, 0.060805, 0.067630, 0.083168, 0.115659",\
+ "0.069823, 0.079193, 0.086642, 0.102509, 0.135166",\
+ "0.368605, 0.368605, 0.369815, 0.373471, 0.381369",\
+ "1.000406, 1.000406, 1.002141, 1.003836, 1.006495");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2421*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[45]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.473885, 0.684615, 0.861464, 1.145505, 1.695445",\
+ "0.493257, 0.703986, 0.880836, 1.164877, 1.714816",\
+ "0.524711, 0.735440, 0.912290, 1.196331, 1.746270",\
+ "0.813647, 1.024377, 1.201226, 1.485267, 2.035206",\
+ "1.407539, 1.618269, 1.795118, 2.079159, 2.629098",\
+ "0.562155, 0.771933, 0.948745, 1.232810, 1.782798",\
+ "0.581527, 0.791304, 0.968117, 1.252182, 1.802170",\
+ "0.612981, 0.822758, 0.999571, 1.283636, 1.833624",\
+ "0.901917, 1.111694, 1.288507, 1.572572, 2.122560",\
+ "1.495809, 1.705587, 1.882399, 2.166464, 2.716452",\
+ "0.651344, 0.852264, 1.028772, 1.312839, 1.862830",\
+ "0.670716, 0.871635, 1.048143, 1.332211, 1.882201",\
+ "0.702170, 0.903089, 1.079598, 1.363665, 1.913656",\
+ "0.991106, 1.192025, 1.368534, 1.652601, 2.202591",\
+ "1.584998, 1.785918, 1.962426, 2.246493, 2.796484",\
+ "0.714933, 0.910084, 1.086463, 1.370256, 1.919821",\
+ "0.734305, 0.929456, 1.105835, 1.389627, 1.939192",\
+ "0.765759, 0.960910, 1.137289, 1.421082, 1.970646",\
+ "1.054695, 1.249846, 1.426225, 1.710018, 2.259583",\
+ "1.648587, 1.843739, 2.020117, 2.303910, 2.853475",\
+ "1.036585, 1.215328, 1.390118, 1.673416, 2.222012",\
+ "1.055957, 1.234700, 1.409489, 1.692788, 2.241384",\
+ "1.087411, 1.266154, 1.440943, 1.724242, 2.272838",\
+ "1.376347, 1.555090, 1.729879, 2.013178, 2.561774",\
+ "1.970239, 2.148982, 2.323771, 2.607070, 3.155666");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\
+ "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\
+ "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\
+ "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\
+ "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\
+ "2.194882, 2.194882, 2.194882, 2.194882, 2.194882");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.483132, 0.693861, 0.870710, 1.154752, 1.704691",\
+ "0.490942, 0.701672, 0.878521, 1.162562, 1.712502",\
+ "0.504361, 0.715091, 0.891940, 1.175981, 1.725921",\
+ "0.657331, 0.868061, 1.044910, 1.328951, 1.878891",\
+ "0.991399, 1.202129, 1.378978, 1.663020, 2.212959",\
+ "0.571402, 0.781179, 0.957991, 1.242057, 1.792045",\
+ "0.579212, 0.788990, 0.965802, 1.249867, 1.799855",\
+ "0.592631, 0.802409, 0.979221, 1.263286, 1.813274",\
+ "0.745601, 0.955379, 1.132191, 1.416256, 1.966244",\
+ "1.079669, 1.289447, 1.466259, 1.750325, 2.300312",\
+ "0.660591, 0.861510, 1.038018, 1.322085, 1.872076",\
+ "0.668401, 0.869320, 1.045829, 1.329896, 1.879887",\
+ "0.681820, 0.882740, 1.059248, 1.343315, 1.893306",\
+ "0.834790, 1.035710, 1.212218, 1.496285, 2.046276",\
+ "1.168858, 1.369778, 1.546286, 1.830353, 2.380344",\
+ "0.724180, 0.919331, 1.095710, 1.379503, 1.929067",\
+ "0.731990, 0.927141, 1.103520, 1.387313, 1.936877",\
+ "0.745409, 0.940561, 1.116939, 1.400732, 1.950297",\
+ "0.898379, 1.093531, 1.269909, 1.553702, 2.103267",\
+ "1.232447, 1.427599, 1.603977, 1.887770, 2.437335",\
+ "1.045832, 1.224575, 1.399364, 1.682663, 2.231259",\
+ "1.053642, 1.232385, 1.407174, 1.690473, 2.239069",\
+ "1.067061, 1.245804, 1.420594, 1.703892, 2.252488",\
+ "1.220031, 1.398774, 1.573564, 1.856862, 2.405458",\
+ "1.554100, 1.732842, 1.907632, 2.190930, 2.739527");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\
+ "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\
+ "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\
+ "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\
+ "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\
+ "1.000959, 1.000959, 1.000959, 1.000959, 1.000959");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2516*/
+
+} /* end of pin tl_o[5] */
+
+pin("tl_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.020161 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[4];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[17]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.778821, 1.003429, 1.297149, 1.790603, 2.777510",\
+ "0.825348, 1.049956, 1.343676, 1.837130, 2.824038",\
+ "0.910982, 1.135590, 1.429310, 1.922764, 2.909672",\
+ "1.134301, 1.358909, 1.652629, 2.146083, 3.132991",\
+ "1.698246, 1.922854, 2.216574, 2.710028, 3.696936",\
+ "0.866262, 1.091031, 1.384796, 1.877318, 2.863444",\
+ "0.912789, 1.137558, 1.431323, 1.923846, 2.909971",\
+ "0.998423, 1.223192, 1.516957, 2.009480, 2.995605",\
+ "1.221742, 1.446511, 1.740276, 2.232799, 3.218925",\
+ "1.785687, 2.010456, 2.304221, 2.796744, 3.782870",\
+ "0.947141, 1.180161, 1.472762, 1.964941, 2.950399",\
+ "0.993669, 1.226688, 1.519289, 2.011468, 2.996926",\
+ "1.079303, 1.312322, 1.604924, 2.097103, 3.082561",\
+ "1.302622, 1.535641, 1.828242, 2.320421, 3.305880",\
+ "1.866567, 2.099586, 2.392188, 2.884367, 3.869825",\
+ "1.004861, 1.246014, 1.536906, 2.028855, 3.013908",\
+ "1.051388, 1.292541, 1.583433, 2.075382, 3.060435",\
+ "1.137022, 1.378175, 1.669067, 2.161016, 3.146070",\
+ "1.360341, 1.601494, 1.892386, 2.384335, 3.369389",\
+ "1.924286, 2.165440, 2.456331, 2.948280, 3.933334",\
+ "1.307537, 1.612873, 1.889025, 2.378309, 3.359364",\
+ "1.354064, 1.659401, 1.935552, 2.424836, 3.405891",\
+ "1.439698, 1.745035, 2.021186, 2.510470, 3.491526",\
+ "1.663017, 1.968354, 2.244505, 2.733789, 3.714845",\
+ "2.226962, 2.532299, 2.808450, 3.297734, 4.278790");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\
+ "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\
+ "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\
+ "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\
+ "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163010, 2.163010, 2.163010, 2.163010");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.717206, 0.941815, 1.235535, 1.728989, 2.715896",\
+ "0.770496, 0.995104, 1.288824, 1.782278, 2.769186",\
+ "0.831244, 1.055852, 1.349573, 1.843026, 2.829934",\
+ "0.965956, 1.190564, 1.484284, 1.977738, 2.964645",\
+ "1.312464, 1.537072, 1.830792, 2.324246, 3.311154",\
+ "0.804648, 1.029416, 1.323182, 1.815704, 2.801830",\
+ "0.857937, 1.082706, 1.376471, 1.868994, 2.855119",\
+ "0.918686, 1.143454, 1.437219, 1.929742, 2.915868",\
+ "1.053397, 1.278166, 1.571931, 2.064453, 3.050579",\
+ "1.399905, 1.624674, 1.918439, 2.410962, 3.397088",\
+ "0.885527, 1.118547, 1.411148, 1.903327, 2.888785",\
+ "0.938817, 1.171836, 1.464437, 1.956616, 2.942075",\
+ "0.999565, 1.232585, 1.525186, 2.017365, 3.002823",\
+ "1.134276, 1.367296, 1.659897, 2.152076, 3.137534",\
+ "1.480785, 1.713804, 2.006406, 2.498585, 3.484043",\
+ "0.943246, 1.184400, 1.475292, 1.967241, 2.952294",\
+ "0.996536, 1.237689, 1.528581, 2.020530, 3.005584",\
+ "1.057284, 1.298438, 1.589330, 2.081279, 3.066332",\
+ "1.191995, 1.433149, 1.724041, 2.215990, 3.201043",\
+ "1.538504, 1.779658, 2.070549, 2.562499, 3.547552",\
+ "1.245923, 1.551259, 1.827411, 2.316695, 3.297750",\
+ "1.299212, 1.604549, 1.880700, 2.369984, 3.351039",\
+ "1.359961, 1.665297, 1.941449, 2.430732, 3.411788",\
+ "1.494672, 1.800008, 2.076160, 2.565444, 3.546499",\
+ "1.841180, 2.146517, 2.422668, 2.911952, 3.893008");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\
+ "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\
+ "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\
+ "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\
+ "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\
+ "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\
+ "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\
+ "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\
+ "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\
+ "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\
+ "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\
+ "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\
+ "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\
+ "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\
+ "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2677*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[19]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.619374, 0.887475, 1.180133, 1.686418, 2.698987",\
+ "0.666474, 0.934595, 1.227354, 1.733911, 2.747024",\
+ "0.753747, 1.021925, 1.314971, 1.822307, 2.836977",\
+ "0.979596, 1.247862, 1.541350, 2.049887, 3.066961",\
+ "1.546840, 1.815220, 2.109287, 2.619390, 3.639598",\
+ "0.706782, 0.975064, 1.267816, 1.773132, 2.784921",\
+ "0.753882, 1.022185, 1.315038, 1.820625, 2.832958",\
+ "0.841156, 1.109515, 1.402658, 1.909021, 2.922911",\
+ "1.067004, 1.335453, 1.629041, 2.136601, 3.152895",\
+ "1.634248, 1.902812, 2.196982, 2.706105, 3.725532",\
+ "0.790149, 1.064125, 1.355782, 1.860753, 2.871876",\
+ "0.837250, 1.111246, 1.403004, 1.908246, 2.919913",\
+ "0.924524, 1.198577, 1.490623, 1.996642, 3.009866",\
+ "1.150375, 1.424515, 1.717007, 2.224223, 3.239850",\
+ "1.717623, 1.991877, 2.284948, 2.793726, 3.812487",\
+ "0.853818, 1.129875, 1.419928, 1.924667, 2.935385",\
+ "0.900919, 1.176996, 1.467150, 1.972159, 2.983422",\
+ "0.988195, 1.264329, 1.554770, 2.060555, 3.073375",\
+ "1.214048, 1.490269, 1.781153, 2.288136, 3.303359",\
+ "1.781297, 2.057633, 2.349094, 2.857639, 3.875996",\
+ "1.190374, 1.495641, 1.772172, 2.274166, 3.280841",\
+ "1.237478, 1.542768, 1.819397, 2.321660, 3.328878",\
+ "1.324760, 1.630116, 1.907025, 2.410059, 3.418831",\
+ "1.550623, 1.856080, 2.133420, 2.637645, 3.648815",\
+ "2.117886, 2.423474, 2.701378, 3.207154, 4.221452");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.053871, 0.053928, 0.055014, 0.058545, 0.065606",\
+ "0.173261, 0.173221, 0.173020, 0.172475, 0.171386",\
+ "0.375447, 0.375353, 0.374960, 0.373952, 0.371937",\
+ "0.885472, 0.885429, 0.885258, 0.884858, 0.884057",\
+ "2.163064, 2.163128, 2.163351, 2.163842, 2.164825",\
+ "0.053871, 0.053928, 0.055025, 0.058545, 0.065606",\
+ "0.173261, 0.173221, 0.173019, 0.172475, 0.171386",\
+ "0.375447, 0.375352, 0.374957, 0.373952, 0.371937",\
+ "0.885472, 0.885428, 0.885257, 0.884858, 0.884057",\
+ "2.163064, 2.163129, 2.163352, 2.163842, 2.164825",\
+ "0.053872, 0.053929, 0.055025, 0.058545, 0.065606",\
+ "0.173260, 0.173220, 0.173019, 0.172475, 0.171386",\
+ "0.375444, 0.375351, 0.374957, 0.373952, 0.371937",\
+ "0.885472, 0.885428, 0.885257, 0.884858, 0.884057",\
+ "2.163065, 2.163130, 2.163352, 2.163842, 2.164825",\
+ "0.053873, 0.053930, 0.055026, 0.058545, 0.065606",\
+ "0.173259, 0.173219, 0.173019, 0.172475, 0.171386",\
+ "0.375442, 0.375349, 0.374957, 0.373952, 0.371937",\
+ "0.885471, 0.885427, 0.885257, 0.884858, 0.884057",\
+ "2.163066, 2.163132, 2.163352, 2.163842, 2.164825",\
+ "0.053880, 0.053946, 0.055062, 0.058559, 0.065606",\
+ "0.173255, 0.173209, 0.173013, 0.172473, 0.171386",\
+ "0.375432, 0.375324, 0.374946, 0.373948, 0.371937",\
+ "0.885469, 0.885413, 0.885253, 0.884856, 0.884057",\
+ "2.163070, 2.163151, 2.163357, 2.163844, 2.164825");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.549769, 0.817593, 1.110465, 1.618513, 2.634607",\
+ "0.610729, 0.878819, 1.171421, 1.677554, 2.689819",\
+ "0.677494, 0.945792, 1.239448, 1.748438, 2.766419",\
+ "0.811699, 1.079980, 1.373547, 1.882297, 2.899797",\
+ "1.155145, 1.423320, 1.716351, 2.223647, 3.238237",\
+ "0.637177, 0.905181, 1.198154, 1.705227, 2.720541",\
+ "0.698137, 0.966409, 1.259104, 1.764268, 2.775753",\
+ "0.764902, 1.033383, 1.327140, 1.835153, 2.852353",\
+ "0.899107, 1.167571, 1.461238, 1.969011, 2.985731",\
+ "1.242554, 1.510911, 1.804038, 2.310361, 3.324171",\
+ "0.720537, 0.994237, 1.286120, 1.792848, 2.807496",\
+ "0.781504, 1.055469, 1.347070, 1.851890, 2.862708",\
+ "0.848274, 1.122447, 1.415106, 1.922774, 2.939308",\
+ "0.982479, 1.256634, 1.549204, 2.056633, 3.072686",\
+ "1.325922, 1.599972, 1.892004, 2.397983, 3.411126",\
+ "0.784201, 1.059981, 1.350266, 1.856762, 2.871005",\
+ "0.845173, 1.121219, 1.411216, 1.915803, 2.926217",\
+ "0.911947, 1.188202, 1.479252, 1.986687, 3.002817",\
+ "1.046151, 1.322389, 1.613351, 2.120546, 3.136195",\
+ "1.389593, 1.665724, 1.956150, 2.461896, 3.474635",\
+ "1.120725, 1.425673, 1.702529, 2.206268, 3.216461",\
+ "1.181728, 1.486982, 1.763459, 2.265301, 3.271673",\
+ "1.248526, 1.554021, 1.831524, 2.336198, 3.348273",\
+ "1.382729, 1.688203, 1.965620, 2.470056, 3.481651",\
+ "1.726158, 2.031510, 2.308404, 2.811399, 3.820091");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.071629, 0.072032, 0.074063, 0.079575, 0.090597",\
+ "0.129720, 0.130266, 0.133020, 0.140492, 0.155435",\
+ "0.214056, 0.214554, 0.217069, 0.223890, 0.237532",\
+ "0.447094, 0.447150, 0.447431, 0.448194, 0.449721",\
+ "1.100693, 1.100667, 1.100537, 1.100183, 1.099477",\
+ "0.071629, 0.072034, 0.074081, 0.079575, 0.090597",\
+ "0.129720, 0.130270, 0.133044, 0.140492, 0.155435",\
+ "0.214056, 0.214558, 0.217090, 0.223890, 0.237532",\
+ "0.447094, 0.447150, 0.447434, 0.448194, 0.449721",\
+ "1.100693, 1.100667, 1.100536, 1.100183, 1.099477",\
+ "0.071640, 0.072041, 0.074081, 0.079575, 0.090597",\
+ "0.129735, 0.130278, 0.133044, 0.140492, 0.155435",\
+ "0.214069, 0.214565, 0.217091, 0.223890, 0.237532",\
+ "0.447096, 0.447151, 0.447434, 0.448194, 0.449721",\
+ "1.100692, 1.100666, 1.100536, 1.100183, 1.099477",\
+ "0.071647, 0.072050, 0.074082, 0.079575, 0.090597",\
+ "0.129745, 0.130291, 0.133046, 0.140492, 0.155435",\
+ "0.214078, 0.214577, 0.217092, 0.223890, 0.237532",\
+ "0.447097, 0.447152, 0.447434, 0.448194, 0.449721",\
+ "1.100691, 1.100666, 1.100535, 1.100183, 1.099477",\
+ "0.071694, 0.072157, 0.074138, 0.079598, 0.090597",\
+ "0.129808, 0.130436, 0.133121, 0.140523, 0.155435",\
+ "0.214136, 0.214709, 0.217161, 0.223918, 0.237532",\
+ "0.447103, 0.447167, 0.447442, 0.448198, 0.449721",\
+ "1.100688, 1.100659, 1.100532, 1.100182, 1.099477");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2675*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[21]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.603037, 0.850281, 1.131477, 1.604469, 2.550452",\
+ "0.650138, 0.897409, 1.178701, 1.651927, 2.598380",\
+ "0.737413, 0.984763, 1.266326, 1.740225, 2.688022",\
+ "0.963264, 1.210735, 1.492718, 1.967654, 2.917526",\
+ "1.530512, 1.778140, 2.060669, 2.536958, 3.489536",\
+ "0.690439, 0.937872, 1.219053, 1.691182, 2.636385",\
+ "0.737540, 0.985001, 1.266277, 1.738640, 2.684314",\
+ "0.824816, 1.072355, 1.353904, 1.826938, 2.773956",\
+ "1.050667, 1.298328, 1.580299, 2.054367, 3.003459",\
+ "1.617915, 1.865734, 2.148256, 2.623672, 3.575470",\
+ "0.771264, 1.026907, 1.307016, 1.778803, 2.723340",\
+ "0.818366, 1.074036, 1.354240, 1.826261, 2.771269",\
+ "0.905641, 1.161391, 1.441867, 1.914558, 2.860911",\
+ "1.131493, 1.387366, 1.668262, 2.141988, 3.090415",\
+ "1.698741, 1.954774, 2.236218, 2.711293, 3.662425",\
+ "0.828931, 1.092619, 1.371156, 1.842715, 2.786849",\
+ "0.876032, 1.139748, 1.418380, 1.890174, 2.834778",\
+ "0.963308, 1.227105, 1.506008, 1.978471, 2.924420",\
+ "1.189160, 1.453082, 1.732403, 2.205900, 3.153924",\
+ "1.756409, 2.020493, 2.300359, 2.775205, 3.725934",\
+ "1.160146, 1.458017, 1.723059, 2.192071, 3.132305",\
+ "1.207253, 1.505153, 1.770286, 2.239531, 3.180234",\
+ "1.294543, 1.592528, 1.857920, 2.327831, 3.269876",\
+ "1.520419, 1.818533, 2.084326, 2.555264, 3.499380",\
+ "2.087698, 2.385982, 2.652296, 3.124575, 4.071390");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.053872, 0.053951, 0.054623, 0.056651, 0.060707",\
+ "0.173260, 0.173205, 0.173015, 0.172544, 0.171603",\
+ "0.375444, 0.375315, 0.374890, 0.373861, 0.371802",\
+ "0.885479, 0.885459, 0.885341, 0.885032, 0.884415",\
+ "2.163055, 2.163084, 2.163257, 2.163712, 2.164621",\
+ "0.053872, 0.053952, 0.054629, 0.056651, 0.060707",\
+ "0.173260, 0.173205, 0.173013, 0.172544, 0.171603",\
+ "0.375444, 0.375314, 0.374887, 0.373861, 0.371802",\
+ "0.885479, 0.885459, 0.885340, 0.885032, 0.884415",\
+ "2.163055, 2.163084, 2.163259, 2.163712, 2.164621",\
+ "0.053873, 0.053953, 0.054629, 0.056651, 0.060707",\
+ "0.173260, 0.173204, 0.173013, 0.172544, 0.171603",\
+ "0.375443, 0.375312, 0.374887, 0.373861, 0.371802",\
+ "0.885479, 0.885458, 0.885340, 0.885032, 0.884415",\
+ "2.163055, 2.163085, 2.163259, 2.163712, 2.164621",\
+ "0.053873, 0.053954, 0.054629, 0.056651, 0.060707",\
+ "0.173259, 0.173203, 0.173013, 0.172544, 0.171603",\
+ "0.375443, 0.375310, 0.374887, 0.373861, 0.371802",\
+ "0.885479, 0.885458, 0.885340, 0.885032, 0.884415",\
+ "2.163055, 2.163086, 2.163259, 2.163712, 2.164621",\
+ "0.053888, 0.053973, 0.054650, 0.056659, 0.060707",\
+ "0.173249, 0.173190, 0.173008, 0.172542, 0.171603",\
+ "0.375418, 0.375279, 0.374876, 0.373857, 0.371802",\
+ "0.885478, 0.885451, 0.885337, 0.885031, 0.884415",\
+ "2.163055, 2.163095, 2.163263, 2.163714, 2.164621");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.533423, 0.780287, 1.060158, 1.529873, 2.469302",\
+ "0.594392, 0.841621, 1.122764, 1.595624, 2.541345",\
+ "0.661163, 0.908679, 1.190820, 1.666147, 2.616802",\
+ "0.795368, 1.042860, 1.324916, 1.800036, 2.750276",\
+ "1.138811, 1.386156, 1.667706, 2.141570, 3.089298",\
+ "0.620825, 0.867875, 1.147723, 1.616586, 2.555236",\
+ "0.681794, 0.929212, 1.210339, 1.682338, 2.627278",\
+ "0.748566, 0.996272, 1.278403, 1.752861, 2.702736",\
+ "0.882770, 1.130452, 1.412499, 1.886750, 2.836210",\
+ "1.226213, 1.473748, 1.755284, 2.228283, 3.175232",\
+ "0.701650, 0.956905, 1.235686, 1.704207, 2.642191",\
+ "0.762619, 1.018247, 1.298302, 1.769958, 2.714233",\
+ "0.829392, 1.085311, 1.366366, 1.840481, 2.789691",\
+ "0.963596, 1.219491, 1.500462, 1.974370, 2.923165",\
+ "1.307039, 1.562785, 1.843247, 2.315904, 3.262187",\
+ "0.759315, 1.022609, 1.299826, 1.768119, 2.705700",\
+ "0.820286, 1.083958, 1.362442, 1.833871, 2.777742",\
+ "0.887059, 1.151028, 1.430506, 1.904394, 2.853200",\
+ "1.021263, 1.285207, 1.564602, 2.038283, 2.986674",\
+ "1.364706, 1.628498, 1.907387, 2.379816, 3.325696",\
+ "1.090457, 1.387917, 1.651696, 2.117462, 3.051156",\
+ "1.151498, 1.449352, 1.714345, 2.183227, 3.123199",\
+ "1.218327, 1.516490, 1.782434, 2.253760, 3.198656",\
+ "1.352526, 1.650664, 1.916528, 2.387648, 3.332130",\
+ "1.695940, 1.993920, 2.259300, 2.729176, 3.671152");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.071642, 0.072195, 0.074119, 0.078878, 0.088395",\
+ "0.129738, 0.130488, 0.133096, 0.139547, 0.152449",\
+ "0.214072, 0.214757, 0.217138, 0.223027, 0.234806",\
+ "0.447096, 0.447173, 0.447439, 0.448098, 0.449416",\
+ "1.100692, 1.100656, 1.100533, 1.100228, 1.099618",\
+ "0.071642, 0.072199, 0.074134, 0.078878, 0.088395",\
+ "0.129738, 0.130493, 0.133116, 0.139547, 0.152449",\
+ "0.214072, 0.214761, 0.217156, 0.223027, 0.234806",\
+ "0.447096, 0.447173, 0.447441, 0.448098, 0.449416",\
+ "1.100692, 1.100656, 1.100532, 1.100228, 1.099618",\
+ "0.071643, 0.072206, 0.074135, 0.078878, 0.088395",\
+ "0.129740, 0.130503, 0.133117, 0.139547, 0.152449",\
+ "0.214073, 0.214770, 0.217157, 0.223027, 0.234806",\
+ "0.447096, 0.447174, 0.447441, 0.448098, 0.449416",\
+ "1.100692, 1.100656, 1.100532, 1.100228, 1.099618",\
+ "0.071645, 0.072218, 0.074135, 0.078878, 0.088395",\
+ "0.129742, 0.130518, 0.133118, 0.139547, 0.152449",\
+ "0.214076, 0.214784, 0.217158, 0.223027, 0.234806",\
+ "0.447096, 0.447176, 0.447441, 0.448098, 0.449416",\
+ "1.100692, 1.100655, 1.100532, 1.100228, 1.099618",\
+ "0.071752, 0.072348, 0.074184, 0.078897, 0.088395",\
+ "0.129887, 0.130696, 0.133183, 0.139574, 0.152449",\
+ "0.214208, 0.214946, 0.217217, 0.223052, 0.234806",\
+ "0.447111, 0.447194, 0.447448, 0.448101, 0.449416",\
+ "1.100685, 1.100646, 1.100529, 1.100227, 1.099618");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2280*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[23]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.240088, 0.510351, 0.797290, 1.285614, 2.262263",\
+ "0.291602, 0.560872, 0.847259, 1.336249, 2.314227",\
+ "0.366122, 0.638120, 0.923420, 1.410996, 2.386150",\
+ "0.571697, 0.846754, 1.130217, 1.614147, 2.582006",\
+ "1.124964, 1.399896, 1.682080, 2.162757, 3.124112",\
+ "0.327497, 0.597936, 0.884917, 1.372329, 2.348197",\
+ "0.379011, 0.648452, 0.934889, 1.422963, 2.400161",\
+ "0.453531, 0.725696, 1.011044, 1.497711, 2.472083",\
+ "0.660133, 0.934325, 1.217830, 1.700861, 2.667939",\
+ "1.213404, 1.487464, 1.769683, 2.249471, 3.210046",\
+ "0.411710, 0.686989, 0.972882, 1.459950, 2.435152",\
+ "0.462735, 0.737494, 1.022853, 1.510585, 2.487116",\
+ "0.540482, 0.814729, 1.099009, 1.585332, 2.559038",\
+ "0.749582, 1.023346, 1.305795, 1.788483, 2.754894",\
+ "1.302860, 1.576480, 1.857647, 2.337093, 3.297001",\
+ "0.475438, 0.752729, 1.037025, 1.523864, 2.498661",\
+ "0.526464, 0.803218, 1.086996, 1.574498, 2.550625",\
+ "0.604208, 0.880438, 1.163152, 1.649246, 2.622547",\
+ "0.813313, 1.089039, 1.369937, 1.852396, 2.818403",\
+ "1.366598, 1.642166, 1.921789, 2.401006, 3.360510",\
+ "0.812369, 1.118362, 1.389087, 1.873289, 2.844117",\
+ "0.863397, 1.168668, 1.439066, 1.923926, 2.896081",\
+ "0.941125, 1.245720, 1.515207, 1.998668, 2.968004",\
+ "1.150264, 1.454128, 1.721955, 2.201803, 3.163859",\
+ "1.703596, 2.007172, 2.273774, 2.750400, 3.705966");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.247846, 0.302431, 0.404057, 0.594296, 0.974773",\
+ "0.313758, 0.345633, 0.434590, 0.626480, 1.010259",\
+ "0.435716, 0.458123, 0.529642, 0.703929, 1.052501",\
+ "0.888071, 0.889365, 0.917551, 1.014829, 1.209385",\
+ "2.165074, 2.165320, 2.171775, 2.192811, 2.234884",\
+ "0.247846, 0.302730, 0.404657, 0.594296, 0.974773",\
+ "0.313758, 0.345847, 0.435195, 0.626480, 1.010259",\
+ "0.435716, 0.458259, 0.530192, 0.703929, 1.052501",\
+ "0.888105, 0.889365, 0.917858, 1.014829, 1.209385",\
+ "2.165074, 2.165323, 2.171841, 2.192811, 2.234884",\
+ "0.250151, 0.303407, 0.404668, 0.594296, 0.974773",\
+ "0.314673, 0.346332, 0.435207, 0.626480, 1.010259",\
+ "0.436528, 0.458564, 0.530202, 0.703929, 1.052501",\
+ "0.888203, 0.889365, 0.917863, 1.014829, 1.209385",\
+ "2.165074, 2.165328, 2.171843, 2.192811, 2.234884",\
+ "0.251745, 0.304389, 0.404700, 0.594296, 0.974773",\
+ "0.315306, 0.347037, 0.435239, 0.626480, 1.010259",\
+ "0.437090, 0.459008, 0.530231, 0.703929, 1.052501",\
+ "0.888293, 0.889365, 0.917880, 1.014829, 1.209385",\
+ "2.165074, 2.165335, 2.171846, 2.192811, 2.234884",\
+ "0.261887, 0.315894, 0.406630, 0.595083, 0.974773",\
+ "0.319332, 0.355290, 0.437185, 0.627274, 1.010259",\
+ "0.440663, 0.464208, 0.531999, 0.704650, 1.052501",\
+ "0.888871, 0.889365, 0.918867, 1.015232, 1.209385",\
+ "2.165074, 2.165424, 2.172060, 2.192898, 2.234884");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.240635, 0.424668, 0.712248, 1.199722, 2.174669",\
+ "0.275706, 0.462604, 0.757879, 1.262184, 2.270793",\
+ "0.326245, 0.516372, 0.817019, 1.338091, 2.380235",\
+ "0.455748, 0.646142, 0.952035, 1.495042, 2.581054",\
+ "0.793588, 0.988001, 1.296787, 1.858775, 2.982751",\
+ "0.328044, 0.512258, 0.799873, 1.286436, 2.260602",\
+ "0.363115, 0.550213, 0.845556, 1.348898, 2.356727",\
+ "0.413654, 0.603984, 0.904750, 1.424805, 2.466169",\
+ "0.543157, 0.733746, 1.039835, 1.581756, 2.666988",\
+ "0.880997, 1.075589, 1.384646, 1.945489, 3.068685",\
+ "0.408911, 0.601324, 0.887837, 1.374058, 2.347558",\
+ "0.443982, 0.639320, 0.933522, 1.436520, 2.443682",\
+ "0.494519, 0.693099, 0.992716, 1.512427, 2.553124",\
+ "0.624023, 0.822845, 1.127803, 1.669378, 2.753943",\
+ "0.961862, 1.164649, 1.472615, 2.033111, 3.155640",\
+ "0.466595, 0.667083, 0.951980, 1.437971, 2.411067",\
+ "0.501666, 0.705138, 0.997668, 1.500433, 2.507191",\
+ "0.552202, 0.758927, 1.056865, 1.576340, 2.616633",\
+ "0.681705, 0.888650, 1.191955, 1.733291, 2.817452",\
+ "1.019543, 1.230399, 1.536770, 2.097024, 3.219149",\
+ "0.769432, 1.032936, 1.304034, 1.787393, 2.756523",\
+ "0.804503, 1.071688, 1.349892, 1.849925, 2.852647",\
+ "0.855021, 1.125605, 1.409260, 1.925902, 2.962089",\
+ "0.984519, 1.255053, 1.544572, 2.082943, 3.162908",\
+ "1.322350, 1.596157, 1.889580, 2.446754, 3.564605");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.078325, 0.113595, 0.189416, 0.342002, 0.647174",\
+ "0.120997, 0.134862, 0.194741, 0.345549, 0.647167",\
+ "0.210707, 0.216021, 0.258625, 0.388109, 0.647078",\
+ "0.448759, 0.449630, 0.471236, 0.541414, 0.681771",\
+ "1.101439, 1.102394, 1.113437, 1.151551, 1.227780",\
+ "0.078325, 0.113799, 0.189898, 0.342002, 0.647174",\
+ "0.120997, 0.134966, 0.195216, 0.345549, 0.647167",\
+ "0.210707, 0.216054, 0.259033, 0.388109, 0.647078",\
+ "0.448759, 0.449638, 0.471457, 0.541414, 0.681771",\
+ "1.101439, 1.102394, 1.113557, 1.151551, 1.227780",\
+ "0.078410, 0.114258, 0.189906, 0.342002, 0.647174",\
+ "0.121014, 0.135201, 0.195225, 0.345549, 0.647167",\
+ "0.210718, 0.216128, 0.259041, 0.388109, 0.647078",\
+ "0.448759, 0.449657, 0.471461, 0.541414, 0.681771",\
+ "1.101445, 1.102394, 1.113560, 1.151551, 1.227780",\
+ "0.078573, 0.114926, 0.189932, 0.342002, 0.647174",\
+ "0.121047, 0.135543, 0.195250, 0.345549, 0.647167",\
+ "0.210740, 0.216235, 0.259062, 0.388109, 0.647078",\
+ "0.448759, 0.449684, 0.471473, 0.541414, 0.681771",\
+ "1.101456, 1.102394, 1.113566, 1.151551, 1.227780",\
+ "0.080054, 0.122746, 0.191480, 0.342634, 0.647174",\
+ "0.121349, 0.139547, 0.196780, 0.346174, 0.647167",\
+ "0.210939, 0.217494, 0.260376, 0.388645, 0.647078",\
+ "0.448759, 0.449998, 0.472185, 0.541705, 0.681771",\
+ "1.101560, 1.102394, 1.113953, 1.151709, 1.227780");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2359*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[24]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.197425, 0.431841, 0.691115, 1.132558, 2.015443",\
+ "0.256864, 0.482200, 0.742850, 1.186401, 2.073503",\
+ "0.340685, 0.558516, 0.820189, 1.263949, 2.151470",\
+ "0.552702, 0.766228, 1.030335, 1.473577, 2.360062",\
+ "1.106653, 1.318570, 1.585965, 2.032625, 2.925946",\
+ "0.284828, 0.519347, 0.778592, 1.219271, 2.101377",\
+ "0.344267, 0.569712, 0.830334, 1.273115, 2.159437",\
+ "0.428088, 0.646034, 0.907673, 1.350662, 2.237404",\
+ "0.640105, 0.853764, 1.117818, 1.560291, 2.445995",\
+ "1.194056, 1.406120, 1.673459, 2.119339, 3.011880",\
+ "0.365631, 0.608197, 0.866553, 1.306892, 2.188332",\
+ "0.425081, 0.658572, 0.918295, 1.360735, 2.246392",\
+ "0.508910, 0.734909, 0.995634, 1.438283, 2.324359",\
+ "0.720937, 0.942676, 1.205779, 1.647911, 2.532950",\
+ "1.274892, 1.495066, 1.761420, 2.206959, 3.098835",\
+ "0.423252, 0.673639, 0.930688, 1.370805, 2.251841",\
+ "0.482725, 0.724031, 0.982430, 1.424648, 2.309901",\
+ "0.566569, 0.800388, 1.059769, 1.502196, 2.387868",\
+ "0.778616, 1.008210, 1.269914, 1.711824, 2.596459",\
+ "1.332580, 1.560649, 1.825555, 2.270872, 3.162344",\
+ "0.752151, 1.035876, 1.282272, 1.720031, 2.597297",\
+ "0.801570, 1.086457, 1.334035, 1.773883, 2.655357",\
+ "0.877150, 1.163054, 1.411376, 1.851432, 2.733324",\
+ "1.083205, 1.371523, 1.621516, 2.061058, 2.941916",\
+ "1.635753, 1.924533, 2.177192, 2.620120, 3.507800");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.177313, 0.213491, 0.303378, 0.457569, 0.765950",\
+ "0.250045, 0.279673, 0.356803, 0.520196, 0.846983",\
+ "0.414565, 0.415724, 0.459633, 0.603345, 0.890769",\
+ "0.887843, 0.887860, 0.923876, 1.046142, 1.290675",\
+ "2.163223, 2.163223, 2.177277, 2.225018, 2.320500",\
+ "0.177313, 0.213790, 0.303862, 0.457569, 0.765950",\
+ "0.250045, 0.279868, 0.357315, 0.520196, 0.846983",\
+ "0.414565, 0.415735, 0.460084, 0.603345, 0.890769",\
+ "0.887843, 0.887860, 0.924259, 1.046142, 1.290675",\
+ "2.163223, 2.163223, 2.177427, 2.225018, 2.320500",\
+ "0.177336, 0.214442, 0.303871, 0.457569, 0.765950",\
+ "0.250094, 0.280294, 0.357324, 0.520196, 0.846983",\
+ "0.414565, 0.415758, 0.460092, 0.603345, 0.890769",\
+ "0.887843, 0.887860, 0.924267, 1.046142, 1.290675",\
+ "2.163223, 2.163223, 2.177430, 2.225018, 2.320500",\
+ "0.177382, 0.215390, 0.303897, 0.457569, 0.765950",\
+ "0.250194, 0.280912, 0.357352, 0.520196, 0.846983",\
+ "0.414565, 0.415792, 0.460117, 0.603345, 0.890769",\
+ "0.887843, 0.887860, 0.924288, 1.046142, 1.290675",\
+ "2.163223, 2.163223, 2.177438, 2.225018, 2.320500",\
+ "0.179822, 0.226518, 0.305460, 0.458204, 0.765950",\
+ "0.255479, 0.288172, 0.359009, 0.520869, 0.846983",\
+ "0.414565, 0.416193, 0.461574, 0.603937, 0.890769",\
+ "0.887843, 0.887866, 0.925527, 1.046646, 1.290675",\
+ "2.163223, 2.163223, 2.177922, 2.225215, 2.320500");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.186404, 0.372214, 0.626375, 1.055893, 1.914929",\
+ "0.215796, 0.420104, 0.691914, 1.154775, 2.080498",\
+ "0.262340, 0.480772, 0.763179, 1.249218, 2.221297",\
+ "0.391105, 0.611507, 0.905161, 1.430325, 2.480653",\
+ "0.735355, 0.947201, 1.248974, 1.808736, 2.928262",\
+ "0.273807, 0.459710, 0.713814, 1.142606, 2.000863",\
+ "0.303199, 0.507653, 0.779458, 1.241489, 2.166432",\
+ "0.349742, 0.568345, 0.850795, 1.335931, 2.307231",\
+ "0.478508, 0.699079, 0.992901, 1.517038, 2.566586",\
+ "0.822757, 1.034759, 1.336822, 1.895450, 3.014196",\
+ "0.354668, 0.548536, 0.801774, 1.230227, 2.087818",\
+ "0.384060, 0.596593, 0.867420, 1.329109, 2.253387",\
+ "0.430602, 0.657342, 0.938759, 1.423552, 2.394186",\
+ "0.559360, 0.788071, 1.080866, 1.604659, 2.653542",\
+ "0.903600, 1.123721, 1.424789, 1.983071, 3.101151",\
+ "0.412406, 0.613944, 0.865907, 1.294139, 2.151327",\
+ "0.441797, 0.662169, 0.931558, 1.393022, 2.316896",\
+ "0.488337, 0.722997, 1.002901, 1.487465, 2.457695",\
+ "0.617079, 0.853721, 1.145016, 1.668572, 2.717051",\
+ "0.961302, 1.189327, 1.488945, 2.046983, 3.164660",\
+ "0.716048, 0.975780, 1.217370, 1.643317, 2.496783",\
+ "0.745435, 1.025964, 1.283359, 1.742337, 2.662352",\
+ "0.795621, 1.087736, 1.354937, 1.836875, 2.803151",\
+ "0.926531, 1.218392, 1.497448, 2.018143, 3.062507",\
+ "1.264602, 1.553481, 1.841728, 2.396697, 3.510116");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.071183, 0.106867, 0.175274, 0.296411, 0.538686",\
+ "0.120882, 0.144922, 0.213025, 0.350085, 0.624205",\
+ "0.200934, 0.210784, 0.256174, 0.378831, 0.624145",\
+ "0.444933, 0.444933, 0.478341, 0.591820, 0.818777",\
+ "1.101084, 1.102468, 1.122484, 1.190474, 1.326455",\
+ "0.071183, 0.107086, 0.175654, 0.296411, 0.538686",\
+ "0.120882, 0.145109, 0.213454, 0.350085, 0.624205",\
+ "0.200934, 0.210847, 0.256559, 0.378831, 0.624145",\
+ "0.444933, 0.444933, 0.478697, 0.591820, 0.818777",\
+ "1.101084, 1.102468, 1.122697, 1.190474, 1.326455",\
+ "0.071251, 0.107567, 0.175661, 0.296411, 0.538686",\
+ "0.120905, 0.145516, 0.213462, 0.350085, 0.624205",\
+ "0.200952, 0.210983, 0.256566, 0.378831, 0.624145",\
+ "0.444933, 0.444933, 0.478703, 0.591820, 0.818777",\
+ "1.101092, 1.102468, 1.122701, 1.190474, 1.326455",\
+ "0.071390, 0.108264, 0.175682, 0.296411, 0.538686",\
+ "0.120951, 0.146107, 0.213486, 0.350085, 0.624205",\
+ "0.200988, 0.211181, 0.256587, 0.378831, 0.624145",\
+ "0.444933, 0.444933, 0.478723, 0.591820, 0.818777",\
+ "1.101108, 1.102468, 1.122713, 1.190474, 1.326455",\
+ "0.072681, 0.116454, 0.176910, 0.296910, 0.538686",\
+ "0.121377, 0.153048, 0.214875, 0.350649, 0.624205",\
+ "0.202909, 0.213502, 0.257831, 0.379336, 0.624145",\
+ "0.444933, 0.444933, 0.479873, 0.592287, 0.818777",\
+ "1.101257, 1.102468, 1.123402, 1.190754, 1.326455");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2411*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[27]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.553758, 0.808668, 1.064878, 1.505326, 2.386221",\
+ "0.599911, 0.854821, 1.111032, 1.551482, 2.432382",\
+ "0.684215, 0.939125, 1.195335, 1.635783, 2.516678",\
+ "0.905378, 1.160288, 1.416497, 1.856937, 2.737819",\
+ "1.466255, 1.721165, 1.977368, 2.417791, 3.298636",\
+ "0.641291, 0.896159, 1.152351, 1.592039, 2.472155",\
+ "0.687444, 0.942312, 1.198505, 1.638195, 2.518316",\
+ "0.771748, 1.026616, 1.282809, 1.722496, 2.602612",\
+ "0.992912, 1.247780, 1.503970, 1.943650, 2.823752",\
+ "1.553789, 1.808657, 2.064841, 2.504504, 3.384570",\
+ "0.730669, 0.984969, 1.240312, 1.679659, 2.559110",\
+ "0.776822, 1.031122, 1.286465, 1.725815, 2.605271",\
+ "0.861126, 1.115426, 1.370769, 1.810116, 2.689567",\
+ "1.082289, 1.336589, 1.591930, 2.031271, 2.910707",\
+ "1.643166, 1.897466, 2.152802, 2.592124, 3.471525",\
+ "0.794611, 1.050352, 1.304446, 1.743572, 2.622619",\
+ "0.840764, 1.096505, 1.350600, 1.789728, 2.668780",\
+ "0.925068, 1.180809, 1.434903, 1.874029, 2.753076",\
+ "1.146232, 1.401973, 1.656065, 2.095183, 2.974216",\
+ "1.707109, 1.962849, 2.216936, 2.656037, 3.535034",\
+ "1.132859, 1.411925, 1.656019, 2.092792, 2.968075",\
+ "1.179013, 1.458078, 1.702173, 2.138948, 3.014236",\
+ "1.263317, 1.542382, 1.786476, 2.223249, 3.098532",\
+ "1.484480, 1.763546, 2.007637, 2.444404, 3.319673",\
+ "2.045357, 2.324422, 2.568509, 3.005257, 3.880490");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\
+ "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\
+ "0.380998, 0.380998, 0.381005, 0.381032, 0.381085",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\
+ "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\
+ "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\
+ "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\
+ "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\
+ "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\
+ "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\
+ "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\
+ "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\
+ "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\
+ "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\
+ "0.176967, 0.176967, 0.176985, 0.177042, 0.177156",\
+ "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162330");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.540267, 0.795177, 1.050726, 1.488938, 2.365363",\
+ "0.562618, 0.817528, 1.073077, 1.511289, 2.387713",\
+ "0.603939, 0.858848, 1.114838, 1.554540, 2.433944",\
+ "0.736907, 0.991817, 1.248027, 1.688475, 2.569372",\
+ "1.086012, 1.340922, 1.597135, 2.037591, 2.918504",\
+ "0.627801, 0.882669, 1.138192, 1.575651, 2.451297",\
+ "0.650152, 0.905020, 1.160543, 1.598002, 2.473647",\
+ "0.691472, 0.946340, 1.202309, 1.641253, 2.519878",\
+ "0.824440, 1.079308, 1.335500, 1.775188, 2.655306",\
+ "1.173546, 1.428414, 1.684608, 2.124305, 3.004438",\
+ "0.717178, 0.971478, 1.226152, 1.663272, 2.538252",\
+ "0.739529, 0.993829, 1.248503, 1.685622, 2.560602",\
+ "0.780849, 1.035149, 1.290269, 1.728874, 2.606833",\
+ "0.913818, 1.168118, 1.423461, 1.862809, 2.742261",\
+ "1.262923, 1.517223, 1.772569, 2.211925, 3.091393",\
+ "0.781121, 1.036862, 1.290286, 1.727184, 2.601761",\
+ "0.803471, 1.059212, 1.312637, 1.749535, 2.624111",\
+ "0.844792, 1.100533, 1.354404, 1.792786, 2.670342",\
+ "0.977760, 1.233501, 1.487595, 1.926721, 2.805770",\
+ "1.326866, 1.582607, 1.836703, 2.275837, 3.154902",\
+ "1.119369, 1.398434, 1.641836, 2.076395, 2.947217",\
+ "1.141720, 1.420785, 1.664187, 2.098746, 2.969567",\
+ "1.183040, 1.462106, 1.705969, 2.142004, 3.015798",\
+ "1.316008, 1.595074, 1.839168, 2.275942, 3.151226",\
+ "1.665114, 1.944180, 2.188276, 2.625058, 3.500358");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\
+ "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\
+ "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\
+ "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\
+ "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\
+ "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\
+ "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\
+ "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\
+ "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\
+ "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\
+ "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\
+ "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\
+ "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\
+ "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\
+ "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\
+ "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\
+ "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\
+ "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\
+ "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\
+ "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\
+ "0.048201, 0.048201, 0.048169, 0.048066, 0.047859",\
+ "0.098620, 0.098620, 0.098586, 0.098478, 0.098260",\
+ "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\
+ "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\
+ "1.101816, 1.101816, 1.101814, 1.101807, 1.101794");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2563*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[31]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.525875, 0.768087, 1.036195, 1.520933, 2.490408",\
+ "0.572028, 0.814241, 1.082351, 1.567096, 2.536584",\
+ "0.656332, 0.898544, 1.166652, 1.651390, 2.620866",\
+ "0.877495, 1.119706, 1.387806, 1.872524, 2.841960",\
+ "1.438372, 1.680579, 1.948659, 2.433326, 3.402659",\
+ "0.613284, 0.855558, 1.123811, 1.607647, 2.576342",\
+ "0.659437, 0.901712, 1.169967, 1.653810, 2.622518",\
+ "0.743741, 0.986015, 1.254268, 1.738104, 2.706800",\
+ "0.964904, 1.207177, 1.475422, 1.959238, 2.927894",\
+ "1.525780, 1.768050, 2.036275, 2.520041, 3.488593",\
+ "0.694098, 0.944352, 1.211775, 1.695269, 2.663297",\
+ "0.740251, 0.990506, 1.257931, 1.741431, 2.709473",\
+ "0.824555, 1.074809, 1.342232, 1.825726, 2.793755",\
+ "1.045718, 1.295971, 1.563386, 2.046860, 3.014849",\
+ "1.606595, 1.856844, 2.124239, 2.607662, 3.575548",\
+ "0.752011, 1.009716, 1.275917, 1.759182, 2.726806",\
+ "0.798164, 1.055869, 1.322073, 1.805345, 2.772982",\
+ "0.882468, 1.140173, 1.406374, 1.889639, 2.857264",\
+ "1.103631, 1.361335, 1.627528, 2.110773, 3.078358",\
+ "1.664508, 1.922208, 2.188382, 2.671575, 3.639057",\
+ "1.085549, 1.370949, 1.627944, 2.108593, 3.072262",\
+ "1.131702, 1.417103, 1.674100, 2.154755, 3.118438",\
+ "1.216006, 1.501406, 1.758401, 2.239050, 3.202720",\
+ "1.437170, 1.722567, 1.979555, 2.460184, 3.423814",\
+ "1.998046, 2.283439, 2.540407, 3.020985, 3.984513");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.051938, 0.051944, 0.051982, 0.052078, 0.052272",\
+ "0.176969, 0.176980, 0.177043, 0.177207, 0.177534",\
+ "0.380998, 0.381003, 0.381033, 0.381108, 0.381260",\
+ "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051938, 0.051944, 0.051982, 0.052078, 0.052272",\
+ "0.176969, 0.176980, 0.177044, 0.177207, 0.177534",\
+ "0.380998, 0.381004, 0.381033, 0.381108, 0.381260",\
+ "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051938, 0.051945, 0.051982, 0.052078, 0.052272",\
+ "0.176969, 0.176980, 0.177044, 0.177207, 0.177534",\
+ "0.380998, 0.381004, 0.381033, 0.381108, 0.381260",\
+ "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051938, 0.051945, 0.051982, 0.052078, 0.052272",\
+ "0.176969, 0.176981, 0.177044, 0.177207, 0.177534",\
+ "0.380998, 0.381004, 0.381033, 0.381108, 0.381260",\
+ "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051938, 0.051947, 0.051983, 0.052079, 0.052272",\
+ "0.176969, 0.176984, 0.177045, 0.177208, 0.177534",\
+ "0.380998, 0.381006, 0.381034, 0.381109, 0.381260",\
+ "0.885971, 0.885971, 0.885972, 0.885974, 0.885979",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.512519, 0.754762, 1.019445, 1.492217, 2.437761",\
+ "0.534869, 0.777112, 1.043739, 1.523217, 2.482171",\
+ "0.576190, 0.818433, 1.086345, 1.570253, 2.538069",\
+ "0.709024, 0.951236, 1.219345, 1.704084, 2.673563",\
+ "1.058130, 1.300344, 1.568461, 2.053223, 3.022748",\
+ "0.599927, 0.842233, 1.107023, 1.578931, 2.523695",\
+ "0.622278, 0.864583, 1.131338, 1.609931, 2.568105",\
+ "0.663599, 0.905904, 1.173958, 1.656967, 2.624003",\
+ "0.796432, 1.038707, 1.306960, 1.790798, 2.759497",\
+ "1.145538, 1.387814, 1.656077, 2.139938, 3.108682",\
+ "0.680742, 0.931028, 1.194987, 1.666553, 2.610650",\
+ "0.703093, 0.953378, 1.219303, 1.697553, 2.655060",\
+ "0.744413, 0.994699, 1.261922, 1.744589, 2.710958",\
+ "0.877247, 1.127501, 1.394925, 1.878420, 2.846452",\
+ "1.226353, 1.476609, 1.744041, 2.227559, 3.195637",\
+ "0.738655, 0.996392, 1.259127, 1.730466, 2.674159",\
+ "0.761006, 1.018743, 1.283444, 1.761466, 2.718569",\
+ "0.802326, 1.060063, 1.326064, 1.808502, 2.774467",\
+ "0.935160, 1.192865, 1.459067, 1.942333, 2.909961",\
+ "1.284266, 1.541972, 1.808183, 2.291472, 3.259146",\
+ "1.072193, 1.357636, 1.611032, 2.079827, 3.019615",\
+ "1.094544, 1.379987, 1.635417, 2.110855, 3.064025",\
+ "1.135864, 1.421307, 1.678082, 2.157909, 3.119923",\
+ "1.268698, 1.554098, 1.811093, 2.291744, 3.255417",\
+ "1.617804, 1.903206, 2.160210, 2.640883, 3.604602");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.048198, 0.048178, 0.048063, 0.047766, 0.047172",\
+ "0.098616, 0.098596, 0.098475, 0.098162, 0.097537",\
+ "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\
+ "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\
+ "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\
+ "0.048198, 0.048178, 0.048062, 0.047766, 0.047172",\
+ "0.098616, 0.098596, 0.098474, 0.098162, 0.097537",\
+ "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\
+ "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\
+ "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\
+ "0.048198, 0.048177, 0.048062, 0.047766, 0.047172",\
+ "0.098616, 0.098595, 0.098474, 0.098162, 0.097537",\
+ "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\
+ "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\
+ "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\
+ "0.048198, 0.048177, 0.048062, 0.047766, 0.047172",\
+ "0.098616, 0.098594, 0.098474, 0.098162, 0.097537",\
+ "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\
+ "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\
+ "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\
+ "0.048198, 0.048170, 0.048059, 0.047765, 0.047172",\
+ "0.098616, 0.098587, 0.098471, 0.098161, 0.097537",\
+ "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\
+ "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\
+ "1.101815, 1.101814, 1.101807, 1.101788, 1.101750");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[32]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.659689, 0.901731, 1.166165, 1.640730, 2.589860",\
+ "0.706217, 0.948259, 1.212695, 1.687267, 2.636411",\
+ "0.791853, 1.033895, 1.298337, 1.772929, 2.722115",\
+ "1.015175, 1.257217, 1.521667, 1.996292, 2.945540",\
+ "1.579124, 1.821166, 2.085628, 2.560294, 3.509625",\
+ "0.747090, 0.989208, 1.253745, 1.727443, 2.675794",\
+ "0.793618, 1.035736, 1.300275, 1.773980, 2.722345",\
+ "0.879254, 1.121372, 1.385917, 1.859643, 2.808049",\
+ "1.102576, 1.344694, 1.609248, 2.083005, 3.031474",\
+ "1.666525, 1.908643, 2.173209, 2.647007, 3.595559",\
+ "0.827897, 1.077990, 1.341708, 1.815064, 2.762749",\
+ "0.874425, 1.124518, 1.388238, 1.861601, 2.809300",\
+ "0.960061, 1.210154, 1.473880, 1.947263, 2.895004",\
+ "1.183383, 1.433476, 1.697210, 2.170625, 3.118429",\
+ "1.747332, 1.997425, 2.261171, 2.734627, 3.682514",\
+ "0.888137, 1.143334, 1.405848, 1.878976, 2.826258",\
+ "0.934665, 1.189862, 1.452378, 1.925513, 2.872809",\
+ "1.020301, 1.275498, 1.538020, 2.011176, 2.958513",\
+ "1.243623, 1.498820, 1.761351, 2.234538, 3.181938",\
+ "1.807572, 2.062769, 2.325312, 2.798540, 3.746023",\
+ "1.226031, 1.504429, 1.757767, 2.228338, 3.171714",\
+ "1.272558, 1.550957, 1.804297, 2.274875, 3.218265",\
+ "1.358195, 1.636593, 1.889939, 2.360538, 3.303969",\
+ "1.581517, 1.859915, 2.113271, 2.583900, 3.527394",\
+ "2.145466, 2.423864, 2.677232, 3.147902, 4.091479");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\
+ "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\
+ "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\
+ "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\
+ "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\
+ "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\
+ "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\
+ "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\
+ "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\
+ "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\
+ "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\
+ "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\
+ "0.052222, 0.052222, 0.052229, 0.052249, 0.052290",\
+ "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\
+ "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\
+ "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\
+ "2.163010, 2.163011, 2.163015, 2.163025, 2.163045");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.598065, 0.840108, 1.104513, 1.578978, 2.527908",\
+ "0.651364, 0.893406, 1.157839, 1.632400, 2.581522",\
+ "0.712119, 0.954162, 1.218616, 1.693252, 2.642524",\
+ "0.846830, 1.088872, 1.353324, 1.827954, 2.777214",\
+ "1.193335, 1.435377, 1.699819, 2.174410, 3.123593",\
+ "0.685466, 0.927585, 1.192093, 1.665691, 2.613842",\
+ "0.738765, 0.980883, 1.245419, 1.719113, 2.667456",\
+ "0.799521, 1.041639, 1.306196, 1.779965, 2.728458",\
+ "0.934231, 1.176349, 1.440905, 1.914667, 2.863148",\
+ "1.280736, 1.522854, 1.787399, 2.261123, 3.209527",\
+ "0.766273, 1.016367, 1.280056, 1.753312, 2.700797",\
+ "0.819572, 1.069665, 1.333382, 1.806733, 2.754411",\
+ "0.880328, 1.130420, 1.394158, 1.867585, 2.815413",\
+ "1.015038, 1.265131, 1.528867, 2.002288, 2.950103",\
+ "1.361543, 1.611636, 1.875361, 2.348744, 3.296482",\
+ "0.826513, 1.081711, 1.344196, 1.817225, 2.764306",\
+ "0.879812, 1.135009, 1.397522, 1.870646, 2.817920",\
+ "0.940568, 1.195765, 1.458299, 1.931498, 2.878922",\
+ "1.075278, 1.330475, 1.593008, 2.066200, 3.013612",\
+ "1.421783, 1.676980, 1.939502, 2.412656, 3.359991",\
+ "1.164407, 1.442806, 1.696114, 2.166586, 3.109762",\
+ "1.217705, 1.496104, 1.749441, 2.220008, 3.163376",\
+ "1.278461, 1.556859, 1.810219, 2.280860, 3.224378",\
+ "1.413172, 1.691570, 1.944927, 2.415563, 3.359068",\
+ "1.759677, 2.038075, 2.291421, 2.762018, 3.705447");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.060051, 0.060051, 0.060093, 0.060235, 0.060520",\
+ "0.114009, 0.114009, 0.114066, 0.114262, 0.114654",\
+ "0.199711, 0.199711, 0.199764, 0.199943, 0.200301",\
+ "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\
+ "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\
+ "0.060051, 0.060051, 0.060094, 0.060235, 0.060520",\
+ "0.114009, 0.114009, 0.114067, 0.114262, 0.114654",\
+ "0.199711, 0.199711, 0.199765, 0.199943, 0.200301",\
+ "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\
+ "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\
+ "0.060051, 0.060051, 0.060094, 0.060235, 0.060520",\
+ "0.114009, 0.114009, 0.114067, 0.114262, 0.114654",\
+ "0.199711, 0.199711, 0.199765, 0.199943, 0.200301",\
+ "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\
+ "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\
+ "0.060051, 0.060051, 0.060094, 0.060235, 0.060520",\
+ "0.114009, 0.114009, 0.114067, 0.114262, 0.114654",\
+ "0.199711, 0.199711, 0.199765, 0.199943, 0.200301",\
+ "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\
+ "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\
+ "0.060051, 0.060051, 0.060095, 0.060236, 0.060520",\
+ "0.114009, 0.114009, 0.114069, 0.114263, 0.114654",\
+ "0.199711, 0.199711, 0.199767, 0.199944, 0.200301",\
+ "0.445489, 0.445489, 0.445496, 0.445515, 0.445555",\
+ "1.101435, 1.101435, 1.101435, 1.101435, 1.101435");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2315*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[34]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.689570, 0.955359, 1.243359, 1.733584, 2.714034",\
+ "0.735723, 1.001512, 1.289513, 1.779738, 2.760189",\
+ "0.820027, 1.085816, 1.373816, 1.864041, 2.844491",\
+ "1.041190, 1.306978, 1.594979, 2.085202, 3.065649",\
+ "1.602065, 1.867854, 2.155853, 2.646073, 3.626513",\
+ "0.776981, 1.042942, 1.330993, 1.820299, 2.799968",\
+ "0.823135, 1.089095, 1.377147, 1.866453, 2.846122",\
+ "0.907439, 1.173399, 1.461450, 1.950756, 2.930425",\
+ "1.128601, 1.394562, 1.682613, 2.171917, 3.151583",\
+ "1.689477, 1.955437, 2.243487, 2.732788, 3.712447",\
+ "0.857898, 1.132003, 1.418959, 1.907921, 2.886923",\
+ "0.904051, 1.178156, 1.465112, 1.954075, 2.933077",\
+ "0.988355, 1.262460, 1.549416, 2.038378, 3.017380",\
+ "1.209518, 1.483622, 1.770578, 2.259539, 3.238538",\
+ "1.770393, 2.044498, 2.331453, 2.820410, 3.799402",\
+ "0.918904, 1.197754, 1.483102, 1.971834, 2.950432",\
+ "0.965057, 1.243907, 1.529255, 2.017988, 2.996586",\
+ "1.049361, 1.328211, 1.613559, 2.102291, 3.080889",\
+ "1.270524, 1.549374, 1.834721, 2.323452, 3.302047",\
+ "1.831399, 2.110249, 2.395596, 2.884323, 3.862911",\
+ "1.254896, 1.563490, 1.835185, 2.321270, 3.295888",\
+ "1.301049, 1.609643, 1.881339, 2.367424, 3.342042",\
+ "1.385353, 1.693947, 1.965642, 2.451727, 3.426345",\
+ "1.606516, 1.915110, 2.186805, 2.672888, 3.647503",\
+ "2.167391, 2.475986, 2.747679, 3.233759, 4.208367");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\
+ "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\
+ "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\
+ "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\
+ "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\
+ "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\
+ "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\
+ "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\
+ "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\
+ "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\
+ "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\
+ "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\
+ "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\
+ "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\
+ "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.676230, 0.942019, 1.230037, 1.720324, 2.700896",\
+ "0.698581, 0.964369, 1.252388, 1.742674, 2.723247",\
+ "0.739901, 1.005690, 1.293708, 1.783995, 2.764567",\
+ "0.872719, 1.138507, 1.426508, 1.916733, 2.897183",\
+ "1.221825, 1.487614, 1.775615, 2.265841, 3.246295",\
+ "0.763642, 1.029602, 1.317671, 1.807038, 2.786830",\
+ "0.785992, 1.051952, 1.340022, 1.829389, 2.809181",\
+ "0.827313, 1.093273, 1.381342, 1.870709, 2.850501",\
+ "0.960130, 1.226091, 1.514142, 2.003448, 2.983117",\
+ "1.309237, 1.575197, 1.863249, 2.352556, 3.332229",\
+ "0.844558, 1.118663, 1.405637, 1.894660, 2.873785",\
+ "0.866909, 1.141013, 1.427987, 1.917011, 2.896136",\
+ "0.908229, 1.182334, 1.469308, 1.958331, 2.937456",\
+ "1.041047, 1.315151, 1.602108, 2.091070, 3.070072",\
+ "1.390153, 1.664258, 1.951214, 2.440178, 3.419184",\
+ "0.905564, 1.184414, 1.469780, 1.958574, 2.937294",\
+ "0.927915, 1.206764, 1.492131, 1.980924, 2.959645",\
+ "0.969235, 1.248085, 1.533451, 2.022245, 3.000965",\
+ "1.102053, 1.380903, 1.666251, 2.154983, 3.133581",\
+ "1.451159, 1.730009, 2.015357, 2.504092, 3.482693",\
+ "1.241556, 1.550150, 1.821864, 2.308010, 3.282750",\
+ "1.263907, 1.572501, 1.844214, 2.330360, 3.305101",\
+ "1.305227, 1.613822, 1.885535, 2.371680, 3.346421",\
+ "1.438045, 1.746639, 2.018334, 2.504419, 3.479037",\
+ "1.787151, 2.095746, 2.367441, 2.853527, 3.828149");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\
+ "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\
+ "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\
+ "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\
+ "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\
+ "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\
+ "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\
+ "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\
+ "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\
+ "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\
+ "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\
+ "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\
+ "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\
+ "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\
+ "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\
+ "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\
+ "0.048192, 0.048192, 0.048185, 0.048165, 0.048124",\
+ "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\
+ "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\
+ "1.101815, 1.101815, 1.101815, 1.101813, 1.101811");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2360*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[35]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.664659, 0.924878, 1.203873, 1.666613, 2.592093",\
+ "0.710813, 0.971031, 1.250026, 1.712767, 2.638247",\
+ "0.795116, 1.055335, 1.334330, 1.797070, 2.722549",\
+ "1.016279, 1.276498, 1.555493, 2.018232, 2.943710",\
+ "1.577155, 1.837373, 2.116368, 2.579105, 3.504579",\
+ "0.752069, 1.012459, 1.291420, 1.753327, 2.678026",\
+ "0.798222, 1.058612, 1.337573, 1.799481, 2.724180",\
+ "0.882526, 1.142916, 1.421877, 1.883784, 2.808483",\
+ "1.103689, 1.364079, 1.643039, 2.104946, 3.029644",\
+ "1.664564, 1.924954, 2.203914, 2.665819, 3.590512",\
+ "0.832929, 1.101504, 1.379383, 1.840949, 2.764981",\
+ "0.879082, 1.147657, 1.425536, 1.887103, 2.811135",\
+ "0.963386, 1.231961, 1.509840, 1.971406, 2.895438",\
+ "1.184549, 1.453124, 1.731003, 2.192568, 3.116599",\
+ "1.745424, 2.013999, 2.291878, 2.753441, 3.677467",\
+ "0.893718, 1.167232, 1.443522, 1.904862, 2.828490",\
+ "0.939871, 1.213386, 1.489675, 1.951016, 2.874644",\
+ "1.024175, 1.297689, 1.573979, 2.035319, 2.958947",\
+ "1.245338, 1.518852, 1.795141, 2.256481, 3.180108",\
+ "1.806213, 2.079728, 2.356016, 2.817354, 3.740976",\
+ "1.228556, 1.532729, 1.795325, 2.254182, 3.173946",\
+ "1.274709, 1.578882, 1.841479, 2.300336, 3.220100",\
+ "1.359013, 1.663186, 1.925782, 2.384639, 3.304403",\
+ "1.580175, 1.884349, 2.146945, 2.605801, 3.525564",\
+ "2.141051, 2.445224, 2.707820, 3.166674, 4.086432");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\
+ "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\
+ "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\
+ "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\
+ "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\
+ "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\
+ "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\
+ "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\
+ "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\
+ "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\
+ "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\
+ "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\
+ "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\
+ "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\
+ "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\
+ "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\
+ "2.162330, 2.162330, 2.162330, 2.162330, 2.162330");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.651319, 0.911538, 1.190542, 1.653312, 2.578852",\
+ "0.673670, 0.933888, 1.212892, 1.675662, 2.601202",\
+ "0.714990, 0.975209, 1.254213, 1.716983, 2.642523",\
+ "0.847808, 1.108027, 1.387022, 1.849762, 2.775242",\
+ "1.196915, 1.457133, 1.736129, 2.198870, 3.124351",\
+ "0.738728, 0.999118, 1.278088, 1.740026, 2.664785",\
+ "0.761079, 1.021469, 1.300439, 1.762377, 2.687136",\
+ "0.802400, 1.062789, 1.341759, 1.803697, 2.728456",\
+ "0.935218, 1.195608, 1.474569, 1.936476, 2.861175",\
+ "1.284324, 1.544714, 1.823675, 2.285584, 3.210285",\
+ "0.819588, 1.088164, 1.366052, 1.827648, 2.751740",\
+ "0.841939, 1.110514, 1.388402, 1.849998, 2.774091",\
+ "0.883259, 1.151835, 1.429723, 1.891319, 2.815412",\
+ "1.016078, 1.284653, 1.562532, 2.024098, 2.948130",\
+ "1.365184, 1.633759, 1.911639, 2.373206, 3.297240",\
+ "0.880378, 1.153892, 1.430190, 1.891561, 2.815249",\
+ "0.902728, 1.176243, 1.452541, 1.913912, 2.837600",\
+ "0.944049, 1.217563, 1.493861, 1.955232, 2.878921",\
+ "1.076867, 1.350381, 1.626671, 2.088011, 3.011639",\
+ "1.425974, 1.699488, 1.975777, 2.437119, 3.360749",\
+ "1.215215, 1.519388, 1.781994, 2.240881, 3.160706",\
+ "1.237566, 1.541739, 1.804345, 2.263232, 3.183056",\
+ "1.278886, 1.583060, 1.845665, 2.304552, 3.224377",\
+ "1.411705, 1.715878, 1.978474, 2.437331, 3.357095",\
+ "1.760811, 2.064984, 2.327581, 2.786439, 3.706205");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\
+ "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\
+ "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\
+ "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\
+ "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\
+ "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\
+ "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\
+ "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\
+ "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\
+ "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\
+ "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\
+ "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\
+ "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\
+ "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\
+ "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\
+ "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\
+ "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\
+ "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\
+ "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\
+ "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\
+ "1.101815, 1.101815, 1.101815, 1.101814, 1.101813");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2403*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[36]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.748501, 1.009671, 1.301852, 1.810246, 2.827035",\
+ "0.794654, 1.055824, 1.348005, 1.856399, 2.873188",\
+ "0.878958, 1.140128, 1.432309, 1.940704, 2.957492",\
+ "1.100121, 1.361291, 1.653472, 2.161867, 3.178656",\
+ "1.660998, 1.922168, 2.214350, 2.722744, 3.739532",\
+ "0.835913, 1.097245, 1.389544, 1.896961, 2.912969",\
+ "0.882066, 1.143398, 1.435697, 1.943114, 2.959122",\
+ "0.966370, 1.227702, 1.520001, 2.027418, 3.043426",\
+ "1.187534, 1.448865, 1.741165, 2.248582, 3.264589",\
+ "1.748411, 2.009742, 2.302042, 2.809459, 3.825466",\
+ "0.916813, 1.186291, 1.477511, 1.984584, 2.999924",\
+ "0.962966, 1.232444, 1.523664, 2.030737, 3.046077",\
+ "1.047270, 1.316748, 1.607968, 2.115041, 3.130381",\
+ "1.268433, 1.537911, 1.829131, 2.336204, 3.351544",\
+ "1.829310, 2.098788, 2.390008, 2.897081, 3.912421",\
+ "0.976448, 1.252020, 1.541657, 2.048497, 3.063433",\
+ "1.022601, 1.298173, 1.587810, 2.094650, 3.109586",\
+ "1.106905, 1.382477, 1.672114, 2.178954, 3.193890",\
+ "1.328068, 1.603641, 1.893278, 2.400118, 3.415053",\
+ "1.888945, 2.164518, 2.454154, 2.960994, 3.975930",\
+ "1.310176, 1.617488, 1.893926, 2.398009, 3.408889",\
+ "1.356329, 1.663641, 1.940079, 2.444162, 3.455042",\
+ "1.440634, 1.747945, 2.024383, 2.528466, 3.539346",\
+ "1.661797, 1.969109, 2.245546, 2.749630, 3.760509",\
+ "2.222674, 2.529986, 2.806423, 3.310507, 4.321386");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.735004, 0.996174, 1.288355, 1.796750, 2.813539",\
+ "0.757355, 1.018525, 1.310706, 1.819101, 2.835889",\
+ "0.798676, 1.059846, 1.352027, 1.860421, 2.877210",\
+ "0.931650, 1.192820, 1.485001, 1.993395, 3.010184",\
+ "1.280755, 1.541925, 1.834106, 2.342501, 3.359290",\
+ "0.822417, 1.083748, 1.376048, 1.883465, 2.899472",\
+ "0.844768, 1.106099, 1.398399, 1.905816, 2.921823",\
+ "0.886088, 1.147419, 1.439719, 1.947136, 2.963144",\
+ "1.019062, 1.280394, 1.572693, 2.080110, 3.096118",\
+ "1.368168, 1.629499, 1.921799, 2.429216, 3.445223",\
+ "0.903316, 1.172794, 1.464014, 1.971087, 2.986427",\
+ "0.925667, 1.195145, 1.486365, 1.993438, 3.008778",\
+ "0.966988, 1.236465, 1.527686, 2.034758, 3.050099",\
+ "1.099962, 1.369439, 1.660660, 2.167732, 3.183073",\
+ "1.449067, 1.718545, 2.009765, 2.516838, 3.532178",\
+ "0.962951, 1.238524, 1.528160, 2.035001, 3.049936",\
+ "0.985302, 1.260875, 1.550511, 2.057351, 3.072287",\
+ "1.026623, 1.302195, 1.591832, 2.098672, 3.113608",\
+ "1.159597, 1.435169, 1.724806, 2.231646, 3.246582",\
+ "1.508702, 1.784275, 2.073912, 2.580752, 3.595687",\
+ "1.296680, 1.603992, 1.880429, 2.384513, 3.395392",\
+ "1.319031, 1.626343, 1.902780, 2.406864, 3.417743",\
+ "1.360351, 1.667663, 1.944100, 2.448184, 3.459064",\
+ "1.493325, 1.800637, 2.077075, 2.581158, 3.592038",\
+ "1.842431, 2.149743, 2.426180, 2.930264, 3.941144");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\
+ "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\
+ "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\
+ "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\
+ "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2467*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[37]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.730463, 0.984563, 1.266812, 1.735637, 2.673288",\
+ "0.776616, 1.030716, 1.312965, 1.781790, 2.719441",\
+ "0.860920, 1.115021, 1.397269, 1.866094, 2.803746",\
+ "1.082084, 1.336184, 1.618432, 2.087258, 3.024909",\
+ "1.642961, 1.897061, 2.179309, 2.648135, 3.585786",\
+ "0.817871, 1.072157, 1.354377, 1.822352, 2.759222",\
+ "0.864024, 1.118310, 1.400530, 1.868505, 2.805375",\
+ "0.948328, 1.202614, 1.484834, 1.952809, 2.889679",\
+ "1.169492, 1.423777, 1.705998, 2.173972, 3.110843",\
+ "1.730369, 1.984654, 2.266875, 2.734849, 3.671720",\
+ "0.898712, 1.161224, 1.442341, 1.909973, 2.846177",\
+ "0.944865, 1.207377, 1.488494, 1.956126, 2.892330",\
+ "1.029169, 1.291681, 1.572798, 2.040430, 2.976635",\
+ "1.250332, 1.512845, 1.793961, 2.261594, 3.197798",\
+ "1.811209, 2.073722, 2.354838, 2.822471, 3.758675",\
+ "0.956353, 1.226984, 1.506480, 1.973886, 2.909686",\
+ "1.002506, 1.273137, 1.552633, 2.020039, 2.955839",\
+ "1.086810, 1.357441, 1.636937, 2.104343, 3.040143",\
+ "1.307973, 1.578604, 1.858101, 2.325507, 3.261307",\
+ "1.868850, 2.139482, 2.418978, 2.886384, 3.822184",\
+ "1.288825, 1.592869, 1.858345, 2.323230, 3.255142",\
+ "1.334978, 1.639022, 1.904498, 2.369383, 3.301295",\
+ "1.419282, 1.723326, 1.988802, 2.453687, 3.385599",\
+ "1.640445, 1.944490, 2.209965, 2.674851, 3.606763",\
+ "2.201322, 2.505367, 2.770842, 3.235728, 4.167640");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\
+ "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\
+ "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\
+ "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\
+ "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\
+ "2.162331, 2.162331, 2.162331, 2.162331, 2.162331");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.716967, 0.971067, 1.253316, 1.722141, 2.659792",\
+ "0.739318, 0.993418, 1.275667, 1.744492, 2.682143",\
+ "0.780639, 1.034739, 1.316987, 1.785813, 2.723464",\
+ "0.913612, 1.167712, 1.449961, 1.918786, 2.856437",\
+ "1.262718, 1.516818, 1.799066, 2.267892, 3.205543",\
+ "0.804375, 1.058661, 1.340881, 1.808856, 2.745726",\
+ "0.826726, 1.081012, 1.363232, 1.831207, 2.768077",\
+ "0.868047, 1.122332, 1.404552, 1.872527, 2.809398",\
+ "1.001020, 1.255306, 1.537526, 2.005501, 2.942371",\
+ "1.350126, 1.604411, 1.886632, 2.354606, 3.291477",\
+ "0.885216, 1.147728, 1.428845, 1.896477, 2.832681",\
+ "0.907567, 1.170079, 1.451195, 1.918828, 2.855032",\
+ "0.948887, 1.211399, 1.492516, 1.960149, 2.896353",\
+ "1.081861, 1.344373, 1.625489, 2.093122, 3.029326",\
+ "1.430966, 1.693479, 1.974595, 2.442228, 3.378432",\
+ "0.942857, 1.213488, 1.492984, 1.960390, 2.896190",\
+ "0.965208, 1.235839, 1.515335, 1.982741, 2.918541",\
+ "1.006528, 1.277159, 1.556656, 2.024062, 2.959862",\
+ "1.139502, 1.410133, 1.689629, 2.157035, 3.092835",\
+ "1.488607, 1.759238, 2.038735, 2.506141, 3.441941",\
+ "1.275329, 1.579373, 1.844849, 2.309734, 3.241646",\
+ "1.297680, 1.601724, 1.867200, 2.332085, 3.263997",\
+ "1.339000, 1.643044, 1.908520, 2.373406, 3.305318",\
+ "1.471974, 1.776018, 2.041493, 2.506379, 3.438291",\
+ "1.821079, 2.125124, 2.390599, 2.855485, 3.787397");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\
+ "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\
+ "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\
+ "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\
+ "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\
+ "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\
+ "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\
+ "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\
+ "1.101816, 1.101816, 1.101816, 1.101816, 1.101816");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2517*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[40]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.732857, 0.971343, 1.249163, 1.734893, 2.706354",\
+ "0.779384, 1.017870, 1.295690, 1.781420, 2.752881",\
+ "0.865018, 1.103504, 1.381324, 1.867054, 2.838515",\
+ "1.088337, 1.326823, 1.604643, 2.090373, 3.061833",\
+ "1.652282, 1.890768, 2.168588, 2.654318, 3.625778",\
+ "0.820269, 1.058867, 1.336783, 1.821608, 2.792287",\
+ "0.866797, 1.105394, 1.383311, 1.868135, 2.838814",\
+ "0.952431, 1.191029, 1.468945, 1.953769, 2.924448",\
+ "1.175750, 1.414347, 1.692263, 2.177088, 3.147767",\
+ "1.739695, 1.978293, 2.256209, 2.741033, 3.711712",\
+ "0.901137, 1.147799, 1.424749, 1.909230, 2.879242",\
+ "0.947664, 1.194327, 1.471276, 1.955757, 2.925770",\
+ "1.033299, 1.279961, 1.556910, 2.041391, 3.011404",\
+ "1.256617, 1.503280, 1.780229, 2.264710, 3.234722",\
+ "1.820563, 2.067225, 2.344174, 2.828655, 3.798667",\
+ "0.958789, 1.213364, 1.488891, 1.973144, 2.942751",\
+ "1.005316, 1.259891, 1.535418, 2.019671, 2.989279",\
+ "1.090950, 1.345525, 1.621053, 2.105305, 3.074913",\
+ "1.314269, 1.568844, 1.844371, 2.328624, 3.298231",\
+ "1.878214, 2.132789, 2.408317, 2.892569, 3.862176",\
+ "1.276921, 1.576900, 1.840930, 2.322562, 3.288208",\
+ "1.323448, 1.623428, 1.887457, 2.369089, 3.334734",\
+ "1.409082, 1.709062, 1.973091, 2.454723, 3.420369",\
+ "1.632401, 1.932381, 2.196410, 2.678042, 3.643687",\
+ "2.196346, 2.496326, 2.760355, 3.241987, 4.207632");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\
+ "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\
+ "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\
+ "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\
+ "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\
+ "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\
+ "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\
+ "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\
+ "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\
+ "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\
+ "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\
+ "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\
+ "2.163010, 2.163010, 2.163010, 2.163012, 2.163014");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.671243, 0.909729, 1.187549, 1.673279, 2.644740",\
+ "0.724532, 0.963018, 1.240838, 1.726568, 2.698029",\
+ "0.785280, 1.023767, 1.301586, 1.787316, 2.758777",\
+ "0.919992, 1.158478, 1.436297, 1.922028, 2.893488",\
+ "1.266500, 1.504986, 1.782806, 2.268536, 3.239997",\
+ "0.758655, 0.997253, 1.275169, 1.759994, 2.730674",\
+ "0.811945, 1.050542, 1.328459, 1.813283, 2.783962",\
+ "0.872693, 1.111291, 1.389207, 1.874031, 2.844710",\
+ "1.007404, 1.246002, 1.523918, 2.008743, 2.979422",\
+ "1.353913, 1.592511, 1.870427, 2.355251, 3.325931",\
+ "0.839523, 1.086185, 1.363135, 1.847616, 2.817629",\
+ "0.892813, 1.139475, 1.416424, 1.900905, 2.870918",\
+ "0.953561, 1.200223, 1.477172, 1.961653, 2.931665",\
+ "1.088272, 1.334934, 1.611884, 2.096365, 3.066377",\
+ "1.434781, 1.681443, 1.958392, 2.442873, 3.412886",\
+ "0.897175, 1.151750, 1.427277, 1.911530, 2.881138",\
+ "0.950464, 1.205039, 1.480567, 1.964819, 2.934427",\
+ "1.011212, 1.265788, 1.541315, 2.025567, 2.995174",\
+ "1.145923, 1.400499, 1.676026, 2.160278, 3.129886",\
+ "1.492432, 1.747007, 2.022535, 2.506787, 3.476395",\
+ "1.215307, 1.515286, 1.779316, 2.260948, 3.226594",\
+ "1.268596, 1.568576, 1.832605, 2.314237, 3.279882",\
+ "1.329345, 1.629324, 1.893353, 2.374985, 3.340631",\
+ "1.464056, 1.764035, 2.028064, 2.509696, 3.475342",\
+ "1.810564, 2.110544, 2.374573, 2.856205, 3.821851");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\
+ "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\
+ "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\
+ "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\
+ "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\
+ "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\
+ "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\
+ "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\
+ "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\
+ "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\
+ "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\
+ "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\
+ "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\
+ "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\
+ "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\
+ "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\
+ "1.101436, 1.101436, 1.101436, 1.101436, 1.101436");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2654*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[46]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.687805, 0.938142, 1.214956, 1.708122, 2.694454",\
+ "0.734333, 0.984670, 1.261485, 1.754655, 2.740993",\
+ "0.819969, 1.070307, 1.347124, 1.840302, 2.826659",\
+ "1.043291, 1.293629, 1.570450, 2.063643, 3.050026",\
+ "1.607241, 1.857579, 2.134405, 2.627615, 3.614036",\
+ "0.775217, 1.025647, 1.302601, 1.794837, 2.780388",\
+ "0.821745, 1.072175, 1.349129, 1.841369, 2.826927",\
+ "0.907382, 1.157812, 1.434768, 1.927017, 2.912592",\
+ "1.130704, 1.381134, 1.658095, 2.150357, 3.135960",\
+ "1.694654, 1.945083, 2.222049, 2.714330, 3.699970",\
+ "0.856074, 1.114534, 1.390566, 1.882460, 2.867343",\
+ "0.902602, 1.161062, 1.437095, 1.928992, 2.913882",\
+ "0.988238, 1.246698, 1.522734, 2.014640, 2.999547",\
+ "1.211560, 1.470021, 1.746060, 2.237980, 3.222915",\
+ "1.775510, 2.033970, 2.310015, 2.801953, 3.786925",\
+ "0.913872, 1.180032, 1.454710, 1.946373, 2.930852",\
+ "0.960400, 1.226560, 1.501239, 1.992905, 2.977391",\
+ "1.046036, 1.312197, 1.586878, 2.078553, 3.063056",\
+ "1.269358, 1.535519, 1.810204, 2.301893, 3.286424",\
+ "1.833308, 2.099468, 2.374159, 2.865866, 3.850434",\
+ "1.246728, 1.542797, 1.806824, 2.295822, 3.276308",\
+ "1.293256, 1.589325, 1.853353, 2.342354, 3.322847",\
+ "1.378892, 1.674961, 1.938992, 2.428002, 3.408513",\
+ "1.602214, 1.898283, 2.162318, 2.651342, 3.631880",\
+ "2.166164, 2.462233, 2.726274, 3.215315, 4.195890");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\
+ "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\
+ "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\
+ "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\
+ "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\
+ "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\
+ "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\
+ "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\
+ "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\
+ "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\
+ "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\
+ "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\
+ "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\
+ "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\
+ "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\
+ "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\
+ "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\
+ "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\
+ "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\
+ "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\
+ "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\
+ "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\
+ "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\
+ "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\
+ "2.163010, 2.163010, 2.163012, 2.163018, 2.163031");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.626180, 0.876518, 1.153319, 1.646441, 2.632685",\
+ "0.679480, 0.929817, 1.206631, 1.699795, 2.686123",\
+ "0.740236, 0.990574, 1.267397, 1.760594, 2.746988",\
+ "0.874947, 1.125284, 1.402106, 1.895301, 2.881690",\
+ "1.221451, 1.471789, 1.748606, 2.241784, 3.228139",\
+ "0.713593, 0.964022, 1.240963, 1.733156, 2.718619",\
+ "0.766892, 1.017322, 1.294275, 1.786510, 2.772057",\
+ "0.827649, 1.078079, 1.355041, 1.847309, 2.832922",\
+ "0.962359, 1.212789, 1.489751, 1.982016, 2.967624",\
+ "1.308864, 1.559294, 1.836250, 2.328499, 3.314073",\
+ "0.794449, 1.052909, 1.328929, 1.820778, 2.805574",\
+ "0.847749, 1.106209, 1.382241, 1.874132, 2.859012",\
+ "0.908505, 1.166965, 1.443007, 1.934931, 2.919877",\
+ "1.043216, 1.301676, 1.577716, 2.069638, 3.054579",\
+ "1.389720, 1.648180, 1.924216, 2.416121, 3.401028",\
+ "0.852247, 1.118408, 1.393072, 1.884692, 2.869083",\
+ "0.905546, 1.171707, 1.446384, 1.938046, 2.922521",\
+ "0.966303, 1.232464, 1.507150, 1.998845, 2.983386",\
+ "1.101013, 1.367174, 1.641860, 2.133552, 3.118088",\
+ "1.447518, 1.713679, 1.988360, 2.480035, 3.464537",\
+ "1.185103, 1.481172, 1.745186, 2.234141, 3.214539",\
+ "1.238403, 1.534472, 1.798498, 2.287495, 3.267977",\
+ "1.299159, 1.595228, 1.859265, 2.348294, 3.328842",\
+ "1.433870, 1.729939, 1.993974, 2.483001, 3.463544",\
+ "1.780374, 2.076443, 2.340474, 2.829484, 3.809993");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\
+ "0.114010, 0.114010, 0.114035, 0.114122, 0.114295",\
+ "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\
+ "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\
+ "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\
+ "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\
+ "0.114010, 0.114010, 0.114035, 0.114122, 0.114295",\
+ "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\
+ "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\
+ "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\
+ "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\
+ "0.114010, 0.114010, 0.114035, 0.114122, 0.114295",\
+ "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\
+ "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\
+ "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\
+ "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\
+ "0.114010, 0.114010, 0.114036, 0.114122, 0.114295",\
+ "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\
+ "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\
+ "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\
+ "0.060053, 0.060053, 0.060071, 0.060134, 0.060259",\
+ "0.114010, 0.114010, 0.114036, 0.114122, 0.114295",\
+ "0.199713, 0.199713, 0.199737, 0.199815, 0.199972",\
+ "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\
+ "1.101435, 1.101435, 1.101434, 1.101430, 1.101422");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2645*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[17]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.486994, 0.689024, 0.898048, 1.222707, 1.844099",\
+ "0.536854, 0.738884, 0.947908, 1.272568, 1.893960",\
+ "0.638722, 0.840752, 1.049776, 1.374436, 1.995828",\
+ "0.876584, 1.078614, 1.287637, 1.612297, 2.233689",\
+ "1.448904, 1.650934, 1.859958, 2.184618, 2.806009",\
+ "0.575735, 0.776343, 0.985328, 1.310012, 1.931453",\
+ "0.625596, 0.826203, 1.035189, 1.359873, 1.981313",\
+ "0.727464, 0.928071, 1.137057, 1.461741, 2.083181",\
+ "0.965325, 1.165933, 1.374918, 1.699602, 2.321043",\
+ "1.537645, 1.738253, 1.947239, 2.271923, 2.893363",\
+ "0.665418, 0.856680, 1.065355, 1.390041, 2.011484",\
+ "0.715279, 0.906541, 1.115216, 1.439901, 2.061345",\
+ "0.817147, 1.008409, 1.217084, 1.541770, 2.163213",\
+ "1.055008, 1.246270, 1.454945, 1.779631, 2.401074",\
+ "1.627329, 1.818590, 2.027266, 2.351951, 2.973394",\
+ "0.724126, 0.914549, 1.123120, 1.447544, 2.068644",\
+ "0.773987, 0.964410, 1.172981, 1.497404, 2.118505",\
+ "0.875855, 1.066278, 1.274849, 1.599272, 2.220373",\
+ "1.113716, 1.304139, 1.512710, 1.837134, 2.458234",\
+ "1.686036, 1.876459, 2.085031, 2.409454, 3.030555",\
+ "1.026901, 1.220157, 1.426788, 1.750778, 2.371040",\
+ "1.076761, 1.270018, 1.476649, 1.800639, 2.420901",\
+ "1.178629, 1.371886, 1.578517, 1.902507, 2.522769",\
+ "1.416491, 1.609747, 1.816378, 2.140368, 2.760630",\
+ "1.988811, 2.182067, 2.388699, 2.712689, 3.332951");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.527722, 0.729752, 0.938776, 1.263436, 1.884828",\
+ "0.550072, 0.752102, 0.961126, 1.285786, 1.907177",\
+ "0.591435, 0.793465, 1.002489, 1.327149, 1.948541",\
+ "0.713471, 0.915501, 1.124525, 1.449185, 2.070576",\
+ "1.045084, 1.247114, 1.456138, 1.780797, 2.402189",\
+ "0.616463, 0.817071, 1.026057, 1.350741, 1.972181",\
+ "0.638813, 0.839421, 1.048407, 1.373091, 1.994531",\
+ "0.680177, 0.880784, 1.089770, 1.414454, 2.035894",\
+ "0.802212, 1.002820, 1.211806, 1.536490, 2.157930",\
+ "1.133825, 1.334433, 1.543419, 1.868103, 2.489543",\
+ "0.706147, 0.897409, 1.106084, 1.430769, 2.052213",\
+ "0.728497, 0.919758, 1.128434, 1.453119, 2.074563",\
+ "0.769860, 0.961122, 1.169797, 1.494483, 2.115926",\
+ "0.891896, 1.083158, 1.291833, 1.616518, 2.237962",\
+ "1.223509, 1.414770, 1.623446, 1.948131, 2.569574",\
+ "0.764855, 0.955278, 1.163849, 1.488272, 2.109373",\
+ "0.787204, 0.977627, 1.186199, 1.510622, 2.131722",\
+ "0.828568, 1.018991, 1.227562, 1.551985, 2.173086",\
+ "0.950603, 1.141026, 1.349598, 1.674021, 2.295122",\
+ "1.282216, 1.472639, 1.681211, 2.005634, 2.626734",\
+ "1.067629, 1.260886, 1.467517, 1.791507, 2.411769",\
+ "1.089979, 1.283235, 1.489867, 1.813857, 2.434119",\
+ "1.131342, 1.324599, 1.531230, 1.855220, 2.475482",\
+ "1.253378, 1.446635, 1.653266, 1.977256, 2.597517",\
+ "1.584991, 1.778247, 1.984879, 2.308869, 2.929131");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011");
+ values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2543*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[19]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.402983, 0.589298, 0.781819, 1.078308, 1.645139",\
+ "0.452846, 0.639161, 0.831682, 1.128171, 1.695002",\
+ "0.554714, 0.741029, 0.933550, 1.230039, 1.796870",\
+ "0.792575, 0.978890, 1.171412, 1.467901, 2.034731",\
+ "1.364896, 1.551211, 1.743732, 2.040221, 2.607052",\
+ "0.491182, 0.676616, 0.869099, 1.165613, 1.732492",\
+ "0.541046, 0.726479, 0.918963, 1.215477, 1.782355",\
+ "0.642913, 0.828347, 1.020831, 1.317344, 1.884223",\
+ "0.880775, 1.066208, 1.258693, 1.555206, 2.122085",\
+ "1.453095, 1.638529, 1.831013, 2.127527, 2.694405",\
+ "0.578213, 0.756948, 0.949126, 1.245641, 1.812524",\
+ "0.628077, 0.806812, 0.998990, 1.295505, 1.862387",\
+ "0.729944, 0.908679, 1.100858, 1.397373, 1.964255",\
+ "0.967806, 1.146541, 1.338719, 1.635234, 2.202116",\
+ "1.540126, 1.718862, 1.911040, 2.207555, 2.774437",\
+ "0.635881, 0.814778, 1.006854, 1.303079, 1.869555",\
+ "0.685744, 0.864642, 1.056718, 1.352942, 1.919418",\
+ "0.787612, 0.966509, 1.158586, 1.454810, 2.021286",\
+ "1.025473, 1.204371, 1.396447, 1.692672, 2.259147",\
+ "1.597794, 1.776692, 1.968768, 2.264992, 2.831468",\
+ "0.938596, 1.120091, 1.310515, 1.606257, 2.171795",\
+ "0.988459, 1.169954, 1.360379, 1.656120, 2.221658",\
+ "1.090327, 1.271822, 1.462247, 1.757988, 2.323526",\
+ "1.328188, 1.509683, 1.700108, 1.995849, 2.561387",\
+ "1.900509, 2.082004, 2.272429, 2.568170, 3.133708");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\
+ "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\
+ "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\
+ "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\
+ "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\
+ "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.423040, 0.630029, 0.815796, 1.107776, 1.669457",\
+ "0.466065, 0.652380, 0.844901, 1.141390, 1.708220",\
+ "0.507428, 0.693743, 0.886264, 1.182753, 1.749583",\
+ "0.629463, 0.815778, 1.008300, 1.304789, 1.871619",\
+ "0.961076, 1.147391, 1.339912, 1.636401, 2.203231",\
+ "0.511411, 0.717348, 0.903077, 1.195081, 1.756810",\
+ "0.554264, 0.739698, 0.932182, 1.228695, 1.795574",\
+ "0.595627, 0.781061, 0.973545, 1.270058, 1.836937",\
+ "0.717663, 0.903096, 1.095581, 1.392094, 1.958972",\
+ "1.049275, 1.234709, 1.427193, 1.723706, 2.290585",\
+ "0.600722, 0.797680, 0.983104, 1.275110, 1.836842",\
+ "0.641295, 0.820030, 1.012209, 1.308724, 1.875605",\
+ "0.682658, 0.861393, 1.053572, 1.350087, 1.916969",\
+ "0.804694, 0.983429, 1.175608, 1.472122, 2.039004",\
+ "1.136306, 1.315041, 1.507220, 1.803735, 2.370616",\
+ "0.664349, 0.855510, 1.040816, 1.332541, 1.893861",\
+ "0.698963, 0.877860, 1.069937, 1.366161, 1.932636",\
+ "0.740326, 0.919223, 1.111300, 1.407524, 1.974000",\
+ "0.862361, 1.041259, 1.233335, 1.529560, 2.096035",\
+ "1.193974, 1.372871, 1.564948, 1.861172, 2.427648",\
+ "0.979328, 1.160823, 1.344474, 1.635713, 2.196086",\
+ "1.001678, 1.183173, 1.373598, 1.669339, 2.234876",\
+ "1.043041, 1.224536, 1.414961, 1.710702, 2.276240",\
+ "1.165076, 1.346571, 1.536997, 1.832738, 2.398275",\
+ "1.496689, 1.678184, 1.868609, 2.164350, 2.729888");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011");
+ values ( "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2604*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[21]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.374729, 0.574327, 0.761134, 1.059803, 1.637058",\
+ "0.424592, 0.624191, 0.810999, 1.109666, 1.686921",\
+ "0.526460, 0.726059, 0.912867, 1.211534, 1.788789",\
+ "0.764322, 0.963920, 1.150728, 1.449396, 2.026650",\
+ "1.336642, 1.536241, 1.723049, 2.021717, 2.598970",\
+ "0.463046, 0.661644, 0.848415, 1.147108, 1.724412",\
+ "0.512909, 0.711509, 0.898280, 1.196972, 1.774274",\
+ "0.614777, 0.813377, 1.000148, 1.298839, 1.876142",\
+ "0.852638, 1.051238, 1.238009, 1.536701, 2.114003",\
+ "1.424959, 1.623559, 1.810330, 2.109022, 2.686324",\
+ "0.552645, 0.741973, 0.928442, 1.227136, 1.804443",\
+ "0.602508, 0.791838, 0.978307, 1.277000, 1.854306",\
+ "0.704376, 0.893705, 1.080175, 1.378868, 1.956174",\
+ "0.942238, 1.131567, 1.318036, 1.616729, 2.194035",\
+ "1.514558, 1.703888, 1.890357, 2.189050, 2.766356",\
+ "0.616737, 0.799794, 0.986158, 1.284587, 1.861501",\
+ "0.666600, 0.849659, 1.036023, 1.334451, 1.911364",\
+ "0.768468, 0.951526, 1.137890, 1.436318, 2.013232",\
+ "1.006329, 1.189388, 1.375752, 1.674180, 2.251093",\
+ "1.578650, 1.761709, 1.948073, 2.246500, 2.823413",\
+ "0.927115, 1.105032, 1.289816, 1.587775, 2.163774",\
+ "0.976978, 1.154897, 1.339680, 1.637639, 2.213636",\
+ "1.078846, 1.256764, 1.441548, 1.739507, 2.315504",\
+ "1.316707, 1.494626, 1.679409, 1.977368, 2.553366",\
+ "1.889028, 2.066947, 2.251730, 2.549689, 3.125686");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\
+ "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.405230, 0.615060, 0.801868, 1.100535, 1.677789",\
+ "0.437811, 0.637410, 0.824218, 1.122885, 1.700139",\
+ "0.479174, 0.678774, 0.865581, 1.164248, 1.741502",\
+ "0.601210, 0.800809, 0.987617, 1.286284, 1.863538",\
+ "0.932822, 1.132421, 1.319229, 1.617896, 2.195150",\
+ "0.493512, 0.702378, 0.889149, 1.187840, 1.765142",\
+ "0.526127, 0.724728, 0.911499, 1.210190, 1.787492",\
+ "0.567491, 0.766091, 0.952862, 1.251554, 1.828856",\
+ "0.689526, 0.888126, 1.074898, 1.373589, 1.950891",\
+ "1.021139, 1.219739, 1.406510, 1.705201, 2.282504",\
+ "0.583007, 0.782706, 0.969176, 1.267869, 1.845174",\
+ "0.615727, 0.805056, 0.991526, 1.290219, 1.867524",\
+ "0.657090, 0.846420, 1.032889, 1.331582, 1.908887",\
+ "0.779126, 0.968455, 1.154925, 1.453618, 2.030923",\
+ "1.110738, 1.300067, 1.486537, 1.785230, 2.362535",\
+ "0.646999, 0.840528, 1.026891, 1.325319, 1.902232",\
+ "0.679819, 0.862878, 1.049241, 1.347669, 1.924582",\
+ "0.721182, 0.904241, 1.090605, 1.389032, 1.965945",\
+ "0.843217, 1.026276, 1.212640, 1.511068, 2.087981",\
+ "1.174830, 1.357889, 1.544252, 1.842680, 2.419593",\
+ "0.967847, 1.145766, 1.330549, 1.628508, 2.204504",\
+ "0.990197, 1.168116, 1.352899, 1.650858, 2.226855",\
+ "1.031560, 1.209479, 1.394262, 1.692221, 2.268218",\
+ "1.153596, 1.331514, 1.516298, 1.814256, 2.390253",\
+ "1.485208, 1.663126, 1.847910, 2.145869, 2.721866");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2705*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[23]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.222114, 0.403093, 0.604570, 0.931647, 1.565679",\
+ "0.278140, 0.457431, 0.657946, 0.989844, 1.636478",\
+ "0.353958, 0.531643, 0.731437, 1.068535, 1.728488",\
+ "0.556156, 0.731457, 0.928039, 1.271464, 1.949653",\
+ "1.100796, 1.274143, 1.466860, 1.814002, 2.504620",\
+ "0.309523, 0.490411, 0.691851, 1.018952, 1.653032",\
+ "0.365549, 0.544749, 0.745227, 1.077150, 1.723831",\
+ "0.441367, 0.618961, 0.818717, 1.155840, 1.815842",\
+ "0.643566, 0.818775, 1.015320, 1.358769, 2.037007",\
+ "1.188205, 1.361462, 1.554141, 1.901307, 2.591974",\
+ "0.390388, 0.570744, 0.771878, 1.098981, 1.733064",\
+ "0.446403, 0.625082, 0.825254, 1.157178, 1.803863",\
+ "0.522211, 0.699294, 0.898744, 1.235869, 1.895873",\
+ "0.724394, 0.899108, 1.095347, 1.438797, 2.117038",\
+ "1.269020, 1.441795, 1.634168, 1.981336, 2.672005",\
+ "0.448070, 0.628579, 0.829627, 1.156500, 1.790257",\
+ "0.504064, 0.682912, 0.883001, 1.214712, 1.861086",\
+ "0.579852, 0.757117, 0.956490, 1.293419, 1.953129",\
+ "0.782005, 0.956923, 1.153085, 1.496370, 2.174338",\
+ "1.326607, 1.499602, 1.691897, 2.038924, 2.729335",\
+ "0.750884, 0.933934, 1.133292, 1.459748, 2.092693",\
+ "0.806686, 0.988222, 1.186665, 1.517973, 2.163558",\
+ "0.882290, 1.062385, 1.260154, 1.596694, 2.255640",\
+ "1.084171, 1.262128, 1.456748, 1.799664, 2.476902",\
+ "1.628551, 1.804755, 1.995558, 2.342230, 3.031935");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.149901, 0.149901, 0.154272, 0.175587, 0.224039",\
+ "0.237266, 0.237266, 0.240202, 0.254165, 0.285843",\
+ "0.399712, 0.400490, 0.400737, 0.406993, 0.422155",\
+ "0.873536, 0.873536, 0.873536, 0.874623, 0.877289",\
+ "2.137324, 2.139116, 2.139203, 2.139986, 2.141907",\
+ "0.149901, 0.149901, 0.154272, 0.175587, 0.224039",\
+ "0.237266, 0.237266, 0.240202, 0.254165, 0.285843",\
+ "0.399712, 0.400490, 0.400737, 0.406993, 0.422155",\
+ "0.873536, 0.873536, 0.873536, 0.874623, 0.877289",\
+ "2.137324, 2.139116, 2.139203, 2.139986, 2.141907",\
+ "0.149901, 0.149901, 0.154272, 0.175587, 0.224039",\
+ "0.237266, 0.237266, 0.240202, 0.254165, 0.285843",\
+ "0.399717, 0.400490, 0.400737, 0.406993, 0.422155",\
+ "0.873536, 0.873536, 0.873536, 0.874623, 0.877289",\
+ "2.137336, 2.139116, 2.139203, 2.139986, 2.141907",\
+ "0.149901, 0.149901, 0.154282, 0.175646, 0.224156",\
+ "0.237266, 0.237266, 0.240209, 0.254204, 0.285920",\
+ "0.399727, 0.400493, 0.400738, 0.407012, 0.422192",\
+ "0.873536, 0.873536, 0.873536, 0.874626, 0.877296",\
+ "2.137358, 2.139123, 2.139203, 2.139988, 2.141912",\
+ "0.149901, 0.149901, 0.154284, 0.175697, 0.224297",\
+ "0.237266, 0.237266, 0.240210, 0.254237, 0.286012",\
+ "0.399816, 0.400514, 0.400738, 0.407027, 0.422236",\
+ "0.873536, 0.873536, 0.873536, 0.874629, 0.877303",\
+ "2.137563, 2.139170, 2.139203, 2.139990, 2.141917");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.146813, 0.421543, 0.619073, 0.936497, 1.550523",\
+ "0.182955, 0.455962, 0.653305, 0.972716, 1.591584",\
+ "0.237642, 0.505732, 0.702816, 1.023104, 1.644353",\
+ "0.371091, 0.634162, 0.830900, 1.151008, 1.772115",\
+ "0.705966, 0.969914, 1.166368, 1.485322, 2.103856",\
+ "0.235216, 0.509090, 0.706354, 1.023802, 1.637876",\
+ "0.271333, 0.543280, 0.740586, 1.060021, 1.678937",\
+ "0.325990, 0.593050, 0.790097, 1.110409, 1.731706",\
+ "0.459423, 0.721480, 0.918180, 1.238313, 1.859468",\
+ "0.794276, 1.057232, 1.253649, 1.572627, 2.191210",\
+ "0.324565, 0.589422, 0.786381, 1.103830, 1.717908",\
+ "0.360611, 0.623613, 0.820613, 1.140050, 1.758969",\
+ "0.415179, 0.673383, 0.870124, 1.190438, 1.811738",\
+ "0.548565, 0.801813, 0.998207, 1.318341, 1.939500",\
+ "0.883356, 1.137565, 1.333676, 1.652655, 2.271241",\
+ "0.388205, 0.647259, 0.844120, 1.161325, 1.775052",\
+ "0.424183, 0.681450, 0.878352, 1.197550, 1.816125",\
+ "0.478670, 0.731220, 0.927863, 1.247941, 1.868900",\
+ "0.612012, 0.859650, 1.055945, 1.375844, 1.996662",\
+ "0.946745, 1.195402, 1.391413, 1.710155, 2.328397",\
+ "0.724572, 0.952620, 1.147783, 1.464552, 2.077430",\
+ "0.760125, 0.986813, 1.182015, 1.500782, 2.118517",\
+ "0.814091, 1.036585, 1.231526, 1.551176, 2.171298",\
+ "0.947154, 1.165011, 1.359608, 1.679079, 2.299060",\
+ "1.281518, 1.500770, 1.695075, 2.013387, 2.630787");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011");
+ values ( "0.071550, 0.074340, 0.076398, 0.092998, 0.129684",\
+ "0.104996, 0.104996, 0.106760, 0.117958, 0.143880",\
+ "0.191043, 0.191210, 0.191730, 0.197481, 0.211138",\
+ "0.431517, 0.431517, 0.431517, 0.433284, 0.437618",\
+ "1.064302, 1.065326, 1.065376, 1.065376, 1.065376",\
+ "0.071556, 0.071791, 0.076398, 0.092998, 0.129684",\
+ "0.104996, 0.104996, 0.106760, 0.117958, 0.143880",\
+ "0.191048, 0.191210, 0.191730, 0.197481, 0.211138",\
+ "0.431517, 0.431517, 0.431517, 0.433284, 0.437618",\
+ "1.064330, 1.065326, 1.065376, 1.065376, 1.065376",\
+ "0.071575, 0.071791, 0.076398, 0.092998, 0.129684",\
+ "0.104996, 0.104996, 0.106760, 0.117958, 0.143880",\
+ "0.191061, 0.191210, 0.191730, 0.197481, 0.211138",\
+ "0.431517, 0.431517, 0.431517, 0.433284, 0.437618",\
+ "1.064411, 1.065326, 1.065376, 1.065376, 1.065376",\
+ "0.071593, 0.071792, 0.076409, 0.093042, 0.129773",\
+ "0.104996, 0.104996, 0.106764, 0.117989, 0.143943",\
+ "0.191073, 0.191211, 0.191731, 0.197497, 0.211171",\
+ "0.431517, 0.431517, 0.431517, 0.433289, 0.437628",\
+ "1.064486, 1.065330, 1.065376, 1.065376, 1.065376",\
+ "0.071706, 0.071799, 0.076411, 0.093080, 0.129880",\
+ "0.104996, 0.104996, 0.106764, 0.118016, 0.144018",\
+ "0.191152, 0.191215, 0.191732, 0.197512, 0.211211",\
+ "0.431517, 0.431517, 0.431517, 0.433294, 0.437641",\
+ "1.064965, 1.065357, 1.065376, 1.065376, 1.065376");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[24]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.170538, 0.344791, 0.534395, 0.834671, 1.413373",\
+ "0.220382, 0.410357, 0.608123, 0.926913, 1.543930",\
+ "0.296720, 0.496999, 0.695612, 1.028145, 1.678018",\
+ "0.503635, 0.714092, 0.910615, 1.258034, 1.946089",\
+ "1.056522, 1.269056, 1.463869, 1.813497, 2.508420",\
+ "0.258747, 0.432108, 0.621676, 0.921976, 1.500726",\
+ "0.308608, 0.497675, 0.695404, 1.014218, 1.631283",\
+ "0.384956, 0.584317, 0.782893, 1.115450, 1.765372",\
+ "0.591859, 0.801410, 0.997896, 1.345339, 2.033442",\
+ "1.144699, 1.356374, 1.551150, 1.900803, 2.595773",\
+ "0.340253, 0.512437, 0.701702, 1.002005, 1.580758",\
+ "0.397921, 0.578003, 0.775430, 1.094246, 1.711315",\
+ "0.474302, 0.664646, 0.862920, 1.195478, 1.845403",\
+ "0.681166, 0.881738, 1.077923, 1.425368, 2.113474",\
+ "1.233862, 1.436702, 1.631177, 1.980831, 2.675804",\
+ "0.397891, 0.570245, 0.759425, 1.059457, 1.637819",\
+ "0.461736, 0.635815, 0.833172, 1.151745, 1.768469",\
+ "0.538147, 0.722460, 0.920664, 1.253017, 1.902637",\
+ "0.744974, 0.939560, 1.135661, 1.482953, 2.170799",\
+ "1.297532, 1.494526, 1.688912, 2.038425, 2.733147",\
+ "0.700600, 0.875392, 1.063084, 1.362647, 1.940096",\
+ "0.765324, 0.940987, 1.136834, 1.454975, 2.070858",\
+ "0.851439, 1.027647, 1.224326, 1.556282, 2.205122",\
+ "1.066882, 1.244797, 1.439323, 1.786257, 2.473396",\
+ "1.621173, 1.799784, 1.992573, 2.341736, 3.035763");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.138974, 0.138974, 0.138974, 0.148689, 0.172413",\
+ "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\
+ "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\
+ "0.872442, 0.873368, 0.873689, 0.874395, 0.875876",\
+ "2.139574, 2.140537, 2.140572, 2.140672, 2.140918",\
+ "0.138974, 0.138974, 0.138974, 0.148689, 0.172413",\
+ "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\
+ "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\
+ "0.872465, 0.873368, 0.873689, 0.874395, 0.875876",\
+ "2.139599, 2.140537, 2.140572, 2.140672, 2.140918",\
+ "0.138974, 0.138974, 0.138974, 0.148689, 0.172413",\
+ "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\
+ "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\
+ "0.872537, 0.873368, 0.873689, 0.874395, 0.875876",\
+ "2.139673, 2.140537, 2.140572, 2.140672, 2.140918",\
+ "0.138974, 0.138974, 0.138974, 0.148718, 0.172471",\
+ "0.231167, 0.231167, 0.231167, 0.238044, 0.254807",\
+ "0.397287, 0.397287, 0.397287, 0.400384, 0.407935",\
+ "0.872606, 0.873372, 0.873689, 0.874396, 0.875879",\
+ "2.139745, 2.140541, 2.140572, 2.140673, 2.140918",\
+ "0.138974, 0.138974, 0.138974, 0.148743, 0.172540",\
+ "0.231167, 0.231167, 0.231167, 0.238062, 0.254856",\
+ "0.397287, 0.397287, 0.397287, 0.400392, 0.407957",\
+ "0.872562, 0.873396, 0.873689, 0.874398, 0.875884",\
+ "2.139699, 2.140566, 2.140572, 2.140673, 2.140919");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.114471, 0.367066, 0.558465, 0.861628, 1.446142",\
+ "0.150570, 0.396419, 0.587661, 0.892759, 1.482112",\
+ "0.204674, 0.442227, 0.633125, 0.939020, 1.530584",\
+ "0.336064, 0.565592, 0.755956, 1.061790, 1.653617",\
+ "0.673293, 0.896815, 1.086094, 1.390763, 1.980611",\
+ "0.202627, 0.454384, 0.645746, 0.948933, 1.533495",\
+ "0.238831, 0.483737, 0.674942, 0.980064, 1.569466",\
+ "0.292913, 0.529545, 0.720406, 1.026325, 1.617937",\
+ "0.424271, 0.652910, 0.843237, 1.149095, 1.740970",\
+ "0.761475, 0.984133, 1.173375, 1.478068, 2.067965",\
+ "0.291726, 0.534712, 0.725773, 1.028962, 1.613527",\
+ "0.328254, 0.564066, 0.754969, 1.060092, 1.649498",\
+ "0.382266, 0.609874, 0.800433, 1.106354, 1.697969",\
+ "0.513528, 0.733239, 0.923264, 1.229123, 1.821002",\
+ "0.850652, 1.064461, 1.253402, 1.558096, 2.147996",\
+ "0.355336, 0.592555, 0.783499, 1.086421, 1.670602",\
+ "0.392174, 0.621907, 0.812695, 1.117557, 1.706585",\
+ "0.446119, 0.667711, 0.858158, 1.163821, 1.755061",\
+ "0.577288, 0.791071, 0.980987, 1.286592, 1.878095",\
+ "0.914335, 1.122288, 1.311124, 1.615562, 2.205085",\
+ "0.691472, 0.897945, 1.087159, 1.389617, 1.972896",\
+ "0.730295, 0.927282, 1.116354, 1.420759, 2.008893",\
+ "0.783810, 0.973061, 1.161817, 1.467025, 2.057376",\
+ "0.914389, 1.096386, 1.284647, 1.589795, 2.180410",\
+ "1.248447, 1.427560, 1.614782, 1.918764, 2.507394");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.055015, 0.067356, 0.073976, 0.088784, 0.119708",\
+ "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\
+ "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\
+ "0.432838, 0.433934, 0.434139, 0.435063, 0.437176",\
+ "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\
+ "0.055327, 0.067356, 0.073976, 0.088784, 0.119708",\
+ "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\
+ "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\
+ "0.432865, 0.433934, 0.434139, 0.435063, 0.437176",\
+ "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\
+ "0.056284, 0.067356, 0.073976, 0.088784, 0.119708",\
+ "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\
+ "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\
+ "0.432950, 0.433934, 0.434139, 0.435063, 0.437176",\
+ "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\
+ "0.057202, 0.067402, 0.073991, 0.088822, 0.119782",\
+ "0.104870, 0.104870, 0.106673, 0.116322, 0.138328",\
+ "0.190674, 0.190674, 0.191256, 0.196143, 0.207567",\
+ "0.433032, 0.433938, 0.434140, 0.435065, 0.437181",\
+ "1.062723, 1.062723, 1.063224, 1.064132, 1.065926",\
+ "0.063072, 0.067724, 0.073993, 0.088854, 0.119873",\
+ "0.104870, 0.104870, 0.106674, 0.116345, 0.138392",\
+ "0.190674, 0.190674, 0.191256, 0.196155, 0.207600",\
+ "0.433553, 0.433966, 0.434140, 0.435067, 0.437187",\
+ "1.062723, 1.062723, 1.063224, 1.064134, 1.065932");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2340*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[27]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.337877, 0.567396, 0.751267, 1.044506, 1.611115",\
+ "0.385816, 0.615335, 0.799206, 1.092445, 1.659054",\
+ "0.487851, 0.717370, 0.901241, 1.194480, 1.761089",\
+ "0.725267, 0.954786, 1.138657, 1.431895, 1.998505",\
+ "1.296926, 1.526444, 1.710315, 2.003554, 2.570163",\
+ "0.426171, 0.654713, 0.838548, 1.131811, 1.698468",\
+ "0.474110, 0.702653, 0.886487, 1.179750, 1.746408",\
+ "0.576145, 0.804687, 0.988522, 1.281785, 1.848443",\
+ "0.813561, 1.042103, 1.225938, 1.519201, 2.085858",\
+ "1.385220, 1.613762, 1.797596, 2.090859, 2.657517",\
+ "0.515866, 0.735041, 0.918575, 1.211839, 1.778500",\
+ "0.563806, 0.782980, 0.966514, 1.259778, 1.826439",\
+ "0.665841, 0.885015, 1.068549, 1.361813, 1.928474",\
+ "0.903256, 1.122430, 1.305965, 1.599229, 2.165890",\
+ "1.474915, 1.694089, 1.877623, 2.170888, 2.737548",\
+ "0.580118, 0.792869, 0.976284, 1.269277, 1.835533",\
+ "0.628057, 0.840809, 1.024223, 1.317216, 1.883472",\
+ "0.730092, 0.942843, 1.126258, 1.419251, 1.985507",\
+ "0.967507, 1.180259, 1.363673, 1.656667, 2.222923",\
+ "1.539166, 1.751918, 1.935332, 2.228325, 2.794581",\
+ "0.919018, 1.098154, 1.279940, 1.572454, 2.137775",\
+ "0.966958, 1.146093, 1.327879, 1.620393, 2.185715",\
+ "1.068992, 1.248128, 1.429914, 1.722428, 2.287750",\
+ "1.306408, 1.485543, 1.667330, 1.959844, 2.525165",\
+ "1.878067, 2.057202, 2.238988, 2.531503, 3.096824");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.372253, 0.601881, 0.784032, 1.076595, 1.643049",\
+ "0.397511, 0.627029, 0.810901, 1.104139, 1.670748",\
+ "0.438896, 0.668415, 0.852286, 1.145524, 1.712134",\
+ "0.561215, 0.790734, 0.974605, 1.267843, 1.834453",\
+ "0.893448, 1.122967, 1.306838, 1.600076, 2.166686",\
+ "0.460528, 0.689198, 0.871313, 1.163900, 1.730402",\
+ "0.485805, 0.714347, 0.898181, 1.191444, 1.758102",\
+ "0.527190, 0.755732, 0.939567, 1.232830, 1.799487",\
+ "0.649509, 0.878051, 1.061886, 1.355149, 1.921806",\
+ "0.981742, 1.210284, 1.394119, 1.687381, 2.254039",\
+ "0.550165, 0.769525, 0.951340, 1.243928, 1.810434",\
+ "0.575500, 0.794674, 0.978208, 1.271473, 1.838133",\
+ "0.616885, 0.836059, 1.019594, 1.312858, 1.879519",\
+ "0.739204, 0.958378, 1.141913, 1.435177, 2.001838",\
+ "1.071437, 1.290611, 1.474146, 1.767410, 2.334071",\
+ "0.614360, 0.827361, 1.009044, 1.301366, 1.867467",\
+ "0.639751, 0.852503, 1.035917, 1.328910, 1.895166",\
+ "0.681136, 0.893888, 1.077302, 1.370296, 1.936552",\
+ "0.803456, 1.016207, 1.199622, 1.492615, 2.058871",\
+ "1.135688, 1.348440, 1.531854, 1.824847, 2.391104",\
+ "0.951814, 1.132696, 1.312700, 1.604543, 2.169709",\
+ "0.978652, 1.157787, 1.339573, 1.632088, 2.197409",\
+ "1.020037, 1.199172, 1.380959, 1.673473, 2.238794",\
+ "1.142356, 1.321491, 1.503278, 1.795792, 2.361114",\
+ "1.474589, 1.653724, 1.835510, 2.128025, 2.693346");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2710*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[31]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.323167, 0.539803, 0.719494, 1.009588, 1.571964",\
+ "0.371106, 0.587742, 0.767433, 1.057527, 1.619903",\
+ "0.473141, 0.689777, 0.869468, 1.159562, 1.721938",\
+ "0.710557, 0.927193, 1.106884, 1.396978, 1.959354",\
+ "1.282216, 1.498852, 1.678543, 1.968637, 2.531013",\
+ "0.411457, 0.627121, 0.806775, 1.096893, 1.659318",\
+ "0.459396, 0.675060, 0.854714, 1.144832, 1.707257",\
+ "0.561431, 0.777095, 0.956749, 1.246867, 1.809292",\
+ "0.798847, 1.014511, 1.194165, 1.484283, 2.046708",\
+ "1.370506, 1.586170, 1.765824, 2.055942, 2.618367",\
+ "0.500498, 0.707454, 0.886802, 1.176922, 1.739349",\
+ "0.548437, 0.755393, 0.934741, 1.224860, 1.787288",\
+ "0.650472, 0.857428, 1.036776, 1.326895, 1.889323",\
+ "0.887888, 1.094844, 1.274192, 1.564311, 2.126739",\
+ "1.459547, 1.666503, 1.845851, 2.135971, 2.698398",\
+ "0.563859, 0.765284, 0.944499, 1.234353, 1.796369",\
+ "0.611798, 0.813223, 0.992438, 1.282292, 1.844308",\
+ "0.713833, 0.915258, 1.094473, 1.384327, 1.946343",\
+ "0.951249, 1.152674, 1.331889, 1.621743, 2.183759",\
+ "1.522908, 1.724333, 1.903548, 2.193402, 2.755418",\
+ "0.888835, 1.070603, 1.248155, 1.537527, 2.098596",\
+ "0.936774, 1.118542, 1.296094, 1.585466, 2.146535",\
+ "1.038809, 1.220577, 1.398129, 1.687501, 2.248570",\
+ "1.276225, 1.457993, 1.635545, 1.924917, 2.485986",\
+ "1.847884, 2.029652, 2.207204, 2.496576, 3.057645");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.360736, 0.577372, 0.757063, 1.047157, 1.609533",\
+ "0.382801, 0.599437, 0.779128, 1.069222, 1.631598",\
+ "0.424186, 0.640822, 0.820514, 1.110608, 1.672984",\
+ "0.546505, 0.763141, 0.942833, 1.232926, 1.795303",\
+ "0.878738, 1.095374, 1.275065, 1.565159, 2.127535",\
+ "0.449026, 0.664690, 0.844344, 1.134462, 1.696887",\
+ "0.471091, 0.686755, 0.866409, 1.156527, 1.718952",\
+ "0.512477, 0.728141, 0.907795, 1.197913, 1.760337",\
+ "0.634796, 0.850460, 1.030114, 1.320232, 1.882656",\
+ "0.967028, 1.182692, 1.362346, 1.652464, 2.214889",\
+ "0.538067, 0.745023, 0.924371, 1.214491, 1.776918",\
+ "0.560132, 0.767088, 0.946436, 1.236556, 1.798984",\
+ "0.601517, 0.808473, 0.987821, 1.277941, 1.840369",\
+ "0.723837, 0.930792, 1.110141, 1.400260, 1.962688",\
+ "1.056069, 1.263025, 1.442373, 1.732492, 2.294920",\
+ "0.601428, 0.802853, 0.982068, 1.271922, 1.833938",\
+ "0.623493, 0.824919, 1.004133, 1.293988, 1.856004",\
+ "0.664878, 0.866304, 1.045519, 1.335373, 1.897389",\
+ "0.787198, 0.988623, 1.167838, 1.457692, 2.019708",\
+ "1.119430, 1.320855, 1.500070, 1.789924, 2.351940",\
+ "0.926404, 1.108172, 1.285724, 1.575096, 2.136165",\
+ "0.948469, 1.130237, 1.307790, 1.597161, 2.158231",\
+ "0.989855, 1.171622, 1.349175, 1.638546, 2.199616",\
+ "1.112174, 1.293941, 1.471494, 1.760865, 2.321935",\
+ "1.444406, 1.626174, 1.803726, 2.093098, 2.654167");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2399*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[32]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.393798, 0.608317, 0.787191, 1.076625, 1.638145",\
+ "0.443659, 0.658178, 0.837052, 1.126486, 1.688006",\
+ "0.545527, 0.760046, 0.938920, 1.228354, 1.789874",\
+ "0.783388, 0.997908, 1.176781, 1.466215, 2.027735",\
+ "1.355708, 1.570228, 1.749101, 2.038536, 2.600056",\
+ "0.482072, 0.695635, 0.874472, 1.163930, 1.725499",\
+ "0.531933, 0.745496, 0.924333, 1.213791, 1.775360",\
+ "0.633801, 0.847364, 1.026201, 1.315659, 1.877228",\
+ "0.871662, 1.085225, 1.264062, 1.553521, 2.115089",\
+ "1.443982, 1.657546, 1.836382, 2.125841, 2.687409",\
+ "0.571616, 0.775963, 0.954499, 1.243959, 1.805530",\
+ "0.621477, 0.825824, 1.004360, 1.293820, 1.855391",\
+ "0.723345, 0.927692, 1.106228, 1.395688, 1.957259",\
+ "0.961206, 1.165553, 1.344089, 1.633549, 2.195120",\
+ "1.533526, 1.737874, 1.916409, 2.205869, 2.767441",\
+ "0.635684, 0.833793, 1.012195, 1.301390, 1.862550",\
+ "0.685545, 0.883654, 1.062056, 1.351251, 1.912411",\
+ "0.787413, 0.985522, 1.163924, 1.453119, 2.014279",\
+ "1.025275, 1.223383, 1.401785, 1.690980, 2.252141",\
+ "1.597595, 1.795703, 1.974106, 2.263301, 2.824461",\
+ "0.959458, 1.139086, 1.315850, 1.604562, 2.164778",\
+ "1.009318, 1.188946, 1.365711, 1.654423, 2.214639",\
+ "1.111187, 1.290814, 1.467579, 1.756291, 2.316507",\
+ "1.349048, 1.528676, 1.705440, 1.994153, 2.554368",\
+ "1.921368, 2.100996, 2.277760, 2.566473, 3.126688");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.434527, 0.649046, 0.827920, 1.117354, 1.678874",\
+ "0.456877, 0.671396, 0.850269, 1.139704, 1.701224",\
+ "0.498240, 0.712759, 0.891633, 1.181067, 1.742587",\
+ "0.620276, 0.834795, 1.013668, 1.303103, 1.864623",\
+ "0.951889, 1.166408, 1.345281, 1.634716, 2.196236",\
+ "0.522801, 0.736364, 0.915201, 1.204659, 1.766227",\
+ "0.545151, 0.758714, 0.937550, 1.227009, 1.788577",\
+ "0.586514, 0.800077, 0.978914, 1.268372, 1.829941",\
+ "0.708550, 0.922113, 1.100950, 1.390408, 1.951976",\
+ "1.040162, 1.253726, 1.432562, 1.722021, 2.283589",\
+ "0.612344, 0.816692, 0.995228, 1.284688, 1.846259",\
+ "0.634694, 0.839042, 1.017577, 1.307038, 1.868609",\
+ "0.676058, 0.880405, 1.058941, 1.348401, 1.909972",\
+ "0.798093, 1.002441, 1.180976, 1.470437, 2.032008",\
+ "1.129706, 1.334054, 1.512589, 1.802049, 2.363621",\
+ "0.676413, 0.874521, 1.052924, 1.342119, 1.903279",\
+ "0.698763, 0.896871, 1.075274, 1.364469, 1.925629",\
+ "0.740127, 0.938235, 1.116637, 1.405832, 1.966993",\
+ "0.862162, 1.060270, 1.238673, 1.527868, 2.089028",\
+ "1.193775, 1.391883, 1.570286, 1.859481, 2.420641",\
+ "1.000186, 1.179814, 1.356578, 1.645291, 2.205507",\
+ "1.022536, 1.202164, 1.378928, 1.667641, 2.227856",\
+ "1.063900, 1.243527, 1.420292, 1.709004, 2.269220",\
+ "1.185935, 1.365563, 1.542327, 1.831040, 2.391255",\
+ "1.517548, 1.697176, 1.873940, 2.162653, 2.722868");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011");
+ values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2477*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[34]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.454939, 0.667221, 0.852612, 1.143493, 1.702667",\
+ "0.502878, 0.715160, 0.900551, 1.191432, 1.750605",\
+ "0.604913, 0.817195, 1.002586, 1.293467, 1.852640",\
+ "0.842329, 1.054611, 1.240002, 1.530883, 2.090056",\
+ "1.413988, 1.626270, 1.811661, 2.102542, 2.661716",\
+ "0.543302, 0.754540, 0.939893, 1.230798, 1.790020",\
+ "0.591241, 0.802479, 0.987832, 1.278737, 1.837959",\
+ "0.693276, 0.904514, 1.089867, 1.380772, 1.939994",\
+ "0.930692, 1.141930, 1.327283, 1.618188, 2.177410",\
+ "1.502351, 1.713589, 1.898942, 2.189847, 2.749069",\
+ "0.632361, 0.834874, 1.019920, 1.310827, 1.870051",\
+ "0.680300, 0.882813, 1.067859, 1.358765, 1.917990",\
+ "0.782335, 0.984848, 1.169894, 1.460800, 2.020025",\
+ "1.019751, 1.222264, 1.407310, 1.698216, 2.257441",\
+ "1.591410, 1.793923, 1.978969, 2.269875, 2.829100",\
+ "0.695656, 0.892702, 1.077631, 1.368254, 1.927063",\
+ "0.743595, 0.940641, 1.125570, 1.416193, 1.975002",\
+ "0.845629, 1.042676, 1.227605, 1.518228, 2.077037",\
+ "1.083045, 1.280092, 1.465021, 1.755644, 2.314453",\
+ "1.654704, 1.851751, 2.036680, 2.327303, 2.886112",\
+ "1.016280, 1.198005, 1.381290, 1.671425, 2.229280",\
+ "1.064219, 1.245944, 1.429229, 1.719364, 2.277219",\
+ "1.166254, 1.347979, 1.531264, 1.821398, 2.379254",\
+ "1.403669, 1.585395, 1.768679, 2.058815, 2.616670",\
+ "1.975328, 2.157054, 2.340338, 2.630474, 3.188329");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.492508, 0.704790, 0.890181, 1.181062, 1.740236",\
+ "0.514573, 0.726856, 0.912247, 1.203127, 1.762301",\
+ "0.555959, 0.768241, 0.953632, 1.244512, 1.803686",\
+ "0.678278, 0.890560, 1.075951, 1.366831, 1.926005",\
+ "1.010510, 1.222792, 1.408183, 1.699064, 2.258237",\
+ "0.580871, 0.792109, 0.977462, 1.268367, 1.827589",\
+ "0.602936, 0.814174, 0.999527, 1.290432, 1.849654",\
+ "0.644321, 0.855559, 1.040913, 1.331817, 1.891039",\
+ "0.766640, 0.977878, 1.163232, 1.454136, 2.013358",\
+ "1.098873, 1.310111, 1.495464, 1.786369, 2.345591",\
+ "0.669930, 0.872443, 1.057489, 1.348396, 1.907620",\
+ "0.691995, 0.894508, 1.079554, 1.370461, 1.929686",\
+ "0.733381, 0.935894, 1.120940, 1.411846, 1.971071",\
+ "0.855700, 1.058213, 1.243259, 1.534165, 2.093390",\
+ "1.187932, 1.390445, 1.575491, 1.866397, 2.425622",\
+ "0.733225, 0.930271, 1.115200, 1.405823, 1.964632",\
+ "0.755290, 0.952336, 1.137265, 1.427888, 1.986697",\
+ "0.796675, 0.993721, 1.178650, 1.469274, 2.028083",\
+ "0.918994, 1.116040, 1.300969, 1.591593, 2.150402",\
+ "1.251227, 1.448273, 1.633202, 1.923825, 2.482634",\
+ "1.053849, 1.235574, 1.418859, 1.708994, 2.266849",\
+ "1.075914, 1.257639, 1.440924, 1.731059, 2.288914",\
+ "1.117299, 1.299025, 1.482309, 1.772444, 2.330299",\
+ "1.239618, 1.421344, 1.604628, 1.894763, 2.452619",\
+ "1.571851, 1.753576, 1.936861, 2.226995, 2.784851");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2561*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[35]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.429494, 0.640486, 0.817408, 1.101335, 1.650898",\
+ "0.477433, 0.688425, 0.865347, 1.149274, 1.698837",\
+ "0.579467, 0.790460, 0.967382, 1.251309, 1.800872",\
+ "0.816883, 1.027876, 1.204798, 1.488725, 2.038288",\
+ "1.388543, 1.599535, 1.776457, 2.060384, 2.609947",\
+ "0.517769, 0.727804, 0.904689, 1.188640, 1.738251",\
+ "0.565708, 0.775743, 0.952628, 1.236579, 1.786190",\
+ "0.667743, 0.877778, 1.054663, 1.338614, 1.888225",\
+ "0.905159, 1.115194, 1.292079, 1.576030, 2.125641",\
+ "1.476818, 1.686853, 1.863738, 2.147689, 2.697300",\
+ "0.606719, 0.808137, 0.984716, 1.268669, 1.818283",\
+ "0.654658, 0.856076, 1.032655, 1.316607, 1.866222",\
+ "0.756693, 0.958111, 1.134690, 1.418642, 1.968257",\
+ "0.994109, 1.195527, 1.372106, 1.656058, 2.205673",\
+ "1.565768, 1.767186, 1.943765, 2.227717, 2.777332",\
+ "0.669974, 0.865958, 1.042407, 1.326085, 1.875272",\
+ "0.717913, 0.913897, 1.090346, 1.374024, 1.923211",\
+ "0.819948, 1.015932, 1.192381, 1.476059, 2.025246",\
+ "1.057364, 1.253348, 1.429797, 1.713475, 2.262662",\
+ "1.629023, 1.825007, 2.001456, 2.285134, 2.834321",\
+ "0.991556, 1.171211, 1.346062, 1.629245, 2.177461",\
+ "1.039495, 1.219150, 1.394001, 1.677184, 2.225400",\
+ "1.141530, 1.321185, 1.496036, 1.779219, 2.327435",\
+ "1.378946, 1.558601, 1.733452, 2.016635, 2.564851",\
+ "1.950605, 2.130260, 2.305111, 2.588294, 3.136510");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\
+ "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.467063, 0.678055, 0.854977, 1.138904, 1.688467",\
+ "0.489128, 0.700120, 0.877042, 1.160969, 1.710532",\
+ "0.530513, 0.741505, 0.918428, 1.202354, 1.751917",\
+ "0.652832, 0.863824, 1.040747, 1.324673, 1.874236",\
+ "0.985064, 1.196057, 1.372979, 1.656906, 2.206469",\
+ "0.555338, 0.765373, 0.942258, 1.226209, 1.775820",\
+ "0.577403, 0.787438, 0.964323, 1.248274, 1.797885",\
+ "0.618789, 0.828824, 1.005709, 1.289660, 1.839271",\
+ "0.741108, 0.951143, 1.128028, 1.411978, 1.961590",\
+ "1.073340, 1.283375, 1.460260, 1.744211, 2.293822",\
+ "0.644288, 0.845706, 1.022285, 1.306238, 1.855852",\
+ "0.666353, 0.867771, 1.044350, 1.328303, 1.877917",\
+ "0.707738, 0.909157, 1.085736, 1.369688, 1.919302",\
+ "0.830057, 1.031476, 1.208055, 1.492007, 2.041621",\
+ "1.162290, 1.363708, 1.540287, 1.824239, 2.373854",\
+ "0.707543, 0.903527, 1.079976, 1.363654, 1.912841",\
+ "0.729608, 0.925592, 1.102041, 1.385719, 1.934906",\
+ "0.770994, 0.966978, 1.143427, 1.427104, 1.976291",\
+ "0.893313, 1.089297, 1.265746, 1.549423, 2.098610",\
+ "1.225545, 1.421529, 1.597978, 1.881656, 2.430843",\
+ "1.029125, 1.208780, 1.383631, 1.666814, 2.215030",\
+ "1.051190, 1.230845, 1.405696, 1.688879, 2.237095",\
+ "1.092575, 1.272231, 1.447082, 1.730264, 2.278481",\
+ "1.214894, 1.394550, 1.569401, 1.852583, 2.400800",\
+ "1.547127, 1.726782, 1.901633, 2.184816, 2.733032");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\
+ "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\
+ "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065030, 1.065030, 1.065030, 1.065030, 1.065030");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2624*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[36]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.495805, 0.717554, 0.895492, 1.184407, 1.745240",\
+ "0.543744, 0.765493, 0.943432, 1.232346, 1.793180",\
+ "0.645779, 0.867528, 1.045467, 1.334381, 1.895214",\
+ "0.883194, 1.104943, 1.282882, 1.571797, 2.132630",\
+ "1.454853, 1.676602, 1.854541, 2.143455, 2.704289",\
+ "0.584213, 0.804872, 0.982773, 1.271712, 1.832594",\
+ "0.632152, 0.852811, 1.030712, 1.319651, 1.880533",\
+ "0.734187, 0.954846, 1.132747, 1.421686, 1.982568",\
+ "0.971603, 1.192262, 1.370163, 1.659102, 2.219983",\
+ "1.543261, 1.763920, 1.941822, 2.230760, 2.791642",\
+ "0.673303, 0.885207, 1.062800, 1.351740, 1.912625",\
+ "0.721243, 0.933146, 1.110739, 1.399680, 1.960565",\
+ "0.823277, 1.035181, 1.212774, 1.501714, 2.062599",\
+ "1.060693, 1.272597, 1.450190, 1.739130, 2.300015",\
+ "1.632352, 1.844256, 2.021849, 2.310789, 2.871674",\
+ "0.736581, 0.943024, 1.120493, 1.409170, 1.969641",\
+ "0.784520, 0.990963, 1.168432, 1.457109, 2.017580",\
+ "0.886555, 1.092998, 1.270467, 1.559144, 2.119615",\
+ "1.123971, 1.330414, 1.507883, 1.796560, 2.357030",\
+ "1.695630, 1.902072, 2.079542, 2.368218, 2.928689",\
+ "1.068830, 1.248253, 1.424150, 1.712342, 2.271862",\
+ "1.116770, 1.296192, 1.472089, 1.760281, 2.319801",\
+ "1.218804, 1.398227, 1.574124, 1.862316, 2.421836",\
+ "1.456220, 1.635643, 1.811539, 2.099732, 2.659251",\
+ "2.027879, 2.207301, 2.383198, 2.671391, 3.230910");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.529176, 0.750903, 0.928871, 1.217786, 1.778615",\
+ "0.555438, 0.777187, 0.955126, 1.244040, 1.804874",\
+ "0.596823, 0.818572, 0.996511, 1.285426, 1.846259",\
+ "0.719142, 0.940891, 1.118830, 1.407745, 1.968578",\
+ "1.051375, 1.273124, 1.451063, 1.739977, 2.300811",\
+ "0.617584, 0.838221, 1.016152, 1.305091, 1.865968",\
+ "0.643846, 0.864506, 1.042407, 1.331345, 1.892227",\
+ "0.685232, 0.905891, 1.083792, 1.372731, 1.933612",\
+ "0.807551, 1.028210, 1.206111, 1.495050, 2.055932",\
+ "1.139784, 1.360443, 1.538344, 1.827282, 2.388164",\
+ "0.706675, 0.918556, 1.096179, 1.385120, 1.946000",\
+ "0.732937, 0.944841, 1.122434, 1.411374, 1.972259",\
+ "0.774322, 0.986226, 1.163819, 1.452759, 2.013644",\
+ "0.896641, 1.108545, 1.286138, 1.575078, 2.135963",\
+ "1.228874, 1.440778, 1.618371, 1.907311, 2.468196",\
+ "0.769953, 0.976375, 1.153872, 1.442550, 2.003015",\
+ "0.796215, 1.002657, 1.180127, 1.468804, 2.029274",\
+ "0.837600, 1.044043, 1.221512, 1.510189, 2.070659",\
+ "0.959919, 1.166362, 1.343831, 1.632508, 2.192978",\
+ "1.292152, 1.498595, 1.676064, 1.964741, 2.525211",\
+ "1.101828, 1.281614, 1.457528, 1.745722, 2.305236",\
+ "1.128464, 1.307886, 1.483783, 1.771976, 2.331495",\
+ "1.169849, 1.349272, 1.525168, 1.813361, 2.372880",\
+ "1.292168, 1.471591, 1.647487, 1.935680, 2.495200",\
+ "1.624401, 1.803824, 1.979720, 2.267913, 2.827432");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2674*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[37]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.473135, 0.702103, 0.886918, 1.182452, 1.753613",\
+ "0.521074, 0.750043, 0.934857, 1.230392, 1.801553",\
+ "0.623109, 0.852077, 1.036892, 1.332426, 1.903588",\
+ "0.860525, 1.089493, 1.274307, 1.569842, 2.141003",\
+ "1.432183, 1.661152, 1.845966, 2.141501, 2.712662",\
+ "0.561467, 0.789422, 0.974199, 1.269758, 1.840967",\
+ "0.609406, 0.837361, 1.022138, 1.317697, 1.888906",\
+ "0.711441, 0.939396, 1.124173, 1.419731, 1.990941",\
+ "0.948857, 1.176811, 1.361588, 1.657147, 2.228357",\
+ "1.520515, 1.748470, 1.933247, 2.228806, 2.800015",\
+ "0.650685, 0.869754, 1.054226, 1.349786, 1.920998",\
+ "0.698624, 0.917693, 1.102165, 1.397725, 1.968938",\
+ "0.800659, 1.019728, 1.204200, 1.499760, 2.070972",\
+ "1.038074, 1.257143, 1.441615, 1.737176, 2.308388",\
+ "1.609733, 1.828802, 2.013274, 2.308835, 2.880047",\
+ "0.714235, 0.927578, 1.111935, 1.407229, 1.978040",\
+ "0.762174, 0.975517, 1.159875, 1.455168, 2.025979",\
+ "0.864209, 1.077552, 1.261909, 1.557203, 2.128014",\
+ "1.101624, 1.314968, 1.499325, 1.794618, 2.365430",\
+ "1.673283, 1.886627, 2.070984, 2.366277, 2.937088",\
+ "1.050030, 1.232851, 1.415593, 1.710411, 2.280293",\
+ "1.097969, 1.280791, 1.463533, 1.758350, 2.328232",\
+ "1.200004, 1.382825, 1.565567, 1.860385, 2.430267",\
+ "1.437420, 1.620241, 1.802983, 2.097801, 2.667683",\
+ "2.009078, 2.191900, 2.374642, 2.669460, 3.239341");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\
+ "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\
+ "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\
+ "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\
+ "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\
+ "2.136637, 2.136637, 2.136637, 2.136637, 2.136637");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.506490, 0.734939, 0.919745, 1.215248, 1.786338",\
+ "0.532768, 0.761737, 0.946551, 1.242086, 1.813247",\
+ "0.574154, 0.803122, 0.987937, 1.283471, 1.854632",\
+ "0.696473, 0.925441, 1.110256, 1.405790, 1.976951",\
+ "1.028706, 1.257674, 1.442488, 1.738023, 2.309184",\
+ "0.594824, 0.822257, 1.007026, 1.302553, 1.873691",\
+ "0.621100, 0.849055, 1.033832, 1.329391, 1.900600",\
+ "0.662486, 0.890440, 1.075217, 1.370776, 1.941986",\
+ "0.784805, 1.012759, 1.197537, 1.493095, 2.064305",\
+ "1.117038, 1.344992, 1.529769, 1.825328, 2.396538",\
+ "0.684045, 0.902590, 1.087053, 1.382582, 1.953723",\
+ "0.710318, 0.929387, 1.113859, 1.409419, 1.980632",\
+ "0.751704, 0.970773, 1.155244, 1.450805, 2.022017",\
+ "0.874023, 1.093092, 1.277564, 1.573124, 2.144336",\
+ "1.206255, 1.425324, 1.609796, 1.905357, 2.476569",\
+ "0.747598, 0.960414, 1.144763, 1.440024, 2.010764",\
+ "0.773868, 0.987212, 1.171569, 1.466862, 2.037673",\
+ "0.815253, 1.028597, 1.212954, 1.508247, 2.079059",\
+ "0.937573, 1.150916, 1.335273, 1.630566, 2.201378",\
+ "1.269805, 1.483149, 1.667506, 1.962799, 2.533611",\
+ "1.083412, 1.265686, 1.448421, 1.743207, 2.313017",\
+ "1.109663, 1.292485, 1.475227, 1.770045, 2.339926",\
+ "1.151049, 1.333870, 1.516612, 1.811430, 2.381312",\
+ "1.273368, 1.456189, 1.638931, 1.933749, 2.503631",\
+ "1.605601, 1.788422, 1.971164, 2.265982, 2.835864");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\
+ "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\
+ "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\
+ "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\
+ "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\
+ "1.065031, 1.065031, 1.065031, 1.065031, 1.065031");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2733*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[40]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.434817, 0.671194, 0.861423, 1.166955, 1.757904",\
+ "0.484677, 0.721055, 0.911284, 1.216816, 1.807764",\
+ "0.586545, 0.822923, 1.013152, 1.318684, 1.909632",\
+ "0.824407, 1.060784, 1.251013, 1.556545, 2.147494",\
+ "1.396727, 1.633105, 1.823334, 2.128865, 2.719814",\
+ "0.523312, 0.758513, 0.948704, 1.254260, 1.845257",\
+ "0.573172, 0.808374, 0.998565, 1.304121, 1.895118",\
+ "0.675041, 0.910242, 1.100433, 1.405989, 1.996986",\
+ "0.912902, 1.148103, 1.338294, 1.643850, 2.234847",\
+ "1.485222, 1.720423, 1.910614, 2.216170, 2.807168",\
+ "0.612642, 0.838848, 1.028731, 1.334289, 1.925289",\
+ "0.662503, 0.888709, 1.078592, 1.384149, 1.975149",\
+ "0.764371, 0.990577, 1.180460, 1.486017, 2.077017",\
+ "1.002232, 1.228438, 1.418321, 1.723879, 2.314878",\
+ "1.574552, 1.800758, 1.990641, 2.296199, 2.887199",\
+ "0.676136, 0.896683, 1.086453, 1.391755, 1.982376",\
+ "0.725997, 0.946544, 1.136314, 1.441616, 2.032237",\
+ "0.827865, 1.048412, 1.238182, 1.543484, 2.134105",\
+ "1.065726, 1.286273, 1.476043, 1.781345, 2.371966",\
+ "1.638046, 1.858593, 2.048363, 2.353665, 2.944287",\
+ "1.011585, 1.202042, 1.390114, 1.694958, 2.284685",\
+ "1.061446, 1.251903, 1.439975, 1.744819, 2.334546",\
+ "1.163314, 1.353770, 1.541843, 1.846687, 2.436414",\
+ "1.401175, 1.591632, 1.779704, 2.084548, 2.674275",\
+ "1.973496, 2.163952, 2.352024, 2.656868, 3.246596");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.475545, 0.711923, 0.902152, 1.207684, 1.798632",\
+ "0.497895, 0.734273, 0.924502, 1.230033, 1.820982",\
+ "0.539258, 0.775636, 0.965865, 1.271397, 1.862345",\
+ "0.661294, 0.897672, 1.087901, 1.393432, 1.984381",\
+ "0.992907, 1.229285, 1.419514, 1.725045, 2.315994",\
+ "0.564040, 0.799242, 0.989433, 1.294989, 1.885986",\
+ "0.586390, 0.821591, 1.011783, 1.317338, 1.908335",\
+ "0.627753, 0.862955, 1.053146, 1.358702, 1.949699",\
+ "0.749789, 0.984990, 1.175182, 1.480737, 2.071735",\
+ "1.081402, 1.316603, 1.506794, 1.812350, 2.403347",\
+ "0.653370, 0.879577, 1.069460, 1.375017, 1.966017",\
+ "0.675720, 0.901927, 1.091810, 1.397367, 1.988367",\
+ "0.717084, 0.943290, 1.133173, 1.438730, 2.029730",\
+ "0.839119, 1.065326, 1.255209, 1.560766, 2.151766",\
+ "1.170732, 1.396938, 1.586821, 1.892379, 2.483379",\
+ "0.716865, 0.937412, 1.127182, 1.432483, 2.023105",\
+ "0.739214, 0.959762, 1.149531, 1.454833, 2.045455",\
+ "0.780578, 1.001125, 1.190895, 1.496197, 2.086818",\
+ "0.902614, 1.123161, 1.312930, 1.618232, 2.208854",\
+ "1.234226, 1.454773, 1.644543, 1.949845, 2.540467",\
+ "1.052314, 1.242770, 1.430842, 1.735687, 2.325414",\
+ "1.074664, 1.265120, 1.453192, 1.758036, 2.347764",\
+ "1.116027, 1.306484, 1.494555, 1.799400, 2.389127",\
+ "1.238063, 1.428519, 1.616591, 1.921436, 2.511163",\
+ "1.569676, 1.760132, 1.948204, 2.253048, 2.842776");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2365*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[46]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.415362, 0.648627, 0.834270, 1.134053, 1.714917",\
+ "0.465223, 0.698488, 0.884131, 1.183914, 1.764778",\
+ "0.567091, 0.800357, 0.985999, 1.285782, 1.866646",\
+ "0.804953, 1.038218, 1.223860, 1.523643, 2.104508",\
+ "1.377273, 1.610538, 1.796180, 2.095963, 2.676828",\
+ "0.503768, 0.735946, 0.921550, 1.221358, 1.802271",\
+ "0.553629, 0.785807, 0.971411, 1.271219, 1.852132",\
+ "0.655497, 0.887675, 1.073280, 1.373087, 1.954000",\
+ "0.893359, 1.125536, 1.311141, 1.610948, 2.191861",\
+ "1.465679, 1.697857, 1.883461, 2.183269, 2.764181",\
+ "0.592852, 0.816281, 1.001577, 1.301386, 1.882302",\
+ "0.642713, 0.866142, 1.051438, 1.351248, 1.932163",\
+ "0.744581, 0.968010, 1.153306, 1.453116, 2.034031",\
+ "0.982442, 1.205871, 1.391168, 1.690977, 2.271893",\
+ "1.554763, 1.778192, 1.963488, 2.263297, 2.844213",\
+ "0.656124, 0.874112, 1.059288, 1.358840, 1.939366",\
+ "0.705985, 0.923973, 1.109149, 1.408702, 1.989227",\
+ "0.807853, 1.025841, 1.211017, 1.510570, 2.091095",\
+ "1.045714, 1.263703, 1.448879, 1.748431, 2.328956",\
+ "1.618035, 1.836023, 2.021199, 2.320751, 2.901277",\
+ "0.990163, 1.179444, 1.362947, 1.662033, 2.241645",\
+ "1.040024, 1.229305, 1.412809, 1.711895, 2.291506",\
+ "1.141892, 1.331173, 1.514677, 1.813762, 2.393374",\
+ "1.379753, 1.569034, 1.752538, 2.051624, 2.631236",\
+ "1.952073, 2.141355, 2.324858, 2.623944, 3.203556");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\
+ "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\
+ "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\
+ "2.137202, 2.137202, 2.137202, 2.137202, 2.137202");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.456091, 0.689356, 0.874999, 1.174782, 1.755646",\
+ "0.478441, 0.711706, 0.897348, 1.197132, 1.777996",\
+ "0.519805, 0.753070, 0.938712, 1.238495, 1.819360",\
+ "0.641840, 0.875105, 1.060748, 1.360531, 1.941395",\
+ "0.973453, 1.206718, 1.392360, 1.692143, 2.273008",\
+ "0.544497, 0.776675, 0.962279, 1.262087, 1.843000",\
+ "0.566847, 0.799025, 0.984629, 1.284437, 1.865350",\
+ "0.608211, 0.840388, 1.025993, 1.325800, 1.906713",\
+ "0.730246, 0.962424, 1.148028, 1.447836, 2.028749",\
+ "1.061859, 1.294037, 1.479641, 1.779449, 2.360361",\
+ "0.633581, 0.857010, 1.042306, 1.342116, 1.923031",\
+ "0.655931, 0.879360, 1.064656, 1.364465, 1.945381",\
+ "0.697294, 0.920723, 1.106020, 1.405829, 1.986745",\
+ "0.819330, 1.042759, 1.228055, 1.527864, 2.108780",\
+ "1.150943, 1.374372, 1.559668, 1.859477, 2.440393",\
+ "0.696853, 0.914841, 1.100017, 1.399570, 1.980095",\
+ "0.719203, 0.937191, 1.122367, 1.421919, 2.002445",\
+ "0.760566, 0.978555, 1.163731, 1.463283, 2.043808",\
+ "0.882602, 1.100590, 1.285766, 1.585318, 2.165844",\
+ "1.214215, 1.432203, 1.617379, 1.916931, 2.497457",\
+ "1.030892, 1.220173, 1.403677, 1.702762, 2.282374",\
+ "1.053242, 1.242523, 1.426026, 1.725112, 2.304724",\
+ "1.094605, 1.283886, 1.467390, 1.766476, 2.346087",\
+ "1.216641, 1.405922, 1.589425, 1.888511, 2.468123",\
+ "1.548254, 1.737535, 1.921038, 2.220124, 2.799736");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2479*/
+
+} /* end of pin tl_o[4] */
+
+pin("tl_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.034401 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[20]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.510374, 0.770025, 1.057985, 1.558099, 2.558328",\
+ "0.560483, 0.820133, 1.108094, 1.608212, 2.608449",\
+ "0.649192, 0.908842, 1.196806, 1.696939, 2.697205",\
+ "0.873358, 1.133008, 1.420973, 1.921111, 2.921387",\
+ "1.425993, 1.685643, 1.973609, 2.473750, 3.474032",\
+ "0.597787, 0.857587, 1.145651, 1.644814, 2.644262",\
+ "0.647895, 0.907696, 1.195760, 1.694927, 2.694383",\
+ "0.736605, 0.996405, 1.284473, 1.783654, 2.783139",\
+ "0.960770, 1.220570, 1.508639, 2.007826, 3.007321",\
+ "1.513405, 1.773205, 2.061275, 2.560465, 3.559966",\
+ "0.678684, 0.946606, 1.233617, 1.732436, 2.731217",\
+ "0.728793, 0.996715, 1.283726, 1.782550, 2.781338",\
+ "0.817502, 1.085424, 1.372439, 1.871277, 2.870094",\
+ "1.041668, 1.309589, 1.596606, 2.095448, 3.094276",\
+ "1.594303, 1.862224, 2.149241, 2.648087, 3.646921",\
+ "0.738268, 1.012297, 1.297762, 1.796350, 2.794726",\
+ "0.788377, 1.062406, 1.347871, 1.846463, 2.844847",\
+ "0.877086, 1.151115, 1.436584, 1.935190, 2.933603",\
+ "1.101252, 1.375280, 1.660750, 2.159362, 3.157785",\
+ "1.653887, 1.927915, 2.213386, 2.712001, 3.710430",\
+ "1.071814, 1.377311, 1.649946, 2.145828, 3.140182",\
+ "1.121922, 1.427420, 1.700056, 2.195941, 3.190303",\
+ "1.210632, 1.516129, 1.788768, 2.284668, 3.279059",\
+ "1.434798, 1.740294, 2.012935, 2.508840, 3.503241",\
+ "1.987432, 2.292929, 2.565571, 3.061479, 4.055886");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\
+ "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\
+ "2.185958, 2.185963, 2.186002, 2.186108, 2.186319",\
+ "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\
+ "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\
+ "2.185958, 2.185964, 2.186003, 2.186108, 2.186319",\
+ "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\
+ "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\
+ "2.185958, 2.185964, 2.186003, 2.186108, 2.186319",\
+ "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\
+ "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\
+ "2.185958, 2.185964, 2.186003, 2.186108, 2.186319",\
+ "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324731, 0.324734, 0.324746, 0.324779, 0.324846",\
+ "0.855415, 0.855432, 0.855507, 0.855713, 0.856129",\
+ "2.185958, 2.185966, 2.186004, 2.186108, 2.186319");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.546335, 0.805984, 1.093953, 1.594109, 2.594421",\
+ "0.568030, 0.827679, 1.115650, 1.615810, 2.616129",\
+ "0.609553, 0.869202, 1.157173, 1.657335, 2.657660",\
+ "0.742836, 1.002485, 1.290455, 1.790615, 2.790934",\
+ "1.091714, 1.351363, 1.639332, 2.139487, 3.139795",\
+ "0.633748, 0.893546, 1.181620, 1.680824, 2.680355",\
+ "0.655443, 0.915241, 1.203316, 1.702524, 2.702063",\
+ "0.696966, 0.956764, 1.244839, 1.744050, 2.743593",\
+ "0.830248, 1.090047, 1.378121, 1.877330, 2.876868",\
+ "1.179126, 1.438925, 1.726998, 2.226201, 3.225729",\
+ "0.714645, 0.982566, 1.269586, 1.768446, 2.767310",\
+ "0.736340, 1.004261, 1.291282, 1.790147, 2.789018",\
+ "0.777863, 1.045783, 1.332805, 1.831672, 2.830549",\
+ "0.911146, 1.179066, 1.466088, 1.964952, 2.963823",\
+ "1.260024, 1.527944, 1.814965, 2.313824, 3.312684",\
+ "0.774229, 1.048256, 1.333731, 1.832360, 2.830819",\
+ "0.795924, 1.069952, 1.355427, 1.854060, 2.852527",\
+ "0.837447, 1.111474, 1.396950, 1.895586, 2.894058",\
+ "0.970730, 1.244757, 1.530232, 2.028866, 3.027332",\
+ "1.319608, 1.593635, 1.879110, 2.377737, 3.376193",\
+ "1.107775, 1.413270, 1.685916, 2.181838, 3.176275",\
+ "1.129470, 1.434965, 1.707612, 2.203538, 3.197983",\
+ "1.170993, 1.476488, 1.749135, 2.245064, 3.239513",\
+ "1.304275, 1.609771, 1.882417, 2.378344, 3.372788",\
+ "1.653153, 1.958649, 2.231294, 2.727215, 3.721649");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.045624, 0.045624, 0.045626, 0.045626, 0.045626",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\
+ "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\
+ "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\
+ "0.045624, 0.045624, 0.045626, 0.045626, 0.045626",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\
+ "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\
+ "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\
+ "0.045624, 0.045624, 0.045626, 0.045626, 0.045626",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\
+ "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\
+ "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\
+ "0.045624, 0.045625, 0.045626, 0.045626, 0.045626",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\
+ "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\
+ "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\
+ "0.045624, 0.045625, 0.045626, 0.045626, 0.045626",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\
+ "0.455137, 0.455145, 0.455183, 0.455287, 0.455497",\
+ "1.170722, 1.170725, 1.170740, 1.170779, 1.170860");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2748*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[22]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.491611, 0.745113, 1.023814, 1.485459, 2.408749",\
+ "0.541720, 0.795222, 1.073923, 1.535570, 2.458864",\
+ "0.630429, 0.883931, 1.162634, 1.624290, 2.547600",\
+ "0.854595, 1.108097, 1.386801, 1.848459, 2.771775",\
+ "1.407230, 1.660732, 1.939436, 2.401096, 3.324415",\
+ "0.579020, 0.832694, 1.111357, 1.572173, 2.494682",\
+ "0.629129, 0.882803, 1.161466, 1.622284, 2.544798",\
+ "0.717839, 0.971512, 1.250178, 1.711004, 2.633534",\
+ "0.942004, 1.195678, 1.474344, 1.935173, 2.857708",\
+ "1.494639, 1.748312, 2.026979, 2.487810, 3.410349",\
+ "0.659835, 0.921740, 1.199320, 1.659795, 2.581637",\
+ "0.709944, 0.971848, 1.249429, 1.709906, 2.631753",\
+ "0.798653, 1.060558, 1.338141, 1.798626, 2.720489",\
+ "1.022819, 1.284723, 1.562307, 2.022795, 2.944664",\
+ "1.575454, 1.837358, 2.114943, 2.575432, 3.497304",\
+ "0.717415, 0.987469, 1.263459, 1.723708, 2.645146",\
+ "0.767524, 1.037577, 1.313568, 1.773819, 2.695262",\
+ "0.856233, 1.126287, 1.402279, 1.862539, 2.783998",\
+ "1.080399, 1.350452, 1.626446, 2.086708, 3.008173",\
+ "1.633034, 1.903087, 2.179081, 2.639345, 3.560813",\
+ "1.049306, 1.352971, 1.615251, 2.073024, 2.990602",\
+ "1.099415, 1.403079, 1.665360, 2.123135, 3.040718",\
+ "1.188124, 1.491788, 1.754072, 2.211854, 3.129454",\
+ "1.412290, 1.715954, 1.978238, 2.436024, 3.353629",\
+ "1.964925, 2.268589, 2.530873, 2.988661, 3.906269");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\
+ "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\
+ "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\
+ "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\
+ "2.185958, 2.185959, 2.185984, 2.186066, 2.186228",\
+ "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\
+ "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\
+ "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\
+ "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\
+ "2.185958, 2.185959, 2.185985, 2.186066, 2.186228",\
+ "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\
+ "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\
+ "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\
+ "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\
+ "2.185958, 2.185959, 2.185985, 2.186066, 2.186228",\
+ "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\
+ "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\
+ "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\
+ "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\
+ "2.185958, 2.185959, 2.185985, 2.186066, 2.186228",\
+ "0.046974, 0.046972, 0.046942, 0.046848, 0.046659",\
+ "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\
+ "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\
+ "0.855415, 0.855419, 0.855470, 0.855629, 0.855950",\
+ "2.185958, 2.185960, 2.185985, 2.186066, 2.186228");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.527572, 0.781074, 1.059780, 1.521448, 2.444784",\
+ "0.549267, 0.802769, 1.081476, 1.543146, 2.466486",\
+ "0.590790, 0.844292, 1.122999, 1.584671, 2.508013",\
+ "0.724072, 0.977574, 1.256281, 1.717952, 2.641292",\
+ "1.072951, 1.326452, 1.605159, 2.066826, 2.990160",\
+ "0.614981, 0.868654, 1.147323, 1.608162, 2.530717",\
+ "0.636677, 0.890350, 1.169019, 1.629860, 2.552420",\
+ "0.678199, 0.931872, 1.210542, 1.671385, 2.593947",\
+ "0.811482, 1.065155, 1.343825, 1.804666, 2.727225",\
+ "1.160360, 1.414033, 1.692702, 2.153540, 3.076094",\
+ "0.695796, 0.957700, 1.235286, 1.695784, 2.617672",\
+ "0.717491, 0.979395, 1.256982, 1.717482, 2.639375",\
+ "0.759014, 1.020918, 1.298506, 1.759007, 2.680902",\
+ "0.892296, 1.154201, 1.431788, 1.892287, 2.814180",\
+ "1.241175, 1.503079, 1.780665, 2.241162, 3.163049",\
+ "0.753376, 1.023429, 1.299425, 1.759697, 2.681181",\
+ "0.775071, 1.045124, 1.321121, 1.781395, 2.702884",\
+ "0.816594, 1.086647, 1.362644, 1.822920, 2.744411",\
+ "0.949877, 1.219929, 1.495926, 1.956201, 2.877689",\
+ "1.298755, 1.568808, 1.844804, 2.305075, 3.226558",\
+ "1.085267, 1.388931, 1.651218, 2.109013, 3.026638",\
+ "1.106962, 1.410626, 1.672914, 2.130711, 3.048340",\
+ "1.148485, 1.452149, 1.714437, 2.172235, 3.089867",\
+ "1.281768, 1.585431, 1.847719, 2.305516, 3.223145",\
+ "1.630646, 1.934309, 2.196596, 2.654391, 3.572014");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\
+ "0.455137, 0.455138, 0.455163, 0.455244, 0.455407",\
+ "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\
+ "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\
+ "0.455137, 0.455138, 0.455164, 0.455244, 0.455407",\
+ "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\
+ "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\
+ "0.455137, 0.455138, 0.455164, 0.455244, 0.455407",\
+ "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\
+ "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\
+ "0.455137, 0.455138, 0.455164, 0.455244, 0.455407",\
+ "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\
+ "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\
+ "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\
+ "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\
+ "0.455137, 0.455139, 0.455164, 0.455245, 0.455407",\
+ "1.170722, 1.170722, 1.170732, 1.170763, 1.170825");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2324*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[31]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.570251, 0.828412, 1.116558, 1.622590, 2.634653",\
+ "0.620360, 0.878521, 1.166668, 1.672702, 2.684771",\
+ "0.709070, 0.967232, 1.255383, 1.761428, 2.773518",\
+ "0.933236, 1.191399, 1.479551, 1.985599, 2.997696",\
+ "1.485871, 1.744034, 2.032187, 2.538238, 3.550339",\
+ "0.657660, 0.915972, 1.204241, 1.709304, 2.720587",\
+ "0.707769, 0.966081, 1.254351, 1.759417, 2.770705",\
+ "0.796479, 1.054792, 1.343066, 1.848142, 2.859451",\
+ "1.020645, 1.278959, 1.567234, 2.072314, 3.083630",\
+ "1.573280, 1.831594, 2.119870, 2.624952, 3.636273",\
+ "0.738545, 1.004968, 1.292206, 1.796926, 2.807542",\
+ "0.788654, 1.055077, 1.342316, 1.847038, 2.857660",\
+ "0.877364, 1.143789, 1.431032, 1.935764, 2.946406",\
+ "1.101530, 1.367955, 1.655199, 2.159935, 3.170585",\
+ "1.654165, 1.920590, 2.207835, 2.712574, 3.723228",\
+ "0.799029, 1.070625, 1.356352, 1.860839, 2.871051",\
+ "0.849138, 1.120734, 1.406462, 1.910952, 2.921169",\
+ "0.937848, 1.209445, 1.495178, 1.999677, 3.009915",\
+ "1.162014, 1.433611, 1.719345, 2.223849, 3.234094",\
+ "1.714649, 1.986246, 2.271981, 2.776487, 3.786737",\
+ "1.134610, 1.435289, 1.708595, 2.210337, 3.216507",\
+ "1.184719, 1.485398, 1.758705, 2.260450, 3.266625",\
+ "1.273429, 1.574110, 1.847420, 2.349176, 3.355371",\
+ "1.497595, 1.798276, 2.071588, 2.573347, 3.579550",\
+ "2.050230, 2.350911, 2.624224, 3.125986, 4.132193");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\
+ "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\
+ "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\
+ "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\
+ "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\
+ "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\
+ "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\
+ "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\
+ "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\
+ "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\
+ "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\
+ "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\
+ "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\
+ "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\
+ "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\
+ "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\
+ "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\
+ "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\
+ "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\
+ "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\
+ "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\
+ "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\
+ "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\
+ "0.855426, 0.855433, 0.855471, 0.855580, 0.855800",\
+ "2.185963, 2.185967, 2.185986, 2.186041, 2.186152");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.606214, 0.864377, 1.152534, 1.658596, 2.670718",\
+ "0.627909, 0.886073, 1.174231, 1.680295, 2.692423",\
+ "0.669432, 0.927596, 1.215755, 1.721821, 2.733952",\
+ "0.802715, 1.060879, 1.349037, 1.855101, 2.867229",\
+ "1.151593, 1.409756, 1.697913, 2.203973, 3.216093",\
+ "0.693623, 0.951938, 1.240217, 1.745310, 2.756651",\
+ "0.715318, 0.973633, 1.261914, 1.767010, 2.778357",\
+ "0.756841, 1.015157, 1.303438, 1.808535, 2.819886",\
+ "0.890124, 1.148439, 1.436720, 1.941815, 2.953162",\
+ "1.239002, 1.497316, 1.785596, 2.290687, 3.302027",\
+ "0.774507, 1.040934, 1.328183, 1.832932, 2.843606",\
+ "0.796203, 1.062629, 1.349880, 1.854631, 2.865312",\
+ "0.837726, 1.104153, 1.391404, 1.896157, 2.906841",\
+ "0.971008, 1.237435, 1.524685, 2.029437, 3.040117",\
+ "1.319886, 1.586312, 1.873561, 2.378309, 3.388982",\
+ "0.834992, 1.106590, 1.392329, 1.896845, 2.907115",\
+ "0.856687, 1.128286, 1.414026, 1.918545, 2.928821",\
+ "0.898210, 1.169809, 1.455549, 1.960070, 2.970350",\
+ "1.031493, 1.303092, 1.588831, 2.093350, 3.103626",\
+ "1.380370, 1.651969, 1.937707, 2.442222, 3.452491",\
+ "1.170573, 1.471255, 1.744571, 2.246343, 3.252572",\
+ "1.192269, 1.492951, 1.766268, 2.268043, 3.274277",\
+ "1.233792, 1.534474, 1.807792, 2.309569, 3.315806",\
+ "1.367074, 1.667757, 1.941074, 2.442849, 3.449082",\
+ "1.715952, 2.016634, 2.289950, 2.791721, 3.797947");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\
+ "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\
+ "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\
+ "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\
+ "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\
+ "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\
+ "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\
+ "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\
+ "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\
+ "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\
+ "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\
+ "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\
+ "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\
+ "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\
+ "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\
+ "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\
+ "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\
+ "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\
+ "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\
+ "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\
+ "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\
+ "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\
+ "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\
+ "0.455143, 0.455146, 0.455165, 0.455220, 0.455331",\
+ "1.170724, 1.170725, 1.170733, 1.170754, 1.170796");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2270*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[33]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.553742, 0.804842, 1.083529, 1.550229, 2.483630",\
+ "0.603850, 0.854951, 1.133639, 1.600341, 2.533747",\
+ "0.692561, 0.943663, 1.222354, 1.689065, 2.622488",\
+ "0.916727, 1.167829, 1.446522, 1.913236, 2.846664",\
+ "1.469362, 1.720464, 1.999158, 2.465874, 3.399306",\
+ "0.641147, 0.892423, 1.171086, 1.636943, 2.569564",\
+ "0.691255, 0.942532, 1.221196, 1.687055, 2.619680",\
+ "0.779966, 1.031244, 1.309911, 1.775779, 2.708421",\
+ "1.004132, 1.255410, 1.534079, 1.999949, 2.932598",\
+ "1.556767, 1.808045, 2.086715, 2.552587, 3.485240",\
+ "0.721960, 0.981448, 1.259048, 1.724564, 2.656519",\
+ "0.772069, 1.031557, 1.309159, 1.774676, 2.706635",\
+ "0.860779, 1.120269, 1.397874, 1.863400, 2.795376",\
+ "1.084945, 1.344435, 1.622041, 2.087571, 3.019553",\
+ "1.637580, 1.897070, 2.174678, 2.640208, 3.572195",\
+ "0.779579, 1.047145, 1.323188, 1.788477, 2.720028",\
+ "0.829687, 1.097255, 1.373298, 1.838589, 2.770144",\
+ "0.918398, 1.185966, 1.462013, 1.927313, 2.858885",\
+ "1.142564, 1.410133, 1.686181, 2.151483, 3.083062",\
+ "1.695199, 1.962768, 2.238817, 2.704121, 3.635704",\
+ "1.113274, 1.412343, 1.675029, 2.137809, 3.065484",\
+ "1.163383, 1.462452, 1.725139, 2.187922, 3.115601",\
+ "1.252093, 1.551164, 1.813854, 2.276645, 3.204341",\
+ "1.476259, 1.775330, 2.038022, 2.500816, 3.428518",\
+ "2.028894, 2.327965, 2.590658, 3.053454, 3.981160");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\
+ "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\
+ "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\
+ "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\
+ "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\
+ "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\
+ "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\
+ "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\
+ "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\
+ "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\
+ "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\
+ "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\
+ "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\
+ "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\
+ "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\
+ "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\
+ "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\
+ "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\
+ "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\
+ "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\
+ "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\
+ "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\
+ "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\
+ "0.855428, 0.855430, 0.855458, 0.855541, 0.855707",\
+ "2.185964, 2.185965, 2.185979, 2.186021, 2.186105");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.589705, 0.840809, 1.119505, 1.586230, 2.519679",\
+ "0.611400, 0.862504, 1.141202, 1.607929, 2.541383",\
+ "0.652923, 0.904028, 1.182726, 1.649454, 2.582911",\
+ "0.786206, 1.037310, 1.316008, 1.782735, 2.716188",\
+ "1.135083, 1.386187, 1.664884, 2.131607, 3.065055",\
+ "0.677110, 0.928390, 1.207063, 1.672943, 2.605613",\
+ "0.698805, 0.950085, 1.228760, 1.694643, 2.627316",\
+ "0.740328, 0.991609, 1.270283, 1.736168, 2.668845",\
+ "0.873611, 1.124891, 1.403565, 1.869448, 2.802122",\
+ "1.222489, 1.473768, 1.752441, 2.218321, 3.150989",\
+ "0.757923, 1.017414, 1.295025, 1.760565, 2.692568",\
+ "0.779619, 1.039110, 1.316722, 1.782264, 2.714272",\
+ "0.821142, 1.080633, 1.358246, 1.823789, 2.755800",\
+ "0.954424, 1.213916, 1.491528, 1.957069, 2.889077",\
+ "1.303302, 1.562793, 1.840404, 2.305942, 3.237944",\
+ "0.815542, 1.083112, 1.359165, 1.824477, 2.756077",\
+ "0.837237, 1.104808, 1.380862, 1.846177, 2.777781",\
+ "0.878760, 1.146331, 1.422385, 1.887702, 2.819309",\
+ "1.012043, 1.279613, 1.555667, 2.020982, 2.952586",\
+ "1.360920, 1.628491, 1.904543, 2.369855, 3.301453",\
+ "1.149238, 1.448310, 1.711006, 2.173810, 3.101533",\
+ "1.170933, 1.470006, 1.732703, 2.195509, 3.123237",\
+ "1.212456, 1.511529, 1.774227, 2.237035, 3.164765",\
+ "1.345739, 1.644811, 1.907508, 2.370315, 3.298042",\
+ "1.694616, 1.993689, 2.256384, 2.719187, 3.646909");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\
+ "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\
+ "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\
+ "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\
+ "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\
+ "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\
+ "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\
+ "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\
+ "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\
+ "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\
+ "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\
+ "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\
+ "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\
+ "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\
+ "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\
+ "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\
+ "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\
+ "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\
+ "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\
+ "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\
+ "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\
+ "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\
+ "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\
+ "0.455143, 0.455145, 0.455158, 0.455200, 0.455284",\
+ "1.170724, 1.170725, 1.170730, 1.170746, 1.170779");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2356*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[35]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.451072, 0.689495, 0.967641, 1.455853, 2.432276",\
+ "0.493930, 0.732354, 1.010260, 1.497643, 2.472409",\
+ "0.570383, 0.808808, 1.086665, 1.573880, 2.548310",\
+ "0.793657, 1.032083, 1.309620, 1.795731, 2.767951",\
+ "1.356346, 1.594772, 1.872207, 2.357962, 3.329473",\
+ "0.538482, 0.777023, 1.055268, 1.542567, 2.518210",\
+ "0.581340, 0.819882, 1.097884, 1.584358, 2.558343",\
+ "0.657793, 0.896336, 1.174289, 1.660595, 2.634244",\
+ "0.881067, 1.119611, 1.397241, 1.882445, 2.853885",\
+ "1.443756, 1.682300, 1.959826, 2.444677, 3.415407",\
+ "0.619344, 0.865949, 1.143233, 1.630189, 2.605165",\
+ "0.662202, 0.908808, 1.185849, 1.671979, 2.645298",\
+ "0.738655, 0.985262, 1.262254, 1.748217, 2.721199",\
+ "0.961929, 1.208537, 1.485206, 1.970067, 2.940840",\
+ "1.524618, 1.771226, 2.047791, 2.532299, 3.502362",\
+ "0.677016, 0.931504, 1.207376, 1.694102, 2.668674",\
+ "0.719874, 0.974362, 1.249992, 1.735892, 2.708807",\
+ "0.796327, 1.050816, 1.326397, 1.812130, 2.784708",\
+ "1.019601, 1.274091, 1.549348, 2.033980, 3.004349",\
+ "1.582290, 1.836781, 2.111933, 2.596212, 3.565871",\
+ "0.998045, 1.294967, 1.559438, 2.043528, 3.014130",\
+ "1.040903, 1.337826, 1.602045, 2.085314, 3.054263",\
+ "1.117357, 1.414280, 1.678448, 2.161551, 3.130164",\
+ "1.340631, 1.637555, 1.901389, 2.383397, 3.349805",\
+ "1.903320, 2.200244, 2.463970, 2.945627, 3.911327");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\
+ "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\
+ "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\
+ "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\
+ "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\
+ "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\
+ "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\
+ "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\
+ "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\
+ "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\
+ "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\
+ "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\
+ "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\
+ "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\
+ "2.186890, 2.186890, 2.186890, 2.186890, 2.186891");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.463085, 0.701506, 0.978942, 1.464699, 2.436214",\
+ "0.490745, 0.729166, 1.006601, 1.492359, 2.463874",\
+ "0.539949, 0.778370, 1.055805, 1.541563, 2.513078",\
+ "0.680533, 0.918956, 1.196391, 1.682148, 2.653661",\
+ "1.033170, 1.271589, 1.549246, 2.035768, 3.008812",\
+ "0.550495, 0.789034, 1.066561, 1.551413, 2.522148",\
+ "0.578155, 0.816694, 1.094220, 1.579073, 2.549807",\
+ "0.627359, 0.865897, 1.143424, 1.628277, 2.599012",\
+ "0.767943, 1.006484, 1.284010, 1.768862, 2.739595",\
+ "1.120580, 1.359117, 1.636868, 2.122482, 3.094745",\
+ "0.631357, 0.877960, 1.154525, 1.639035, 2.609103",\
+ "0.659017, 0.905619, 1.182185, 1.666695, 2.636762",\
+ "0.708221, 0.954823, 1.231389, 1.715899, 2.685967",\
+ "0.848805, 1.095410, 1.371975, 1.856484, 2.826550",\
+ "1.201442, 1.448043, 1.724832, 2.210104, 3.181700",\
+ "0.689029, 0.943515, 1.218668, 1.702948, 2.672612",\
+ "0.716689, 0.971174, 1.246328, 1.730608, 2.700271",\
+ "0.765893, 1.020378, 1.295531, 1.779812, 2.749476",\
+ "0.906477, 1.160964, 1.436117, 1.920397, 2.890059",\
+ "1.259114, 1.513598, 1.788975, 2.274017, 3.245209",\
+ "1.010056, 1.306978, 1.570705, 2.052364, 3.018068",\
+ "1.037716, 1.334638, 1.598365, 2.080023, 3.045727",\
+ "1.086920, 1.383842, 1.647568, 2.129227, 3.094932",\
+ "1.227505, 1.524428, 1.788154, 2.269813, 3.235515",\
+ "1.580140, 1.877061, 2.141020, 2.623435, 3.590666");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.031044, 0.031047, 0.031141, 0.031458, 0.032092",\
+ "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\
+ "0.031044, 0.031047, 0.031142, 0.031458, 0.032092",\
+ "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\
+ "0.031044, 0.031047, 0.031142, 0.031458, 0.032092",\
+ "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\
+ "0.031044, 0.031047, 0.031142, 0.031458, 0.032092",\
+ "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\
+ "0.031045, 0.031048, 0.031146, 0.031459, 0.032092",\
+ "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169261, 1.169262, 1.169281, 1.169343, 1.169468");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2423*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[36]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.549373, 0.808602, 1.094677, 1.588458, 2.576021",\
+ "0.599470, 0.858699, 1.144772, 1.638553, 2.626115",\
+ "0.688134, 0.947361, 1.233431, 1.727210, 2.714768",\
+ "0.912284, 1.171509, 1.457578, 1.951357, 2.938914",\
+ "1.464909, 1.724133, 2.010202, 2.503980, 3.491537",\
+ "0.636786, 0.896164, 1.182323, 1.675173, 2.661954",\
+ "0.686883, 0.946261, 1.232418, 1.725268, 2.712049",\
+ "0.775547, 1.034922, 1.321077, 1.813925, 2.800702",\
+ "0.999696, 1.259071, 1.545225, 2.038072, 3.024848",\
+ "1.552321, 1.811695, 2.097848, 2.590695, 3.577471",\
+ "0.717681, 0.985182, 1.270288, 1.762795, 2.748909",\
+ "0.767778, 1.035279, 1.320384, 1.812890, 2.799004",\
+ "0.856442, 1.123940, 1.409043, 1.901547, 2.887657",\
+ "1.080592, 1.348089, 1.633190, 2.125694, 3.111803",\
+ "1.633216, 1.900714, 2.185814, 2.678318, 3.664426",\
+ "0.777205, 1.050872, 1.334432, 1.826709, 2.812418",\
+ "0.827302, 1.100968, 1.384528, 1.876804, 2.862513",\
+ "0.915966, 1.189630, 1.473186, 1.965461, 2.951166",\
+ "1.140115, 1.413779, 1.697334, 2.189608, 3.175312",\
+ "1.692740, 1.966403, 2.249958, 2.742231, 3.727935",\
+ "1.110638, 1.415870, 1.686553, 2.176160, 3.157875",\
+ "1.160735, 1.465966, 1.736648, 2.226255, 3.207969",\
+ "1.249399, 1.554628, 1.825307, 2.314913, 3.296622",\
+ "1.473549, 1.778776, 2.049454, 2.539060, 3.520768",\
+ "2.026173, 2.331400, 2.602078, 3.091683, 4.073391");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\
+ "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\
+ "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\
+ "0.855404, 0.855405, 0.855408, 0.855419, 0.855440",\
+ "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\
+ "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\
+ "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\
+ "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\
+ "0.855404, 0.855405, 0.855408, 0.855419, 0.855440",\
+ "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\
+ "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\
+ "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\
+ "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\
+ "0.855404, 0.855405, 0.855408, 0.855419, 0.855440",\
+ "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\
+ "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\
+ "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\
+ "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\
+ "0.855405, 0.855405, 0.855408, 0.855419, 0.855440",\
+ "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\
+ "0.046980, 0.046982, 0.046983, 0.046983, 0.046983",\
+ "0.140333, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\
+ "0.855405, 0.855405, 0.855408, 0.855419, 0.855440",\
+ "2.185952, 2.185953, 2.185954, 2.185960, 2.185970");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.585206, 0.844429, 1.130494, 1.624271, 2.611824",\
+ "0.606889, 0.866111, 1.152175, 1.645951, 2.633503",\
+ "0.648404, 0.907626, 1.193689, 1.687465, 2.675017",\
+ "0.781694, 1.040916, 1.326981, 1.820757, 2.808309",\
+ "1.130589, 1.389812, 1.675878, 2.169654, 3.157208",\
+ "0.672619, 0.931991, 1.218140, 1.710986, 2.697757",\
+ "0.694301, 0.953673, 1.239821, 1.732666, 2.719437",\
+ "0.735816, 0.995187, 1.281336, 1.774180, 2.760951",\
+ "0.869107, 1.128478, 1.414627, 1.907472, 2.894243",\
+ "1.218002, 1.477374, 1.763524, 2.256369, 3.243142",\
+ "0.753514, 1.021009, 1.306106, 1.798608, 2.784713",\
+ "0.775196, 1.042691, 1.327787, 1.820288, 2.806392",\
+ "0.816712, 1.084206, 1.369301, 1.861803, 2.847906",\
+ "0.950002, 1.217496, 1.502593, 1.995094, 2.981198",\
+ "1.298897, 1.566392, 1.851490, 2.343992, 3.330097",\
+ "0.813038, 1.086698, 1.370250, 1.862521, 2.848222",\
+ "0.834720, 1.108380, 1.391931, 1.884202, 2.869901",\
+ "0.876235, 1.149895, 1.433445, 1.925716, 2.911415",\
+ "1.009526, 1.283186, 1.566736, 2.059008, 3.044707",\
+ "1.358421, 1.632081, 1.915633, 2.407905, 3.393606",\
+ "1.146470, 1.451694, 1.722370, 2.211973, 3.193677",\
+ "1.168153, 1.473376, 1.744051, 2.233654, 3.215357",\
+ "1.209668, 1.514891, 1.785565, 2.275168, 3.256871",\
+ "1.342959, 1.648182, 1.918857, 2.408459, 3.390163",\
+ "1.691854, 1.997078, 2.267754, 2.757357, 3.739062");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\
+ "0.082751, 0.082753, 0.082754, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\
+ "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\
+ "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\
+ "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\
+ "0.082751, 0.082753, 0.082754, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\
+ "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\
+ "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\
+ "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\
+ "0.082751, 0.082753, 0.082754, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\
+ "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\
+ "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\
+ "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\
+ "0.082752, 0.082753, 0.082754, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\
+ "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\
+ "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\
+ "0.045700, 0.045704, 0.045708, 0.045711, 0.045717",\
+ "0.082752, 0.082753, 0.082754, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\
+ "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\
+ "1.170720, 1.170720, 1.170720, 1.170722, 1.170727");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2482*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[37]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.531759, 0.784650, 1.063366, 1.526559, 2.452945",\
+ "0.581856, 0.834746, 1.113461, 1.576654, 2.503039",\
+ "0.670520, 0.923407, 1.202119, 1.665310, 2.591694",\
+ "0.894669, 1.147555, 1.426266, 1.889457, 2.815840",\
+ "1.447294, 1.700179, 1.978889, 2.442080, 3.368464",\
+ "0.619167, 0.872231, 1.150913, 1.613273, 2.538878",\
+ "0.669264, 0.922327, 1.201009, 1.663368, 2.588973",\
+ "0.757928, 1.010988, 1.289666, 1.752025, 2.677628",\
+ "0.982077, 1.235136, 1.513813, 1.976171, 2.901774",\
+ "1.534702, 1.787760, 2.066437, 2.528795, 3.454397",\
+ "0.699981, 0.961270, 1.238877, 1.700895, 2.625834",\
+ "0.750078, 1.011366, 1.288972, 1.750990, 2.675928",\
+ "0.838742, 1.100027, 1.377629, 1.839646, 2.764583",\
+ "1.062892, 1.324176, 1.601776, 2.063793, 2.988729",\
+ "1.615517, 1.876800, 2.154400, 2.616416, 3.541352",\
+ "0.757572, 1.026990, 1.303015, 1.764808, 2.689342",\
+ "0.807669, 1.077086, 1.353110, 1.814903, 2.739437",\
+ "0.896333, 1.165747, 1.441768, 1.903559, 2.828092",\
+ "1.120482, 1.389895, 1.665915, 2.127706, 3.052238",\
+ "1.673107, 1.942519, 2.218538, 2.680329, 3.604861",\
+ "1.090182, 1.392406, 1.654823, 2.114129, 3.034798",\
+ "1.140279, 1.442501, 1.704918, 2.164223, 3.084893",\
+ "1.228943, 1.531161, 1.793575, 2.252880, 3.173548",\
+ "1.453092, 1.755309, 2.017722, 2.477027, 3.397694",\
+ "2.005717, 2.307933, 2.570345, 3.029650, 3.950317");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\
+ "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\
+ "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\
+ "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\
+ "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\
+ "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\
+ "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\
+ "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\
+ "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\
+ "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\
+ "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\
+ "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\
+ "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\
+ "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\
+ "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\
+ "0.855404, 0.855404, 0.855406, 0.855410, 0.855418",\
+ "2.185952, 2.185952, 2.185953, 2.185955, 2.185959");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.567591, 0.820473, 1.099180, 1.562370, 2.488752",\
+ "0.589274, 0.842155, 1.120860, 1.584051, 2.510432",\
+ "0.630789, 0.883670, 1.162374, 1.625565, 2.551946",\
+ "0.764080, 1.016961, 1.295666, 1.758857, 2.685237",\
+ "1.112975, 1.365857, 1.644563, 2.107754, 3.034136",\
+ "0.655000, 0.908054, 1.186727, 1.649085, 2.574686",\
+ "0.676682, 0.929736, 1.208408, 1.670765, 2.596366",\
+ "0.718198, 0.971251, 1.249922, 1.712279, 2.637879",\
+ "0.851488, 1.104542, 1.383214, 1.845571, 2.771171",\
+ "1.200383, 1.453438, 1.732111, 2.194468, 3.120070",\
+ "0.735814, 0.997094, 1.274690, 1.736706, 2.661641",\
+ "0.757496, 1.018775, 1.296371, 1.758387, 2.683321",\
+ "0.799012, 1.060290, 1.337885, 1.799901, 2.724834",\
+ "0.932302, 1.193581, 1.471177, 1.933192, 2.858126",\
+ "1.281197, 1.542477, 1.820074, 2.282090, 3.207025",\
+ "0.793404, 1.062813, 1.338829, 1.800619, 2.725150",\
+ "0.815087, 1.084495, 1.360510, 1.822300, 2.746830",\
+ "0.856602, 1.126010, 1.402024, 1.863814, 2.788343",\
+ "0.989893, 1.259301, 1.535315, 1.997105, 2.921635",\
+ "1.338787, 1.608197, 1.884213, 2.346003, 3.270534",\
+ "1.126013, 1.428226, 1.690636, 2.149940, 3.070606",\
+ "1.147696, 1.449908, 1.712317, 2.171620, 3.092286",\
+ "1.189211, 1.491422, 1.753831, 2.213135, 3.133800",\
+ "1.322502, 1.624713, 1.887123, 2.346426, 3.267091",\
+ "1.671397, 1.973610, 2.236020, 2.695324, 3.615990");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\
+ "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\
+ "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\
+ "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\
+ "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\
+ "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\
+ "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\
+ "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\
+ "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\
+ "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\
+ "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\
+ "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\
+ "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\
+ "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\
+ "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\
+ "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\
+ "0.045700, 0.045706, 0.045710, 0.045712, 0.045714",\
+ "0.082752, 0.082753, 0.082755, 0.082755, 0.082756",\
+ "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\
+ "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\
+ "1.170720, 1.170720, 1.170720, 1.170721, 1.170722");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2546*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[39]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.406169, 0.656592, 0.934420, 1.432277, 2.427991",\
+ "0.449017, 0.699439, 0.977034, 1.474087, 2.468193",\
+ "0.525461, 0.775882, 1.053428, 1.550312, 2.544081",\
+ "0.748731, 0.999151, 1.276378, 1.772159, 2.763722",\
+ "1.311413, 1.561833, 1.838149, 2.330786, 3.316060",\
+ "0.493579, 0.744100, 1.022078, 1.518992, 2.513925",\
+ "0.536427, 0.786947, 1.064689, 1.560801, 2.554126",\
+ "0.612871, 0.863390, 1.141083, 1.637027, 2.630014",\
+ "0.836140, 1.086659, 1.364029, 1.858874, 2.849656",\
+ "1.398823, 1.649341, 1.925790, 2.417500, 3.401994",\
+ "0.574430, 0.832981, 1.110043, 1.606613, 2.600880",\
+ "0.617278, 0.875827, 1.152654, 1.648423, 2.641081",\
+ "0.693722, 0.952271, 1.229048, 1.724649, 2.716969",\
+ "0.916992, 1.175540, 1.451994, 1.946496, 2.936611",\
+ "1.479674, 1.738222, 2.013755, 2.505122, 3.488949",\
+ "0.633136, 0.898470, 1.174188, 1.670527, 2.664389",\
+ "0.675984, 0.941316, 1.216799, 1.712336, 2.704590",\
+ "0.752428, 1.017760, 1.293192, 1.788562, 2.780478",\
+ "0.975698, 1.241029, 1.516138, 2.010409, 3.000120",\
+ "1.538380, 1.803711, 2.077899, 2.569036, 3.552458",\
+ "0.968049, 1.261165, 1.526347, 2.019992, 3.009845",\
+ "1.010896, 1.304012, 1.568950, 2.061798, 3.050046",\
+ "1.087340, 1.380455, 1.645342, 2.138023, 3.125935",\
+ "1.310609, 1.603724, 1.868277, 2.359865, 3.345576",\
+ "1.873291, 2.166406, 2.430006, 2.918479, 3.897913");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.072784, 0.072803, 0.073020, 0.073739, 0.075177",\
+ "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\
+ "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\
+ "0.855741, 0.855755, 0.855915, 0.856445, 0.857505",\
+ "2.187214, 2.187237, 2.187508, 2.188406, 2.190202",\
+ "0.072784, 0.072803, 0.073022, 0.073739, 0.075177",\
+ "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\
+ "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\
+ "0.855741, 0.855755, 0.855917, 0.856445, 0.857505",\
+ "2.187214, 2.187237, 2.187511, 2.188406, 2.190202",\
+ "0.072785, 0.072803, 0.073022, 0.073739, 0.075177",\
+ "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\
+ "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\
+ "0.855742, 0.855755, 0.855917, 0.856445, 0.857505",\
+ "2.187214, 2.187238, 2.187511, 2.188406, 2.190202",\
+ "0.072787, 0.072803, 0.073023, 0.073739, 0.075177",\
+ "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\
+ "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\
+ "0.855743, 0.855755, 0.855917, 0.856445, 0.857505",\
+ "2.187217, 2.187238, 2.187511, 2.188406, 2.190202",\
+ "0.072792, 0.072806, 0.073030, 0.073742, 0.075177",\
+ "0.151158, 0.151161, 0.151205, 0.151343, 0.151621",\
+ "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\
+ "0.855747, 0.855757, 0.855922, 0.856447, 0.857505",\
+ "2.187224, 2.187241, 2.187521, 2.188410, 2.190202");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.418201, 0.668626, 0.943179, 1.429721, 2.402805",\
+ "0.445861, 0.696286, 0.970980, 1.458010, 2.432069",\
+ "0.495070, 0.745495, 1.020403, 1.508166, 2.483693",\
+ "0.635634, 0.886057, 1.161631, 1.651703, 2.631847",\
+ "0.988299, 1.238725, 1.516052, 2.012175, 3.004421",\
+ "0.505610, 0.756134, 1.030800, 1.516435, 2.488739",\
+ "0.533270, 0.783794, 1.058603, 1.544724, 2.518003",\
+ "0.582480, 0.833003, 1.108028, 1.594880, 2.569627",\
+ "0.723043, 0.973565, 1.249264, 1.738417, 2.717781",\
+ "1.075708, 1.326233, 1.603704, 2.098890, 3.090355",\
+ "0.586462, 0.845014, 1.118765, 1.604057, 2.575694",\
+ "0.614122, 0.872674, 1.146568, 1.632346, 2.604958",\
+ "0.663331, 0.921884, 1.195993, 1.682502, 2.656582",\
+ "0.803894, 1.062445, 1.337229, 1.826039, 2.804736",\
+ "1.156560, 1.415114, 1.691670, 2.186512, 3.177310",\
+ "0.645168, 0.910503, 1.182908, 1.667970, 2.639203",\
+ "0.672828, 0.938163, 1.210711, 1.696259, 2.668467",\
+ "0.722037, 0.987373, 1.260136, 1.746415, 2.720091",\
+ "0.862600, 1.127934, 1.401372, 1.889952, 2.868245",\
+ "1.215266, 1.480603, 1.755814, 2.250425, 3.240819",\
+ "0.980081, 1.273199, 1.534953, 2.017389, 2.984659",\
+ "1.007741, 1.300859, 1.562760, 2.045680, 3.013923",\
+ "1.056951, 1.350069, 1.612193, 2.095839, 3.065547",\
+ "1.197513, 1.490629, 1.753453, 2.239386, 3.213701",\
+ "1.550180, 1.843298, 2.107956, 2.599883, 3.586275");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.031046, 0.031099, 0.031481, 0.032572, 0.034755",\
+ "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\
+ "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\
+ "0.457144, 0.457135, 0.457066, 0.456868, 0.456473",\
+ "1.169261, 1.169272, 1.169347, 1.169562, 1.169994",\
+ "0.031046, 0.031099, 0.031484, 0.032572, 0.034755",\
+ "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\
+ "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\
+ "0.457144, 0.457135, 0.457065, 0.456868, 0.456473",\
+ "1.169261, 1.169272, 1.169348, 1.169562, 1.169994",\
+ "0.031046, 0.031100, 0.031484, 0.032572, 0.034755",\
+ "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\
+ "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\
+ "0.457144, 0.457134, 0.457065, 0.456868, 0.456473",\
+ "1.169261, 1.169272, 1.169348, 1.169562, 1.169994",\
+ "0.031048, 0.031101, 0.031484, 0.032572, 0.034755",\
+ "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\
+ "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\
+ "0.457144, 0.457134, 0.457065, 0.456868, 0.456473",\
+ "1.169261, 1.169272, 1.169348, 1.169562, 1.169994",\
+ "0.031051, 0.031118, 0.031495, 0.032577, 0.034755",\
+ "0.078405, 0.078410, 0.078444, 0.078540, 0.078733",\
+ "0.173504, 0.173502, 0.173487, 0.173443, 0.173357",\
+ "0.457143, 0.457131, 0.457063, 0.456867, 0.456473",\
+ "1.169262, 1.169275, 1.169350, 1.169563, 1.169994");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2619*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[41]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.553465, 0.819964, 1.109829, 1.605668, 2.597345",\
+ "0.603560, 0.870058, 1.159923, 1.655763, 2.647441",\
+ "0.692214, 0.958711, 1.248576, 1.744417, 2.736099",\
+ "0.916360, 1.182856, 1.472721, 1.968563, 2.960246",\
+ "1.468983, 1.735479, 2.025344, 2.521186, 3.512870",\
+ "0.640874, 0.907555, 1.197480, 1.692382, 2.683279",\
+ "0.690968, 0.957649, 1.247574, 1.742477, 2.733375",\
+ "0.779622, 1.046302, 1.336226, 1.831131, 2.822032",\
+ "1.003768, 1.270447, 1.560372, 2.055277, 3.046180",\
+ "1.556391, 1.823070, 2.112994, 2.607900, 3.598804",\
+ "0.721784, 0.996619, 1.285445, 1.780004, 2.770234",\
+ "0.771879, 1.046713, 1.335539, 1.830098, 2.820330",\
+ "0.860533, 1.135366, 1.424191, 1.918753, 2.908988",\
+ "1.084679, 1.359511, 1.648337, 2.142899, 3.133135",\
+ "1.637302, 1.912134, 2.200959, 2.695522, 3.685759",\
+ "0.783629, 1.062374, 1.349589, 1.843917, 2.833743",\
+ "0.833723, 1.112468, 1.399683, 1.894011, 2.883839",\
+ "0.922377, 1.201121, 1.488336, 1.982666, 2.972497",\
+ "1.146523, 1.425267, 1.712481, 2.206812, 3.196644",\
+ "1.699146, 1.977889, 2.265103, 2.759435, 3.749268",\
+ "1.121586, 1.428200, 1.701728, 2.193373, 3.179199",\
+ "1.171680, 1.478294, 1.751822, 2.243467, 3.229295",\
+ "1.260334, 1.566947, 1.840474, 2.332122, 3.317953",\
+ "1.484480, 1.791093, 2.064620, 2.556268, 3.542100",\
+ "2.037102, 2.343715, 2.617242, 3.108891, 4.094724");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\
+ "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\
+ "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\
+ "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\
+ "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\
+ "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\
+ "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\
+ "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\
+ "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\
+ "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\
+ "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\
+ "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\
+ "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\
+ "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\
+ "2.185946, 2.185946, 2.185947, 2.185952, 2.185961");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.589270, 0.855765, 1.145630, 1.641474, 2.633161",\
+ "0.610950, 0.877444, 1.167309, 1.663153, 2.654842",\
+ "0.652464, 0.918958, 1.208822, 1.704667, 2.696356",\
+ "0.785756, 1.052250, 1.342115, 1.837959, 2.829648",\
+ "1.134654, 1.401149, 1.691014, 2.186858, 3.178545",\
+ "0.676679, 0.943356, 1.233280, 1.728188, 2.719095",\
+ "0.698358, 0.965036, 1.254959, 1.749868, 2.740776",\
+ "0.739872, 1.006549, 1.296473, 1.791381, 2.782290",\
+ "0.873164, 1.139841, 1.429765, 1.924673, 2.915581",\
+ "1.222063, 1.488740, 1.778664, 2.273572, 3.264479",\
+ "0.757589, 1.032420, 1.321245, 1.815809, 2.806050",\
+ "0.779269, 1.054100, 1.342925, 1.837489, 2.827731",\
+ "0.820783, 1.095613, 1.384438, 1.879003, 2.869245",\
+ "0.954075, 1.228905, 1.517730, 2.012295, 3.002537",\
+ "1.302974, 1.577804, 1.866629, 2.361193, 3.351434",\
+ "0.819433, 1.098175, 1.385389, 1.879722, 2.869559",\
+ "0.841113, 1.119855, 1.407069, 1.901402, 2.891240",\
+ "0.882627, 1.161368, 1.448582, 1.942916, 2.932754",\
+ "1.015919, 1.294661, 1.581874, 2.076208, 3.066046",\
+ "1.364817, 1.643559, 1.930773, 2.425107, 3.414943",\
+ "1.157390, 1.464001, 1.737528, 2.229178, 3.215015",\
+ "1.179069, 1.485680, 1.759207, 2.250858, 3.236696",\
+ "1.220583, 1.527194, 1.800721, 2.292372, 3.278210",\
+ "1.353875, 1.660486, 1.934013, 2.425664, 3.411501",\
+ "1.702774, 2.009385, 2.282912, 2.774562, 3.760399");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.045715, 0.045718, 0.045719, 0.045719, 0.045719",\
+ "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\
+ "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\
+ "0.045715, 0.045718, 0.045719, 0.045719, 0.045719",\
+ "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\
+ "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\
+ "0.045715, 0.045718, 0.045719, 0.045719, 0.045719",\
+ "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\
+ "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\
+ "0.045716, 0.045718, 0.045719, 0.045719, 0.045719",\
+ "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\
+ "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\
+ "0.045716, 0.045718, 0.045719, 0.045719, 0.045719",\
+ "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\
+ "1.170717, 1.170717, 1.170718, 1.170720, 1.170723");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2551*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[42]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.535912, 0.788172, 1.068241, 1.533239, 2.463234",\
+ "0.586006, 0.838266, 1.118335, 1.583333, 2.513329",\
+ "0.674661, 0.926920, 1.206988, 1.671987, 2.601985",\
+ "0.898807, 1.151066, 1.431133, 1.896132, 2.826131",\
+ "1.451430, 1.703688, 1.983755, 2.448755, 3.378754",\
+ "0.623320, 0.875758, 1.155794, 1.619953, 2.549168",\
+ "0.673414, 0.925853, 1.205888, 1.670047, 2.599263",\
+ "0.762069, 1.014506, 1.294541, 1.758701, 2.687918",\
+ "0.986215, 1.238652, 1.518686, 1.982847, 2.912065",\
+ "1.538838, 1.791275, 2.071309, 2.535469, 3.464688",\
+ "0.704222, 0.964810, 1.243757, 1.707574, 2.636123",\
+ "0.754316, 1.014904, 1.293851, 1.757668, 2.686218",\
+ "0.842971, 1.103558, 1.382504, 1.846323, 2.774873",\
+ "1.067117, 1.327704, 1.606649, 2.070468, 2.999020",\
+ "1.619740, 1.880326, 2.159272, 2.623091, 3.551643",\
+ "0.761984, 1.030547, 1.307896, 1.771487, 2.699632",\
+ "0.812078, 1.080642, 1.357990, 1.821582, 2.749727",\
+ "0.900733, 1.169295, 1.446643, 1.910236, 2.838382",\
+ "1.124879, 1.393441, 1.670788, 2.134381, 3.062529",\
+ "1.677502, 1.946064, 2.223411, 2.687004, 3.615152",\
+ "1.092601, 1.396168, 1.659722, 2.120816, 3.045088",\
+ "1.142695, 1.446262, 1.709816, 2.170910, 3.095183",\
+ "1.231350, 1.534915, 1.798469, 2.259564, 3.183838",\
+ "1.455496, 1.759061, 2.022614, 2.483710, 3.407985",\
+ "2.008119, 2.311684, 2.575236, 3.036332, 3.960608");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\
+ "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\
+ "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\
+ "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\
+ "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\
+ "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\
+ "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\
+ "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\
+ "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\
+ "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\
+ "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\
+ "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\
+ "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\
+ "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\
+ "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\
+ "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\
+ "2.185946, 2.185946, 2.185946, 2.185949, 2.185954");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.571718, 0.823975, 1.104042, 1.569042, 2.499043",\
+ "0.593398, 0.845655, 1.125721, 1.590722, 2.520724",\
+ "0.634911, 0.887169, 1.167235, 1.632236, 2.562238",\
+ "0.768203, 1.020461, 1.300527, 1.765528, 2.695529",\
+ "1.117102, 1.369359, 1.649426, 2.114426, 3.044427",\
+ "0.659126, 0.911562, 1.191595, 1.655756, 2.584977",\
+ "0.680806, 0.933241, 1.213274, 1.677436, 2.606658",\
+ "0.722320, 0.974755, 1.254788, 1.718950, 2.648171",\
+ "0.855612, 1.108047, 1.388080, 1.852242, 2.781463",\
+ "1.204510, 1.456946, 1.736979, 2.201141, 3.130361",\
+ "0.740028, 1.000613, 1.279558, 1.743378, 2.671932",\
+ "0.761708, 1.022293, 1.301237, 1.765058, 2.693613",\
+ "0.803222, 1.063807, 1.342751, 1.806571, 2.735126",\
+ "0.936514, 1.197099, 1.476043, 1.939863, 2.868418",\
+ "1.285412, 1.545998, 1.824942, 2.288762, 3.217316",\
+ "0.797790, 1.066351, 1.343697, 1.807291, 2.735441",\
+ "0.819470, 1.088030, 1.365376, 1.828971, 2.757122",\
+ "0.860984, 1.129544, 1.406890, 1.870484, 2.798635",\
+ "0.994276, 1.262836, 1.540182, 2.003777, 2.931927",\
+ "1.343174, 1.611735, 1.889081, 2.352675, 3.280825",\
+ "1.128407, 1.431970, 1.695523, 2.156619, 3.080897",\
+ "1.150087, 1.453650, 1.717202, 2.178299, 3.102577",\
+ "1.191600, 1.495163, 1.758715, 2.219813, 3.144091",\
+ "1.324893, 1.628456, 1.892008, 2.353105, 3.277383",\
+ "1.673791, 1.977355, 2.240907, 2.702003, 3.626281");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\
+ "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\
+ "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\
+ "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\
+ "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\
+ "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\
+ "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\
+ "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\
+ "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\
+ "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\
+ "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\
+ "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\
+ "0.045715, 0.045717, 0.045718, 0.045718, 0.045718",\
+ "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\
+ "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\
+ "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\
+ "1.170717, 1.170717, 1.170717, 1.170718, 1.170720");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2487*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[43]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.552964, 0.814309, 1.099442, 1.604025, 2.613190",\
+ "0.595811, 0.857156, 1.142289, 1.646869, 2.656030",\
+ "0.672254, 0.933599, 1.218732, 1.723310, 2.732467",\
+ "0.895523, 1.156868, 1.442001, 1.946579, 2.955732",\
+ "1.458204, 1.719550, 2.004683, 2.509259, 3.518410",\
+ "0.640373, 0.901851, 1.187121, 1.690739, 2.699123",\
+ "0.683220, 0.944698, 1.229968, 1.733584, 2.741963",\
+ "0.759663, 1.021142, 1.306411, 1.810025, 2.818400",\
+ "0.982932, 1.244411, 1.529680, 2.033293, 3.041666",\
+ "1.545614, 1.807093, 2.092361, 2.595973, 3.604344",\
+ "0.723483, 0.990810, 1.275087, 1.778361, 2.786078",\
+ "0.766329, 1.033657, 1.317933, 1.821205, 2.828918",\
+ "0.842772, 1.110100, 1.394377, 1.897646, 2.905355",\
+ "1.066041, 1.333369, 1.617646, 2.120914, 3.128621",\
+ "1.628723, 1.896051, 2.180327, 2.683595, 3.691299",\
+ "0.786922, 1.056412, 1.339232, 1.842274, 2.849587",\
+ "0.829768, 1.099259, 1.382079, 1.885119, 2.892427",\
+ "0.906211, 1.175702, 1.458522, 1.961560, 2.968864",\
+ "1.129480, 1.398971, 1.681791, 2.184828, 3.192130",\
+ "1.692162, 1.961653, 2.244473, 2.747508, 3.754808",\
+ "1.122015, 1.420432, 1.691460, 2.191767, 3.195044",\
+ "1.164862, 1.463279, 1.734307, 2.234612, 3.237884",\
+ "1.241305, 1.539723, 1.810750, 2.311053, 3.314321",\
+ "1.464574, 1.762992, 2.034019, 2.534321, 3.537586",\
+ "2.027255, 2.325674, 2.596701, 3.097001, 4.100264");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.072811, 0.072811, 0.072826, 0.072880, 0.072987",\
+ "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\
+ "2.187247, 2.187247, 2.187266, 2.187333, 2.187467",\
+ "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\
+ "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\
+ "2.187247, 2.187247, 2.187267, 2.187333, 2.187467",\
+ "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\
+ "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\
+ "2.187247, 2.187247, 2.187267, 2.187333, 2.187467",\
+ "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\
+ "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\
+ "2.187247, 2.187247, 2.187267, 2.187333, 2.187467",\
+ "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\
+ "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855773, 0.855812, 0.855891",\
+ "2.187247, 2.187247, 2.187267, 2.187334, 2.187467");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.564998, 0.826343, 1.111477, 1.616063, 2.625237",\
+ "0.592658, 0.854002, 1.139137, 1.643723, 2.652897",\
+ "0.641868, 0.903212, 1.188347, 1.692935, 2.702110",\
+ "0.782429, 1.043773, 1.328907, 1.833490, 2.842657",\
+ "1.135098, 1.396442, 1.681576, 2.186166, 3.195345",\
+ "0.652408, 0.913885, 1.199155, 1.702778, 2.711171",\
+ "0.680068, 0.941545, 1.226815, 1.730438, 2.738831",\
+ "0.729278, 0.990755, 1.276025, 1.779649, 2.788044",\
+ "0.869838, 1.131316, 1.416586, 1.920205, 2.928591",\
+ "1.222507, 1.483984, 1.769255, 2.272880, 3.281279",\
+ "0.735517, 1.002843, 1.287121, 1.790400, 2.798126",\
+ "0.763177, 1.030503, 1.314781, 1.818060, 2.825786",\
+ "0.812387, 1.079713, 1.363991, 1.867271, 2.874999",\
+ "0.952947, 1.220274, 1.504552, 2.007827, 3.015546",\
+ "1.305617, 1.572943, 1.857221, 2.360502, 3.368234",\
+ "0.798956, 1.068446, 1.351267, 1.854313, 2.861635",\
+ "0.826616, 1.096106, 1.378927, 1.881973, 2.889295",\
+ "0.875826, 1.145315, 1.428137, 1.931184, 2.938508",\
+ "1.016386, 1.285877, 1.568697, 2.071740, 3.079055",\
+ "1.369056, 1.638545, 1.921366, 2.424415, 3.431743",\
+ "1.134049, 1.432466, 1.703495, 2.203806, 3.207091",\
+ "1.161709, 1.460126, 1.731154, 2.231466, 3.234751",\
+ "1.210919, 1.509335, 1.780365, 2.280677, 3.283964",\
+ "1.351480, 1.649897, 1.920925, 2.421233, 3.424510",\
+ "1.704149, 2.002565, 2.273594, 2.773909, 3.777199");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.031035, 0.031069, 0.031220, 0.031570, 0.032271",\
+ "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169266, 1.169295, 1.169365, 1.169503",\
+ "0.031035, 0.031069, 0.031221, 0.031570, 0.032271",\
+ "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169266, 1.169296, 1.169365, 1.169503",\
+ "0.031035, 0.031070, 0.031221, 0.031570, 0.032271",\
+ "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169266, 1.169296, 1.169365, 1.169503",\
+ "0.031035, 0.031071, 0.031221, 0.031570, 0.032271",\
+ "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169266, 1.169296, 1.169365, 1.169503",\
+ "0.031035, 0.031083, 0.031224, 0.031571, 0.032271",\
+ "0.078403, 0.078407, 0.078420, 0.078451, 0.078513",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169268, 1.169296, 1.169365, 1.169503");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[44]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.538940, 0.779876, 1.050099, 1.503272, 2.409617",\
+ "0.581786, 0.822723, 1.092946, 1.546117, 2.452459",\
+ "0.658229, 0.899166, 1.169389, 1.622558, 2.528897",\
+ "0.881498, 1.122435, 1.392658, 1.845826, 2.752164",\
+ "1.444180, 1.685117, 1.955339, 2.408507, 3.314842",\
+ "0.626346, 0.867426, 1.137614, 1.589986, 2.495551",\
+ "0.669192, 0.910272, 1.180461, 1.632831, 2.538393",\
+ "0.745635, 0.986716, 1.256904, 1.709272, 2.614831",\
+ "0.968904, 1.209985, 1.480173, 1.932540, 2.838098",\
+ "1.531586, 1.772666, 2.042854, 2.495221, 3.400776",\
+ "0.707175, 0.956384, 1.225576, 1.677607, 2.582506",\
+ "0.750022, 0.999231, 1.268423, 1.720452, 2.625348",\
+ "0.826465, 1.075674, 1.344866, 1.796893, 2.701786",\
+ "1.049734, 1.298944, 1.568135, 2.020162, 2.925053",\
+ "1.612416, 1.861625, 2.130816, 2.582842, 3.487731",\
+ "0.764818, 1.021986, 1.289713, 1.741520, 2.646015",\
+ "0.807664, 1.064833, 1.332560, 1.784365, 2.688857",\
+ "0.884107, 1.141276, 1.409003, 1.860806, 2.765295",\
+ "1.107376, 1.364545, 1.632272, 2.084074, 2.988562",\
+ "1.670058, 1.927227, 2.194953, 2.646755, 3.551240",\
+ "1.090702, 1.386049, 1.641418, 2.090797, 2.991471",\
+ "1.133548, 1.428896, 1.684264, 2.133642, 3.034313",\
+ "1.209992, 1.505339, 1.760707, 2.210084, 3.110751",\
+ "1.433261, 1.728608, 1.983976, 2.433352, 3.334018",\
+ "1.995942, 2.291290, 2.546658, 2.996032, 3.896696");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\
+ "0.151162, 0.151162, 0.151164, 0.151172, 0.151188",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\
+ "2.187248, 2.187248, 2.187262, 2.187313, 2.187414",\
+ "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\
+ "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\
+ "2.187248, 2.187248, 2.187262, 2.187313, 2.187414",\
+ "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\
+ "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\
+ "2.187248, 2.187248, 2.187262, 2.187313, 2.187414",\
+ "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\
+ "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\
+ "2.187248, 2.187248, 2.187263, 2.187313, 2.187414",\
+ "0.072811, 0.072811, 0.072824, 0.072864, 0.072944",\
+ "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\
+ "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\
+ "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\
+ "2.187248, 2.187248, 2.187263, 2.187313, 2.187414");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.550974, 0.791910, 1.062134, 1.515310, 2.421661",\
+ "0.578634, 0.819570, 1.089794, 1.542970, 2.449322",\
+ "0.627844, 0.868780, 1.139004, 1.592180, 2.498534",\
+ "0.768404, 1.009341, 1.279564, 1.732737, 2.639084",\
+ "1.121073, 1.362010, 1.632233, 2.085412, 2.991768",\
+ "0.638380, 0.879460, 1.149649, 1.602023, 2.507595",\
+ "0.666040, 0.907120, 1.177309, 1.629683, 2.535255",\
+ "0.715250, 0.956330, 1.226519, 1.678894, 2.584468",\
+ "0.855810, 1.096890, 1.367079, 1.819451, 2.725018",\
+ "1.208480, 1.449559, 1.719748, 2.172125, 3.077702",\
+ "0.719210, 0.968418, 1.237611, 1.689645, 2.594550",\
+ "0.746870, 0.996078, 1.265271, 1.717305, 2.622211",\
+ "0.796080, 1.045288, 1.314481, 1.766516, 2.671423",\
+ "0.936640, 1.185849, 1.455041, 1.907072, 2.811973",\
+ "1.289309, 1.538518, 1.807710, 2.259747, 3.164657",\
+ "0.776852, 1.034020, 1.301748, 1.753558, 2.658059",\
+ "0.804512, 1.061680, 1.329408, 1.781218, 2.685719",\
+ "0.853722, 1.110890, 1.378618, 1.830429, 2.734932",\
+ "0.994283, 1.251451, 1.519178, 1.970985, 2.875482",\
+ "1.346952, 1.604120, 1.871847, 2.323660, 3.228166",\
+ "1.102736, 1.398083, 1.653452, 2.102835, 3.003515",\
+ "1.130396, 1.425743, 1.681112, 2.130495, 3.031176",\
+ "1.179606, 1.474952, 1.730322, 2.179706, 3.080388",\
+ "1.320167, 1.615513, 1.870883, 2.320263, 3.220938",\
+ "1.672836, 1.968182, 2.223552, 2.672937, 3.573622");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.031036, 0.031054, 0.031161, 0.031438, 0.031991",\
+ "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\
+ "0.031036, 0.031055, 0.031162, 0.031438, 0.031991",\
+ "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\
+ "0.031036, 0.031055, 0.031162, 0.031438, 0.031991",\
+ "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\
+ "0.031036, 0.031055, 0.031162, 0.031438, 0.031991",\
+ "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\
+ "0.031036, 0.031062, 0.031165, 0.031439, 0.031991",\
+ "0.078403, 0.078406, 0.078415, 0.078439, 0.078488",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169259, 1.169264, 1.169285, 1.169339, 1.169448");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2727*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[46]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.564410, 0.823611, 1.109689, 1.603513, 2.591161",\
+ "0.607267, 0.866469, 1.152547, 1.646371, 2.634019",\
+ "0.683720, 0.942922, 1.229000, 1.722825, 2.710474",\
+ "0.906994, 1.166196, 1.452275, 1.946099, 2.933748",\
+ "1.469683, 1.728885, 2.014963, 2.508788, 3.496438",\
+ "0.651822, 0.911173, 1.197335, 1.690228, 2.677094",\
+ "0.694680, 0.954031, 1.240193, 1.733086, 2.719953",\
+ "0.771133, 1.030483, 1.316646, 1.809540, 2.796407",\
+ "0.994407, 1.253758, 1.539921, 2.032814, 3.019682",\
+ "1.557095, 1.816446, 2.102610, 2.595503, 3.582371",\
+ "0.732717, 1.000191, 1.285301, 1.777850, 2.764050",\
+ "0.775575, 1.043049, 1.328159, 1.820708, 2.806908",\
+ "0.852028, 1.119502, 1.404612, 1.897162, 2.883362",\
+ "1.075302, 1.342776, 1.627887, 2.120436, 3.106637",\
+ "1.637990, 1.905464, 2.190576, 2.683125, 3.669326",\
+ "0.792238, 1.065880, 1.349444, 1.841763, 2.827559",\
+ "0.835095, 1.108738, 1.392303, 1.884622, 2.870417",\
+ "0.911548, 1.185191, 1.468756, 1.961075, 2.946871",\
+ "1.134822, 1.408465, 1.692031, 2.184350, 3.170146",\
+ "1.697511, 1.971154, 2.254719, 2.747039, 3.732835",\
+ "1.125661, 1.430876, 1.701565, 2.191215, 3.173015",\
+ "1.168519, 1.473734, 1.744423, 2.234074, 3.215873",\
+ "1.244972, 1.550187, 1.820877, 2.310527, 3.292327",\
+ "1.468246, 1.773462, 2.044151, 2.533802, 3.515602",\
+ "2.030934, 2.336150, 2.606840, 3.096491, 4.078291");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\
+ "0.151107, 0.151106, 0.151104, 0.151103, 0.151101",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\
+ "2.186892, 2.186883, 2.186870, 2.186864, 2.186852",\
+ "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\
+ "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\
+ "2.186892, 2.186883, 2.186870, 2.186864, 2.186852",\
+ "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\
+ "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\
+ "2.186892, 2.186882, 2.186870, 2.186864, 2.186852",\
+ "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\
+ "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\
+ "2.186892, 2.186882, 2.186870, 2.186864, 2.186852",\
+ "0.072525, 0.072517, 0.072509, 0.072504, 0.072494",\
+ "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855551, 0.855544, 0.855538, 0.855535, 0.855527",\
+ "2.186891, 2.186880, 2.186870, 2.186864, 2.186852");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.576423, 0.835624, 1.121701, 1.615525, 2.603172",\
+ "0.604083, 0.863284, 1.149361, 1.643184, 2.630832",\
+ "0.653288, 0.912488, 1.198565, 1.692388, 2.680036",\
+ "0.793871, 1.053072, 1.339149, 1.832974, 2.820621",\
+ "1.146508, 1.405709, 1.691785, 2.185609, 3.173255",\
+ "0.663836, 0.923186, 1.209347, 1.702240, 2.689106",\
+ "0.691496, 0.950845, 1.237007, 1.729899, 2.716765",\
+ "0.740700, 1.000050, 1.286211, 1.779103, 2.765969",\
+ "0.881284, 1.140634, 1.426796, 1.919688, 2.906555",\
+ "1.233921, 1.493270, 1.779431, 2.272324, 3.259189",\
+ "0.744731, 1.012204, 1.297313, 1.789862, 2.776061",\
+ "0.772390, 1.039863, 1.324972, 1.817521, 2.803720",\
+ "0.821595, 1.089068, 1.374177, 1.866726, 2.852924",\
+ "0.962178, 1.229652, 1.514761, 2.007311, 2.993510",\
+ "1.314816, 1.582289, 1.867397, 2.359946, 3.346144",\
+ "0.804251, 1.077893, 1.361457, 1.853775, 2.839570",\
+ "0.831911, 1.105553, 1.389116, 1.881435, 2.867229",\
+ "0.881115, 1.154757, 1.438321, 1.930639, 2.916433",\
+ "1.021699, 1.295341, 1.578905, 2.071224, 3.057019",\
+ "1.374336, 1.647978, 1.931541, 2.423859, 3.409653",\
+ "1.137675, 1.442889, 1.713577, 2.203227, 3.185026",\
+ "1.165335, 1.470549, 1.741237, 2.230887, 3.212686",\
+ "1.214539, 1.519753, 1.790441, 2.280091, 3.261889",\
+ "1.355123, 1.660337, 1.931026, 2.420676, 3.402475",\
+ "1.707760, 2.012974, 2.283661, 2.773311, 3.755109");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\
+ "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457146, 0.457146, 0.457146",\
+ "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\
+ "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\
+ "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457146, 0.457146, 0.457146",\
+ "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\
+ "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\
+ "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\
+ "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\
+ "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\
+ "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\
+ "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457146, 0.457146, 0.457146, 0.457146",\
+ "1.169260, 1.169260, 1.169262, 1.169268, 1.169281");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2658*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[47]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.548070, 0.800917, 1.079123, 1.542119, 2.468112",\
+ "0.590927, 0.843775, 1.121981, 1.584977, 2.510970",\
+ "0.667380, 0.920228, 1.198434, 1.661431, 2.587423",\
+ "0.890654, 1.143502, 1.421709, 1.884705, 2.810698",\
+ "1.453343, 1.706191, 1.984398, 2.447394, 3.373387",\
+ "0.635475, 0.888501, 1.166668, 1.628833, 2.554045",\
+ "0.678333, 0.931359, 1.209527, 1.671691, 2.596904",\
+ "0.754786, 1.007812, 1.285980, 1.748145, 2.673357",\
+ "0.978060, 1.231086, 1.509255, 1.971419, 2.896632",\
+ "1.540748, 1.793775, 2.071944, 2.534108, 3.459321",\
+ "0.716287, 0.977534, 1.254631, 1.716454, 2.641000",\
+ "0.759144, 1.020392, 1.297489, 1.759312, 2.683859",\
+ "0.835597, 1.096845, 1.373943, 1.835766, 2.760312",\
+ "1.058871, 1.320120, 1.597218, 2.059040, 2.983587",\
+ "1.621560, 1.882808, 2.159906, 2.621729, 3.546276",\
+ "0.773896, 1.043245, 1.318770, 1.780367, 2.704509",\
+ "0.816754, 1.086103, 1.361628, 1.823225, 2.747368",\
+ "0.893206, 1.162556, 1.438081, 1.899679, 2.823821",\
+ "1.116481, 1.385830, 1.661356, 2.122953, 3.047096",\
+ "1.679169, 1.948519, 2.224045, 2.685642, 3.609785",\
+ "1.108670, 1.408584, 1.670573, 2.129684, 3.049965",\
+ "1.151528, 1.451442, 1.713432, 2.172543, 3.092824",\
+ "1.227981, 1.527896, 1.789885, 2.248996, 3.169277",\
+ "1.451255, 1.751170, 2.013160, 2.472271, 3.392552",\
+ "2.013944, 2.313859, 2.575849, 3.034960, 3.955241");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.072526, 0.072516, 0.072505, 0.072503, 0.072500",\
+ "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\
+ "2.186892, 2.186879, 2.186865, 2.186863, 2.186859",\
+ "0.072526, 0.072516, 0.072505, 0.072503, 0.072500",\
+ "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\
+ "2.186892, 2.186878, 2.186865, 2.186863, 2.186859",\
+ "0.072526, 0.072515, 0.072505, 0.072503, 0.072500",\
+ "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\
+ "2.186892, 2.186878, 2.186865, 2.186863, 2.186859",\
+ "0.072526, 0.072515, 0.072505, 0.072503, 0.072500",\
+ "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\
+ "2.186892, 2.186878, 2.186865, 2.186863, 2.186859",\
+ "0.072524, 0.072513, 0.072505, 0.072503, 0.072500",\
+ "0.151107, 0.151104, 0.151103, 0.151102, 0.151102",\
+ "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\
+ "0.855550, 0.855541, 0.855535, 0.855534, 0.855532",\
+ "2.186889, 2.186875, 2.186865, 2.186863, 2.186859");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.560083, 0.812930, 1.091135, 1.554131, 2.480123",\
+ "0.587743, 0.840589, 1.118794, 1.581790, 2.507782",\
+ "0.636947, 0.889794, 1.167998, 1.630994, 2.556986",\
+ "0.777531, 1.030378, 1.308583, 1.771580, 2.697572",\
+ "1.130168, 1.383014, 1.661218, 2.124214, 3.050207",\
+ "0.647489, 0.900513, 1.178680, 1.640844, 2.566057",\
+ "0.675148, 0.928173, 1.206340, 1.668504, 2.593716",\
+ "0.724353, 0.977377, 1.255544, 1.717708, 2.642920",\
+ "0.864936, 1.117962, 1.396129, 1.858294, 2.783506",\
+ "1.217574, 1.470598, 1.748764, 2.210928, 3.136140",\
+ "0.728300, 0.989547, 1.266643, 1.728466, 2.653012",\
+ "0.755960, 1.017207, 1.294303, 1.756125, 2.680671",\
+ "0.805164, 1.066411, 1.343507, 1.805329, 2.729875",\
+ "0.945748, 1.206995, 1.484092, 1.945915, 2.870461",\
+ "1.298385, 1.559631, 1.836727, 2.298549, 3.223095",\
+ "0.785910, 1.055257, 1.330781, 1.792379, 2.716521",\
+ "0.813569, 1.082917, 1.358441, 1.820038, 2.744180",\
+ "0.862774, 1.132121, 1.407645, 1.869242, 2.793384",\
+ "1.003357, 1.272706, 1.548230, 2.009828, 2.933970",\
+ "1.355995, 1.625342, 1.900865, 2.362462, 3.286604",\
+ "1.120684, 1.420597, 1.682585, 2.141696, 3.061977",\
+ "1.148343, 1.448256, 1.710245, 2.169356, 3.089636",\
+ "1.197548, 1.497461, 1.759449, 2.218560, 3.138840",\
+ "1.338132, 1.638045, 1.900034, 2.359145, 3.279426",\
+ "1.690769, 1.990681, 2.252669, 2.711780, 3.632061");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\
+ "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\
+ "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\
+ "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\
+ "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\
+ "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\
+ "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\
+ "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\
+ "0.031042, 0.031042, 0.031048, 0.031067, 0.031107",\
+ "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\
+ "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\
+ "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\
+ "1.169260, 1.169260, 1.169261, 1.169265, 1.169273");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2601*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[20]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.380795, 0.602668, 0.780712, 1.069465, 1.629809",\
+ "0.415064, 0.636936, 0.814980, 1.103733, 1.664078",\
+ "0.488546, 0.710419, 0.888463, 1.177216, 1.737561",\
+ "0.709765, 0.931638, 1.109681, 1.398435, 1.958779",\
+ "1.271568, 1.493441, 1.671484, 1.960238, 2.520582",\
+ "0.469199, 0.689987, 0.867992, 1.156770, 1.717163",\
+ "0.503468, 0.724255, 0.902261, 1.191038, 1.751431",\
+ "0.576950, 0.797738, 0.975743, 1.264521, 1.824914",\
+ "0.798169, 1.018957, 1.196962, 1.485740, 2.046133",\
+ "1.359972, 1.580759, 1.758765, 2.047543, 2.607936",\
+ "0.558271, 0.770322, 0.948019, 1.236798, 1.797194",\
+ "0.592539, 0.804590, 0.982288, 1.271067, 1.831463",\
+ "0.666022, 0.878073, 1.055770, 1.344549, 1.904946",\
+ "0.887241, 1.099292, 1.276989, 1.565768, 2.126164",\
+ "1.449044, 1.661095, 1.838792, 2.127571, 2.687967",\
+ "0.621529, 0.828138, 1.005713, 1.294227, 1.854208",\
+ "0.655798, 0.862407, 1.039981, 1.328496, 1.888477",\
+ "0.729280, 0.935889, 1.113464, 1.401978, 1.961960",\
+ "0.950499, 1.157108, 1.334682, 1.623197, 2.183178",\
+ "1.512302, 1.718911, 1.896485, 2.185000, 2.744981",\
+ "0.953935, 1.133367, 1.309369, 1.597399, 2.156428",\
+ "0.988204, 1.167636, 1.343637, 1.631667, 2.190696",\
+ "1.061687, 1.241118, 1.417120, 1.705150, 2.264179",\
+ "1.282905, 1.462337, 1.638339, 1.926369, 2.485398",\
+ "1.844708, 2.024140, 2.200142, 2.488172, 3.047201");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\
+ "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\
+ "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\
+ "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\
+ "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\
+ "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\
+ "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\
+ "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\
+ "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\
+ "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131889");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.351941, 0.573814, 0.751857, 1.040610, 1.600955",\
+ "0.377860, 0.599733, 0.777776, 1.066529, 1.626874",\
+ "0.432503, 0.654375, 0.832419, 1.121172, 1.681517",\
+ "0.582379, 0.804252, 0.982296, 1.271049, 1.831393",\
+ "0.955531, 1.177403, 1.355447, 1.644200, 2.204545",\
+ "0.440345, 0.661132, 0.839138, 1.127915, 1.688308",\
+ "0.466264, 0.687051, 0.865057, 1.153834, 1.714228",\
+ "0.520907, 0.741694, 0.919700, 1.208477, 1.768870",\
+ "0.670783, 0.891571, 1.069576, 1.358354, 1.918747",\
+ "1.043935, 1.264722, 1.442728, 1.731505, 2.291898",\
+ "0.529417, 0.741468, 0.919165, 1.207944, 1.768340",\
+ "0.555336, 0.767386, 0.945084, 1.233863, 1.794259",\
+ "0.609978, 0.822029, 0.999727, 1.288506, 1.848902",\
+ "0.759855, 0.971906, 1.149603, 1.438382, 1.998778",\
+ "1.133006, 1.345057, 1.522755, 1.811534, 2.371930",\
+ "0.592675, 0.799284, 0.976858, 1.265373, 1.825354",\
+ "0.618594, 0.825203, 1.002777, 1.291292, 1.851273",\
+ "0.673236, 0.879846, 1.057420, 1.345935, 1.905916",\
+ "0.823113, 1.029722, 1.207296, 1.495811, 2.055792",\
+ "1.196265, 1.402874, 1.580448, 1.868963, 2.428944",\
+ "0.925081, 1.104513, 1.280515, 1.568545, 2.127573",\
+ "0.951000, 1.130432, 1.306434, 1.594464, 2.153493",\
+ "1.005643, 1.185075, 1.361076, 1.649106, 2.208135",\
+ "1.155519, 1.334951, 1.510953, 1.798983, 2.358012",\
+ "1.528671, 1.708103, 1.884104, 2.172134, 2.731164");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011");
+ values ( "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\
+ "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\
+ "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\
+ "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\
+ "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122213, 1.122213, 1.122213, 1.122213, 1.122214");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2664*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[22]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.357049, 0.595251, 0.779226, 1.073282, 1.641542",\
+ "0.391318, 0.630694, 0.814727, 1.108794, 1.677077",\
+ "0.464801, 0.704176, 0.888210, 1.182277, 1.750560",\
+ "0.686019, 0.925396, 1.109429, 1.403496, 1.971779",\
+ "1.247822, 1.487198, 1.671232, 1.965299, 2.533582",\
+ "0.445388, 0.682569, 0.866506, 1.160588, 1.728896",\
+ "0.479656, 0.718012, 0.902008, 1.196099, 1.764431",\
+ "0.553139, 0.791495, 0.975491, 1.269582, 1.837914",\
+ "0.774358, 1.012714, 1.196710, 1.490801, 2.059132",\
+ "1.336161, 1.574517, 1.758512, 2.052604, 2.620935",\
+ "0.534519, 0.762902, 0.946533, 1.240616, 1.808927",\
+ "0.568788, 0.798345, 0.982035, 1.276128, 1.844462",\
+ "0.642270, 0.871828, 1.055518, 1.349610, 1.917945",\
+ "0.863489, 1.093047, 1.276737, 1.570829, 2.139164",\
+ "1.425292, 1.654850, 1.838539, 2.132632, 2.700967",\
+ "0.597943, 0.820727, 1.004241, 1.298055, 1.865961",\
+ "0.632211, 0.856174, 1.039743, 1.333567, 1.901497",\
+ "0.705694, 0.929657, 1.113225, 1.407049, 1.974979",\
+ "0.926913, 1.150876, 1.334444, 1.628268, 2.196198",\
+ "1.488716, 1.712679, 1.896247, 2.190071, 2.758001",\
+ "0.932941, 1.126006, 1.307899, 1.601235, 2.168205",\
+ "0.967209, 1.161484, 1.343401, 1.636746, 2.203741",\
+ "1.040692, 1.234967, 1.416883, 1.710229, 2.277223",\
+ "1.261911, 1.456186, 1.638102, 1.931448, 2.498442",\
+ "1.823713, 2.017988, 2.199905, 2.493251, 3.060245");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\
+ "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\
+ "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\
+ "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\
+ "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\
+ "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\
+ "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\
+ "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\
+ "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\
+ "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\
+ "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\
+ "2.131887, 2.131887, 2.131887, 2.131888, 2.131891");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.328195, 0.567571, 0.751605, 1.045671, 1.613954",\
+ "0.354114, 0.593490, 0.777524, 1.071590, 1.639874",\
+ "0.408757, 0.648133, 0.832166, 1.126233, 1.694516",\
+ "0.558634, 0.798009, 0.982043, 1.276110, 1.844393",\
+ "0.931785, 1.171161, 1.355194, 1.649261, 2.217544",\
+ "0.416534, 0.654889, 0.838885, 1.132977, 1.701308",\
+ "0.442453, 0.680808, 0.864804, 1.158895, 1.727227",\
+ "0.497095, 0.735451, 0.919447, 1.213538, 1.781870",\
+ "0.646972, 0.885328, 1.069324, 1.363415, 1.931746",\
+ "1.020123, 1.258479, 1.442475, 1.736566, 2.304898",\
+ "0.505665, 0.735223, 0.918912, 1.213005, 1.781339",\
+ "0.531584, 0.761142, 0.944831, 1.238924, 1.807259",\
+ "0.586226, 0.815784, 0.999474, 1.293567, 1.861901",\
+ "0.736103, 0.965661, 1.149351, 1.443443, 2.011778",\
+ "1.109254, 1.338812, 1.522502, 1.816595, 2.384929",\
+ "0.569089, 0.793052, 0.976620, 1.270444, 1.838374",\
+ "0.595008, 0.818971, 1.002539, 1.296363, 1.864293",\
+ "0.649650, 0.873613, 1.057182, 1.351006, 1.918935",\
+ "0.799527, 1.023490, 1.207058, 1.500882, 2.068812",\
+ "1.172678, 1.396641, 1.580210, 1.874034, 2.441963",\
+ "0.904086, 1.098361, 1.280278, 1.573624, 2.140618",\
+ "0.930005, 1.124280, 1.306197, 1.599543, 2.166537",\
+ "0.984648, 1.178923, 1.360839, 1.654185, 2.221179",\
+ "1.134525, 1.328800, 1.510716, 1.804062, 2.371056",\
+ "1.507676, 1.701951, 1.883868, 2.177213, 2.744207");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\
+ "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\
+ "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\
+ "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\
+ "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\
+ "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\
+ "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122212, 1.122212, 1.122212, 1.122213, 1.122215");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[31]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.439056, 0.659338, 0.836735, 1.125199, 1.685426",\
+ "0.473321, 0.693604, 0.871000, 1.159464, 1.719692",\
+ "0.546805, 0.767087, 0.944484, 1.232948, 1.793175",\
+ "0.768026, 0.988308, 1.165705, 1.454169, 2.014396",\
+ "1.329834, 1.550117, 1.727513, 2.015977, 2.576204",\
+ "0.527452, 0.746657, 0.924016, 1.212504, 1.772779",\
+ "0.561718, 0.780922, 0.958281, 1.246769, 1.807045",\
+ "0.635202, 0.854406, 1.031765, 1.320253, 1.880529",\
+ "0.856422, 1.075626, 1.252986, 1.541474, 2.101749",\
+ "1.418231, 1.637435, 1.814794, 2.103282, 2.663558",\
+ "0.616803, 0.826989, 1.004043, 1.292532, 1.852811",\
+ "0.651068, 0.861255, 1.038308, 1.326798, 1.887077",\
+ "0.724552, 0.934738, 1.111792, 1.400281, 1.960560",\
+ "0.945773, 1.155959, 1.333013, 1.621502, 2.181781",\
+ "1.507581, 1.717768, 1.894821, 2.183311, 2.743589",\
+ "0.680452, 0.884805, 1.061735, 1.349962, 1.909826",\
+ "0.714717, 0.919071, 1.096000, 1.384227, 1.944092",\
+ "0.788201, 0.992554, 1.169484, 1.457711, 2.017575",\
+ "1.009422, 1.213775, 1.390705, 1.678931, 2.238796",\
+ "1.571230, 1.775584, 1.952513, 2.240740, 2.800604",\
+ "1.011732, 1.190021, 1.365390, 1.653133, 2.212047",\
+ "1.045997, 1.224287, 1.399656, 1.687398, 2.246312",\
+ "1.119481, 1.297770, 1.473139, 1.760882, 2.319796",\
+ "1.340702, 1.518991, 1.694360, 1.982103, 2.541017",\
+ "1.902511, 2.080800, 2.256169, 2.543911, 3.102825");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\
+ "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\
+ "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\
+ "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\
+ "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.410231, 0.630513, 0.807909, 1.096372, 1.656599",\
+ "0.436125, 0.656408, 0.833804, 1.122268, 1.682495",\
+ "0.490769, 0.711051, 0.888448, 1.176911, 1.737139",\
+ "0.640645, 0.860927, 1.038324, 1.326787, 1.887015",\
+ "1.013797, 1.234079, 1.411476, 1.699939, 2.260167",\
+ "0.498627, 0.717831, 0.895190, 1.183677, 1.743952",\
+ "0.524522, 0.743726, 0.921085, 1.209573, 1.769848",\
+ "0.579165, 0.798369, 0.975729, 1.264216, 1.824492",\
+ "0.729041, 0.948246, 1.125605, 1.414093, 1.974368",\
+ "1.102193, 1.321398, 1.498757, 1.787244, 2.347520",\
+ "0.587977, 0.798164, 0.975217, 1.263706, 1.823984",\
+ "0.613872, 0.824059, 1.001112, 1.289602, 1.849880",\
+ "0.668516, 0.878702, 1.055755, 1.344245, 1.904523",\
+ "0.818392, 1.028578, 1.205631, 1.494121, 2.054400",\
+ "1.191543, 1.401730, 1.578784, 1.867273, 2.427552",\
+ "0.651626, 0.855980, 1.032909, 1.321135, 1.880999",\
+ "0.677521, 0.881875, 1.058804, 1.347031, 1.906895",\
+ "0.732164, 0.936518, 1.113448, 1.401674, 1.961538",\
+ "0.882041, 1.086394, 1.263324, 1.551550, 2.111415",\
+ "1.255192, 1.459546, 1.636476, 1.924702, 2.484566",\
+ "0.982907, 1.161196, 1.336565, 1.624306, 2.183219",\
+ "1.008801, 1.187091, 1.362460, 1.650202, 2.209116",\
+ "1.063445, 1.241734, 1.417103, 1.704845, 2.263759",\
+ "1.213321, 1.391610, 1.566979, 1.854722, 2.413635",\
+ "1.586473, 1.764762, 1.940131, 2.227873, 2.786787");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2417*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[33]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.416720, 0.653678, 0.840231, 1.138631, 1.715459",\
+ "0.450985, 0.687943, 0.874496, 1.172896, 1.749724",\
+ "0.524469, 0.761427, 0.947980, 1.246380, 1.823208",\
+ "0.745690, 0.982648, 1.169201, 1.467601, 2.044429",\
+ "1.307499, 1.544456, 1.731009, 2.029409, 2.606237",\
+ "0.505034, 0.740996, 0.927512, 1.225936, 1.802812",\
+ "0.539300, 0.775261, 0.961777, 1.260202, 1.837078",\
+ "0.612783, 0.848745, 1.035261, 1.333685, 1.910561",\
+ "0.834004, 1.069966, 1.256482, 1.554906, 2.131782",\
+ "1.395813, 1.631774, 1.818290, 2.116714, 2.693590",\
+ "0.594427, 0.821326, 1.007539, 1.305964, 1.882844",\
+ "0.628693, 0.855591, 1.041804, 1.340230, 1.917109",\
+ "0.702176, 0.929075, 1.115288, 1.413714, 1.990593",\
+ "0.923397, 1.150296, 1.336509, 1.634935, 2.211814",\
+ "1.485206, 1.712105, 1.898317, 2.196743, 2.773622",\
+ "0.658240, 0.879157, 1.065253, 1.363414, 1.939900",\
+ "0.692506, 0.913422, 1.099519, 1.397680, 1.974165",\
+ "0.765989, 0.986906, 1.173002, 1.471163, 2.047649",\
+ "0.987210, 1.208127, 1.394223, 1.692384, 2.268870",\
+ "1.549019, 1.769935, 1.956032, 2.254193, 2.830678",\
+ "0.995697, 1.184467, 1.368911, 1.666602, 2.242170",\
+ "1.029963, 1.218732, 1.403177, 1.700868, 2.276436",\
+ "1.103446, 1.292216, 1.476660, 1.774352, 2.349919",\
+ "1.324667, 1.513437, 1.697881, 1.995573, 2.571140",\
+ "1.886476, 2.075245, 2.259690, 2.557381, 3.132948");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\
+ "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\
+ "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\
+ "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\
+ "0.027424, 0.027425, 0.027425, 0.027426, 0.027428",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\
+ "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131895");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.387894, 0.624852, 0.811405, 1.109804, 1.686631",\
+ "0.413789, 0.650747, 0.837300, 1.135700, 1.712528",\
+ "0.468433, 0.705391, 0.891944, 1.190343, 1.767171",\
+ "0.618309, 0.855267, 1.041820, 1.340220, 1.917047",\
+ "0.991461, 1.228418, 1.414971, 1.713371, 2.290199",\
+ "0.476209, 0.712170, 0.898686, 1.197109, 1.773985",\
+ "0.502103, 0.738065, 0.924581, 1.223005, 1.799881",\
+ "0.556747, 0.792708, 0.979225, 1.277649, 1.854524",\
+ "0.706623, 0.942585, 1.129101, 1.427525, 2.004401",\
+ "1.079775, 1.315736, 1.502252, 1.800677, 2.377553",\
+ "0.565602, 0.792500, 0.978712, 1.277138, 1.854016",\
+ "0.591497, 0.818395, 1.004608, 1.303034, 1.879913",\
+ "0.646140, 0.873039, 1.059251, 1.357677, 1.934556",\
+ "0.796016, 1.022915, 1.209128, 1.507553, 2.084432",\
+ "1.169168, 1.396067, 1.582279, 1.880705, 2.457584",\
+ "0.629415, 0.850331, 1.036427, 1.334588, 1.911072",\
+ "0.655310, 0.876226, 1.062322, 1.360483, 1.936969",\
+ "0.709953, 0.930869, 1.116966, 1.415127, 1.991612",\
+ "0.859829, 1.080746, 1.266842, 1.565003, 2.141489",\
+ "1.232981, 1.453897, 1.639994, 1.938155, 2.514640",\
+ "0.966871, 1.155640, 1.340085, 1.637776, 2.213343",\
+ "0.992766, 1.181536, 1.365980, 1.663672, 2.239239",\
+ "1.047410, 1.236179, 1.420624, 1.718315, 2.293883",\
+ "1.197286, 1.386055, 1.570500, 1.868191, 2.443759",\
+ "1.570438, 1.759207, 1.943652, 2.241343, 2.816911");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015465, 0.015465, 0.015465, 0.015466, 0.015467",\
+ "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2525*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[35]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.317807, 0.553382, 0.743028, 1.048041, 1.638313",\
+ "0.360716, 0.596291, 0.785937, 1.090950, 1.681222",\
+ "0.437216, 0.672790, 0.862436, 1.167450, 1.757720",\
+ "0.660515, 0.896090, 1.085736, 1.390749, 1.981019",\
+ "1.219139, 1.454558, 1.644426, 1.949632, 2.540179",\
+ "0.406273, 0.640700, 0.830308, 1.135346, 1.725666",\
+ "0.449182, 0.683609, 0.873218, 1.178255, 1.768575",\
+ "0.525681, 0.760108, 0.949717, 1.254755, 1.845074",\
+ "0.748981, 0.983408, 1.173017, 1.478054, 2.068373",\
+ "1.307619, 1.541876, 1.731707, 2.036937, 2.627532",\
+ "0.495773, 0.721033, 0.910335, 1.215375, 1.805698",\
+ "0.538682, 0.763942, 0.953244, 1.258284, 1.848607",\
+ "0.615182, 0.840441, 1.029744, 1.334783, 1.925105",\
+ "0.838481, 1.063741, 1.253043, 1.558083, 2.148405",\
+ "1.397163, 1.622209, 1.811734, 2.116965, 2.707564",\
+ "0.559539, 0.778868, 0.968056, 1.272841, 1.862785",\
+ "0.602449, 0.821777, 1.010965, 1.315750, 1.905694",\
+ "0.678948, 0.898276, 1.087465, 1.392249, 1.982193",\
+ "0.902248, 1.121576, 1.310764, 1.615548, 2.205492",\
+ "1.460969, 1.680044, 1.869455, 2.174432, 2.764652",\
+ "0.896716, 1.084217, 1.271716, 1.576043, 2.165093",\
+ "0.939625, 1.127126, 1.314625, 1.618952, 2.208002",\
+ "1.016124, 1.203625, 1.391125, 1.695451, 2.284501",\
+ "1.239424, 1.426925, 1.614424, 1.918751, 2.507800",\
+ "1.798400, 1.985393, 2.173115, 2.477634, 3.066961");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\
+ "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\
+ "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\
+ "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\
+ "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\
+ "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\
+ "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\
+ "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\
+ "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\
+ "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\
+ "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\
+ "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\
+ "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\
+ "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\
+ "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\
+ "2.135110, 2.135110, 2.135110, 2.135111, 2.135114");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.305217, 0.540636, 0.730505, 1.035711, 1.626258",\
+ "0.334877, 0.570296, 0.760166, 1.065372, 1.655918",\
+ "0.386817, 0.622236, 0.812106, 1.117312, 1.707858",\
+ "0.535277, 0.770695, 0.960565, 1.265772, 1.856318",\
+ "0.899736, 1.135311, 1.324957, 1.629971, 2.220244",\
+ "0.393698, 0.627954, 0.817786, 1.123016, 1.713611",\
+ "0.423358, 0.657614, 0.847447, 1.152677, 1.743272",\
+ "0.475298, 0.709554, 0.899387, 1.204617, 1.795212",\
+ "0.623757, 0.858014, 1.047846, 1.353077, 1.943671",\
+ "0.988201, 1.222629, 1.412238, 1.717276, 2.307598",\
+ "0.483241, 0.708287, 0.897813, 1.203045, 1.793643",\
+ "0.512901, 0.737947, 0.927473, 1.232705, 1.823303",\
+ "0.564842, 0.789887, 0.979414, 1.284645, 1.875243",\
+ "0.713301, 0.938347, 1.127873, 1.433105, 2.023703",\
+ "1.077702, 1.302962, 1.492265, 1.797305, 2.387629",\
+ "0.547048, 0.766122, 0.955534, 1.260511, 1.850731",\
+ "0.576708, 0.795782, 0.985195, 1.290171, 1.880391",\
+ "0.628648, 0.847722, 1.037135, 1.342111, 1.932331",\
+ "0.777107, 0.996181, 1.185595, 1.490571, 2.080791",\
+ "1.141469, 1.360797, 1.549985, 1.854770, 2.444716",\
+ "0.884478, 1.071471, 1.259194, 1.563713, 2.153039",\
+ "0.914138, 1.101131, 1.288855, 1.593374, 2.182700",\
+ "0.966078, 1.153071, 1.340795, 1.645314, 2.234640",\
+ "1.114538, 1.301530, 1.489255, 1.793774, 2.383100",\
+ "1.478645, 1.666146, 1.853645, 2.157973, 2.747025");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011");
+ values ( "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\
+ "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\
+ "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\
+ "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\
+ "1.119158, 1.119160, 1.119160, 1.119170, 1.119193",\
+ "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\
+ "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\
+ "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\
+ "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\
+ "1.119158, 1.119160, 1.119160, 1.119170, 1.119193",\
+ "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\
+ "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\
+ "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\
+ "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\
+ "1.119158, 1.119160, 1.119160, 1.119170, 1.119193",\
+ "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\
+ "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\
+ "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\
+ "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\
+ "1.119159, 1.119160, 1.119160, 1.119170, 1.119193",\
+ "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\
+ "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\
+ "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\
+ "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\
+ "1.119160, 1.119160, 1.119160, 1.119170, 1.119193");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2639*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[36]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.385015, 0.606699, 0.784745, 1.073680, 1.634527",\
+ "0.435014, 0.656698, 0.834744, 1.123679, 1.684526",\
+ "0.515571, 0.737187, 0.915297, 1.204231, 1.765078",\
+ "0.736804, 0.958420, 1.136530, 1.425464, 1.986311",\
+ "1.298648, 1.520264, 1.698375, 1.987309, 2.548156",\
+ "0.473424, 0.694018, 0.872026, 1.160985, 1.721881",\
+ "0.523423, 0.744017, 0.922025, 1.210984, 1.771880",\
+ "0.603979, 0.824505, 1.002578, 1.291536, 1.852431",\
+ "0.825212, 1.045738, 1.223811, 1.512769, 2.073665",\
+ "1.387057, 1.607583, 1.785656, 2.074614, 2.635510",\
+ "0.562514, 0.774353, 0.952053, 1.241014, 1.801912",\
+ "0.612513, 0.824352, 1.002052, 1.291013, 1.851911",\
+ "0.693070, 0.904840, 1.082605, 1.371564, 1.932463",\
+ "0.914303, 1.126073, 1.303838, 1.592798, 2.153697",\
+ "1.476147, 1.687918, 1.865683, 2.154643, 2.715541",\
+ "0.625792, 0.832174, 1.009746, 1.298444, 1.858928",\
+ "0.675791, 0.882173, 1.059745, 1.348443, 1.908927",\
+ "0.756348, 0.962666, 1.140298, 1.428994, 1.989478",\
+ "0.977581, 1.183899, 1.361531, 1.650227, 2.210711",\
+ "1.539425, 1.745744, 1.923376, 2.212072, 2.772557",\
+ "0.956955, 1.137434, 1.313402, 1.601616, 2.161149",\
+ "1.006954, 1.187433, 1.363401, 1.651615, 2.211148",\
+ "1.086373, 1.267959, 1.443954, 1.732166, 2.291699",\
+ "1.307606, 1.489192, 1.665187, 1.953399, 2.512933",\
+ "1.869451, 2.051037, 2.227032, 2.515244, 3.074778");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\
+ "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\
+ "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\
+ "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\
+ "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.379185, 0.600800, 0.778912, 1.067847, 1.628695",\
+ "0.404931, 0.626547, 0.804658, 1.093592, 1.654439",\
+ "0.459580, 0.681196, 0.859307, 1.148241, 1.709088",\
+ "0.609453, 0.831069, 1.009180, 1.298114, 1.858961",\
+ "0.965195, 1.186879, 1.364924, 1.653859, 2.214706",\
+ "0.467593, 0.688119, 0.866193, 1.155152, 1.716048",\
+ "0.493340, 0.713866, 0.891939, 1.180897, 1.741792",\
+ "0.547989, 0.768515, 0.946587, 1.235546, 1.796441",\
+ "0.697862, 0.918388, 1.096461, 1.385419, 1.946315",\
+ "1.053603, 1.274197, 1.452205, 1.741164, 2.302060",\
+ "0.556683, 0.768454, 0.946220, 1.235180, 1.796080",\
+ "0.582430, 0.794201, 0.971965, 1.260925, 1.821824",\
+ "0.637079, 0.848850, 1.026614, 1.315574, 1.876473",\
+ "0.786952, 0.998723, 1.176488, 1.465447, 2.026346",\
+ "1.142694, 1.354532, 1.532232, 1.821193, 2.382091",\
+ "0.619961, 0.826280, 1.003913, 1.292610, 1.853095",\
+ "0.645708, 0.852026, 1.029659, 1.318355, 1.878839",\
+ "0.700357, 0.906675, 1.084307, 1.373004, 1.933488",\
+ "0.850230, 1.056549, 1.234181, 1.522877, 2.083362",\
+ "1.205971, 1.412353, 1.589925, 1.878623, 2.439106",\
+ "0.949987, 1.131573, 1.307569, 1.595782, 2.155316",\
+ "0.975733, 1.157320, 1.333315, 1.621527, 2.181061",\
+ "1.030382, 1.211969, 1.387964, 1.676176, 2.235709",\
+ "1.180256, 1.361842, 1.537837, 1.826049, 2.385583",\
+ "1.537134, 1.717614, 1.893581, 2.181795, 2.741328");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\
+ "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\
+ "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\
+ "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\
+ "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\
+ "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\
+ "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\
+ "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\
+ "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\
+ "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2690*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[37]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.362229, 0.589916, 0.774631, 1.069784, 1.640082",\
+ "0.412228, 0.639915, 0.824630, 1.119783, 1.690081",\
+ "0.492795, 0.719167, 0.903893, 1.199092, 1.769493",\
+ "0.714028, 0.940400, 1.125127, 1.420325, 1.990727",\
+ "1.275872, 1.502245, 1.686972, 1.982170, 2.552572",\
+ "0.450567, 0.677234, 0.861912, 1.157089, 1.727435",\
+ "0.500567, 0.727233, 0.911911, 1.207088, 1.777434",\
+ "0.581133, 0.806485, 0.991174, 1.286397, 1.856847",\
+ "0.802366, 1.027718, 1.212408, 1.507630, 2.078080",\
+ "1.364210, 1.589563, 1.774253, 2.069476, 2.639925",\
+ "0.539804, 0.757567, 0.941939, 1.237118, 1.807467",\
+ "0.589803, 0.807566, 0.991938, 1.287117, 1.857466",\
+ "0.670367, 0.886817, 1.071201, 1.366425, 1.936878",\
+ "0.891600, 1.108051, 1.292434, 1.587659, 2.158112",\
+ "1.453444, 1.669896, 1.854280, 2.149504, 2.719957",\
+ "0.603371, 0.815390, 0.999649, 1.294559, 1.864506",\
+ "0.653370, 0.865389, 1.049648, 1.344558, 1.914505",\
+ "0.733934, 0.944641, 1.128911, 1.423867, 1.993918",\
+ "0.955166, 1.165874, 1.350144, 1.645100, 2.215151",\
+ "1.517011, 1.727719, 1.911989, 2.206946, 2.776997",\
+ "0.939278, 1.120654, 1.303307, 1.597741, 2.166757",\
+ "0.989277, 1.170653, 1.353306, 1.647740, 2.216756",\
+ "1.069831, 1.249906, 1.432569, 1.727049, 2.296169",\
+ "1.291064, 1.471139, 1.653802, 1.948282, 2.517402",\
+ "1.852909, 2.032984, 2.215647, 2.510128, 3.079247");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.027448, 0.027445, 0.027445, 0.027445, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\
+ "0.027448, 0.027445, 0.027445, 0.027445, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\
+ "0.027447, 0.027445, 0.027445, 0.027445, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\
+ "0.027447, 0.027445, 0.027445, 0.027445, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\
+ "0.027446, 0.027445, 0.027445, 0.027445, 0.027445",\
+ "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\
+ "2.131897, 2.131897, 2.131897, 2.131897, 2.131897");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.356406, 0.582783, 0.767510, 1.062709, 1.633111",\
+ "0.382155, 0.608528, 0.793254, 1.088453, 1.658855",\
+ "0.436803, 0.663177, 0.847903, 1.143102, 1.713504",\
+ "0.586677, 0.813050, 0.997777, 1.292975, 1.863377",\
+ "0.942409, 1.170095, 1.354810, 1.649963, 2.220260",\
+ "0.444744, 0.670102, 0.854791, 1.150014, 1.720465",\
+ "0.470493, 0.695846, 0.880535, 1.175758, 1.746208",\
+ "0.525141, 0.750495, 0.935184, 1.230407, 1.800857",\
+ "0.675015, 0.900368, 1.085058, 1.380280, 1.950730",\
+ "1.030747, 1.257413, 1.442091, 1.737268, 2.307614",\
+ "0.533979, 0.750434, 0.934818, 1.230043, 1.800496",\
+ "0.559727, 0.776178, 0.960562, 1.255787, 1.826240",\
+ "0.614376, 0.830827, 1.015211, 1.310436, 1.880889",\
+ "0.764250, 0.980701, 1.165085, 1.460309, 2.030762",\
+ "1.119983, 1.337745, 1.522118, 1.817296, 2.387645",\
+ "0.597545, 0.808257, 0.992528, 1.287485, 1.857536",\
+ "0.623294, 0.834002, 1.018272, 1.313228, 1.883280",\
+ "0.677942, 0.888651, 1.072921, 1.367877, 1.937928",\
+ "0.827816, 1.038524, 1.222794, 1.517751, 2.087802",\
+ "1.183551, 1.395569, 1.579828, 1.874738, 2.444685",\
+ "0.933445, 1.113522, 1.296186, 1.590666, 2.159787",\
+ "0.959191, 1.139267, 1.321930, 1.616410, 2.185530",\
+ "1.013840, 1.193916, 1.376579, 1.671059, 2.240179",\
+ "1.163714, 1.343789, 1.526452, 1.820932, 2.390052",\
+ "1.519457, 1.700833, 1.883486, 2.177920, 2.746935");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.015179, 0.015170, 0.015169, 0.015169, 0.015168",\
+ "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\
+ "0.015179, 0.015170, 0.015169, 0.015169, 0.015168",\
+ "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\
+ "0.015178, 0.015170, 0.015169, 0.015169, 0.015168",\
+ "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\
+ "0.015177, 0.015170, 0.015169, 0.015169, 0.015168",\
+ "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\
+ "0.015173, 0.015170, 0.015169, 0.015169, 0.015168",\
+ "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\
+ "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122219, 1.122219, 1.122219, 1.122219, 1.122219");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2258*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[39]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.309159, 0.541794, 0.727047, 1.026481, 1.606878",\
+ "0.349227, 0.581863, 0.767115, 1.066549, 1.646947",\
+ "0.425113, 0.657750, 0.843001, 1.142434, 1.722832",\
+ "0.644749, 0.877387, 1.062637, 1.362070, 1.942469",\
+ "1.197363, 1.430001, 1.615251, 1.914684, 2.495083",\
+ "0.397555, 0.629112, 0.814328, 1.113786, 1.694232",\
+ "0.437623, 0.669181, 0.854396, 1.153854, 1.734300",\
+ "0.513508, 0.745068, 0.930282, 1.229739, 1.810186",\
+ "0.733145, 0.964705, 1.149918, 1.449375, 2.029822",\
+ "1.285759, 1.517319, 1.702532, 2.001989, 2.582437",\
+ "0.486858, 0.709445, 0.894355, 1.193814, 1.774263",\
+ "0.526927, 0.749514, 0.934423, 1.233882, 1.814332",\
+ "0.602812, 0.825401, 1.010309, 1.309767, 1.890217",\
+ "0.822449, 1.045038, 1.229945, 1.529404, 2.109854",\
+ "1.375063, 1.597652, 1.782559, 2.082017, 2.662468",\
+ "0.550445, 0.767276, 0.952066, 1.251268, 1.831326",\
+ "0.590513, 0.807345, 0.992134, 1.291336, 1.871395",\
+ "0.666399, 0.883232, 1.068019, 1.367221, 1.947281",\
+ "0.886036, 1.102869, 1.287656, 1.586857, 2.166918",\
+ "1.438650, 1.655483, 1.840269, 2.139471, 2.719532",\
+ "0.886476, 1.072598, 1.255724, 1.554460, 2.133606",\
+ "0.926545, 1.112668, 1.295792, 1.594528, 2.173675",\
+ "1.002432, 1.188554, 1.371677, 1.670413, 2.249560",\
+ "1.222068, 1.408191, 1.591314, 1.890050, 2.469197",\
+ "1.774683, 1.960806, 2.143928, 2.442663, 3.021811");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\
+ "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\
+ "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\
+ "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\
+ "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\
+ "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\
+ "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\
+ "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\
+ "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\
+ "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\
+ "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\
+ "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\
+ "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\
+ "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\
+ "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\
+ "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\
+ "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\
+ "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\
+ "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\
+ "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\
+ "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\
+ "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\
+ "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\
+ "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\
+ "2.135299, 2.135299, 2.135299, 2.135304, 2.135317");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.283419, 0.516054, 0.701307, 1.000741, 1.581138",\
+ "0.313066, 0.545699, 0.730954, 1.030388, 1.610784",\
+ "0.365001, 0.597634, 0.782889, 1.082323, 1.662719",\
+ "0.513456, 0.746088, 0.931344, 1.230778, 1.811174",\
+ "0.885857, 1.118488, 1.303746, 1.603180, 2.183575",\
+ "0.371815, 0.603373, 0.788588, 1.088046, 1.668492",\
+ "0.401461, 0.633018, 0.818235, 1.117693, 1.698138",\
+ "0.453396, 0.684952, 0.870170, 1.169628, 1.750072",\
+ "0.601851, 0.833406, 1.018625, 1.318083, 1.898527",\
+ "0.974253, 1.205806, 1.391027, 1.690485, 2.270928",\
+ "0.461119, 0.683706, 0.868615, 1.168074, 1.748523",\
+ "0.490765, 0.713351, 0.898262, 1.197721, 1.778169",\
+ "0.542700, 0.765285, 0.950197, 1.249656, 1.830104",\
+ "0.691155, 0.913739, 1.098652, 1.398111, 1.978559",\
+ "1.063556, 1.286139, 1.471054, 1.770513, 2.350960",\
+ "0.524705, 0.741537, 0.926326, 1.225528, 1.805587",\
+ "0.554351, 0.771182, 0.955972, 1.255175, 1.835233",\
+ "0.606286, 0.823116, 1.007907, 1.307110, 1.887167",\
+ "0.754741, 0.971570, 1.156362, 1.455565, 2.035622",\
+ "1.127142, 1.343970, 1.528764, 1.827967, 2.408023",\
+ "0.860737, 1.046859, 1.229984, 1.528720, 2.107866",\
+ "0.890382, 1.076504, 1.259631, 1.558367, 2.137512",\
+ "0.942317, 1.128438, 1.311566, 1.610302, 2.189447",\
+ "1.090771, 1.276893, 1.460021, 1.758757, 2.337902",\
+ "1.463172, 1.649293, 1.832423, 2.131159, 2.710303");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011");
+ values ( "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\
+ "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\
+ "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\
+ "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\
+ "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\
+ "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\
+ "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\
+ "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\
+ "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\
+ "1.119113, 1.119113, 1.119113, 1.119121, 1.119143");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2336*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[41]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.409726, 0.620265, 0.806005, 1.096897, 1.655910",\
+ "0.459725, 0.670264, 0.856003, 1.146896, 1.705909",\
+ "0.539627, 0.750535, 0.935997, 1.226788, 1.785793",\
+ "0.760860, 0.971768, 1.157229, 1.448020, 2.007025",\
+ "1.322703, 1.533611, 1.719072, 2.009862, 2.568867",\
+ "0.498079, 0.707583, 0.893286, 1.184203, 1.743264",\
+ "0.548078, 0.757582, 0.943284, 1.234201, 1.793262",\
+ "0.627981, 0.837853, 1.023278, 1.314093, 1.873147",\
+ "0.849213, 1.059086, 1.244510, 1.535325, 2.094379",\
+ "1.411056, 1.620929, 1.806353, 2.097167, 2.656221",\
+ "0.587342, 0.787916, 0.973312, 1.264231, 1.823296",\
+ "0.637340, 0.837914, 1.023311, 1.314230, 1.873294",\
+ "0.717243, 0.918186, 1.103305, 1.394121, 1.953178",\
+ "0.938476, 1.139418, 1.324537, 1.615354, 2.174411",\
+ "1.500319, 1.701261, 1.886380, 2.177196, 2.736252",\
+ "0.650926, 0.845743, 1.031024, 1.321659, 1.880308",\
+ "0.700925, 0.895741, 1.081023, 1.371658, 1.930306",\
+ "0.780828, 0.976013, 1.161016, 1.451549, 2.010190",\
+ "1.002060, 1.197245, 1.382248, 1.672781, 2.231423",\
+ "1.563903, 1.759089, 1.944091, 2.234624, 2.793264",\
+ "0.970227, 1.151036, 1.334683, 1.624829, 2.182525",\
+ "1.020226, 1.201034, 1.384681, 1.674827, 2.232523",\
+ "1.100497, 1.281306, 1.464674, 1.754719, 2.312408",\
+ "1.321730, 1.502538, 1.685907, 1.975951, 2.533640",\
+ "1.883573, 2.064381, 2.247749, 2.537794, 3.095482");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\
+ "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\
+ "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\
+ "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\
+ "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.403233, 0.614141, 0.799601, 1.090390, 1.649393",\
+ "0.428986, 0.639894, 0.825355, 1.116146, 1.675151",\
+ "0.483635, 0.694543, 0.880004, 1.170794, 1.729799",\
+ "0.633508, 0.844416, 1.029877, 1.320668, 1.879673",\
+ "0.989900, 1.200439, 1.386178, 1.677071, 2.236084",\
+ "0.491587, 0.701459, 0.886882, 1.177695, 1.736746",\
+ "0.517340, 0.727212, 0.912636, 1.203451, 1.762504",\
+ "0.571988, 0.781861, 0.967285, 1.258099, 1.817153",\
+ "0.721862, 0.931734, 1.117158, 1.407973, 1.967026",\
+ "1.078253, 1.287757, 1.473459, 1.764376, 2.323438",\
+ "0.580849, 0.781792, 0.966909, 1.257724, 1.816778",\
+ "0.606602, 0.807544, 0.992663, 1.283479, 1.842536",\
+ "0.661251, 0.862193, 1.047312, 1.338128, 1.897184",\
+ "0.811124, 1.012067, 1.197185, 1.488001, 2.047058",\
+ "1.167515, 1.368089, 1.553486, 1.844405, 2.403470",\
+ "0.644433, 0.839619, 1.024620, 1.315152, 1.873790",\
+ "0.670186, 0.865372, 1.050374, 1.340907, 1.899548",\
+ "0.724835, 0.920020, 1.105023, 1.395556, 1.954196",\
+ "0.874709, 1.069894, 1.254896, 1.545429, 2.104070",\
+ "1.231100, 1.425916, 1.611198, 1.901833, 2.460482",\
+ "0.964103, 1.144912, 1.328278, 1.618321, 2.176007",\
+ "0.989856, 1.170664, 1.354033, 1.644077, 2.201765",\
+ "1.044504, 1.225313, 1.408681, 1.698726, 2.256414",\
+ "1.194378, 1.375186, 1.558555, 1.848599, 2.406287",\
+ "1.550400, 1.731209, 1.914856, 2.205003, 2.762699");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\
+ "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\
+ "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\
+ "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\
+ "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\
+ "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2358*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[42]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.383225, 0.593036, 0.770038, 1.054268, 1.604513",\
+ "0.433223, 0.643035, 0.820037, 1.104266, 1.654512",\
+ "0.513146, 0.723307, 0.900324, 1.184595, 1.734933",\
+ "0.734379, 0.944539, 1.121556, 1.405827, 1.956165",\
+ "1.296223, 1.506382, 1.683399, 1.967670, 2.518007",\
+ "0.471502, 0.680354, 0.857319, 1.141573, 1.691867",\
+ "0.521500, 0.730353, 0.907318, 1.191571, 1.741865",\
+ "0.601422, 0.810625, 0.987605, 1.271900, 1.822286",\
+ "0.822655, 1.031858, 1.208837, 1.493132, 2.043518",\
+ "1.384499, 1.593700, 1.770680, 2.054975, 2.605360",\
+ "0.560557, 0.760687, 0.937346, 1.221601, 1.771898",\
+ "0.610556, 0.810685, 0.987345, 1.271600, 1.821897",\
+ "0.690474, 0.890957, 1.067632, 1.351929, 1.902318",\
+ "0.911707, 1.112190, 1.288864, 1.573161, 2.123550",\
+ "1.473551, 1.674033, 1.850707, 2.135003, 2.685391",\
+ "0.623957, 0.818509, 0.995037, 1.279018, 1.828889",\
+ "0.673955, 0.868507, 1.045036, 1.329017, 1.878888",\
+ "0.753870, 0.948779, 1.125323, 1.409346, 1.959309",\
+ "0.975103, 1.170012, 1.346555, 1.630578, 2.180541",\
+ "1.536947, 1.731855, 1.908398, 2.192420, 2.742383",\
+ "0.944232, 1.123764, 1.298692, 1.582179, 2.131082",\
+ "0.994231, 1.173763, 1.348691, 1.632178, 2.181080",\
+ "1.074451, 1.254037, 1.428978, 1.712507, 2.261501",\
+ "1.295684, 1.475269, 1.650211, 1.933739, 2.482733",\
+ "1.857528, 2.037112, 2.212053, 2.495582, 3.044575");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.027427, 0.027429, 0.027430, 0.027431, 0.027432",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\
+ "0.027427, 0.027429, 0.027430, 0.027431, 0.027432",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\
+ "0.027428, 0.027429, 0.027430, 0.027431, 0.027432",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\
+ "0.027428, 0.027429, 0.027430, 0.027431, 0.027432",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\
+ "0.027428, 0.027429, 0.027430, 0.027431, 0.027432",\
+ "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\
+ "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\
+ "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\
+ "2.131895, 2.131895, 2.131895, 2.131895, 2.131896");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.376757, 0.586911, 0.763927, 1.048197, 1.598532",\
+ "0.402506, 0.612665, 0.789682, 1.073953, 1.624290",\
+ "0.457155, 0.667314, 0.844331, 1.128602, 1.678938",\
+ "0.607028, 0.817188, 0.994204, 1.278475, 1.828812",\
+ "0.963398, 1.173210, 1.350212, 1.634442, 2.184688",\
+ "0.465033, 0.674229, 0.851208, 1.135502, 1.685885",\
+ "0.490782, 0.699983, 0.876963, 1.161258, 1.711643",\
+ "0.545431, 0.754632, 0.931612, 1.215907, 1.766292",\
+ "0.695304, 0.904506, 1.081485, 1.365780, 1.916165",\
+ "1.051675, 1.260528, 1.437493, 1.721747, 2.272042",\
+ "0.554085, 0.754561, 0.931235, 1.215531, 1.765917",\
+ "0.579834, 0.780316, 0.956990, 1.241287, 1.791675",\
+ "0.634483, 0.834964, 1.011639, 1.295935, 1.846323",\
+ "0.784356, 0.984838, 1.161512, 1.445809, 1.996197",\
+ "1.140731, 1.340860, 1.517520, 1.801775, 2.352073",\
+ "0.617480, 0.812384, 0.988926, 1.272948, 1.822908",\
+ "0.643230, 0.838138, 1.014681, 1.298704, 1.848666",\
+ "0.697878, 0.892787, 1.069330, 1.353353, 1.903315",\
+ "0.847752, 1.042660, 1.219203, 1.503226, 2.053188",\
+ "1.204130, 1.398682, 1.575211, 1.859193, 2.409064",\
+ "0.938061, 1.117640, 1.292582, 1.576109, 2.125101",\
+ "0.963811, 1.143395, 1.318336, 1.601865, 2.150858",\
+ "1.018459, 1.198044, 1.372985, 1.656513, 2.205507",\
+ "1.168333, 1.347917, 1.522858, 1.806387, 2.355381",\
+ "1.524406, 1.703938, 1.878866, 2.162354, 2.711256");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.015179, 0.015189, 0.015191, 0.015192, 0.015197",\
+ "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015179, 0.015189, 0.015191, 0.015192, 0.015197",\
+ "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015180, 0.015189, 0.015191, 0.015192, 0.015197",\
+ "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015181, 0.015190, 0.015191, 0.015192, 0.015197",\
+ "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\
+ "0.015181, 0.015190, 0.015191, 0.015192, 0.015197",\
+ "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\
+ "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\
+ "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\
+ "1.122218, 1.122218, 1.122218, 1.122218, 1.122218");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2303*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[43]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.405550, 0.622555, 0.800684, 1.089918, 1.651394",\
+ "0.445619, 0.662624, 0.840753, 1.129987, 1.691463",\
+ "0.521505, 0.738510, 0.916639, 1.205873, 1.767349",\
+ "0.741141, 0.958147, 1.136276, 1.425510, 1.986986",\
+ "1.293756, 1.510761, 1.688890, 1.978124, 2.539600",\
+ "0.493926, 0.709873, 0.887965, 1.177224, 1.738747",\
+ "0.533995, 0.749942, 0.928034, 1.217292, 1.778816",\
+ "0.609881, 0.825828, 1.003920, 1.293178, 1.854702",\
+ "0.829518, 1.045465, 1.223557, 1.512815, 2.074339",\
+ "1.382132, 1.598079, 1.776171, 2.065429, 2.626953",\
+ "0.583177, 0.790206, 0.967992, 1.257252, 1.818779",\
+ "0.623246, 0.830275, 1.008061, 1.297321, 1.858848",\
+ "0.699132, 0.906161, 1.083947, 1.373207, 1.934734",\
+ "0.918768, 1.125798, 1.303584, 1.592844, 2.154371",\
+ "1.471382, 1.678412, 1.856198, 2.145458, 2.706985",\
+ "0.646716, 0.848023, 1.025686, 1.314683, 1.875797",\
+ "0.686785, 0.888092, 1.065755, 1.354752, 1.915866",\
+ "0.762671, 0.963978, 1.141641, 1.430638, 1.991752",\
+ "0.982307, 1.183615, 1.361278, 1.650275, 2.211389",\
+ "1.534921, 1.736229, 1.913892, 2.202889, 2.764003",\
+ "0.974642, 1.153245, 1.329341, 1.617855, 2.178021",\
+ "1.014711, 1.193314, 1.369410, 1.657924, 2.218090",\
+ "1.090597, 1.269200, 1.445296, 1.733810, 2.293976",\
+ "1.310234, 1.488837, 1.664933, 1.953447, 2.513613",\
+ "1.862848, 2.041451, 2.217547, 2.506061, 3.066227");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\
+ "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\
+ "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\
+ "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\
+ "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\
+ "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\
+ "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\
+ "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\
+ "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\
+ "2.135322, 2.135322, 2.135323, 2.135323, 2.135323");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.379810, 0.596815, 0.774944, 1.064179, 1.625654",\
+ "0.409456, 0.626461, 0.804590, 1.093824, 1.655300",\
+ "0.461390, 0.678396, 0.856524, 1.145759, 1.707235",\
+ "0.609845, 0.826850, 1.004979, 1.294214, 1.855689",\
+ "0.982246, 1.199251, 1.377380, 1.666614, 2.228090",\
+ "0.468186, 0.684134, 0.862225, 1.151484, 1.713008",\
+ "0.497832, 0.713779, 0.891871, 1.181129, 1.742653",\
+ "0.549766, 0.765714, 0.943805, 1.233064, 1.794588",\
+ "0.698221, 0.914169, 1.092260, 1.381519, 1.943043",\
+ "1.070622, 1.286569, 1.464661, 1.753919, 2.315443",\
+ "0.557437, 0.764467, 0.942252, 1.231513, 1.793039",\
+ "0.587083, 0.794112, 0.971898, 1.261158, 1.822685",\
+ "0.639017, 0.846047, 1.023832, 1.313093, 1.874619",\
+ "0.787472, 0.994502, 1.172287, 1.461547, 2.023074",\
+ "1.159873, 1.366902, 1.544688, 1.833948, 2.395475",\
+ "0.620976, 0.822284, 0.999946, 1.288943, 1.850057",\
+ "0.650622, 0.851929, 1.029592, 1.318589, 1.879703",\
+ "0.702556, 0.903864, 1.081526, 1.370523, 1.931637",\
+ "0.851011, 1.052318, 1.229981, 1.518978, 2.080092",\
+ "1.223412, 1.424719, 1.602382, 1.891379, 2.452493",\
+ "0.948902, 1.127506, 1.303602, 1.592116, 2.152281",\
+ "0.978548, 1.157151, 1.333247, 1.621761, 2.181927",\
+ "1.030483, 1.209086, 1.385182, 1.673696, 2.233861",\
+ "1.178937, 1.357541, 1.533637, 1.822151, 2.382316",\
+ "1.551338, 1.729941, 1.906037, 2.194551, 2.754717");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011");
+ values ( "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\
+ "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\
+ "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\
+ "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\
+ "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\
+ "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\
+ "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\
+ "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\
+ "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\
+ "1.119108, 1.119108, 1.119109, 1.119113, 1.119123");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2271*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[44]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.386364, 0.626816, 0.817125, 1.119925, 1.704580",\
+ "0.426433, 0.666885, 0.857194, 1.159994, 1.744649",\
+ "0.502319, 0.742771, 0.933080, 1.235880, 1.820535",\
+ "0.721956, 0.962408, 1.152717, 1.455517, 2.040172",\
+ "1.274570, 1.515022, 1.705331, 2.008131, 2.592786",\
+ "0.474664, 0.714134, 0.904406, 1.207230, 1.791934",\
+ "0.514733, 0.754203, 0.944475, 1.247299, 1.832002",\
+ "0.590619, 0.830089, 1.020361, 1.323185, 1.907888",\
+ "0.810256, 1.049726, 1.239998, 1.542822, 2.127525",\
+ "1.362870, 1.602340, 1.792612, 2.095436, 2.680139",\
+ "0.563948, 0.794465, 0.984433, 1.287259, 1.871965",\
+ "0.604017, 0.834534, 1.024502, 1.327327, 1.912034",\
+ "0.679903, 0.910420, 1.100388, 1.403213, 1.987920",\
+ "0.899539, 1.130056, 1.320024, 1.622850, 2.207557",\
+ "1.452153, 1.682670, 1.872638, 2.175464, 2.760171",\
+ "0.627629, 0.852329, 1.042155, 1.344718, 1.929040",\
+ "0.667698, 0.892398, 1.082224, 1.384787, 1.969109",\
+ "0.743584, 0.968284, 1.158110, 1.460673, 2.044995",\
+ "0.963221, 1.187921, 1.377747, 1.680310, 2.264632",\
+ "1.515835, 1.740535, 1.930361, 2.232924, 2.817246",\
+ "0.964253, 1.157875, 1.345814, 1.647914, 2.231333",\
+ "1.004322, 1.197944, 1.385883, 1.687983, 2.271402",\
+ "1.080208, 1.273830, 1.461769, 1.763869, 2.347288",\
+ "1.299845, 1.493467, 1.681406, 1.983506, 2.566925",\
+ "1.852459, 2.046081, 2.234020, 2.536120, 3.119539");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\
+ "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\
+ "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\
+ "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\
+ "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\
+ "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\
+ "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\
+ "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\
+ "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\
+ "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\
+ "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\
+ "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\
+ "2.135323, 2.135323, 2.135323, 2.135323, 2.135323");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.360625, 0.601076, 0.791385, 1.094185, 1.678841",\
+ "0.390270, 0.630722, 0.821031, 1.123831, 1.708486",\
+ "0.442205, 0.682656, 0.872965, 1.175765, 1.760421",\
+ "0.590660, 0.831111, 1.021420, 1.324220, 1.908875",\
+ "0.963060, 1.203512, 1.393821, 1.696621, 2.281276",\
+ "0.448924, 0.688394, 0.878666, 1.181490, 1.766194",\
+ "0.478570, 0.718040, 0.908312, 1.211136, 1.795840",\
+ "0.530504, 0.769974, 0.960246, 1.263070, 1.847774",\
+ "0.678959, 0.918429, 1.108701, 1.411525, 1.996229",\
+ "1.051360, 1.290830, 1.481102, 1.783926, 2.368629",\
+ "0.538208, 0.768725, 0.958693, 1.261519, 1.846226",\
+ "0.567854, 0.798371, 0.988339, 1.291164, 1.875871",\
+ "0.619788, 0.850305, 1.040273, 1.343099, 1.927806",\
+ "0.768243, 0.998760, 1.188728, 1.491554, 2.076260",\
+ "1.140644, 1.371161, 1.561129, 1.863954, 2.448661",\
+ "0.601890, 0.826589, 1.016415, 1.318978, 1.903300",\
+ "0.631535, 0.856235, 1.046061, 1.348624, 1.932946",\
+ "0.683470, 0.908169, 1.097996, 1.400558, 1.984880",\
+ "0.831925, 1.056624, 1.246450, 1.549013, 2.133335",\
+ "1.204325, 1.429025, 1.618851, 1.921414, 2.505736",\
+ "0.938514, 1.132136, 1.320075, 1.622174, 2.205594",\
+ "0.968159, 1.161781, 1.349720, 1.651820, 2.235239",\
+ "1.020094, 1.213716, 1.401655, 1.703755, 2.287174",\
+ "1.168548, 1.362170, 1.550110, 1.852209, 2.435628",\
+ "1.540949, 1.734571, 1.922510, 2.224610, 2.808029");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011");
+ values ( "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\
+ "1.119107, 1.119112, 1.119115, 1.119119, 1.119125",\
+ "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\
+ "1.119107, 1.119112, 1.119115, 1.119119, 1.119125",\
+ "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\
+ "1.119108, 1.119112, 1.119115, 1.119119, 1.119125",\
+ "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\
+ "1.119108, 1.119112, 1.119115, 1.119119, 1.119125",\
+ "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\
+ "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\
+ "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\
+ "0.439545, 0.439546, 0.439547, 0.439548, 0.439550",\
+ "1.119111, 1.119112, 1.119115, 1.119119, 1.119125");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2441*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[46]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.401355, 0.623039, 0.801084, 1.090019, 1.650864",\
+ "0.444265, 0.665948, 0.843993, 1.132928, 1.693773",\
+ "0.520764, 0.742448, 0.920493, 1.209427, 1.770273",\
+ "0.744064, 0.965747, 1.143793, 1.432727, 1.993572",\
+ "1.303239, 1.524854, 1.702965, 1.991765, 2.552283",\
+ "0.489764, 0.710357, 0.888365, 1.177324, 1.738218",\
+ "0.532673, 0.753266, 0.931274, 1.220233, 1.781127",\
+ "0.609173, 0.829766, 1.007774, 1.296732, 1.857626",\
+ "0.832472, 1.053066, 1.231073, 1.520032, 2.080926",\
+ "1.391647, 1.612173, 1.790246, 2.079070, 2.639636",\
+ "0.578854, 0.790693, 0.968392, 1.257352, 1.818249",\
+ "0.621763, 0.833602, 1.011301, 1.300261, 1.861158",\
+ "0.698263, 0.910101, 1.087801, 1.376761, 1.937658",\
+ "0.921562, 1.133401, 1.311100, 1.600060, 2.160957",\
+ "1.480738, 1.692508, 1.870273, 2.159099, 2.719668",\
+ "0.642132, 0.848514, 1.026085, 1.314782, 1.875265",\
+ "0.685041, 0.891423, 1.068994, 1.357691, 1.918174",\
+ "0.761541, 0.967922, 1.145494, 1.434191, 1.994673",\
+ "0.984840, 1.191222, 1.368793, 1.657490, 2.217973",\
+ "1.544015, 1.750334, 1.927966, 2.216528, 2.776682",\
+ "0.973287, 1.153774, 1.329742, 1.617954, 2.177485",\
+ "1.016196, 1.196683, 1.372651, 1.660863, 2.220395",\
+ "1.092696, 1.273183, 1.449150, 1.737363, 2.296894",\
+ "1.315995, 1.496482, 1.672450, 1.960662, 2.520194",\
+ "1.874038, 2.055627, 2.231622, 2.519700, 3.078903");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\
+ "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\
+ "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\
+ "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\
+ "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\
+ "2.135107, 2.135107, 2.135107, 2.135106, 2.135106");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.389319, 0.610934, 0.789045, 1.077845, 1.638363",\
+ "0.418979, 0.640595, 0.818706, 1.107506, 1.668024",\
+ "0.470920, 0.692535, 0.870646, 1.159446, 1.719964",\
+ "0.619380, 0.840995, 1.019106, 1.307906, 1.868424",\
+ "0.983284, 1.204968, 1.383013, 1.671947, 2.232793",\
+ "0.477727, 0.698253, 0.876326, 1.165150, 1.725716",\
+ "0.507388, 0.727914, 0.905987, 1.194811, 1.755377",\
+ "0.559328, 0.779854, 0.957927, 1.246751, 1.807317",\
+ "0.707788, 0.928314, 1.106387, 1.395211, 1.955777",\
+ "1.071693, 1.292286, 1.470294, 1.759253, 2.320147",\
+ "0.566817, 0.778588, 0.956353, 1.245178, 1.805748",\
+ "0.596478, 0.808249, 0.986014, 1.274839, 1.835409",\
+ "0.648419, 0.860189, 1.037954, 1.326780, 1.887349",\
+ "0.796878, 1.008649, 1.186414, 1.475240, 2.035809",\
+ "1.160783, 1.372622, 1.550321, 1.839281, 2.400178",\
+ "0.630095, 0.836414, 1.014046, 1.302608, 1.862762",\
+ "0.659756, 0.866074, 1.043707, 1.332269, 1.892423",\
+ "0.711696, 0.918015, 1.095647, 1.384209, 1.944364",\
+ "0.860156, 1.066475, 1.244107, 1.532669, 2.092824",\
+ "1.224061, 1.430443, 1.608014, 1.896711, 2.457193",\
+ "0.960117, 1.141707, 1.317702, 1.605780, 2.164983",\
+ "0.989778, 1.171368, 1.347363, 1.635441, 2.194643",\
+ "1.041718, 1.223308, 1.399303, 1.687381, 2.246584",\
+ "1.190178, 1.371768, 1.547763, 1.835841, 2.395044",\
+ "1.555216, 1.735703, 1.911671, 2.199883, 2.759414");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\
+ "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\
+ "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\
+ "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\
+ "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\
+ "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\
+ "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\
+ "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\
+ "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\
+ "1.119158, 1.119158, 1.119158, 1.119158, 1.119157");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2497*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[47]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.380051, 0.607077, 0.791540, 1.086441, 1.656420",\
+ "0.422960, 0.649986, 0.834449, 1.129350, 1.699329",\
+ "0.499459, 0.726486, 0.910949, 1.205850, 1.775828",\
+ "0.722759, 0.949785, 1.134248, 1.429149, 1.999128",\
+ "1.281942, 1.507667, 1.692145, 1.987100, 2.557201",\
+ "0.468382, 0.694395, 0.878821, 1.173746, 1.743773",\
+ "0.511291, 0.737304, 0.921730, 1.216655, 1.786682",\
+ "0.587791, 0.813804, 0.998230, 1.293155, 1.863182",\
+ "0.811090, 1.037103, 1.221529, 1.516454, 2.086481",\
+ "1.370273, 1.594985, 1.779426, 2.074405, 2.644555",\
+ "0.557789, 0.774725, 0.958848, 1.253775, 1.823805",\
+ "0.600698, 0.817634, 1.001757, 1.296684, 1.866714",\
+ "0.677198, 0.894134, 1.078257, 1.373183, 1.943213",\
+ "0.900497, 1.117434, 1.301556, 1.596483, 2.166513",\
+ "1.459679, 1.675315, 1.859452, 2.154434, 2.724586",\
+ "0.621599, 0.832548, 1.016557, 1.311216, 1.880844",\
+ "0.664508, 0.875457, 1.059467, 1.354125, 1.923753",\
+ "0.741007, 0.951957, 1.135966, 1.430625, 2.000253",\
+ "0.964307, 1.175256, 1.359266, 1.653924, 2.223552",\
+ "1.523487, 1.733139, 1.917162, 2.211875, 2.781626",\
+ "0.958721, 1.137805, 1.320215, 1.614397, 2.183095",\
+ "1.001630, 1.180714, 1.363124, 1.657306, 2.226004",\
+ "1.078130, 1.257213, 1.439624, 1.733806, 2.302503",\
+ "1.301429, 1.480513, 1.662923, 1.957105, 2.525803",\
+ "1.859271, 2.038396, 2.220819, 2.515056, 3.083877");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136075, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\
+ "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136075, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\
+ "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\
+ "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\
+ "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\
+ "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\
+ "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\
+ "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\
+ "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\
+ "2.135108, 2.135106, 2.135105, 2.135105, 2.135105");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.368022, 0.593747, 0.778225, 1.073180, 1.643281",\
+ "0.397682, 0.623408, 0.807886, 1.102841, 1.672942",\
+ "0.449623, 0.675348, 0.859826, 1.154781, 1.724883",\
+ "0.598083, 0.823808, 1.008286, 1.303241, 1.873343",\
+ "0.961980, 1.189006, 1.373469, 1.668370, 2.238349",\
+ "0.456353, 0.681065, 0.865506, 1.160485, 1.730635",\
+ "0.486014, 0.710726, 0.895167, 1.190146, 1.760296",\
+ "0.537954, 0.762666, 0.947107, 1.242086, 1.812236",\
+ "0.686414, 0.911126, 1.095567, 1.390546, 1.960696",\
+ "1.050311, 1.276324, 1.460750, 1.755675, 2.325702",\
+ "0.545759, 0.761395, 0.945533, 1.240514, 1.810667",\
+ "0.575419, 0.791056, 0.975194, 1.270175, 1.840328",\
+ "0.627360, 0.842997, 1.027134, 1.322115, 1.892268",\
+ "0.775819, 0.991457, 1.175594, 1.470575, 2.040728",\
+ "1.139718, 1.356654, 1.540777, 1.835704, 2.405734",\
+ "0.609567, 0.819218, 1.003242, 1.297955, 1.867706",\
+ "0.639228, 0.848879, 1.032903, 1.327616, 1.897367",\
+ "0.691168, 0.900820, 1.084843, 1.379556, 1.949308",\
+ "0.839628, 1.049280, 1.233303, 1.528016, 2.097767",\
+ "1.203528, 1.414477, 1.598486, 1.893145, 2.462773",\
+ "0.945351, 1.124476, 1.306899, 1.601136, 2.169957",\
+ "0.975012, 1.154137, 1.336560, 1.630797, 2.199618",\
+ "1.026952, 1.206077, 1.388500, 1.682738, 2.251558",\
+ "1.175412, 1.354537, 1.536960, 1.831198, 2.400018",\
+ "1.540650, 1.719733, 1.902144, 2.196326, 2.765023");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401");
+ index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011");
+ values ( "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\
+ "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\
+ "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\
+ "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\
+ "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\
+ "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\
+ "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\
+ "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\
+ "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\
+ "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\
+ "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\
+ "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\
+ "1.119159, 1.119157, 1.119157, 1.119157, 1.119157");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2420*/
+
+} /* end of pin tl_o[3] */
+
+pin("tl_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.020161 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[16]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.596162, 0.867359, 1.159405, 1.656731, 2.651384",\
+ "0.643260, 0.914475, 1.206618, 1.704208, 2.699388",\
+ "0.730525, 1.001791, 1.294214, 1.792557, 2.789245",\
+ "0.956361, 1.227706, 1.520560, 2.020066, 3.019080",\
+ "1.523589, 1.795036, 2.088453, 2.589476, 3.591523",\
+ "0.683575, 0.954952, 1.247062, 1.743446, 2.737318",\
+ "0.730672, 1.002068, 1.294276, 1.790923, 2.785322",\
+ "0.817938, 1.089384, 1.381874, 1.879272, 2.875178",\
+ "1.043774, 1.315300, 1.608224, 2.106781, 3.105014",\
+ "1.611001, 1.882631, 2.176121, 2.676191, 3.677457",\
+ "0.766406, 1.044042, 1.335028, 1.831069, 2.824273",\
+ "0.813504, 1.091158, 1.382242, 1.878545, 2.872277",\
+ "0.900771, 1.178475, 1.469840, 1.966895, 2.962133",\
+ "1.126608, 1.404392, 1.696190, 2.194404, 3.191969",\
+ "1.693838, 1.971725, 2.264088, 2.763813, 3.764412",\
+ "0.829815, 1.109836, 1.399173, 1.894982, 2.887782",\
+ "0.876913, 1.156952, 1.446387, 1.942459, 2.935786",\
+ "0.964180, 1.244271, 1.533985, 2.030808, 3.025642",\
+ "1.190018, 1.470190, 1.760335, 2.258317, 3.255478",\
+ "1.757249, 2.037525, 2.328233, 2.827727, 3.827921",\
+ "1.164720, 1.476052, 1.751329, 2.244448, 3.233238",\
+ "1.211820, 1.523174, 1.798545, 2.291926, 3.281242",\
+ "1.299091, 1.610508, 1.886151, 2.380279, 3.371099",\
+ "1.524935, 1.836451, 2.112513, 2.607793, 3.600934",\
+ "2.092175, 2.403818, 2.680427, 3.177208, 4.173377");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.053862, 0.053914, 0.054909, 0.058152, 0.064638",\
+ "0.173267, 0.173231, 0.173035, 0.172508, 0.171453",\
+ "0.375460, 0.375376, 0.374957, 0.373858, 0.371660",\
+ "0.885481, 0.885445, 0.885292, 0.884908, 0.884140",\
+ "2.163051, 2.163105, 2.163316, 2.163829, 2.164857",\
+ "0.053862, 0.053914, 0.054919, 0.058152, 0.064638",\
+ "0.173267, 0.173231, 0.173034, 0.172508, 0.171453",\
+ "0.375460, 0.375376, 0.374953, 0.373858, 0.371660",\
+ "0.885481, 0.885444, 0.885291, 0.884908, 0.884140",\
+ "2.163051, 2.163105, 2.163317, 2.163829, 2.164857",\
+ "0.053863, 0.053915, 0.054919, 0.058152, 0.064638",\
+ "0.173266, 0.173230, 0.173034, 0.172508, 0.171453",\
+ "0.375459, 0.375374, 0.374953, 0.373858, 0.371660",\
+ "0.885480, 0.885444, 0.885290, 0.884908, 0.884140",\
+ "2.163052, 2.163106, 2.163317, 2.163829, 2.164857",\
+ "0.053864, 0.053916, 0.054920, 0.058152, 0.064638",\
+ "0.173266, 0.173229, 0.173034, 0.172508, 0.171453",\
+ "0.375457, 0.375372, 0.374953, 0.373858, 0.371660",\
+ "0.885480, 0.885443, 0.885290, 0.884908, 0.884140",\
+ "2.163053, 2.163108, 2.163317, 2.163829, 2.164857",\
+ "0.053868, 0.053932, 0.054952, 0.058165, 0.064638",\
+ "0.173263, 0.173218, 0.173028, 0.172506, 0.171453",\
+ "0.375451, 0.375346, 0.374942, 0.373853, 0.371660",\
+ "0.885476, 0.885432, 0.885287, 0.884906, 0.884140",\
+ "2.163059, 2.163123, 2.163322, 2.163831, 2.164857");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.526597, 0.797546, 1.089766, 1.588771, 2.586781",\
+ "0.587519, 0.858706, 1.150697, 1.647877, 2.642235",\
+ "0.654254, 0.925628, 1.218645, 1.718590, 2.718481",\
+ "0.788462, 1.059820, 1.352751, 1.852464, 2.851889",\
+ "1.131923, 1.403187, 1.695595, 2.193900, 3.190510",\
+ "0.614010, 0.885137, 1.177429, 1.675486, 2.672715",\
+ "0.674932, 0.946299, 1.238354, 1.734592, 2.728169",\
+ "0.741667, 1.013223, 1.306311, 1.805305, 2.804415",\
+ "0.875874, 1.147414, 1.440416, 1.939178, 2.937823",\
+ "1.219336, 1.490780, 1.783256, 2.280615, 3.276443",\
+ "0.696837, 0.974222, 1.265395, 1.763108, 2.759670",\
+ "0.757763, 1.035389, 1.326320, 1.822214, 2.815124",\
+ "0.824502, 1.102316, 1.394277, 1.892928, 2.891370",\
+ "0.958709, 1.236507, 1.528382, 2.026801, 3.024778",\
+ "1.302169, 1.579871, 1.871222, 2.368237, 3.363399",\
+ "0.760242, 1.040009, 1.329540, 1.827022, 2.823179",\
+ "0.821171, 1.101182, 1.390465, 1.886127, 2.878633",\
+ "0.887912, 1.168114, 1.458422, 1.956841, 2.954879",\
+ "1.022119, 1.302305, 1.592527, 2.090714, 3.088287",\
+ "1.365578, 1.645666, 1.935366, 2.432151, 3.426908",\
+ "1.095129, 1.406150, 1.681713, 2.176495, 3.168635",\
+ "1.156076, 1.467395, 1.742619, 2.235593, 3.224089",\
+ "1.222832, 1.534384, 1.810604, 2.306318, 3.300335",\
+ "1.357038, 1.668570, 1.944707, 2.440191, 3.433743",\
+ "1.700489, 2.011903, 2.287532, 2.781621, 3.772364");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.071571, 0.071932, 0.073911, 0.079246, 0.089916",\
+ "0.129642, 0.130131, 0.132813, 0.140046, 0.154511",\
+ "0.213984, 0.214431, 0.216880, 0.223483, 0.236689",\
+ "0.447086, 0.447136, 0.447410, 0.448149, 0.449626",\
+ "1.100696, 1.100673, 1.100546, 1.100205, 1.099521",\
+ "0.071571, 0.071935, 0.073927, 0.079246, 0.089916",\
+ "0.129642, 0.130135, 0.132836, 0.140046, 0.154511",\
+ "0.213984, 0.214435, 0.216901, 0.223483, 0.236689",\
+ "0.447086, 0.447137, 0.447412, 0.448149, 0.449626",\
+ "1.100696, 1.100673, 1.100545, 1.100205, 1.099521",\
+ "0.071578, 0.071942, 0.073928, 0.079246, 0.089916",\
+ "0.129651, 0.130144, 0.132837, 0.140046, 0.154511",\
+ "0.213993, 0.214443, 0.216901, 0.223483, 0.236689",\
+ "0.447087, 0.447137, 0.447412, 0.448149, 0.449626",\
+ "1.100696, 1.100673, 1.100545, 1.100205, 1.099521",\
+ "0.071582, 0.071951, 0.073929, 0.079246, 0.089916",\
+ "0.129657, 0.130157, 0.132838, 0.140046, 0.154511",\
+ "0.213998, 0.214454, 0.216902, 0.223483, 0.236689",\
+ "0.447088, 0.447139, 0.447413, 0.448149, 0.449626",\
+ "1.100696, 1.100672, 1.100545, 1.100205, 1.099521",\
+ "0.071611, 0.072061, 0.073983, 0.079268, 0.089916",\
+ "0.129696, 0.130306, 0.132911, 0.140076, 0.154511",\
+ "0.214033, 0.214590, 0.216969, 0.223510, 0.236689",\
+ "0.447092, 0.447154, 0.447420, 0.448152, 0.449626",\
+ "1.100694, 1.100665, 1.100542, 1.100203, 1.099521");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2642*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[18]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.620483, 0.875327, 1.158797, 1.657448, 2.654750",\
+ "0.666691, 0.921535, 1.205006, 1.703663, 2.700977",\
+ "0.750941, 1.005785, 1.289255, 1.787906, 2.785209",\
+ "0.971936, 1.226783, 1.510836, 2.011498, 3.012820",\
+ "1.532384, 1.787236, 2.072631, 2.577909, 3.588464",\
+ "0.707891, 0.962871, 1.246456, 1.744162, 2.740684",\
+ "0.754100, 1.009078, 1.292665, 1.790377, 2.786911",\
+ "0.838350, 1.093329, 1.376915, 1.874621, 2.871142",\
+ "1.059345, 1.314327, 1.598502, 2.098212, 3.098754",\
+ "1.619793, 1.874780, 2.160311, 2.664623, 3.674398",\
+ "0.788766, 1.051830, 1.334422, 1.831784, 2.827639",\
+ "0.834975, 1.098037, 1.380631, 1.877999, 2.873866",\
+ "0.919225, 1.182288, 1.464880, 1.962242, 2.958097",\
+ "1.140220, 1.403286, 1.686468, 2.185834, 3.185709",\
+ "1.700668, 1.963739, 2.248277, 2.752245, 3.761353",\
+ "0.848948, 1.117433, 1.398566, 1.895697, 2.891148",\
+ "0.895156, 1.163640, 1.444775, 1.941912, 2.937375",\
+ "0.979406, 1.247891, 1.529024, 2.026155, 3.021606",\
+ "1.200402, 1.468889, 1.750613, 2.249747, 3.249218",\
+ "1.760850, 2.029342, 2.312423, 2.816158, 3.824862",\
+ "1.183848, 1.481469, 1.750734, 2.245165, 3.236604",\
+ "1.230056, 1.527677, 1.796943, 2.291380, 3.282831",\
+ "1.314306, 1.611928, 1.881192, 2.375623, 3.367063",\
+ "1.535303, 1.832926, 2.102801, 2.599223, 3.594674",\
+ "2.095753, 2.393380, 2.664657, 3.165653, 4.170318");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\
+ "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\
+ "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\
+ "0.885930, 0.885935, 0.885937, 0.885937, 0.885937",\
+ "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\
+ "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\
+ "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\
+ "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\
+ "0.885930, 0.885935, 0.885937, 0.885937, 0.885937",\
+ "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\
+ "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\
+ "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\
+ "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\
+ "0.885930, 0.885935, 0.885937, 0.885937, 0.885937",\
+ "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\
+ "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\
+ "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\
+ "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\
+ "0.885931, 0.885935, 0.885937, 0.885937, 0.885937",\
+ "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\
+ "0.052746, 0.052746, 0.052771, 0.052852, 0.053015",\
+ "0.178338, 0.178338, 0.178380, 0.178516, 0.178792",\
+ "0.381631, 0.381631, 0.381651, 0.381714, 0.381841",\
+ "0.885932, 0.885936, 0.885937, 0.885937, 0.885937",\
+ "2.162390, 2.162390, 2.162428, 2.162552, 2.162801");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.568910, 0.823730, 1.112547, 1.629674, 2.663928",\
+ "0.612218, 0.867064, 1.154057, 1.664859, 2.686463",\
+ "0.668015, 0.922863, 1.208574, 1.714952, 2.727708",\
+ "0.803644, 1.058488, 1.343000, 1.845245, 2.849735",\
+ "1.152943, 1.407785, 1.691260, 2.189933, 3.187279",\
+ "0.656319, 0.911274, 1.200265, 1.716388, 2.749862",\
+ "0.699627, 0.954607, 1.241755, 1.751573, 2.772397",\
+ "0.755424, 1.010406, 1.296258, 1.801666, 2.813642",\
+ "0.891053, 1.146032, 1.430671, 1.931960, 2.935669",\
+ "1.240352, 1.495328, 1.778919, 2.276647, 3.273213",\
+ "0.737194, 1.000233, 1.288231, 1.804010, 2.836817",\
+ "0.780502, 1.043566, 1.329721, 1.839195, 2.859352",\
+ "0.836299, 1.099365, 1.384223, 1.889288, 2.900597",\
+ "0.971928, 1.234991, 1.518637, 2.019581, 3.022624",\
+ "1.321227, 1.584288, 1.866885, 2.364269, 3.360168",\
+ "0.797372, 1.065835, 1.352379, 1.867923, 2.900326",\
+ "0.840683, 1.109169, 1.393867, 1.903108, 2.922861",\
+ "0.896481, 1.164968, 1.448369, 1.953201, 2.964106",\
+ "1.032109, 1.300594, 1.582782, 2.083494, 3.086133",\
+ "1.381408, 1.649890, 1.931029, 2.428182, 3.423677",\
+ "1.132264, 1.429870, 1.704734, 2.217468, 3.245782",\
+ "1.175584, 1.473206, 1.746158, 2.252626, 3.268317",\
+ "1.231382, 1.529005, 1.800615, 2.302701, 3.309562",\
+ "1.367010, 1.664631, 1.934986, 2.432977, 3.431589",\
+ "1.716307, 2.013927, 2.283197, 2.777650, 3.769133");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\
+ "0.096054, 0.096054, 0.095973, 0.095695, 0.095137",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\
+ "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\
+ "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\
+ "0.096054, 0.096054, 0.095972, 0.095695, 0.095137",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\
+ "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\
+ "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\
+ "0.096054, 0.096054, 0.095972, 0.095695, 0.095137",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\
+ "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\
+ "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\
+ "0.096054, 0.096054, 0.095972, 0.095695, 0.095137",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\
+ "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\
+ "0.046309, 0.046309, 0.046283, 0.046200, 0.046032",\
+ "0.096054, 0.096054, 0.095970, 0.095693, 0.095137",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\
+ "1.101657, 1.101657, 1.101653, 1.101637, 1.101605");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2640*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[21]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.197465, 0.431884, 0.691143, 1.132576, 2.015443",\
+ "0.256904, 0.482244, 0.742878, 1.186420, 2.073503",\
+ "0.340726, 0.558560, 0.820216, 1.263968, 2.151470",\
+ "0.552743, 0.766273, 1.030363, 1.473596, 2.360062",\
+ "1.106694, 1.318615, 1.585993, 2.032644, 2.925946",\
+ "0.284867, 0.519390, 0.778620, 1.219289, 2.101377",\
+ "0.344307, 0.569755, 0.830361, 1.273133, 2.159437",\
+ "0.428128, 0.646078, 0.907700, 1.350681, 2.237404",\
+ "0.640145, 0.853808, 1.117845, 1.560309, 2.445995",\
+ "1.194097, 1.406166, 1.673486, 2.119357, 3.011879",\
+ "0.365670, 0.608240, 0.866580, 1.306910, 2.188332",\
+ "0.425121, 0.658616, 0.918322, 1.360754, 2.246392",\
+ "0.508950, 0.734952, 0.995661, 1.438301, 2.324359",\
+ "0.720977, 0.942721, 1.205806, 1.647930, 2.532950",\
+ "1.274933, 1.495112, 1.761447, 2.206978, 3.098835",\
+ "0.423291, 0.673682, 0.930715, 1.370823, 2.251841",\
+ "0.482765, 0.724074, 0.982457, 1.424666, 2.309901",\
+ "0.566610, 0.800431, 1.059796, 1.502214, 2.387868",\
+ "0.778657, 1.008255, 1.269941, 1.711842, 2.596459",\
+ "1.332621, 1.560694, 1.825583, 2.270890, 3.162344",\
+ "0.752280, 1.035917, 1.282299, 1.720049, 2.597297",\
+ "0.801700, 1.086498, 1.334062, 1.773901, 2.655357",\
+ "0.877280, 1.163095, 1.411404, 1.851450, 2.733324",\
+ "1.083334, 1.371566, 1.621543, 2.061076, 2.941916",\
+ "1.635803, 1.924576, 2.177220, 2.620138, 3.507800");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.177313, 0.213506, 0.303388, 0.457575, 0.765950",\
+ "0.250045, 0.279683, 0.356813, 0.520203, 0.846983",\
+ "0.414563, 0.415723, 0.459642, 0.603351, 0.890769",\
+ "0.887841, 0.887858, 0.923884, 1.046147, 1.290675",\
+ "2.163213, 2.163213, 2.177271, 2.225014, 2.320500",\
+ "0.177313, 0.213805, 0.303871, 0.457575, 0.765950",\
+ "0.250045, 0.279878, 0.357325, 0.520203, 0.846983",\
+ "0.414563, 0.415734, 0.460093, 0.603351, 0.890769",\
+ "0.887841, 0.887859, 0.924267, 1.046147, 1.290675",\
+ "2.163213, 2.163213, 2.177421, 2.225014, 2.320500",\
+ "0.177336, 0.214457, 0.303880, 0.457575, 0.765950",\
+ "0.250094, 0.280303, 0.357335, 0.520203, 0.846983",\
+ "0.414563, 0.415757, 0.460101, 0.603351, 0.890769",\
+ "0.887841, 0.887859, 0.924274, 1.046147, 1.290675",\
+ "2.163213, 2.163213, 2.177424, 2.225014, 2.320500",\
+ "0.177382, 0.215405, 0.303907, 0.457575, 0.765950",\
+ "0.250194, 0.280922, 0.357363, 0.520203, 0.846983",\
+ "0.414563, 0.415792, 0.460126, 0.603351, 0.890769",\
+ "0.887841, 0.887859, 0.924295, 1.046147, 1.290675",\
+ "2.163213, 2.163213, 2.177432, 2.225014, 2.320500",\
+ "0.179823, 0.226531, 0.305470, 0.458210, 0.765950",\
+ "0.255480, 0.288180, 0.359019, 0.520875, 0.846983",\
+ "0.414563, 0.416192, 0.461583, 0.603943, 0.890769",\
+ "0.887841, 0.887865, 0.925535, 1.046651, 1.290675",\
+ "2.163213, 2.163213, 2.177916, 2.225211, 2.320500");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.186444, 0.372257, 0.626401, 1.055911, 1.914929",\
+ "0.215837, 0.420150, 0.691942, 1.154794, 2.080498",\
+ "0.262380, 0.480818, 0.763209, 1.249238, 2.221297",\
+ "0.391146, 0.611553, 0.905194, 1.430347, 2.480653",\
+ "0.735395, 0.947247, 1.249008, 1.808760, 2.928262",\
+ "0.273847, 0.459753, 0.713841, 1.142624, 2.000862",\
+ "0.303239, 0.507698, 0.779487, 1.241508, 2.166432",\
+ "0.349783, 0.568392, 0.850825, 1.335951, 2.307231",\
+ "0.478548, 0.699125, 0.992933, 1.517060, 2.566586",\
+ "0.822797, 1.034805, 1.336856, 1.895473, 3.014196",\
+ "0.354708, 0.548579, 0.801801, 1.230244, 2.087817",\
+ "0.384100, 0.596639, 0.867448, 1.329128, 2.253387",\
+ "0.430643, 0.657388, 0.938789, 1.423572, 2.394186",\
+ "0.559400, 0.788117, 1.080899, 1.604681, 2.653542",\
+ "0.903640, 1.123767, 1.424824, 1.983094, 3.101151",\
+ "0.412447, 0.613987, 0.865934, 1.294157, 2.151326",\
+ "0.441838, 0.662214, 0.931587, 1.393041, 2.316896",\
+ "0.488379, 0.723043, 1.002931, 1.487485, 2.457695",\
+ "0.617120, 0.853767, 1.145048, 1.668593, 2.717051",\
+ "0.961342, 1.189372, 1.488979, 2.047006, 3.164660",\
+ "0.716098, 0.975821, 1.217396, 1.643334, 2.496783",\
+ "0.745485, 1.026006, 1.283388, 1.742355, 2.662352",\
+ "0.795750, 1.087780, 1.354967, 1.836895, 2.803151",\
+ "0.926660, 1.218436, 1.497480, 2.018165, 3.062507",\
+ "1.264652, 1.553524, 1.841762, 2.396720, 3.510116");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.071183, 0.106877, 0.175281, 0.296416, 0.538687",\
+ "0.120882, 0.144932, 0.213033, 0.350090, 0.624205",\
+ "0.200934, 0.210788, 0.256182, 0.378836, 0.624145",\
+ "0.444935, 0.444935, 0.478349, 0.591825, 0.818777",\
+ "1.101088, 1.102468, 1.122488, 1.190477, 1.326455",\
+ "0.071183, 0.107097, 0.175661, 0.296416, 0.538687",\
+ "0.120882, 0.145118, 0.213463, 0.350090, 0.624205",\
+ "0.200934, 0.210850, 0.256566, 0.378836, 0.624145",\
+ "0.444935, 0.444935, 0.478705, 0.591825, 0.818777",\
+ "1.101088, 1.102468, 1.122701, 1.190477, 1.326455",\
+ "0.071251, 0.107578, 0.175668, 0.296416, 0.538687",\
+ "0.120905, 0.145525, 0.213471, 0.350090, 0.624205",\
+ "0.200952, 0.210986, 0.256574, 0.378836, 0.624145",\
+ "0.444935, 0.444935, 0.478711, 0.591825, 0.818777",\
+ "1.101096, 1.102468, 1.122705, 1.190477, 1.326455",\
+ "0.071390, 0.108275, 0.175689, 0.296416, 0.538687",\
+ "0.120951, 0.146116, 0.213494, 0.350090, 0.624205",\
+ "0.200988, 0.211184, 0.256595, 0.378836, 0.624145",\
+ "0.444935, 0.444935, 0.478731, 0.591825, 0.818777",\
+ "1.101112, 1.102468, 1.122717, 1.190477, 1.326455",\
+ "0.072681, 0.116463, 0.176917, 0.296915, 0.538687",\
+ "0.121377, 0.153056, 0.214884, 0.350655, 0.624205",\
+ "0.202910, 0.213504, 0.257838, 0.379341, 0.624145",\
+ "0.444935, 0.444935, 0.479881, 0.592292, 0.818777",\
+ "1.101261, 1.102468, 1.123406, 1.190757, 1.326455");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2293*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[24]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.606811, 0.855240, 1.131420, 1.600406, 2.538379",\
+ "0.653020, 0.901448, 1.177629, 1.646621, 2.584605",\
+ "0.737270, 0.985698, 1.261878, 1.730864, 2.668837",\
+ "0.958264, 1.206694, 1.482871, 1.951840, 2.889778",\
+ "1.518707, 1.767142, 2.043312, 2.512236, 3.450085",\
+ "0.694214, 0.942805, 1.218983, 1.687119, 2.624312",\
+ "0.740423, 0.989013, 1.265193, 1.733334, 2.670539",\
+ "0.824672, 1.073263, 1.349441, 1.817578, 2.754771",\
+ "1.045666, 1.294259, 1.570434, 2.038553, 2.975712",\
+ "1.606110, 1.854707, 2.130875, 2.598950, 3.536019",\
+ "0.775027, 1.031783, 1.306946, 1.774740, 2.711267",\
+ "0.821236, 1.077992, 1.353155, 1.820955, 2.757494",\
+ "0.905485, 1.162242, 1.437404, 1.905199, 2.841726",\
+ "1.126479, 1.383237, 1.658397, 2.126174, 3.062667",\
+ "1.686923, 1.943686, 2.218838, 2.686570, 3.622974",\
+ "0.832667, 1.097413, 1.371085, 1.838653, 2.774776",\
+ "0.878876, 1.143622, 1.417294, 1.884868, 2.821003",\
+ "0.963125, 1.227872, 1.501543, 1.969111, 2.905235",\
+ "1.184119, 1.448868, 1.722536, 2.190087, 3.126176",\
+ "1.744563, 2.009316, 2.282977, 2.750483, 3.686483",\
+ "1.167769, 1.461851, 1.722948, 2.187993, 3.120233",\
+ "1.213978, 1.508059, 1.769157, 2.234208, 3.166459",\
+ "1.298227, 1.592309, 1.853406, 2.318451, 3.250691",\
+ "1.519221, 1.813305, 2.074399, 2.539426, 3.471632",\
+ "2.079665, 2.373755, 2.634840, 3.099823, 4.031939");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.052753, 0.052753, 0.052776, 0.052854, 0.053011",\
+ "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\
+ "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\
+ "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\
+ "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\
+ "0.052753, 0.052753, 0.052777, 0.052854, 0.053011",\
+ "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\
+ "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\
+ "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\
+ "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\
+ "0.052753, 0.052753, 0.052777, 0.052854, 0.053011",\
+ "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\
+ "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\
+ "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\
+ "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\
+ "0.052753, 0.052753, 0.052777, 0.052854, 0.053011",\
+ "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\
+ "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\
+ "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\
+ "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\
+ "0.052753, 0.052753, 0.052777, 0.052855, 0.053011",\
+ "0.178350, 0.178350, 0.178390, 0.178521, 0.178785",\
+ "0.381637, 0.381637, 0.381656, 0.381716, 0.381838",\
+ "0.885927, 0.885932, 0.885936, 0.885936, 0.885936",\
+ "2.162395, 2.162395, 2.162431, 2.162547, 2.162780");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.555254, 0.803664, 1.079873, 1.549041, 2.487376",\
+ "0.598546, 0.846975, 1.123154, 1.592132, 2.530087",\
+ "0.654342, 0.902772, 1.178949, 1.647912, 2.585838",\
+ "0.789973, 1.038401, 1.314582, 1.783569, 2.721544",\
+ "1.139274, 1.387700, 1.663883, 2.132891, 3.070906",\
+ "0.642657, 0.891229, 1.167437, 1.635754, 2.573310",\
+ "0.685949, 0.934540, 1.210717, 1.678845, 2.616020",\
+ "0.741745, 0.990338, 1.266512, 1.734625, 2.671772",\
+ "0.877376, 1.125967, 1.402145, 1.870283, 2.807478",\
+ "1.226676, 1.475265, 1.751447, 2.219604, 3.156840",\
+ "0.723469, 0.980207, 1.255399, 1.723375, 2.660265",\
+ "0.766762, 1.023519, 1.298680, 1.766466, 2.702976",\
+ "0.822557, 1.079316, 1.354475, 1.822246, 2.758727",\
+ "0.958189, 1.214945, 1.490107, 1.957903, 2.894433",\
+ "1.307489, 1.564244, 1.839409, 2.307225, 3.243795",\
+ "0.781109, 1.045837, 1.319539, 1.787287, 2.723774",\
+ "0.824402, 1.089149, 1.362819, 1.830378, 2.766484",\
+ "0.880198, 1.144946, 1.418614, 1.886158, 2.822236",\
+ "1.015829, 1.280575, 1.554247, 2.021816, 2.957942",\
+ "1.365129, 1.629874, 1.903549, 2.371138, 3.307304",\
+ "1.116211, 1.410268, 1.671404, 2.136628, 3.069230",\
+ "1.159504, 1.453587, 1.714682, 2.179718, 3.111940",\
+ "1.215299, 1.509384, 1.770477, 2.235498, 3.167692",\
+ "1.350931, 1.645012, 1.906110, 2.371156, 3.303398",\
+ "1.700231, 1.994310, 2.255412, 2.720478, 3.652760");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\
+ "0.096045, 0.096045, 0.095965, 0.095693, 0.095150",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\
+ "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\
+ "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\
+ "0.096045, 0.096045, 0.095964, 0.095693, 0.095150",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\
+ "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\
+ "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\
+ "0.096045, 0.096045, 0.095964, 0.095693, 0.095150",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\
+ "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\
+ "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\
+ "0.096045, 0.096045, 0.095964, 0.095693, 0.095150",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\
+ "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\
+ "0.046307, 0.046307, 0.046283, 0.046204, 0.046045",\
+ "0.096045, 0.096045, 0.095961, 0.095692, 0.095150",\
+ "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\
+ "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\
+ "1.101656, 1.101656, 1.101651, 1.101636, 1.101606");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2451*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[26]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.574242, 0.825673, 1.106128, 1.575345, 2.513779",\
+ "0.621341, 0.872791, 1.153329, 1.622748, 2.561586",\
+ "0.708610, 0.960115, 1.240890, 1.710886, 2.650879",\
+ "0.934451, 1.186041, 1.467182, 1.938070, 2.879846",\
+ "1.501685, 1.753387, 2.035005, 2.507055, 3.451155",\
+ "0.661652, 0.913251, 1.193695, 1.662059, 2.599712",\
+ "0.708750, 0.960370, 1.240897, 1.709462, 2.647520",\
+ "0.796019, 1.047694, 1.328459, 1.797601, 2.736813",\
+ "1.021860, 1.273621, 1.554754, 2.024784, 2.965779",\
+ "1.589094, 1.840967, 2.122581, 2.593769, 3.537089",\
+ "0.742484, 1.002291, 1.281659, 1.749681, 2.686667",\
+ "0.789583, 1.049409, 1.328861, 1.797084, 2.734475",\
+ "0.876852, 1.136734, 1.416423, 1.885223, 2.823768",\
+ "1.102693, 1.362663, 1.642718, 2.112406, 3.052734",\
+ "1.669927, 1.930012, 2.210544, 2.681391, 3.624044",\
+ "0.800100, 1.068010, 1.345799, 1.813594, 2.750176",\
+ "0.847199, 1.115129, 1.393000, 1.860997, 2.797984",\
+ "0.934467, 1.202456, 1.480563, 1.949136, 2.887277",\
+ "1.160309, 1.428387, 1.706858, 2.176319, 3.116243",\
+ "1.727543, 1.995738, 2.274684, 2.745304, 3.687553",\
+ "1.129877, 1.433405, 1.697668, 2.162941, 3.095633",\
+ "1.176977, 1.480531, 1.744871, 2.210345, 3.143440",\
+ "1.264251, 1.567875, 1.832440, 2.298486, 3.232733",\
+ "1.490099, 1.793832, 2.058744, 2.525673, 3.461699",\
+ "2.057343, 2.361218, 2.626582, 3.094663, 4.033009");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.053866, 0.053921, 0.054375, 0.055698, 0.058344",\
+ "0.173264, 0.173226, 0.173060, 0.172656, 0.171847",\
+ "0.375455, 0.375364, 0.374978, 0.374041, 0.372167",\
+ "0.885489, 0.885476, 0.885382, 0.885110, 0.884566",\
+ "2.163040, 2.163059, 2.163198, 2.163598, 2.164399",\
+ "0.053866, 0.053922, 0.054379, 0.055698, 0.058344",\
+ "0.173264, 0.173226, 0.173059, 0.172656, 0.171847",\
+ "0.375455, 0.375363, 0.374975, 0.374041, 0.372167",\
+ "0.885489, 0.885476, 0.885381, 0.885110, 0.884566",\
+ "2.163040, 2.163059, 2.163199, 2.163598, 2.164399",\
+ "0.053866, 0.053923, 0.054379, 0.055698, 0.058344",\
+ "0.173264, 0.173225, 0.173059, 0.172656, 0.171847",\
+ "0.375455, 0.375361, 0.374975, 0.374041, 0.372167",\
+ "0.885489, 0.885476, 0.885381, 0.885110, 0.884566",\
+ "2.163040, 2.163059, 2.163199, 2.163598, 2.164399",\
+ "0.053866, 0.053924, 0.054379, 0.055698, 0.058344",\
+ "0.173264, 0.173224, 0.173059, 0.172656, 0.171847",\
+ "0.375454, 0.375359, 0.374975, 0.374041, 0.372167",\
+ "0.885489, 0.885476, 0.885381, 0.885110, 0.884566",\
+ "2.163040, 2.163060, 2.163199, 2.163598, 2.164399",\
+ "0.053870, 0.053942, 0.054392, 0.055703, 0.058344",\
+ "0.173261, 0.173212, 0.173054, 0.172654, 0.171847",\
+ "0.375447, 0.375331, 0.374965, 0.374037, 0.372167",\
+ "0.885488, 0.885472, 0.885378, 0.885109, 0.884566",\
+ "2.163042, 2.163065, 2.163203, 2.163600, 2.164399");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.504662, 0.755823, 1.035123, 1.501524, 2.434327",\
+ "0.565599, 0.817019, 1.097428, 1.566532, 2.504740",\
+ "0.632345, 0.883968, 1.165247, 1.636471, 2.578919",\
+ "0.766552, 1.018158, 1.299363, 1.770409, 2.712501",\
+ "1.110008, 1.361510, 1.642273, 2.112240, 3.052173",\
+ "0.592071, 0.843399, 1.122681, 1.588239, 2.520261",\
+ "0.653008, 0.904597, 1.184994, 1.653246, 2.590674",\
+ "0.719755, 0.971548, 1.252820, 1.723185, 2.664853",\
+ "0.853962, 1.105738, 1.386936, 1.857124, 2.798434",\
+ "1.197417, 1.449089, 1.729842, 2.198954, 3.138107",\
+ "0.672903, 0.932434, 1.210645, 1.675861, 2.607216",\
+ "0.733841, 0.993636, 1.272958, 1.740868, 2.677629",\
+ "0.800588, 1.060591, 1.340784, 1.810807, 2.751808",\
+ "0.934794, 1.194780, 1.474900, 1.944745, 2.885390",\
+ "1.278250, 1.538130, 1.817806, 2.286576, 3.225062",\
+ "0.730518, 0.998146, 1.274784, 1.739774, 2.670725",\
+ "0.791456, 1.059355, 1.337098, 1.804781, 2.741138",\
+ "0.858203, 1.126316, 1.404924, 1.874720, 2.815317",\
+ "0.992410, 1.260504, 1.539040, 2.008659, 2.948899",\
+ "1.335865, 1.603851, 1.881946, 2.350489, 3.288571",\
+ "1.060274, 1.363457, 1.626624, 2.089109, 3.016181",\
+ "1.121233, 1.424747, 1.688966, 2.154127, 3.086594",\
+ "1.187996, 1.491771, 1.756814, 2.224075, 3.160773",\
+ "1.322202, 1.625954, 1.890928, 2.358013, 3.294354",\
+ "1.665648, 1.969269, 2.233823, 2.699839, 3.634027");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.071595, 0.071985, 0.073663, 0.077752, 0.085929",\
+ "0.129674, 0.130204, 0.132478, 0.138021, 0.149107",\
+ "0.214013, 0.214497, 0.216573, 0.221634, 0.231755",\
+ "0.447089, 0.447144, 0.447376, 0.447942, 0.449074",\
+ "1.100695, 1.100670, 1.100562, 1.100300, 1.099777",\
+ "0.071595, 0.071989, 0.073676, 0.077752, 0.085929",\
+ "0.129674, 0.130208, 0.132495, 0.138021, 0.149107",\
+ "0.214013, 0.214501, 0.216589, 0.221634, 0.231755",\
+ "0.447089, 0.447144, 0.447378, 0.447942, 0.449074",\
+ "1.100695, 1.100670, 1.100561, 1.100300, 1.099777",\
+ "0.071595, 0.071996, 0.073676, 0.077752, 0.085929",\
+ "0.129674, 0.130218, 0.132496, 0.138021, 0.149107",\
+ "0.214014, 0.214510, 0.216590, 0.221634, 0.231755",\
+ "0.447089, 0.447145, 0.447378, 0.447942, 0.449074",\
+ "1.100695, 1.100669, 1.100561, 1.100300, 1.099777",\
+ "0.071596, 0.072006, 0.073677, 0.077752, 0.085929",\
+ "0.129675, 0.130232, 0.132497, 0.138021, 0.149107",\
+ "0.214014, 0.214523, 0.216591, 0.221634, 0.231755",\
+ "0.447090, 0.447146, 0.447378, 0.447942, 0.449074",\
+ "1.100695, 1.100668, 1.100561, 1.100300, 1.099777",\
+ "0.071627, 0.072128, 0.073719, 0.077769, 0.085929",\
+ "0.129718, 0.130397, 0.132553, 0.138044, 0.149107",\
+ "0.214054, 0.214674, 0.216642, 0.221655, 0.231755",\
+ "0.447094, 0.447163, 0.447384, 0.447944, 0.449074",\
+ "1.100693, 1.100661, 1.100559, 1.100299, 1.099777");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2541*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[27]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.244315, 0.514723, 0.800077, 1.287472, 2.262263",\
+ "0.295834, 0.565221, 0.850051, 1.338109, 2.314226",\
+ "0.370354, 0.642449, 0.926203, 1.412852, 2.386149",\
+ "0.577074, 0.851060, 1.132979, 1.615988, 2.582005",\
+ "1.130301, 1.404191, 1.684823, 2.164586, 3.124112",\
+ "0.331716, 0.602319, 0.887697, 1.374185, 2.348197",\
+ "0.383234, 0.652812, 0.937673, 1.424822, 2.400160",\
+ "0.457755, 0.730036, 1.013820, 1.499564, 2.472083",\
+ "0.665475, 0.938641, 1.220586, 1.702701, 2.667939",\
+ "1.218705, 1.491770, 1.772419, 2.251299, 3.210045",\
+ "0.417649, 0.691352, 0.975660, 1.461806, 2.435152",\
+ "0.468650, 0.741835, 1.025635, 1.512442, 2.487115",\
+ "0.546403, 0.819049, 1.101783, 1.587185, 2.559038",\
+ "0.755504, 1.027643, 1.308548, 1.790321, 2.754894",\
+ "1.308745, 1.580767, 1.860382, 2.338919, 3.297000",\
+ "0.482221, 0.757061, 1.039803, 1.525718, 2.498661",\
+ "0.533223, 0.807529, 1.089778, 1.576355, 2.550624",\
+ "0.610973, 0.884729, 1.165926, 1.651097, 2.622547",\
+ "0.820080, 1.093307, 1.372690, 1.854234, 2.818403",\
+ "1.373332, 1.646424, 1.924523, 2.402832, 3.360509",\
+ "0.824496, 1.122462, 1.391851, 1.875132, 2.844117",\
+ "0.875514, 1.172748, 1.441833, 1.925771, 2.896080",\
+ "0.953244, 1.249783, 1.517967, 2.000508, 2.968003",\
+ "1.162385, 1.458171, 1.724694, 2.203629, 3.163859",\
+ "1.715704, 2.011206, 2.276494, 2.752214, 3.705966");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.247846, 0.303832, 0.405143, 0.595020, 0.974773",\
+ "0.313786, 0.346638, 0.435686, 0.627210, 1.010259",\
+ "0.435716, 0.458756, 0.530637, 0.704592, 1.052501",\
+ "0.888071, 0.889365, 0.918106, 1.015199, 1.209385",\
+ "2.165255, 2.165436, 2.171895, 2.192891, 2.234884",\
+ "0.247846, 0.304139, 0.405737, 0.595020, 0.974773",\
+ "0.313786, 0.346858, 0.436285, 0.627210, 1.010259",\
+ "0.435716, 0.458895, 0.531182, 0.704592, 1.052501",\
+ "0.888102, 0.889365, 0.918410, 1.015199, 1.209385",\
+ "2.165255, 2.165437, 2.171961, 2.192891, 2.234884",\
+ "0.250082, 0.304803, 0.405749, 0.595020, 0.974773",\
+ "0.314671, 0.347334, 0.436296, 0.627210, 1.010259",\
+ "0.436504, 0.459195, 0.531192, 0.704592, 1.052501",\
+ "0.888199, 0.889365, 0.918416, 1.015199, 1.209385",\
+ "2.165255, 2.165441, 2.171962, 2.192891, 2.234884",\
+ "0.251727, 0.305767, 0.405781, 0.595020, 0.974773",\
+ "0.315322, 0.348025, 0.436329, 0.627210, 1.010259",\
+ "0.437083, 0.459631, 0.531222, 0.704592, 1.052501",\
+ "0.888292, 0.889365, 0.918433, 1.015199, 1.209385",\
+ "2.165255, 2.165446, 2.171966, 2.192891, 2.234884",\
+ "0.262263, 0.317092, 0.407706, 0.595800, 0.974773",\
+ "0.319491, 0.356149, 0.438270, 0.627998, 1.010259",\
+ "0.440795, 0.464750, 0.532985, 0.705307, 1.052501",\
+ "0.888892, 0.889365, 0.919417, 1.015598, 1.209385",\
+ "2.165255, 2.165507, 2.172179, 2.192978, 2.234884");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.244906, 0.429066, 0.715031, 1.201577, 2.174669",\
+ "0.279961, 0.467088, 0.760757, 1.264102, 2.270793",\
+ "0.330500, 0.520871, 0.819993, 1.340074, 2.380235",\
+ "0.460001, 0.650607, 0.955135, 1.497108, 2.581054",\
+ "0.797840, 0.992388, 1.299994, 1.860913, 2.982751",\
+ "0.332306, 0.516668, 0.802648, 1.288290, 2.260602",\
+ "0.367361, 0.554708, 0.848427, 1.350815, 2.356727",\
+ "0.417900, 0.608494, 0.907716, 1.426787, 2.466169",\
+ "0.547401, 0.738223, 1.042926, 1.583821, 2.666988",\
+ "0.885240, 1.079987, 1.387844, 1.947626, 3.068685",\
+ "0.413157, 0.605714, 0.890611, 1.375910, 2.347558",\
+ "0.448212, 0.643794, 0.936391, 1.438436, 2.443682",\
+ "0.498750, 0.697588, 0.995681, 1.514407, 2.553124",\
+ "0.628251, 0.827301, 1.130892, 1.671441, 2.753943",\
+ "0.966089, 1.169027, 1.475811, 2.035246, 3.155640",\
+ "0.470897, 0.671442, 0.954754, 1.439822, 2.411067",\
+ "0.505953, 0.709581, 1.000537, 1.502348, 2.507191",\
+ "0.556489, 0.763385, 1.059829, 1.578320, 2.616633",\
+ "0.685989, 0.893075, 1.195044, 1.735354, 2.817452",\
+ "1.023827, 1.234747, 1.539967, 2.099159, 3.219149",\
+ "0.774671, 1.037059, 1.306793, 1.789232, 2.756522",\
+ "0.809728, 1.075884, 1.352747, 1.851827, 2.852647",\
+ "0.860246, 1.129813, 1.412209, 1.927867, 2.962089",\
+ "0.989742, 1.259233, 1.547645, 2.084991, 3.162908",\
+ "1.327573, 1.600271, 1.892761, 2.448874, 3.564605");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.078481, 0.114548, 0.190287, 0.342583, 0.647174",\
+ "0.121015, 0.135349, 0.195602, 0.346123, 0.647167",\
+ "0.210717, 0.216175, 0.259364, 0.388602, 0.647078",\
+ "0.448759, 0.449668, 0.471637, 0.541681, 0.681771",\
+ "1.102116, 1.102394, 1.113655, 1.151696, 1.227780",\
+ "0.078481, 0.114757, 0.190764, 0.342583, 0.647174",\
+ "0.121015, 0.135456, 0.196073, 0.346123, 0.647167",\
+ "0.210717, 0.216208, 0.259768, 0.388602, 0.647078",\
+ "0.448759, 0.449677, 0.471856, 0.541681, 0.681771",\
+ "1.102116, 1.102394, 1.113774, 1.151696, 1.227780",\
+ "0.078556, 0.115208, 0.190773, 0.342583, 0.647174",\
+ "0.121030, 0.135687, 0.196082, 0.346123, 0.647167",\
+ "0.210727, 0.216281, 0.259776, 0.388602, 0.647078",\
+ "0.448759, 0.449695, 0.471860, 0.541681, 0.681771",\
+ "1.102118, 1.102394, 1.113776, 1.151696, 1.227780",\
+ "0.078710, 0.115863, 0.190799, 0.342583, 0.647174",\
+ "0.121062, 0.136023, 0.196108, 0.346123, 0.647167",\
+ "0.210748, 0.216386, 0.259798, 0.388602, 0.647078",\
+ "0.448759, 0.449721, 0.471872, 0.541681, 0.681771",\
+ "1.102121, 1.102394, 1.113783, 1.151696, 1.227780",\
+ "0.080154, 0.123560, 0.192343, 0.343209, 0.647174",\
+ "0.121358, 0.139963, 0.197633, 0.346742, 0.647167",\
+ "0.210943, 0.217625, 0.261108, 0.389133, 0.647078",\
+ "0.448759, 0.450031, 0.472582, 0.541969, 0.681771",\
+ "1.102151, 1.102394, 1.114168, 1.151853, 1.227780");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2586*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[28]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.802622, 1.056036, 1.346324, 1.867286, 2.909209",\
+ "0.849165, 1.102582, 1.392879, 1.913861, 2.955825",\
+ "0.934845, 1.188269, 1.478593, 1.999634, 3.041714",\
+ "1.158235, 1.411669, 1.702036, 2.223166, 3.265427",\
+ "1.722272, 1.975720, 2.266142, 2.787390, 3.829885",\
+ "0.890034, 1.143575, 1.434056, 1.954001, 2.995142",\
+ "0.936578, 1.190121, 1.480612, 2.000576, 3.041759",\
+ "1.022258, 1.275808, 1.566326, 2.086349, 3.127648",\
+ "1.245647, 1.499208, 1.789768, 2.309881, 3.351360",\
+ "1.809685, 2.063260, 2.353875, 2.874104, 3.915819",\
+ "0.970907, 1.232542, 1.522024, 2.041623, 3.082098",\
+ "1.017450, 1.279087, 1.568579, 2.088199, 3.128714",\
+ "1.103130, 1.364774, 1.654293, 2.173971, 3.214603",\
+ "1.326520, 1.588175, 1.877736, 2.397503, 3.438315",\
+ "1.890557, 2.152227, 2.441842, 2.961727, 4.002774",\
+ "1.029596, 1.298156, 1.586172, 2.105536, 3.145607",\
+ "1.076139, 1.344701, 1.632727, 2.152112, 3.192223",\
+ "1.161819, 1.430389, 1.718441, 2.237885, 3.278112",\
+ "1.385208, 1.653790, 1.941884, 2.461417, 3.501824",\
+ "1.949246, 2.217842, 2.505991, 3.025640, 4.066283",\
+ "1.361666, 1.662270, 1.938568, 2.455101, 3.491063",\
+ "1.408209, 1.708817, 1.985123, 2.501677, 3.537679",\
+ "1.493889, 1.794507, 2.070838, 2.587449, 3.623568",\
+ "1.717279, 2.017912, 2.294282, 2.810982, 3.847281",\
+ "2.281316, 2.581969, 2.858389, 3.375206, 4.411739");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.052266, 0.052273, 0.052301, 0.052359, 0.052477",\
+ "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\
+ "0.378069, 0.378057, 0.378013, 0.377917, 0.377724",\
+ "0.885437, 0.885434, 0.885402, 0.885305, 0.885113",\
+ "2.163117, 2.163121, 2.163168, 2.163310, 2.163594",\
+ "0.052266, 0.052273, 0.052301, 0.052359, 0.052477",\
+ "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\
+ "0.378069, 0.378057, 0.378012, 0.377917, 0.377724",\
+ "0.885437, 0.885434, 0.885401, 0.885305, 0.885113",\
+ "2.163117, 2.163121, 2.163169, 2.163310, 2.163594",\
+ "0.052266, 0.052274, 0.052301, 0.052359, 0.052477",\
+ "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\
+ "0.378069, 0.378057, 0.378012, 0.377917, 0.377724",\
+ "0.885437, 0.885434, 0.885401, 0.885305, 0.885113",\
+ "2.163117, 2.163121, 2.163169, 2.163310, 2.163594",\
+ "0.052266, 0.052274, 0.052301, 0.052359, 0.052477",\
+ "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\
+ "0.378069, 0.378057, 0.378012, 0.377917, 0.377724",\
+ "0.885437, 0.885434, 0.885401, 0.885305, 0.885113",\
+ "2.163117, 2.163121, 2.163169, 2.163310, 2.163594",\
+ "0.052266, 0.052276, 0.052301, 0.052360, 0.052477",\
+ "0.174376, 0.174369, 0.174352, 0.174311, 0.174230",\
+ "0.378069, 0.378052, 0.378011, 0.377916, 0.377724",\
+ "0.885437, 0.885432, 0.885400, 0.885305, 0.885113",\
+ "2.163117, 2.163123, 2.163170, 2.163311, 2.163594");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.740784, 0.994165, 1.284321, 1.804998, 2.846352",\
+ "0.794288, 1.047701, 1.337984, 1.858934, 2.900834",\
+ "0.855205, 1.108643, 1.399026, 1.920190, 2.962518",\
+ "0.989902, 1.243338, 1.533712, 2.054859, 3.097151",\
+ "1.336325, 1.589748, 1.880072, 2.401109, 3.443183",\
+ "0.828197, 1.081704, 1.372052, 1.891713, 2.932285",\
+ "0.881701, 1.135240, 1.425716, 1.945649, 2.986768",\
+ "0.942617, 1.196183, 1.486758, 2.006905, 3.048452",\
+ "1.077314, 1.330878, 1.621445, 2.141573, 3.183085",\
+ "1.423737, 1.677287, 1.967804, 2.487824, 3.529117",\
+ "0.909070, 1.170669, 1.460019, 1.979335, 3.019240",\
+ "0.962574, 1.224207, 1.513683, 2.033271, 3.073723",\
+ "1.023490, 1.285149, 1.574726, 2.094527, 3.135407",\
+ "1.158187, 1.419844, 1.709412, 2.229196, 3.270040",\
+ "1.504610, 1.766254, 2.055771, 2.575446, 3.616072",\
+ "0.967758, 1.236282, 1.524167, 2.043248, 3.082749",\
+ "1.021262, 1.289820, 1.577832, 2.097185, 3.137232",\
+ "1.082179, 1.350764, 1.638874, 2.158441, 3.198916",\
+ "1.216876, 1.485459, 1.773561, 2.293109, 3.333549",\
+ "1.563299, 1.831868, 2.119919, 2.639359, 3.679581",\
+ "1.299828, 1.600384, 1.876561, 2.392812, 3.428205",\
+ "1.353332, 1.653935, 1.930228, 2.446749, 3.482688",\
+ "1.414249, 1.714888, 1.991272, 2.508006, 3.544372",\
+ "1.548946, 1.849582, 2.125958, 2.642674, 3.679005",\
+ "1.895369, 2.195986, 2.472316, 2.988924, 4.025037");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.060356, 0.060405, 0.060595, 0.061007, 0.061830",\
+ "0.114429, 0.114496, 0.114756, 0.115316, 0.116436",\
+ "0.200095, 0.200156, 0.200394, 0.200905, 0.201928",\
+ "0.445532, 0.445539, 0.445566, 0.445623, 0.445737",\
+ "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\
+ "0.060356, 0.060405, 0.060597, 0.061007, 0.061830",\
+ "0.114429, 0.114496, 0.114758, 0.115316, 0.116436",\
+ "0.200095, 0.200157, 0.200396, 0.200905, 0.201928",\
+ "0.445532, 0.445539, 0.445566, 0.445623, 0.445737",\
+ "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\
+ "0.060356, 0.060406, 0.060597, 0.061007, 0.061830",\
+ "0.114429, 0.114498, 0.114758, 0.115316, 0.116436",\
+ "0.200095, 0.200158, 0.200396, 0.200905, 0.201928",\
+ "0.445532, 0.445539, 0.445566, 0.445623, 0.445737",\
+ "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\
+ "0.060356, 0.060408, 0.060597, 0.061007, 0.061830",\
+ "0.114429, 0.114500, 0.114758, 0.115316, 0.116436",\
+ "0.200095, 0.200160, 0.200396, 0.200905, 0.201928",\
+ "0.445532, 0.445540, 0.445566, 0.445623, 0.445737",\
+ "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\
+ "0.060356, 0.060425, 0.060601, 0.061009, 0.061830",\
+ "0.114429, 0.114524, 0.114764, 0.115319, 0.116436",\
+ "0.200095, 0.200182, 0.200401, 0.200907, 0.201928",\
+ "0.445532, 0.445542, 0.445567, 0.445623, 0.445737",\
+ "1.101415, 1.101411, 1.101399, 1.101373, 1.101320");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2628*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[29]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.793277, 1.039130, 1.319023, 1.798101, 2.756257",\
+ "0.839819, 1.085675, 1.365575, 1.844669, 2.802857",\
+ "0.925498, 1.171358, 1.451280, 1.930420, 2.888700",\
+ "1.148884, 1.394753, 1.674707, 2.153918, 3.112340",\
+ "1.712918, 1.958797, 2.238793, 2.718097, 3.676705",\
+ "0.880682, 1.126695, 1.406620, 1.884815, 2.842191",\
+ "0.927225, 1.173240, 1.453171, 1.931383, 2.888791",\
+ "1.012903, 1.258923, 1.538876, 2.017133, 2.974633",\
+ "1.236289, 1.482318, 1.762303, 2.240632, 3.198274",\
+ "1.800323, 2.046363, 2.326390, 2.804811, 3.762639",\
+ "0.961504, 1.215685, 1.494583, 1.972436, 2.929146",\
+ "1.008047, 1.262229, 1.541135, 2.019004, 2.975746",\
+ "1.093725, 1.347913, 1.626839, 2.104754, 3.061589",\
+ "1.317111, 1.571308, 1.850267, 2.328253, 3.285229",\
+ "1.881145, 2.135353, 2.414354, 2.892432, 3.849594",\
+ "1.019140, 1.281331, 1.558724, 2.036349, 2.992655",\
+ "1.065682, 1.327876, 1.605276, 2.082916, 3.039255",\
+ "1.151360, 1.413560, 1.690981, 2.168667, 3.125098",\
+ "1.374747, 1.636955, 1.914408, 2.392166, 3.348738",\
+ "1.938781, 2.201000, 2.478495, 2.956345, 3.913103",\
+ "1.348815, 1.645927, 1.910691, 2.385732, 3.338111",\
+ "1.395358, 1.692472, 1.957243, 2.432300, 3.384711",\
+ "1.481036, 1.778158, 2.042948, 2.518051, 3.470554",\
+ "1.704422, 2.001556, 2.266376, 2.741550, 3.694194",\
+ "2.268456, 2.565605, 2.830464, 3.305729, 4.258559");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\
+ "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\
+ "0.378072, 0.378063, 0.378028, 0.377953, 0.377801",\
+ "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\
+ "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\
+ "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\
+ "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\
+ "0.378072, 0.378063, 0.378028, 0.377953, 0.377801",\
+ "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\
+ "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\
+ "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\
+ "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\
+ "0.378072, 0.378063, 0.378028, 0.377953, 0.377801",\
+ "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\
+ "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\
+ "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\
+ "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\
+ "0.378072, 0.378062, 0.378028, 0.377953, 0.377801",\
+ "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\
+ "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\
+ "0.052265, 0.052272, 0.052292, 0.052338, 0.052430",\
+ "0.174378, 0.174372, 0.174359, 0.174327, 0.174262",\
+ "0.378072, 0.378059, 0.378027, 0.377952, 0.377801",\
+ "0.885436, 0.885430, 0.885396, 0.885299, 0.885105",\
+ "2.163117, 2.163126, 2.163177, 2.163319, 2.163605");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.731449, 0.977276, 1.257067, 1.735920, 2.693626",\
+ "0.784944, 1.030796, 1.310685, 1.789754, 2.747891",\
+ "0.845853, 1.091725, 1.371691, 1.850929, 2.809405",\
+ "0.980551, 1.226421, 1.506381, 1.985605, 2.944052",\
+ "1.326977, 1.572838, 1.852758, 2.331896, 3.290171",\
+ "0.818854, 1.064841, 1.344662, 1.822633, 2.779559",\
+ "0.872349, 1.118361, 1.398281, 1.876467, 2.833825",\
+ "0.933258, 1.179290, 1.459288, 1.937643, 2.895339",\
+ "1.067956, 1.313987, 1.593977, 2.072318, 3.029986",\
+ "1.414383, 1.660403, 1.940354, 2.418609, 3.376105",\
+ "0.899676, 1.153830, 1.432626, 1.910254, 2.866514",\
+ "0.953171, 1.207350, 1.486244, 1.964088, 2.920780",\
+ "1.014081, 1.268280, 1.547251, 2.025264, 2.982294",\
+ "1.148778, 1.402976, 1.681941, 2.159939, 3.116941",\
+ "1.495205, 1.749392, 2.028318, 2.506230, 3.463060",\
+ "0.957311, 1.219475, 1.496767, 1.974167, 2.930023",\
+ "1.010806, 1.272997, 1.550386, 2.028001, 2.984289",\
+ "1.071716, 1.333927, 1.611393, 2.089177, 3.045803",\
+ "1.206414, 1.468623, 1.746082, 2.223852, 3.180450",\
+ "1.552840, 1.815039, 2.092459, 2.570143, 3.526569",\
+ "1.286987, 1.584062, 1.848731, 2.323550, 3.275480",\
+ "1.340482, 1.637592, 1.902352, 2.377385, 3.329745",\
+ "1.401392, 1.698529, 1.963361, 2.438561, 3.391259",\
+ "1.536089, 1.833225, 2.098050, 2.573236, 3.525906",\
+ "1.882516, 2.179637, 2.444427, 2.919527, 3.872025");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.060343, 0.060380, 0.060528, 0.060852, 0.061502",\
+ "0.114411, 0.114462, 0.114664, 0.115106, 0.115991",\
+ "0.200079, 0.200126, 0.200310, 0.200714, 0.201522",\
+ "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\
+ "1.101416, 1.101414, 1.101404, 1.101383, 1.101341",\
+ "0.060343, 0.060381, 0.060529, 0.060852, 0.061502",\
+ "0.114411, 0.114463, 0.114665, 0.115106, 0.115991",\
+ "0.200079, 0.200126, 0.200311, 0.200714, 0.201522",\
+ "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\
+ "1.101416, 1.101414, 1.101404, 1.101383, 1.101341",\
+ "0.060343, 0.060382, 0.060529, 0.060852, 0.061502",\
+ "0.114411, 0.114464, 0.114665, 0.115106, 0.115991",\
+ "0.200079, 0.200127, 0.200311, 0.200714, 0.201522",\
+ "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\
+ "1.101416, 1.101413, 1.101404, 1.101383, 1.101341",\
+ "0.060343, 0.060383, 0.060529, 0.060852, 0.061502",\
+ "0.114411, 0.114465, 0.114665, 0.115106, 0.115991",\
+ "0.200079, 0.200128, 0.200311, 0.200714, 0.201522",\
+ "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\
+ "1.101416, 1.101413, 1.101404, 1.101383, 1.101341",\
+ "0.060343, 0.060396, 0.060532, 0.060854, 0.061502",\
+ "0.114411, 0.114483, 0.114670, 0.115108, 0.115991",\
+ "0.200079, 0.200145, 0.200315, 0.200715, 0.201522",\
+ "0.445531, 0.445538, 0.445557, 0.445602, 0.445692",\
+ "1.101416, 1.101413, 1.101404, 1.101383, 1.101341");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2679*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[31]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.704078, 0.962448, 1.254543, 1.772415, 2.808159",\
+ "0.750305, 1.008676, 1.300771, 1.818645, 2.854393",\
+ "0.834537, 1.092907, 1.385001, 1.902873, 2.938617",\
+ "1.055475, 1.313845, 1.605937, 2.123804, 3.159536",\
+ "1.615778, 1.874147, 2.166233, 2.684084, 3.719787",\
+ "0.791487, 1.050012, 1.342263, 1.859129, 2.894093",\
+ "0.837714, 1.096239, 1.388491, 1.905359, 2.940326",\
+ "0.921945, 1.180470, 1.472721, 1.989588, 3.024551",\
+ "1.142884, 1.401409, 1.693658, 2.210518, 3.245470",\
+ "1.703187, 1.961710, 2.253953, 2.770799, 3.805721",\
+ "0.872371, 1.139015, 1.430229, 1.946751, 2.981048",\
+ "0.918598, 1.185243, 1.476457, 1.992981, 3.027281",\
+ "1.002829, 1.269474, 1.560688, 2.077209, 3.111506",\
+ "1.223768, 1.490412, 1.781624, 2.298140, 3.332425",\
+ "1.784070, 2.050714, 2.341920, 2.858420, 3.892676",\
+ "0.932831, 1.204683, 1.494377, 2.010664, 3.044557",\
+ "0.979058, 1.250910, 1.540605, 2.056894, 3.090790",\
+ "1.063289, 1.335141, 1.624835, 2.141123, 3.175015",\
+ "1.284228, 1.556080, 1.845772, 2.362053, 3.395934",\
+ "1.844531, 2.116381, 2.406067, 2.922334, 3.956185",\
+ "1.268348, 1.569475, 1.846740, 2.360211, 3.390013",\
+ "1.314575, 1.615702, 1.892967, 2.406441, 3.436246",\
+ "1.398806, 1.699933, 1.977198, 2.490670, 3.520471",\
+ "1.619745, 1.920872, 2.198134, 2.711600, 3.741390",\
+ "2.180047, 2.481173, 2.758430, 3.271881, 4.301641");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\
+ "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\
+ "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\
+ "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\
+ "2.162832, 2.162841, 2.162898, 2.163049, 2.163351",\
+ "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\
+ "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\
+ "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\
+ "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\
+ "2.162832, 2.162841, 2.162899, 2.163049, 2.163351",\
+ "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\
+ "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\
+ "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\
+ "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\
+ "2.162832, 2.162841, 2.162899, 2.163049, 2.163351",\
+ "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\
+ "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\
+ "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\
+ "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\
+ "2.162832, 2.162841, 2.162899, 2.163049, 2.163351",\
+ "0.053020, 0.053022, 0.053033, 0.053061, 0.053117",\
+ "0.178801, 0.178805, 0.178823, 0.178870, 0.178965",\
+ "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\
+ "0.885630, 0.885621, 0.885584, 0.885482, 0.885278",\
+ "2.162832, 2.162845, 2.162900, 2.163050, 2.163351");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.653096, 0.911470, 1.203587, 1.721520, 2.757385",\
+ "0.695785, 0.954155, 1.246248, 1.764117, 2.799856",\
+ "0.751534, 1.009904, 1.301996, 1.819860, 2.855588",\
+ "0.887244, 1.145615, 1.437709, 1.955581, 2.991326",\
+ "1.236608, 1.494979, 1.787076, 2.304955, 3.340714",\
+ "0.740505, 0.999033, 1.291307, 1.808234, 2.843319",\
+ "0.783194, 1.041719, 1.333969, 1.850832, 2.885789",\
+ "0.838943, 1.097468, 1.389716, 1.906574, 2.941522",\
+ "0.974653, 1.233178, 1.525429, 2.042296, 3.077260",\
+ "1.324017, 1.582542, 1.874796, 2.391670, 3.426647",\
+ "0.821388, 1.088037, 1.379274, 1.895856, 2.930274",\
+ "0.864078, 1.130722, 1.421935, 1.938454, 2.972744",\
+ "0.919827, 1.186471, 1.477682, 1.994196, 3.028477",\
+ "1.055537, 1.322181, 1.613395, 2.129917, 3.164215",\
+ "1.404901, 1.671546, 1.962763, 2.479291, 3.513602",\
+ "0.881849, 1.153705, 1.443422, 1.959769, 2.993783",\
+ "0.924538, 1.196390, 1.486083, 2.002367, 3.036253",\
+ "0.980287, 1.252139, 1.541830, 2.058109, 3.091986",\
+ "1.115997, 1.387849, 1.677543, 2.193830, 3.227724",\
+ "1.465361, 1.737213, 2.026911, 2.543204, 3.577111",\
+ "1.217365, 1.518498, 1.795785, 2.309317, 3.339239",\
+ "1.260055, 1.561182, 1.838445, 2.351914, 3.381710",\
+ "1.315804, 1.616930, 1.894192, 2.407657, 3.437442",\
+ "1.451514, 1.752641, 2.029906, 2.543378, 3.573180",\
+ "1.800878, 2.102005, 2.379273, 2.892752, 3.922567");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\
+ "0.095119, 0.095114, 0.095079, 0.094989, 0.094807",\
+ "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\
+ "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\
+ "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\
+ "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\
+ "0.095119, 0.095114, 0.095079, 0.094989, 0.094807",\
+ "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\
+ "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\
+ "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\
+ "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\
+ "0.095119, 0.095114, 0.095079, 0.094989, 0.094807",\
+ "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\
+ "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\
+ "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\
+ "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\
+ "0.095119, 0.095113, 0.095079, 0.094989, 0.094807",\
+ "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\
+ "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\
+ "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\
+ "0.046012, 0.046003, 0.045967, 0.045868, 0.045670",\
+ "0.095119, 0.095111, 0.095078, 0.094988, 0.094807",\
+ "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\
+ "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\
+ "1.101604, 1.101603, 1.101601, 1.101596, 1.101585");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[33]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.687749, 0.939290, 1.220370, 1.693212, 2.638895",\
+ "0.733976, 0.985517, 1.266598, 1.739441, 2.685128",\
+ "0.818208, 1.069748, 1.350828, 1.823670, 2.769354",\
+ "1.039147, 1.290687, 1.571764, 2.044601, 2.990274",\
+ "1.599449, 1.850988, 2.132060, 2.604883, 3.550529",\
+ "0.775154, 1.026875, 1.307946, 1.779925, 2.724829",\
+ "0.821381, 1.073102, 1.354175, 1.826155, 2.771062",\
+ "0.905613, 1.157333, 1.438405, 1.910384, 2.855288",\
+ "1.126552, 1.378272, 1.659341, 2.131315, 3.076208",\
+ "1.686854, 1.938572, 2.219636, 2.691597, 3.636462",\
+ "0.855968, 1.115908, 1.395910, 1.867546, 2.811784",\
+ "0.902195, 1.162135, 1.442138, 1.913776, 2.858017",\
+ "0.986426, 1.246367, 1.526368, 1.998005, 2.942243",\
+ "1.207365, 1.467305, 1.747304, 2.218936, 3.163163",\
+ "1.767667, 2.027606, 2.307599, 2.779218, 3.723417",\
+ "0.913586, 1.181618, 1.460050, 1.931459, 2.875293",\
+ "0.959814, 1.227846, 1.506278, 1.977689, 2.921526",\
+ "1.044045, 1.312077, 1.590508, 2.061918, 3.005752",\
+ "1.264984, 1.533015, 1.811444, 2.282849, 3.226672",\
+ "1.825286, 2.093316, 2.371740, 2.843130, 3.786926",\
+ "1.247292, 1.546964, 1.811953, 2.280817, 3.220749",\
+ "1.293519, 1.593192, 1.858181, 2.327047, 3.266982",\
+ "1.377751, 1.677423, 1.942412, 2.411276, 3.351208",\
+ "1.598690, 1.898361, 2.163348, 2.632206, 3.572128",\
+ "2.158992, 2.458661, 2.723643, 3.192488, 4.132382");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\
+ "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\
+ "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\
+ "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\
+ "2.162833, 2.162845, 2.162902, 2.163039, 2.163313",\
+ "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\
+ "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\
+ "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\
+ "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\
+ "2.162833, 2.162845, 2.162903, 2.163039, 2.163313",\
+ "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\
+ "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\
+ "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\
+ "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\
+ "2.162833, 2.162846, 2.162903, 2.163039, 2.163313",\
+ "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\
+ "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\
+ "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\
+ "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\
+ "2.162833, 2.162846, 2.162903, 2.163039, 2.163313",\
+ "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\
+ "0.178802, 0.178807, 0.178824, 0.178867, 0.178953",\
+ "0.381846, 0.381848, 0.381856, 0.381876, 0.381916",\
+ "0.885629, 0.885618, 0.885581, 0.885489, 0.885303",\
+ "2.162833, 2.162850, 2.162904, 2.163039, 2.163313");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.636768, 0.888313, 1.169416, 1.642313, 2.588106",\
+ "0.679456, 0.930997, 1.212076, 1.684915, 2.630593",\
+ "0.735206, 0.986745, 1.267823, 1.740657, 2.686327",\
+ "0.870915, 1.122456, 1.403536, 1.876378, 2.822062",\
+ "1.220279, 1.471821, 1.752903, 2.225752, 3.171448",\
+ "0.724173, 0.975898, 1.256993, 1.729026, 2.674040",\
+ "0.766861, 1.018582, 1.299652, 1.771628, 2.716527",\
+ "0.822611, 1.074330, 1.355399, 1.827371, 2.772260",\
+ "0.958320, 1.210041, 1.491113, 1.963092, 2.907996",\
+ "1.307685, 1.559406, 1.840480, 2.312465, 3.257382",\
+ "0.804986, 1.064932, 1.344956, 1.816648, 2.760995",\
+ "0.847675, 1.107615, 1.387615, 1.859249, 2.803482",\
+ "0.903424, 1.163364, 1.443362, 1.914992, 2.859215",\
+ "1.039134, 1.299074, 1.579076, 2.050713, 2.994951",\
+ "1.388498, 1.648439, 1.928443, 2.400086, 3.344337",\
+ "0.862605, 1.130642, 1.409096, 1.880560, 2.824504",\
+ "0.905293, 1.173325, 1.451756, 1.923162, 2.866991",\
+ "0.961043, 1.229074, 1.507503, 1.978905, 2.922724",\
+ "1.096752, 1.364785, 1.643216, 2.114626, 3.058460",\
+ "1.446117, 1.714149, 1.992583, 2.463999, 3.407846",\
+ "1.196311, 1.495989, 1.761000, 2.229918, 3.169960",\
+ "1.238999, 1.538671, 1.803659, 2.272520, 3.212447",\
+ "1.294749, 1.594420, 1.859406, 2.328263, 3.268181",\
+ "1.430458, 1.730130, 1.995120, 2.463984, 3.403916",\
+ "1.779823, 2.079495, 2.344487, 2.813357, 3.753302");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.046010, 0.046003, 0.045965, 0.045875, 0.045695",\
+ "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\
+ "0.188959, 0.188960, 0.188961, 0.188966, 0.188974",\
+ "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\
+ "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\
+ "0.046010, 0.046002, 0.045965, 0.045875, 0.045695",\
+ "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\
+ "0.188959, 0.188960, 0.188961, 0.188966, 0.188974",\
+ "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\
+ "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\
+ "0.046010, 0.046002, 0.045965, 0.045875, 0.045695",\
+ "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\
+ "0.188959, 0.188960, 0.188961, 0.188966, 0.188974",\
+ "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\
+ "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\
+ "0.046010, 0.046002, 0.045965, 0.045875, 0.045695",\
+ "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\
+ "0.188959, 0.188960, 0.188962, 0.188966, 0.188974",\
+ "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\
+ "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\
+ "0.046010, 0.045999, 0.045964, 0.045875, 0.045695",\
+ "0.095118, 0.095108, 0.095076, 0.094994, 0.094830",\
+ "0.188959, 0.188960, 0.188962, 0.188966, 0.188974",\
+ "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\
+ "1.101604, 1.101603, 1.101601, 1.101596, 1.101586");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2370*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[34]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.622933, 0.904214, 1.205191, 1.719790, 2.748989",\
+ "0.669468, 0.950758, 1.251803, 1.766599, 2.796192",\
+ "0.755125, 1.036441, 1.337680, 1.853039, 2.883759",\
+ "0.978478, 1.259834, 1.561373, 2.077602, 3.110059",\
+ "1.542469, 1.823877, 2.125806, 2.643168, 3.677893",\
+ "0.710344, 0.991835, 1.292902, 1.806505, 2.834923",\
+ "0.756879, 1.038379, 1.339514, 1.853314, 2.882126",\
+ "0.842536, 1.124062, 1.425393, 1.939754, 2.969692",\
+ "1.065890, 1.347456, 1.649089, 2.164316, 3.195993",\
+ "1.629880, 1.911499, 2.213525, 2.729883, 3.763827",\
+ "0.799646, 1.080982, 1.380869, 1.894127, 2.921878",\
+ "0.846182, 1.127527, 1.427481, 1.940936, 2.969081",\
+ "0.931839, 1.213210, 1.513360, 2.027376, 3.056648",\
+ "1.155193, 1.436604, 1.737056, 2.251938, 3.282948",\
+ "1.719185, 2.000648, 2.301492, 2.817505, 3.850782",\
+ "0.863267, 1.146859, 1.445016, 1.958041, 2.985387",\
+ "0.909803, 1.193403, 1.491629, 2.004849, 3.032590",\
+ "0.995460, 1.279087, 1.577507, 2.091290, 3.120157",\
+ "1.218815, 1.502483, 1.801203, 2.315852, 3.346457",\
+ "1.782807, 2.066528, 2.365640, 2.881418, 3.914291",\
+ "1.199521, 1.514063, 1.797347, 2.307577, 3.330843",\
+ "1.246057, 1.560610, 1.843961, 2.354387, 3.378046",\
+ "1.331717, 1.646302, 1.929846, 2.440829, 3.465612",\
+ "1.555075, 1.869709, 2.153550, 2.665395, 3.691913",\
+ "2.119071, 2.433770, 2.717999, 3.230966, 4.259747");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.052243, 0.052269, 0.054671, 0.062895, 0.079343",\
+ "0.174393, 0.174375, 0.174239, 0.173844, 0.173056",\
+ "0.378107, 0.378064, 0.377824, 0.377171, 0.375864",\
+ "0.885321, 0.885201, 0.884881, 0.884213, 0.882876",\
+ "2.163287, 2.163464, 2.163713, 2.163931, 2.164366",\
+ "0.052243, 0.052269, 0.054697, 0.062895, 0.079343",\
+ "0.174393, 0.174374, 0.174237, 0.173844, 0.173056",\
+ "0.378107, 0.378064, 0.377822, 0.377171, 0.375864",\
+ "0.885321, 0.885200, 0.884879, 0.884213, 0.882876",\
+ "2.163287, 2.163465, 2.163714, 2.163931, 2.164366",\
+ "0.052243, 0.052270, 0.054697, 0.062895, 0.079343",\
+ "0.174392, 0.174374, 0.174237, 0.173844, 0.173056",\
+ "0.378106, 0.378063, 0.377822, 0.377171, 0.375864",\
+ "0.885318, 0.885198, 0.884879, 0.884213, 0.882876",\
+ "2.163292, 2.163468, 2.163714, 2.163931, 2.164366",\
+ "0.052244, 0.052270, 0.054698, 0.062895, 0.079343",\
+ "0.174392, 0.174374, 0.174237, 0.173844, 0.173056",\
+ "0.378106, 0.378062, 0.377822, 0.377171, 0.375864",\
+ "0.885315, 0.885196, 0.884879, 0.884213, 0.882876",\
+ "2.163296, 2.163471, 2.163714, 2.163931, 2.164366",\
+ "0.052246, 0.052278, 0.054782, 0.062929, 0.079343",\
+ "0.174391, 0.174368, 0.174233, 0.173843, 0.173056",\
+ "0.378102, 0.378049, 0.377815, 0.377168, 0.375864",\
+ "0.885300, 0.885164, 0.884872, 0.884210, 0.882876",\
+ "2.163318, 2.163518, 2.163716, 2.163932, 2.164366");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.561209, 0.842364, 1.145718, 1.669104, 2.715876",\
+ "0.614604, 0.895880, 1.196912, 1.711724, 2.741347",\
+ "0.675435, 0.956806, 1.258457, 1.775014, 2.808127",\
+ "0.810139, 1.091502, 1.393093, 1.909477, 2.942242",\
+ "1.156606, 1.437920, 1.739149, 2.254480, 3.285141",\
+ "0.648620, 0.929984, 1.233457, 1.755819, 2.801810",\
+ "0.702015, 0.983501, 1.284623, 1.798438, 2.827281",\
+ "0.762846, 1.044428, 1.346174, 1.861729, 2.894061",\
+ "0.897551, 1.179124, 1.480810, 1.996191, 3.028176",\
+ "1.244017, 1.525542, 1.826863, 2.341195, 3.371075",\
+ "0.737920, 1.019129, 1.321424, 1.843441, 2.888765",\
+ "0.791317, 1.072648, 1.372590, 1.886060, 2.914236",\
+ "0.852150, 1.133576, 1.434141, 1.949351, 2.981016",\
+ "0.986854, 1.268272, 1.568777, 2.083813, 3.115131",\
+ "1.333320, 1.614689, 1.914829, 2.428817, 3.458030",\
+ "0.801540, 1.085002, 1.385573, 1.907354, 2.952274",\
+ "0.854938, 1.138524, 1.436738, 1.949974, 2.977745",\
+ "0.915772, 1.199455, 1.498289, 2.013264, 3.044525",\
+ "1.050476, 1.334151, 1.632925, 2.147727, 3.178640",\
+ "1.396941, 1.680567, 1.978977, 2.492730, 3.521539",\
+ "1.137784, 1.452168, 1.737993, 2.256927, 3.297729",\
+ "1.191192, 1.505727, 1.789070, 2.299511, 3.323201",\
+ "1.252033, 1.566686, 1.850639, 2.362809, 3.389981",\
+ "1.386736, 1.701380, 1.985273, 2.497271, 3.524096",\
+ "1.733197, 2.047781, 2.331315, 2.842270, 3.866995");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.060194, 0.060374, 0.061744, 0.065730, 0.073703",\
+ "0.114206, 0.114454, 0.116316, 0.121721, 0.132532",\
+ "0.199891, 0.200118, 0.201818, 0.206753, 0.216623",\
+ "0.445510, 0.445535, 0.445725, 0.446277, 0.447381",\
+ "1.101426, 1.101414, 1.101326, 1.101071, 1.100560",\
+ "0.060194, 0.060375, 0.061757, 0.065730, 0.073703",\
+ "0.114206, 0.114455, 0.116333, 0.121721, 0.132532",\
+ "0.199891, 0.200119, 0.201834, 0.206753, 0.216623",\
+ "0.445510, 0.445535, 0.445727, 0.446277, 0.447381",\
+ "1.101426, 1.101414, 1.101325, 1.101071, 1.100560",\
+ "0.060197, 0.060379, 0.061757, 0.065730, 0.073703",\
+ "0.114210, 0.114460, 0.116333, 0.121721, 0.132532",\
+ "0.199895, 0.200123, 0.201834, 0.206753, 0.216623",\
+ "0.445510, 0.445535, 0.445727, 0.446277, 0.447381",\
+ "1.101426, 1.101414, 1.101325, 1.101071, 1.100560",\
+ "0.060200, 0.060383, 0.061757, 0.065730, 0.073703",\
+ "0.114213, 0.114466, 0.116334, 0.121721, 0.132532",\
+ "0.199898, 0.200129, 0.201835, 0.206753, 0.216623",\
+ "0.445510, 0.445536, 0.445727, 0.446277, 0.447381",\
+ "1.101425, 1.101413, 1.101325, 1.101071, 1.100560",\
+ "0.060213, 0.060438, 0.061798, 0.065747, 0.073703",\
+ "0.114232, 0.114541, 0.116389, 0.121744, 0.132532",\
+ "0.199915, 0.200198, 0.201885, 0.206773, 0.216623",\
+ "0.445512, 0.445544, 0.445733, 0.446279, 0.447381",\
+ "1.101425, 1.101410, 1.101323, 1.101070, 1.100560");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2367*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[41]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.746470, 1.014882, 1.306808, 1.802638, 2.794297",\
+ "0.792702, 1.061114, 1.353041, 1.848873, 2.840536",\
+ "0.876929, 1.145341, 1.437267, 1.933097, 2.924756",\
+ "1.097854, 1.366266, 1.658190, 2.154013, 3.145659",\
+ "1.658121, 1.926532, 2.218450, 2.714257, 3.705872",\
+ "0.833878, 1.102487, 1.394459, 1.889352, 2.880230",\
+ "0.880110, 1.148719, 1.440691, 1.935587, 2.926469",\
+ "0.964337, 1.232946, 1.524917, 2.019811, 3.010689",\
+ "1.185262, 1.453871, 1.745840, 2.240727, 3.231593",\
+ "1.745530, 2.014137, 2.306100, 2.800972, 3.791806",\
+ "0.914792, 1.191581, 1.482424, 1.976974, 2.967185",\
+ "0.961024, 1.237813, 1.528656, 2.023208, 3.013424",\
+ "1.045251, 1.322040, 1.612882, 2.107432, 3.097644",\
+ "1.266176, 1.542965, 1.833805, 2.328349, 3.318548",\
+ "1.826444, 2.103231, 2.394065, 2.888593, 3.878761",\
+ "0.976718, 1.257380, 1.546568, 2.040887, 3.030694",\
+ "1.022949, 1.303612, 1.592801, 2.087121, 3.076933",\
+ "1.107176, 1.387838, 1.677027, 2.171345, 3.161153",\
+ "1.328102, 1.608763, 1.897949, 2.392262, 3.382057",\
+ "1.888369, 2.169030, 2.458210, 2.952506, 3.942270",\
+ "1.314895, 1.623717, 1.898706, 2.390343, 3.376151",\
+ "1.361127, 1.669949, 1.944939, 2.436577, 3.422390",\
+ "1.445354, 1.754176, 2.029165, 2.520801, 3.506609",\
+ "1.666279, 1.975101, 2.250087, 2.741717, 3.727513",\
+ "2.226547, 2.535367, 2.810348, 3.301962, 4.287725");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\
+ "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\
+ "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\
+ "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\
+ "2.163183, 2.163193, 2.163255, 2.163418, 2.163742",\
+ "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\
+ "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\
+ "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\
+ "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\
+ "2.163183, 2.163194, 2.163256, 2.163418, 2.163742",\
+ "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\
+ "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\
+ "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\
+ "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\
+ "2.163183, 2.163194, 2.163256, 2.163418, 2.163742",\
+ "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\
+ "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\
+ "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\
+ "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\
+ "2.163183, 2.163194, 2.163256, 2.163418, 2.163742",\
+ "0.053085, 0.053088, 0.053099, 0.053129, 0.053189",\
+ "0.178912, 0.178916, 0.178935, 0.178986, 0.179088",\
+ "0.381897, 0.381899, 0.381907, 0.381931, 0.381978",\
+ "0.885391, 0.885382, 0.885341, 0.885232, 0.885012",\
+ "2.163183, 2.163198, 2.163258, 2.163418, 2.163742");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.695629, 0.964045, 1.256010, 1.751953, 2.743838",\
+ "0.738170, 1.006582, 1.298507, 1.794334, 2.785986",\
+ "0.793908, 1.062320, 1.354243, 1.850064, 2.841706",\
+ "0.929637, 1.198049, 1.489976, 1.985806, 2.977466",\
+ "1.279017, 1.547430, 1.839359, 2.335196, 3.326870",\
+ "0.783037, 1.051650, 1.343661, 1.838667, 2.829772",\
+ "0.825579, 1.094187, 1.386158, 1.881048, 2.871920",\
+ "0.881317, 1.149925, 1.441893, 1.936778, 2.927640",\
+ "1.017045, 1.285654, 1.577626, 2.072520, 3.063399",\
+ "1.366425, 1.635035, 1.927009, 2.421910, 3.412804",\
+ "0.863951, 1.140744, 1.431626, 1.926289, 2.916727",\
+ "0.906492, 1.183281, 1.474123, 1.968669, 2.958875",\
+ "0.962231, 1.239019, 1.529858, 2.024400, 3.014595",\
+ "1.097959, 1.374748, 1.665591, 2.160141, 3.150354",\
+ "1.447339, 1.724128, 2.014974, 2.509532, 3.499759",\
+ "0.925877, 1.206543, 1.495770, 1.990202, 2.980236",\
+ "0.968418, 1.249080, 1.538267, 2.032583, 3.022384",\
+ "1.024156, 1.304818, 1.594002, 2.088313, 3.078104",\
+ "1.159885, 1.440547, 1.729735, 2.224055, 3.213863",\
+ "1.509265, 1.789927, 2.079118, 2.573445, 3.563268",\
+ "1.264054, 1.572882, 1.847910, 2.339658, 3.325692",\
+ "1.306595, 1.615417, 1.890405, 2.382038, 3.367840",\
+ "1.362333, 1.671155, 1.946141, 2.437769, 3.423560",\
+ "1.498062, 1.806884, 2.081874, 2.573510, 3.559319",\
+ "1.847442, 2.156265, 2.431257, 2.922901, 3.908724");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.045780, 0.045773, 0.045733, 0.045626, 0.045413",\
+ "0.094908, 0.094902, 0.094864, 0.094767, 0.094572",\
+ "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\
+ "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\
+ "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\
+ "0.045780, 0.045773, 0.045733, 0.045626, 0.045413",\
+ "0.094908, 0.094902, 0.094864, 0.094767, 0.094572",\
+ "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\
+ "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\
+ "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\
+ "0.045780, 0.045773, 0.045733, 0.045626, 0.045413",\
+ "0.094908, 0.094901, 0.094864, 0.094767, 0.094572",\
+ "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\
+ "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\
+ "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\
+ "0.045780, 0.045773, 0.045732, 0.045626, 0.045413",\
+ "0.094908, 0.094901, 0.094864, 0.094767, 0.094572",\
+ "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\
+ "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\
+ "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\
+ "0.045780, 0.045771, 0.045731, 0.045626, 0.045413",\
+ "0.094908, 0.094899, 0.094863, 0.094766, 0.094572",\
+ "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\
+ "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\
+ "1.101591, 1.101591, 1.101588, 1.101583, 1.101571");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2564*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[42]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.720239, 0.982131, 1.267428, 1.744868, 2.699749",\
+ "0.766471, 1.028363, 1.313660, 1.791102, 2.745986",\
+ "0.850698, 1.112590, 1.397886, 1.875327, 2.830208",\
+ "1.071623, 1.333515, 1.618809, 2.096245, 3.051117",\
+ "1.631890, 1.893781, 2.179071, 2.656495, 3.611344",\
+ "0.807647, 1.069728, 1.355020, 1.831583, 2.785683",\
+ "0.853879, 1.115960, 1.401253, 1.877816, 2.831920",\
+ "0.938106, 1.200187, 1.485479, 1.962041, 2.916142",\
+ "1.159031, 1.421112, 1.706402, 2.182960, 3.137051",\
+ "1.719299, 1.981378, 2.266663, 2.743210, 3.697278",\
+ "0.888462, 1.158804, 1.442984, 1.919204, 2.872638",\
+ "0.934694, 1.205035, 1.489217, 1.965438, 2.918875",\
+ "1.018921, 1.289262, 1.573443, 2.049663, 3.003097",\
+ "1.239846, 1.510187, 1.794366, 2.270581, 3.224006",\
+ "1.800113, 2.070453, 2.354627, 2.830831, 3.784233",\
+ "0.949702, 1.224575, 1.507125, 1.983117, 2.936147",\
+ "0.995934, 1.270807, 1.553358, 2.029351, 2.982384",\
+ "1.080161, 1.355034, 1.637584, 2.113576, 3.066606",\
+ "1.301086, 1.575958, 1.858507, 2.334494, 3.287515",\
+ "1.861354, 2.136225, 2.418768, 2.894744, 3.847742",\
+ "1.285416, 1.590595, 1.859077, 2.332497, 3.281603",\
+ "1.331648, 1.636827, 1.905309, 2.378731, 3.327840",\
+ "1.415875, 1.721054, 1.989536, 2.462955, 3.412062",\
+ "1.636800, 1.941979, 2.210458, 2.683874, 3.632971",\
+ "2.197067, 2.502244, 2.770720, 3.244124, 4.193198");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\
+ "0.178912, 0.178915, 0.178931, 0.178968, 0.179043",\
+ "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\
+ "0.885390, 0.885384, 0.885350, 0.885270, 0.885109",\
+ "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\
+ "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\
+ "0.178912, 0.178915, 0.178931, 0.178968, 0.179043",\
+ "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\
+ "0.885390, 0.885384, 0.885350, 0.885270, 0.885109",\
+ "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\
+ "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\
+ "0.178912, 0.178916, 0.178931, 0.178968, 0.179043",\
+ "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\
+ "0.885390, 0.885383, 0.885350, 0.885270, 0.885109",\
+ "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\
+ "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\
+ "0.178912, 0.178916, 0.178931, 0.178968, 0.179043",\
+ "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\
+ "0.885390, 0.885383, 0.885350, 0.885270, 0.885109",\
+ "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\
+ "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\
+ "0.178912, 0.178917, 0.178931, 0.178968, 0.179043",\
+ "0.381897, 0.381899, 0.381906, 0.381923, 0.381957",\
+ "0.885390, 0.885381, 0.885349, 0.885270, 0.885109",\
+ "2.163185, 2.163199, 2.163245, 2.163363, 2.163599");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.669399, 0.931295, 1.216611, 1.694099, 2.649075",\
+ "0.711939, 0.973832, 1.259127, 1.736565, 2.691442",\
+ "0.767677, 1.029569, 1.314863, 1.792297, 2.747166",\
+ "0.903406, 1.165299, 1.450595, 1.928036, 2.882917",\
+ "1.252786, 1.514679, 1.799978, 2.277424, 3.232316",\
+ "0.756807, 1.018892, 1.304204, 1.780813, 2.735009",\
+ "0.799348, 1.061428, 1.346719, 1.823279, 2.777375",\
+ "0.855086, 1.117166, 1.402455, 1.879012, 2.833100",\
+ "0.990815, 1.252895, 1.538187, 2.014750, 2.968851",\
+ "1.340194, 1.602276, 1.887570, 2.364138, 3.318250",\
+ "0.837622, 1.107967, 1.392168, 1.868435, 2.821964",\
+ "0.880162, 1.150504, 1.434683, 1.910901, 2.864330",\
+ "0.935900, 1.206241, 1.490419, 1.966633, 2.920055",\
+ "1.071629, 1.341971, 1.626151, 2.102372, 3.055806",\
+ "1.421009, 1.691351, 1.975534, 2.451760, 3.405205",\
+ "0.898862, 1.173739, 1.456309, 1.932348, 2.885473",\
+ "0.941403, 1.216275, 1.498824, 1.974814, 2.927839",\
+ "0.997141, 1.272013, 1.554560, 2.030546, 2.983564",\
+ "1.132869, 1.407742, 1.690292, 2.166285, 3.119315",\
+ "1.482249, 1.757123, 2.039675, 2.515673, 3.468714",\
+ "1.234576, 1.539761, 1.808261, 2.281728, 3.230929",\
+ "1.277116, 1.582295, 1.850776, 2.324194, 3.273295",\
+ "1.332854, 1.638033, 1.906512, 2.379926, 3.329020",\
+ "1.468583, 1.773762, 2.042244, 2.515665, 3.464771",\
+ "1.817963, 2.123143, 2.391627, 2.865052, 3.814170");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.045779, 0.045773, 0.045741, 0.045663, 0.045507",\
+ "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\
+ "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\
+ "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\
+ "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\
+ "0.045779, 0.045773, 0.045740, 0.045663, 0.045507",\
+ "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\
+ "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\
+ "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\
+ "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\
+ "0.045779, 0.045773, 0.045740, 0.045663, 0.045507",\
+ "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\
+ "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\
+ "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\
+ "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\
+ "0.045779, 0.045772, 0.045740, 0.045663, 0.045507",\
+ "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\
+ "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\
+ "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\
+ "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\
+ "0.045779, 0.045770, 0.045740, 0.045662, 0.045507",\
+ "0.094907, 0.094898, 0.094871, 0.094800, 0.094658",\
+ "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\
+ "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\
+ "1.101591, 1.101590, 1.101589, 1.101584, 1.101576");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2515*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[45]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.505424, 0.768046, 1.055041, 1.540850, 2.512468",\
+ "0.551960, 0.814596, 1.101656, 1.587624, 2.559559",\
+ "0.637620, 0.900293, 1.187543, 1.673963, 2.646803",\
+ "0.860979, 1.123711, 1.411252, 1.898370, 2.872607",\
+ "1.424976, 1.687784, 1.975705, 2.463734, 3.439793",\
+ "0.593483, 0.855643, 1.142658, 1.627564, 2.598402",\
+ "0.640020, 0.902192, 1.189274, 1.674337, 2.645493",\
+ "0.725680, 0.987891, 1.275163, 1.760677, 2.732737",\
+ "0.949039, 1.211309, 1.498873, 1.985084, 2.958541",\
+ "1.513036, 1.775383, 2.063330, 2.550448, 3.525727",\
+ "0.682045, 0.944707, 1.230622, 1.715185, 2.685357",\
+ "0.728581, 0.991257, 1.277238, 1.761959, 2.732448",\
+ "0.814241, 1.076956, 1.363127, 1.848298, 2.819692",\
+ "1.037599, 1.300375, 1.586838, 2.072705, 3.045496",\
+ "1.601596, 1.864452, 2.151294, 2.638070, 3.612682",\
+ "0.745042, 1.010463, 1.294765, 1.779098, 2.748866",\
+ "0.791578, 1.057013, 1.341381, 1.825872, 2.795957",\
+ "0.877238, 1.142714, 1.427269, 1.912211, 2.883201",\
+ "1.100596, 1.366135, 1.650980, 2.136618, 3.109005",\
+ "1.664593, 1.930213, 2.215437, 2.701982, 3.676191",\
+ "1.077301, 1.376325, 1.646801, 2.128510, 3.094322",\
+ "1.123837, 1.422881, 1.693418, 2.175285, 3.141412",\
+ "1.209496, 1.508595, 1.779311, 2.261626, 3.228657",\
+ "1.432853, 1.732038, 2.003029, 2.486036, 3.454461",\
+ "1.996848, 2.296144, 2.567495, 3.051404, 4.021647");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.052246, 0.052286, 0.053457, 0.057279, 0.064922",\
+ "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\
+ "0.378101, 0.378105, 0.378105, 0.378105, 0.378105",\
+ "0.885463, 0.885472, 0.885472, 0.885472, 0.885472",\
+ "2.163077, 2.163087, 2.163255, 2.163786, 2.164848",\
+ "0.052246, 0.052286, 0.053469, 0.057279, 0.064922",\
+ "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\
+ "0.378101, 0.378105, 0.378105, 0.378105, 0.378105",\
+ "0.885464, 0.885472, 0.885472, 0.885472, 0.885472",\
+ "2.163077, 2.163087, 2.163257, 2.163786, 2.164848",\
+ "0.052246, 0.052287, 0.053469, 0.057279, 0.064922",\
+ "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\
+ "0.378102, 0.378105, 0.378105, 0.378105, 0.378105",\
+ "0.885464, 0.885472, 0.885472, 0.885472, 0.885472",\
+ "2.163077, 2.163087, 2.163257, 2.163786, 2.164848",\
+ "0.052246, 0.052288, 0.053470, 0.057279, 0.064922",\
+ "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\
+ "0.378102, 0.378105, 0.378105, 0.378105, 0.378105",\
+ "0.885465, 0.885472, 0.885472, 0.885472, 0.885472",\
+ "2.163077, 2.163087, 2.163257, 2.163786, 2.164848",\
+ "0.052246, 0.052302, 0.053509, 0.057295, 0.064922",\
+ "0.174391, 0.174392, 0.174392, 0.174392, 0.174392",\
+ "0.378103, 0.378105, 0.378105, 0.378105, 0.378105",\
+ "0.885469, 0.885472, 0.885472, 0.885472, 0.885472",\
+ "2.163077, 2.163090, 2.163262, 2.163788, 2.164848");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.443684, 0.706121, 0.992534, 1.477296, 2.446822",\
+ "0.497094, 0.759709, 1.046667, 1.532387, 2.503829",\
+ "0.557938, 0.820691, 1.108342, 1.595724, 2.570488",\
+ "0.692641, 0.955383, 1.242975, 1.730217, 2.704702",\
+ "1.039101, 1.301772, 1.589012, 2.075409, 3.048203",\
+ "0.531743, 0.793716, 1.080148, 1.564010, 2.532755",\
+ "0.585154, 0.847306, 1.134284, 1.619101, 2.589763",\
+ "0.645997, 0.908289, 1.195965, 1.682438, 2.656422",\
+ "0.780700, 1.042981, 1.330598, 1.816931, 2.790636",\
+ "1.127160, 1.389370, 1.676632, 2.162122, 3.134136",\
+ "0.620305, 0.882776, 1.168112, 1.651631, 2.619710",\
+ "0.673715, 0.936370, 1.222248, 1.706723, 2.676718",\
+ "0.734558, 0.997357, 1.283929, 1.770059, 2.743377",\
+ "0.869261, 1.132048, 1.418562, 1.904553, 2.877591",\
+ "1.215722, 1.478435, 1.764596, 2.249744, 3.221091",\
+ "0.683303, 0.948526, 1.232255, 1.715544, 2.683219",\
+ "0.736712, 1.002125, 1.286391, 1.770636, 2.740227",\
+ "0.797555, 1.063117, 1.348072, 1.833972, 2.806886",\
+ "0.932258, 1.197807, 1.482705, 1.968466, 2.941100",\
+ "1.278719, 1.544192, 1.828738, 2.313657, 3.284600",\
+ "1.015567, 1.314320, 1.584279, 2.064952, 3.028676",\
+ "1.068972, 1.367985, 1.638425, 2.120048, 3.085683",\
+ "1.129811, 1.429028, 1.700123, 2.183391, 3.152342",\
+ "1.264514, 1.563714, 1.834755, 2.317884, 3.286556",\
+ "1.610977, 1.910073, 2.180780, 2.663072, 3.630056");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.060218, 0.060490, 0.061813, 0.065017, 0.071424",\
+ "0.114238, 0.114613, 0.116413, 0.120756, 0.129442",\
+ "0.199921, 0.200263, 0.201907, 0.205872, 0.213802",\
+ "0.445513, 0.445551, 0.445735, 0.446179, 0.447066",\
+ "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\
+ "0.060218, 0.060493, 0.061823, 0.065017, 0.071424",\
+ "0.114238, 0.114616, 0.116427, 0.120756, 0.129442",\
+ "0.199921, 0.200266, 0.201919, 0.205872, 0.213802",\
+ "0.445513, 0.445551, 0.445736, 0.446179, 0.447066",\
+ "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\
+ "0.060218, 0.060498, 0.061824, 0.065017, 0.071424",\
+ "0.114238, 0.114624, 0.116427, 0.120756, 0.129442",\
+ "0.199921, 0.200273, 0.201920, 0.205872, 0.213802",\
+ "0.445513, 0.445552, 0.445736, 0.446179, 0.447066",\
+ "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\
+ "0.060218, 0.060507, 0.061824, 0.065017, 0.071424",\
+ "0.114238, 0.114635, 0.116428, 0.120756, 0.129442",\
+ "0.199921, 0.200284, 0.201920, 0.205872, 0.213802",\
+ "0.445513, 0.445553, 0.445737, 0.446179, 0.447066",\
+ "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\
+ "0.060218, 0.060603, 0.061857, 0.065030, 0.071424",\
+ "0.114238, 0.114768, 0.116472, 0.120774, 0.129442",\
+ "0.199921, 0.200405, 0.201961, 0.205888, 0.213802",\
+ "0.445513, 0.445567, 0.445741, 0.446180, 0.447066",\
+ "1.101424, 1.101424, 1.101424, 1.101424, 1.101424");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2700*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[16]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.378256, 0.565826, 0.756593, 1.054119, 1.624836",\
+ "0.428118, 0.615688, 0.806455, 1.103981, 1.674699",\
+ "0.529986, 0.717556, 0.908323, 1.205849, 1.776567",\
+ "0.767847, 0.955417, 1.146184, 1.443710, 2.014428",\
+ "1.340168, 1.527737, 1.718505, 2.016031, 2.586749",\
+ "0.466466, 0.653144, 0.843873, 1.141424, 1.712190",\
+ "0.516328, 0.703006, 0.893736, 1.191286, 1.762052",\
+ "0.618195, 0.804874, 0.995604, 1.293154, 1.863920",\
+ "0.856057, 1.042735, 1.233465, 1.531015, 2.101782",\
+ "1.428377, 1.615056, 1.805786, 2.103336, 2.674102",\
+ "0.553983, 0.733479, 0.923900, 1.221452, 1.792222",\
+ "0.603845, 0.783341, 0.973763, 1.271315, 1.842084",\
+ "0.705713, 0.885209, 1.075631, 1.373183, 1.943952",\
+ "0.943574, 1.123071, 1.313492, 1.611044, 2.181813",\
+ "1.515895, 1.695391, 1.885813, 2.183364, 2.754134",\
+ "0.611623, 0.791310, 0.981624, 1.278894, 1.849260",\
+ "0.661485, 0.841172, 1.031486, 1.328757, 1.899123",\
+ "0.763353, 0.943040, 1.133354, 1.430624, 2.000991",\
+ "1.001214, 1.180901, 1.371215, 1.668486, 2.238852",\
+ "1.573535, 1.753222, 1.943536, 2.240806, 2.811173",\
+ "0.913876, 1.096638, 1.285285, 1.582076, 2.151510",\
+ "0.963738, 1.146500, 1.335147, 1.631939, 2.201373",\
+ "1.065606, 1.248368, 1.437015, 1.733807, 2.303241",\
+ "1.303467, 1.486229, 1.674876, 1.971668, 2.541102",\
+ "1.875787, 2.058550, 2.247197, 2.543989, 3.113423");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137192, 2.137192, 2.137192, 2.137192, 2.137192");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.406562, 0.606556, 0.797323, 1.091399, 1.653630",\
+ "0.441336, 0.628906, 0.819673, 1.117199, 1.687917",\
+ "0.482700, 0.670269, 0.861036, 1.158563, 1.729280",\
+ "0.604735, 0.792305, 0.983072, 1.280598, 1.851316",\
+ "0.936348, 1.123917, 1.314685, 1.612211, 2.182929",\
+ "0.494915, 0.693874, 0.884604, 1.178704, 1.740983",\
+ "0.529546, 0.716224, 0.906954, 1.204504, 1.775270",\
+ "0.570909, 0.757588, 0.948317, 1.245868, 1.816634",\
+ "0.692944, 0.879623, 1.070353, 1.367903, 1.938669",\
+ "1.024557, 1.211236, 1.401965, 1.699516, 2.270282",\
+ "0.583845, 0.774209, 0.964631, 1.258732, 1.821015",\
+ "0.617063, 0.796559, 0.986981, 1.284533, 1.855302",\
+ "0.658427, 0.837923, 1.028344, 1.325896, 1.896666",\
+ "0.780462, 0.959958, 1.150380, 1.447932, 2.018701",\
+ "1.112075, 1.291571, 1.481992, 1.779544, 2.350314",\
+ "0.646974, 0.832040, 1.022354, 1.316164, 1.878034",\
+ "0.674703, 0.854390, 1.044704, 1.341975, 1.912341",\
+ "0.716066, 0.895753, 1.086067, 1.383338, 1.953704",\
+ "0.838102, 1.017789, 1.208103, 1.505373, 2.075740",\
+ "1.169714, 1.349402, 1.539716, 1.836986, 2.407352",\
+ "0.954606, 1.137368, 1.326015, 1.619337, 2.180259",\
+ "0.976956, 1.159718, 1.348365, 1.645157, 2.214591",\
+ "1.018319, 1.201081, 1.389728, 1.686520, 2.255954",\
+ "1.140355, 1.323117, 1.511764, 1.808556, 2.377990",\
+ "1.471967, 1.654730, 1.843377, 2.140168, 2.709602");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011");
+ values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2509*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[18]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.377666, 0.597755, 0.775019, 1.063430, 1.623644",\
+ "0.425426, 0.645514, 0.822779, 1.111188, 1.671399",\
+ "0.527520, 0.747609, 0.924873, 1.213283, 1.773495",\
+ "0.765177, 0.985265, 1.162530, 1.450942, 2.011159",\
+ "1.337186, 1.557274, 1.734539, 2.022954, 2.583179",\
+ "0.466063, 0.685073, 0.862300, 1.150735, 1.710998",\
+ "0.513823, 0.732832, 0.910060, 1.198493, 1.758752",\
+ "0.615917, 0.834927, 1.012154, 1.300588, 1.860848",\
+ "0.853574, 1.072584, 1.249811, 1.538247, 2.098513",\
+ "1.425583, 1.644592, 1.821819, 2.110259, 2.670533",\
+ "0.555414, 0.765406, 0.942327, 1.230764, 1.791029",\
+ "0.603174, 0.813165, 0.990086, 1.278522, 1.838784",\
+ "0.705268, 0.915260, 1.092181, 1.380617, 1.940880",\
+ "0.942925, 1.152916, 1.329838, 1.618276, 2.178544",\
+ "1.514933, 1.724925, 1.901846, 2.190288, 2.750564",\
+ "0.619064, 0.823222, 1.000019, 1.288193, 1.848044",\
+ "0.666823, 0.870981, 1.047778, 1.335951, 1.895798",\
+ "0.768918, 0.973076, 1.149873, 1.438046, 1.997895",\
+ "1.006574, 1.210732, 1.387530, 1.675705, 2.235559",\
+ "1.578583, 1.782741, 1.959538, 2.247717, 2.807579",\
+ "0.950146, 1.128438, 1.303674, 1.591364, 2.150265",\
+ "0.997905, 1.176197, 1.351434, 1.639122, 2.198019",\
+ "1.100000, 1.278292, 1.453528, 1.741217, 2.300115",\
+ "1.337656, 1.515949, 1.691185, 1.978876, 2.537780",\
+ "1.909665, 2.087957, 2.263194, 2.550888, 3.109800");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\
+ "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\
+ "0.375697, 0.375697, 0.375697, 0.375693, 0.375682",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\
+ "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\
+ "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\
+ "0.375697, 0.375697, 0.375697, 0.375693, 0.375682",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\
+ "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\
+ "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\
+ "0.375697, 0.375697, 0.375697, 0.375693, 0.375682",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\
+ "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\
+ "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\
+ "0.375697, 0.375697, 0.375697, 0.375693, 0.375681",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\
+ "0.035377, 0.035377, 0.035377, 0.035400, 0.035455",\
+ "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\
+ "0.375697, 0.375697, 0.375697, 0.375693, 0.375681",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.402575, 0.622525, 0.800017, 1.088497, 1.648804",\
+ "0.437980, 0.658068, 0.835333, 1.123750, 1.683980",\
+ "0.479393, 0.699481, 0.876745, 1.165163, 1.725394",\
+ "0.601610, 0.821698, 0.998963, 1.287380, 1.847608",\
+ "0.933557, 1.153646, 1.330910, 1.619324, 2.179546",\
+ "0.490972, 0.709843, 0.887297, 1.175802, 1.736157",\
+ "0.526376, 0.745386, 0.922613, 1.211055, 1.771333",\
+ "0.567789, 0.786799, 0.964026, 1.252468, 1.812747",\
+ "0.690007, 0.909017, 1.086244, 1.374685, 1.934961",\
+ "1.021954, 1.240964, 1.418191, 1.706629, 2.266899",\
+ "0.580323, 0.790176, 0.967324, 1.255831, 1.816189",\
+ "0.615727, 0.825719, 1.002640, 1.291084, 1.851365",\
+ "0.657140, 0.867132, 1.044053, 1.332497, 1.892779",\
+ "0.779358, 0.989349, 1.166271, 1.454713, 2.014993",\
+ "1.111305, 1.321296, 1.498218, 1.786658, 2.346931",\
+ "0.643973, 0.848003, 1.025017, 1.313260, 1.873204",\
+ "0.679377, 0.883535, 1.060332, 1.348513, 1.908380",\
+ "0.720790, 0.924948, 1.101745, 1.389926, 1.949794",\
+ "0.843007, 1.047165, 1.223963, 1.512143, 2.072008",\
+ "1.174954, 1.379112, 1.555910, 1.844087, 2.403945",\
+ "0.972398, 1.153296, 1.328672, 1.616431, 2.175425",\
+ "1.010459, 1.188751, 1.363988, 1.651684, 2.210601",\
+ "1.051872, 1.230164, 1.405401, 1.693097, 2.252014",\
+ "1.174089, 1.352381, 1.527618, 1.815314, 2.374228",\
+ "1.506037, 1.684329, 1.859565, 2.147258, 2.706166");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\
+ "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\
+ "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\
+ "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\
+ "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\
+ "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\
+ "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\
+ "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\
+ "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\
+ "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\
+ "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\
+ "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\
+ "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\
+ "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\
+ "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\
+ "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\
+ "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\
+ "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\
+ "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\
+ "1.064285, 1.064285, 1.064285, 1.064278, 1.064261");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2574*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[21]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.170596, 0.344816, 0.534412, 0.834679, 1.413369",\
+ "0.220441, 0.410383, 0.608141, 0.926922, 1.543926",\
+ "0.296778, 0.497025, 0.695631, 1.028154, 1.678015",\
+ "0.503693, 0.714118, 0.910633, 1.258044, 1.946084",\
+ "1.056578, 1.269082, 1.463888, 1.813508, 2.508415",\
+ "0.258804, 0.432134, 0.621693, 0.921985, 1.500723",\
+ "0.308666, 0.497701, 0.695422, 1.014227, 1.631279",\
+ "0.385015, 0.584343, 0.782912, 1.115460, 1.765368",\
+ "0.591916, 0.801436, 0.997914, 1.345350, 2.033438",\
+ "1.144755, 1.356400, 1.551169, 1.900813, 2.595769",\
+ "0.340291, 0.512462, 0.701720, 1.002013, 1.580754",\
+ "0.397987, 0.578029, 0.775449, 1.094256, 1.711311",\
+ "0.474366, 0.664671, 0.862939, 1.195488, 1.845400",\
+ "0.681230, 0.881765, 1.077941, 1.425378, 2.113470",\
+ "1.233925, 1.436728, 1.631195, 1.980842, 2.675800",\
+ "0.397929, 0.570271, 0.759443, 1.059465, 1.637816",\
+ "0.461810, 0.635841, 0.833191, 1.151754, 1.768465",\
+ "0.538221, 0.722485, 0.920682, 1.253027, 1.902633",\
+ "0.745047, 0.939586, 1.135680, 1.482963, 2.170795",\
+ "1.297604, 1.494552, 1.688930, 2.038435, 2.733142",\
+ "0.700648, 0.875417, 1.063102, 1.362655, 1.940093",\
+ "0.765372, 0.941013, 1.136853, 1.454984, 2.070854",\
+ "0.851488, 1.027673, 1.224345, 1.556291, 2.205118",\
+ "1.066931, 1.244823, 1.439341, 1.786267, 2.473392",\
+ "1.621222, 1.799810, 1.992591, 2.341746, 3.035759");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.138974, 0.138974, 0.138974, 0.148690, 0.172413",\
+ "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\
+ "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\
+ "0.872440, 0.873368, 0.873689, 0.874395, 0.875876",\
+ "2.139579, 2.140538, 2.140572, 2.140672, 2.140918",\
+ "0.138974, 0.138974, 0.138974, 0.148690, 0.172413",\
+ "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\
+ "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\
+ "0.872464, 0.873368, 0.873689, 0.874395, 0.875876",\
+ "2.139603, 2.140538, 2.140572, 2.140672, 2.140918",\
+ "0.138974, 0.138974, 0.138974, 0.148690, 0.172413",\
+ "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\
+ "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\
+ "0.872536, 0.873368, 0.873689, 0.874395, 0.875876",\
+ "2.139678, 2.140538, 2.140572, 2.140672, 2.140918",\
+ "0.138974, 0.138974, 0.138974, 0.148719, 0.172470",\
+ "0.231167, 0.231167, 0.231167, 0.238044, 0.254807",\
+ "0.397287, 0.397287, 0.397287, 0.400384, 0.407935",\
+ "0.872605, 0.873372, 0.873689, 0.874397, 0.875879",\
+ "2.139749, 2.140541, 2.140572, 2.140673, 2.140918",\
+ "0.138974, 0.138974, 0.138974, 0.148743, 0.172540",\
+ "0.231167, 0.231167, 0.231167, 0.238062, 0.254856",\
+ "0.397287, 0.397287, 0.397287, 0.400392, 0.407957",\
+ "0.872560, 0.873396, 0.873689, 0.874398, 0.875884",\
+ "2.139703, 2.140566, 2.140572, 2.140673, 2.140919");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.114526, 0.367093, 0.558483, 0.861637, 1.446138",\
+ "0.150625, 0.396446, 0.587679, 0.892767, 1.482109",\
+ "0.204730, 0.442254, 0.633143, 0.939029, 1.530580",\
+ "0.336119, 0.565619, 0.755974, 1.061799, 1.653613",\
+ "0.673349, 0.896842, 1.086112, 1.390772, 1.980608",\
+ "0.202682, 0.454411, 0.645764, 0.948942, 1.533492",\
+ "0.238886, 0.483764, 0.674960, 0.980073, 1.569463",\
+ "0.292968, 0.529572, 0.720424, 1.026334, 1.617934",\
+ "0.424327, 0.652937, 0.843255, 1.149104, 1.740967",\
+ "0.761530, 0.984159, 1.173393, 1.478077, 2.067961",\
+ "0.291788, 0.534739, 0.725791, 1.028971, 1.613523",\
+ "0.328316, 0.564093, 0.754987, 1.060101, 1.649494",\
+ "0.382328, 0.609901, 0.800451, 1.106363, 1.697965",\
+ "0.513590, 0.733265, 0.923281, 1.229132, 1.820998",\
+ "0.850714, 1.064488, 1.253420, 1.558105, 2.147993",\
+ "0.355407, 0.592582, 0.783517, 1.086430, 1.670599",\
+ "0.392245, 0.621934, 0.812712, 1.117566, 1.706581",\
+ "0.446190, 0.667738, 0.858175, 1.163830, 1.755058",\
+ "0.577359, 0.791098, 0.981005, 1.286600, 1.878091",\
+ "0.914407, 1.122314, 1.311141, 1.615571, 2.205081",\
+ "0.691600, 0.897972, 1.087176, 1.389626, 1.972893",\
+ "0.730424, 0.927308, 1.116372, 1.420767, 2.008889",\
+ "0.783940, 0.973087, 1.161835, 1.467034, 2.057372",\
+ "0.914518, 1.096413, 1.284664, 1.589804, 2.180407",\
+ "1.248497, 1.427586, 1.614800, 1.918772, 2.507391");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011");
+ values ( "0.055015, 0.067358, 0.073977, 0.088785, 0.119708",\
+ "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\
+ "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\
+ "0.432841, 0.433934, 0.434139, 0.435063, 0.437176",\
+ "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\
+ "0.055327, 0.067358, 0.073977, 0.088785, 0.119708",\
+ "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\
+ "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\
+ "0.432868, 0.433934, 0.434139, 0.435063, 0.437176",\
+ "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\
+ "0.056284, 0.067358, 0.073977, 0.088785, 0.119708",\
+ "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\
+ "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\
+ "0.432953, 0.433934, 0.434139, 0.435063, 0.437176",\
+ "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\
+ "0.057202, 0.067404, 0.073991, 0.088823, 0.119782",\
+ "0.104870, 0.104870, 0.106673, 0.116322, 0.138328",\
+ "0.190674, 0.190674, 0.191256, 0.196143, 0.207567",\
+ "0.433035, 0.433938, 0.434140, 0.435065, 0.437181",\
+ "1.062723, 1.062723, 1.063224, 1.064132, 1.065926",\
+ "0.063074, 0.067726, 0.073994, 0.088855, 0.119873",\
+ "0.104870, 0.104870, 0.106674, 0.116345, 0.138392",\
+ "0.190674, 0.190674, 0.191256, 0.196155, 0.207600",\
+ "0.433555, 0.433967, 0.434140, 0.435067, 0.437187",\
+ "1.062723, 1.062723, 1.063224, 1.064134, 1.065932");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2723*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[24]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.357397, 0.601995, 0.794649, 1.097312, 1.679722",\
+ "0.405158, 0.649756, 0.842409, 1.145087, 1.727533",\
+ "0.507252, 0.751850, 0.944504, 1.247180, 1.829623",\
+ "0.744907, 0.989505, 1.182159, 1.483890, 2.064025",\
+ "1.316914, 1.559947, 1.747496, 2.046616, 2.624655",\
+ "0.445689, 0.689313, 0.881930, 1.184617, 1.767075",\
+ "0.493449, 0.737074, 0.929690, 1.232392, 1.814886",\
+ "0.595543, 0.839168, 1.031785, 1.334485, 1.916976",\
+ "0.833198, 1.076823, 1.269440, 1.571195, 2.151379",\
+ "1.405205, 1.647264, 1.834777, 2.133921, 2.712009",\
+ "0.535203, 0.769642, 0.961957, 1.264645, 1.847107",\
+ "0.582964, 0.817402, 1.009717, 1.312421, 1.894918",\
+ "0.685058, 0.919496, 1.111811, 1.414514, 1.997008",\
+ "0.922713, 1.157152, 1.349467, 1.651224, 2.231411",\
+ "1.494720, 1.727593, 1.914804, 2.213950, 2.792040",\
+ "0.599211, 0.827507, 1.019685, 1.322102, 1.904177",\
+ "0.646972, 0.875268, 1.067446, 1.369877, 1.951988",\
+ "0.749066, 0.977362, 1.169540, 1.471970, 2.054078",\
+ "0.986721, 1.215017, 1.407195, 1.708678, 2.288475",\
+ "1.558728, 1.785452, 1.972520, 2.271401, 2.849100",\
+ "0.937895, 1.133051, 1.323345, 1.625296, 2.206465",\
+ "0.985656, 1.180812, 1.371106, 1.673071, 2.254277",\
+ "1.087750, 1.282906, 1.473200, 1.775164, 2.356366",\
+ "1.325405, 1.520561, 1.710855, 2.011869, 2.590756",\
+ "1.897411, 2.090956, 2.276178, 2.574590, 3.151375");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.035362, 0.035362, 0.035362, 0.035420, 0.035563",\
+ "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\
+ "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\
+ "0.035362, 0.035362, 0.035362, 0.035420, 0.035563",\
+ "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\
+ "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\
+ "0.035362, 0.035362, 0.035362, 0.035420, 0.035563",\
+ "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\
+ "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\
+ "0.035362, 0.035362, 0.035362, 0.035421, 0.035564",\
+ "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\
+ "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\
+ "0.035362, 0.035362, 0.035362, 0.035421, 0.035564",\
+ "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\
+ "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\
+ "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\
+ "2.136600, 2.136600, 2.136600, 2.136600, 2.136600");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.382270, 0.607170, 0.794344, 1.093466, 1.671509",\
+ "0.417706, 0.645645, 0.832819, 1.131939, 1.709979",\
+ "0.459119, 0.700449, 0.887937, 1.187057, 1.765097",\
+ "0.581337, 0.825935, 1.018589, 1.319527, 1.897724",\
+ "0.913286, 1.157884, 1.350538, 1.652760, 2.234094",\
+ "0.470573, 0.694488, 0.881625, 1.180771, 1.758862",\
+ "0.505998, 0.732962, 0.920100, 1.219244, 1.797333",\
+ "0.547411, 0.787767, 0.975218, 1.274362, 1.852450",\
+ "0.669629, 0.913253, 1.105870, 1.406832, 1.985077",\
+ "1.001577, 1.245202, 1.437819, 1.740065, 2.321447",\
+ "0.560124, 0.774817, 0.961652, 1.260799, 1.838894",\
+ "0.595513, 0.813291, 1.000127, 1.299273, 1.877364",\
+ "0.636925, 0.868096, 1.055245, 1.354391, 1.932482",\
+ "0.759143, 0.993582, 1.185897, 1.486860, 2.065109",\
+ "1.091092, 1.325531, 1.517846, 1.820093, 2.401479",\
+ "0.624166, 0.832637, 1.019369, 1.318251, 1.895954",\
+ "0.659520, 0.871112, 1.057843, 1.356724, 1.934424",\
+ "0.700933, 0.925949, 1.112961, 1.411842, 1.989542",\
+ "0.823151, 1.051447, 1.243625, 1.544312, 2.122169",\
+ "1.155100, 1.383396, 1.575574, 1.877549, 2.458546",\
+ "0.960128, 1.137870, 1.323027, 1.621440, 2.198229",\
+ "0.998204, 1.176344, 1.361501, 1.659913, 2.236699",\
+ "1.039617, 1.231408, 1.416619, 1.715032, 2.291817",\
+ "1.161835, 1.356991, 1.547285, 1.847501, 2.424445",\
+ "1.493784, 1.688940, 1.879234, 2.180742, 2.760831");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011");
+ values ( "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\
+ "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\
+ "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\
+ "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\
+ "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\
+ "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\
+ "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\
+ "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\
+ "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\
+ "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\
+ "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\
+ "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\
+ "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\
+ "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\
+ "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\
+ "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\
+ "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\
+ "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\
+ "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\
+ "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\
+ "1.064290, 1.064290, 1.064290, 1.064282, 1.064264");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2363*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[26]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.348095, 0.545075, 0.727042, 1.018426, 1.581852",\
+ "0.397956, 0.594939, 0.776906, 1.068290, 1.631715",\
+ "0.499824, 0.696806, 0.878774, 1.170157, 1.733583",\
+ "0.737685, 0.934668, 1.116635, 1.408019, 1.971444",\
+ "1.310006, 1.506989, 1.688956, 1.980340, 2.543765",\
+ "0.436445, 0.632394, 0.814323, 1.105731, 1.669206",\
+ "0.486307, 0.682257, 0.864187, 1.155595, 1.719068",\
+ "0.588175, 0.784125, 0.966055, 1.257463, 1.820936",\
+ "0.826036, 1.021986, 1.203916, 1.495324, 2.058797",\
+ "1.398357, 1.594307, 1.776237, 2.067645, 2.631118",\
+ "0.525620, 0.712727, 0.894350, 1.185759, 1.749237",\
+ "0.575481, 0.762590, 0.944214, 1.235623, 1.799100",\
+ "0.677349, 0.864458, 1.046082, 1.337491, 1.900968",\
+ "0.915211, 1.102319, 1.283943, 1.575353, 2.138829",\
+ "1.487531, 1.674640, 1.856264, 2.147673, 2.711150",\
+ "0.589087, 0.770548, 0.952053, 1.243192, 1.806260",\
+ "0.638949, 0.820411, 1.001917, 1.293056, 1.856122",\
+ "0.740817, 0.922279, 1.103785, 1.394924, 1.957990",\
+ "0.978678, 1.160140, 1.341646, 1.632786, 2.195851",\
+ "1.550998, 1.732461, 1.913967, 2.205106, 2.768172",\
+ "0.896146, 1.075801, 1.255710, 1.546367, 2.108490",\
+ "0.946008, 1.125664, 1.305574, 1.596231, 2.158352",\
+ "1.047876, 1.227532, 1.407442, 1.698099, 2.260220",\
+ "1.285737, 1.465394, 1.645303, 1.935960, 2.498081",\
+ "1.858057, 2.037714, 2.217624, 2.508281, 3.070402");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\
+ "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\
+ "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\
+ "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\
+ "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\
+ "2.137191, 2.137192, 2.137192, 2.137192, 2.137192");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.386309, 0.585807, 0.767775, 1.059158, 1.622583",\
+ "0.411174, 0.608157, 0.790125, 1.081508, 1.644933",\
+ "0.452537, 0.649520, 0.831488, 1.122872, 1.686296",\
+ "0.574573, 0.771556, 0.953524, 1.244907, 1.808332",\
+ "0.906186, 1.103168, 1.285136, 1.576519, 2.139944",\
+ "0.474546, 0.673125, 0.855056, 1.146463, 1.709936",\
+ "0.499525, 0.695475, 0.877406, 1.168813, 1.732286",\
+ "0.540888, 0.736839, 0.918769, 1.210177, 1.773650",\
+ "0.662924, 0.858874, 1.040805, 1.332212, 1.895685",\
+ "0.994536, 1.190487, 1.372417, 1.663825, 2.227298",\
+ "0.563389, 0.753458, 0.935083, 1.226492, 1.789968",\
+ "0.588699, 0.775808, 0.957433, 1.248842, 1.812318",\
+ "0.630063, 0.817172, 0.998796, 1.290205, 1.853681",\
+ "0.752098, 0.939207, 1.120831, 1.412241, 1.975717",\
+ "1.083711, 1.270820, 1.452444, 1.743853, 2.307329",\
+ "0.626548, 0.811280, 0.992786, 1.283925, 1.846990",\
+ "0.652167, 0.833630, 1.015136, 1.306275, 1.869340",\
+ "0.693530, 0.874993, 1.056499, 1.347638, 1.910704",\
+ "0.815566, 0.997028, 1.178535, 1.469674, 2.032739",\
+ "1.147178, 1.328641, 1.510147, 1.801286, 2.364352",\
+ "0.936876, 1.116533, 1.296443, 1.587100, 2.149220",\
+ "0.959225, 1.138883, 1.318793, 1.609450, 2.171570",\
+ "1.000589, 1.180246, 1.360156, 1.650813, 2.212934",\
+ "1.122624, 1.302282, 1.482192, 1.772848, 2.334969",\
+ "1.454237, 1.633894, 1.813804, 2.104461, 2.666582");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011");
+ values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\
+ "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\
+ "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\
+ "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\
+ "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\
+ "1.064247, 1.064247, 1.064247, 1.064247, 1.064247");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2685*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[27]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.226427, 0.405869, 0.606598, 0.932774, 1.565599",\
+ "0.282384, 0.460178, 0.659964, 0.990994, 1.636396",\
+ "0.358192, 0.534364, 0.733448, 1.069708, 1.728405",\
+ "0.560390, 0.734140, 0.930018, 1.272669, 1.949568",\
+ "1.105015, 1.276795, 1.468799, 1.815230, 2.504534",\
+ "0.313828, 0.493186, 0.693879, 1.020079, 1.652953",\
+ "0.369785, 0.547496, 0.747245, 1.078299, 1.723750",\
+ "0.445593, 0.621681, 0.820729, 1.157013, 1.815759",\
+ "0.647791, 0.821458, 1.017299, 1.359975, 2.036922",\
+ "1.192415, 1.364112, 1.556080, 1.902535, 2.591887",\
+ "0.394677, 0.573514, 0.773906, 1.100108, 1.732984",\
+ "0.450625, 0.627823, 0.827272, 1.158327, 1.803782",\
+ "0.526423, 0.702008, 0.900756, 1.237042, 1.895791",\
+ "0.728608, 0.901785, 1.097326, 1.440003, 2.116953",\
+ "1.273221, 1.444439, 1.636107, 1.982563, 2.671918",\
+ "0.452415, 0.631348, 0.831654, 1.157626, 1.790177",\
+ "0.508343, 0.685651, 0.885018, 1.215861, 1.861005",\
+ "0.584122, 0.759831, 0.958501, 1.294592, 1.953046",\
+ "0.786278, 0.959598, 1.155063, 1.497575, 2.174253",\
+ "1.330868, 1.502245, 1.693835, 2.040151, 2.729248",\
+ "0.756161, 0.936672, 1.135317, 1.460873, 2.092613",\
+ "0.811907, 0.990932, 1.188681, 1.519120, 2.163478",\
+ "0.887507, 1.065070, 1.262163, 1.597865, 2.255558",\
+ "1.089394, 1.264774, 1.458724, 1.800867, 2.476817",\
+ "1.633766, 1.807370, 1.997495, 2.343456, 3.031849");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.149901, 0.149901, 0.154318, 0.175674, 0.224033",\
+ "0.237266, 0.237266, 0.240233, 0.254222, 0.285839",\
+ "0.400134, 0.400516, 0.400740, 0.407020, 0.422153",\
+ "0.873536, 0.873536, 0.873536, 0.874627, 0.877289",\
+ "2.137014, 2.139136, 2.139203, 2.139990, 2.141907",\
+ "0.149901, 0.149901, 0.154318, 0.175674, 0.224033",\
+ "0.237266, 0.237266, 0.240233, 0.254222, 0.285839",\
+ "0.400134, 0.400516, 0.400740, 0.407020, 0.422153",\
+ "0.873536, 0.873536, 0.873536, 0.874627, 0.877289",\
+ "2.137014, 2.139136, 2.139203, 2.139990, 2.141907",\
+ "0.149901, 0.149901, 0.154318, 0.175674, 0.224033",\
+ "0.237266, 0.237266, 0.240233, 0.254222, 0.285839",\
+ "0.400136, 0.400516, 0.400740, 0.407020, 0.422153",\
+ "0.873536, 0.873536, 0.873536, 0.874627, 0.877289",\
+ "2.137026, 2.139136, 2.139203, 2.139990, 2.141907",\
+ "0.149901, 0.149901, 0.154329, 0.175732, 0.224149",\
+ "0.237266, 0.237266, 0.240240, 0.254260, 0.285916",\
+ "0.400141, 0.400517, 0.400740, 0.407038, 0.422190",\
+ "0.873536, 0.873536, 0.873536, 0.874631, 0.877295",\
+ "2.137051, 2.139143, 2.139203, 2.139992, 2.141911",\
+ "0.149901, 0.149901, 0.154330, 0.175783, 0.224291",\
+ "0.237266, 0.237266, 0.240241, 0.254293, 0.286008",\
+ "0.400183, 0.400527, 0.400740, 0.407054, 0.422234",\
+ "0.873536, 0.873536, 0.873536, 0.874633, 0.877303",\
+ "2.137286, 2.139199, 2.139203, 2.139994, 2.141917");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.152176, 0.424550, 0.621056, 0.937588, 1.550446",\
+ "0.188303, 0.458742, 0.655289, 0.973816, 1.591506",\
+ "0.242989, 0.508512, 0.704797, 1.024208, 1.644274",\
+ "0.376456, 0.636940, 0.832877, 1.152112, 1.772037",\
+ "0.711310, 0.972696, 1.168342, 1.486421, 2.103779",\
+ "0.240546, 0.511867, 0.708337, 1.024893, 1.637799",\
+ "0.276651, 0.546059, 0.742570, 1.061121, 1.678860",\
+ "0.331309, 0.595830, 0.792078, 1.111513, 1.731628",\
+ "0.464761, 0.724258, 0.920158, 1.239417, 1.859390",\
+ "0.799595, 1.060013, 1.255623, 1.573726, 2.191132",\
+ "0.330479, 0.592194, 0.788364, 1.104922, 1.717831",\
+ "0.366514, 0.626386, 0.822597, 1.141150, 1.758891",\
+ "0.421085, 0.676157, 0.872105, 1.191542, 1.811660",\
+ "0.554489, 0.804585, 1.000185, 1.319445, 1.939422",\
+ "0.889264, 1.140340, 1.335650, 1.653755, 2.271164",\
+ "0.394961, 0.650030, 0.846103, 1.162416, 1.774975",\
+ "0.430928, 0.684222, 0.880335, 1.198650, 1.816048",\
+ "0.485415, 0.733993, 0.929843, 1.249045, 1.868822",\
+ "0.618773, 0.862421, 1.057922, 1.376948, 1.996584",\
+ "0.953489, 1.198177, 1.393386, 1.711254, 2.328319",\
+ "0.736666, 0.955361, 1.149764, 1.465641, 2.077353",\
+ "0.772199, 0.989556, 1.183996, 1.501880, 2.118440",\
+ "0.826145, 1.039328, 1.233504, 1.552278, 2.171221",\
+ "0.959204, 1.167753, 1.361583, 1.680181, 2.298982",\
+ "1.293546, 1.503515, 1.697047, 2.014484, 2.630710");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011");
+ values ( "0.071550, 0.071795, 0.076447, 0.093063, 0.129680",\
+ "0.104996, 0.104996, 0.106778, 0.118004, 0.143877",\
+ "0.191021, 0.191212, 0.191736, 0.197505, 0.211137",\
+ "0.431517, 0.431517, 0.431517, 0.433292, 0.437617",\
+ "1.063952, 1.065332, 1.065376, 1.065376, 1.065376",\
+ "0.071556, 0.071795, 0.076447, 0.093063, 0.129680",\
+ "0.104996, 0.104996, 0.106778, 0.118004, 0.143877",\
+ "0.191026, 0.191212, 0.191736, 0.197505, 0.211137",\
+ "0.431517, 0.431517, 0.431517, 0.433292, 0.437617",\
+ "1.063986, 1.065332, 1.065376, 1.065376, 1.065376",\
+ "0.071574, 0.071795, 0.076447, 0.093063, 0.129680",\
+ "0.104996, 0.104996, 0.106778, 0.118004, 0.143877",\
+ "0.191041, 0.191212, 0.191736, 0.197505, 0.211137",\
+ "0.431517, 0.431517, 0.431517, 0.433292, 0.437617",\
+ "1.064092, 1.065332, 1.065376, 1.065376, 1.065376",\
+ "0.071593, 0.071796, 0.076458, 0.093108, 0.129768",\
+ "0.104996, 0.104996, 0.106782, 0.118035, 0.143939",\
+ "0.191055, 0.191213, 0.191737, 0.197522, 0.211169",\
+ "0.431517, 0.431517, 0.431517, 0.433297, 0.437628",\
+ "1.064195, 1.065337, 1.065376, 1.065376, 1.065376",\
+ "0.071710, 0.071803, 0.076460, 0.093146, 0.129875",\
+ "0.104996, 0.104996, 0.106783, 0.118062, 0.144015",\
+ "0.191146, 0.191218, 0.191737, 0.197536, 0.211209",\
+ "0.431517, 0.431517, 0.431517, 0.433301, 0.437640",\
+ "1.064855, 1.065373, 1.065376, 1.065376, 1.065376");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2743*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[28]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.511543, 0.732095, 0.909621, 1.198355, 1.759116",\
+ "0.561373, 0.781924, 0.959450, 1.248185, 1.808946",\
+ "0.663244, 0.883796, 1.061322, 1.350056, 1.910817",\
+ "0.901102, 1.121654, 1.299180, 1.587914, 2.148676",\
+ "1.473419, 1.693970, 1.871496, 2.160231, 2.720992",\
+ "0.599955, 0.819413, 0.996902, 1.285660, 1.846469",\
+ "0.649784, 0.869243, 1.046731, 1.335490, 1.896299",\
+ "0.751656, 0.971114, 1.148603, 1.437361, 1.998171",\
+ "0.989514, 1.208973, 1.386461, 1.675220, 2.236029",\
+ "1.561830, 1.781289, 1.958777, 2.247536, 2.808345",\
+ "0.689055, 0.899748, 1.076928, 1.365689, 1.926501",\
+ "0.738884, 0.949578, 1.126758, 1.415518, 1.976331",\
+ "0.840756, 1.051450, 1.228629, 1.517390, 2.078202",\
+ "1.078614, 1.289308, 1.466488, 1.755248, 2.316061",\
+ "1.650930, 1.861624, 2.038804, 2.327564, 2.888377",\
+ "0.752342, 0.957565, 1.134620, 1.423118, 1.983516",\
+ "0.802171, 1.007395, 1.184450, 1.472948, 2.033346",\
+ "0.904043, 1.109266, 1.286322, 1.574819, 2.135217",\
+ "1.141901, 1.347125, 1.524180, 1.812678, 2.373076",\
+ "1.714217, 1.919441, 2.096496, 2.384994, 2.945392",\
+ "1.083355, 1.262794, 1.438277, 1.726290, 2.285737",\
+ "1.133185, 1.312624, 1.488106, 1.776120, 2.335567",\
+ "1.235056, 1.414496, 1.589978, 1.877991, 2.437438",\
+ "1.472914, 1.652354, 1.827836, 2.115849, 2.675297",\
+ "2.045231, 2.224670, 2.400152, 2.688166, 3.247612");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\
+ "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\
+ "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\
+ "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\
+ "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.544225, 0.764777, 0.942302, 1.231037, 1.791798",\
+ "0.574581, 0.795133, 0.972659, 1.261393, 1.822155",\
+ "0.615945, 0.836497, 1.014023, 1.302758, 1.863519",\
+ "0.737984, 0.958535, 1.136061, 1.424796, 1.985557",\
+ "1.069601, 1.290153, 1.467679, 1.756413, 2.317174",\
+ "0.632637, 0.852095, 1.029583, 1.318342, 1.879151",\
+ "0.662993, 0.882452, 1.059940, 1.348698, 1.909508",\
+ "0.704357, 0.923816, 1.101304, 1.390063, 1.950872",\
+ "0.826395, 1.045854, 1.223342, 1.512101, 2.072910",\
+ "1.158013, 1.377472, 1.554960, 1.843718, 2.404528",\
+ "0.721737, 0.932430, 1.109610, 1.398370, 1.959183",\
+ "0.752093, 0.962787, 1.139967, 1.428727, 1.989540",\
+ "0.793457, 1.004151, 1.181331, 1.470091, 2.030904",\
+ "0.915496, 1.126189, 1.303369, 1.592129, 2.152942",\
+ "1.247113, 1.457807, 1.634987, 1.923747, 2.484560",\
+ "0.785023, 0.990247, 1.167302, 1.455800, 2.016198",\
+ "0.815380, 1.020603, 1.197659, 1.486156, 2.046555",\
+ "0.856744, 1.061968, 1.239023, 1.527521, 2.087919",\
+ "0.978782, 1.184006, 1.361061, 1.649559, 2.209957",\
+ "1.310400, 1.515623, 1.692679, 1.981176, 2.541574",\
+ "1.116037, 1.295476, 1.470958, 1.758972, 2.318419",\
+ "1.146393, 1.325833, 1.501315, 1.789329, 2.348775",\
+ "1.187757, 1.367197, 1.542679, 1.830693, 2.390140",\
+ "1.309796, 1.489235, 1.664717, 1.952731, 2.512178",\
+ "1.641413, 1.820853, 1.996335, 2.284348, 2.843795");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011");
+ values ( "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[29]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.493881, 0.730366, 0.921755, 1.228337, 1.821155",\
+ "0.543711, 0.780195, 0.971585, 1.278167, 1.870984",\
+ "0.645582, 0.882067, 1.073456, 1.380038, 1.972856",\
+ "0.883440, 1.119925, 1.311315, 1.617896, 2.210714",\
+ "1.455756, 1.692241, 1.883631, 2.190213, 2.783030",\
+ "0.582168, 0.817683, 1.009036, 1.315642, 1.908508",\
+ "0.631998, 0.867513, 1.058866, 1.365472, 1.958338",\
+ "0.733870, 0.969384, 1.160737, 1.467343, 2.060209",\
+ "0.971728, 1.207243, 1.398596, 1.705202, 2.298068",\
+ "1.544044, 1.779559, 1.970912, 2.277518, 2.870384",\
+ "0.671482, 0.898014, 1.089063, 1.395671, 1.988540",\
+ "0.721312, 0.947843, 1.138893, 1.445500, 2.038369",\
+ "0.823183, 1.049715, 1.240764, 1.547372, 2.140241",\
+ "1.061042, 1.287573, 1.478623, 1.785230, 2.378099",\
+ "1.633358, 1.859889, 2.050939, 2.357546, 2.950415",\
+ "0.735219, 0.955859, 1.146789, 1.453140, 2.045635",\
+ "0.785049, 1.005688, 1.196618, 1.502970, 2.095464",\
+ "0.886921, 1.107560, 1.298490, 1.604841, 2.197336",\
+ "1.124779, 1.345418, 1.536348, 1.842699, 2.435194",\
+ "1.697095, 1.917734, 2.108664, 2.415015, 3.007510",\
+ "1.072194, 1.261268, 1.450449, 1.756345, 2.347952",\
+ "1.122024, 1.311097, 1.500278, 1.806174, 2.397781",\
+ "1.223895, 1.412969, 1.602150, 1.908046, 2.499653",\
+ "1.461754, 1.650827, 1.840008, 2.145904, 2.737511",\
+ "2.034070, 2.223143, 2.412324, 2.718220, 3.309827");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\
+ "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\
+ "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\
+ "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\
+ "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\
+ "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\
+ "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\
+ "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\
+ "2.137213, 2.137213, 2.137213, 2.137213, 2.137213");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.526563, 0.763047, 0.954437, 1.261019, 1.853837",\
+ "0.556919, 0.793404, 0.984794, 1.291375, 1.884193",\
+ "0.598283, 0.834768, 1.026158, 1.332739, 1.925557",\
+ "0.720322, 0.956806, 1.148196, 1.454778, 2.047596",\
+ "1.051939, 1.288424, 1.479813, 1.786395, 2.379213",\
+ "0.614850, 0.850365, 1.041718, 1.348324, 1.941190",\
+ "0.645207, 0.880722, 1.072075, 1.378680, 1.971546",\
+ "0.686571, 0.922086, 1.113439, 1.420045, 2.012911",\
+ "0.808609, 1.044124, 1.235477, 1.542083, 2.134949",\
+ "1.140227, 1.375741, 1.567094, 1.873700, 2.466566",\
+ "0.704164, 0.930695, 1.121745, 1.428352, 2.021222",\
+ "0.734520, 0.961052, 1.152102, 1.458709, 2.051578",\
+ "0.775885, 1.002416, 1.193466, 1.500073, 2.092942",\
+ "0.897923, 1.124454, 1.315504, 1.622111, 2.214981",\
+ "1.229540, 1.456072, 1.647121, 1.953729, 2.546598",\
+ "0.767901, 0.988540, 1.179470, 1.485822, 2.078316",\
+ "0.798258, 1.018897, 1.209827, 1.516178, 2.108673",\
+ "0.839622, 1.060261, 1.251191, 1.557542, 2.150037",\
+ "0.961660, 1.182299, 1.373229, 1.679581, 2.272075",\
+ "1.293278, 1.513917, 1.704847, 2.011198, 2.603693",\
+ "1.104876, 1.293949, 1.483130, 1.789026, 2.380633",\
+ "1.135232, 1.324306, 1.513487, 1.819383, 2.410990",\
+ "1.176597, 1.365670, 1.554851, 1.860747, 2.452354",\
+ "1.298635, 1.487708, 1.676889, 1.982785, 2.574392",\
+ "1.630252, 1.819326, 2.008507, 2.314403, 2.906010");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2333*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[31]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.470602, 0.685204, 0.866879, 1.157031, 1.717773",\
+ "0.518644, 0.733246, 0.914922, 1.205074, 1.765816",\
+ "0.620710, 0.835312, 1.016988, 1.307140, 1.867882",\
+ "0.851211, 1.065814, 1.247489, 1.537641, 2.098383",\
+ "1.409103, 1.623705, 1.805381, 2.095532, 2.656275",\
+ "0.558998, 0.772522, 0.954160, 1.244336, 1.805127",\
+ "0.607041, 0.820565, 1.002203, 1.292379, 1.853169",\
+ "0.709107, 0.922631, 1.104269, 1.394445, 1.955235",\
+ "0.939608, 1.153132, 1.334770, 1.624946, 2.185737",\
+ "1.497499, 1.711023, 1.892661, 2.182837, 2.743628",\
+ "0.648348, 0.852854, 1.034187, 1.324365, 1.885158",\
+ "0.696391, 0.900897, 1.082230, 1.372408, 1.933201",\
+ "0.798457, 1.002963, 1.184296, 1.474474, 2.035267",\
+ "1.028958, 1.233464, 1.414797, 1.704975, 2.265768",\
+ "1.586850, 1.791356, 1.972688, 2.262866, 2.823659",\
+ "0.711997, 0.910682, 1.091889, 1.381795, 1.942174",\
+ "0.760040, 0.958725, 1.139932, 1.429837, 1.990217",\
+ "0.862106, 1.060791, 1.241998, 1.531904, 2.092283",\
+ "1.092607, 1.291292, 1.472499, 1.762405, 2.322784",\
+ "1.650499, 1.849183, 2.030391, 2.320296, 2.880676",\
+ "1.035012, 1.215977, 1.395546, 1.684966, 2.244397",\
+ "1.083055, 1.264019, 1.443589, 1.733009, 2.292439",\
+ "1.185121, 1.366086, 1.545655, 1.835075, 2.394506",\
+ "1.415622, 1.596586, 1.776156, 2.065576, 2.625007",\
+ "1.973513, 2.154478, 2.334047, 2.623468, 3.182898");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.455792, 0.670394, 0.852070, 1.142222, 1.702964",\
+ "0.494395, 0.708997, 0.890673, 1.180825, 1.741567",\
+ "0.549522, 0.764125, 0.945800, 1.235952, 1.796694",\
+ "0.682338, 0.896940, 1.078616, 1.368768, 1.929510",\
+ "1.022840, 1.237442, 1.419117, 1.709269, 2.270011",\
+ "0.544189, 0.757712, 0.939351, 1.229527, 1.790317",\
+ "0.582792, 0.796315, 0.977954, 1.268130, 1.828920",\
+ "0.637919, 0.851443, 1.033081, 1.323257, 1.884048",\
+ "0.770735, 0.984258, 1.165897, 1.456073, 2.016863",\
+ "1.111236, 1.324760, 1.506398, 1.796574, 2.357365",\
+ "0.633539, 0.838045, 1.019377, 1.309555, 1.870349",\
+ "0.672142, 0.876648, 1.057981, 1.348158, 1.908952",\
+ "0.727269, 0.931775, 1.113108, 1.403286, 1.964079",\
+ "0.860085, 1.064591, 1.245924, 1.536101, 2.096895",\
+ "1.200586, 1.405093, 1.586425, 1.876603, 2.437396",\
+ "0.697188, 0.895872, 1.077080, 1.366985, 1.927365",\
+ "0.735791, 0.934475, 1.115683, 1.405588, 1.965968",\
+ "0.790918, 0.989603, 1.170810, 1.460716, 2.021095",\
+ "0.923734, 1.122418, 1.303626, 1.593531, 2.153911",\
+ "1.264235, 1.462920, 1.644127, 1.934033, 2.494412",\
+ "1.020202, 1.201167, 1.380737, 1.670157, 2.229587",\
+ "1.058805, 1.239770, 1.419340, 1.708760, 2.268190",\
+ "1.113933, 1.294898, 1.474467, 1.763887, 2.323318",\
+ "1.246748, 1.427713, 1.607283, 1.896703, 2.456133",\
+ "1.587250, 1.768215, 1.947784, 2.237205, 2.796635");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011");
+ values ( "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\
+ "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\
+ "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\
+ "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\
+ "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\
+ "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2437*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[33]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.448199, 0.668078, 0.854477, 1.152594, 1.728783",\
+ "0.496242, 0.716121, 0.902520, 1.200637, 1.776826",\
+ "0.598308, 0.818187, 1.004586, 1.302703, 1.878892",\
+ "0.828809, 1.048688, 1.235087, 1.533204, 2.109392",\
+ "1.386700, 1.606579, 1.792978, 2.091095, 2.667284",\
+ "0.536520, 0.755396, 0.941758, 1.239900, 1.816137",\
+ "0.584563, 0.803439, 0.989801, 1.287942, 1.864179",\
+ "0.686629, 0.905505, 1.091867, 1.390008, 1.966245",\
+ "0.917129, 1.136006, 1.322368, 1.620509, 2.196746",\
+ "1.475021, 1.693897, 1.880259, 2.178401, 2.754637",\
+ "0.625932, 0.835726, 1.021785, 1.319928, 1.896168",\
+ "0.673975, 0.883769, 1.069828, 1.367971, 1.944211",\
+ "0.776041, 0.985835, 1.171894, 1.470037, 2.046277",\
+ "1.006542, 1.216336, 1.402395, 1.700537, 2.276778",\
+ "1.564433, 1.774227, 1.960286, 2.258429, 2.834669",\
+ "0.689763, 0.893549, 1.079499, 1.377377, 1.953223",\
+ "0.737806, 0.941592, 1.127542, 1.425420, 2.001266",\
+ "0.839872, 1.043658, 1.229608, 1.527486, 2.103332",\
+ "1.070373, 1.274158, 1.460109, 1.757986, 2.333832",\
+ "1.628264, 1.832049, 2.018000, 2.315878, 2.891724",\
+ "1.020000, 1.198799, 1.383157, 1.680565, 2.255491",\
+ "1.068043, 1.246842, 1.431200, 1.728607, 2.303534",\
+ "1.170109, 1.348908, 1.533266, 1.830673, 2.405600",\
+ "1.400609, 1.579409, 1.763767, 2.061174, 2.636101",\
+ "1.958501, 2.137300, 2.321658, 2.619065, 3.193992");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.433389, 0.653268, 0.839667, 1.137784, 1.713973",\
+ "0.471993, 0.691871, 0.878270, 1.176387, 1.752576",\
+ "0.527120, 0.746999, 0.933398, 1.231515, 1.807704",\
+ "0.659935, 0.879814, 1.066213, 1.364330, 1.940519",\
+ "1.000437, 1.220316, 1.406715, 1.704832, 2.281021",\
+ "0.521709, 0.740586, 0.926948, 1.225089, 1.801326",\
+ "0.560313, 0.779189, 0.965551, 1.263693, 1.839930",\
+ "0.615440, 0.834317, 1.020679, 1.318820, 1.895057",\
+ "0.748256, 0.967132, 1.153494, 1.451635, 2.027873",\
+ "1.088757, 1.307634, 1.493996, 1.792137, 2.368374",\
+ "0.611122, 0.820916, 1.006975, 1.305118, 1.881358",\
+ "0.649725, 0.859520, 1.045578, 1.343721, 1.919961",\
+ "0.704853, 0.914647, 1.100706, 1.398849, 1.975089",\
+ "0.837668, 1.047462, 1.233521, 1.531664, 2.107904",\
+ "1.178170, 1.387964, 1.574023, 1.872166, 2.448406",\
+ "0.674953, 0.878738, 1.064689, 1.362566, 1.938412",\
+ "0.713556, 0.917342, 1.103292, 1.401170, 1.977016",\
+ "0.768684, 0.972469, 1.158420, 1.456297, 2.032143",\
+ "0.901499, 1.105285, 1.291235, 1.589113, 2.164959",\
+ "1.242001, 1.445786, 1.631737, 1.929615, 2.505460",\
+ "1.005189, 1.183989, 1.368347, 1.665754, 2.240681",\
+ "1.043793, 1.222592, 1.406950, 1.704358, 2.279284",\
+ "1.098920, 1.277719, 1.462078, 1.759485, 2.334412",\
+ "1.231736, 1.410535, 1.594893, 1.892301, 2.467227",\
+ "1.572237, 1.751037, 1.935395, 2.232802, 2.807729");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011");
+ values ( "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\
+ "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\
+ "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\
+ "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\
+ "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\
+ "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2540*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[34]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.361629, 0.625108, 0.820219, 1.137042, 1.751491",\
+ "0.411458, 0.674937, 0.870045, 1.186864, 1.801305",\
+ "0.513330, 0.776809, 0.971917, 1.288736, 1.903178",\
+ "0.751188, 1.014667, 1.209775, 1.526594, 2.141035",\
+ "1.323504, 1.586983, 1.782091, 2.098909, 2.713349",\
+ "0.450018, 0.712426, 0.907500, 1.224347, 1.838845",\
+ "0.499848, 0.762256, 0.957326, 1.274169, 1.888658",\
+ "0.601719, 0.864127, 1.059198, 1.376041, 1.990532",\
+ "0.839577, 1.101985, 1.297056, 1.613899, 2.228389",\
+ "1.411893, 1.674302, 1.869372, 2.186214, 2.800702",\
+ "0.539154, 0.792761, 0.987527, 1.304375, 1.918876",\
+ "0.588984, 0.842590, 1.037353, 1.354197, 1.968690",\
+ "0.690855, 0.944462, 1.139225, 1.456070, 2.070563",\
+ "0.928713, 1.182320, 1.377083, 1.693927, 2.308420",\
+ "1.501029, 1.754636, 1.949399, 2.266243, 2.880734",\
+ "0.602519, 0.850602, 1.045260, 1.361870, 1.976021",\
+ "0.652348, 0.900431, 1.095087, 1.411692, 2.025835",\
+ "0.754220, 1.002303, 1.196958, 1.513565, 2.127708",\
+ "0.992078, 1.240161, 1.434817, 1.751422, 2.365565",\
+ "1.564394, 1.812477, 2.007132, 2.323737, 2.937879",\
+ "0.937147, 1.156000, 1.348922, 1.665098, 2.278399",\
+ "0.986977, 1.205830, 1.398749, 1.714920, 2.328213",\
+ "1.088848, 1.307701, 1.500621, 1.816792, 2.430086",\
+ "1.326707, 1.545559, 1.738479, 2.054650, 2.667943",\
+ "1.899023, 2.117875, 2.310795, 2.626965, 3.240257");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.039738, 0.039738, 0.039733, 0.039724, 0.039707",\
+ "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\
+ "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\
+ "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\
+ "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\
+ "0.039738, 0.039738, 0.039733, 0.039724, 0.039707",\
+ "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\
+ "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\
+ "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\
+ "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\
+ "0.039738, 0.039738, 0.039733, 0.039724, 0.039707",\
+ "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\
+ "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\
+ "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\
+ "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\
+ "0.039738, 0.039738, 0.039733, 0.039724, 0.039706",\
+ "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\
+ "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\
+ "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\
+ "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\
+ "0.039738, 0.039738, 0.039733, 0.039724, 0.039706",\
+ "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\
+ "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\
+ "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\
+ "2.137214, 2.137214, 2.137214, 2.137215, 2.137215");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.394276, 0.657755, 0.852725, 1.169033, 1.782342",\
+ "0.424667, 0.688146, 0.883253, 1.200070, 1.814509",\
+ "0.466031, 0.729510, 0.924618, 1.241435, 1.855873",\
+ "0.588069, 0.851548, 1.046656, 1.363473, 1.977913",\
+ "0.919687, 1.183166, 1.378274, 1.695092, 2.309533",\
+ "0.482665, 0.745074, 0.940006, 1.256338, 1.869696",\
+ "0.513056, 0.775464, 0.970534, 1.287375, 1.901862",\
+ "0.554420, 0.816828, 1.011898, 1.328740, 1.943227",\
+ "0.676459, 0.938867, 1.133937, 1.450778, 2.065267",\
+ "1.008076, 1.270484, 1.465555, 1.782397, 2.396886",\
+ "0.571801, 0.825408, 1.020033, 1.336366, 1.949727",\
+ "0.602192, 0.855799, 1.050561, 1.367404, 1.981894",\
+ "0.643556, 0.897163, 1.091925, 1.408768, 2.023258",\
+ "0.765595, 1.019201, 1.213964, 1.530807, 2.145298",\
+ "1.097212, 1.350819, 1.545582, 1.862426, 2.476918",\
+ "0.635166, 0.883249, 1.077766, 1.393860, 2.006869",\
+ "0.665557, 0.913640, 1.108294, 1.424899, 2.039039",\
+ "0.706921, 0.955004, 1.149659, 1.466263, 2.080403",\
+ "0.828959, 1.077042, 1.271697, 1.588302, 2.202443",\
+ "1.160577, 1.408660, 1.603315, 1.919921, 2.534063",\
+ "0.969795, 1.188647, 1.381428, 1.697086, 2.309244",\
+ "1.000185, 1.219038, 1.411957, 1.728126, 2.341417",\
+ "1.041550, 1.260402, 1.453321, 1.769491, 2.382781",\
+ "1.163588, 1.382441, 1.575360, 1.891530, 2.504821",\
+ "1.495205, 1.714058, 1.906978, 2.223148, 2.836441");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011");
+ values ( "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\
+ "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\
+ "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\
+ "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064246, 1.064246, 1.064246, 1.064246, 1.064246");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2607*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[41]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.485123, 0.675497, 0.864625, 1.161795, 1.733234",\
+ "0.533166, 0.723539, 0.912668, 1.209837, 1.781277",\
+ "0.635232, 0.825605, 1.014734, 1.311903, 1.883343",\
+ "0.865729, 1.056102, 1.245231, 1.542400, 2.113840",\
+ "1.423621, 1.613994, 1.803123, 2.100292, 2.671732",\
+ "0.573330, 0.762815, 0.951906, 1.249100, 1.820588",\
+ "0.621373, 0.810857, 0.999949, 1.297143, 1.868630",\
+ "0.723439, 0.912923, 1.102015, 1.399209, 1.970696",\
+ "0.953936, 1.143420, 1.332512, 1.629706, 2.201193",\
+ "1.511828, 1.701312, 1.890404, 2.187598, 2.759085",\
+ "0.662165, 0.843147, 1.031933, 1.329129, 1.900620",\
+ "0.710207, 0.891190, 1.079975, 1.377171, 1.948662",\
+ "0.812273, 0.993256, 1.182042, 1.479237, 2.050728",\
+ "1.042770, 1.223753, 1.412539, 1.709734, 2.281225",\
+ "1.600662, 1.781645, 1.970431, 2.267626, 2.839117",\
+ "0.722821, 0.900974, 1.089653, 1.386572, 1.957662",\
+ "0.770863, 0.949017, 1.137696, 1.434614, 2.005704",\
+ "0.872929, 1.051083, 1.239762, 1.536680, 2.107770",\
+ "1.103426, 1.281580, 1.470258, 1.767177, 2.338267",\
+ "1.661318, 1.839472, 2.028151, 2.325069, 2.896159",\
+ "1.025458, 1.206267, 1.393313, 1.689754, 2.259915",\
+ "1.073501, 1.254310, 1.441355, 1.737797, 2.307958",\
+ "1.175567, 1.356376, 1.543421, 1.839863, 2.410024",\
+ "1.406064, 1.586873, 1.773918, 2.070360, 2.640521",\
+ "1.963956, 2.144765, 2.331810, 2.628252, 3.198413");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.470306, 0.660679, 0.849808, 1.146978, 1.718417",\
+ "0.508912, 0.699286, 0.888414, 1.185584, 1.757023",\
+ "0.564040, 0.754413, 0.943542, 1.240712, 1.812151",\
+ "0.696855, 0.887228, 1.076357, 1.373527, 1.944966",\
+ "1.037356, 1.227730, 1.416858, 1.714028, 2.285468",\
+ "0.558513, 0.747998, 0.937089, 1.234283, 1.805771",\
+ "0.597120, 0.786604, 0.975695, 1.272889, 1.844377",\
+ "0.652247, 0.841732, 1.030823, 1.328017, 1.899504",\
+ "0.785062, 0.974547, 1.163638, 1.460832, 2.032320",\
+ "1.125564, 1.315048, 1.504139, 1.801333, 2.372821",\
+ "0.647348, 0.828330, 1.017116, 1.314311, 1.885802",\
+ "0.685954, 0.866936, 1.055722, 1.352918, 1.924409",\
+ "0.741081, 0.922064, 1.110850, 1.408045, 1.979536",\
+ "0.873897, 1.054879, 1.243665, 1.540860, 2.112351",\
+ "1.214398, 1.395380, 1.584166, 1.881362, 2.452853",\
+ "0.708003, 0.886157, 1.074836, 1.371754, 1.942844",\
+ "0.746610, 0.924764, 1.113442, 1.410361, 1.981451",\
+ "0.801737, 0.979891, 1.168570, 1.465488, 2.036578",\
+ "0.934552, 1.112706, 1.301385, 1.598303, 2.169393",\
+ "1.275054, 1.453207, 1.641886, 1.938805, 2.509895",\
+ "1.010641, 1.191450, 1.378495, 1.674937, 2.245098",\
+ "1.049248, 1.230056, 1.417102, 1.713544, 2.283704",\
+ "1.104375, 1.285184, 1.472229, 1.768671, 2.338832",\
+ "1.237190, 1.417999, 1.605044, 1.901486, 2.471647",\
+ "1.577692, 1.758500, 1.945546, 2.241987, 2.812148");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011");
+ values ( "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2372*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[42]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.459771, 0.648282, 0.825192, 1.109164, 1.658848",\
+ "0.507814, 0.696324, 0.873234, 1.157206, 1.706890",\
+ "0.609880, 0.798391, 0.975300, 1.259272, 1.808956",\
+ "0.840377, 1.028888, 1.205797, 1.489769, 2.039453",\
+ "1.398269, 1.586780, 1.763690, 2.047661, 2.597345",\
+ "0.548200, 0.735600, 0.912473, 1.196469, 1.746201",\
+ "0.596242, 0.783643, 0.960515, 1.244511, 1.794243",\
+ "0.698308, 0.885709, 1.062581, 1.346577, 1.896309",\
+ "0.928805, 1.116206, 1.293078, 1.577074, 2.126806",\
+ "1.486698, 1.674098, 1.850971, 2.134966, 2.684699",\
+ "0.637701, 0.815933, 0.992500, 1.276497, 1.826233",\
+ "0.685743, 0.863975, 1.040542, 1.324540, 1.874275",\
+ "0.787809, 0.966041, 1.142608, 1.426606, 1.976341",\
+ "1.018306, 1.196538, 1.373105, 1.657103, 2.206838",\
+ "1.576198, 1.754430, 1.930997, 2.214995, 2.764730",\
+ "0.697261, 0.873753, 1.050191, 1.333914, 1.883222",\
+ "0.745304, 0.921796, 1.098233, 1.381956, 1.931265",\
+ "0.847370, 1.023862, 1.200299, 1.484022, 2.033331",\
+ "1.077867, 1.254359, 1.430796, 1.714519, 2.263828",\
+ "1.635759, 1.812251, 1.988688, 2.272411, 2.821720",\
+ "0.999714, 1.179002, 1.353846, 1.637074, 2.185413",\
+ "1.047756, 1.227044, 1.401888, 1.685117, 2.233455",\
+ "1.149822, 1.329110, 1.503954, 1.787183, 2.335521",\
+ "1.380320, 1.559607, 1.734451, 2.017680, 2.566018",\
+ "1.938212, 2.117499, 2.292344, 2.575572, 3.123910");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\
+ "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\
+ "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\
+ "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\
+ "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\
+ "2.136611, 2.136611, 2.136611, 2.136611, 2.136611");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.444954, 0.633465, 0.810375, 1.094347, 1.644030",\
+ "0.483561, 0.672071, 0.848981, 1.132953, 1.682637",\
+ "0.538688, 0.727199, 0.904109, 1.188081, 1.737764",\
+ "0.671503, 0.860014, 1.036924, 1.320896, 1.870579",\
+ "1.012004, 1.200515, 1.377425, 1.661397, 2.211081",\
+ "0.533383, 0.720783, 0.897656, 1.181652, 1.731384",\
+ "0.571989, 0.759389, 0.936262, 1.220258, 1.769990",\
+ "0.627117, 0.814517, 0.991390, 1.275386, 1.825118",\
+ "0.759932, 0.947332, 1.124205, 1.408201, 1.957933",\
+ "1.100433, 1.287833, 1.464706, 1.748702, 2.298434",\
+ "0.622883, 0.801115, 0.977683, 1.261680, 1.811415",\
+ "0.661490, 0.839722, 1.016289, 1.300287, 1.850022",\
+ "0.716617, 0.894849, 1.071416, 1.355414, 1.905149",\
+ "0.849432, 1.027664, 1.204232, 1.488229, 2.037964",\
+ "1.189934, 1.368166, 1.544733, 1.828730, 2.378466",\
+ "0.682444, 0.858936, 1.035374, 1.319097, 1.868405",\
+ "0.721051, 0.897543, 1.073980, 1.357703, 1.907012",\
+ "0.776178, 0.952670, 1.129108, 1.412831, 1.962139",\
+ "0.908993, 1.085485, 1.261923, 1.545646, 2.094954",\
+ "1.249495, 1.425987, 1.602424, 1.886147, 2.435456",\
+ "0.984897, 1.164185, 1.339029, 1.622257, 2.170596",\
+ "1.023503, 1.202791, 1.377635, 1.660863, 2.209202",\
+ "1.078631, 1.257918, 1.432763, 1.715991, 2.264329",\
+ "1.211446, 1.390733, 1.565578, 1.848806, 2.397144",\
+ "1.551947, 1.731235, 1.906079, 2.189307, 2.737646");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011");
+ values ( "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\
+ "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\
+ "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\
+ "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\
+ "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\
+ "1.064240, 1.064240, 1.064240, 1.064240, 1.064240");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2329*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[45]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.301772, 0.506117, 0.689126, 0.977165, 1.531523",\
+ "0.351626, 0.555943, 0.738945, 1.026979, 1.581328",\
+ "0.453495, 0.657815, 0.840818, 1.128852, 1.683202",\
+ "0.691355, 0.895673, 1.078675, 1.366709, 1.921058",\
+ "1.263674, 1.467989, 1.650990, 1.939023, 2.493371",\
+ "0.390122, 0.593435, 0.776407, 1.064470, 1.618876",\
+ "0.439975, 0.643261, 0.826226, 1.114284, 1.668681",\
+ "0.541844, 0.745133, 0.928099, 1.216157, 1.770555",\
+ "0.779704, 0.982991, 1.165956, 1.454014, 2.008411",\
+ "1.352023, 1.555307, 1.738271, 2.026328, 2.580724",\
+ "0.479549, 0.673766, 0.856434, 1.144499, 1.698908",\
+ "0.529399, 0.723592, 0.906253, 1.194312, 1.748713",\
+ "0.631269, 0.825464, 1.008125, 1.296185, 1.850587",\
+ "0.869129, 1.063322, 1.245983, 1.534042, 2.088443",\
+ "1.441448, 1.635638, 1.818298, 2.106356, 2.660756",\
+ "0.543362, 0.731582, 0.914140, 1.201921, 1.755909",\
+ "0.593211, 0.781408, 0.963959, 1.251735, 1.805714",\
+ "0.695080, 0.883280, 1.065832, 1.353608, 1.907588",\
+ "0.932940, 1.121138, 1.303689, 1.591465, 2.145445",\
+ "1.505259, 1.693454, 1.876004, 2.163779, 2.717757",\
+ "0.859181, 1.036793, 1.217797, 1.505086, 2.058114",\
+ "0.909031, 1.086618, 1.267616, 1.554900, 2.107919",\
+ "1.010900, 1.188490, 1.369488, 1.656773, 2.209793",\
+ "1.248760, 1.426348, 1.607346, 1.894630, 2.447649",\
+ "1.821079, 1.998664, 2.179661, 2.466944, 3.019962");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.039786, 0.039731, 0.039718, 0.039707, 0.039690",\
+ "0.147768, 0.147761, 0.147759, 0.147758, 0.147756",\
+ "0.375012, 0.375021, 0.375023, 0.375024, 0.375027",\
+ "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\
+ "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\
+ "0.039784, 0.039731, 0.039718, 0.039707, 0.039690",\
+ "0.147768, 0.147761, 0.147759, 0.147758, 0.147756",\
+ "0.375012, 0.375021, 0.375023, 0.375024, 0.375027",\
+ "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\
+ "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\
+ "0.039780, 0.039731, 0.039718, 0.039707, 0.039690",\
+ "0.147767, 0.147761, 0.147759, 0.147758, 0.147756",\
+ "0.375013, 0.375021, 0.375023, 0.375024, 0.375027",\
+ "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\
+ "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\
+ "0.039776, 0.039731, 0.039718, 0.039707, 0.039690",\
+ "0.147767, 0.147761, 0.147759, 0.147758, 0.147756",\
+ "0.375014, 0.375021, 0.375023, 0.375024, 0.375027",\
+ "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\
+ "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\
+ "0.039779, 0.039730, 0.039718, 0.039707, 0.039690",\
+ "0.147767, 0.147761, 0.147759, 0.147758, 0.147756",\
+ "0.375013, 0.375021, 0.375023, 0.375024, 0.375027",\
+ "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\
+ "2.137207, 2.137208, 2.137209, 2.137210, 2.137212");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.335876, 0.546804, 0.729804, 1.017837, 1.572184",\
+ "0.364841, 0.569151, 0.752151, 1.040183, 1.594529",\
+ "0.406205, 0.610515, 0.793515, 1.081547, 1.635894",\
+ "0.528241, 0.732554, 0.915554, 1.203587, 1.757934",\
+ "0.859855, 1.064172, 1.247173, 1.535207, 2.089556",\
+ "0.424190, 0.634122, 0.817085, 1.105142, 1.659538",\
+ "0.453190, 0.656469, 0.839432, 1.127488, 1.681883",\
+ "0.494554, 0.697833, 0.880796, 1.168852, 1.723248",\
+ "0.616590, 0.819872, 1.002835, 1.290892, 1.845288",\
+ "0.948204, 1.151490, 1.334454, 1.622512, 2.176909",\
+ "0.513507, 0.714453, 0.897112, 1.185170, 1.739569",\
+ "0.542614, 0.736800, 0.919459, 1.207516, 1.761914",\
+ "0.583978, 0.778164, 0.960823, 1.248881, 1.803279",\
+ "0.706014, 0.900203, 1.082862, 1.370920, 1.925319",\
+ "1.037629, 1.231821, 1.414481, 1.702540, 2.256941",\
+ "0.577218, 0.772269, 0.954818, 1.242593, 1.796571",\
+ "0.606425, 0.794616, 0.977165, 1.264939, 1.818916",\
+ "0.647789, 0.835980, 1.018529, 1.306303, 1.860281",\
+ "0.769825, 0.958019, 1.140568, 1.428343, 1.982321",\
+ "1.101440, 1.289637, 1.472187, 1.759963, 2.313942",\
+ "0.899896, 1.077479, 1.258475, 1.545758, 2.098775",\
+ "0.922245, 1.099826, 1.280822, 1.568104, 2.121120",\
+ "0.963609, 1.141190, 1.322186, 1.609468, 2.162485",\
+ "1.085645, 1.263229, 1.444225, 1.731508, 2.284525",\
+ "1.417260, 1.594847, 1.775844, 2.063128, 2.616147");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161");
+ index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011");
+ values ( "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\
+ "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\
+ "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\
+ "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\
+ "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\
+ "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\
+ "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\
+ "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\
+ "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\
+ "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\
+ "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\
+ "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\
+ "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\
+ "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\
+ "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\
+ "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\
+ "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\
+ "1.064247, 1.064246, 1.064246, 1.064246, 1.064246");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2545*/
+
+} /* end of pin tl_o[2] */
+
+pin("tl_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001509 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.046822, 0.200204, 0.375821, 0.698828, 1.344843",\
+ "0.133063, 0.287379, 0.462927, 0.785543, 1.430777",\
+ "0.215932, 0.375508, 0.550883, 0.873166, 1.517732",\
+ "0.273510, 0.439904, 0.614999, 0.937080, 1.581241",\
+ "0.571476, 0.789768, 0.965387, 1.285824, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.022274, 0.297864, 0.631591, 1.248582, 2.482564",\
+ "0.026983, 0.298841, 0.633546, 1.248582, 2.482564",\
+ "0.040131, 0.301114, 0.633582, 1.248582, 2.482564",\
+ "0.052012, 0.304418, 0.633682, 1.248582, 2.482564",\
+ "0.127272, 0.343015, 0.639946, 1.251147, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.066617, 0.172302, 0.283906, 0.488180, 0.896728",\
+ "0.154032, 0.259620, 0.371187, 0.575485, 0.984081",\
+ "0.234373, 0.339957, 0.451214, 0.655513, 1.064113",\
+ "0.291019, 0.397505, 0.508757, 0.712758, 1.120761",\
+ "0.584343, 0.700840, 0.812391, 1.015773, 1.422537");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.023322, 0.186287, 0.386928, 0.759411, 1.504378",\
+ "0.023322, 0.186429, 0.387433, 0.759411, 1.504378",\
+ "0.024460, 0.186429, 0.387433, 0.759411, 1.504378",\
+ "0.026582, 0.186429, 0.387433, 0.759411, 1.504378",\
+ "0.045430, 0.190441, 0.387433, 0.759411, 1.504658");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.046822, 0.200204, 0.375821, 0.698828, 1.344843",\
+ "0.133063, 0.287379, 0.462927, 0.785543, 1.430777",\
+ "0.215932, 0.375508, 0.550883, 0.873166, 1.517732",\
+ "0.273510, 0.439904, 0.614999, 0.937080, 1.581241",\
+ "0.571476, 0.789768, 0.965387, 1.285824, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.022274, 0.297864, 0.631591, 1.247358, 2.473548",\
+ "0.026983, 0.298841, 0.633546, 1.247358, 2.473548",\
+ "0.040131, 0.301114, 0.633582, 1.247433, 2.473548",\
+ "0.052012, 0.304418, 0.633682, 1.248176, 2.473548",\
+ "0.127272, 0.343015, 0.639946, 1.251147, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.066617, 0.172302, 0.283906, 0.488180, 0.896728",\
+ "0.154032, 0.259620, 0.371187, 0.575485, 0.984081",\
+ "0.234373, 0.339957, 0.451214, 0.655513, 1.064113",\
+ "0.291019, 0.397505, 0.508757, 0.712758, 1.120761",\
+ "0.584343, 0.700840, 0.812391, 1.015773, 1.422537");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011");
+ values ( "0.023322, 0.185492, 0.385423, 0.757182, 1.500701",\
+ "0.023322, 0.185492, 0.385423, 0.757182, 1.500701",\
+ "0.024460, 0.185492, 0.385423, 0.757182, 1.500701",\
+ "0.026582, 0.186104, 0.385879, 0.758083, 1.502492",\
+ "0.045430, 0.190441, 0.385949, 0.758852, 1.504658");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022274, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215141, 0.169212, 0.139013, 0.127669, 0.141354",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023322, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250035, 0.174713, 0.106554, 0.083587, 0.146501",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022274, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147068, -0.104651, -0.070164, -0.030741, 0.275306",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023322, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163191, -0.097276, -0.039617, 0.002344, 0.222952",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[1]_hldr*/
+
+} /* end of pin tl_o[1] */
+
+pin("tl_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044859 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : tl_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[65]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859");
+ index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.097208, 0.256769, 0.409091, 0.656426, 1.137408",\
+ "0.115461, 0.284095, 0.450445, 0.715246, 1.227124",\
+ "0.150308, 0.323698, 0.505958, 0.792733, 1.344666",\
+ "0.555435, 0.728531, 0.927338, 1.279607, 1.977668",\
+ "1.416767, 1.591727, 1.785882, 2.145544, 2.866017",\
+ "0.184700, 0.344133, 0.496471, 0.743731, 1.224761",\
+ "0.202953, 0.371467, 0.537861, 0.802551, 1.314477",\
+ "0.237800, 0.411073, 0.593415, 0.880038, 1.432020",\
+ "0.642927, 0.815906, 1.014839, 1.366912, 2.065021",\
+ "1.504259, 1.679104, 1.873371, 2.232849, 2.953371",\
+ "0.265280, 0.424472, 0.576498, 0.823760, 1.304793",\
+ "0.283590, 0.451806, 0.617887, 0.882580, 1.394509",\
+ "0.318468, 0.491412, 0.673442, 0.960067, 1.512051",\
+ "0.723592, 0.896245, 1.094866, 1.446940, 2.145053",\
+ "1.584936, 1.759443, 1.953398, 2.312878, 3.033402",\
+ "0.322520, 0.482020, 0.634043, 0.881006, 1.361440",\
+ "0.340954, 0.509354, 0.675432, 0.939825, 1.451157",\
+ "0.375896, 0.548960, 0.730986, 1.017312, 1.568699",\
+ "0.781016, 0.953793, 1.152410, 1.504186, 2.201700",\
+ "1.642386, 1.816991, 2.010942, 2.370123, 3.090050",\
+ "0.620809, 0.786662, 0.937678, 1.184021, 1.663244",\
+ "0.640290, 0.814221, 0.979067, 1.242841, 1.752972",\
+ "0.675782, 0.853946, 1.034621, 1.320328, 1.870529",\
+ "1.080868, 1.258772, 1.456046, 1.807201, 2.503586",\
+ "1.942453, 2.122015, 2.314578, 2.673139, 3.391944");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859");
+ index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.031051, 0.064939, 0.106507, 0.168112, 0.284243",\
+ "0.062823, 0.089481, 0.136238, 0.207829, 0.343471",\
+ "0.126154, 0.132352, 0.184740, 0.267437, 0.424225",\
+ "0.854886, 0.854886, 0.855036, 0.913502, 1.057002",\
+ "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\
+ "0.031051, 0.064968, 0.106612, 0.168112, 0.284243",\
+ "0.062823, 0.089504, 0.136357, 0.207829, 0.343471",\
+ "0.126154, 0.132357, 0.184878, 0.267437, 0.424225",\
+ "0.854886, 0.854886, 0.855037, 0.913502, 1.057002",\
+ "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\
+ "0.031266, 0.064968, 0.106612, 0.168112, 0.284243",\
+ "0.062992, 0.089504, 0.136357, 0.207829, 0.343471",\
+ "0.126193, 0.132357, 0.184878, 0.267437, 0.424225",\
+ "0.854886, 0.854886, 0.855037, 0.913502, 1.057002",\
+ "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\
+ "0.031727, 0.064968, 0.106612, 0.168112, 0.284243",\
+ "0.063355, 0.089504, 0.136357, 0.207829, 0.343471",\
+ "0.126277, 0.132357, 0.184878, 0.267437, 0.424225",\
+ "0.854886, 0.854886, 0.855037, 0.913502, 1.057002",\
+ "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\
+ "0.035640, 0.065810, 0.106612, 0.168112, 0.284287",\
+ "0.066433, 0.090167, 0.136357, 0.207829, 0.343522",\
+ "0.126993, 0.132511, 0.184878, 0.267437, 0.424284",\
+ "0.854886, 0.854886, 0.855037, 0.913502, 1.057056",\
+ "2.399794, 2.399794, 2.399794, 2.406500, 2.422979");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859");
+ index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.062809, 0.283388, 0.498683, 0.866951, 1.603486",\
+ "0.068905, 0.306781, 0.537627, 0.930389, 1.715913",\
+ "0.080269, 0.336426, 0.586045, 1.007586, 1.850669",\
+ "0.212849, 0.497229, 0.809203, 1.343143, 2.411022",\
+ "0.495174, 0.777787, 1.106916, 1.706802, 2.906575",\
+ "0.150255, 0.370725, 0.585933, 0.953667, 1.689420",\
+ "0.156684, 0.394170, 0.624955, 1.017105, 1.801846",\
+ "0.168373, 0.423879, 0.673464, 1.094302, 1.936603",\
+ "0.301203, 0.584867, 0.896980, 1.429859, 2.496955",\
+ "0.583505, 0.865416, 1.194902, 1.793518, 2.992509",\
+ "0.236169, 0.459238, 0.673893, 1.041290, 1.776375",\
+ "0.243498, 0.482807, 0.712916, 1.104728, 1.888801",\
+ "0.256066, 0.512668, 0.761427, 1.181925, 2.023558",\
+ "0.389574, 0.674096, 0.984949, 1.517482, 2.583910",\
+ "0.671814, 0.954623, 1.282876, 1.881141, 3.079464",\
+ "0.296494, 0.524194, 0.738017, 1.105204, 1.839884",\
+ "0.304623, 0.547943, 0.777044, 1.168642, 1.952310",\
+ "0.317970, 0.578026, 0.825559, 1.245839, 2.087067",\
+ "0.452080, 0.740091, 1.049099, 1.581396, 2.647419",\
+ "0.734265, 1.020587, 1.347036, 1.945055, 3.142973",\
+ "0.612030, 0.880553, 1.088866, 1.454138, 2.185340",\
+ "0.625211, 0.906402, 1.128142, 1.517678, 2.297766",\
+ "0.643489, 0.939075, 1.176949, 1.594995, 2.432523",\
+ "0.781402, 1.108582, 1.401631, 1.931020, 2.992876",\
+ "1.063240, 1.388711, 1.700238, 2.294955, 3.488429");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859");
+ index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.011160, 0.064436, 0.116932, 0.202254, 0.372899",\
+ "0.020800, 0.078264, 0.137685, 0.234686, 0.428687",\
+ "0.041454, 0.098634, 0.166400, 0.277542, 0.499826",\
+ "0.284826, 0.291930, 0.346150, 0.498019, 0.801757",\
+ "0.801745, 0.802553, 0.834131, 0.941202, 1.155343",\
+ "0.012155, 0.064608, 0.117203, 0.202254, 0.372899",\
+ "0.021847, 0.078458, 0.137993, 0.234686, 0.428687",\
+ "0.042416, 0.098854, 0.166753, 0.277542, 0.499826",\
+ "0.284826, 0.291998, 0.346632, 0.498019, 0.801757",\
+ "0.801745, 0.802560, 0.834471, 0.941202, 1.155343",\
+ "0.014841, 0.065015, 0.117208, 0.202254, 0.372899",\
+ "0.024678, 0.078917, 0.137999, 0.234686, 0.428687",\
+ "0.045017, 0.099375, 0.166760, 0.277542, 0.499826",\
+ "0.284826, 0.292159, 0.346641, 0.498019, 0.801757",\
+ "0.801745, 0.802579, 0.834477, 0.941202, 1.155343",\
+ "0.017226, 0.065607, 0.117221, 0.202254, 0.372899",\
+ "0.027191, 0.079585, 0.138014, 0.234686, 0.428687",\
+ "0.047325, 0.100134, 0.166777, 0.277542, 0.499826",\
+ "0.284826, 0.292394, 0.346665, 0.498019, 0.801757",\
+ "0.801745, 0.802605, 0.834494, 0.941202, 1.155343",\
+ "0.032302, 0.072514, 0.118088, 0.202610, 0.372899",\
+ "0.043078, 0.087374, 0.139000, 0.235090, 0.428687",\
+ "0.061921, 0.108981, 0.167906, 0.278005, 0.499826",\
+ "0.284826, 0.295133, 0.348208, 0.498652, 0.801757",\
+ "0.801745, 0.802917, 0.835582, 0.941648, 1.155343");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "tl_o[65]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859");
+ index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.091649, 0.250131, 0.402296, 0.649078, 1.128418",\
+ "0.104662, 0.273549, 0.438178, 0.701696, 1.211503",\
+ "0.129595, 0.307072, 0.486657, 0.770890, 1.318582",\
+ "0.419859, 0.596841, 0.797852, 1.150232, 1.846445",\
+ "1.036012, 1.213814, 1.416984, 1.786820, 2.524206",\
+ "0.179141, 0.337450, 0.489577, 0.736383, 1.215771",\
+ "0.192154, 0.360868, 0.525459, 0.789001, 1.298857",\
+ "0.217087, 0.394391, 0.573938, 0.858195, 1.405936",\
+ "0.507351, 0.684160, 0.885133, 1.237537, 1.933798",\
+ "1.123504, 1.301133, 1.504265, 1.874125, 2.611559",\
+ "0.259715, 0.417789, 0.569604, 0.816412, 1.295803",\
+ "0.272795, 0.441207, 0.605486, 0.869029, 1.378888",\
+ "0.297783, 0.474730, 0.653965, 0.938223, 1.485967",\
+ "0.588044, 0.764499, 0.965159, 1.317566, 2.013830",\
+ "1.204202, 1.381472, 1.584292, 1.954154, 2.691591",\
+ "0.316944, 0.475532, 0.627237, 0.873742, 1.352620",\
+ "0.330166, 0.498989, 0.663147, 0.926397, 1.435779",\
+ "0.355271, 0.532545, 0.711661, 0.995637, 1.542949",\
+ "0.645525, 0.822313, 1.022907, 1.375159, 2.071169",\
+ "1.261694, 1.439288, 1.642045, 2.011797, 2.749029",\
+ "0.615137, 0.780253, 0.930886, 1.176831, 1.654602",\
+ "0.629566, 0.803991, 0.966800, 1.229517, 1.737849",\
+ "0.655668, 0.837777, 1.015319, 1.298796, 1.845130",\
+ "0.945865, 1.127532, 1.326573, 1.678471, 2.373782",\
+ "1.562129, 1.744529, 1.945711, 2.315152, 3.051762");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859");
+ index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.022568, 0.058250, 0.097501, 0.158155, 0.273924",\
+ "0.045222, 0.077904, 0.123497, 0.193808, 0.327390",\
+ "0.090348, 0.107489, 0.163971, 0.245678, 0.396404",\
+ "0.621445, 0.621445, 0.621445, 0.691541, 0.864683",\
+ "1.751287, 1.751287, 1.752785, 1.770247, 1.811996",\
+ "0.022568, 0.058250, 0.097501, 0.158155, 0.273924",\
+ "0.045222, 0.077904, 0.123497, 0.193808, 0.327390",\
+ "0.090348, 0.107489, 0.163971, 0.245678, 0.396404",\
+ "0.621445, 0.621445, 0.621445, 0.691541, 0.864683",\
+ "1.751287, 1.751287, 1.752785, 1.770247, 1.811996",\
+ "0.022795, 0.058250, 0.097501, 0.158155, 0.273924",\
+ "0.045430, 0.077904, 0.123497, 0.193808, 0.327390",\
+ "0.090457, 0.107489, 0.163971, 0.245678, 0.396404",\
+ "0.621445, 0.621445, 0.621445, 0.691541, 0.864683",\
+ "1.751287, 1.751287, 1.752785, 1.770247, 1.811996",\
+ "0.023283, 0.058385, 0.097589, 0.158295, 0.274203",\
+ "0.045877, 0.078027, 0.123601, 0.193969, 0.327712",\
+ "0.090692, 0.107553, 0.164104, 0.245861, 0.396767",\
+ "0.621445, 0.621445, 0.621445, 0.691750, 0.865100",\
+ "1.751287, 1.751287, 1.752788, 1.770297, 1.812096",\
+ "0.027423, 0.059345, 0.097603, 0.158415, 0.274540",\
+ "0.049669, 0.078907, 0.123617, 0.194107, 0.328101",\
+ "0.092680, 0.108015, 0.164124, 0.246016, 0.397205",\
+ "0.621445, 0.621445, 0.621445, 0.691929, 0.865604",\
+ "1.751287, 1.751287, 1.752789, 1.770340, 1.812218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859");
+ index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.062799, 0.282922, 0.497986, 0.866154, 1.602100",\
+ "0.068878, 0.306290, 0.537336, 0.930038, 1.714836",\
+ "0.080236, 0.335964, 0.585498, 1.006969, 1.849055",\
+ "0.212818, 0.496736, 0.807979, 1.341514, 2.406755",\
+ "0.493894, 0.777156, 1.106499, 1.705590, 2.901373",\
+ "0.150236, 0.370257, 0.585236, 0.952870, 1.688034",\
+ "0.156640, 0.393680, 0.624665, 1.016754, 1.800770",\
+ "0.168330, 0.423416, 0.672918, 1.093685, 1.934989",\
+ "0.301173, 0.584370, 0.895755, 1.428230, 2.492689",\
+ "0.582238, 0.864786, 1.194485, 1.792306, 2.987307",\
+ "0.236126, 0.458767, 0.673196, 1.040499, 1.774989",\
+ "0.243411, 0.482319, 0.712626, 1.104385, 1.887725",\
+ "0.255996, 0.512204, 0.760881, 1.181320, 2.021944",\
+ "0.389544, 0.673587, 0.983724, 1.515878, 2.579644",\
+ "0.670583, 0.953997, 1.282458, 1.879963, 3.074262",\
+ "0.296431, 0.523718, 0.737319, 1.104467, 1.838498",\
+ "0.304497, 0.547459, 0.776753, 1.168383, 1.951234",\
+ "0.317876, 0.577559, 0.825013, 1.245352, 2.085453",\
+ "0.452050, 0.739568, 1.047875, 1.580045, 2.643153",\
+ "0.733066, 1.019967, 1.346619, 1.944209, 3.137771",\
+ "0.611833, 0.880022, 1.088168, 1.453430, 2.183954",\
+ "0.624839, 0.905962, 1.127852, 1.517465, 2.296690",\
+ "0.643244, 0.938579, 1.176404, 1.594573, 2.430909",\
+ "0.781372, 1.107880, 1.400406, 1.929807, 2.988609",\
+ "1.062240, 1.388161, 1.699817, 2.294288, 3.483227");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859");
+ index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011");
+ values ( "0.011131, 0.063936, 0.115966, 0.201201, 0.370930",\
+ "0.020777, 0.078242, 0.137616, 0.234279, 0.426765",\
+ "0.041132, 0.097162, 0.164744, 0.275022, 0.494619",\
+ "0.282873, 0.290343, 0.344847, 0.495374, 0.795117",\
+ "0.794988, 0.797692, 0.832143, 0.938552, 1.150445",\
+ "0.012121, 0.064104, 0.116237, 0.201201, 0.370930",\
+ "0.021825, 0.078435, 0.137924, 0.234279, 0.426765",\
+ "0.042062, 0.097382, 0.165095, 0.275022, 0.494619",\
+ "0.282873, 0.290415, 0.345327, 0.495374, 0.795117",\
+ "0.794988, 0.797718, 0.832482, 0.938552, 1.150445",\
+ "0.014795, 0.064505, 0.116242, 0.201211, 0.370930",\
+ "0.024656, 0.078894, 0.137930, 0.234291, 0.426765",\
+ "0.044575, 0.097903, 0.165102, 0.275036, 0.494619",\
+ "0.282873, 0.290585, 0.345336, 0.495392, 0.795117",\
+ "0.794988, 0.797779, 0.832488, 0.938565, 1.150445",\
+ "0.017168, 0.065086, 0.116256, 0.201314, 0.370930",\
+ "0.027169, 0.079562, 0.137945, 0.234407, 0.426765",\
+ "0.046806, 0.098662, 0.165119, 0.275169, 0.494619",\
+ "0.282873, 0.290832, 0.345360, 0.495573, 0.795117",\
+ "0.794988, 0.797869, 0.832505, 0.938693, 1.150445",\
+ "0.032175, 0.071874, 0.117123, 0.201725, 0.370930",\
+ "0.043057, 0.087350, 0.138929, 0.234874, 0.426765",\
+ "0.060912, 0.107509, 0.166242, 0.275701, 0.494619",\
+ "0.282873, 0.293712, 0.346892, 0.496300, 0.795117",\
+ "0.794988, 0.798911, 0.833588, 0.939207, 1.150445");
+ }
+
+ } /* end of arc clk_ast_tlul_i_tl_o[0]_redg_min*/
+
+} /* end of pin tl_o[0] */
+} /* end of bus tl_o */
+
+pin("ast_init_done_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000556 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_init_done_o;
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011");
+ values ( "0.043384, 0.198284, 0.374379, 0.697867, 1.344843",\
+ "0.129257, 0.285459, 0.461486, 0.784583, 1.430777",\
+ "0.210733, 0.373589, 0.549444, 0.872207, 1.517732",\
+ "0.267175, 0.437989, 0.613561, 0.936121, 1.581241",\
+ "0.558327, 0.787842, 0.963956, 1.284870, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011");
+ values ( "0.018706, 0.294221, 0.628837, 1.246746, 2.482563",\
+ "0.023795, 0.295177, 0.630806, 1.246746, 2.482563",\
+ "0.037168, 0.297482, 0.630842, 1.246746, 2.482563",\
+ "0.048861, 0.300835, 0.630939, 1.246746, 2.482563",\
+ "0.122687, 0.339900, 0.637218, 1.249328, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011");
+ values ( "0.063197, 0.171101, 0.283015, 0.487593, 0.896749",\
+ "0.150760, 0.258420, 0.370296, 0.574898, 0.984103",\
+ "0.230918, 0.338761, 0.450323, 0.654927, 1.064134",\
+ "0.287331, 0.396309, 0.507868, 0.712173, 1.120782",\
+ "0.578538, 0.699638, 0.811505, 1.015189, 1.422559");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011");
+ values ( "0.020743, 0.184138, 0.385305, 0.758342, 1.504417",\
+ "0.020743, 0.184274, 0.385812, 0.758342, 1.504417",\
+ "0.021682, 0.184274, 0.385812, 0.758342, 1.504417",\
+ "0.023987, 0.184274, 0.385812, 0.758342, 1.504417",\
+ "0.042807, 0.188367, 0.385812, 0.758342, 1.504697");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_init_done_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011");
+ values ( "0.043384, 0.198284, 0.374379, 0.697867, 1.344843",\
+ "0.129257, 0.285459, 0.461486, 0.784583, 1.430777",\
+ "0.210733, 0.373589, 0.549444, 0.872207, 1.517732",\
+ "0.267175, 0.437989, 0.613561, 0.936121, 1.581241",\
+ "0.558327, 0.787842, 0.963956, 1.284870, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011");
+ values ( "0.018706, 0.294221, 0.628837, 1.245531, 2.473548",\
+ "0.023795, 0.295177, 0.630806, 1.245531, 2.473548",\
+ "0.037168, 0.297482, 0.630842, 1.245606, 2.473548",\
+ "0.048861, 0.300835, 0.630939, 1.246347, 2.473548",\
+ "0.122687, 0.339900, 0.637218, 1.249328, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011");
+ values ( "0.063197, 0.171101, 0.283015, 0.487593, 0.896749",\
+ "0.150760, 0.258420, 0.370296, 0.574898, 0.984103",\
+ "0.230918, 0.338761, 0.450323, 0.654927, 1.064134",\
+ "0.287331, 0.396309, 0.507868, 0.712173, 1.120782",\
+ "0.578538, 0.699638, 0.811505, 1.015189, 1.422559");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011");
+ values ( "0.020743, 0.183352, 0.383802, 0.756115, 1.500740",\
+ "0.020743, 0.183352, 0.383802, 0.756115, 1.500740",\
+ "0.021682, 0.183352, 0.383802, 0.756115, 1.500740",\
+ "0.023987, 0.183968, 0.384256, 0.757015, 1.502532",\
+ "0.042807, 0.188367, 0.384324, 0.757782, 1.504697");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_init_done_o_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018706, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.166278, 0.120559, 0.090376, 0.079044, 0.092801",\
+ "0.171862, 0.126143, 0.095959, 0.084628, 0.098385",\
+ "0.245234, 0.199449, 0.169261, 0.157926, 0.171660",\
+ "0.322551, 0.276573, 0.246370, 0.235023, 0.248691",\
+ "0.666536, 0.618843, 0.588507, 0.577057, 0.590140");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020743, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.195653, 0.120302, 0.052066, 0.028959, 0.090570",\
+ "0.201000, 0.125650, 0.057413, 0.034307, 0.095918",\
+ "0.271909, 0.196575, 0.128353, 0.105282, 0.167257",\
+ "0.351861, 0.276541, 0.208391, 0.185439, 0.248491",\
+ "0.700887, 0.625677, 0.558111, 0.536111, 0.607801");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_init_done_o_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018706, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.098385, -0.055930, -0.021532, 0.019602, 0.346880",\
+ "-0.103969, -0.061514, -0.027115, 0.014019, 0.341296",\
+ "-0.177290, -0.134846, -0.100420, -0.059816, 0.260884",\
+ "-0.254454, -0.212046, -0.177538, -0.138520, 0.162505",\
+ "-0.597087, -0.554990, -0.519760, -0.494735, -0.367407");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020743, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.108800, -0.043157, 0.014117, 0.055975, 0.277251",\
+ "-0.114148, -0.048505, 0.008770, 0.050627, 0.271903",\
+ "-0.185082, -0.119364, -0.061987, -0.020103, 0.200995",\
+ "-0.265110, -0.199164, -0.141461, -0.099488, 0.121043",\
+ "-0.614747, -0.546974, -0.486651, -0.443970, -0.227977");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_init_done_o_hldr*/
+
+} /* end of pin ast_init_done_o */
+
+pin("clk_ast_adc_i") {
+ direction : input ;
+ clock : true ;
+ max_transition : 2.480000 ;
+ capacitance : 0.009042 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_ast_adc_i;
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : min_pulse_width ;
+ fall_constraint( scalar ){
+ values ( "0.151080");
+ }
+
+ } /* end of arc clk_ast_adc_i_clk_ast_adc_i_pwl*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : min_pulse_width ;
+ rise_constraint( scalar ){
+ values ( "0.077628");
+ }
+
+ } /* end of arc clk_ast_adc_i_clk_ast_adc_i_pwh*/
+
+} /* end of pin clk_ast_adc_i */
+
+pin("rst_ast_adc_ni") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.009042 ;
+
+ /* Other user defined attributes. */
+ original_pin : rst_ast_adc_ni;
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.274432, 0.227738, 0.193623, 0.189926, 0.219386",\
+ "0.355422, 0.308727, 0.274612, 0.270915, 0.300375",\
+ "0.429898, 0.383203, 0.349088, 0.345391, 0.374851",\
+ "0.553172, 0.506477, 0.472362, 0.468665, 0.498125",\
+ "0.739732, 0.693038, 0.658922, 0.655226, 0.684685");
+ }
+
+ } /* end of arc clk_ast_adc_i_rst_ast_adc_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.027752, 0.053659, 0.141339, 0.280082, 0.570819",\
+ "-0.108741, -0.027330, 0.060350, 0.199093, 0.489830",\
+ "-0.183217, -0.101806, -0.014126, 0.124617, 0.415354",\
+ "-0.306491, -0.225081, -0.137400, 0.001342, 0.292080",\
+ "-0.493052, -0.411641, -0.323961, -0.185218, 0.105519");
+ }
+
+ } /* end of arc clk_ast_adc_i_rst_ast_adc_ni_remrr*/
+
+} /* end of pin rst_ast_adc_ni */
+
+pin("clk_ast_alert_i") {
+ direction : input ;
+ clock : true ;
+ max_transition : 2.480000 ;
+ capacitance : 0.111907 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_ast_alert_i;
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : min_pulse_width ;
+ fall_constraint( scalar ){
+ values ( "0.131491");
+ }
+
+ } /* end of arc clk_ast_alert_i_clk_ast_alert_i_pwl*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : min_pulse_width ;
+ rise_constraint( scalar ){
+ values ( "0.073311");
+ }
+
+ } /* end of arc clk_ast_alert_i_clk_ast_alert_i_pwh*/
+
+} /* end of pin clk_ast_alert_i */
+
+pin("rst_ast_alert_ni") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.063611 ;
+
+ /* Other user defined attributes. */
+ original_pin : rst_ast_alert_ni;
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.113563, 0.076989, 0.018933, 0.022110, 0.146261",\
+ "0.193721, 0.155461, 0.100982, 0.103788, 0.220372",\
+ "0.282614, 0.243810, 0.191411, 0.194005, 0.308054",\
+ "0.566671, 0.464344, 0.331922, 0.334358, 0.433019",\
+ "1.363218, 1.178999, 0.828491, 0.816184, 0.684690");
+ }
+
+ } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : recovery_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.092068, 0.057718, -0.003401, -0.002983, 0.002097",\
+ "0.189535, 0.154850, 0.093649, 0.094132, 0.100007",\
+ "0.301664, 0.264351, 0.202415, 0.202944, 0.209366",\
+ "0.503950, 0.455349, 0.390148, 0.390390, 0.393333",\
+ "0.857313, 0.785929, 0.714140, 0.713804, 0.709723");
+ }
+
+ } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_recfr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.123357, 0.181341, 0.319709, 0.347503, 0.685278",\
+ "0.102353, 0.159959, 0.295858, 0.323234, 0.655939",\
+ "0.092806, 0.153066, 0.290747, 0.317698, 0.645224",\
+ "0.064479, 0.123792, 0.266686, 0.294183, 0.628352",\
+ "-0.004662, 0.048858, 0.204447, 0.233992, 0.593057");
+ }
+
+ } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : removal_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.074257, 0.131115, 0.268439, 0.296209, 0.633696",\
+ "-0.014192, 0.042690, 0.179264, 0.206921, 0.543039",\
+ "-0.102387, -0.045223, 0.090380, 0.117827, 0.451393",\
+ "-0.249899, -0.191425, -0.054943, -0.027706, 0.303305",\
+ "-0.492713, -0.431597, -0.293340, -0.266527, 0.059328");
+ }
+
+ } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_remfr*/
+
+} /* end of pin rst_ast_alert_ni */
+
+pin("clk_ast_es_i") {
+ direction : input ;
+ clock : true ;
+ max_transition : 2.480000 ;
+ capacitance : 0.142021 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_ast_es_i;
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : min_pulse_width ;
+ fall_constraint( scalar ){
+ values ( "0.131491");
+ }
+
+ } /* end of arc clk_ast_es_i_clk_ast_es_i_pwl*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : min_pulse_width ;
+ rise_constraint( scalar ){
+ values ( "0.073311");
+ }
+
+ } /* end of arc clk_ast_es_i_clk_ast_es_i_pwh*/
+
+} /* end of pin clk_ast_es_i */
+
+pin("rst_ast_es_ni") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.184622 ;
+
+ /* Other user defined attributes. */
+ original_pin : rst_ast_es_ni;
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.210479, 0.169372, 0.114546, 0.118621, 0.168150",\
+ "0.293165, 0.250654, 0.192180, 0.195438, 0.235030",\
+ "0.391384, 0.349291, 0.288209, 0.290833, 0.322724",\
+ "0.566327, 0.524466, 0.460601, 0.462751, 0.488884",\
+ "0.947368, 0.905673, 0.836972, 0.838520, 0.857344");
+ }
+
+ } /* end of arc clk_ast_es_i_rst_ast_es_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.051490, -0.010118, 0.054432, 0.065559, 0.200781",\
+ "-0.130202, -0.094826, -0.027856, -0.016996, 0.114987",\
+ "-0.215839, -0.180431, -0.119977, -0.109196, 0.021823",\
+ "-0.347231, -0.311623, -0.255002, -0.244742, -0.120048",\
+ "-0.619519, -0.583379, -0.529999, -0.521121, -0.413232");
+ }
+
+ } /* end of arc clk_ast_es_i_rst_ast_es_ni_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.330641, 0.279192, 0.245179, 0.243672, 0.279220",\
+ "0.409639, 0.358190, 0.324177, 0.322670, 0.358218",\
+ "0.487644, 0.436183, 0.402110, 0.400492, 0.435798",\
+ "0.623048, 0.571541, 0.537264, 0.535269, 0.569741",\
+ "0.842293, 0.790722, 0.756013, 0.753223, 0.785948");
+ }
+
+ } /* end of arc clk_ast_ext_i_rst_ast_es_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.138360, -0.088735, -0.049180, 0.004893, 0.111904",\
+ "-0.218903, -0.169277, -0.129723, -0.075649, 0.031362",\
+ "-0.301318, -0.252007, -0.212321, -0.158231, -0.051325",\
+ "-0.443423, -0.394857, -0.354861, -0.300729, -0.194073",\
+ "-0.673239, -0.626523, -0.585755, -0.531523, -0.425485");
+ }
+
+ } /* end of arc clk_ast_ext_i_rst_ast_es_ni_remrr*/
+
+} /* end of pin rst_ast_es_ni */
+
+pin("clk_ast_rng_i") {
+ direction : input ;
+ clock : true ;
+ max_transition : 2.480000 ;
+ capacitance : 0.016298 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_ast_rng_i;
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : min_pulse_width ;
+ fall_constraint( scalar ){
+ values ( "0.131491");
+ }
+
+ } /* end of arc clk_ast_rng_i_clk_ast_rng_i_pwl*/
+
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : min_pulse_width ;
+ rise_constraint( scalar ){
+ values ( "0.073311");
+ }
+
+ } /* end of arc clk_ast_rng_i_clk_ast_rng_i_pwh*/
+
+} /* end of pin clk_ast_rng_i */
+
+pin("rst_ast_rng_ni") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.019282 ;
+
+ /* Other user defined attributes. */
+ original_pin : rst_ast_rng_ni;
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.397809, 0.355150, 0.299205, 0.303092, 0.350337",\
+ "0.476858, 0.434199, 0.378254, 0.382142, 0.429386",\
+ "0.555484, 0.512828, 0.456739, 0.460590, 0.507394",\
+ "0.694132, 0.651484, 0.595040, 0.598802, 0.644521",\
+ "0.924501, 0.881869, 0.824615, 0.828174, 0.871421");
+ }
+
+ } /* end of arc clk_ast_rng_i_rst_ast_rng_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.051490, -0.010118, 0.054432, 0.065559, 0.200781",\
+ "-0.130202, -0.094826, -0.027856, -0.016996, 0.114987",\
+ "-0.215839, -0.180431, -0.119977, -0.109196, 0.021823",\
+ "-0.347231, -0.311623, -0.255002, -0.244742, -0.120048",\
+ "-0.619519, -0.580113, -0.514458, -0.503429, -0.369398");
+ }
+
+ } /* end of arc clk_ast_rng_i_rst_ast_rng_ni_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.210479, 0.160879, 0.128086, 0.118621, 0.168150",\
+ "0.293165, 0.241596, 0.206622, 0.195438, 0.235030",\
+ "0.391384, 0.339830, 0.303295, 0.290833, 0.322724",\
+ "0.566327, 0.514573, 0.476374, 0.462751, 0.488884",\
+ "0.947368, 0.895031, 0.853939, 0.838520, 0.857344");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rst_ast_rng_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.124168, -0.077180, -0.040446, -0.015137, 0.108101",\
+ "-0.205037, -0.158304, -0.123014, -0.098281, 0.025219",\
+ "-0.301967, -0.254997, -0.221149, -0.197116, -0.074898",\
+ "-0.470369, -0.422280, -0.389838, -0.366778, -0.249319",\
+ "-0.834370, -0.783388, -0.753247, -0.732123, -0.626660");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rst_ast_rng_ni_remrr*/
+
+} /* end of pin rst_ast_rng_ni */
+
+pin("clk_ast_tlul_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.070969 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_ast_tlul_i;
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : min_pulse_width ;
+ fall_constraint( scalar ){
+ values ( "0.149001");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_ast_tlul_i_pwl*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : min_pulse_width ;
+ rise_constraint( scalar ){
+ values ( "0.073311");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_ast_tlul_i_pwh*/
+
+} /* end of pin clk_ast_tlul_i */
+
+pin("rst_ast_tlul_ni") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 2.103311 ;
+
+ /* Other user defined attributes. */
+ original_pin : rst_ast_tlul_ni;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.716936, 0.665384, 0.628579, 0.622004, 0.646451",\
+ "0.794990, 0.743439, 0.706634, 0.700058, 0.724506",\
+ "0.863378, 0.811826, 0.775021, 0.768446, 0.792893",\
+ "0.983598, 0.932046, 0.895241, 0.888666, 0.913113",\
+ "1.184568, 1.133018, 1.096165, 1.089503, 1.113762");
+ }
+
+ } /* end of arc clk_ast_ext_i_rst_ast_tlul_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.208883, -0.162400, -0.121535, -0.067290, 0.038670",\
+ "-0.289818, -0.243335, -0.202470, -0.148225, -0.042265",\
+ "-0.371428, -0.325048, -0.284140, -0.229890, -0.123964",\
+ "-0.514608, -0.468588, -0.427530, -0.373260, -0.267455",\
+ "-0.754762, -0.708893, -0.668362, -0.614349, -0.508655");
+ }
+
+ } /* end of arc clk_ast_ext_i_rst_ast_tlul_ni_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.210479, 0.169372, 0.114546, 0.118621, 0.168150",\
+ "0.293165, 0.250654, 0.192180, 0.195438, 0.235030",\
+ "0.391384, 0.349291, 0.288209, 0.290833, 0.322724",\
+ "0.566327, 0.524466, 0.460601, 0.462751, 0.488884",\
+ "0.947368, 0.905673, 0.836972, 0.838520, 0.857344");
+ }
+
+ } /* end of arc clk_ast_rng_i_rst_ast_tlul_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.124168, -0.086693, -0.025277, -0.015137, 0.108101",\
+ "-0.205037, -0.167443, -0.108443, -0.098281, 0.025219",\
+ "-0.301967, -0.263763, -0.207172, -0.197116, -0.074898",\
+ "-0.470369, -0.430682, -0.376443, -0.366778, -0.249319",\
+ "-0.834370, -0.791194, -0.740802, -0.732123, -0.626660");
+ }
+
+ } /* end of arc clk_ast_rng_i_rst_ast_tlul_ni_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "1.869923, 1.822277, 1.788958, 1.777550, 1.806108",\
+ "1.951337, 1.903690, 1.870372, 1.858964, 1.887521",\
+ "2.032032, 1.984385, 1.951067, 1.939659, 1.968216",\
+ "2.170088, 2.122442, 2.089123, 2.077716, 2.106273",\
+ "2.387489, 2.339843, 2.306524, 2.295116, 2.323674");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rst_ast_tlul_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.059314, 0.134642, 0.207217, 0.259023, 0.524416",\
+ "-0.004435, 0.071727, 0.144173, 0.196109, 0.463735",\
+ "-0.061661, 0.013696, 0.087717, 0.140099, 0.405234",\
+ "-0.144853, -0.069971, 0.004287, 0.056772, 0.321975",\
+ "-0.313738, -0.239256, -0.166173, -0.113918, 0.154394");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rst_ast_tlul_ni_remrr*/
+
+} /* end of pin rst_ast_tlul_ni */
+
+pin("clk_ast_usb_i") {
+ direction : input ;
+ clock : true ;
+ max_transition : 2.480000 ;
+ capacitance : 0.008679 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_ast_usb_i;
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : min_pulse_width ;
+ fall_constraint( scalar ){
+ values ( "0.131491");
+ }
+
+ } /* end of arc clk_ast_usb_i_clk_ast_usb_i_pwl*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : min_pulse_width ;
+ rise_constraint( scalar ){
+ values ( "0.073311");
+ }
+
+ } /* end of arc clk_ast_usb_i_clk_ast_usb_i_pwh*/
+
+} /* end of pin clk_ast_usb_i */
+
+pin("rst_ast_usb_ni") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.013220 ;
+
+ /* Other user defined attributes. */
+ original_pin : rst_ast_usb_ni;
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.400327, 0.357670, 0.301625, 0.305488, 0.352426",\
+ "0.476049, 0.433392, 0.377347, 0.381210, 0.428148",\
+ "0.548090, 0.505436, 0.449256, 0.453084, 0.499610",\
+ "0.675976, 0.633329, 0.576799, 0.580539, 0.625997",\
+ "0.887381, 0.844752, 0.787402, 0.790936, 0.833890");
+ }
+
+ } /* end of arc clk_ast_usb_i_rst_ast_usb_ni_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.128239, -0.088359, -0.022542, -0.011521, 0.122413",\
+ "-0.208722, -0.168842, -0.103025, -0.092004, 0.041930",\
+ "-0.287884, -0.248004, -0.182187, -0.171166, -0.037232",\
+ "-0.421984, -0.382104, -0.316287, -0.305266, -0.171332",\
+ "-0.631259, -0.591379, -0.525562, -0.514541, -0.380607");
+ }
+
+ } /* end of arc clk_ast_usb_i_rst_ast_usb_ni_remrr*/
+
+} /* end of pin rst_ast_usb_ni */
+
+pin("clk_ast_ext_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.005952 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_ast_ext_i;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : min_pulse_width ;
+ fall_constraint( scalar ){
+ values ( "0.300783");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_ast_ext_i_pwl*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : min_pulse_width ;
+ rise_constraint( scalar ){
+ values ( "0.123380");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_ast_ext_i_pwh*/
+
+} /* end of pin clk_ast_ext_i */
+
+pin("por_ni") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000461 ;
+
+ /* Other user defined attributes. */
+ original_pin : por_ni;
+} /* end of pin por_ni */
+bus ( sns_clks_i ) {
+
+ bus_type : BUS27_type2 ;
+ direction : input ;
+
+pin("sns_clks_i[26]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[26];
+} /* end of pin sns_clks_i[26] */
+
+pin("sns_clks_i[25]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[25];
+} /* end of pin sns_clks_i[25] */
+
+pin("sns_clks_i[24]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[24];
+} /* end of pin sns_clks_i[24] */
+
+pin("sns_clks_i[23]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[23];
+} /* end of pin sns_clks_i[23] */
+
+pin("sns_clks_i[22]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[22];
+} /* end of pin sns_clks_i[22] */
+
+pin("sns_clks_i[21]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[21];
+} /* end of pin sns_clks_i[21] */
+
+pin("sns_clks_i[20]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[20];
+} /* end of pin sns_clks_i[20] */
+
+pin("sns_clks_i[19]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[19];
+} /* end of pin sns_clks_i[19] */
+
+pin("sns_clks_i[18]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[18];
+} /* end of pin sns_clks_i[18] */
+
+pin("sns_clks_i[17]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[17];
+} /* end of pin sns_clks_i[17] */
+
+pin("sns_clks_i[16]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[16];
+} /* end of pin sns_clks_i[16] */
+
+pin("sns_clks_i[15]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[15];
+} /* end of pin sns_clks_i[15] */
+
+pin("sns_clks_i[14]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[14];
+} /* end of pin sns_clks_i[14] */
+
+pin("sns_clks_i[13]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[13];
+} /* end of pin sns_clks_i[13] */
+
+pin("sns_clks_i[12]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[12];
+} /* end of pin sns_clks_i[12] */
+
+pin("sns_clks_i[11]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[11];
+} /* end of pin sns_clks_i[11] */
+
+pin("sns_clks_i[10]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[10];
+} /* end of pin sns_clks_i[10] */
+
+pin("sns_clks_i[9]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[9];
+} /* end of pin sns_clks_i[9] */
+
+pin("sns_clks_i[8]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[8];
+} /* end of pin sns_clks_i[8] */
+
+pin("sns_clks_i[7]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[7];
+} /* end of pin sns_clks_i[7] */
+
+pin("sns_clks_i[6]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[6];
+} /* end of pin sns_clks_i[6] */
+
+pin("sns_clks_i[5]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[5];
+} /* end of pin sns_clks_i[5] */
+
+pin("sns_clks_i[4]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[4];
+} /* end of pin sns_clks_i[4] */
+
+pin("sns_clks_i[3]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[3];
+} /* end of pin sns_clks_i[3] */
+
+pin("sns_clks_i[2]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[2];
+} /* end of pin sns_clks_i[2] */
+
+pin("sns_clks_i[1]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[1];
+} /* end of pin sns_clks_i[1] */
+
+pin("sns_clks_i[0]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_clks_i[0];
+} /* end of pin sns_clks_i[0] */
+} /* end of bus sns_clks_i */
+bus ( sns_rsts_i ) {
+
+ bus_type : BUS56_type3 ;
+ direction : input ;
+
+pin("sns_rsts_i[55]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[55];
+} /* end of pin sns_rsts_i[55] */
+
+pin("sns_rsts_i[54]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[54];
+} /* end of pin sns_rsts_i[54] */
+
+pin("sns_rsts_i[53]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[53];
+} /* end of pin sns_rsts_i[53] */
+
+pin("sns_rsts_i[52]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[52];
+} /* end of pin sns_rsts_i[52] */
+
+pin("sns_rsts_i[51]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[51];
+} /* end of pin sns_rsts_i[51] */
+
+pin("sns_rsts_i[50]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[50];
+} /* end of pin sns_rsts_i[50] */
+
+pin("sns_rsts_i[49]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[49];
+} /* end of pin sns_rsts_i[49] */
+
+pin("sns_rsts_i[48]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[48];
+} /* end of pin sns_rsts_i[48] */
+
+pin("sns_rsts_i[47]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[47];
+} /* end of pin sns_rsts_i[47] */
+
+pin("sns_rsts_i[46]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[46];
+} /* end of pin sns_rsts_i[46] */
+
+pin("sns_rsts_i[45]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[45];
+} /* end of pin sns_rsts_i[45] */
+
+pin("sns_rsts_i[44]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[44];
+} /* end of pin sns_rsts_i[44] */
+
+pin("sns_rsts_i[43]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[43];
+} /* end of pin sns_rsts_i[43] */
+
+pin("sns_rsts_i[42]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[42];
+} /* end of pin sns_rsts_i[42] */
+
+pin("sns_rsts_i[41]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[41];
+} /* end of pin sns_rsts_i[41] */
+
+pin("sns_rsts_i[40]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[40];
+} /* end of pin sns_rsts_i[40] */
+
+pin("sns_rsts_i[39]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[39];
+} /* end of pin sns_rsts_i[39] */
+
+pin("sns_rsts_i[38]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[38];
+} /* end of pin sns_rsts_i[38] */
+
+pin("sns_rsts_i[37]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[37];
+} /* end of pin sns_rsts_i[37] */
+
+pin("sns_rsts_i[36]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[36];
+} /* end of pin sns_rsts_i[36] */
+
+pin("sns_rsts_i[35]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[35];
+} /* end of pin sns_rsts_i[35] */
+
+pin("sns_rsts_i[34]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[34];
+} /* end of pin sns_rsts_i[34] */
+
+pin("sns_rsts_i[33]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[33];
+} /* end of pin sns_rsts_i[33] */
+
+pin("sns_rsts_i[32]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[32];
+} /* end of pin sns_rsts_i[32] */
+
+pin("sns_rsts_i[31]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[31];
+} /* end of pin sns_rsts_i[31] */
+
+pin("sns_rsts_i[30]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[30];
+} /* end of pin sns_rsts_i[30] */
+
+pin("sns_rsts_i[29]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[29];
+} /* end of pin sns_rsts_i[29] */
+
+pin("sns_rsts_i[28]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[28];
+} /* end of pin sns_rsts_i[28] */
+
+pin("sns_rsts_i[27]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[27];
+} /* end of pin sns_rsts_i[27] */
+
+pin("sns_rsts_i[26]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[26];
+} /* end of pin sns_rsts_i[26] */
+
+pin("sns_rsts_i[25]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[25];
+} /* end of pin sns_rsts_i[25] */
+
+pin("sns_rsts_i[24]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[24];
+} /* end of pin sns_rsts_i[24] */
+
+pin("sns_rsts_i[23]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[23];
+} /* end of pin sns_rsts_i[23] */
+
+pin("sns_rsts_i[22]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[22];
+} /* end of pin sns_rsts_i[22] */
+
+pin("sns_rsts_i[21]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[21];
+} /* end of pin sns_rsts_i[21] */
+
+pin("sns_rsts_i[20]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[20];
+} /* end of pin sns_rsts_i[20] */
+
+pin("sns_rsts_i[19]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[19];
+} /* end of pin sns_rsts_i[19] */
+
+pin("sns_rsts_i[18]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[18];
+} /* end of pin sns_rsts_i[18] */
+
+pin("sns_rsts_i[17]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[17];
+} /* end of pin sns_rsts_i[17] */
+
+pin("sns_rsts_i[16]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[16];
+} /* end of pin sns_rsts_i[16] */
+
+pin("sns_rsts_i[15]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[15];
+} /* end of pin sns_rsts_i[15] */
+
+pin("sns_rsts_i[14]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[14];
+} /* end of pin sns_rsts_i[14] */
+
+pin("sns_rsts_i[13]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[13];
+} /* end of pin sns_rsts_i[13] */
+
+pin("sns_rsts_i[12]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[12];
+} /* end of pin sns_rsts_i[12] */
+
+pin("sns_rsts_i[11]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[11];
+} /* end of pin sns_rsts_i[11] */
+
+pin("sns_rsts_i[10]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[10];
+} /* end of pin sns_rsts_i[10] */
+
+pin("sns_rsts_i[9]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[9];
+} /* end of pin sns_rsts_i[9] */
+
+pin("sns_rsts_i[8]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[8];
+} /* end of pin sns_rsts_i[8] */
+
+pin("sns_rsts_i[7]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[7];
+} /* end of pin sns_rsts_i[7] */
+
+pin("sns_rsts_i[6]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[6];
+} /* end of pin sns_rsts_i[6] */
+
+pin("sns_rsts_i[5]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[5];
+} /* end of pin sns_rsts_i[5] */
+
+pin("sns_rsts_i[4]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[4];
+} /* end of pin sns_rsts_i[4] */
+
+pin("sns_rsts_i[3]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[3];
+} /* end of pin sns_rsts_i[3] */
+
+pin("sns_rsts_i[2]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[2];
+} /* end of pin sns_rsts_i[2] */
+
+pin("sns_rsts_i[1]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[1];
+} /* end of pin sns_rsts_i[1] */
+
+pin("sns_rsts_i[0]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_rsts_i[0];
+} /* end of pin sns_rsts_i[0] */
+} /* end of bus sns_rsts_i */
+
+pin("sns_spi_ext_clk_i") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : sns_spi_ext_clk_i;
+} /* end of pin sns_spi_ext_clk_i */
+
+pin("vcc_supp_i") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : vcc_supp_i;
+} /* end of pin vcc_supp_i */
+
+pin("vcaon_supp_i") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : vcaon_supp_i;
+} /* end of pin vcaon_supp_i */
+
+pin("vcmain_supp_i") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : vcmain_supp_i;
+} /* end of pin vcmain_supp_i */
+
+pin("vioa_supp_i") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : vioa_supp_i;
+} /* end of pin vioa_supp_i */
+
+pin("viob_supp_i") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : viob_supp_i;
+} /* end of pin viob_supp_i */
+bus ( ast_pwst_o ) {
+
+ bus_type : BUS5_type4 ;
+ direction : output ;
+
+pin("ast_pwst_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.652273 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000495 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_o[4];
+} /* end of pin ast_pwst_o[4] */
+
+pin("ast_pwst_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.007560 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_o[3];
+} /* end of pin ast_pwst_o[3] */
+
+pin("ast_pwst_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.029213 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000584 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_o[2];
+ timing () {
+ related_pin : "ast_pwst_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\
+ "0.125647, 0.191441, 0.306120, 0.621529, 1.461089",\
+ "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\
+ "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\
+ "0.704776, 0.781389, 0.901027, 1.217412, 2.063059");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.118650, 0.232640, 0.431328, 0.981607, 2.441227",\
+ "0.118668, 0.232640, 0.431330, 0.981682, 2.441227",\
+ "0.118668, 0.233537, 0.432463, 0.981682, 2.441227",\
+ "0.120002, 0.233537, 0.433774, 0.981682, 2.441227",\
+ "0.161250, 0.255527, 0.435044, 0.981682, 2.441227");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\
+ "0.068682, 0.082462, 0.106420, 0.172219, 0.347402",\
+ "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\
+ "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\
+ "0.645975, 0.686648, 0.737659, 0.832084, 1.014107");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.026953, 0.051423, 0.094862, 0.215093, 0.534102",\
+ "0.026955, 0.051424, 0.094862, 0.215093, 0.534102",\
+ "0.033450, 0.053875, 0.094993, 0.215093, 0.534241",\
+ "0.046741, 0.065795, 0.101823, 0.215093, 0.534701",\
+ "0.120319, 0.148529, 0.186126, 0.267902, 0.543427");
+ }
+
+ } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "ast_pwst_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\
+ "0.125568, 0.191362, 0.306040, 0.621450, 1.461010",\
+ "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\
+ "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\
+ "0.704776, 0.781389, 0.901027, 1.217412, 2.063059");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.118650, 0.232611, 0.431328, 0.977612, 2.431972",\
+ "0.118650, 0.232611, 0.431330, 0.977612, 2.431972",\
+ "0.118650, 0.233259, 0.432463, 0.977612, 2.431972",\
+ "0.120002, 0.233259, 0.433774, 0.977612, 2.431972",\
+ "0.161250, 0.255527, 0.435044, 0.981481, 2.431972");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\
+ "0.068410, 0.082189, 0.106148, 0.171946, 0.347129",\
+ "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\
+ "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\
+ "0.645975, 0.686648, 0.737659, 0.832084, 1.014107");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.026953, 0.051423, 0.094862, 0.214557, 0.534102",\
+ "0.026954, 0.051424, 0.094862, 0.214557, 0.534102",\
+ "0.033450, 0.053875, 0.094993, 0.214557, 0.534241",\
+ "0.046741, 0.065795, 0.101823, 0.215088, 0.534701",\
+ "0.120319, 0.148529, 0.186126, 0.267902, 0.543427");
+ }
+
+ } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una_min*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.120145, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.404676, 0.353105, 0.318351, 0.315478, 0.348023",\
+ "0.454532, 0.402961, 0.368207, 0.365334, 0.397879",\
+ "0.484555, 0.432984, 0.398230, 0.395357, 0.427902",\
+ "0.566329, 0.514758, 0.480004, 0.477131, 0.509676",\
+ "0.956464, 0.904894, 0.869963, 0.866772, 0.898621");
+ }
+
+ } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.118140, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.316729, -0.270030, -0.234537, -0.184982, -0.086025",\
+ "-0.365783, -0.319083, -0.283591, -0.234035, -0.135079",\
+ "-0.396608, -0.349909, -0.314416, -0.264861, -0.165904",\
+ "-0.478382, -0.431683, -0.396190, -0.346635, -0.247678",\
+ "-0.868371, -0.821645, -0.786315, -0.736867, -0.638027");
+ }
+
+ } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380000.531250, 380000.593750, 380000.718750, 380001.031250, 380001.875000",\
+ "380000.625000, 380000.687500, 380000.812500, 380001.125000, 380001.968750",\
+ "380000.687500, 380000.750000, 380000.875000, 380001.187500, 380002.031250",\
+ "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\
+ "380001.062500, 380001.125000, 380001.250000, 380001.562500, 380002.406250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\
+ "380001.968750, 380001.968750, 380002.000000, 380002.062500, 380002.250000",\
+ "380002.062500, 380002.062500, 380002.093750, 380002.156250, 380002.343750",\
+ "380002.125000, 380002.125000, 380002.156250, 380002.218750, 380002.406250",\
+ "380002.468750, 380002.468750, 380002.500000, 380002.562500, 380002.750000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\
+ "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\
+ "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\
+ "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\
+ "0.031251, 0.056161, 0.101276, 0.226771, 0.561875");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.396377, 0.462195, 0.577090, 0.892530, 1.731965",\
+ "0.483687, 0.549505, 0.664400, 0.979841, 1.819276",\
+ "0.581466, 0.647284, 0.762179, 1.077619, 1.917054",\
+ "0.654025, 0.719843, 0.834738, 1.150178, 1.989613",\
+ "1.042482, 1.108301, 1.223195, 1.538636, 2.378071");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\
+ "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\
+ "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\
+ "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\
+ "0.118140, 0.231881, 0.431660, 0.979741, 2.437812");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.326727, 0.341464, 0.366815, 0.435950, 0.619738",\
+ "0.414576, 0.429313, 0.454664, 0.523799, 0.707587",\
+ "0.495656, 0.510394, 0.535744, 0.604879, 0.788667",\
+ "0.553927, 0.568665, 0.594015, 0.663150, 0.846938",\
+ "0.864022, 0.878760, 0.904110, 0.973245, 1.157033");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380000.406250, 380000.468750, 380000.593750, 380000.906250, 380001.750000",\
+ "380000.500000, 380000.562500, 380000.687500, 380001.000000, 380001.843750",\
+ "380000.593750, 380000.656250, 380000.781250, 380001.093750, 380001.937500",\
+ "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\
+ "380001.000000, 380001.062500, 380001.187500, 380001.500000, 380002.343750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380001.781250, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\
+ "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\
+ "380002.000000, 380002.000000, 380002.031250, 380002.093750, 380002.281250",\
+ "380002.187500, 380002.187500, 380002.218750, 380002.281250, 380002.468750",\
+ "380002.500000, 380002.500000, 380002.531250, 380002.593750, 380002.781250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\
+ "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\
+ "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\
+ "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\
+ "0.031236, 0.056156, 0.101275, 0.226769, 0.561877");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "379999.937500, 380000.000000, 380000.093750, 380000.406250, 380001.250000",\
+ "380000.031250, 380000.093750, 380000.187500, 380000.500000, 380001.343750",\
+ "380000.093750, 380000.156250, 380000.250000, 380000.562500, 380001.406250",\
+ "380000.250000, 380000.312500, 380000.406250, 380000.718750, 380001.562500",\
+ "380000.468750, 380000.531250, 380000.625000, 380000.937500, 380001.781250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\
+ "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\
+ "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\
+ "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\
+ "0.118145, 0.231881, 0.431660, 0.979741, 2.437852");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380001.375000, 380001.406250, 380001.437500, 380001.500000, 380001.687500",\
+ "380001.468750, 380001.500000, 380001.531250, 380001.593750, 380001.781250",\
+ "380001.562500, 380001.593750, 380001.625000, 380001.687500, 380001.875000",\
+ "380001.750000, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\
+ "380002.000000, 380002.031250, 380002.062500, 380002.125000, 380002.312500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una_min*/
+
+} /* end of pin ast_pwst_o[2] */
+
+pin("ast_pwst_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.101136 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\
+ "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\
+ "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\
+ "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\
+ "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\
+ "7.693051, 7.884589, 8.004029, 8.262691, 9.135794");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\
+ "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\
+ "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\
+ "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\
+ "5.773359, 5.930601, 6.056160, 6.243834, 6.833694");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\
+ "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\
+ "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\
+ "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\
+ "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\
+ "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\
+ "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\
+ "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\
+ "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\
+ "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\
+ "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\
+ "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\
+ "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\
+ "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\
+ "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\
+ "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\
+ "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\
+ "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\
+ "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\
+ "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\
+ "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\
+ "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\
+ "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\
+ "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\
+ "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\
+ "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\
+ "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\
+ "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\
+ "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una_min*/
+
+} /* end of pin ast_pwst_o[1] */
+
+pin("ast_pwst_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.101136 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\
+ "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\
+ "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\
+ "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\
+ "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\
+ "7.693051, 7.884589, 8.004029, 8.262691, 9.135794");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\
+ "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\
+ "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\
+ "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\
+ "5.773359, 5.930601, 6.056160, 6.243834, 6.833694");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\
+ "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\
+ "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\
+ "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\
+ "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\
+ "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\
+ "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\
+ "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\
+ "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\
+ "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\
+ "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\
+ "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\
+ "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\
+ "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\
+ "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\
+ "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\
+ "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\
+ "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\
+ "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\
+ "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\
+ "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\
+ "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\
+ "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\
+ "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\
+ "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\
+ "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\
+ "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\
+ "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\
+ "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una_min*/
+
+} /* end of pin ast_pwst_o[0] */
+} /* end of bus ast_pwst_o */
+bus ( ast_pwst_h_o ) {
+
+ bus_type : BUS5_type4 ;
+ direction : output ;
+
+pin("ast_pwst_h_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003358 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_h_o[4];
+} /* end of pin ast_pwst_h_o[4] */
+
+pin("ast_pwst_h_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.007560 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_h_o[3];
+} /* end of pin ast_pwst_h_o[3] */
+
+pin("ast_pwst_h_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.029213 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000584 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_h_o[2];
+ timing () {
+ related_pin : "ast_pwst_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\
+ "0.125647, 0.191441, 0.306120, 0.621529, 1.461089",\
+ "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\
+ "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\
+ "0.704776, 0.781389, 0.901027, 1.217412, 2.063059");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.118650, 0.232640, 0.431328, 0.981607, 2.441227",\
+ "0.118668, 0.232640, 0.431330, 0.981682, 2.441227",\
+ "0.118668, 0.233537, 0.432463, 0.981682, 2.441227",\
+ "0.120002, 0.233537, 0.433774, 0.981682, 2.441227",\
+ "0.161250, 0.255527, 0.435044, 0.981682, 2.441227");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\
+ "0.068682, 0.082462, 0.106420, 0.172219, 0.347402",\
+ "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\
+ "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\
+ "0.645975, 0.686648, 0.737659, 0.832084, 1.014107");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.026953, 0.051423, 0.094862, 0.215093, 0.534102",\
+ "0.026955, 0.051424, 0.094862, 0.215093, 0.534102",\
+ "0.033450, 0.053875, 0.094993, 0.215093, 0.534241",\
+ "0.046741, 0.065795, 0.101823, 0.215093, 0.534701",\
+ "0.120319, 0.148529, 0.186126, 0.267902, 0.543427");
+ }
+
+ } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "ast_pwst_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\
+ "0.125568, 0.191362, 0.306040, 0.621450, 1.461010",\
+ "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\
+ "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\
+ "0.704776, 0.781389, 0.901027, 1.217412, 2.063059");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.118650, 0.232611, 0.431328, 0.977612, 2.431972",\
+ "0.118650, 0.232611, 0.431330, 0.977612, 2.431972",\
+ "0.118650, 0.233259, 0.432463, 0.977612, 2.431972",\
+ "0.120002, 0.233259, 0.433774, 0.977612, 2.431972",\
+ "0.161250, 0.255527, 0.435044, 0.981481, 2.431972");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\
+ "0.068410, 0.082189, 0.106148, 0.171946, 0.347129",\
+ "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\
+ "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\
+ "0.645975, 0.686648, 0.737659, 0.832084, 1.014107");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.026953, 0.051423, 0.094862, 0.214557, 0.534102",\
+ "0.026954, 0.051424, 0.094862, 0.214557, 0.534102",\
+ "0.033450, 0.053875, 0.094993, 0.214557, 0.534241",\
+ "0.046741, 0.065795, 0.101823, 0.215088, 0.534701",\
+ "0.120319, 0.148529, 0.186126, 0.267902, 0.543427");
+ }
+
+ } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una_min*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.120145, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.404676, 0.353105, 0.318351, 0.315478, 0.348023",\
+ "0.454532, 0.402961, 0.368207, 0.365334, 0.397879",\
+ "0.484555, 0.432984, 0.398230, 0.395357, 0.427902",\
+ "0.566329, 0.514758, 0.480004, 0.477131, 0.509676",\
+ "0.956464, 0.904894, 0.869963, 0.866772, 0.898621");
+ }
+
+ } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.118140, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.316729, -0.270030, -0.234537, -0.184982, -0.086025",\
+ "-0.365783, -0.319083, -0.283591, -0.234035, -0.135079",\
+ "-0.396608, -0.349909, -0.314416, -0.264861, -0.165904",\
+ "-0.478382, -0.431683, -0.396190, -0.346635, -0.247678",\
+ "-0.868371, -0.821645, -0.786315, -0.736867, -0.638027");
+ }
+
+ } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380000.531250, 380000.593750, 380000.718750, 380001.031250, 380001.875000",\
+ "380000.625000, 380000.687500, 380000.812500, 380001.125000, 380001.968750",\
+ "380000.687500, 380000.750000, 380000.875000, 380001.187500, 380002.031250",\
+ "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\
+ "380001.062500, 380001.125000, 380001.250000, 380001.562500, 380002.406250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\
+ "380001.968750, 380001.968750, 380002.000000, 380002.062500, 380002.250000",\
+ "380002.062500, 380002.062500, 380002.093750, 380002.156250, 380002.343750",\
+ "380002.125000, 380002.125000, 380002.156250, 380002.218750, 380002.406250",\
+ "380002.468750, 380002.468750, 380002.500000, 380002.562500, 380002.750000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\
+ "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\
+ "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\
+ "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\
+ "0.031251, 0.056161, 0.101276, 0.226771, 0.561875");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.396377, 0.462195, 0.577090, 0.892530, 1.731965",\
+ "0.483687, 0.549505, 0.664400, 0.979841, 1.819276",\
+ "0.581466, 0.647284, 0.762179, 1.077619, 1.917054",\
+ "0.654025, 0.719843, 0.834738, 1.150178, 1.989613",\
+ "1.042482, 1.108301, 1.223195, 1.538636, 2.378071");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\
+ "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\
+ "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\
+ "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\
+ "0.118140, 0.231881, 0.431660, 0.979741, 2.437812");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.326727, 0.341464, 0.366815, 0.435950, 0.619738",\
+ "0.414576, 0.429313, 0.454664, 0.523799, 0.707587",\
+ "0.495656, 0.510394, 0.535744, 0.604879, 0.788667",\
+ "0.553927, 0.568665, 0.594015, 0.663150, 0.846938",\
+ "0.864022, 0.878760, 0.904110, 0.973245, 1.157033");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380000.406250, 380000.468750, 380000.593750, 380000.906250, 380001.750000",\
+ "380000.500000, 380000.562500, 380000.687500, 380001.000000, 380001.843750",\
+ "380000.593750, 380000.656250, 380000.781250, 380001.093750, 380001.937500",\
+ "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\
+ "380001.000000, 380001.062500, 380001.187500, 380001.500000, 380002.343750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\
+ "0.120145, 0.234100, 0.432069, 0.982878, 2.445448");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380001.781250, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\
+ "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\
+ "380002.000000, 380002.000000, 380002.031250, 380002.093750, 380002.281250",\
+ "380002.187500, 380002.187500, 380002.218750, 380002.281250, 380002.468750",\
+ "380002.500000, 380002.500000, 380002.531250, 380002.593750, 380002.781250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\
+ "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\
+ "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\
+ "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\
+ "0.031236, 0.056156, 0.101275, 0.226769, 0.561877");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "379999.937500, 380000.000000, 380000.093750, 380000.406250, 380001.250000",\
+ "380000.031250, 380000.093750, 380000.187500, 380000.500000, 380001.343750",\
+ "380000.093750, 380000.156250, 380000.250000, 380000.562500, 380001.406250",\
+ "380000.250000, 380000.312500, 380000.406250, 380000.718750, 380001.562500",\
+ "380000.468750, 380000.531250, 380000.625000, 380000.937500, 380001.781250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\
+ "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\
+ "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\
+ "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\
+ "0.118145, 0.231881, 0.431660, 0.979741, 2.437852");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "380001.375000, 380001.406250, 380001.437500, 380001.500000, 380001.687500",\
+ "380001.468750, 380001.500000, 380001.531250, 380001.593750, 380001.781250",\
+ "380001.562500, 380001.593750, 380001.625000, 380001.687500, 380001.875000",\
+ "380001.750000, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\
+ "380002.000000, 380002.031250, 380002.062500, 380002.125000, 380002.312500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213");
+ values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\
+ "0.026020, 0.051544, 0.096671, 0.220662, 0.551206");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una_min*/
+
+} /* end of pin ast_pwst_h_o[2] */
+
+pin("ast_pwst_h_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.101136 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_h_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\
+ "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\
+ "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\
+ "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\
+ "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\
+ "7.693051, 7.884589, 8.004029, 8.262691, 9.135794");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\
+ "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\
+ "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\
+ "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\
+ "5.773359, 5.930601, 6.056160, 6.243834, 6.833694");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\
+ "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\
+ "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\
+ "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\
+ "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\
+ "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\
+ "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\
+ "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\
+ "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\
+ "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\
+ "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\
+ "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\
+ "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\
+ "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\
+ "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\
+ "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\
+ "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\
+ "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\
+ "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\
+ "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\
+ "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\
+ "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\
+ "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\
+ "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\
+ "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\
+ "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\
+ "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\
+ "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\
+ "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una_min*/
+
+} /* end of pin ast_pwst_h_o[1] */
+
+pin("ast_pwst_h_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.101136 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast_pwst_h_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\
+ "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\
+ "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\
+ "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\
+ "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\
+ "7.693051, 7.884589, 8.004029, 8.262691, 9.135794");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\
+ "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\
+ "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\
+ "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\
+ "5.773359, 5.930601, 6.056160, 6.243834, 6.833694");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\
+ "0.242588, 0.288084, 0.303651, 0.497673, 1.551133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\
+ "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\
+ "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\
+ "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\
+ "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\
+ "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\
+ "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\
+ "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\
+ "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\
+ "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\
+ "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\
+ "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\
+ "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\
+ "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\
+ "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\
+ "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\
+ "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\
+ "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\
+ "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\
+ "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\
+ "0.256850, 0.317997, 0.317997, 0.797663, 2.394832");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\
+ "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\
+ "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\
+ "0.242595, 0.288092, 0.303657, 0.497674, 1.551132");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\
+ "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\
+ "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\
+ "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\
+ "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\
+ "0.256090, 0.317188, 0.317188, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\
+ "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\
+ "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\
+ "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\
+ "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\
+ "0.256090, 0.291712, 0.291712, 0.797460, 2.395127");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\
+ "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\
+ "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\
+ "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\
+ "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136");
+ values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\
+ "0.242962, 0.288493, 0.303943, 0.497719, 1.551101");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una_min*/
+
+} /* end of pin ast_pwst_h_o[0] */
+} /* end of bus ast_pwst_h_o */
+
+pin("main_pd_ni") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001140 ;
+
+ /* Other user defined attributes. */
+ original_pin : main_pd_ni;
+} /* end of pin main_pd_ni */
+
+pin("main_env_iso_en_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000488 ;
+
+ /* Other user defined attributes. */
+ original_pin : main_env_iso_en_i;
+} /* end of pin main_env_iso_en_i */
+
+pin("flash_power_down_h_o") {
+ direction : output ;
+ max_transition : 3.720000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.350585 ;
+ min_capacitance : 0.000387 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.004062 ;
+
+ /* Other user defined attributes. */
+ original_pin : flash_power_down_h_o;
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380000.718750, 380000.781250, 380000.937500, 380001.375000, 380002.718750",\
+ "380000.812500, 380000.875000, 380001.031250, 380001.468750, 380002.812500",\
+ "380000.875000, 380000.937500, 380001.093750, 380001.531250, 380002.875000",\
+ "380000.937500, 380001.000000, 380001.156250, 380001.593750, 380002.937500",\
+ "380001.250000, 380001.312500, 380001.468750, 380001.906250, 380003.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074057, 0.193193, 0.452097, 1.259663, 3.712074",\
+ "0.074058, 0.193193, 0.452097, 1.259663, 3.712070",\
+ "0.074060, 0.193194, 0.452097, 1.259660, 3.712049",\
+ "0.074063, 0.193195, 0.452097, 1.259657, 3.712028",\
+ "0.074111, 0.193204, 0.452092, 1.259600, 3.711658");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380002.000000, 380002.031250, 380002.093750, 380002.312500, 380002.843750",\
+ "380002.093750, 380002.125000, 380002.187500, 380002.406250, 380002.937500",\
+ "380002.187500, 380002.218750, 380002.281250, 380002.500000, 380003.031250",\
+ "380002.250000, 380002.281250, 380002.343750, 380002.562500, 380003.093750",\
+ "380002.593750, 380002.625000, 380002.687500, 380002.906250, 380003.437500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_power_down_h_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.352648, 0.424230, 0.570187, 1.017271, 2.367661",\
+ "0.440969, 0.512551, 0.658508, 1.105592, 2.455982",\
+ "0.531538, 0.603120, 0.749077, 1.196161, 2.546552",\
+ "0.596976, 0.668558, 0.814515, 1.261599, 2.611990",\
+ "0.939689, 1.011271, 1.157229, 1.604312, 2.954703");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.254546, 0.300198, 0.374019, 0.564384, 1.125543",\
+ "0.341890, 0.387542, 0.461363, 0.651728, 1.212887",\
+ "0.422786, 0.468439, 0.542260, 0.732625, 1.293784",\
+ "0.480635, 0.526288, 0.600109, 0.790475, 1.351633",\
+ "0.785321, 0.830974, 0.904795, 1.095161, 1.656318");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054514, 0.105890, 0.199332, 0.496290, 1.444361",\
+ "0.054514, 0.105890, 0.199332, 0.496290, 1.444361",\
+ "0.054513, 0.105889, 0.199332, 0.496290, 1.444360",\
+ "0.054513, 0.105887, 0.199332, 0.496290, 1.444359",\
+ "0.054513, 0.105887, 0.199332, 0.496290, 1.444358");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_power_down_h_o_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380000.593750, 380000.656250, 380000.812500, 380001.250000, 380002.593750",\
+ "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\
+ "380000.781250, 380000.843750, 380001.000000, 380001.437500, 380002.781250",\
+ "380000.937500, 380001.000000, 380001.156250, 380001.593750, 380002.937500",\
+ "380001.187500, 380001.250000, 380001.406250, 380001.843750, 380003.187500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380001.906250, 380001.937500, 380002.000000, 380002.218750, 380002.750000",\
+ "380002.000000, 380002.031250, 380002.093750, 380002.312500, 380002.843750",\
+ "380002.125000, 380002.156250, 380002.218750, 380002.437500, 380002.968750",\
+ "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\
+ "380002.625000, 380002.656250, 380002.718750, 380002.937500, 380003.468750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364");
+ }
+
+ } /* end of arc padmux2ast_i[4]_flash_power_down_h_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380000.593750, 380000.656250, 380000.812500, 380001.250000, 380002.593750",\
+ "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\
+ "380000.750000, 380000.812500, 380000.968750, 380001.406250, 380002.750000",\
+ "380000.906250, 380000.968750, 380001.125000, 380001.562500, 380002.906250",\
+ "380001.125000, 380001.187500, 380001.343750, 380001.781250, 380003.125000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\
+ "0.074048, 0.193192, 0.452098, 1.259674, 3.712141");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380001.906250, 380001.937500, 380002.000000, 380002.218750, 380002.750000",\
+ "380002.000000, 380002.031250, 380002.093750, 380002.312500, 380002.843750",\
+ "380002.093750, 380002.125000, 380002.187500, 380002.406250, 380002.937500",\
+ "380002.281250, 380002.312500, 380002.375000, 380002.593750, 380003.125000",\
+ "380002.531250, 380002.562500, 380002.625000, 380002.843750, 380003.375000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\
+ "0.054518, 0.105901, 0.199326, 0.496289, 1.444364");
+ }
+
+ } /* end of arc padmux2ast_i[4]_flash_power_down_h_o_una_min*/
+
+} /* end of pin flash_power_down_h_o */
+
+pin("flash_power_ready_h_o") {
+ direction : output ;
+ max_transition : 3.720000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.350585 ;
+ min_capacitance : 0.000387 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.004062 ;
+
+ /* Other user defined attributes. */
+ original_pin : flash_power_ready_h_o;
+} /* end of pin flash_power_ready_h_o */
+bus ( otp_power_seq_i ) {
+
+ bus_type : BUS2_type5 ;
+ direction : input ;
+
+pin("otp_power_seq_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002066 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_power_seq_i[1];
+} /* end of pin otp_power_seq_i[1] */
+
+pin("otp_power_seq_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002439 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_power_seq_i[0];
+} /* end of pin otp_power_seq_i[0] */
+} /* end of bus otp_power_seq_i */
+bus ( otp_power_seq_h_o ) {
+
+ bus_type : BUS2_type5 ;
+ direction : output ;
+
+pin("otp_power_seq_h_o[1]") {
+ direction : output ;
+ max_transition : 3.720000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.350585 ;
+ min_capacitance : 0.000387 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.004062 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_power_seq_h_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380000.812500, 380000.875000, 380001.031250, 380001.468750, 380002.812500",\
+ "380000.906250, 380000.968750, 380001.125000, 380001.562500, 380002.906250",\
+ "380000.968750, 380001.031250, 380001.187500, 380001.625000, 380002.968750",\
+ "380001.031250, 380001.093750, 380001.250000, 380001.687500, 380003.031250",\
+ "380001.343750, 380001.406250, 380001.562500, 380002.000000, 380003.343750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\
+ "380002.406250, 380002.437500, 380002.500000, 380002.718750, 380003.250000",\
+ "380002.500000, 380002.531250, 380002.593750, 380002.812500, 380003.343750",\
+ "380002.562500, 380002.593750, 380002.656250, 380002.875000, 380003.406250",\
+ "380002.906250, 380002.937500, 380003.000000, 380003.218750, 380003.750000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343");
+ }
+
+ } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.448711, 0.520292, 0.666247, 1.113340, 2.463725",\
+ "0.537164, 0.608745, 0.754701, 1.201793, 2.552178",\
+ "0.627117, 0.698698, 0.844654, 1.291746, 2.642131",\
+ "0.691522, 0.763103, 0.909059, 1.356151, 2.706536",\
+ "1.028584, 1.100166, 1.246121, 1.693213, 3.043598");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.535143, 0.580795, 0.654612, 0.844979, 1.406126",\
+ "0.622520, 0.668171, 0.741989, 0.932356, 1.493503",\
+ "0.703389, 0.749041, 0.822858, 1.013225, 1.574372",\
+ "0.761087, 0.806739, 0.880556, 1.070923, 1.632070",\
+ "1.064074, 1.109726, 1.183543, 1.373910, 1.935057");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343");
+ }
+
+ } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "otp_power_seq_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.280735, 0.352314, 0.498262, 0.945381, 2.295748",\
+ "0.365932, 0.437494, 0.583395, 1.030705, 2.380943",\
+ "0.458471, 0.529972, 0.675698, 1.123714, 2.473475",\
+ "0.634070, 0.705499, 0.850886, 1.299582, 2.649080",\
+ "0.942777, 1.014243, 1.159029, 1.607148, 2.957408");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074065, 0.193195, 0.452096, 1.259655, 3.712015",\
+ "0.074153, 0.193212, 0.452096, 1.259655, 3.712015",\
+ "0.074479, 0.193278, 0.452096, 1.259655, 3.712015",\
+ "0.075512, 0.193773, 0.452096, 1.259655, 3.712015",\
+ "0.077859, 0.195201, 0.452096, 1.259655, 3.712015");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.164110, 0.209762, 0.283580, 0.473944, 1.035104",\
+ "0.247135, 0.292784, 0.366597, 0.556994, 1.118023",\
+ "0.324377, 0.370013, 0.443807, 0.634329, 1.194869",\
+ "0.452551, 0.498155, 0.571901, 0.762742, 1.322028",\
+ "0.650770, 0.696491, 0.770670, 0.961172, 1.520128");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054518, 0.105900, 0.199326, 0.496289, 1.444363",\
+ "0.054583, 0.105900, 0.199350, 0.496296, 1.444363",\
+ "0.054828, 0.105900, 0.199442, 0.496321, 1.444363",\
+ "0.055455, 0.105900, 0.199678, 0.496387, 1.444363",\
+ "0.057468, 0.107107, 0.200875, 0.496387, 1.444363");
+ }
+
+ } /* end of arc otp_power_seq_i[1]_otp_power_seq_h_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_power_seq_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.280735, 0.352314, 0.498262, 0.945381, 2.295748",\
+ "0.365932, 0.437494, 0.583395, 1.030705, 2.380943",\
+ "0.458471, 0.529972, 0.675698, 1.123714, 2.473475",\
+ "0.634070, 0.705499, 0.850886, 1.299582, 2.649080",\
+ "0.942777, 1.014243, 1.159029, 1.607148, 2.957408");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074065, 0.193195, 0.451499, 1.259037, 3.706044",\
+ "0.074153, 0.193212, 0.451499, 1.259037, 3.706044",\
+ "0.074479, 0.193278, 0.451499, 1.259037, 3.706044",\
+ "0.075512, 0.193773, 0.451499, 1.259037, 3.706044",\
+ "0.077859, 0.195201, 0.451499, 1.259378, 3.706689");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.164110, 0.209762, 0.283580, 0.473944, 1.035104",\
+ "0.247135, 0.292784, 0.366597, 0.556994, 1.118023",\
+ "0.324377, 0.370013, 0.443807, 0.634329, 1.194869",\
+ "0.452551, 0.498155, 0.571901, 0.762742, 1.322028",\
+ "0.650770, 0.696491, 0.770670, 0.961172, 1.520128");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054518, 0.104862, 0.199326, 0.496289, 1.441414",\
+ "0.054583, 0.104862, 0.199350, 0.496296, 1.441414",\
+ "0.054828, 0.104862, 0.199442, 0.496321, 1.441414",\
+ "0.055455, 0.104862, 0.199678, 0.496356, 1.441414",\
+ "0.057468, 0.107107, 0.200875, 0.496356, 1.442153");
+ }
+
+ } /* end of arc otp_power_seq_i[1]_otp_power_seq_h_o[1]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\
+ "380000.781250, 380000.843750, 380001.000000, 380001.437500, 380002.781250",\
+ "380000.875000, 380000.937500, 380001.093750, 380001.531250, 380002.875000",\
+ "380001.031250, 380001.093750, 380001.250000, 380001.687500, 380003.031250",\
+ "380001.281250, 380001.343750, 380001.500000, 380001.937500, 380003.281250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380002.218750, 380002.250000, 380002.312500, 380002.531250, 380003.062500",\
+ "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\
+ "380002.437500, 380002.468750, 380002.531250, 380002.750000, 380003.281250",\
+ "380002.625000, 380002.656250, 380002.718750, 380002.937500, 380003.468750",\
+ "380002.937500, 380002.968750, 380003.031250, 380003.250000, 380003.781250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343");
+ }
+
+ } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\
+ "380000.781250, 380000.843750, 380001.000000, 380001.437500, 380002.781250",\
+ "380000.843750, 380000.906250, 380001.062500, 380001.500000, 380002.843750",\
+ "380001.000000, 380001.062500, 380001.218750, 380001.656250, 380003.000000",\
+ "380001.218750, 380001.281250, 380001.437500, 380001.875000, 380003.218750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\
+ "0.074053, 0.193192, 0.452098, 1.259669, 3.712109");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380002.218750, 380002.250000, 380002.312500, 380002.531250, 380003.062500",\
+ "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\
+ "380002.406250, 380002.437500, 380002.500000, 380002.718750, 380003.250000",\
+ "380002.593750, 380002.625000, 380002.687500, 380002.906250, 380003.437500",\
+ "380002.843750, 380002.875000, 380002.937500, 380003.156250, 380003.687500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\
+ "0.054525, 0.105893, 0.199328, 0.496289, 1.444343");
+ }
+
+ } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[1]_una_min*/
+
+} /* end of pin otp_power_seq_h_o[1] */
+
+pin("otp_power_seq_h_o[0]") {
+ direction : output ;
+ max_transition : 3.720000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.350585 ;
+ min_capacitance : 0.000387 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.004062 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_power_seq_h_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380002.312500, 380002.406250, 380002.531250, 380003.000000, 380004.343750",\
+ "380002.406250, 380002.500000, 380002.625000, 380003.093750, 380004.437500",\
+ "380002.500000, 380002.593750, 380002.718750, 380003.187500, 380004.531250",\
+ "380002.562500, 380002.656250, 380002.781250, 380003.250000, 380004.593750",\
+ "380002.906250, 380003.000000, 380003.125000, 380003.593750, 380004.937500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.073833, 0.193149, 0.452120, 1.259926, 3.713809",\
+ "0.073833, 0.193149, 0.452120, 1.259926, 3.713809",\
+ "0.073833, 0.193149, 0.452120, 1.259926, 3.713809",\
+ "0.073834, 0.193149, 0.452120, 1.259926, 3.713806",\
+ "0.073834, 0.193149, 0.452120, 1.259926, 3.713804");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380000.593750, 380000.656250, 380000.718750, 380000.906250, 380001.468750",\
+ "380000.687500, 380000.750000, 380000.812500, 380001.000000, 380001.562500",\
+ "380000.750000, 380000.812500, 380000.875000, 380001.062500, 380001.625000",\
+ "380000.812500, 380000.875000, 380000.937500, 380001.125000, 380001.687500",\
+ "380001.125000, 380001.187500, 380001.250000, 380001.437500, 380002.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054415, 0.105307, 0.199650, 0.496371, 1.443909",\
+ "0.054415, 0.105307, 0.199650, 0.496371, 1.443909",\
+ "0.054415, 0.105307, 0.199650, 0.496371, 1.443909",\
+ "0.054415, 0.105309, 0.199649, 0.496371, 1.443911",\
+ "0.054417, 0.105319, 0.199643, 0.496370, 1.443919");
+ }
+
+ } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.573426, 0.645049, 0.791123, 1.237737, 2.588445",\
+ "0.660803, 0.732425, 0.878500, 1.325114, 2.675822",\
+ "0.741672, 0.813295, 0.959369, 1.405983, 2.756691",\
+ "0.799370, 0.870993, 1.017067, 1.463682, 2.814389",\
+ "1.102357, 1.173980, 1.320054, 1.766668, 3.117376");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.260939, 0.306616, 0.380550, 0.571046, 1.131945",\
+ "0.349392, 0.395070, 0.469004, 0.659499, 1.220399",\
+ "0.439345, 0.485023, 0.558957, 0.749452, 1.310352",\
+ "0.503750, 0.549428, 0.623362, 0.813857, 1.374757",\
+ "0.840813, 0.886490, 0.960424, 1.150919, 1.711819");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908");
+ }
+
+ } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "otp_power_seq_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.258742, 0.330399, 0.476573, 0.922786, 2.273765",\
+ "0.342268, 0.413906, 0.560027, 1.006455, 2.357289",\
+ "0.432373, 0.503959, 0.649927, 1.096969, 2.447388",\
+ "0.604916, 0.676353, 0.821884, 1.270636, 2.619913",\
+ "0.890695, 0.962107, 1.107175, 1.555746, 2.905733");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.073647, 0.193112, 0.452140, 1.260145, 3.715251",\
+ "0.073746, 0.193131, 0.452140, 1.260145, 3.715251",\
+ "0.074030, 0.193188, 0.452140, 1.260145, 3.715251",\
+ "0.074867, 0.193375, 0.452140, 1.260145, 3.715251",\
+ "0.076941, 0.194654, 0.452140, 1.260145, 3.715251");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.158895, 0.204571, 0.278502, 0.468994, 1.029901",\
+ "0.236396, 0.282061, 0.355936, 0.546363, 1.107398",\
+ "0.299798, 0.345438, 0.419238, 0.609722, 1.170409",\
+ "0.399856, 0.445471, 0.519267, 0.710096, 1.269222",\
+ "0.539370, 0.585337, 0.659872, 0.850367, 1.409363");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054417, 0.105322, 0.199642, 0.496369, 1.443922",\
+ "0.054466, 0.105609, 0.199642, 0.496369, 1.443922",\
+ "0.054754, 0.105639, 0.199642, 0.496369, 1.443922",\
+ "0.055765, 0.105639, 0.199849, 0.496390, 1.443922",\
+ "0.058856, 0.108680, 0.201816, 0.496464, 1.443922");
+ }
+
+ } /* end of arc otp_power_seq_i[0]_otp_power_seq_h_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_power_seq_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.258742, 0.330399, 0.476573, 0.922786, 2.273765",\
+ "0.342268, 0.413906, 0.560027, 1.006455, 2.357289",\
+ "0.432373, 0.503959, 0.649927, 1.096969, 2.447388",\
+ "0.604916, 0.676353, 0.821884, 1.270636, 2.619913",\
+ "0.890695, 0.962107, 1.107175, 1.555746, 2.905733");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.073647, 0.193112, 0.451380, 1.258785, 3.705802",\
+ "0.073746, 0.193131, 0.451380, 1.258785, 3.705802",\
+ "0.074030, 0.193188, 0.451380, 1.258785, 3.705802",\
+ "0.074867, 0.193375, 0.451380, 1.258785, 3.705802",\
+ "0.076941, 0.194654, 0.451380, 1.259595, 3.705802");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.158895, 0.204571, 0.278502, 0.468994, 1.029901",\
+ "0.236396, 0.282061, 0.355936, 0.546363, 1.107398",\
+ "0.299798, 0.345438, 0.419238, 0.609722, 1.170409",\
+ "0.399856, 0.445471, 0.519267, 0.710096, 1.269222",\
+ "0.539370, 0.585337, 0.659872, 0.850367, 1.409363");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054417, 0.105076, 0.199414, 0.496314, 1.441319",\
+ "0.054466, 0.105076, 0.199414, 0.496314, 1.441319",\
+ "0.054754, 0.105076, 0.199414, 0.496314, 1.441319",\
+ "0.055765, 0.105076, 0.199849, 0.496390, 1.441319",\
+ "0.058856, 0.108680, 0.201816, 0.496464, 1.442721");
+ }
+
+ } /* end of arc otp_power_seq_i[0]_otp_power_seq_h_o[0]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380000.468750, 380000.531250, 380000.593750, 380000.781250, 380001.343750",\
+ "380000.562500, 380000.625000, 380000.687500, 380000.875000, 380001.437500",\
+ "380000.656250, 380000.718750, 380000.781250, 380000.968750, 380001.531250",\
+ "380000.812500, 380000.875000, 380000.937500, 380001.125000, 380001.687500",\
+ "380001.062500, 380001.125000, 380001.187500, 380001.375000, 380001.937500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380002.218750, 380002.312500, 380002.437500, 380002.906250, 380004.250000",\
+ "380002.312500, 380002.406250, 380002.531250, 380003.000000, 380004.343750",\
+ "380002.437500, 380002.531250, 380002.656250, 380003.125000, 380004.468750",\
+ "380002.625000, 380002.718750, 380002.843750, 380003.312500, 380004.656250",\
+ "380002.937500, 380003.031250, 380003.156250, 380003.625000, 380004.968750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817");
+ }
+
+ } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380000.468750, 380000.531250, 380000.593750, 380000.781250, 380001.343750",\
+ "380000.562500, 380000.625000, 380000.687500, 380000.875000, 380001.437500",\
+ "380000.625000, 380000.687500, 380000.750000, 380000.937500, 380001.500000",\
+ "380000.781250, 380000.843750, 380000.906250, 380001.093750, 380001.656250",\
+ "380001.000000, 380001.062500, 380001.125000, 380001.312500, 380001.875000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\
+ "0.054414, 0.105305, 0.199651, 0.496372, 1.443908");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "380002.218750, 380002.312500, 380002.437500, 380002.906250, 380004.250000",\
+ "380002.312500, 380002.406250, 380002.531250, 380003.000000, 380004.343750",\
+ "380002.406250, 380002.500000, 380002.625000, 380003.093750, 380004.437500",\
+ "380002.593750, 380002.687500, 380002.812500, 380003.281250, 380004.625000",\
+ "380002.843750, 380002.937500, 380003.062500, 380003.531250, 380004.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585");
+ values ( "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\
+ "0.073832, 0.193148, 0.452121, 1.259928, 3.713817");
+ }
+
+ } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[0]_inv_min*/
+
+} /* end of pin otp_power_seq_h_o[0] */
+} /* end of bus otp_power_seq_h_o */
+
+pin("clk_src_sys_en_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002156 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_sys_en_i;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\
+ "0.271588, 0.219415, 0.179927, 0.162045, 0.157577",\
+ "0.363033, 0.310027, 0.270334, 0.252385, 0.247965",\
+ "0.507780, 0.454308, 0.413646, 0.395357, 0.391106",\
+ "0.811131, 0.757315, 0.714144, 0.694969, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\
+ "0.324602, 0.241857, 0.166855, 0.126539, 0.100040",\
+ "0.429418, 0.345854, 0.270221, 0.227986, 0.196782",\
+ "0.605833, 0.521783, 0.445878, 0.397956, 0.350944",\
+ "0.983325, 0.898854, 0.822917, 0.761117, 0.674795");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_en_i_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\
+ "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\
+ "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\
+ "-0.373429, -0.330963, -0.299719, -0.251733, -0.152256",\
+ "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\
+ "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\
+ "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\
+ "-0.470591, -0.397956, -0.329423, -0.234665, -0.046227",\
+ "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_en_i_hldr*/
+
+} /* end of pin clk_src_sys_en_i */
+bus ( clk_src_sys_jen_i ) {
+
+ bus_type : BUS4_type6 ;
+ direction : input ;
+
+pin("clk_src_sys_jen_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_sys_jen_i[3];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.116868, 0.046289, 0.009123, -0.023399, -0.072101",\
+ "0.130035, 0.060315, 0.022495, -0.010308, -0.059037",\
+ "0.171476, 0.101933, 0.064692, 0.030941, -0.021156",\
+ "0.330098, 0.263569, 0.222296, 0.181197, 0.112987",\
+ "0.772581, 0.713134, 0.646673, 0.587289, 0.496722");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.164832, 0.206226, 0.283518, 0.436969, 0.781571",\
+ "0.176771, 0.218346, 0.296254, 0.450000, 0.794722",\
+ "0.219963, 0.260510, 0.337961, 0.490822, 0.833567",\
+ "0.396019, 0.435268, 0.507744, 0.654408, 0.985407",\
+ "0.931350, 0.951153, 1.007354, 1.144760, 1.468564");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.015255, 0.029491, 0.060650, 0.100375, 0.176530",\
+ "-0.028040, 0.015174, 0.046352, 0.086407, 0.163478",\
+ "-0.067695, -0.029062, 0.006032, 0.048125, 0.126390",\
+ "-0.170614, -0.143005, -0.113142, -0.070129, 0.016864",\
+ "-0.388675, -0.412783, -0.403332, -0.363654, -0.262218");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.058687, -0.133819, -0.215174, -0.342668, -0.608913",\
+ "-0.070579, -0.145649, -0.226804, -0.353700, -0.618487",\
+ "-0.113780, -0.187774, -0.267897, -0.394083, -0.658063",\
+ "-0.257059, -0.339271, -0.416614, -0.539608, -0.797794",\
+ "-0.613549, -0.743897, -0.832843, -0.961101, -1.220625");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[3]_hldr*/
+
+} /* end of pin clk_src_sys_jen_i[3] */
+
+pin("clk_src_sys_jen_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_sys_jen_i[2];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\
+ "0.210849, 0.158775, 0.118789, 0.100962, 0.097230",\
+ "0.247906, 0.195949, 0.156513, 0.138649, 0.134169",\
+ "0.400793, 0.347442, 0.307665, 0.289688, 0.285288",\
+ "0.811131, 0.757315, 0.714144, 0.694969, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\
+ "0.258619, 0.175944, 0.100656, 0.060195, 0.033618",\
+ "0.297457, 0.214925, 0.140086, 0.100267, 0.074986",\
+ "0.472698, 0.388796, 0.312903, 0.269875, 0.236728",\
+ "0.983325, 0.898854, 0.822917, 0.761117, 0.674795");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\
+ "-0.107327, -0.064625, -0.028931, 0.021950, 0.124428",\
+ "-0.144374, -0.101567, -0.065911, -0.015040, 0.087453",\
+ "-0.286358, -0.243809, -0.210094, -0.159889, -0.057011",\
+ "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\
+ "-0.140562, -0.065848, 0.000282, 0.091894, 0.274227",\
+ "-0.179341, -0.104491, -0.038333, 0.053525, 0.236523",\
+ "-0.350407, -0.276449, -0.208169, -0.113499, 0.074989",\
+ "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[2]_hldr*/
+
+} /* end of pin clk_src_sys_jen_i[2] */
+
+pin("clk_src_sys_jen_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_sys_jen_i[1];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\
+ "0.210849, 0.158775, 0.118789, 0.100962, 0.097230",\
+ "0.247906, 0.195949, 0.156513, 0.138649, 0.134169",\
+ "0.400793, 0.347442, 0.307665, 0.289688, 0.285288",\
+ "0.811131, 0.757315, 0.714144, 0.694969, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\
+ "0.258619, 0.175944, 0.100656, 0.060195, 0.033618",\
+ "0.297457, 0.214925, 0.140086, 0.100267, 0.074986",\
+ "0.472698, 0.388796, 0.312903, 0.269875, 0.236728",\
+ "0.983325, 0.898854, 0.822917, 0.761117, 0.674795");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\
+ "-0.107327, -0.064625, -0.028931, 0.021950, 0.124428",\
+ "-0.144374, -0.101567, -0.065911, -0.015040, 0.087453",\
+ "-0.286358, -0.243809, -0.210094, -0.159889, -0.057011",\
+ "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\
+ "-0.140562, -0.065848, 0.000282, 0.091894, 0.274227",\
+ "-0.179341, -0.104491, -0.038333, 0.053525, 0.236523",\
+ "-0.350407, -0.276449, -0.208169, -0.113499, 0.074989",\
+ "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[1]_hldr*/
+
+} /* end of pin clk_src_sys_jen_i[1] */
+
+pin("clk_src_sys_jen_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_sys_jen_i[0];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.116868, 0.046289, 0.009123, -0.023399, -0.072101",\
+ "0.130035, 0.060315, 0.022495, -0.010308, -0.059037",\
+ "0.171476, 0.101933, 0.064692, 0.030941, -0.021156",\
+ "0.330098, 0.263569, 0.222296, 0.181197, 0.112987",\
+ "0.772581, 0.713134, 0.646673, 0.587289, 0.496722");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.164832, 0.206226, 0.283518, 0.436969, 0.781571",\
+ "0.176771, 0.218346, 0.296254, 0.450000, 0.794722",\
+ "0.219963, 0.260510, 0.337961, 0.490822, 0.833567",\
+ "0.396019, 0.435268, 0.507744, 0.654408, 0.985407",\
+ "0.931350, 0.951153, 1.007354, 1.144760, 1.468564");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.015255, 0.029491, 0.060650, 0.100375, 0.176530",\
+ "-0.028040, 0.015174, 0.046352, 0.086407, 0.163478",\
+ "-0.067695, -0.029062, 0.006032, 0.048125, 0.126390",\
+ "-0.170614, -0.143005, -0.113142, -0.070129, 0.016864",\
+ "-0.388675, -0.412783, -0.403332, -0.363654, -0.262218");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.058687, -0.133819, -0.215174, -0.342668, -0.608913",\
+ "-0.070579, -0.145649, -0.226804, -0.353700, -0.618487",\
+ "-0.113780, -0.187774, -0.267897, -0.394083, -0.658063",\
+ "-0.257059, -0.339271, -0.416614, -0.539608, -0.797794",\
+ "-0.613549, -0.743897, -0.832843, -0.961101, -1.220625");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[0]_hldr*/
+
+} /* end of pin clk_src_sys_jen_i[0] */
+} /* end of bus clk_src_sys_jen_i */
+
+pin("clk_src_sys_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.069236 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.009042 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_sys_o;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : falling_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\
+ "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\
+ "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\
+ "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\
+ "1.261778, 1.293108, 1.361483, 1.578982, 2.139170");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\
+ "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\
+ "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\
+ "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\
+ "1.205621, 1.248652, 1.342563, 1.639882, 2.402873");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_o_fedg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : falling_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\
+ "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\
+ "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\
+ "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\
+ "1.260982, 1.292312, 1.360687, 1.578186, 2.138375");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\
+ "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\
+ "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\
+ "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\
+ "1.203406, 1.246437, 1.340349, 1.637667, 2.400659");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_o_fedg_min*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "1.165332, 1.196662, 1.265037, 1.482536, 2.042725",\
+ "1.244902, 1.276232, 1.344607, 1.562106, 2.122294",\
+ "1.324816, 1.356146, 1.424521, 1.642020, 2.202208",\
+ "1.454541, 1.485872, 1.554247, 1.771746, 2.331934",\
+ "1.654547, 1.685877, 1.754252, 1.971751, 2.531940");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "1.060530, 1.103561, 1.197473, 1.494792, 2.257783",\
+ "1.149702, 1.192733, 1.286645, 1.583964, 2.346955",\
+ "1.240645, 1.283676, 1.377588, 1.674906, 2.437898",\
+ "1.395684, 1.438715, 1.532626, 1.829945, 2.592937",\
+ "1.648565, 1.691596, 1.785508, 2.082827, 2.845818");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "1.149655, 1.180985, 1.249360, 1.466859, 2.027048",\
+ "1.229405, 1.260735, 1.329110, 1.546609, 2.106797",\
+ "1.304807, 1.336138, 1.404513, 1.622012, 2.182200",\
+ "1.424932, 1.456262, 1.524637, 1.742136, 2.302324",\
+ "1.608101, 1.639431, 1.707806, 1.925305, 2.485494");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "1.052743, 1.095775, 1.189686, 1.487005, 2.249996",\
+ "1.140331, 1.183362, 1.277273, 1.574592, 2.337583",\
+ "1.227129, 1.270160, 1.364072, 1.661390, 2.424382",\
+ "1.376376, 1.419407, 1.513318, 1.810637, 2.573628",\
+ "1.620792, 1.663824, 1.757735, 2.055053, 2.818045");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\
+ "0.321380, 0.396761, 0.561274, 1.083463, 2.426166");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_o_una_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "970011.625000, 970011.687500, 970011.750000, 970011.937500, 970012.500000",\
+ "970011.750000, 970011.812500, 970011.875000, 970012.062500, 970012.625000",\
+ "970011.875000, 970011.937500, 970012.000000, 970012.187500, 970012.750000",\
+ "970011.875000, 970011.937500, 970012.000000, 970012.187500, 970012.750000",\
+ "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.125000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "970010.187500, 970010.250000, 970010.375000, 970010.625000, 970011.437500",\
+ "970010.312500, 970010.375000, 970010.500000, 970010.750000, 970011.562500",\
+ "970010.437500, 970010.500000, 970010.625000, 970010.875000, 970011.687500",\
+ "970010.437500, 970010.500000, 970010.625000, 970010.875000, 970011.687500",\
+ "970010.812500, 970010.875000, 970011.000000, 970011.250000, 970012.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_sys_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.692745, 0.724133, 0.792634, 1.010340, 1.570735",\
+ "0.780545, 0.811933, 0.880435, 1.098141, 1.658535",\
+ "0.861845, 0.893233, 0.961734, 1.179440, 1.739835",\
+ "0.919998, 0.951386, 1.019887, 1.237593, 1.797988",\
+ "1.228719, 1.260107, 1.328608, 1.546314, 2.106709");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.771503, 0.814271, 0.907608, 1.204488, 1.969053",\
+ "0.859377, 0.902145, 0.995481, 1.292362, 2.056926",\
+ "0.953713, 0.996481, 1.089818, 1.386698, 2.151263",\
+ "1.021471, 1.064239, 1.157575, 1.454456, 2.219020",\
+ "1.382169, 1.424937, 1.518274, 1.815154, 2.579719");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_sys_o_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "970007.000000, 970007.000000, 970007.062500, 970007.312500, 970007.875000",\
+ "970007.125000, 970007.125000, 970007.187500, 970007.437500, 970008.000000",\
+ "970007.125000, 970007.125000, 970007.187500, 970007.437500, 970008.000000",\
+ "970007.375000, 970007.375000, 970007.437500, 970007.687500, 970008.250000",\
+ "970007.625000, 970007.625000, 970007.687500, 970007.937500, 970008.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "970010.062500, 970010.125000, 970010.250000, 970010.500000, 970011.312500",\
+ "970010.187500, 970010.250000, 970010.375000, 970010.625000, 970011.437500",\
+ "970010.312500, 970010.375000, 970010.500000, 970010.750000, 970011.562500",\
+ "970010.562500, 970010.625000, 970010.750000, 970011.000000, 970011.812500",\
+ "970010.812500, 970010.875000, 970011.000000, 970011.250000, 970012.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_sys_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "380001.281250, 380001.312500, 380001.375000, 380001.593750, 380002.156250",\
+ "380001.375000, 380001.406250, 380001.468750, 380001.687500, 380002.250000",\
+ "380001.437500, 380001.468750, 380001.531250, 380001.750000, 380002.312500",\
+ "380001.593750, 380001.625000, 380001.687500, 380001.906250, 380002.468750",\
+ "380001.812500, 380001.843750, 380001.906250, 380002.125000, 380002.687500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "380002.656250, 380002.718750, 380002.812500, 380003.093750, 380003.875000",\
+ "380002.750000, 380002.812500, 380002.906250, 380003.187500, 380003.968750",\
+ "380002.843750, 380002.906250, 380003.000000, 380003.281250, 380004.062500",\
+ "380003.031250, 380003.093750, 380003.187500, 380003.468750, 380004.250000",\
+ "380003.281250, 380003.343750, 380003.437500, 380003.718750, 380004.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_sys_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "970008.250000, 970008.250000, 970008.375000, 970008.687500, 970009.437500",\
+ "970008.375000, 970008.375000, 970008.500000, 970008.812500, 970009.562500",\
+ "970008.375000, 970008.375000, 970008.500000, 970008.812500, 970009.562500",\
+ "970008.625000, 970008.625000, 970008.750000, 970009.062500, 970009.812500",\
+ "970008.875000, 970008.875000, 970009.000000, 970009.312500, 970010.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\
+ "0.319241, 0.394420, 0.558621, 1.081391, 2.429504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "970011.500000, 970011.562500, 970011.625000, 970011.812500, 970012.375000",\
+ "970011.625000, 970011.687500, 970011.750000, 970011.937500, 970012.500000",\
+ "970011.750000, 970011.812500, 970011.875000, 970012.062500, 970012.625000",\
+ "970012.000000, 970012.062500, 970012.125000, 970012.312500, 970012.875000",\
+ "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.125000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_sys_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "380000.531250, 380000.562500, 380000.656250, 380000.937500, 380001.718750",\
+ "380000.625000, 380000.656250, 380000.750000, 380001.031250, 380001.812500",\
+ "380000.687500, 380000.718750, 380000.812500, 380001.093750, 380001.875000",\
+ "380000.843750, 380000.875000, 380000.968750, 380001.250000, 380002.031250",\
+ "380001.062500, 380001.093750, 380001.187500, 380001.468750, 380002.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\
+ "0.317826, 0.392935, 0.556854, 1.079626, 2.426166");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "380001.875000, 380001.906250, 380001.968750, 380002.187500, 380002.750000",\
+ "380001.968750, 380002.000000, 380002.062500, 380002.281250, 380002.843750",\
+ "380002.062500, 380002.093750, 380002.156250, 380002.375000, 380002.937500",\
+ "380002.250000, 380002.281250, 380002.343750, 380002.562500, 380003.125000",\
+ "380002.500000, 380002.531250, 380002.593750, 380002.812500, 380003.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_sys_o_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "590009.875000, 590009.937500, 590010.000000, 590010.187500, 590010.750000",\
+ "590010.000000, 590010.062500, 590010.125000, 590010.312500, 590010.875000",\
+ "590010.000000, 590010.062500, 590010.125000, 590010.312500, 590010.875000",\
+ "590010.125000, 590010.187500, 590010.250000, 590010.437500, 590011.000000",\
+ "590010.375000, 590010.437500, 590010.500000, 590010.687500, 590011.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "590008.000000, 590008.000000, 590008.125000, 590008.437500, 590009.187500",\
+ "590008.125000, 590008.125000, 590008.250000, 590008.562500, 590009.312500",\
+ "590008.250000, 590008.250000, 590008.375000, 590008.687500, 590009.437500",\
+ "590008.375000, 590008.375000, 590008.500000, 590008.812500, 590009.562500",\
+ "590008.750000, 590008.750000, 590008.875000, 590009.187500, 590009.937500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\
+ "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\
+ "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\
+ "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\
+ "0.319235, 0.394420, 0.558621, 1.081391, 2.429503");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_sys_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "590008.625000, 590008.625000, 590008.687500, 590008.937500, 590009.500000",\
+ "590008.625000, 590008.625000, 590008.687500, 590008.937500, 590009.500000",\
+ "590008.750000, 590008.750000, 590008.812500, 590009.062500, 590009.625000",\
+ "590008.875000, 590008.875000, 590008.937500, 590009.187500, 590009.750000",\
+ "590009.125000, 590009.125000, 590009.187500, 590009.437500, 590010.000000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "590006.875000, 590006.937500, 590007.000000, 590007.312500, 590008.062500",\
+ "590007.000000, 590007.062500, 590007.125000, 590007.437500, 590008.187500",\
+ "590007.125000, 590007.187500, 590007.250000, 590007.562500, 590008.312500",\
+ "590007.250000, 590007.312500, 590007.375000, 590007.687500, 590008.437500",\
+ "590007.500000, 590007.562500, 590007.625000, 590007.937500, 590008.687500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\
+ "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\
+ "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\
+ "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\
+ "0.319235, 0.394241, 0.557935, 1.080416, 2.426166");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_sys_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "590008.437500, 590008.500000, 590008.625000, 590008.875000, 590009.687500",\
+ "590008.562500, 590008.625000, 590008.750000, 590009.000000, 590009.812500",\
+ "590008.562500, 590008.625000, 590008.750000, 590009.000000, 590009.812500",\
+ "590008.687500, 590008.750000, 590008.875000, 590009.125000, 590009.937500",\
+ "590008.937500, 590009.000000, 590009.125000, 590009.375000, 590010.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\
+ "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\
+ "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\
+ "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\
+ "0.319235, 0.394420, 0.558621, 1.081391, 2.429503");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.625000",\
+ "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.750000",\
+ "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590007.875000",\
+ "590007.125000, 590007.125000, 590007.187500, 590007.437500, 590008.000000",\
+ "590007.500000, 590007.500000, 590007.562500, 590007.812500, 590008.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\
+ "0.268551, 0.328271, 0.458604, 0.872597, 1.937878");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_sys_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "590008.437500, 590008.500000, 590008.625000, 590008.875000, 590009.687500",\
+ "590008.437500, 590008.500000, 590008.625000, 590008.875000, 590009.687500",\
+ "590008.562500, 590008.625000, 590008.750000, 590009.000000, 590009.812500",\
+ "590008.687500, 590008.750000, 590008.875000, 590009.125000, 590009.937500",\
+ "590008.937500, 590009.000000, 590009.125000, 590009.375000, 590010.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\
+ "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\
+ "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\
+ "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\
+ "0.319235, 0.394241, 0.557935, 1.080416, 2.426166");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.625000",\
+ "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.750000",\
+ "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590007.875000",\
+ "590007.125000, 590007.125000, 590007.187500, 590007.437500, 590008.000000",\
+ "590007.375000, 590007.375000, 590007.437500, 590007.687500, 590008.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236");
+ values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\
+ "0.266320, 0.325777, 0.455536, 0.867948, 1.929571");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_sys_o_inv_min*/
+
+} /* end of pin clk_src_sys_o */
+
+pin("clk_src_sys_val_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.090214 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002720 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_sys_val_o;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.393375, 0.428628, 0.510890, 0.784879, 1.641015",\
+ "0.480773, 0.516025, 0.598287, 0.872277, 1.728413",\
+ "0.561620, 0.596872, 0.679134, 0.953123, 1.809259",\
+ "0.699752, 0.735005, 0.817267, 1.091256, 1.947392",\
+ "0.940296, 0.975559, 1.057603, 1.330256, 2.187617");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\
+ "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\
+ "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\
+ "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\
+ "0.090897, 0.157759, 0.313710, 0.838442, 2.477149");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.432455, 0.458343, 0.517176, 0.707295, 1.304954",\
+ "0.519853, 0.545740, 0.604574, 0.794693, 1.392351",\
+ "0.600665, 0.626553, 0.685387, 0.875506, 1.473164",\
+ "0.738675, 0.764563, 0.823397, 1.013516, 1.611174",\
+ "0.958865, 0.984753, 1.043586, 1.233705, 1.831364");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\
+ "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\
+ "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\
+ "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\
+ "0.074157, 0.115650, 0.215819, 0.564523, 1.651598");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.266769, 0.302004, 0.384050, 0.657034, 1.516706",\
+ "0.354958, 0.390193, 0.472239, 0.745222, 1.604895",\
+ "0.442595, 0.477830, 0.559876, 0.832859, 1.692532",\
+ "0.590863, 0.626097, 0.708144, 0.981127, 1.840799",\
+ "0.826177, 0.861412, 0.943458, 1.216442, 2.076114");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\
+ "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\
+ "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\
+ "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\
+ "0.090757, 0.157284, 0.313129, 0.831079, 2.456895");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.303512, 0.329439, 0.388317, 0.578409, 1.176194",\
+ "0.391701, 0.417628, 0.476506, 0.666598, 1.264383",\
+ "0.479338, 0.505265, 0.564143, 0.754235, 1.352020",\
+ "0.627605, 0.653533, 0.712411, 0.902503, 1.500287",\
+ "0.853156, 0.879043, 0.937890, 1.128062, 1.724915");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\
+ "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\
+ "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\
+ "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\
+ "0.072021, 0.113734, 0.214400, 0.561002, 1.650535");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.091331, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.274613, 0.222555, 0.182645, 0.164813, 0.160978",\
+ "0.311604, 0.259547, 0.219637, 0.201805, 0.197970",\
+ "0.350063, 0.298005, 0.258095, 0.240263, 0.236428",\
+ "0.426515, 0.374464, 0.334588, 0.316753, 0.312873",\
+ "0.811131, 0.757315, 0.714144, 0.694969, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.074152, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.319192, 0.236521, 0.161241, 0.120791, 0.094238",\
+ "0.350005, 0.267334, 0.192054, 0.151604, 0.125051",\
+ "0.404336, 0.321669, 0.246404, 0.205976, 0.179465",\
+ "0.493898, 0.411245, 0.336023, 0.295656, 0.269270",\
+ "0.983325, 0.898854, 0.822917, 0.761117, 0.683170");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.090757, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.098980, -0.056266, -0.020568, 0.030300, 0.132735",\
+ "-0.130504, -0.087736, -0.052066, -0.001191, 0.101296",\
+ "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\
+ "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\
+ "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.072021, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.133098, -0.057590, 0.008390, 0.100023, 0.282590",\
+ "-0.157464, -0.082691, -0.016549, 0.075171, 0.257794",\
+ "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\
+ "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\
+ "-0.787774, -0.712937, -0.646782, -0.554947, -0.372013");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_hldr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.091331, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.404032, 0.352558, 0.318430, 0.316711, 0.351792",\
+ "0.438477, 0.387003, 0.352875, 0.351156, 0.386237",\
+ "0.480582, 0.429108, 0.394981, 0.393261, 0.428342",\
+ "0.577835, 0.526352, 0.492184, 0.490390, 0.525306",\
+ "1.061708, 1.010135, 0.975535, 0.972941, 1.006095");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.090757, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.316209, -0.269420, -0.233349, -0.183696, -0.085143",\
+ "-0.350428, -0.303639, -0.267567, -0.217915, -0.119361",\
+ "-0.392769, -0.345980, -0.309909, -0.260256, -0.161702",\
+ "-0.490012, -0.443234, -0.407200, -0.357545, -0.258944",\
+ "-0.973610, -0.926934, -0.891298, -0.841646, -0.742588");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "970010.375000, 970010.437500, 970010.500000, 970010.750000, 970011.625000",\
+ "970010.500000, 970010.562500, 970010.625000, 970010.875000, 970011.750000",\
+ "970010.625000, 970010.687500, 970010.750000, 970011.000000, 970011.875000",\
+ "970010.625000, 970010.687500, 970010.750000, 970011.000000, 970011.875000",\
+ "970011.000000, 970011.062500, 970011.125000, 970011.375000, 970012.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "970010.375000, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\
+ "970010.500000, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\
+ "970010.625000, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\
+ "970010.625000, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\
+ "970011.000000, 970011.000000, 970011.062500, 970011.250000, 970011.875000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_sys_val_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.735494, 0.770750, 0.853002, 1.126914, 1.983374",\
+ "0.823294, 0.858551, 0.940802, 1.214714, 2.071174",\
+ "0.904594, 0.939850, 1.022102, 1.296013, 2.152474",\
+ "0.962747, 0.998003, 1.080255, 1.354167, 2.210627",\
+ "1.271467, 1.306724, 1.388975, 1.662887, 2.519347");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.709749, 0.735637, 0.794488, 0.984673, 1.581583",\
+ "0.797549, 0.823438, 0.882288, 1.072473, 1.669383",\
+ "0.878849, 0.904737, 0.963588, 1.153773, 1.750682",\
+ "0.937002, 0.962891, 1.021741, 1.211926, 1.808836",\
+ "1.245723, 1.271611, 1.330462, 1.520647, 2.117556");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_sys_val_o_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "970007.125000, 970007.187500, 970007.250000, 970007.562500, 970008.375000",\
+ "970007.250000, 970007.312500, 970007.375000, 970007.687500, 970008.500000",\
+ "970007.250000, 970007.312500, 970007.375000, 970007.687500, 970008.500000",\
+ "970007.500000, 970007.562500, 970007.625000, 970007.937500, 970008.750000",\
+ "970007.750000, 970007.812500, 970007.875000, 970008.187500, 970009.000000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "970010.250000, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\
+ "970010.375000, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\
+ "970010.500000, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\
+ "970010.750000, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\
+ "970011.000000, 970011.000000, 970011.062500, 970011.250000, 970011.875000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "380000.500000, 380000.531250, 380000.593750, 380000.875000, 380001.750000",\
+ "380000.593750, 380000.625000, 380000.687500, 380000.968750, 380001.843750",\
+ "380000.656250, 380000.687500, 380000.750000, 380001.031250, 380001.906250",\
+ "380000.812500, 380000.843750, 380000.906250, 380001.187500, 380002.062500",\
+ "380001.031250, 380001.062500, 380001.125000, 380001.406250, 380002.281250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "380001.906250, 380001.937500, 380002.000000, 380002.187500, 380002.781250",\
+ "380002.000000, 380002.031250, 380002.093750, 380002.281250, 380002.875000",\
+ "380002.093750, 380002.125000, 380002.187500, 380002.375000, 380002.968750",\
+ "380002.281250, 380002.312500, 380002.375000, 380002.562500, 380003.156250",\
+ "380002.531250, 380002.562500, 380002.625000, 380002.812500, 380003.406250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "970007.187500, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\
+ "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\
+ "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\
+ "970007.562500, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\
+ "970007.812500, 970007.812500, 970007.875000, 970008.062500, 970008.687500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563923, 1.651340");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "970010.250000, 970010.312500, 970010.375000, 970010.625000, 970011.500000",\
+ "970010.375000, 970010.437500, 970010.500000, 970010.750000, 970011.625000",\
+ "970010.500000, 970010.562500, 970010.625000, 970010.875000, 970011.750000",\
+ "970010.750000, 970010.812500, 970010.875000, 970011.125000, 970012.000000",\
+ "970011.000000, 970011.062500, 970011.125000, 970011.375000, 970012.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\
+ "0.091331, 0.157635, 0.313856, 0.840284, 2.469430");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "380000.531250, 380000.562500, 380000.625000, 380000.812500, 380001.406250",\
+ "380000.625000, 380000.656250, 380000.718750, 380000.906250, 380001.500000",\
+ "380000.687500, 380000.718750, 380000.781250, 380000.968750, 380001.562500",\
+ "380000.843750, 380000.875000, 380000.937500, 380001.125000, 380001.718750",\
+ "380001.062500, 380001.093750, 380001.156250, 380001.343750, 380001.937500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\
+ "0.072027, 0.113736, 0.214396, 0.560990, 1.651196");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "380001.937500, 380001.968750, 380002.062500, 380002.343750, 380003.187500",\
+ "380002.031250, 380002.062500, 380002.156250, 380002.437500, 380003.281250",\
+ "380002.125000, 380002.156250, 380002.250000, 380002.531250, 380003.375000",\
+ "380002.312500, 380002.343750, 380002.437500, 380002.718750, 380003.562500",\
+ "380002.562500, 380002.593750, 380002.687500, 380002.968750, 380003.812500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\
+ "0.090757, 0.157284, 0.313155, 0.830725, 2.460156");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "590008.625000, 590008.687500, 590008.750000, 590009.000000, 590009.875000",\
+ "590008.750000, 590008.812500, 590008.875000, 590009.125000, 590010.000000",\
+ "590008.750000, 590008.812500, 590008.875000, 590009.125000, 590010.000000",\
+ "590008.875000, 590008.937500, 590009.000000, 590009.250000, 590010.125000",\
+ "590009.125000, 590009.187500, 590009.250000, 590009.500000, 590010.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\
+ "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\
+ "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\
+ "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\
+ "0.091331, 0.157635, 0.313861, 0.840307, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "590006.937500, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\
+ "590007.062500, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\
+ "590007.187500, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\
+ "590007.312500, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\
+ "590007.687500, 590007.687500, 590007.750000, 590007.937500, 590008.562500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563930, 1.651340");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "590008.437500, 590008.437500, 590008.562500, 590008.812500, 590009.687500",\
+ "590008.437500, 590008.437500, 590008.562500, 590008.812500, 590009.687500",\
+ "590008.562500, 590008.562500, 590008.687500, 590008.937500, 590009.812500",\
+ "590008.687500, 590008.687500, 590008.812500, 590009.062500, 590009.937500",\
+ "590008.937500, 590008.937500, 590009.062500, 590009.312500, 590010.187500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\
+ "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\
+ "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\
+ "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\
+ "0.090757, 0.157286, 0.312487, 0.829843, 2.465812");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "590006.750000, 590006.812500, 590006.875000, 590007.062500, 590007.625000",\
+ "590006.875000, 590006.937500, 590007.000000, 590007.187500, 590007.750000",\
+ "590007.000000, 590007.062500, 590007.125000, 590007.312500, 590007.875000",\
+ "590007.125000, 590007.187500, 590007.250000, 590007.437500, 590008.000000",\
+ "590007.375000, 590007.437500, 590007.500000, 590007.687500, 590008.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\
+ "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\
+ "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\
+ "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\
+ "0.072111, 0.113800, 0.214396, 0.559011, 1.650020");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "590008.625000, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.750000, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.750000, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.875000, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\
+ "590009.125000, 590009.125000, 590009.187500, 590009.375000, 590010.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\
+ "0.074152, 0.115602, 0.215213, 0.563930, 1.651340");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "590006.875000, 590006.937500, 590007.000000, 590007.312500, 590008.125000",\
+ "590007.000000, 590007.062500, 590007.125000, 590007.437500, 590008.250000",\
+ "590007.125000, 590007.187500, 590007.250000, 590007.562500, 590008.375000",\
+ "590007.250000, 590007.312500, 590007.375000, 590007.687500, 590008.500000",\
+ "590007.625000, 590007.687500, 590007.750000, 590008.062500, 590008.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\
+ "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\
+ "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\
+ "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\
+ "0.091331, 0.157635, 0.313861, 0.840307, 2.469430");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "590008.625000, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.625000, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.750000, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.875000, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\
+ "590009.125000, 590009.125000, 590009.187500, 590009.375000, 590010.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\
+ "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\
+ "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\
+ "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\
+ "0.072111, 0.113800, 0.214396, 0.559011, 1.650020");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "590006.875000, 590006.937500, 590007.000000, 590007.312500, 590008.125000",\
+ "590007.000000, 590007.062500, 590007.125000, 590007.437500, 590008.250000",\
+ "590007.125000, 590007.187500, 590007.250000, 590007.562500, 590008.375000",\
+ "590007.250000, 590007.312500, 590007.375000, 590007.687500, 590008.500000",\
+ "590007.500000, 590007.562500, 590007.625000, 590007.937500, 590008.750000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214");
+ values ( "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\
+ "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\
+ "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\
+ "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\
+ "0.090757, 0.157286, 0.312487, 0.829843, 2.465812");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_inv_min*/
+
+} /* end of pin clk_src_sys_val_o */
+
+pin("clk_src_aon_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 4.852190 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.018084 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_aon_o;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.829798, 0.861406, 1.030187, 1.471304, 2.111221",\
+ "0.918104, 0.949713, 1.118494, 1.559610, 2.199528",\
+ "1.006314, 1.037922, 1.206704, 1.647820, 2.287737",\
+ "1.155623, 1.187232, 1.356013, 1.797129, 2.437046",\
+ "1.394957, 1.426565, 1.595346, 2.036462, 2.676380");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.883488, 0.912350, 1.061245, 1.451119, 2.016701",\
+ "0.970887, 0.999749, 1.148644, 1.538518, 2.104100",\
+ "1.051701, 1.080563, 1.229459, 1.619333, 2.184914",\
+ "1.189711, 1.218573, 1.367469, 1.757343, 2.322925",\
+ "1.410200, 1.439062, 1.587957, 1.977831, 2.543413");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\
+ "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\
+ "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\
+ "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\
+ "0.017866, 0.065807, 0.337647, 1.043323, 2.067033");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_aon_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.829665, 0.861273, 1.030054, 1.471171, 2.111088",\
+ "0.917971, 0.949579, 1.118361, 1.559477, 2.199394",\
+ "1.006180, 1.037788, 1.206569, 1.647686, 2.287603",\
+ "1.155489, 1.187097, 1.355879, 1.796995, 2.436912",\
+ "1.394823, 1.426431, 1.595212, 2.036328, 2.676246");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.882434, 0.911296, 1.060191, 1.450065, 2.015647",\
+ "0.969833, 0.998695, 1.147590, 1.537464, 2.103046",\
+ "1.050646, 1.079508, 1.228404, 1.618278, 2.183859",\
+ "1.188651, 1.217513, 1.366409, 1.756283, 2.321865",\
+ "1.409136, 1.437999, 1.586894, 1.976768, 2.542350");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\
+ "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\
+ "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\
+ "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\
+ "0.017866, 0.065807, 0.337647, 1.043323, 2.067033");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_aon_o_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "970010.562500, 970010.562500, 970010.750000, 970011.187500, 970011.812500",\
+ "970010.687500, 970010.687500, 970010.875000, 970011.312500, 970011.937500",\
+ "970010.812500, 970010.812500, 970011.000000, 970011.437500, 970012.062500",\
+ "970010.812500, 970010.812500, 970011.000000, 970011.437500, 970012.062500",\
+ "970011.187500, 970011.187500, 970011.375000, 970011.812500, 970012.437500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "970010.375000, 970010.375000, 970010.562500, 970010.937500, 970011.500000",\
+ "970010.500000, 970010.500000, 970010.687500, 970011.062500, 970011.625000",\
+ "970010.625000, 970010.625000, 970010.812500, 970011.187500, 970011.750000",\
+ "970010.625000, 970010.625000, 970010.812500, 970011.187500, 970011.750000",\
+ "970011.000000, 970011.000000, 970011.187500, 970011.562500, 970012.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_aon_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.860464, 0.892073, 1.060854, 1.501970, 2.141887",\
+ "0.948265, 0.979873, 1.148654, 1.589771, 2.229688",\
+ "1.029564, 1.061172, 1.229954, 1.671070, 2.310987",\
+ "1.087717, 1.119326, 1.288107, 1.729223, 2.369140",\
+ "1.396438, 1.428046, 1.596828, 2.037944, 2.677861");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.970766, 0.999628, 1.148520, 1.538388, 2.103961",\
+ "1.058640, 1.087502, 1.236394, 1.626262, 2.191835",\
+ "1.152976, 1.181838, 1.330730, 1.720598, 2.286171",\
+ "1.220734, 1.249595, 1.398488, 1.788356, 2.353929",\
+ "1.581432, 1.610294, 1.759186, 2.149055, 2.714628");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_aon_o_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "970007.187500, 970007.187500, 970007.375000, 970007.812500, 970008.437500",\
+ "970007.312500, 970007.312500, 970007.500000, 970007.937500, 970008.562500",\
+ "970007.312500, 970007.312500, 970007.500000, 970007.937500, 970008.562500",\
+ "970007.562500, 970007.562500, 970007.750000, 970008.187500, 970008.812500",\
+ "970007.812500, 970007.812500, 970008.000000, 970008.437500, 970009.062500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "970010.250000, 970010.250000, 970010.437500, 970010.812500, 970011.375000",\
+ "970010.375000, 970010.375000, 970010.562500, 970010.937500, 970011.500000",\
+ "970010.500000, 970010.500000, 970010.687500, 970011.062500, 970011.625000",\
+ "970010.750000, 970010.750000, 970010.937500, 970011.312500, 970011.875000",\
+ "970011.000000, 970011.000000, 970011.187500, 970011.562500, 970012.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_aon_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "380008.531250, 380008.562500, 380008.750000, 380009.187500, 380009.812500",\
+ "380008.625000, 380008.656250, 380008.843750, 380009.281250, 380009.906250",\
+ "380008.687500, 380008.718750, 380008.906250, 380009.343750, 380009.968750",\
+ "380008.843750, 380008.875000, 380009.062500, 380009.500000, 380010.125000",\
+ "380009.062500, 380009.093750, 380009.281250, 380009.718750, 380010.343750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "380007.906250, 380007.906250, 380008.062500, 380008.468750, 380009.031250",\
+ "380008.000000, 380008.000000, 380008.156250, 380008.562500, 380009.125000",\
+ "380008.093750, 380008.093750, 380008.250000, 380008.656250, 380009.218750",\
+ "380008.281250, 380008.281250, 380008.437500, 380008.843750, 380009.406250",\
+ "380008.531250, 380008.531250, 380008.687500, 380009.093750, 380009.656250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_aon_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "970007.437500, 970007.437500, 970007.625000, 970008.000000, 970008.562500",\
+ "970007.562500, 970007.562500, 970007.750000, 970008.125000, 970008.687500",\
+ "970007.562500, 970007.562500, 970007.750000, 970008.125000, 970008.687500",\
+ "970007.812500, 970007.812500, 970008.000000, 970008.375000, 970008.937500",\
+ "970008.062500, 970008.062500, 970008.250000, 970008.625000, 970009.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "970010.437500, 970010.437500, 970010.625000, 970011.062500, 970011.687500",\
+ "970010.562500, 970010.562500, 970010.750000, 970011.187500, 970011.812500",\
+ "970010.687500, 970010.687500, 970010.875000, 970011.312500, 970011.937500",\
+ "970010.937500, 970010.937500, 970011.125000, 970011.562500, 970012.187500",\
+ "970011.187500, 970011.187500, 970011.375000, 970011.812500, 970012.437500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_aon_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "380000.750000, 380000.750000, 380000.906250, 380001.312500, 380001.875000",\
+ "380000.843750, 380000.843750, 380001.000000, 380001.406250, 380001.968750",\
+ "380000.906250, 380000.906250, 380001.062500, 380001.468750, 380002.031250",\
+ "380001.062500, 380001.062500, 380001.218750, 380001.625000, 380002.187500",\
+ "380001.281250, 380001.281250, 380001.437500, 380001.843750, 380002.406250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\
+ "0.017866, 0.065808, 0.337669, 1.043341, 2.067043");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "380002.031250, 380002.062500, 380002.250000, 380002.687500, 380003.312500",\
+ "380002.125000, 380002.156250, 380002.343750, 380002.781250, 380003.406250",\
+ "380002.218750, 380002.250000, 380002.437500, 380002.875000, 380003.500000",\
+ "380002.406250, 380002.437500, 380002.625000, 380003.062500, 380003.687500",\
+ "380002.656250, 380002.687500, 380002.875000, 380003.312500, 380003.937500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\
+ "0.018689, 0.076907, 0.397582, 1.240182, 2.462523");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_aon_o_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "590008.812500, 590008.812500, 590009.000000, 590009.437500, 590010.062500",\
+ "590008.937500, 590008.937500, 590009.125000, 590009.562500, 590010.187500",\
+ "590008.937500, 590008.937500, 590009.125000, 590009.562500, 590010.187500",\
+ "590009.062500, 590009.062500, 590009.250000, 590009.687500, 590010.312500",\
+ "590009.312500, 590009.312500, 590009.500000, 590009.937500, 590010.562500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "590007.187500, 590007.187500, 590007.375000, 590007.750000, 590008.312500",\
+ "590007.312500, 590007.312500, 590007.500000, 590007.875000, 590008.437500",\
+ "590007.437500, 590007.437500, 590007.625000, 590008.000000, 590008.562500",\
+ "590007.562500, 590007.562500, 590007.750000, 590008.125000, 590008.687500",\
+ "590007.937500, 590007.937500, 590008.125000, 590008.500000, 590009.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_aon_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "590008.812500, 590008.812500, 590009.000000, 590009.437500, 590010.062500",\
+ "590008.812500, 590008.812500, 590009.000000, 590009.437500, 590010.062500",\
+ "590008.937500, 590008.937500, 590009.125000, 590009.562500, 590010.187500",\
+ "590009.062500, 590009.062500, 590009.250000, 590009.687500, 590010.312500",\
+ "590009.312500, 590009.312500, 590009.500000, 590009.937500, 590010.562500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\
+ "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\
+ "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\
+ "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\
+ "0.018689, 0.076907, 0.397577, 1.240181, 2.462529");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "590007.187500, 590007.187500, 590007.375000, 590007.750000, 590008.312500",\
+ "590007.312500, 590007.312500, 590007.500000, 590007.875000, 590008.437500",\
+ "590007.437500, 590007.437500, 590007.625000, 590008.000000, 590008.562500",\
+ "590007.562500, 590007.562500, 590007.750000, 590008.125000, 590008.687500",\
+ "590007.812500, 590007.812500, 590008.000000, 590008.375000, 590008.937500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\
+ "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\
+ "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\
+ "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\
+ "0.017866, 0.065808, 0.337663, 1.043336, 2.067040");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_aon_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "590008.625000, 590008.625000, 590008.812500, 590009.187500, 590009.750000",\
+ "590008.750000, 590008.750000, 590008.937500, 590009.312500, 590009.875000",\
+ "590008.750000, 590008.750000, 590008.937500, 590009.312500, 590009.875000",\
+ "590008.875000, 590008.875000, 590009.062500, 590009.437500, 590010.000000",\
+ "590009.125000, 590009.125000, 590009.312500, 590009.687500, 590010.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\
+ "0.017866, 0.065807, 0.337660, 1.043334, 2.067039");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "590006.937500, 590006.937500, 590007.125000, 590007.562500, 590008.187500",\
+ "590007.062500, 590007.062500, 590007.250000, 590007.687500, 590008.312500",\
+ "590007.187500, 590007.187500, 590007.375000, 590007.812500, 590008.437500",\
+ "590007.312500, 590007.312500, 590007.500000, 590007.937500, 590008.562500",\
+ "590007.687500, 590007.687500, 590007.875000, 590008.312500, 590008.937500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\
+ "0.018690, 0.076907, 0.397572, 1.240181, 2.462535");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_aon_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "590008.625000, 590008.625000, 590008.812500, 590009.187500, 590009.750000",\
+ "590008.625000, 590008.625000, 590008.812500, 590009.187500, 590009.750000",\
+ "590008.750000, 590008.750000, 590008.937500, 590009.312500, 590009.875000",\
+ "590008.875000, 590008.875000, 590009.062500, 590009.437500, 590010.000000",\
+ "590009.125000, 590009.125000, 590009.312500, 590009.687500, 590010.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\
+ "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\
+ "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\
+ "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\
+ "0.017866, 0.065808, 0.337663, 1.043336, 2.067040");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "590006.937500, 590006.937500, 590007.125000, 590007.562500, 590008.187500",\
+ "590007.062500, 590007.062500, 590007.250000, 590007.687500, 590008.312500",\
+ "590007.187500, 590007.187500, 590007.375000, 590007.812500, 590008.437500",\
+ "590007.312500, 590007.312500, 590007.500000, 590007.937500, 590008.562500",\
+ "590007.562500, 590007.562500, 590007.750000, 590008.187500, 590008.812500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190");
+ values ( "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\
+ "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\
+ "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\
+ "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\
+ "0.018689, 0.076907, 0.397577, 1.240181, 2.462529");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_aon_o_inv_min*/
+
+} /* end of pin clk_src_aon_o */
+
+pin("clk_src_aon_val_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.090214 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_aon_val_o;
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "970010.375000, 970010.375000, 970010.500000, 970010.750000, 970011.625000",\
+ "970010.500000, 970010.500000, 970010.625000, 970010.875000, 970011.750000",\
+ "970010.625000, 970010.625000, 970010.750000, 970011.000000, 970011.875000",\
+ "970010.625000, 970010.625000, 970010.750000, 970011.000000, 970011.875000",\
+ "970011.000000, 970011.000000, 970011.125000, 970011.375000, 970012.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\
+ "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\
+ "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_aon_val_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.710726, 0.747218, 0.829413, 1.103529, 1.981775",\
+ "0.798527, 0.835019, 0.917213, 1.191329, 2.069575",\
+ "0.879826, 0.916318, 0.998513, 1.272629, 2.150875",\
+ "0.937979, 0.974471, 1.056666, 1.330782, 2.209028",\
+ "1.246700, 1.283192, 1.365386, 1.639502, 2.517748");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.688713, 0.718170, 0.777854, 0.968115, 1.580205",\
+ "0.776513, 0.805970, 0.865655, 1.055915, 1.668005",\
+ "0.857813, 0.887270, 0.946954, 1.137214, 1.749305",\
+ "0.915966, 0.945423, 1.005107, 1.195368, 1.807458",\
+ "1.224687, 1.254144, 1.313828, 1.504088, 2.116179");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_aon_val_o_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "970007.125000, 970007.125000, 970007.250000, 970007.500000, 970008.375000",\
+ "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\
+ "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\
+ "970007.500000, 970007.500000, 970007.625000, 970007.875000, 970008.750000",\
+ "970007.750000, 970007.750000, 970007.875000, 970008.125000, 970009.000000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "970010.187500, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\
+ "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\
+ "970010.687500, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "380000.468750, 380000.500000, 380000.593750, 380000.843750, 380001.750000",\
+ "380000.562500, 380000.593750, 380000.687500, 380000.937500, 380001.843750",\
+ "380000.625000, 380000.656250, 380000.750000, 380001.000000, 380001.906250",\
+ "380000.781250, 380000.812500, 380000.906250, 380001.156250, 380002.062500",\
+ "380001.000000, 380001.031250, 380001.125000, 380001.375000, 380002.281250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "380001.906250, 380001.937500, 380002.000000, 380002.187500, 380002.781250",\
+ "380002.000000, 380002.031250, 380002.093750, 380002.281250, 380002.875000",\
+ "380002.093750, 380002.125000, 380002.187500, 380002.375000, 380002.968750",\
+ "380002.281250, 380002.312500, 380002.375000, 380002.562500, 380003.156250",\
+ "380002.531250, 380002.562500, 380002.625000, 380002.812500, 380003.406250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "970007.187500, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\
+ "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\
+ "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\
+ "970007.562500, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\
+ "970007.812500, 970007.812500, 970007.875000, 970008.062500, 970008.687500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536743, 1.653005");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "970010.250000, 970010.250000, 970010.375000, 970010.625000, 970011.500000",\
+ "970010.375000, 970010.375000, 970010.500000, 970010.750000, 970011.625000",\
+ "970010.500000, 970010.500000, 970010.625000, 970010.875000, 970011.750000",\
+ "970010.750000, 970010.750000, 970010.875000, 970011.125000, 970012.000000",\
+ "970011.000000, 970011.000000, 970011.125000, 970011.375000, 970012.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799035, 2.469430");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "380000.500000, 380000.531250, 380000.593750, 380000.781250, 380001.406250",\
+ "380000.593750, 380000.625000, 380000.687500, 380000.875000, 380001.500000",\
+ "380000.656250, 380000.687500, 380000.750000, 380000.937500, 380001.562500",\
+ "380000.812500, 380000.843750, 380000.906250, 380001.093750, 380001.718750",\
+ "380001.031250, 380001.062500, 380001.125000, 380001.312500, 380001.937500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\
+ "0.046907, 0.088182, 0.186999, 0.533681, 1.651611");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "380001.906250, 380001.968750, 380002.031250, 380002.312500, 380003.187500",\
+ "380002.000000, 380002.062500, 380002.125000, 380002.406250, 380003.281250",\
+ "380002.093750, 380002.156250, 380002.218750, 380002.500000, 380003.375000",\
+ "380002.281250, 380002.343750, 380002.406250, 380002.687500, 380003.562500",\
+ "380002.531250, 380002.593750, 380002.656250, 380002.937500, 380003.812500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\
+ "0.051468, 0.115906, 0.271423, 0.789292, 2.460133");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "590008.625000, 590008.625000, 590008.750000, 590009.000000, 590009.875000",\
+ "590008.750000, 590008.750000, 590008.875000, 590009.125000, 590010.000000",\
+ "590008.750000, 590008.750000, 590008.875000, 590009.125000, 590010.000000",\
+ "590008.875000, 590008.875000, 590009.000000, 590009.250000, 590010.125000",\
+ "590009.125000, 590009.125000, 590009.250000, 590009.500000, 590010.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799058, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "590006.937500, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\
+ "590007.062500, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\
+ "590007.187500, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\
+ "590007.312500, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\
+ "590007.687500, 590007.687500, 590007.750000, 590007.937500, 590008.562500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536750, 1.653005");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "590008.437500, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\
+ "590008.437500, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\
+ "590008.562500, 590008.562500, 590008.625000, 590008.937500, 590009.812500",\
+ "590008.687500, 590008.687500, 590008.750000, 590009.062500, 590009.937500",\
+ "590008.937500, 590008.937500, 590009.000000, 590009.312500, 590010.187500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\
+ "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\
+ "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\
+ "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\
+ "0.051557, 0.115907, 0.271016, 0.788173, 2.465855");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "590006.750000, 590006.750000, 590006.812500, 590007.000000, 590007.625000",\
+ "590006.875000, 590006.875000, 590006.937500, 590007.125000, 590007.750000",\
+ "590007.000000, 590007.000000, 590007.062500, 590007.250000, 590007.875000",\
+ "590007.125000, 590007.125000, 590007.187500, 590007.375000, 590008.000000",\
+ "590007.375000, 590007.375000, 590007.437500, 590007.625000, 590008.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\
+ "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\
+ "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\
+ "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\
+ "0.046941, 0.088258, 0.187000, 0.531185, 1.650439");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\
+ "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\
+ "0.049199, 0.090220, 0.188113, 0.536750, 1.653005");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\
+ "590007.625000, 590007.625000, 590007.750000, 590008.000000, 590008.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\
+ "0.051936, 0.116244, 0.271542, 0.799058, 2.469430");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\
+ "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\
+ "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\
+ "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\
+ "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\
+ "0.046941, 0.088258, 0.187000, 0.531185, 1.650439");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\
+ "590007.500000, 590007.500000, 590007.625000, 590007.875000, 590008.750000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214");
+ values ( "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\
+ "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\
+ "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\
+ "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\
+ "0.051557, 0.115907, 0.271016, 0.788173, 2.465855");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_inv_min*/
+
+} /* end of pin clk_src_aon_val_o */
+
+pin("clk_src_io_en_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002154 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_io_en_i;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\
+ "0.271588, 0.219415, 0.179927, 0.162045, 0.157577",\
+ "0.363033, 0.310027, 0.270334, 0.252385, 0.247965",\
+ "0.507780, 0.454308, 0.413646, 0.395357, 0.391106",\
+ "0.811131, 0.757315, 0.714144, 0.694969, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\
+ "0.324602, 0.241857, 0.166855, 0.126539, 0.100040",\
+ "0.429418, 0.345854, 0.270221, 0.227986, 0.196782",\
+ "0.605833, 0.521783, 0.445878, 0.397956, 0.350944",\
+ "0.983325, 0.898854, 0.822917, 0.761117, 0.674795");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_en_i_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\
+ "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\
+ "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\
+ "-0.373429, -0.330963, -0.299719, -0.251733, -0.152256",\
+ "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\
+ "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\
+ "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\
+ "-0.470591, -0.397956, -0.329423, -0.234665, -0.046227",\
+ "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_en_i_hldr*/
+
+} /* end of pin clk_src_io_en_i */
+
+pin("clk_src_io_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.069236 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.028657 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_io_o;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : falling_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\
+ "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\
+ "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\
+ "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\
+ "1.549102, 1.558939, 1.580409, 1.648733, 2.140488");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\
+ "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\
+ "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\
+ "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\
+ "1.576328, 1.589726, 1.618968, 1.712027, 2.381811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044609, 1.208373, 2.387050");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_o_fedg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : falling_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\
+ "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\
+ "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\
+ "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\
+ "1.548301, 1.558138, 1.579608, 1.647932, 2.139687");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\
+ "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\
+ "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\
+ "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\
+ "1.574098, 1.587497, 1.616739, 1.709798, 2.379581");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044608, 1.208373, 2.387050");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_o_fedg_min*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "1.452656, 1.462494, 1.483963, 1.552287, 2.044042",\
+ "1.532226, 1.542063, 1.563532, 1.631856, 2.123611",\
+ "1.612140, 1.621977, 1.643447, 1.711771, 2.203526",\
+ "1.741866, 1.751703, 1.773172, 1.841496, 2.333251",\
+ "1.941871, 1.951709, 1.973178, 2.041502, 2.533257");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "1.431237, 1.444636, 1.473878, 1.566937, 2.236720",\
+ "1.520409, 1.533808, 1.563050, 1.656109, 2.325892",\
+ "1.611352, 1.624751, 1.653993, 1.747052, 2.416835",\
+ "1.766391, 1.779789, 1.809031, 1.902090, 2.571874",\
+ "2.019272, 2.032671, 2.061913, 2.154972, 2.824755");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044609, 1.208373, 2.387050");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "1.436974, 1.446811, 1.468281, 1.536605, 2.028360",\
+ "1.516723, 1.526561, 1.548030, 1.616354, 2.108109",\
+ "1.592126, 1.601964, 1.623433, 1.691757, 2.183512",\
+ "1.712250, 1.722088, 1.743557, 1.811881, 2.303636",\
+ "1.895420, 1.905257, 1.926727, 1.995051, 2.486806");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "1.423435, 1.436834, 1.466076, 1.559135, 2.228919",\
+ "1.511023, 1.524422, 1.553663, 1.646723, 2.316506",\
+ "1.597821, 1.611220, 1.640462, 1.733521, 2.403305",\
+ "1.747068, 1.760467, 1.789708, 1.882767, 2.552551",\
+ "1.991484, 2.004883, 2.034125, 2.127184, 2.796968");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\
+ "0.969570, 0.993149, 1.044608, 1.208373, 2.387050");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_o_una_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "970011.937500, 970011.937500, 970011.937500, 970012.062500, 970012.500000",\
+ "970012.062500, 970012.062500, 970012.062500, 970012.187500, 970012.625000",\
+ "970012.187500, 970012.187500, 970012.187500, 970012.312500, 970012.750000",\
+ "970012.187500, 970012.187500, 970012.187500, 970012.312500, 970012.750000",\
+ "970012.562500, 970012.562500, 970012.562500, 970012.687500, 970013.125000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "970010.562500, 970010.625000, 970010.625000, 970010.687500, 970011.375000",\
+ "970010.687500, 970010.750000, 970010.750000, 970010.812500, 970011.500000",\
+ "970010.812500, 970010.875000, 970010.875000, 970010.937500, 970011.625000",\
+ "970010.812500, 970010.875000, 970010.875000, 970010.937500, 970011.625000",\
+ "970011.187500, 970011.250000, 970011.250000, 970011.312500, 970012.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_io_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.979131, 0.988972, 1.010450, 1.078799, 1.570735",\
+ "1.066932, 1.076773, 1.098250, 1.166599, 1.658535",\
+ "1.148231, 1.158072, 1.179549, 1.247899, 1.739835",\
+ "1.206384, 1.216226, 1.237703, 1.306052, 1.797988",\
+ "1.515105, 1.524946, 1.546423, 1.614772, 2.106709");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "1.139635, 1.153062, 1.182364, 1.275615, 1.946779",\
+ "1.227509, 1.240935, 1.270237, 1.363488, 2.034653",\
+ "1.321845, 1.335272, 1.364574, 1.457825, 2.128989",\
+ "1.389603, 1.403029, 1.432331, 1.525582, 2.196747",\
+ "1.750301, 1.763728, 1.793030, 1.886281, 2.557446");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_io_o_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "970007.250000, 970007.250000, 970007.312500, 970007.375000, 970007.875000",\
+ "970007.375000, 970007.375000, 970007.437500, 970007.500000, 970008.000000",\
+ "970007.375000, 970007.375000, 970007.437500, 970007.500000, 970008.000000",\
+ "970007.625000, 970007.625000, 970007.687500, 970007.750000, 970008.250000",\
+ "970007.875000, 970007.875000, 970007.937500, 970008.000000, 970008.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "970010.437500, 970010.500000, 970010.500000, 970010.562500, 970011.250000",\
+ "970010.562500, 970010.625000, 970010.625000, 970010.687500, 970011.375000",\
+ "970010.687500, 970010.750000, 970010.750000, 970010.812500, 970011.500000",\
+ "970010.937500, 970011.000000, 970011.000000, 970011.062500, 970011.750000",\
+ "970011.187500, 970011.250000, 970011.250000, 970011.312500, 970012.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_io_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "380001.562500, 380001.593750, 380001.593750, 380001.687500, 380002.156250",\
+ "380001.656250, 380001.687500, 380001.687500, 380001.781250, 380002.250000",\
+ "380001.718750, 380001.750000, 380001.750000, 380001.843750, 380002.312500",\
+ "380001.875000, 380001.906250, 380001.906250, 380002.000000, 380002.468750",\
+ "380002.093750, 380002.125000, 380002.125000, 380002.218750, 380002.687500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "380003.031250, 380003.062500, 380003.093750, 380003.187500, 380003.843750",\
+ "380003.125000, 380003.156250, 380003.187500, 380003.281250, 380003.937500",\
+ "380003.218750, 380003.250000, 380003.281250, 380003.375000, 380004.031250",\
+ "380003.406250, 380003.437500, 380003.468750, 380003.562500, 380004.218750",\
+ "380003.656250, 380003.687500, 380003.718750, 380003.812500, 380004.468750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_io_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "970008.625000, 970008.625000, 970008.625000, 970008.750000, 970009.437500",\
+ "970008.750000, 970008.750000, 970008.750000, 970008.875000, 970009.562500",\
+ "970008.750000, 970008.750000, 970008.750000, 970008.875000, 970009.562500",\
+ "970009.000000, 970009.000000, 970009.000000, 970009.125000, 970009.812500",\
+ "970009.250000, 970009.250000, 970009.250000, 970009.375000, 970010.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390203");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "970011.812500, 970011.812500, 970011.812500, 970011.937500, 970012.375000",\
+ "970011.937500, 970011.937500, 970011.937500, 970012.062500, 970012.500000",\
+ "970012.062500, 970012.062500, 970012.062500, 970012.187500, 970012.625000",\
+ "970012.312500, 970012.312500, 970012.312500, 970012.437500, 970012.875000",\
+ "970012.562500, 970012.562500, 970012.562500, 970012.687500, 970013.125000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_io_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "380000.875000, 380000.906250, 380000.937500, 380001.031250, 380001.687500",\
+ "380000.968750, 380001.000000, 380001.031250, 380001.125000, 380001.781250",\
+ "380001.031250, 380001.062500, 380001.093750, 380001.187500, 380001.843750",\
+ "380001.187500, 380001.218750, 380001.250000, 380001.343750, 380002.000000",\
+ "380001.406250, 380001.437500, 380001.468750, 380001.562500, 380002.218750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\
+ "0.965198, 0.988888, 1.040589, 1.205123, 2.387050");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "380002.156250, 380002.187500, 380002.187500, 380002.281250, 380002.750000",\
+ "380002.250000, 380002.281250, 380002.281250, 380002.375000, 380002.843750",\
+ "380002.343750, 380002.375000, 380002.375000, 380002.468750, 380002.937500",\
+ "380002.531250, 380002.562500, 380002.562500, 380002.656250, 380003.125000",\
+ "380002.781250, 380002.812500, 380002.812500, 380002.906250, 380003.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_io_o_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "590010.187500, 590010.187500, 590010.187500, 590010.312500, 590010.750000",\
+ "590010.312500, 590010.312500, 590010.312500, 590010.437500, 590010.875000",\
+ "590010.312500, 590010.312500, 590010.312500, 590010.437500, 590010.875000",\
+ "590010.437500, 590010.437500, 590010.437500, 590010.562500, 590011.000000",\
+ "590010.687500, 590010.687500, 590010.687500, 590010.812500, 590011.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "590008.375000, 590008.375000, 590008.375000, 590008.500000, 590009.187500",\
+ "590008.500000, 590008.500000, 590008.500000, 590008.625000, 590009.312500",\
+ "590008.625000, 590008.625000, 590008.625000, 590008.750000, 590009.437500",\
+ "590008.750000, 590008.750000, 590008.750000, 590008.875000, 590009.562500",\
+ "590009.125000, 590009.125000, 590009.125000, 590009.250000, 590009.937500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390202");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_io_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "590008.875000, 590008.875000, 590008.937500, 590009.000000, 590009.500000",\
+ "590008.875000, 590008.875000, 590008.937500, 590009.000000, 590009.500000",\
+ "590009.000000, 590009.000000, 590009.062500, 590009.125000, 590009.625000",\
+ "590009.125000, 590009.125000, 590009.187500, 590009.250000, 590009.750000",\
+ "590009.375000, 590009.375000, 590009.437500, 590009.500000, 590010.000000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "590007.250000, 590007.250000, 590007.312500, 590007.375000, 590008.062500",\
+ "590007.375000, 590007.375000, 590007.437500, 590007.500000, 590008.187500",\
+ "590007.500000, 590007.500000, 590007.562500, 590007.625000, 590008.312500",\
+ "590007.625000, 590007.625000, 590007.687500, 590007.750000, 590008.437500",\
+ "590007.875000, 590007.875000, 590007.937500, 590008.000000, 590008.687500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\
+ "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\
+ "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\
+ "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\
+ "0.965982, 0.989673, 1.041377, 1.205920, 2.387050");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_io_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "590008.812500, 590008.875000, 590008.875000, 590008.937500, 590009.625000",\
+ "590008.937500, 590009.000000, 590009.000000, 590009.062500, 590009.750000",\
+ "590008.937500, 590009.000000, 590009.000000, 590009.062500, 590009.750000",\
+ "590009.062500, 590009.125000, 590009.125000, 590009.187500, 590009.875000",\
+ "590009.312500, 590009.375000, 590009.375000, 590009.437500, 590010.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\
+ "0.967112, 0.990771, 1.042405, 1.206725, 2.390202");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "590007.000000, 590007.000000, 590007.062500, 590007.125000, 590007.625000",\
+ "590007.125000, 590007.125000, 590007.187500, 590007.250000, 590007.750000",\
+ "590007.250000, 590007.250000, 590007.312500, 590007.375000, 590007.875000",\
+ "590007.375000, 590007.375000, 590007.437500, 590007.500000, 590008.000000",\
+ "590007.750000, 590007.750000, 590007.812500, 590007.875000, 590008.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\
+ "0.813271, 0.831978, 0.872805, 1.002733, 1.937878");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_io_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "590008.812500, 590008.875000, 590008.875000, 590008.937500, 590009.625000",\
+ "590008.812500, 590008.875000, 590008.875000, 590008.937500, 590009.625000",\
+ "590008.937500, 590009.000000, 590009.000000, 590009.062500, 590009.750000",\
+ "590009.062500, 590009.125000, 590009.125000, 590009.187500, 590009.875000",\
+ "590009.312500, 590009.375000, 590009.375000, 590009.437500, 590010.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\
+ "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\
+ "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\
+ "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\
+ "0.965982, 0.989673, 1.041377, 1.205920, 2.387050");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "590007.000000, 590007.000000, 590007.062500, 590007.125000, 590007.625000",\
+ "590007.125000, 590007.125000, 590007.187500, 590007.250000, 590007.750000",\
+ "590007.250000, 590007.250000, 590007.312500, 590007.375000, 590007.875000",\
+ "590007.375000, 590007.375000, 590007.437500, 590007.500000, 590008.000000",\
+ "590007.625000, 590007.625000, 590007.687500, 590007.750000, 590008.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236");
+ values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\
+ "0.808825, 0.827468, 0.868155, 0.997637, 1.929571");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_io_o_inv_min*/
+
+} /* end of pin clk_src_io_o */
+
+pin("clk_src_io_val_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.090214 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_io_val_o;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.349435, 0.390046, 0.472189, 0.746558, 1.641427",\
+ "0.436833, 0.477444, 0.559587, 0.833956, 1.728824",\
+ "0.517679, 0.558291, 0.640433, 0.914803, 1.809671",\
+ "0.655812, 0.696423, 0.778566, 1.052935, 1.947804",\
+ "0.895822, 0.936589, 1.018755, 1.291518, 2.187617");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\
+ "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\
+ "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\
+ "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\
+ "0.023045, 0.083902, 0.239677, 0.764756, 2.477069");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.392641, 0.430353, 0.490673, 0.680876, 1.305538",\
+ "0.480039, 0.517751, 0.578071, 0.768273, 1.392936",\
+ "0.560851, 0.598563, 0.658884, 0.849086, 1.473748",\
+ "0.698861, 0.736574, 0.796894, 0.987096, 1.611758",\
+ "0.919051, 0.956763, 1.017083, 1.207286, 1.831948");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\
+ "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\
+ "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\
+ "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\
+ "0.028953, 0.070788, 0.167469, 0.516472, 1.652650");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_val_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.222488, 0.262832, 0.344930, 0.617962, 1.516487",\
+ "0.310677, 0.351020, 0.433119, 0.706150, 1.604676",\
+ "0.398314, 0.438657, 0.520756, 0.793787, 1.692313",\
+ "0.546582, 0.586925, 0.669023, 0.942055, 1.840581",\
+ "0.781897, 0.822240, 0.904338, 1.177370, 2.075895");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\
+ "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\
+ "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\
+ "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\
+ "0.021529, 0.083764, 0.238778, 0.757629, 2.456834");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.263406, 0.301157, 0.361570, 0.551735, 1.176520",\
+ "0.351595, 0.389345, 0.449758, 0.639924, 1.264709",\
+ "0.439232, 0.476982, 0.537395, 0.727561, 1.352346",\
+ "0.587500, 0.625250, 0.685663, 0.875828, 1.500613",\
+ "0.814247, 0.851409, 0.911729, 1.102035, 1.725865");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\
+ "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\
+ "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\
+ "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\
+ "0.025912, 0.068635, 0.165828, 0.512808, 1.651582");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_val_o_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\
+ "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\
+ "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\
+ "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\
+ "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_io_val_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.691562, 0.732168, 0.814319, 1.088582, 1.983787",\
+ "0.779362, 0.819968, 0.902120, 1.176383, 2.071587",\
+ "0.860662, 0.901268, 0.983419, 1.257682, 2.152886",\
+ "0.918815, 0.959421, 1.041572, 1.315835, 2.211040",\
+ "1.227535, 1.268142, 1.350293, 1.624556, 2.519760");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.670852, 0.708006, 0.768329, 0.958648, 1.582536",\
+ "0.758652, 0.795807, 0.856129, 1.046448, 1.670336",\
+ "0.839952, 0.877106, 0.937428, 1.127748, 1.751636",\
+ "0.898105, 0.935259, 0.995582, 1.185901, 1.809789",\
+ "1.206825, 1.243980, 1.304302, 1.494621, 2.118509");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_io_val_o_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970007.125000, 970007.125000, 970007.250000, 970007.500000, 970008.375000",\
+ "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\
+ "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\
+ "970007.500000, 970007.500000, 970007.625000, 970007.875000, 970008.750000",\
+ "970007.750000, 970007.750000, 970007.875000, 970008.125000, 970009.000000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970010.187500, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\
+ "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\
+ "970010.687500, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "380000.437500, 380000.500000, 380000.562500, 380000.843750, 380001.750000",\
+ "380000.531250, 380000.593750, 380000.656250, 380000.937500, 380001.843750",\
+ "380000.593750, 380000.656250, 380000.718750, 380001.000000, 380001.906250",\
+ "380000.750000, 380000.812500, 380000.875000, 380001.156250, 380002.062500",\
+ "380000.968750, 380001.031250, 380001.093750, 380001.375000, 380002.281250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "380001.875000, 380001.906250, 380001.968750, 380002.156250, 380002.781250",\
+ "380001.968750, 380002.000000, 380002.062500, 380002.250000, 380002.875000",\
+ "380002.062500, 380002.093750, 380002.156250, 380002.343750, 380002.968750",\
+ "380002.250000, 380002.281250, 380002.343750, 380002.531250, 380003.156250",\
+ "380002.500000, 380002.531250, 380002.593750, 380002.781250, 380003.406250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970007.125000, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\
+ "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\
+ "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\
+ "970007.500000, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\
+ "970007.750000, 970007.812500, 970007.875000, 970008.062500, 970008.687500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515896, 1.652424");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970010.187500, 970010.250000, 970010.312500, 970010.625000, 970011.500000",\
+ "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\
+ "970010.687500, 970010.750000, 970010.812500, 970011.125000, 970012.000000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\
+ "0.022870, 0.084359, 0.238855, 0.766786, 2.469430");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "380000.500000, 380000.531250, 380000.593750, 380000.781250, 380001.406250",\
+ "380000.593750, 380000.625000, 380000.687500, 380000.875000, 380001.500000",\
+ "380000.656250, 380000.687500, 380000.750000, 380000.937500, 380001.562500",\
+ "380000.812500, 380000.843750, 380000.906250, 380001.093750, 380001.718750",\
+ "380001.031250, 380001.062500, 380001.125000, 380001.312500, 380001.937500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\
+ "0.025902, 0.068641, 0.165825, 0.512797, 1.652262");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "380001.906250, 380001.937500, 380002.031250, 380002.281250, 380003.187500",\
+ "380002.000000, 380002.031250, 380002.125000, 380002.375000, 380003.281250",\
+ "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\
+ "380002.281250, 380002.312500, 380002.406250, 380002.656250, 380003.562500",\
+ "380002.531250, 380002.562500, 380002.656250, 380002.906250, 380003.812500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\
+ "0.021561, 0.083764, 0.238778, 0.757109, 2.460111");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590008.562500, 590008.625000, 590008.687500, 590009.000000, 590009.875000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\
+ "590008.812500, 590008.875000, 590008.937500, 590009.250000, 590010.125000",\
+ "590009.062500, 590009.125000, 590009.187500, 590009.500000, 590010.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\
+ "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\
+ "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\
+ "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\
+ "0.022871, 0.084359, 0.238855, 0.766810, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590006.875000, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\
+ "590007.000000, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\
+ "590007.125000, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\
+ "590007.250000, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\
+ "590007.625000, 590007.687500, 590007.750000, 590007.937500, 590008.562500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515903, 1.652424");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\
+ "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\
+ "590008.500000, 590008.562500, 590008.625000, 590008.937500, 590009.812500",\
+ "590008.625000, 590008.687500, 590008.750000, 590009.062500, 590009.937500",\
+ "590008.875000, 590008.937500, 590009.000000, 590009.312500, 590010.187500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\
+ "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\
+ "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\
+ "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\
+ "0.022032, 0.083764, 0.238625, 0.755849, 2.465788");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590006.750000, 590006.750000, 590006.812500, 590007.000000, 590007.625000",\
+ "590006.875000, 590006.875000, 590006.937500, 590007.125000, 590007.750000",\
+ "590007.000000, 590007.000000, 590007.062500, 590007.250000, 590007.875000",\
+ "590007.125000, 590007.125000, 590007.187500, 590007.375000, 590008.000000",\
+ "590007.375000, 590007.375000, 590007.437500, 590007.625000, 590008.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\
+ "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\
+ "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\
+ "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\
+ "0.026015, 0.068726, 0.165865, 0.510718, 1.651078");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\
+ "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\
+ "0.028495, 0.070786, 0.167370, 0.515903, 1.652424");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\
+ "590007.625000, 590007.625000, 590007.750000, 590008.000000, 590008.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\
+ "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\
+ "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\
+ "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\
+ "0.022871, 0.084359, 0.238855, 0.766810, 2.469430");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\
+ "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\
+ "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\
+ "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\
+ "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\
+ "0.026015, 0.068726, 0.165865, 0.510718, 1.651078");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\
+ "590007.500000, 590007.500000, 590007.625000, 590007.875000, 590008.750000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\
+ "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\
+ "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\
+ "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\
+ "0.022032, 0.083764, 0.238625, 0.755849, 2.465788");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_inv_min*/
+
+} /* end of pin clk_src_io_val_o */
+bus ( clk_src_io_48m_o ) {
+
+ bus_type : BUS4_type6 ;
+ direction : output ;
+
+pin("clk_src_io_48m_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_io_48m_o[3];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\
+ "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\
+ "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\
+ "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.016716, 0.317340, 0.625771, 1.239746, 2.466601");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\
+ "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\
+ "0.034639, 0.196727, 0.379890, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\
+ "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\
+ "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\
+ "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\
+ "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\
+ "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\
+ "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.016716, 0.317340, 0.625211, 1.239292, 2.466325");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\
+ "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\
+ "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\
+ "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\
+ "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\
+ "0.034639, 0.196727, 0.378735, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_src_io_o_clk_src_io_48m_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\
+ "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\
+ "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\
+ "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\
+ "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\
+ "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\
+ "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_src_io_o_clk_src_io_48m_o[3]_redg_min*/
+
+} /* end of pin clk_src_io_48m_o[3] */
+
+pin("clk_src_io_48m_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_io_48m_o[2];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\
+ "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\
+ "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\
+ "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\
+ "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\
+ "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\
+ "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\
+ "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\
+ "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\
+ "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.041734, 0.154598, 0.389479, 0.764390, 1.515348");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\
+ "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\
+ "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\
+ "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\
+ "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\
+ "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\
+ "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\
+ "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\
+ "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\
+ "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\
+ "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\
+ "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\
+ "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\
+ "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\
+ "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\
+ "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\
+ "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\
+ "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\
+ "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.041734, 0.154598, 0.389568, 0.764056, 1.513362");
+ }
+
+ } /* end of arc clk_src_io_o_clk_src_io_48m_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\
+ "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\
+ "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\
+ "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\
+ "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\
+ "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\
+ "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_src_io_o_clk_src_io_48m_o[2]_redg_min*/
+
+} /* end of pin clk_src_io_48m_o[2] */
+
+pin("clk_src_io_48m_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_io_48m_o[1];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\
+ "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\
+ "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\
+ "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\
+ "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\
+ "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\
+ "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\
+ "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\
+ "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\
+ "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.041734, 0.154598, 0.389479, 0.764390, 1.515348");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\
+ "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\
+ "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\
+ "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\
+ "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\
+ "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\
+ "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\
+ "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\
+ "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\
+ "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\
+ "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\
+ "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\
+ "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\
+ "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\
+ "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\
+ "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\
+ "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\
+ "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\
+ "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.041734, 0.154598, 0.389568, 0.764056, 1.513362");
+ }
+
+ } /* end of arc clk_src_io_o_clk_src_io_48m_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\
+ "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\
+ "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\
+ "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\
+ "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\
+ "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\
+ "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_src_io_o_clk_src_io_48m_o[1]_redg_min*/
+
+} /* end of pin clk_src_io_48m_o[1] */
+
+pin("clk_src_io_48m_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_io_48m_o[0];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\
+ "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\
+ "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\
+ "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.016716, 0.317340, 0.625771, 1.239746, 2.466601");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\
+ "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\
+ "0.034639, 0.196727, 0.379890, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\
+ "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\
+ "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\
+ "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\
+ "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\
+ "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\
+ "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.016716, 0.317340, 0.625211, 1.239292, 2.466325");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\
+ "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\
+ "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\
+ "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\
+ "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\
+ "0.034639, 0.196727, 0.378735, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_src_io_o_clk_src_io_48m_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\
+ "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\
+ "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\
+ "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\
+ "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\
+ "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\
+ "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_src_io_o_clk_src_io_48m_o[0]_redg_min*/
+
+} /* end of pin clk_src_io_48m_o[0] */
+} /* end of bus clk_src_io_48m_o */
+
+pin("usb_ref_pulse_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000498 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_ref_pulse_i;
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.601598, 0.562432, 0.511802, 0.512897, 0.526214",\
+ "0.685611, 0.646445, 0.595815, 0.596911, 0.610227",\
+ "0.776643, 0.737477, 0.686847, 0.687943, 0.701259",\
+ "0.941188, 0.902022, 0.851392, 0.852488, 0.865804",\
+ "1.218007, 1.178841, 1.128211, 1.129307, 1.142623");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.502275, 0.444594, 0.389492, 0.390588, 0.403904",\
+ "0.590200, 0.532519, 0.477417, 0.478513, 0.491829",\
+ "0.690598, 0.632917, 0.577816, 0.578911, 0.592227",\
+ "0.875082, 0.817401, 0.762299, 0.763395, 0.776711",\
+ "1.192023, 1.134342, 1.079240, 1.080336, 1.093652");
+ }
+
+ } /* end of arc clk_ast_usb_i_usb_ref_pulse_i_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.289933, -0.256850, -0.198215, -0.184587, -0.018969",\
+ "-0.373947, -0.340864, -0.282229, -0.268602, -0.102983",\
+ "-0.464983, -0.431900, -0.373265, -0.359637, -0.194019",\
+ "-0.629535, -0.596452, -0.537817, -0.524189, -0.358571",\
+ "-0.906192, -0.873109, -0.814474, -0.800846, -0.635228");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.244346, -0.193347, -0.096886, -0.078739, 0.141805",\
+ "-0.332296, -0.281297, -0.184836, -0.166688, 0.053856",\
+ "-0.432681, -0.381682, -0.285221, -0.267073, -0.046529",\
+ "-0.616949, -0.565951, -0.469489, -0.451342, -0.230798",\
+ "-0.933995, -0.882996, -0.786535, -0.768387, -0.547843");
+ }
+
+ } /* end of arc clk_ast_usb_i_usb_ref_pulse_i_hldr*/
+
+} /* end of pin usb_ref_pulse_i */
+
+pin("usb_ref_val_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000622 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_ref_val_i;
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.572947, 0.533781, 0.483152, 0.484247, 0.497563",\
+ "0.655514, 0.616348, 0.565718, 0.566814, 0.580130",\
+ "0.734317, 0.695151, 0.644522, 0.645617, 0.658933",\
+ "0.870061, 0.830896, 0.780266, 0.781361, 0.794677",\
+ "1.084318, 1.045152, 0.994522, 0.995618, 1.008934");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.471556, 0.413875, 0.358773, 0.359869, 0.373185",\
+ "0.557541, 0.499860, 0.444758, 0.445854, 0.459170",\
+ "0.648123, 0.590443, 0.535341, 0.536436, 0.549753",\
+ "0.811397, 0.753716, 0.698614, 0.699710, 0.713026",\
+ "1.086303, 1.028622, 0.973521, 0.974616, 0.987932");
+ }
+
+ } /* end of arc clk_ast_usb_i_usb_ref_val_i_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.261299, -0.228217, -0.169581, -0.155962, 0.009554",\
+ "-0.343866, -0.310783, -0.252148, -0.238528, -0.073013",\
+ "-0.422669, -0.389587, -0.330951, -0.317332, -0.151816",\
+ "-0.558414, -0.525331, -0.466695, -0.453076, -0.287561",\
+ "-0.772670, -0.739587, -0.680952, -0.667332, -0.501817");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.213704, -0.162701, -0.066223, -0.048077, 0.172450",\
+ "-0.299689, -0.248686, -0.152209, -0.134063, 0.086465",\
+ "-0.390272, -0.339269, -0.242791, -0.224645, -0.004118",\
+ "-0.553545, -0.502542, -0.406065, -0.387919, -0.167392",\
+ "-0.828451, -0.777448, -0.680971, -0.662825, -0.442298");
+ }
+
+ } /* end of arc clk_ast_usb_i_usb_ref_val_i_hldr*/
+
+} /* end of pin usb_ref_val_i */
+
+pin("clk_src_usb_en_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001677 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_usb_en_i;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\
+ "0.271588, 0.219415, 0.179927, 0.162045, 0.157577",\
+ "0.363033, 0.310027, 0.270334, 0.252385, 0.247965",\
+ "0.507780, 0.454308, 0.413646, 0.395357, 0.391106",\
+ "0.811131, 0.757315, 0.714144, 0.694969, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\
+ "0.324602, 0.241857, 0.166855, 0.126539, 0.100040",\
+ "0.429418, 0.345854, 0.270221, 0.227986, 0.196782",\
+ "0.605833, 0.521783, 0.445878, 0.397956, 0.350944",\
+ "0.983325, 0.898854, 0.822917, 0.761117, 0.674795");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_en_i_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\
+ "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\
+ "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\
+ "-0.373429, -0.330963, -0.299719, -0.251733, -0.152256",\
+ "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\
+ "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\
+ "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\
+ "-0.470591, -0.397956, -0.329423, -0.234665, -0.046227",\
+ "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_en_i_hldr*/
+
+} /* end of pin clk_src_usb_en_i */
+
+pin("clk_src_usb_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.069236 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_usb_o;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : falling_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\
+ "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\
+ "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\
+ "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\
+ "1.737872, 1.770095, 1.839437, 2.057034, 2.749000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\
+ "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\
+ "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\
+ "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\
+ "1.568604, 1.612346, 1.706142, 2.005007, 2.947481");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_o_fedg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : falling_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\
+ "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\
+ "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\
+ "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\
+ "1.093582, 1.125805, 1.195148, 1.412745, 2.104710");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\
+ "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\
+ "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\
+ "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\
+ "1.010551, 1.054292, 1.148088, 1.446953, 2.389427");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_o_fedg_min*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.101180, 1.133403, 1.202745, 1.420342, 2.112307",\
+ "1.189325, 1.221548, 1.290891, 1.508488, 2.200453",\
+ "1.285347, 1.317570, 1.386912, 1.604509, 2.296474",\
+ "1.453311, 1.485534, 1.554876, 1.772473, 2.464438",\
+ "1.727352, 1.759575, 1.828917, 2.046515, 2.738480");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.029003, 1.072744, 1.166540, 1.465405, 2.407880",\
+ "1.116853, 1.160595, 1.254391, 1.553256, 2.495730",\
+ "1.198296, 1.242037, 1.335833, 1.634698, 2.577173",\
+ "1.337780, 1.381521, 1.475317, 1.774182, 2.716657",\
+ "1.565882, 1.609623, 1.703419, 2.002285, 2.944759");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.100277, 1.132500, 1.201842, 1.419439, 2.111404",\
+ "1.188403, 1.220626, 1.289968, 1.507565, 2.199530",\
+ "1.284444, 1.316668, 1.386010, 1.603607, 2.295572",\
+ "1.452407, 1.484630, 1.553972, 1.771569, 2.463535",\
+ "1.726368, 1.758591, 1.827933, 2.045531, 2.737496");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.026546, 1.070287, 1.164084, 1.462948, 2.405423",\
+ "1.114365, 1.158106, 1.251902, 1.550767, 2.493242",\
+ "1.195575, 1.239316, 1.333112, 1.631977, 2.574452",\
+ "1.335306, 1.379047, 1.472843, 1.771708, 2.714183",\
+ "1.563376, 1.607117, 1.700913, 1.999778, 2.942253");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_o_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.641426, 1.673649, 1.742991, 1.960589, 2.652554",\
+ "1.720995, 1.753218, 1.822561, 2.040158, 2.732123",\
+ "1.800790, 1.833013, 1.902355, 2.119953, 2.811918",\
+ "1.930632, 1.962856, 2.032198, 2.249795, 2.941760",\
+ "2.130731, 2.162954, 2.232296, 2.449894, 3.141859");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017599, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.423514, 1.467255, 1.561051, 1.859916, 2.802391",\
+ "1.512686, 1.556427, 1.650223, 1.949089, 2.891563",\
+ "1.603640, 1.647381, 1.741178, 2.040043, 2.982517",\
+ "1.758735, 1.802476, 1.896272, 2.195137, 3.137612",\
+ "2.011581, 2.055323, 2.149119, 2.447984, 3.390458");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.625646, 1.657869, 1.727212, 1.944809, 2.636774",\
+ "1.705396, 1.737619, 1.806961, 2.024558, 2.716523",\
+ "1.780640, 1.812864, 1.882206, 2.099803, 2.791768",\
+ "1.900872, 1.933095, 2.002438, 2.220035, 2.912000",\
+ "2.084163, 2.116387, 2.185729, 2.403326, 3.095291");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "1.415430, 1.459171, 1.552967, 1.851832, 2.794307",\
+ "1.503017, 1.546759, 1.640555, 1.939419, 2.881894",\
+ "1.589827, 1.633568, 1.727364, 2.026229, 2.968703",\
+ "1.739106, 1.782847, 1.876643, 2.175508, 3.117983",\
+ "1.983528, 2.027269, 2.121065, 2.419930, 3.362405");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\
+ "0.020388, 0.096008, 0.262833, 0.786379, 2.444935");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_o_una_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "970012.125000, 970012.187500, 970012.250000, 970012.437500, 970013.125000",\
+ "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.250000",\
+ "970012.375000, 970012.437500, 970012.500000, 970012.687500, 970013.375000",\
+ "970012.375000, 970012.437500, 970012.500000, 970012.687500, 970013.375000",\
+ "970012.750000, 970012.812500, 970012.875000, 970013.062500, 970013.750000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "970010.062500, 970010.062500, 970010.187500, 970010.500000, 970011.437500",\
+ "970010.187500, 970010.187500, 970010.312500, 970010.625000, 970011.562500",\
+ "970010.312500, 970010.312500, 970010.437500, 970010.750000, 970011.687500",\
+ "970010.312500, 970010.312500, 970010.437500, 970010.750000, 970011.687500",\
+ "970010.687500, 970010.687500, 970010.812500, 970011.125000, 970012.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_usb_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.559788, 0.592011, 0.660516, 0.878515, 1.570735",\
+ "0.647589, 0.679811, 0.748316, 0.966316, 1.658535",\
+ "0.728888, 0.761111, 0.829615, 1.047615, 1.739835",\
+ "0.787041, 0.819264, 0.887769, 1.105768, 1.797988",\
+ "1.095762, 1.127984, 1.196489, 1.414489, 2.106709");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.600873, 0.644670, 0.738286, 1.035322, 1.979740",\
+ "0.688747, 0.732544, 0.826160, 1.123196, 2.067614",\
+ "0.783083, 0.826880, 0.920496, 1.217532, 2.161950",\
+ "0.850841, 0.894638, 0.988254, 1.285290, 2.229708",\
+ "1.211540, 1.255336, 1.348952, 1.645988, 2.590406");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_usb_o_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "970006.875000, 970006.875000, 970006.937500, 970007.187500, 970007.875000",\
+ "970007.000000, 970007.000000, 970007.062500, 970007.312500, 970008.000000",\
+ "970007.000000, 970007.000000, 970007.062500, 970007.312500, 970008.000000",\
+ "970007.250000, 970007.250000, 970007.312500, 970007.562500, 970008.250000",\
+ "970007.500000, 970007.500000, 970007.562500, 970007.812500, 970008.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "970009.937500, 970009.937500, 970010.062500, 970010.375000, 970011.312500",\
+ "970010.062500, 970010.062500, 970010.187500, 970010.500000, 970011.437500",\
+ "970010.187500, 970010.187500, 970010.312500, 970010.625000, 970011.562500",\
+ "970010.437500, 970010.437500, 970010.562500, 970010.875000, 970011.812500",\
+ "970010.687500, 970010.687500, 970010.812500, 970011.125000, 970012.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_usb_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "380001.781250, 380001.812500, 380001.875000, 380002.093750, 380002.781250",\
+ "380001.875000, 380001.906250, 380001.968750, 380002.187500, 380002.875000",\
+ "380001.937500, 380001.968750, 380002.031250, 380002.250000, 380002.937500",\
+ "380002.093750, 380002.125000, 380002.187500, 380002.406250, 380003.093750",\
+ "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.312500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "380003.031250, 380003.062500, 380003.156250, 380003.468750, 380004.406250",\
+ "380003.125000, 380003.156250, 380003.250000, 380003.562500, 380004.500000",\
+ "380003.218750, 380003.250000, 380003.343750, 380003.656250, 380004.593750",\
+ "380003.406250, 380003.437500, 380003.531250, 380003.843750, 380004.781250",\
+ "380003.656250, 380003.687500, 380003.781250, 380004.093750, 380005.031250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_usb_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "970008.625000, 970008.687500, 970008.750000, 970009.062500, 970010.000000",\
+ "970008.750000, 970008.812500, 970008.875000, 970009.187500, 970010.125000",\
+ "970008.750000, 970008.812500, 970008.875000, 970009.187500, 970010.125000",\
+ "970009.000000, 970009.062500, 970009.125000, 970009.437500, 970010.375000",\
+ "970009.250000, 970009.312500, 970009.375000, 970009.687500, 970010.625000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260986, 0.783299, 2.448362");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "970012.000000, 970012.062500, 970012.125000, 970012.312500, 970013.000000",\
+ "970012.125000, 970012.187500, 970012.250000, 970012.437500, 970013.125000",\
+ "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.250000",\
+ "970012.500000, 970012.562500, 970012.625000, 970012.812500, 970013.500000",\
+ "970012.750000, 970012.812500, 970012.875000, 970013.062500, 970013.750000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\
+ "0.042128, 0.086864, 0.207230, 0.622005, 1.937878");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_usb_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "380000.343750, 380000.375000, 380000.468750, 380000.781250, 380001.718750",\
+ "380000.437500, 380000.468750, 380000.562500, 380000.875000, 380001.812500",\
+ "380000.500000, 380000.531250, 380000.625000, 380000.937500, 380001.875000",\
+ "380000.656250, 380000.687500, 380000.781250, 380001.093750, 380002.031250",\
+ "380000.875000, 380000.906250, 380001.000000, 380001.312500, 380002.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\
+ "0.020039, 0.095921, 0.259491, 0.781146, 2.444935");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "380001.750000, 380001.781250, 380001.843750, 380002.062500, 380002.750000",\
+ "380001.843750, 380001.875000, 380001.937500, 380002.156250, 380002.843750",\
+ "380001.937500, 380001.968750, 380002.031250, 380002.250000, 380002.937500",\
+ "380002.125000, 380002.156250, 380002.218750, 380002.437500, 380003.125000",\
+ "380002.375000, 380002.406250, 380002.468750, 380002.687500, 380003.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_usb_o_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "590010.375000, 590010.437500, 590010.500000, 590010.687500, 590011.375000",\
+ "590010.500000, 590010.562500, 590010.625000, 590010.812500, 590011.500000",\
+ "590010.500000, 590010.562500, 590010.625000, 590010.812500, 590011.500000",\
+ "590010.625000, 590010.687500, 590010.750000, 590010.937500, 590011.625000",\
+ "590010.875000, 590010.937500, 590011.000000, 590011.187500, 590011.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\
+ "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\
+ "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\
+ "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\
+ "0.042077, 0.086820, 0.207230, 0.622005, 1.937878");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.750000",\
+ "590008.500000, 590008.562500, 590008.625000, 590008.937500, 590009.875000",\
+ "590008.625000, 590008.687500, 590008.750000, 590009.062500, 590010.000000",\
+ "590008.750000, 590008.812500, 590008.875000, 590009.187500, 590010.125000",\
+ "590009.125000, 590009.187500, 590009.250000, 590009.562500, 590010.500000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260980, 0.783299, 2.448362");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_usb_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "590008.437500, 590008.500000, 590008.562500, 590008.812500, 590009.500000",\
+ "590008.437500, 590008.500000, 590008.562500, 590008.812500, 590009.500000",\
+ "590008.562500, 590008.625000, 590008.687500, 590008.937500, 590009.625000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.062500, 590009.750000",\
+ "590008.937500, 590009.000000, 590009.062500, 590009.312500, 590010.000000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "590006.687500, 590006.750000, 590006.875000, 590007.125000, 590008.125000",\
+ "590006.812500, 590006.875000, 590007.000000, 590007.250000, 590008.250000",\
+ "590006.937500, 590007.000000, 590007.125000, 590007.375000, 590008.375000",\
+ "590007.062500, 590007.125000, 590007.250000, 590007.500000, 590008.500000",\
+ "590007.312500, 590007.375000, 590007.500000, 590007.750000, 590008.750000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\
+ "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\
+ "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\
+ "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\
+ "0.020388, 0.095624, 0.260980, 0.781920, 2.444935");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_usb_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "590008.312500, 590008.312500, 590008.437500, 590008.750000, 590009.687500",\
+ "590008.437500, 590008.437500, 590008.562500, 590008.875000, 590009.812500",\
+ "590008.437500, 590008.437500, 590008.562500, 590008.875000, 590009.812500",\
+ "590008.562500, 590008.562500, 590008.687500, 590009.000000, 590009.937500",\
+ "590008.812500, 590008.812500, 590008.937500, 590009.250000, 590010.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\
+ "0.038124, 0.100137, 0.260980, 0.783299, 2.448362");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "590006.625000, 590006.625000, 590006.687500, 590006.937500, 590007.625000",\
+ "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.750000",\
+ "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.875000",\
+ "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590008.000000",\
+ "590007.375000, 590007.375000, 590007.437500, 590007.687500, 590008.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\
+ "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\
+ "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\
+ "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\
+ "0.042077, 0.086820, 0.207230, 0.622005, 1.937878");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_usb_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "590008.312500, 590008.312500, 590008.437500, 590008.750000, 590009.687500",\
+ "590008.312500, 590008.312500, 590008.437500, 590008.750000, 590009.687500",\
+ "590008.437500, 590008.437500, 590008.562500, 590008.875000, 590009.812500",\
+ "590008.562500, 590008.562500, 590008.687500, 590009.000000, 590009.937500",\
+ "590008.812500, 590008.812500, 590008.937500, 590009.250000, 590010.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\
+ "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\
+ "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\
+ "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\
+ "0.020388, 0.095624, 0.260980, 0.781920, 2.444935");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "590006.625000, 590006.625000, 590006.687500, 590006.937500, 590007.625000",\
+ "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.750000",\
+ "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.875000",\
+ "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590008.000000",\
+ "590007.250000, 590007.250000, 590007.312500, 590007.562500, 590008.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236");
+ values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\
+ "0.017600, 0.075142, 0.205270, 0.618216, 1.929571");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_usb_o_inv_min*/
+
+} /* end of pin clk_src_usb_o */
+
+pin("clk_src_usb_val_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.090214 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : clk_src_usb_val_o;
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.349057, 0.389670, 0.471811, 0.746196, 1.641015",\
+ "0.436455, 0.477067, 0.559209, 0.833594, 1.728413",\
+ "0.517302, 0.557914, 0.640055, 0.914441, 1.809259",\
+ "0.655434, 0.696047, 0.778188, 1.052573, 1.947392",\
+ "0.895822, 0.936589, 1.018755, 1.291518, 2.187617");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\
+ "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\
+ "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\
+ "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\
+ "0.023046, 0.083902, 0.239672, 0.764756, 2.477149");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.392641, 0.430353, 0.490673, 0.680876, 1.305538",\
+ "0.480039, 0.517751, 0.578071, 0.768273, 1.392936",\
+ "0.560851, 0.598563, 0.658884, 0.849086, 1.473748",\
+ "0.698861, 0.736574, 0.796894, 0.987096, 1.611758",\
+ "0.919051, 0.956763, 1.017083, 1.207286, 1.831948");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\
+ "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\
+ "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\
+ "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\
+ "0.028951, 0.070788, 0.167468, 0.516468, 1.652661");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_val_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.222724, 0.263066, 0.345165, 0.618191, 1.516706",\
+ "0.310912, 0.351255, 0.433354, 0.706380, 1.604895",\
+ "0.398549, 0.438892, 0.520991, 0.794016, 1.692532",\
+ "0.546817, 0.587159, 0.669259, 0.942284, 1.840799",\
+ "0.782132, 0.822474, 0.904573, 1.177599, 2.076114");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\
+ "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\
+ "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\
+ "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\
+ "0.021530, 0.083764, 0.238778, 0.757619, 2.456895");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.263657, 0.301407, 0.361820, 0.551984, 1.176778",\
+ "0.351846, 0.389595, 0.450008, 0.640173, 1.264967",\
+ "0.439483, 0.477232, 0.537645, 0.727810, 1.352604",\
+ "0.587750, 0.625500, 0.685913, 0.876077, 1.500872",\
+ "0.813891, 0.851054, 0.911373, 1.101677, 1.725499");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\
+ "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\
+ "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\
+ "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\
+ "0.025914, 0.068635, 0.165828, 0.512808, 1.651598");
+ }
+
+ } /* end of arc clk_ast_ext_i_clk_src_usb_val_o_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\
+ "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\
+ "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\
+ "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\
+ "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_usb_val_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.691181, 0.731788, 0.813938, 1.088216, 1.983374",\
+ "0.778982, 0.819588, 0.901739, 1.176016, 2.071174",\
+ "0.860281, 0.900888, 0.983038, 1.257316, 2.152474",\
+ "0.918434, 0.959041, 1.041191, 1.315469, 2.210627",\
+ "1.227155, 1.267762, 1.349912, 1.624190, 2.519347");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.670492, 0.707647, 0.767969, 0.958286, 1.582166",\
+ "0.758292, 0.795447, 0.855769, 1.046087, 1.669967",\
+ "0.839591, 0.876747, 0.937069, 1.127386, 1.751266",\
+ "0.897745, 0.934900, 0.995222, 1.185539, 1.809419",\
+ "1.206465, 1.243621, 1.303943, 1.494260, 2.118140");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262");
+ }
+
+ } /* end of arc clk_ast_tlul_i_clk_src_usb_val_o_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970007.125000, 970007.125000, 970007.250000, 970007.500000, 970008.375000",\
+ "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\
+ "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\
+ "970007.500000, 970007.500000, 970007.625000, 970007.875000, 970008.750000",\
+ "970007.750000, 970007.750000, 970007.875000, 970008.125000, 970009.000000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970010.187500, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\
+ "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\
+ "970010.687500, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "380000.437500, 380000.500000, 380000.562500, 380000.843750, 380001.750000",\
+ "380000.531250, 380000.593750, 380000.656250, 380000.937500, 380001.843750",\
+ "380000.593750, 380000.656250, 380000.718750, 380001.000000, 380001.906250",\
+ "380000.750000, 380000.812500, 380000.875000, 380001.156250, 380002.062500",\
+ "380000.968750, 380001.031250, 380001.093750, 380001.375000, 380002.281250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "380001.875000, 380001.906250, 380001.968750, 380002.156250, 380002.781250",\
+ "380001.968750, 380002.000000, 380002.062500, 380002.250000, 380002.875000",\
+ "380002.062500, 380002.093750, 380002.156250, 380002.343750, 380002.968750",\
+ "380002.250000, 380002.281250, 380002.343750, 380002.531250, 380003.156250",\
+ "380002.500000, 380002.531250, 380002.593750, 380002.781250, 380003.406250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970007.125000, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\
+ "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\
+ "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\
+ "970007.500000, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\
+ "970007.750000, 970007.812500, 970007.875000, 970008.062500, 970008.687500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515912, 1.652408");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "970010.187500, 970010.250000, 970010.312500, 970010.625000, 970011.500000",\
+ "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\
+ "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\
+ "970010.687500, 970010.750000, 970010.812500, 970011.125000, 970012.000000",\
+ "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766838, 2.469430");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "380000.500000, 380000.531250, 380000.593750, 380000.781250, 380001.406250",\
+ "380000.593750, 380000.625000, 380000.687500, 380000.875000, 380001.500000",\
+ "380000.656250, 380000.687500, 380000.750000, 380000.937500, 380001.562500",\
+ "380000.812500, 380000.843750, 380000.906250, 380001.093750, 380001.718750",\
+ "380001.031250, 380001.062500, 380001.125000, 380001.312500, 380001.937500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\
+ "0.025904, 0.068640, 0.165825, 0.512797, 1.652262");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "380001.906250, 380001.937500, 380002.031250, 380002.281250, 380003.187500",\
+ "380002.000000, 380002.031250, 380002.125000, 380002.375000, 380003.281250",\
+ "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\
+ "380002.281250, 380002.312500, 380002.406250, 380002.656250, 380003.562500",\
+ "380002.531250, 380002.562500, 380002.656250, 380002.906250, 380003.812500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\
+ "0.021562, 0.083764, 0.238778, 0.757102, 2.460156");
+ }
+
+ } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590008.562500, 590008.625000, 590008.687500, 590009.000000, 590009.875000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\
+ "590008.812500, 590008.875000, 590008.937500, 590009.250000, 590010.125000",\
+ "590009.062500, 590009.125000, 590009.187500, 590009.500000, 590010.375000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766861, 2.469430");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590006.875000, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\
+ "590007.000000, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\
+ "590007.125000, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\
+ "590007.250000, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\
+ "590007.625000, 590007.687500, 590007.750000, 590007.937500, 590008.562500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515919, 1.652408");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\
+ "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\
+ "590008.500000, 590008.562500, 590008.625000, 590008.937500, 590009.812500",\
+ "590008.625000, 590008.687500, 590008.750000, 590009.062500, 590009.937500",\
+ "590008.875000, 590008.937500, 590009.000000, 590009.312500, 590010.187500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\
+ "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\
+ "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\
+ "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\
+ "0.022032, 0.083764, 0.238629, 0.755850, 2.465812");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590006.750000, 590006.750000, 590006.812500, 590007.000000, 590007.625000",\
+ "590006.875000, 590006.875000, 590006.937500, 590007.125000, 590007.750000",\
+ "590007.000000, 590007.000000, 590007.062500, 590007.250000, 590007.875000",\
+ "590007.125000, 590007.125000, 590007.187500, 590007.375000, 590008.000000",\
+ "590007.375000, 590007.375000, 590007.437500, 590007.625000, 590008.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\
+ "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\
+ "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\
+ "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\
+ "0.026011, 0.068726, 0.165863, 0.510725, 1.651082");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\
+ "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\
+ "0.028494, 0.070786, 0.167369, 0.515919, 1.652408");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\
+ "590007.625000, 590007.625000, 590007.750000, 590008.000000, 590008.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\
+ "0.022871, 0.084362, 0.238855, 0.766861, 2.469430");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\
+ "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\
+ "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\
+ "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\
+ "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\
+ "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\
+ "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\
+ "0.026011, 0.068726, 0.165863, 0.510725, 1.651082");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\
+ "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\
+ "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\
+ "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\
+ "590007.500000, 590007.500000, 590007.625000, 590007.875000, 590008.750000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214");
+ values ( "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\
+ "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\
+ "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\
+ "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\
+ "0.022032, 0.083764, 0.238629, 0.755850, 2.465812");
+ }
+
+ } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_inv_min*/
+
+} /* end of pin clk_src_usb_val_o */
+bus ( usb_io_pu_cal_o ) {
+
+ bus_type : BUS20_type7 ;
+ direction : output ;
+
+pin("usb_io_pu_cal_o[19]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[19];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\
+ "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\
+ "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\
+ "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\
+ "0.830581, 0.852045, 0.888318, 1.293020, 2.184924");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\
+ "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070225, 0.128223, 0.852056, 2.450128",\
+ "0.046369, 0.071964, 0.128232, 0.852062, 2.450135");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\
+ "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\
+ "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\
+ "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\
+ "0.839028, 0.848765, 0.862546, 1.001302, 1.307204");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025202, 0.034115, 0.048740, 0.301167, 0.860107",\
+ "0.025202, 0.034115, 0.048740, 0.301167, 0.860107",\
+ "0.025203, 0.034116, 0.048742, 0.301167, 0.860107",\
+ "0.025205, 0.034118, 0.048744, 0.301167, 0.860107",\
+ "0.025222, 0.034137, 0.048764, 0.301167, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[19]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.197396, 0.217798, 0.253787, 0.659515, 1.549779",\
+ "0.285773, 0.306177, 0.342166, 0.747894, 1.638158",\
+ "0.375534, 0.395928, 0.431912, 0.837641, 1.727905",\
+ "0.439799, 0.460179, 0.496157, 0.901887, 1.792151",\
+ "0.781328, 0.801955, 0.838037, 1.243750, 2.134013");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\
+ "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\
+ "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\
+ "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\
+ "0.041673, 0.070094, 0.126932, 0.849969, 2.447141");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.177011, 0.187648, 0.201756, 0.342079, 0.647165",\
+ "0.264382, 0.275019, 0.289127, 0.429450, 0.734536",\
+ "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\
+ "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\
+ "0.681430, 0.692081, 0.706196, 0.846525, 1.151605");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\
+ "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\
+ "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\
+ "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\
+ "0.024126, 0.032778, 0.047567, 0.299569, 0.856157");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[19]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[19] */
+
+pin("usb_io_pu_cal_o[18]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[18];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\
+ "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\
+ "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\
+ "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\
+ "0.830581, 0.852045, 0.888318, 1.293020, 2.184924");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\
+ "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070225, 0.128223, 0.852056, 2.450128",\
+ "0.046369, 0.071964, 0.128232, 0.852062, 2.450135");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\
+ "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\
+ "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\
+ "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\
+ "0.839028, 0.848765, 0.862546, 1.001302, 1.307204");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025200, 0.034112, 0.048740, 0.301167, 0.860107",\
+ "0.025200, 0.034112, 0.048740, 0.301167, 0.860107",\
+ "0.025202, 0.034115, 0.048742, 0.301167, 0.860107",\
+ "0.025205, 0.034118, 0.048744, 0.301167, 0.860107",\
+ "0.025221, 0.034136, 0.048764, 0.301167, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[18]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.211928, 0.232331, 0.268319, 0.674047, 1.564311",\
+ "0.300343, 0.320746, 0.356735, 0.762463, 1.652727",\
+ "0.394726, 0.415129, 0.451117, 0.856845, 1.747110",\
+ "0.462784, 0.483187, 0.519176, 0.924904, 1.815168",\
+ "0.787427, 0.807827, 0.843815, 1.249543, 2.139807");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041661, 0.070068, 0.126730, 0.849972, 2.447344",\
+ "0.041661, 0.070068, 0.126730, 0.849972, 2.447344",\
+ "0.041661, 0.070068, 0.126730, 0.849972, 2.447344",\
+ "0.041661, 0.070068, 0.126730, 0.849972, 2.447345",\
+ "0.041673, 0.070061, 0.126728, 0.849969, 2.447347");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.180996, 0.190508, 0.204096, 0.342744, 0.648655",\
+ "0.266400, 0.277038, 0.291146, 0.430107, 0.736018",\
+ "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\
+ "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\
+ "0.681430, 0.692081, 0.706196, 0.846525, 1.151605");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\
+ "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\
+ "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\
+ "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\
+ "0.024126, 0.032778, 0.047567, 0.299569, 0.856157");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[18]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[18] */
+
+pin("usb_io_pu_cal_o[17]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[17];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\
+ "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\
+ "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\
+ "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\
+ "0.830581, 0.852045, 0.888318, 1.293020, 2.184924");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044601, 0.070148, 0.128218, 0.852056, 2.450125",\
+ "0.044663, 0.070159, 0.128218, 0.852056, 2.450125",\
+ "0.044669, 0.070182, 0.128220, 0.852056, 2.450126",\
+ "0.044669, 0.070225, 0.128223, 0.852056, 2.450128",\
+ "0.046118, 0.071698, 0.128232, 0.852061, 2.450135");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\
+ "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\
+ "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\
+ "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\
+ "0.839028, 0.848765, 0.862546, 1.001302, 1.307204");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025212, 0.034126, 0.048740, 0.301166, 0.860107",\
+ "0.025213, 0.034127, 0.048740, 0.301166, 0.860107",\
+ "0.025216, 0.034130, 0.048742, 0.301166, 0.860107",\
+ "0.025218, 0.034133, 0.048744, 0.301166, 0.860107",\
+ "0.025235, 0.034151, 0.048764, 0.301166, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[17]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\
+ "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\
+ "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\
+ "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\
+ "0.763219, 0.783617, 0.819604, 1.225332, 2.115596");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\
+ "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\
+ "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\
+ "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\
+ "0.041673, 0.070054, 0.126726, 0.849969, 2.447349");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.175899, 0.186544, 0.200656, 0.340982, 0.646065",\
+ "0.263271, 0.273916, 0.288028, 0.428355, 0.733437",\
+ "0.344128, 0.354771, 0.368883, 0.509209, 0.814291",\
+ "0.401818, 0.412460, 0.426571, 0.566896, 0.871980",\
+ "0.705550, 0.716209, 0.730328, 0.870660, 1.175736");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\
+ "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\
+ "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\
+ "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\
+ "0.024126, 0.032778, 0.047574, 0.299569, 0.856133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[17]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[17] */
+
+pin("usb_io_pu_cal_o[16]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[16];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\
+ "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\
+ "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\
+ "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\
+ "0.830581, 0.852045, 0.888318, 1.293020, 2.184924");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\
+ "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\
+ "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\
+ "0.044695, 0.070225, 0.128223, 0.852056, 2.450128",\
+ "0.044695, 0.070368, 0.128232, 0.852056, 2.450135");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\
+ "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\
+ "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\
+ "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\
+ "0.839028, 0.848765, 0.862546, 1.001302, 1.307204");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025212, 0.034126, 0.048740, 0.301166, 0.860107",\
+ "0.025212, 0.034126, 0.048740, 0.301166, 0.860107",\
+ "0.025216, 0.034130, 0.048742, 0.301166, 0.860107",\
+ "0.025218, 0.034133, 0.048744, 0.301166, 0.860107",\
+ "0.025235, 0.034151, 0.048764, 0.301166, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[16]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.241214, 0.262542, 0.298754, 0.703431, 1.595333",\
+ "0.329624, 0.350953, 0.387164, 0.791841, 1.683743",\
+ "0.418828, 0.440156, 0.476368, 0.881044, 1.772947",\
+ "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\
+ "0.763219, 0.783617, 0.819604, 1.225332, 2.115596");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\
+ "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\
+ "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\
+ "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\
+ "0.041673, 0.070054, 0.126726, 0.849969, 2.447349");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.180996, 0.190508, 0.204096, 0.342744, 0.648655",\
+ "0.268360, 0.277871, 0.291459, 0.430107, 0.736018",\
+ "0.349209, 0.358716, 0.372303, 0.510951, 0.816863",\
+ "0.406926, 0.416431, 0.430016, 0.568664, 0.874576",\
+ "0.710950, 0.720466, 0.734056, 0.872703, 1.178614");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\
+ "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\
+ "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\
+ "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\
+ "0.024126, 0.032778, 0.047572, 0.299569, 0.856139");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[16]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[16] */
+
+pin("usb_io_pu_cal_o[15]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[15];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\
+ "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\
+ "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\
+ "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\
+ "0.862468, 0.884064, 0.920396, 1.325122, 2.217029");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\
+ "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070220, 0.128222, 0.852056, 2.450128",\
+ "0.046369, 0.071964, 0.128250, 0.852062, 2.450147");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.208477, 0.218207, 0.231981, 0.370730, 0.676633",\
+ "0.296951, 0.306682, 0.320455, 0.459205, 0.765107",\
+ "0.387709, 0.397440, 0.411214, 0.549964, 0.855866",\
+ "0.453111, 0.462843, 0.476618, 0.615368, 0.921270",\
+ "0.800244, 0.809980, 0.823761, 0.962517, 1.268419");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025202, 0.034115, 0.048739, 0.301167, 0.860107",\
+ "0.025202, 0.034115, 0.048739, 0.301167, 0.860107",\
+ "0.025203, 0.034116, 0.048740, 0.301167, 0.860107",\
+ "0.025205, 0.034118, 0.048742, 0.301167, 0.860107",\
+ "0.025222, 0.034137, 0.048763, 0.301167, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[15]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.197396, 0.217798, 0.253787, 0.659515, 1.549779",\
+ "0.285773, 0.306177, 0.342166, 0.747894, 1.638158",\
+ "0.375534, 0.395928, 0.431912, 0.837641, 1.727905",\
+ "0.439799, 0.460179, 0.496157, 0.901887, 1.792151",\
+ "0.781328, 0.801955, 0.838037, 1.243750, 2.134013");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041685, 0.069999, 0.126709, 0.849953, 2.447141",\
+ "0.041695, 0.069999, 0.126709, 0.849953, 2.447141",\
+ "0.041741, 0.069999, 0.126709, 0.849953, 2.447141",\
+ "0.041758, 0.069999, 0.126709, 0.849953, 2.447141",\
+ "0.041766, 0.070174, 0.126932, 0.849953, 2.447141");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.177011, 0.187648, 0.201756, 0.340918, 0.646830",\
+ "0.264382, 0.275019, 0.289127, 0.428292, 0.734203",\
+ "0.342508, 0.353145, 0.367252, 0.506601, 0.812513",\
+ "0.397042, 0.407678, 0.421785, 0.561150, 0.867061",\
+ "0.681430, 0.692081, 0.706196, 0.845682, 1.151594");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\
+ "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\
+ "0.024117, 0.032767, 0.047553, 0.299569, 0.856201",\
+ "0.024117, 0.032759, 0.047552, 0.299568, 0.856201",\
+ "0.024117, 0.032759, 0.047552, 0.299568, 0.856157");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[15]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[15] */
+
+pin("usb_io_pu_cal_o[14]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[14];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\
+ "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\
+ "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\
+ "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\
+ "0.862468, 0.884064, 0.920396, 1.325122, 2.217029");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\
+ "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070220, 0.128222, 0.852056, 2.450128",\
+ "0.046369, 0.071964, 0.128250, 0.852062, 2.450147");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.208477, 0.218207, 0.231981, 0.370730, 0.676633",\
+ "0.296951, 0.306682, 0.320455, 0.459205, 0.765107",\
+ "0.387709, 0.397440, 0.411214, 0.549964, 0.855866",\
+ "0.453111, 0.462843, 0.476618, 0.615368, 0.921270",\
+ "0.800244, 0.809980, 0.823761, 0.962517, 1.268419");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025200, 0.034112, 0.048739, 0.301167, 0.860107",\
+ "0.025200, 0.034112, 0.048739, 0.301167, 0.860107",\
+ "0.025202, 0.034115, 0.048740, 0.301167, 0.860107",\
+ "0.025205, 0.034118, 0.048742, 0.301167, 0.860107",\
+ "0.025221, 0.034136, 0.048763, 0.301167, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[14]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.211928, 0.232331, 0.268319, 0.674047, 1.564311",\
+ "0.300343, 0.320746, 0.356735, 0.762463, 1.652727",\
+ "0.394726, 0.415129, 0.451117, 0.856845, 1.747110",\
+ "0.462784, 0.483187, 0.519176, 0.924904, 1.815168",\
+ "0.787427, 0.807827, 0.843815, 1.249543, 2.139807");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041685, 0.070068, 0.126730, 0.849967, 2.447344",\
+ "0.041695, 0.070068, 0.126730, 0.849965, 2.447344",\
+ "0.041741, 0.070068, 0.126730, 0.849957, 2.447344",\
+ "0.041758, 0.070068, 0.126730, 0.849954, 2.447345",\
+ "0.041766, 0.070061, 0.126728, 0.849953, 2.447347");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.179169, 0.188682, 0.202271, 0.340918, 0.646830",\
+ "0.266400, 0.276055, 0.289644, 0.428292, 0.734203",\
+ "0.342508, 0.353145, 0.367252, 0.506601, 0.812513",\
+ "0.397042, 0.407678, 0.421785, 0.561150, 0.867061",\
+ "0.681430, 0.692081, 0.706196, 0.845682, 1.151594");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\
+ "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\
+ "0.024117, 0.032767, 0.047553, 0.299569, 0.856201",\
+ "0.024117, 0.032759, 0.047552, 0.299568, 0.856201",\
+ "0.024117, 0.032759, 0.047552, 0.299568, 0.856157");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[14]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[14] */
+
+pin("usb_io_pu_cal_o[13]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[13];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\
+ "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\
+ "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\
+ "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\
+ "0.862468, 0.884064, 0.920396, 1.325122, 2.217029");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044601, 0.070167, 0.128219, 0.852056, 2.450125",\
+ "0.044663, 0.070167, 0.128219, 0.852056, 2.450125",\
+ "0.044669, 0.070177, 0.128220, 0.852056, 2.450126",\
+ "0.044669, 0.070220, 0.128222, 0.852056, 2.450128",\
+ "0.046118, 0.071698, 0.128250, 0.852061, 2.450147");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.208477, 0.218207, 0.231981, 0.372429, 0.677586",\
+ "0.296951, 0.306682, 0.320688, 0.461137, 0.766294",\
+ "0.391373, 0.402162, 0.416428, 0.556878, 0.862036",\
+ "0.460819, 0.471609, 0.485876, 0.626327, 0.931486",\
+ "0.825748, 0.836544, 0.850818, 0.991274, 1.296437");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025212, 0.034126, 0.048739, 0.301166, 0.860107",\
+ "0.025213, 0.034127, 0.048739, 0.301166, 0.860107",\
+ "0.025216, 0.034130, 0.048740, 0.301166, 0.860107",\
+ "0.025218, 0.034133, 0.048742, 0.301166, 0.860107",\
+ "0.025235, 0.034151, 0.048763, 0.301166, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[13]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\
+ "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\
+ "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\
+ "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\
+ "0.763219, 0.783617, 0.819604, 1.225332, 2.115596");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041685, 0.070060, 0.126728, 0.849967, 2.447347",\
+ "0.041695, 0.070060, 0.126728, 0.849965, 2.447347",\
+ "0.041741, 0.070060, 0.126728, 0.849957, 2.447347",\
+ "0.041758, 0.070060, 0.126728, 0.849954, 2.447347",\
+ "0.041766, 0.070054, 0.126726, 0.849953, 2.447349");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.175899, 0.186544, 0.200656, 0.340918, 0.646065",\
+ "0.263271, 0.273916, 0.288028, 0.428292, 0.733437",\
+ "0.344128, 0.354365, 0.367954, 0.506601, 0.812513",\
+ "0.399406, 0.408915, 0.422502, 0.561150, 0.867061",\
+ "0.683934, 0.693446, 0.707035, 0.845682, 1.151594");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024118, 0.032771, 0.047561, 0.299569, 0.856177",\
+ "0.024118, 0.032771, 0.047561, 0.299569, 0.856176",\
+ "0.024117, 0.032767, 0.047560, 0.299569, 0.856176",\
+ "0.024117, 0.032759, 0.047558, 0.299568, 0.856176",\
+ "0.024117, 0.032759, 0.047558, 0.299568, 0.856133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[13]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[13] */
+
+pin("usb_io_pu_cal_o[12]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[12];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\
+ "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\
+ "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\
+ "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\
+ "0.862468, 0.884064, 0.920396, 1.325122, 2.217029");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044695, 0.070193, 0.128219, 0.852056, 2.450125",\
+ "0.044695, 0.070193, 0.128219, 0.852056, 2.450125",\
+ "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\
+ "0.044695, 0.070220, 0.128222, 0.852056, 2.450128",\
+ "0.044695, 0.070644, 0.128250, 0.852056, 2.450147");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.208477, 0.218207, 0.231981, 0.372429, 0.677586",\
+ "0.296951, 0.306682, 0.320455, 0.460894, 0.766051",\
+ "0.391373, 0.402162, 0.416428, 0.556878, 0.862036",\
+ "0.460819, 0.471609, 0.485876, 0.626327, 0.931486",\
+ "0.825748, 0.836544, 0.850818, 0.991274, 1.296437");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025212, 0.034126, 0.048739, 0.301166, 0.860107",\
+ "0.025212, 0.034126, 0.048739, 0.301166, 0.860107",\
+ "0.025216, 0.034130, 0.048740, 0.301166, 0.860107",\
+ "0.025218, 0.034133, 0.048742, 0.301166, 0.860107",\
+ "0.025235, 0.034151, 0.048763, 0.301166, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[12]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.238920, 0.260258, 0.296474, 0.701152, 1.593054",\
+ "0.327371, 0.348714, 0.384932, 0.789611, 1.681513",\
+ "0.416587, 0.437948, 0.474174, 0.878857, 1.770759",\
+ "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\
+ "0.763219, 0.783617, 0.819604, 1.225332, 2.115596");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041685, 0.070060, 0.126728, 0.849967, 2.447347",\
+ "0.041695, 0.070060, 0.126728, 0.849965, 2.447347",\
+ "0.041741, 0.070060, 0.126728, 0.849957, 2.447347",\
+ "0.041758, 0.070060, 0.126728, 0.849954, 2.447347",\
+ "0.041766, 0.070054, 0.126726, 0.849953, 2.447349");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.179169, 0.188682, 0.202271, 0.340918, 0.646830",\
+ "0.266542, 0.276055, 0.289644, 0.428292, 0.734203",\
+ "0.344853, 0.354365, 0.367954, 0.506601, 0.812513",\
+ "0.399406, 0.408915, 0.422502, 0.561150, 0.867061",\
+ "0.683934, 0.693446, 0.707035, 0.845682, 1.151594");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024118, 0.032771, 0.047563, 0.299569, 0.856171",\
+ "0.024118, 0.032771, 0.047563, 0.299569, 0.856171",\
+ "0.024117, 0.032767, 0.047561, 0.299569, 0.856171",\
+ "0.024117, 0.032759, 0.047559, 0.299568, 0.856171",\
+ "0.024117, 0.032759, 0.047559, 0.299568, 0.856139");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[12]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[12] */
+
+pin("usb_io_pu_cal_o[11]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[11];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\
+ "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\
+ "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\
+ "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\
+ "0.858742, 0.881931, 0.919078, 1.324622, 2.214868");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\
+ "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\
+ "0.051946, 0.077865, 0.129119, 0.852080, 2.449966",\
+ "0.052034, 0.077959, 0.129147, 0.852081, 2.449966",\
+ "0.052292, 0.078232, 0.129231, 0.852081, 2.450003");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.206143, 0.216949, 0.231236, 0.371702, 0.676873",\
+ "0.294617, 0.305423, 0.319710, 0.460177, 0.765348",\
+ "0.385375, 0.396181, 0.410468, 0.550935, 0.856106",\
+ "0.450776, 0.461583, 0.475870, 0.616338, 0.921509",\
+ "0.797902, 0.808713, 0.823006, 0.963477, 1.268652");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025267, 0.034187, 0.048727, 0.301161, 0.860108",\
+ "0.025267, 0.034187, 0.048727, 0.301161, 0.860108",\
+ "0.025267, 0.034188, 0.048728, 0.301161, 0.860108",\
+ "0.025268, 0.034189, 0.048730, 0.301161, 0.860108",\
+ "0.025282, 0.034204, 0.048751, 0.301161, 0.860108");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[11]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.205226, 0.224853, 0.260301, 0.664656, 1.556533",\
+ "0.293604, 0.313232, 0.348681, 0.753036, 1.644913",\
+ "0.383357, 0.402977, 0.438423, 0.842777, 1.734654",\
+ "0.447610, 0.467222, 0.502663, 0.907016, 1.798893",\
+ "0.789341, 0.809115, 0.844630, 1.249013, 2.140893");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\
+ "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\
+ "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\
+ "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\
+ "0.037854, 0.066833, 0.128000, 0.850658, 2.444969");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.179497, 0.189096, 0.202727, 0.341364, 0.647272",\
+ "0.266868, 0.276467, 0.290098, 0.428735, 0.734643",\
+ "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\
+ "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\
+ "0.683921, 0.693531, 0.707168, 0.845803, 1.151711");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\
+ "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\
+ "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\
+ "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\
+ "0.024427, 0.033054, 0.047472, 0.299575, 0.856462");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[11]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[11] */
+
+pin("usb_io_pu_cal_o[10]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[10];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\
+ "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\
+ "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\
+ "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\
+ "0.858742, 0.881931, 0.919078, 1.324622, 2.214868");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\
+ "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\
+ "0.051946, 0.077865, 0.129119, 0.852080, 2.449966",\
+ "0.052034, 0.077959, 0.129147, 0.852081, 2.449966",\
+ "0.052292, 0.078232, 0.129231, 0.852081, 2.450003");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.206143, 0.216949, 0.231236, 0.371702, 0.676873",\
+ "0.294617, 0.305423, 0.319710, 0.460177, 0.765348",\
+ "0.385375, 0.396181, 0.410468, 0.550935, 0.856106",\
+ "0.450776, 0.461583, 0.475870, 0.616338, 0.921509",\
+ "0.797902, 0.808713, 0.823006, 0.963477, 1.268652");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025267, 0.034187, 0.048724, 0.301161, 0.860108",\
+ "0.025267, 0.034187, 0.048724, 0.301161, 0.860108",\
+ "0.025267, 0.034188, 0.048727, 0.301161, 0.860108",\
+ "0.025268, 0.034189, 0.048730, 0.301161, 0.860108",\
+ "0.025282, 0.034204, 0.048750, 0.301161, 0.860108");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[10]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.219758, 0.239385, 0.274833, 0.679189, 1.571066",\
+ "0.308173, 0.327801, 0.363249, 0.767605, 1.659482",\
+ "0.402556, 0.422183, 0.457632, 0.861987, 1.753864",\
+ "0.470615, 0.490242, 0.525690, 0.930046, 1.821923",\
+ "0.795255, 0.814880, 0.850328, 1.254683, 2.146560");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.037493, 0.066526, 0.127980, 0.850723, 2.444973",\
+ "0.037493, 0.066526, 0.127980, 0.850723, 2.444973",\
+ "0.037493, 0.066525, 0.127980, 0.850723, 2.444973",\
+ "0.037493, 0.066525, 0.127980, 0.850723, 2.444972",\
+ "0.037489, 0.066522, 0.127980, 0.850723, 2.444969");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.184074, 0.193673, 0.207304, 0.345941, 0.651849",\
+ "0.268886, 0.278485, 0.292117, 0.430754, 0.736662",\
+ "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\
+ "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\
+ "0.683921, 0.693531, 0.707168, 0.845803, 1.151711");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\
+ "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\
+ "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\
+ "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\
+ "0.024427, 0.033054, 0.047472, 0.299575, 0.856462");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[10]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[10] */
+
+pin("usb_io_pu_cal_o[9]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[9];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\
+ "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\
+ "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\
+ "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\
+ "0.858742, 0.881931, 0.919078, 1.324622, 2.214868");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449964",\
+ "0.051871, 0.077785, 0.129094, 0.852080, 2.449965",\
+ "0.051946, 0.077865, 0.129119, 0.852080, 2.449965",\
+ "0.052034, 0.077959, 0.129147, 0.852081, 2.449965",\
+ "0.052292, 0.078232, 0.129231, 0.852081, 2.449997");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.209465, 0.219196, 0.232970, 0.371719, 0.677621",\
+ "0.298173, 0.307904, 0.321678, 0.460428, 0.766330",\
+ "0.393912, 0.403643, 0.417418, 0.556169, 0.862071",\
+ "0.463358, 0.473091, 0.486867, 0.625618, 0.931520",\
+ "0.828290, 0.838027, 0.851809, 0.990566, 1.296468");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025267, 0.034187, 0.048739, 0.301161, 0.860107",\
+ "0.025267, 0.034187, 0.048740, 0.301161, 0.860107",\
+ "0.025267, 0.034188, 0.048743, 0.301161, 0.860107",\
+ "0.025268, 0.034189, 0.048747, 0.301161, 0.860107",\
+ "0.025282, 0.034204, 0.048767, 0.301161, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[9]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.202317, 0.221942, 0.257390, 0.661745, 1.553622",\
+ "0.290456, 0.310081, 0.345529, 0.749884, 1.641761",\
+ "0.379864, 0.399489, 0.434937, 0.839292, 1.731169",\
+ "0.443880, 0.463505, 0.498953, 0.903308, 1.795185",\
+ "0.771045, 0.790669, 0.826116, 1.230471, 2.122348");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\
+ "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\
+ "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\
+ "0.037489, 0.066522, 0.127980, 0.850724, 2.444972",\
+ "0.037486, 0.066519, 0.127980, 0.850725, 2.444969");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.178388, 0.187993, 0.201627, 0.340263, 0.646171",\
+ "0.265760, 0.275365, 0.289000, 0.427635, 0.733544",\
+ "0.345043, 0.355588, 0.369648, 0.508490, 0.814398",\
+ "0.399593, 0.410134, 0.424192, 0.564475, 0.869603",\
+ "0.684147, 0.694701, 0.708766, 0.849054, 1.154177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\
+ "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\
+ "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\
+ "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\
+ "0.024446, 0.033071, 0.047472, 0.299576, 0.856462");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[9]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[9] */
+
+pin("usb_io_pu_cal_o[8]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[8];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\
+ "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\
+ "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\
+ "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\
+ "0.858742, 0.881931, 0.919078, 1.324622, 2.214868");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\
+ "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\
+ "0.051946, 0.077865, 0.129119, 0.852080, 2.449966",\
+ "0.052034, 0.077959, 0.129147, 0.852081, 2.449966",\
+ "0.052292, 0.078232, 0.129231, 0.852081, 2.449966");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.209465, 0.219196, 0.232970, 0.371719, 0.677621",\
+ "0.297931, 0.307661, 0.321435, 0.460184, 0.766087",\
+ "0.393912, 0.403643, 0.417418, 0.556169, 0.862071",\
+ "0.463358, 0.473091, 0.486867, 0.625618, 0.931520",\
+ "0.828290, 0.838027, 0.851809, 0.990566, 1.296468");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025267, 0.034187, 0.048739, 0.301161, 0.860107",\
+ "0.025267, 0.034187, 0.048739, 0.301161, 0.860107",\
+ "0.025267, 0.034188, 0.048743, 0.301161, 0.860107",\
+ "0.025268, 0.034189, 0.048747, 0.301161, 0.860107",\
+ "0.025282, 0.034204, 0.048767, 0.301161, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[8]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.248424, 0.271436, 0.308509, 0.714064, 1.604311",\
+ "0.336713, 0.359725, 0.396797, 0.802353, 1.692600",\
+ "0.429673, 0.449299, 0.484746, 0.889101, 1.780978",\
+ "0.486001, 0.505626, 0.541074, 0.945429, 1.837306",\
+ "0.771045, 0.790669, 0.826116, 1.230471, 2.122348");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\
+ "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\
+ "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\
+ "0.037489, 0.066522, 0.127980, 0.850724, 2.444972",\
+ "0.037486, 0.066519, 0.127980, 0.850725, 2.444969");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.184129, 0.194678, 0.208740, 0.349027, 0.654152",\
+ "0.268945, 0.279493, 0.293555, 0.433842, 0.738967",\
+ "0.345043, 0.355588, 0.369648, 0.509933, 0.815059",\
+ "0.399593, 0.410134, 0.424192, 0.564475, 0.869603",\
+ "0.684147, 0.694701, 0.708766, 0.849054, 1.154177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\
+ "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\
+ "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\
+ "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\
+ "0.024441, 0.033067, 0.047472, 0.299576, 0.856462");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[8]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[8] */
+
+pin("usb_io_pu_cal_o[7]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[7];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.310638, 0.333683, 0.370769, 0.776322, 1.666569",\
+ "0.398002, 0.421047, 0.458133, 0.863687, 1.753934",\
+ "0.478900, 0.501952, 0.539042, 0.944594, 1.834842",\
+ "0.536750, 0.559833, 0.596935, 1.002486, 1.892733",\
+ "0.841468, 0.864657, 0.901804, 1.307347, 2.197594");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.051891, 0.077808, 0.129101, 0.852080, 2.449966",\
+ "0.051892, 0.077808, 0.129101, 0.852080, 2.449966",\
+ "0.051912, 0.077829, 0.129108, 0.852080, 2.449966",\
+ "0.051998, 0.077921, 0.129136, 0.852080, 2.449966",\
+ "0.052293, 0.078232, 0.129231, 0.852081, 2.450003");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.213971, 0.224767, 0.239042, 0.379500, 0.684663",\
+ "0.302629, 0.313425, 0.327700, 0.468158, 0.773321",\
+ "0.398375, 0.409171, 0.423447, 0.563905, 0.869068",\
+ "0.467906, 0.478703, 0.492979, 0.633438, 0.938602",\
+ "0.835457, 0.846260, 0.860543, 1.001007, 1.306175");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025238, 0.034155, 0.048727, 0.301163, 0.860108",\
+ "0.025238, 0.034155, 0.048727, 0.301163, 0.860108",\
+ "0.025238, 0.034156, 0.048728, 0.301163, 0.860108",\
+ "0.025240, 0.034158, 0.048730, 0.301163, 0.860108",\
+ "0.025257, 0.034176, 0.048751, 0.301163, 0.860108");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[7]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.205226, 0.224853, 0.260301, 0.664656, 1.556533",\
+ "0.293604, 0.313232, 0.348681, 0.753036, 1.644913",\
+ "0.383357, 0.402977, 0.438423, 0.842777, 1.734654",\
+ "0.447610, 0.467222, 0.502663, 0.907016, 1.798893",\
+ "0.789341, 0.809115, 0.844630, 1.249013, 2.140893");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\
+ "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\
+ "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\
+ "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\
+ "0.037854, 0.066833, 0.128000, 0.850658, 2.444959");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.176807, 0.187341, 0.201395, 0.341364, 0.646807",\
+ "0.264176, 0.274709, 0.288763, 0.428735, 0.734175",\
+ "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\
+ "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\
+ "0.683921, 0.693531, 0.707168, 0.845803, 1.151711");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\
+ "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\
+ "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\
+ "0.024391, 0.033017, 0.047450, 0.299575, 0.856488",\
+ "0.024427, 0.033054, 0.047464, 0.299575, 0.856488");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[7]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[7] */
+
+pin("usb_io_pu_cal_o[6]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[6];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.310638, 0.333683, 0.370769, 0.776322, 1.666569",\
+ "0.398002, 0.421047, 0.458133, 0.863687, 1.753934",\
+ "0.478900, 0.501952, 0.539042, 0.944594, 1.834842",\
+ "0.536750, 0.559833, 0.596935, 1.002486, 1.892733",\
+ "0.841468, 0.864657, 0.901804, 1.307347, 2.197594");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.051891, 0.077808, 0.129101, 0.852080, 2.449966",\
+ "0.051892, 0.077808, 0.129101, 0.852080, 2.449966",\
+ "0.051912, 0.077829, 0.129108, 0.852080, 2.449966",\
+ "0.051998, 0.077921, 0.129136, 0.852080, 2.449966",\
+ "0.052293, 0.078232, 0.129231, 0.852081, 2.450003");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.213971, 0.224767, 0.239042, 0.379500, 0.684663",\
+ "0.302629, 0.313425, 0.327700, 0.468158, 0.773321",\
+ "0.398375, 0.409171, 0.423447, 0.563905, 0.869068",\
+ "0.467906, 0.478703, 0.492979, 0.633438, 0.938602",\
+ "0.835457, 0.846260, 0.860543, 1.001007, 1.306175");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025238, 0.034155, 0.048724, 0.301163, 0.860108",\
+ "0.025238, 0.034155, 0.048724, 0.301163, 0.860108",\
+ "0.025238, 0.034156, 0.048727, 0.301163, 0.860108",\
+ "0.025240, 0.034158, 0.048730, 0.301163, 0.860108",\
+ "0.025257, 0.034176, 0.048750, 0.301163, 0.860108");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[6]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.219758, 0.239385, 0.274833, 0.679189, 1.571066",\
+ "0.308173, 0.327801, 0.363249, 0.767605, 1.659482",\
+ "0.402556, 0.422183, 0.457632, 0.861987, 1.753864",\
+ "0.469866, 0.490242, 0.525690, 0.930046, 1.821923",\
+ "0.795255, 0.814880, 0.850328, 1.254683, 2.146560");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.037493, 0.066526, 0.127980, 0.850723, 2.444963",\
+ "0.037493, 0.066526, 0.127980, 0.850723, 2.444963",\
+ "0.037493, 0.066525, 0.127980, 0.850723, 2.444963",\
+ "0.037493, 0.066525, 0.127980, 0.850723, 2.444962",\
+ "0.037489, 0.066522, 0.127980, 0.850723, 2.444959");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.176807, 0.187341, 0.201395, 0.341676, 0.646807",\
+ "0.264176, 0.274709, 0.288763, 0.429043, 0.734175",\
+ "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\
+ "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\
+ "0.683921, 0.693531, 0.707168, 0.845803, 1.151711");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\
+ "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\
+ "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\
+ "0.024391, 0.033017, 0.047450, 0.299575, 0.856488",\
+ "0.024427, 0.033054, 0.047464, 0.299575, 0.856488");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[6]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[6] */
+
+pin("usb_io_pu_cal_o[5]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[5];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320620, 0.341983, 0.378211, 0.782894, 1.674796",\
+ "0.407985, 0.429348, 0.465575, 0.870258, 1.762161",\
+ "0.488889, 0.510256, 0.546486, 0.951170, 1.843073",\
+ "0.546764, 0.568152, 0.604391, 1.009078, 1.900981",\
+ "0.851568, 0.873026, 0.909296, 1.313997, 2.205901");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044601, 0.070156, 0.128218, 0.852056, 2.450125",\
+ "0.044663, 0.070159, 0.128218, 0.852056, 2.450125",\
+ "0.044669, 0.070166, 0.128219, 0.852056, 2.450125",\
+ "0.044669, 0.070209, 0.128222, 0.852056, 2.450127",\
+ "0.046118, 0.071698, 0.128231, 0.852061, 2.450134");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.216513, 0.226251, 0.240034, 0.378792, 0.684694",\
+ "0.305171, 0.314909, 0.328692, 0.467450, 0.773352",\
+ "0.400916, 0.410655, 0.424439, 0.563197, 0.869098",\
+ "0.470448, 0.480187, 0.493971, 0.632730, 0.938632",\
+ "0.838001, 0.847745, 0.861536, 1.000300, 1.306202");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025212, 0.034126, 0.048771, 0.301166, 0.860107",\
+ "0.025213, 0.034127, 0.048771, 0.301166, 0.860107",\
+ "0.025216, 0.034130, 0.048772, 0.301166, 0.860107",\
+ "0.025218, 0.034133, 0.048774, 0.301166, 0.860107",\
+ "0.025235, 0.034151, 0.048795, 0.301166, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[5]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\
+ "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\
+ "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\
+ "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\
+ "0.763219, 0.783617, 0.819604, 1.225332, 2.115596");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\
+ "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\
+ "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\
+ "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\
+ "0.041716, 0.070054, 0.126726, 0.849962, 2.447349");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.175899, 0.186544, 0.200656, 0.340982, 0.646065",\
+ "0.263271, 0.273916, 0.288028, 0.428355, 0.733437",\
+ "0.344128, 0.354771, 0.368883, 0.509209, 0.814291",\
+ "0.401818, 0.412460, 0.426571, 0.566896, 0.871980",\
+ "0.705550, 0.716209, 0.730328, 0.870579, 1.175736");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024130, 0.032772, 0.047558, 0.299569, 0.856133",\
+ "0.024130, 0.032772, 0.047558, 0.299569, 0.856133",\
+ "0.024130, 0.032772, 0.047558, 0.299569, 0.856133",\
+ "0.024130, 0.032776, 0.047558, 0.299569, 0.856133",\
+ "0.024160, 0.032809, 0.047574, 0.299570, 0.856133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[5]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[5] */
+
+pin("usb_io_pu_cal_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[4];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320620, 0.341983, 0.378211, 0.782894, 1.674796",\
+ "0.407985, 0.429348, 0.465575, 0.870258, 1.762161",\
+ "0.488889, 0.510256, 0.546486, 0.951170, 1.843073",\
+ "0.546764, 0.568152, 0.604391, 1.009078, 1.900981",\
+ "0.851568, 0.873026, 0.909296, 1.313997, 2.205901");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\
+ "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\
+ "0.044695, 0.070193, 0.128219, 0.852056, 2.450125",\
+ "0.044695, 0.070209, 0.128222, 0.852056, 2.450127",\
+ "0.044695, 0.070356, 0.128231, 0.852056, 2.450134");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.216513, 0.226251, 0.240034, 0.378792, 0.684694",\
+ "0.305171, 0.314909, 0.328692, 0.467450, 0.773352",\
+ "0.400916, 0.410655, 0.424439, 0.563197, 0.869098",\
+ "0.470448, 0.480187, 0.493971, 0.632730, 0.938632",\
+ "0.838001, 0.847745, 0.861536, 1.000300, 1.306202");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025212, 0.034126, 0.048771, 0.301166, 0.860107",\
+ "0.025212, 0.034126, 0.048771, 0.301166, 0.860107",\
+ "0.025216, 0.034130, 0.048772, 0.301166, 0.860107",\
+ "0.025218, 0.034133, 0.048774, 0.301166, 0.860107",\
+ "0.025235, 0.034151, 0.048795, 0.301166, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.238935, 0.260283, 0.296504, 0.701185, 1.593087",\
+ "0.327362, 0.348711, 0.384931, 0.789612, 1.681514",\
+ "0.416458, 0.437806, 0.474027, 0.878708, 1.770610",\
+ "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\
+ "0.763219, 0.783617, 0.819604, 1.225332, 2.115596");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\
+ "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\
+ "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\
+ "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\
+ "0.041716, 0.070054, 0.126726, 0.849962, 2.447349");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.179257, 0.188774, 0.202365, 0.341012, 0.646923",\
+ "0.266626, 0.276142, 0.289732, 0.428379, 0.734291",\
+ "0.347482, 0.356996, 0.370585, 0.509232, 0.815144",\
+ "0.405200, 0.414714, 0.428304, 0.566951, 0.872863",\
+ "0.708812, 0.718338, 0.731933, 0.870579, 1.176490");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024130, 0.032772, 0.047559, 0.299569, 0.856139",\
+ "0.024130, 0.032772, 0.047559, 0.299569, 0.856139",\
+ "0.024130, 0.032772, 0.047559, 0.299569, 0.856139",\
+ "0.024130, 0.032776, 0.047559, 0.299569, 0.856139",\
+ "0.024160, 0.032809, 0.047572, 0.299570, 0.856139");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[4]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[4] */
+
+pin("usb_io_pu_cal_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\
+ "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\
+ "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\
+ "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\
+ "0.851113, 0.872490, 0.908724, 1.313410, 2.205313");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.046369, 0.071964, 0.128220, 0.852062, 2.450126");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\
+ "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\
+ "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\
+ "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\
+ "0.837901, 0.847639, 0.861421, 1.000178, 1.306080");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025202, 0.034115, 0.048744, 0.301167, 0.860107",\
+ "0.025202, 0.034115, 0.048744, 0.301167, 0.860107",\
+ "0.025203, 0.034116, 0.048746, 0.301167, 0.860107",\
+ "0.025205, 0.034118, 0.048746, 0.301167, 0.860107",\
+ "0.025222, 0.034137, 0.048767, 0.301167, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.197396, 0.217798, 0.253787, 0.659515, 1.549779",\
+ "0.285773, 0.306177, 0.342166, 0.747894, 1.638158",\
+ "0.375534, 0.395928, 0.431912, 0.837641, 1.727905",\
+ "0.439799, 0.460179, 0.496157, 0.901887, 1.792151",\
+ "0.781328, 0.801955, 0.838037, 1.243750, 2.134013");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\
+ "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\
+ "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\
+ "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\
+ "0.041728, 0.070141, 0.126932, 0.849959, 2.447141");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.177011, 0.187648, 0.201756, 0.342079, 0.647165",\
+ "0.264382, 0.275019, 0.289127, 0.429450, 0.734536",\
+ "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\
+ "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\
+ "0.681430, 0.692081, 0.706196, 0.846525, 1.151605");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\
+ "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\
+ "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\
+ "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\
+ "0.024132, 0.032784, 0.047567, 0.299569, 0.856157");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[3]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[3] */
+
+pin("usb_io_pu_cal_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\
+ "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\
+ "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\
+ "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\
+ "0.851113, 0.872490, 0.908724, 1.313410, 2.205313");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\
+ "0.046369, 0.071964, 0.128220, 0.852062, 2.450126");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\
+ "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\
+ "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\
+ "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\
+ "0.837901, 0.847639, 0.861421, 1.000178, 1.306080");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025200, 0.034112, 0.048744, 0.301167, 0.860107",\
+ "0.025200, 0.034112, 0.048744, 0.301167, 0.860107",\
+ "0.025202, 0.034115, 0.048746, 0.301167, 0.860107",\
+ "0.025205, 0.034118, 0.048746, 0.301166, 0.860107",\
+ "0.025221, 0.034136, 0.048767, 0.301165, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.211928, 0.232331, 0.268319, 0.674047, 1.564311",\
+ "0.300343, 0.320746, 0.356735, 0.762463, 1.652727",\
+ "0.394726, 0.415129, 0.451117, 0.856845, 1.747110",\
+ "0.462784, 0.483187, 0.519176, 0.924904, 1.815168",\
+ "0.787427, 0.807827, 0.843815, 1.249543, 2.139807");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041723, 0.070068, 0.126730, 0.849961, 2.447344",\
+ "0.041723, 0.070068, 0.126730, 0.849961, 2.447344",\
+ "0.041723, 0.070068, 0.126730, 0.849961, 2.447344",\
+ "0.041723, 0.070068, 0.126730, 0.849961, 2.447345",\
+ "0.041728, 0.070061, 0.126728, 0.849959, 2.447347");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.181588, 0.192225, 0.206333, 0.346656, 0.651742",\
+ "0.266400, 0.277038, 0.291146, 0.431469, 0.736554",\
+ "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\
+ "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\
+ "0.681430, 0.692081, 0.706196, 0.846525, 1.151605");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\
+ "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\
+ "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\
+ "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\
+ "0.024132, 0.032784, 0.047567, 0.299569, 0.856157");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[2]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[2] */
+
+pin("usb_io_pu_cal_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\
+ "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\
+ "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\
+ "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\
+ "0.851113, 0.872490, 0.908724, 1.313410, 2.205313");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044601, 0.070181, 0.128220, 0.852056, 2.450126",\
+ "0.044663, 0.070181, 0.128220, 0.852056, 2.450126",\
+ "0.044669, 0.070181, 0.128220, 0.852056, 2.450126",\
+ "0.044669, 0.070181, 0.128220, 0.852056, 2.450126",\
+ "0.046118, 0.071698, 0.128220, 0.852061, 2.450126");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\
+ "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\
+ "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\
+ "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\
+ "0.837901, 0.847639, 0.861421, 1.000178, 1.306080");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025212, 0.034126, 0.048744, 0.301166, 0.860107",\
+ "0.025213, 0.034127, 0.048744, 0.301166, 0.860107",\
+ "0.025216, 0.034130, 0.048746, 0.301165, 0.860107",\
+ "0.025218, 0.034133, 0.048746, 0.301165, 0.860107",\
+ "0.025235, 0.034151, 0.048767, 0.301164, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\
+ "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\
+ "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\
+ "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\
+ "0.763219, 0.783617, 0.819604, 1.225332, 2.115596");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\
+ "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\
+ "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\
+ "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\
+ "0.041728, 0.070054, 0.126726, 0.849959, 2.447349");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.175899, 0.186544, 0.200656, 0.340982, 0.646065",\
+ "0.263271, 0.273916, 0.288028, 0.428355, 0.733437",\
+ "0.344128, 0.354771, 0.368883, 0.509209, 0.814291",\
+ "0.401818, 0.412460, 0.426571, 0.566896, 0.871980",\
+ "0.705550, 0.716209, 0.730328, 0.870660, 1.175736");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\
+ "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\
+ "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\
+ "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\
+ "0.024132, 0.032784, 0.047574, 0.299569, 0.856133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[1]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[1] */
+
+pin("usb_io_pu_cal_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044612 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_io_pu_cal_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\
+ "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\
+ "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\
+ "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\
+ "0.851113, 0.872490, 0.908724, 1.313410, 2.205313");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\
+ "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\
+ "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\
+ "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\
+ "0.044688, 0.070187, 0.128220, 0.852056, 2.450126");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\
+ "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\
+ "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\
+ "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\
+ "0.837901, 0.847639, 0.861421, 1.000178, 1.306080");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.025212, 0.034126, 0.048744, 0.301166, 0.860107",\
+ "0.025212, 0.034126, 0.048744, 0.301166, 0.860107",\
+ "0.025216, 0.034130, 0.048746, 0.301165, 0.860107",\
+ "0.025218, 0.034133, 0.048746, 0.301165, 0.860107",\
+ "0.025235, 0.034151, 0.048767, 0.301164, 0.860107");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.253595, 0.273995, 0.309982, 0.715710, 1.605975",\
+ "0.340966, 0.361366, 0.397353, 0.803081, 1.693346",\
+ "0.421845, 0.442245, 0.478233, 0.883961, 1.774225",\
+ "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\
+ "0.763219, 0.783617, 0.819604, 1.225332, 2.115596");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\
+ "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\
+ "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\
+ "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\
+ "0.041728, 0.070054, 0.126726, 0.849959, 2.447349");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.187072, 0.197718, 0.211831, 0.352158, 0.657240",\
+ "0.275510, 0.286157, 0.300270, 0.440597, 0.745678",\
+ "0.366248, 0.376893, 0.391005, 0.531331, 0.836413",\
+ "0.431562, 0.442205, 0.456315, 0.596641, 0.901724",\
+ "0.774613, 0.785269, 0.799387, 0.939719, 1.244796");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612");
+ values ( "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\
+ "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\
+ "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\
+ "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\
+ "0.024132, 0.032784, 0.047572, 0.299569, 0.856139");
+ }
+
+ } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[0]_redg_min*/
+
+} /* end of pin usb_io_pu_cal_o[0] */
+} /* end of bus usb_io_pu_cal_o */
+
+pin("adc_pd_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000990 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_pd_i;
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.145974, 0.070413, 0.002322, -0.008532, 0.040411",\
+ "0.237817, 0.162519, 0.094482, 0.084652, 0.136438",\
+ "0.327313, 0.252083, 0.184412, 0.176262, 0.232381",\
+ "0.476369, 0.401228, 0.333138, 0.324719, 0.380566",\
+ "0.727129, 0.652156, 0.582810, 0.572596, 0.624823");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.143537, 0.097803, 0.067619, 0.059035, 0.070038",\
+ "0.237266, 0.190708, 0.160460, 0.151771, 0.162549",\
+ "0.329371, 0.281569, 0.251215, 0.242361, 0.252794",\
+ "0.482853, 0.435010, 0.403977, 0.394743, 0.404895",\
+ "0.739407, 0.691484, 0.659103, 0.649115, 0.658707");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_pd_i_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.059104, 0.006478, 0.063764, 0.149867, 0.326932",\
+ "-0.151184, -0.084885, -0.026675, 0.059343, 0.235088",\
+ "-0.241063, -0.173618, -0.113766, -0.027872, 0.145596",\
+ "-0.389953, -0.320592, -0.259252, -0.172562, 0.001425",\
+ "-0.640054, -0.566890, -0.503114, -0.414430, -0.237640");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.075633, -0.033180, 0.001225, 0.107355, 0.367997",\
+ "-0.168712, -0.126409, -0.091657, -0.008939, 0.184913",\
+ "-0.259774, -0.217681, -0.182405, -0.135026, -0.041991",\
+ "-0.408979, -0.365800, -0.330498, -0.282705, -0.188522",\
+ "-0.657040, -0.611703, -0.576351, -0.527733, -0.431269");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_pd_i_hldr*/
+
+} /* end of pin adc_pd_i */
+
+pin("adc_a0_ai") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_a0_ai;
+} /* end of pin adc_a0_ai */
+
+pin("adc_a1_ai") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_a1_ai;
+} /* end of pin adc_a1_ai */
+bus ( adc_chnsel_i ) {
+
+ bus_type : BUS2_type5 ;
+ direction : input ;
+
+pin("adc_chnsel_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000460 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_chnsel_i[1];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.500117, 0.461902, 0.438325, 0.435047, 0.453355",\
+ "0.595615, 0.557400, 0.533823, 0.530545, 0.548853",\
+ "0.695525, 0.657310, 0.633733, 0.630455, 0.648763",\
+ "0.875461, 0.837246, 0.813669, 0.810391, 0.828699",\
+ "1.191947, 1.153731, 1.130154, 1.126876, 1.145184");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.605397, 0.537315, 0.507057, 0.526616, 0.751141",\
+ "0.681420, 0.613337, 0.583080, 0.602638, 0.827164",\
+ "0.783637, 0.715554, 0.685297, 0.704855, 0.929381",\
+ "0.996963, 0.928735, 0.898477, 0.918181, 1.142707",\
+ "1.384407, 1.315680, 1.285422, 1.305625, 1.530151");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_chnsel_i[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.108536, -0.069519, -0.039211, 0.000204, 0.221057",\
+ "-0.207833, -0.168834, -0.138446, -0.098987, 0.125559",\
+ "-0.311546, -0.272599, -0.241997, -0.202419, 0.025649",\
+ "-0.492274, -0.453433, -0.422380, -0.382553, -0.154287",\
+ "-0.791907, -0.753246, -0.721402, -0.681127, -0.470772");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.305777, -0.243225, -0.192080, -0.118367, 0.030759",\
+ "-0.381816, -0.319265, -0.268119, -0.194406, -0.045281",\
+ "-0.483977, -0.421325, -0.370075, -0.296389, -0.147462",\
+ "-0.695975, -0.632864, -0.581137, -0.507574, -0.359554",\
+ "-1.082510, -1.018340, -0.965517, -0.892237, -0.746305");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_chnsel_i[1]_hldr*/
+
+} /* end of pin adc_chnsel_i[1] */
+
+pin("adc_chnsel_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000438 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_chnsel_i[0];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.501910, 0.463695, 0.440118, 0.436840, 0.455148",\
+ "0.598688, 0.560473, 0.536896, 0.533618, 0.551926",\
+ "0.702673, 0.664458, 0.640881, 0.637603, 0.655911",\
+ "0.888472, 0.850257, 0.826680, 0.823402, 0.841710",\
+ "1.218538, 1.180323, 1.156746, 1.153468, 1.171776");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.606473, 0.538391, 0.508134, 0.527691, 0.752217",\
+ "0.684191, 0.616110, 0.585852, 0.605410, 0.829935",\
+ "0.780333, 0.712252, 0.681994, 0.701552, 0.926077",\
+ "0.980044, 0.911864, 0.881606, 0.901262, 1.125788",\
+ "1.359676, 1.291175, 1.260918, 1.280894, 1.505420");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_chnsel_i[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.110705, -0.071690, -0.041374, -0.001954, 0.219264",\
+ "-0.211096, -0.172099, -0.141707, -0.102245, 0.122486",\
+ "-0.318758, -0.279812, -0.249205, -0.209624, 0.018501",\
+ "-0.505427, -0.466584, -0.435539, -0.395715, -0.167298",\
+ "-0.819228, -0.780572, -0.748725, -0.708453, -0.497364");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.306862, -0.244315, -0.193173, -0.119459, 0.029674",\
+ "-0.384597, -0.322050, -0.270908, -0.197194, -0.048061",\
+ "-0.480694, -0.418072, -0.366852, -0.293158, -0.144173",\
+ "-0.679326, -0.616367, -0.564798, -0.491194, -0.342874",\
+ "-1.058081, -0.994264, -0.941806, -0.868432, -0.721804");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_chnsel_i[0]_hldr*/
+
+} /* end of pin adc_chnsel_i[0] */
+} /* end of bus adc_chnsel_i */
+bus ( adc_d_o ) {
+
+ bus_type : BUS10_type8 ;
+ direction : output ;
+
+pin("adc_d_o[9]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[9];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[9]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[9]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[9]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[9]_hldr*/
+
+} /* end of pin adc_d_o[9] */
+
+pin("adc_d_o[8]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[8];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[8]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[8]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[8]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[8]_hldr*/
+
+} /* end of pin adc_d_o[8] */
+
+pin("adc_d_o[7]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[7];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[7]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[7]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[7]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[7]_hldr*/
+
+} /* end of pin adc_d_o[7] */
+
+pin("adc_d_o[6]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[6];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[6]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[6]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[6]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[6]_hldr*/
+
+} /* end of pin adc_d_o[6] */
+
+pin("adc_d_o[5]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[5];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[5]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[5]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[5]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[5]_hldr*/
+
+} /* end of pin adc_d_o[5] */
+
+pin("adc_d_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[4];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[4]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[4]_hldr*/
+
+} /* end of pin adc_d_o[4] */
+
+pin("adc_d_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[3];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[3]_hldr*/
+
+} /* end of pin adc_d_o[3] */
+
+pin("adc_d_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[2];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[2]_hldr*/
+
+} /* end of pin adc_d_o[2] */
+
+pin("adc_d_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[1];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[1]_hldr*/
+
+} /* end of pin adc_d_o[1] */
+
+pin("adc_d_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000474 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_o[0];
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\
+ "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\
+ "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\
+ "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\
+ "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\
+ "0.042630, 0.188229, 0.385715, 0.758292, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\
+ "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\
+ "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\
+ "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\
+ "0.557160, 0.787678, 0.963834, 1.284789, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\
+ "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\
+ "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\
+ "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\
+ "0.122287, 0.339635, 0.636985, 1.249173, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\
+ "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\
+ "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\
+ "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\
+ "0.578145, 0.699559, 0.811451, 1.015162, 1.422583");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011");
+ values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\
+ "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\
+ "0.042630, 0.188229, 0.384226, 0.757731, 1.504742");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\
+ "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\
+ "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\
+ "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\
+ "0.789608, 0.741801, 0.711356, 0.702451, 0.712846");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\
+ "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\
+ "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\
+ "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\
+ "0.906305, 0.831103, 0.763471, 0.755707, 0.812875");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\
+ "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\
+ "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\
+ "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\
+ "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\
+ "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\
+ "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\
+ "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\
+ "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_o[0]_hldr*/
+
+} /* end of pin adc_d_o[0] */
+} /* end of bus adc_d_o */
+
+pin("adc_d_val_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000485 ;
+
+ /* Other user defined attributes. */
+ original_pin : adc_d_val_o;
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011");
+ values ( "0.043124, 0.198142, 0.374272, 0.697796, 1.344843",\
+ "0.128968, 0.285317, 0.461380, 0.784513, 1.430777",\
+ "0.210336, 0.373448, 0.549338, 0.872136, 1.517732",\
+ "0.345497, 0.527907, 0.703118, 1.025430, 1.670053",\
+ "0.557318, 0.787701, 0.963851, 1.284800, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011");
+ values ( "0.018442, 0.293953, 0.628634, 1.246610, 2.482563",\
+ "0.023559, 0.294907, 0.630604, 1.246610, 2.482563",\
+ "0.036948, 0.297215, 0.630640, 1.246610, 2.482563",\
+ "0.064957, 0.305264, 0.630873, 1.247249, 2.482563",\
+ "0.122341, 0.339671, 0.637017, 1.249194, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011");
+ values ( "0.062980, 0.171026, 0.282963, 0.487563, 0.896764",\
+ "0.150552, 0.258345, 0.370244, 0.574868, 0.984118",\
+ "0.230698, 0.338686, 0.450271, 0.654897, 1.064149",\
+ "0.365964, 0.476710, 0.588288, 0.792197, 1.200014",\
+ "0.578168, 0.699563, 0.811453, 1.015159, 1.422574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011");
+ values ( "0.020581, 0.184004, 0.385209, 0.758288, 1.504444",\
+ "0.020581, 0.184139, 0.385717, 0.758288, 1.504444",\
+ "0.021507, 0.184139, 0.385717, 0.758288, 1.504444",\
+ "0.027064, 0.184695, 0.385717, 0.758288, 1.504725",\
+ "0.042640, 0.188237, 0.385717, 0.758288, 1.504725");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_val_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011");
+ values ( "0.043124, 0.198142, 0.374272, 0.697796, 1.344843",\
+ "0.128968, 0.285317, 0.461380, 0.784513, 1.430777",\
+ "0.210336, 0.373448, 0.549338, 0.872136, 1.517732",\
+ "0.345497, 0.527907, 0.703118, 1.025430, 1.670053",\
+ "0.557318, 0.787701, 0.963851, 1.284800, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011");
+ values ( "0.018442, 0.293953, 0.628634, 1.245396, 2.473548",\
+ "0.023559, 0.294907, 0.630604, 1.245396, 2.473548",\
+ "0.036948, 0.297215, 0.630640, 1.245471, 2.473548",\
+ "0.064957, 0.305264, 0.630873, 1.247249, 2.473548",\
+ "0.122341, 0.339671, 0.637017, 1.249194, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011");
+ values ( "0.062980, 0.171026, 0.282963, 0.487563, 0.896764",\
+ "0.150552, 0.258345, 0.370244, 0.574868, 0.984118",\
+ "0.230698, 0.338686, 0.450271, 0.654897, 1.064149",\
+ "0.365964, 0.476710, 0.588288, 0.792197, 1.200014",\
+ "0.578168, 0.699563, 0.811453, 1.015159, 1.422574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011");
+ values ( "0.020581, 0.183219, 0.383707, 0.756060, 1.500767",\
+ "0.020581, 0.183219, 0.383707, 0.756060, 1.500767",\
+ "0.021507, 0.183219, 0.383707, 0.756060, 1.500767",\
+ "0.027064, 0.184695, 0.384228, 0.757727, 1.504725",\
+ "0.042640, 0.188237, 0.384228, 0.757727, 1.504725");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_val_o_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018442, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.243976, 0.197294, 0.167037, 0.158332, 0.169076",\
+ "0.249724, 0.203042, 0.172784, 0.164080, 0.174823",\
+ "0.330128, 0.283446, 0.253188, 0.244484, 0.255227",\
+ "0.421667, 0.374985, 0.344728, 0.336023, 0.346766",\
+ "0.857546, 0.810300, 0.779998, 0.771221, 0.781810");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020581, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.235882, 0.160549, 0.092329, 0.081659, 0.131277",\
+ "0.241065, 0.165732, 0.097513, 0.086843, 0.136460",\
+ "0.320960, 0.245631, 0.177435, 0.166874, 0.216773",\
+ "0.424142, 0.348830, 0.280724, 0.270576, 0.321539",\
+ "0.869196, 0.793968, 0.726309, 0.718213, 0.774472");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_val_o_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_adc_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.018442, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.172771, -0.130490, -0.095686, -0.016470, 0.167392",\
+ "-0.178433, -0.136153, -0.101349, -0.022133, 0.161730",\
+ "-0.256684, -0.214404, -0.179600, -0.100383, 0.083479",\
+ "-0.345053, -0.302773, -0.267969, -0.188752, -0.004890",\
+ "-0.762797, -0.720612, -0.685586, -0.621349, -0.480218");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020581, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.121789, -0.056140, 0.001137, 0.087226, 0.264264",\
+ "-0.127527, -0.061878, -0.004601, 0.081488, 0.258526",\
+ "-0.211930, -0.146176, -0.088749, -0.002671, 0.174159",\
+ "-0.309060, -0.243056, -0.185270, -0.099220, 0.077113",\
+ "-0.732847, -0.665438, -0.605637, -0.519740, -0.346201");
+ }
+
+ } /* end of arc clk_ast_adc_i_adc_d_val_o_hldr*/
+
+} /* end of pin adc_d_val_o */
+
+pin("rng_en_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : rng_en_i;
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\
+ "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\
+ "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\
+ "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\
+ "0.811131, 0.757315, 0.714144, 0.695925, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\
+ "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\
+ "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\
+ "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\
+ "0.983325, 0.898854, 0.822917, 0.782684, 0.674795");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rng_en_i_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\
+ "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\
+ "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\
+ "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\
+ "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\
+ "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\
+ "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\
+ "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\
+ "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rng_en_i_hldr*/
+
+} /* end of pin rng_en_i */
+
+pin("rng_fips_i") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : rng_fips_i;
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\
+ "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\
+ "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\
+ "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\
+ "0.811131, 0.757315, 0.714144, 0.695925, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\
+ "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\
+ "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\
+ "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\
+ "0.983325, 0.898854, 0.822917, 0.782684, 0.674795");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rng_fips_i_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\
+ "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\
+ "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\
+ "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\
+ "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\
+ "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\
+ "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\
+ "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\
+ "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rng_fips_i_hldr*/
+
+} /* end of pin rng_fips_i */
+
+pin("rng_val_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : rng_val_o;
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.043198, 0.198183, 0.374303, 0.697816, 1.344843",\
+ "0.100770, 0.256465, 0.432811, 0.755524, 1.400950",\
+ "0.234375, 0.400817, 0.576577, 0.899279, 1.544683",\
+ "0.266829, 0.437889, 0.613486, 0.936071, 1.581241",\
+ "0.557607, 0.787741, 0.963881, 1.284820, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.018518, 0.294029, 0.628692, 1.246649, 2.482563",\
+ "0.020629, 0.294660, 0.630087, 1.246649, 2.482563",\
+ "0.041968, 0.298715, 0.630739, 1.246649, 2.482563",\
+ "0.048693, 0.300646, 0.630795, 1.246649, 2.482563",\
+ "0.122440, 0.339737, 0.637074, 1.249232, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.063098, 0.171066, 0.282997, 0.487591, 0.896779",\
+ "0.123042, 0.230894, 0.342842, 0.547360, 0.956396",\
+ "0.254755, 0.363148, 0.474725, 0.679218, 1.088204",\
+ "0.287224, 0.396275, 0.507850, 0.712171, 1.120812",\
+ "0.578369, 0.699604, 0.811487, 1.015187, 1.422589");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.020669, 0.184077, 0.385272, 0.758339, 1.504472",\
+ "0.020669, 0.184227, 0.385542, 0.758386, 1.504472",\
+ "0.022583, 0.184227, 0.385542, 0.758386, 1.504472",\
+ "0.023913, 0.184227, 0.385542, 0.758386, 1.504472",\
+ "0.042731, 0.188308, 0.385542, 0.758386, 1.504752");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_val_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.043198, 0.198183, 0.374303, 0.697816, 1.344843",\
+ "0.100770, 0.256465, 0.432811, 0.755524, 1.400950",\
+ "0.234375, 0.400817, 0.576577, 0.899279, 1.544683",\
+ "0.266829, 0.437889, 0.613486, 0.936071, 1.581241",\
+ "0.557607, 0.787741, 0.963881, 1.284820, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.018518, 0.294029, 0.628692, 1.245563, 2.473548",\
+ "0.020629, 0.294660, 0.630087, 1.245563, 2.473548",\
+ "0.041968, 0.298715, 0.630739, 1.245824, 2.473548",\
+ "0.048693, 0.300646, 0.630795, 1.246251, 2.473548",\
+ "0.122440, 0.339737, 0.637074, 1.249232, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.063098, 0.171066, 0.282997, 0.487591, 0.896779",\
+ "0.123042, 0.230894, 0.342842, 0.547360, 0.956396",\
+ "0.254755, 0.363148, 0.474725, 0.679218, 1.088204",\
+ "0.287224, 0.396275, 0.507850, 0.712171, 1.120812",\
+ "0.578369, 0.699604, 0.811487, 1.015187, 1.422589");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.020669, 0.183553, 0.383962, 0.756493, 1.501555",\
+ "0.020669, 0.183553, 0.383962, 0.756493, 1.501555",\
+ "0.022583, 0.183553, 0.383962, 0.756493, 1.501555",\
+ "0.023913, 0.183907, 0.384224, 0.757011, 1.502586",\
+ "0.042731, 0.188308, 0.384291, 0.757778, 1.504752");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_val_o_redg_min*/
+
+} /* end of pin rng_val_o */
+bus ( rng_b_o ) {
+
+ bus_type : BUS4_type6 ;
+ direction : output ;
+
+pin("rng_b_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001003 ;
+
+ /* Other user defined attributes. */
+ original_pin : rng_b_o[3];
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\
+ "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\
+ "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\
+ "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\
+ "0.564763, 0.788747, 0.964628, 1.285318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\
+ "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\
+ "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\
+ "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\
+ "0.124896, 0.341364, 0.638500, 1.250182, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\
+ "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\
+ "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\
+ "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\
+ "0.581429, 0.700226, 0.811944, 1.015486, 1.422571");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\
+ "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.044109, 0.189380, 0.386379, 0.758933, 1.504720");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_b_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\
+ "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\
+ "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\
+ "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\
+ "0.564763, 0.788747, 0.964628, 1.285318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\
+ "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\
+ "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\
+ "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\
+ "0.124896, 0.341364, 0.638500, 1.250182, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\
+ "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\
+ "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\
+ "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\
+ "0.581429, 0.700226, 0.811944, 1.015486, 1.422571");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\
+ "0.044109, 0.189380, 0.385129, 0.758326, 1.504720");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_b_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_falling ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020388, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.036802, 0.036802, 0.036802, 0.036802, 0.036802",\
+ "0.042346, 0.042346, 0.042346, 0.042346, 0.042346",\
+ "0.109280, 0.109280, 0.109280, 0.109280, 0.109280",\
+ "0.178232, 0.178232, 0.178232, 0.178232, 0.178232",\
+ "0.458063, 0.458063, 0.458063, 0.458063, 0.458063");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022008, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.053733, 0.053733, 0.053733, 0.053733, 0.053733",\
+ "0.060946, 0.060946, 0.060946, 0.060946, 0.060946",\
+ "0.137682, 0.137682, 0.137682, 0.137682, 0.137682",\
+ "0.226588, 0.226588, 0.226588, 0.226588, 0.226588",\
+ "0.644240, 0.644240, 0.644240, 0.644240, 0.644240");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rng_b_o[3]_cgsf*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.020388, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.034468, -0.034468, -0.034468, -0.034468, -0.034468",\
+ "-0.040015, -0.040015, -0.040015, -0.040015, -0.040015",\
+ "-0.106260, -0.106260, -0.106260, -0.106260, -0.106260",\
+ "-0.173208, -0.173208, -0.173208, -0.173208, -0.173208",\
+ "-0.445027, -0.445027, -0.445027, -0.445027, -0.445027");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022008, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.046633, -0.046633, -0.046633, -0.046633, -0.046633",\
+ "-0.053872, -0.053872, -0.053872, -0.053872, -0.053872",\
+ "-0.131912, -0.131912, -0.131912, -0.131912, -0.131912",\
+ "-0.220120, -0.220120, -0.220120, -0.220120, -0.220120",\
+ "-0.629632, -0.629632, -0.629632, -0.629632, -0.629632");
+ }
+
+ } /* end of arc clk_ast_tlul_i_rng_b_o[3]_cghr*/
+
+} /* end of pin rng_b_o[3] */
+
+pin("rng_b_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001003 ;
+
+ /* Other user defined attributes. */
+ original_pin : rng_b_o[2];
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\
+ "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\
+ "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\
+ "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\
+ "0.564763, 0.788747, 0.964628, 1.285318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\
+ "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\
+ "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\
+ "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\
+ "0.124896, 0.341364, 0.638500, 1.250182, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\
+ "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\
+ "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\
+ "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\
+ "0.581429, 0.700226, 0.811944, 1.015486, 1.422571");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\
+ "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.044109, 0.189380, 0.386379, 0.758933, 1.504720");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_b_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\
+ "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\
+ "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\
+ "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\
+ "0.564763, 0.788747, 0.964628, 1.285318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\
+ "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\
+ "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\
+ "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\
+ "0.124896, 0.341364, 0.638500, 1.250182, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\
+ "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\
+ "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\
+ "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\
+ "0.581429, 0.700226, 0.811944, 1.015486, 1.422571");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\
+ "0.044109, 0.189380, 0.385129, 0.758326, 1.504720");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_b_o[2]_redg_min*/
+
+} /* end of pin rng_b_o[2] */
+
+pin("rng_b_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001003 ;
+
+ /* Other user defined attributes. */
+ original_pin : rng_b_o[1];
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\
+ "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\
+ "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\
+ "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\
+ "0.564763, 0.788747, 0.964628, 1.285318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\
+ "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\
+ "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\
+ "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\
+ "0.124896, 0.341364, 0.638500, 1.250182, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\
+ "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\
+ "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\
+ "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\
+ "0.581429, 0.700226, 0.811944, 1.015486, 1.422571");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\
+ "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.044109, 0.189380, 0.386379, 0.758933, 1.504720");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_b_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\
+ "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\
+ "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\
+ "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\
+ "0.564763, 0.788747, 0.964628, 1.285318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\
+ "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\
+ "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\
+ "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\
+ "0.124896, 0.341364, 0.638500, 1.250182, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\
+ "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\
+ "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\
+ "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\
+ "0.581429, 0.700226, 0.811944, 1.015486, 1.422571");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\
+ "0.044109, 0.189380, 0.385129, 0.758326, 1.504720");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_b_o[1]_redg_min*/
+
+} /* end of pin rng_b_o[1] */
+
+pin("rng_b_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001003 ;
+
+ /* Other user defined attributes. */
+ original_pin : rng_b_o[0];
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\
+ "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\
+ "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\
+ "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\
+ "0.564763, 0.788747, 0.964628, 1.285318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\
+ "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\
+ "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\
+ "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\
+ "0.124896, 0.341364, 0.638500, 1.250182, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\
+ "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\
+ "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\
+ "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\
+ "0.581429, 0.700226, 0.811944, 1.015486, 1.422571");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\
+ "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\
+ "0.044109, 0.189380, 0.386379, 0.758933, 1.504720");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_b_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\
+ "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\
+ "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\
+ "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\
+ "0.564763, 0.788747, 0.964628, 1.285318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\
+ "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\
+ "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\
+ "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\
+ "0.124896, 0.341364, 0.638500, 1.250182, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\
+ "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\
+ "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\
+ "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\
+ "0.581429, 0.700226, 0.811944, 1.015486, 1.422571");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\
+ "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\
+ "0.044109, 0.189380, 0.385129, 0.758326, 1.504720");
+ }
+
+ } /* end of arc clk_ast_rng_i_rng_b_o[0]_redg_min*/
+
+} /* end of pin rng_b_o[0] */
+} /* end of bus rng_b_o */
+bus ( entropy_rsp_i ) {
+
+ bus_type : BUS34_type9 ;
+ direction : input ;
+
+pin("entropy_rsp_i[33]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001563 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[33];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "1.119801, 1.062115, 1.000165, 1.001253, 1.020223",\
+ "1.200891, 1.143205, 1.081255, 1.082343, 1.101313",\
+ "1.316914, 1.259228, 1.197278, 1.198366, 1.217336",\
+ "1.518457, 1.460771, 1.398821, 1.399909, 1.418879",\
+ "1.859802, 1.802116, 1.740050, 1.741138, 1.760224");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.903123, 0.863686, 0.813020, 0.814108, 0.827330",\
+ "1.003527, 0.964090, 0.913424, 0.914512, 0.927734",\
+ "1.127836, 1.088399, 1.037733, 1.038821, 1.052043",\
+ "1.347378, 1.307941, 1.257275, 1.258363, 1.271584",\
+ "1.738717, 1.699280, 1.648614, 1.649702, 1.662924");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[33]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.168954, -0.118035, -0.021877, -0.003703, 0.217154",\
+ "-0.249369, -0.198449, -0.102291, -0.084118, 0.136740",\
+ "-0.329424, -0.278473, -0.182197, -0.164034, 0.056702",\
+ "-0.457832, -0.406830, -0.310356, -0.292210, -0.071679",\
+ "-0.639075, -0.587937, -0.490944, -0.472842, -0.252849");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.139897, -0.089049, 0.006833, 0.025029, 0.246173",\
+ "-0.240100, -0.189184, -0.093041, -0.074866, 0.146007",\
+ "-0.358064, -0.306668, -0.208689, -0.190671, 0.057939",\
+ "-0.516949, -0.483468, -0.393287, -0.375391, -0.096605",\
+ "-0.756377, -0.722936, -0.665170, -0.641259, -0.350671");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[33]_hldr*/
+
+} /* end of pin entropy_rsp_i[33] */
+
+pin("entropy_rsp_i[32]") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[32];
+} /* end of pin entropy_rsp_i[32] */
+
+pin("entropy_rsp_i[31]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[31];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[31]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[31]_hldr*/
+
+} /* end of pin entropy_rsp_i[31] */
+
+pin("entropy_rsp_i[30]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[30];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[30]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[30]_hldr*/
+
+} /* end of pin entropy_rsp_i[30] */
+
+pin("entropy_rsp_i[29]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[29];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[29]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[29]_hldr*/
+
+} /* end of pin entropy_rsp_i[29] */
+
+pin("entropy_rsp_i[28]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[28];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[28]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[28]_hldr*/
+
+} /* end of pin entropy_rsp_i[28] */
+
+pin("entropy_rsp_i[27]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[27];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[27]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[27]_hldr*/
+
+} /* end of pin entropy_rsp_i[27] */
+
+pin("entropy_rsp_i[26]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[26];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[26]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[26]_hldr*/
+
+} /* end of pin entropy_rsp_i[26] */
+
+pin("entropy_rsp_i[25]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[25];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[25]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[25]_hldr*/
+
+} /* end of pin entropy_rsp_i[25] */
+
+pin("entropy_rsp_i[24]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[24];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[24]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[24]_hldr*/
+
+} /* end of pin entropy_rsp_i[24] */
+
+pin("entropy_rsp_i[23]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[23];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[23]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[23]_hldr*/
+
+} /* end of pin entropy_rsp_i[23] */
+
+pin("entropy_rsp_i[22]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[22];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[22]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[22]_hldr*/
+
+} /* end of pin entropy_rsp_i[22] */
+
+pin("entropy_rsp_i[21]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[21];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[21]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[21]_hldr*/
+
+} /* end of pin entropy_rsp_i[21] */
+
+pin("entropy_rsp_i[20]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[20];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[20]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[20]_hldr*/
+
+} /* end of pin entropy_rsp_i[20] */
+
+pin("entropy_rsp_i[19]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[19];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[19]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[19]_hldr*/
+
+} /* end of pin entropy_rsp_i[19] */
+
+pin("entropy_rsp_i[18]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[18];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[18]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[18]_hldr*/
+
+} /* end of pin entropy_rsp_i[18] */
+
+pin("entropy_rsp_i[17]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[17];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[17]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[17]_hldr*/
+
+} /* end of pin entropy_rsp_i[17] */
+
+pin("entropy_rsp_i[16]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[16];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[16]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[16]_hldr*/
+
+} /* end of pin entropy_rsp_i[16] */
+
+pin("entropy_rsp_i[15]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[15];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[15]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[15]_hldr*/
+
+} /* end of pin entropy_rsp_i[15] */
+
+pin("entropy_rsp_i[14]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[14];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[14]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[14]_hldr*/
+
+} /* end of pin entropy_rsp_i[14] */
+
+pin("entropy_rsp_i[13]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[13];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[13]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[13]_hldr*/
+
+} /* end of pin entropy_rsp_i[13] */
+
+pin("entropy_rsp_i[12]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[12];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[12]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[12]_hldr*/
+
+} /* end of pin entropy_rsp_i[12] */
+
+pin("entropy_rsp_i[11]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[11];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[11]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[11]_hldr*/
+
+} /* end of pin entropy_rsp_i[11] */
+
+pin("entropy_rsp_i[10]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[10];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[10]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[10]_hldr*/
+
+} /* end of pin entropy_rsp_i[10] */
+
+pin("entropy_rsp_i[9]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[9];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[9]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[9]_hldr*/
+
+} /* end of pin entropy_rsp_i[9] */
+
+pin("entropy_rsp_i[8]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[8];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[8]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[8]_hldr*/
+
+} /* end of pin entropy_rsp_i[8] */
+
+pin("entropy_rsp_i[7]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[7];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[7]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[7]_hldr*/
+
+} /* end of pin entropy_rsp_i[7] */
+
+pin("entropy_rsp_i[6]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[6];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[6]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[6]_hldr*/
+
+} /* end of pin entropy_rsp_i[6] */
+
+pin("entropy_rsp_i[5]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[5];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[5]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[5]_hldr*/
+
+} /* end of pin entropy_rsp_i[5] */
+
+pin("entropy_rsp_i[4]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[4];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[4]_hldr*/
+
+} /* end of pin entropy_rsp_i[4] */
+
+pin("entropy_rsp_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[3];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[3]_hldr*/
+
+} /* end of pin entropy_rsp_i[3] */
+
+pin("entropy_rsp_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[2];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[2]_hldr*/
+
+} /* end of pin entropy_rsp_i[2] */
+
+pin("entropy_rsp_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[1];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[1]_hldr*/
+
+} /* end of pin entropy_rsp_i[1] */
+
+pin("entropy_rsp_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001123 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_rsp_i[0];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\
+ "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\
+ "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\
+ "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\
+ "0.818496, 0.778874, 0.728184, 0.729266, 0.742423");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\
+ "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\
+ "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\
+ "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\
+ "0.940670, 0.882965, 0.769819, 0.775584, 0.845650");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\
+ "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\
+ "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\
+ "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\
+ "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\
+ "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\
+ "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\
+ "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\
+ "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_rsp_i[0]_hldr*/
+
+} /* end of pin entropy_rsp_i[0] */
+} /* end of bus entropy_rsp_i */
+bus ( entropy_req_o ) {
+
+ bus_type : BUS1_type10 ;
+ direction : output ;
+
+pin("entropy_req_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : entropy_req_o[0];
+ timing () {
+ related_pin : "clk_ast_es_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011");
+ values ( "0.041147, 0.197164, 0.373538, 0.697306, 1.344843",\
+ "0.098611, 0.255444, 0.432048, 0.755015, 1.400950",\
+ "0.230794, 0.399801, 0.575814, 0.898771, 1.544683",\
+ "0.262809, 0.436873, 0.612723, 0.935562, 1.581241",\
+ "0.549011, 0.786720, 0.963122, 1.284314, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011");
+ values ( "0.016407, 0.292097, 0.627231, 1.245675, 2.482563",\
+ "0.018818, 0.292719, 0.628632, 1.245675, 2.482563",\
+ "0.040240, 0.296800, 0.629285, 1.245675, 2.482563",\
+ "0.046879, 0.298746, 0.629340, 1.245675, 2.482563",\
+ "0.119467, 0.338085, 0.635627, 1.248267, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011");
+ values ( "0.061012, 0.170429, 0.282525, 0.487280, 0.896790",\
+ "0.121003, 0.230257, 0.342370, 0.547049, 0.956407",\
+ "0.252523, 0.362513, 0.474253, 0.678907, 1.088215",\
+ "0.284909, 0.395640, 0.507378, 0.711860, 1.120823",\
+ "0.574684, 0.698966, 0.811016, 1.014877, 1.422600");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011");
+ values ( "0.018854, 0.182937, 0.384410, 0.757771, 1.504492",\
+ "0.018854, 0.183085, 0.384681, 0.757818, 1.504492",\
+ "0.021110, 0.183085, 0.384681, 0.757818, 1.504492",\
+ "0.022486, 0.183085, 0.384681, 0.757818, 1.504492",\
+ "0.041128, 0.187207, 0.384681, 0.757818, 1.504772");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_req_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_es_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011");
+ values ( "0.041147, 0.197164, 0.373538, 0.697306, 1.344843",\
+ "0.098611, 0.255444, 0.432048, 0.755015, 1.400950",\
+ "0.230794, 0.399801, 0.575814, 0.898771, 1.544683",\
+ "0.262809, 0.436873, 0.612723, 0.935562, 1.581241",\
+ "0.549011, 0.786720, 0.963122, 1.284314, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011");
+ values ( "0.016407, 0.292097, 0.627231, 1.244593, 2.473548",\
+ "0.018818, 0.292719, 0.628632, 1.244593, 2.473548",\
+ "0.040240, 0.296800, 0.629285, 1.244855, 2.473548",\
+ "0.046879, 0.298746, 0.629340, 1.245281, 2.473548",\
+ "0.119467, 0.338085, 0.635627, 1.248267, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011");
+ values ( "0.061012, 0.170429, 0.282525, 0.487280, 0.896790",\
+ "0.121003, 0.230257, 0.342370, 0.547049, 0.956407",\
+ "0.252523, 0.362513, 0.474253, 0.678907, 1.088215",\
+ "0.284909, 0.395640, 0.507378, 0.711860, 1.120823",\
+ "0.574684, 0.698966, 0.811016, 1.014877, 1.422600");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011");
+ values ( "0.018854, 0.182418, 0.383102, 0.755926, 1.501575",\
+ "0.018854, 0.182418, 0.383102, 0.755926, 1.501575",\
+ "0.021110, 0.182418, 0.383102, 0.755926, 1.501575",\
+ "0.022486, 0.182773, 0.383362, 0.756444, 1.502606",\
+ "0.041128, 0.187207, 0.383428, 0.757210, 1.504772");
+ }
+
+ } /* end of arc clk_ast_es_i_entropy_req_o[0]_redg_min*/
+
+} /* end of pin entropy_req_o[0] */
+} /* end of bus entropy_req_o */
+bus ( fla_alert_src_i ) {
+
+ bus_type : BUS2_type5 ;
+ direction : input ;
+
+pin("fla_alert_src_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000977 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_alert_src_i[1];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.160061, 0.122171, 0.071764, 0.072890, 0.086576",\
+ "0.244155, 0.206260, 0.155798, 0.156930, 0.170689",\
+ "0.325133, 0.287001, 0.236508, 0.237633, 0.251310",\
+ "0.464429, 0.425692, 0.375119, 0.376227, 0.389693",\
+ "0.687556, 0.647617, 0.596849, 0.597922, 0.610956");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.188609, 0.130944, 0.016876, 0.021970, 0.083878",\
+ "0.276270, 0.218603, 0.104578, 0.109703, 0.171989",\
+ "0.365048, 0.307375, 0.193490, 0.198718, 0.262247",\
+ "0.519717, 0.462029, 0.348488, 0.353966, 0.420536",\
+ "0.771986, 0.714301, 0.601221, 0.607099, 0.678536");
+ }
+
+ } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.092219, -0.058653, -0.001237, 0.026220, 0.359896",\
+ "-0.176268, -0.142720, -0.085214, -0.058223, 0.269794",\
+ "-0.257056, -0.223577, -0.165901, -0.140924, 0.162616",\
+ "-0.395865, -0.362566, -0.304455, -0.284621, -0.043580",\
+ "-0.617889, -0.584914, -0.525934, -0.516364, -0.400062");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.101777, -0.050927, 0.044966, 0.063162, 0.284294",\
+ "-0.189465, -0.138565, -0.042479, -0.024300, 0.196634",\
+ "-0.278331, -0.227265, -0.130550, -0.112424, 0.107856",\
+ "-0.433215, -0.381745, -0.283488, -0.265494, -0.046811",\
+ "-0.685809, -0.633481, -0.532401, -0.514612, -0.298423");
+ }
+
+ } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_hldr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : recovery_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.346181, 0.303572, 0.245705, 0.249110, 0.290489",\
+ "0.442377, 0.399789, 0.341790, 0.345163, 0.386153",\
+ "0.570076, 0.527583, 0.468994, 0.472224, 0.511474",\
+ "0.816390, 0.774143, 0.714024, 0.716882, 0.751614",\
+ "1.243561, 1.201654, 1.139151, 1.141470, 1.169661");
+ }
+
+ } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_recfr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : removal_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.258352, -0.220900, -0.161340, -0.151153, -0.027357",\
+ "-0.354483, -0.317000, -0.257562, -0.247380, -0.123649",\
+ "-0.481891, -0.444270, -0.385376, -0.375219, -0.251777",\
+ "-0.727449, -0.689470, -0.631990, -0.621894, -0.499204",\
+ "-1.152401, -1.113697, -1.058374, -1.048432, -0.927596");
+ }
+
+ } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_remfr*/
+
+} /* end of pin fla_alert_src_i[1] */
+
+pin("fla_alert_src_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001210 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_alert_src_i[0];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.153898, 0.096234, -0.017862, -0.012789, 0.048865",\
+ "0.234547, 0.176873, 0.063006, 0.068247, 0.131938",\
+ "0.312922, 0.255231, 0.141780, 0.147323, 0.214693",\
+ "0.443628, 0.385987, 0.272716, 0.278561, 0.349586",\
+ "0.643976, 0.586670, 0.471971, 0.477562, 0.545510");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.135497, 0.097521, 0.047194, 0.048307, 0.061839",\
+ "0.227162, 0.188584, 0.138031, 0.139144, 0.152665",\
+ "0.314547, 0.274830, 0.224128, 0.225207, 0.238331",\
+ "0.459106, 0.419271, 0.367632, 0.368682, 0.381446",\
+ "0.699539, 0.659946, 0.606277, 0.607276, 0.619410");
+ }
+
+ } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.067048, -0.016232, 0.079533, 0.097739, 0.319005",\
+ "-0.147841, -0.096754, 0.000043, 0.018162, 0.238358",\
+ "-0.226477, -0.174901, -0.076238, -0.058278, 0.159985",\
+ "-0.357390, -0.304774, -0.203323, -0.185507, 0.031000",\
+ "-0.557290, -0.502515, -0.398294, -0.380283, -0.161393");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.067653, -0.034085, 0.023249, 0.050680, 0.384046",\
+ "-0.158725, -0.125379, -0.067382, -0.046199, 0.211248",\
+ "-0.245194, -0.212186, -0.153370, -0.141879, -0.002219",\
+ "-0.386154, -0.352349, -0.293338, -0.283677, -0.166272",\
+ "-0.618941, -0.583206, -0.524120, -0.514248, -0.394277");
+ }
+
+ } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_hldr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.348301, 0.305676, 0.248104, 0.251583, 0.293858",\
+ "0.429286, 0.386661, 0.329089, 0.332567, 0.374842",\
+ "0.504635, 0.462011, 0.404396, 0.407864, 0.450008",\
+ "0.638699, 0.596084, 0.538251, 0.541665, 0.583146",\
+ "0.863013, 0.820471, 0.762185, 0.765489, 0.805634");
+ }
+
+ } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.260501, -0.223062, -0.163229, -0.153056, -0.029425",\
+ "-0.341485, -0.304046, -0.244213, -0.234040, -0.110409",\
+ "-0.416836, -0.379397, -0.319604, -0.309428, -0.185759",\
+ "-0.550887, -0.513443, -0.453851, -0.443663, -0.319850",\
+ "-0.774977, -0.737427, -0.678253, -0.668084, -0.544492");
+ }
+
+ } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_remrr*/
+
+} /* end of pin fla_alert_src_i[0] */
+} /* end of bus fla_alert_src_i */
+bus ( otp_alert_src_i ) {
+
+ bus_type : BUS2_type5 ;
+ direction : input ;
+
+pin("otp_alert_src_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000977 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_alert_src_i[1];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.160061, 0.122171, 0.071764, 0.072890, 0.086576",\
+ "0.244155, 0.206260, 0.155798, 0.156930, 0.170689",\
+ "0.325133, 0.287001, 0.236508, 0.237633, 0.251310",\
+ "0.464429, 0.425692, 0.375119, 0.376227, 0.389693",\
+ "0.687556, 0.647617, 0.596849, 0.597922, 0.610956");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.188609, 0.130944, 0.016876, 0.021970, 0.083878",\
+ "0.276270, 0.218603, 0.104578, 0.109703, 0.171989",\
+ "0.365048, 0.307375, 0.193490, 0.198718, 0.262247",\
+ "0.519717, 0.462029, 0.348488, 0.353966, 0.420536",\
+ "0.771986, 0.714301, 0.601221, 0.607099, 0.678536");
+ }
+
+ } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.092219, -0.058653, -0.001237, 0.026220, 0.359896",\
+ "-0.176268, -0.142720, -0.085214, -0.058223, 0.269794",\
+ "-0.257056, -0.223577, -0.165901, -0.140924, 0.162616",\
+ "-0.395865, -0.362566, -0.304455, -0.284621, -0.043580",\
+ "-0.617889, -0.584914, -0.525934, -0.516364, -0.400062");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.101777, -0.050927, 0.044966, 0.063162, 0.284294",\
+ "-0.189465, -0.138565, -0.042479, -0.024300, 0.196634",\
+ "-0.278331, -0.227265, -0.130550, -0.112424, 0.107856",\
+ "-0.433215, -0.381745, -0.283488, -0.265494, -0.046811",\
+ "-0.685809, -0.633481, -0.532401, -0.514612, -0.298423");
+ }
+
+ } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_hldr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : recovery_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.346181, 0.303572, 0.245705, 0.249110, 0.290489",\
+ "0.442377, 0.399789, 0.341790, 0.345163, 0.386153",\
+ "0.570076, 0.527583, 0.468994, 0.472224, 0.511474",\
+ "0.816390, 0.774143, 0.714024, 0.716882, 0.751614",\
+ "1.243561, 1.201654, 1.139151, 1.141470, 1.169661");
+ }
+
+ } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_recfr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : removal_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.258352, -0.220900, -0.161340, -0.151153, -0.027357",\
+ "-0.354483, -0.317000, -0.257562, -0.247380, -0.123649",\
+ "-0.481891, -0.444270, -0.385376, -0.375219, -0.251777",\
+ "-0.727449, -0.689470, -0.631990, -0.621894, -0.499204",\
+ "-1.152401, -1.113697, -1.058374, -1.048432, -0.927596");
+ }
+
+ } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_remfr*/
+
+} /* end of pin otp_alert_src_i[1] */
+
+pin("otp_alert_src_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001210 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_alert_src_i[0];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.153898, 0.096234, -0.017862, -0.012789, 0.048865",\
+ "0.234547, 0.176873, 0.063006, 0.068247, 0.131938",\
+ "0.312922, 0.255231, 0.141780, 0.147323, 0.214693",\
+ "0.443628, 0.385987, 0.272716, 0.278561, 0.349586",\
+ "0.643976, 0.586670, 0.471971, 0.477562, 0.545510");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.135497, 0.097521, 0.047194, 0.048307, 0.061839",\
+ "0.227162, 0.188584, 0.138031, 0.139144, 0.152665",\
+ "0.314547, 0.274830, 0.224128, 0.225207, 0.238331",\
+ "0.459106, 0.419271, 0.367632, 0.368682, 0.381446",\
+ "0.699539, 0.659946, 0.606277, 0.607276, 0.619410");
+ }
+
+ } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.067048, -0.016232, 0.079533, 0.097739, 0.319005",\
+ "-0.147841, -0.096754, 0.000043, 0.018162, 0.238358",\
+ "-0.226477, -0.174901, -0.076238, -0.058278, 0.159985",\
+ "-0.357390, -0.304774, -0.203323, -0.185507, 0.031000",\
+ "-0.557290, -0.502515, -0.398294, -0.380283, -0.161393");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.067653, -0.034085, 0.023249, 0.050680, 0.384046",\
+ "-0.158725, -0.125379, -0.067382, -0.046199, 0.211248",\
+ "-0.245194, -0.212186, -0.153370, -0.141879, -0.002219",\
+ "-0.386154, -0.352349, -0.293338, -0.283677, -0.166272",\
+ "-0.618941, -0.583206, -0.524120, -0.514248, -0.394277");
+ }
+
+ } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_hldr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.348301, 0.305676, 0.248104, 0.251583, 0.293858",\
+ "0.429286, 0.386661, 0.329089, 0.332567, 0.374842",\
+ "0.504635, 0.462011, 0.404396, 0.407864, 0.450008",\
+ "0.638699, 0.596084, 0.538251, 0.541665, 0.583146",\
+ "0.863013, 0.820471, 0.762185, 0.765489, 0.805634");
+ }
+
+ } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.260501, -0.223062, -0.163229, -0.153056, -0.029425",\
+ "-0.341485, -0.304046, -0.244213, -0.234040, -0.110409",\
+ "-0.416836, -0.379397, -0.319604, -0.309428, -0.185759",\
+ "-0.550887, -0.513443, -0.453851, -0.443663, -0.319850",\
+ "-0.774977, -0.737427, -0.678253, -0.668084, -0.544492");
+ }
+
+ } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_remrr*/
+
+} /* end of pin otp_alert_src_i[0] */
+} /* end of bus otp_alert_src_i */
+bus ( alert_rsp_i ) {
+
+ bus_type : BUS52_type11 ;
+ direction : input ;
+
+pin("alert_rsp_i[51]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[51];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[51]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[51]_hldr*/
+
+} /* end of pin alert_rsp_i[51] */
+
+pin("alert_rsp_i[50]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[50];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[50]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[50]_hldr*/
+
+} /* end of pin alert_rsp_i[50] */
+
+pin("alert_rsp_i[49]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[49];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[49]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[49]_hldr*/
+
+} /* end of pin alert_rsp_i[49] */
+
+pin("alert_rsp_i[48]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[48];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[48]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[48]_hldr*/
+
+} /* end of pin alert_rsp_i[48] */
+
+pin("alert_rsp_i[47]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[47];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[47]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[47]_hldr*/
+
+} /* end of pin alert_rsp_i[47] */
+
+pin("alert_rsp_i[46]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[46];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[46]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[46]_hldr*/
+
+} /* end of pin alert_rsp_i[46] */
+
+pin("alert_rsp_i[45]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[45];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[45]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[45]_hldr*/
+
+} /* end of pin alert_rsp_i[45] */
+
+pin("alert_rsp_i[44]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[44];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[44]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[44]_hldr*/
+
+} /* end of pin alert_rsp_i[44] */
+
+pin("alert_rsp_i[43]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[43];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[43]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[43]_hldr*/
+
+} /* end of pin alert_rsp_i[43] */
+
+pin("alert_rsp_i[42]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[42];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[42]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[42]_hldr*/
+
+} /* end of pin alert_rsp_i[42] */
+
+pin("alert_rsp_i[41]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[41];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[41]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[41]_hldr*/
+
+} /* end of pin alert_rsp_i[41] */
+
+pin("alert_rsp_i[40]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[40];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[40]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[40]_hldr*/
+
+} /* end of pin alert_rsp_i[40] */
+
+pin("alert_rsp_i[39]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[39];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[39]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[39]_hldr*/
+
+} /* end of pin alert_rsp_i[39] */
+
+pin("alert_rsp_i[38]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[38];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[38]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[38]_hldr*/
+
+} /* end of pin alert_rsp_i[38] */
+
+pin("alert_rsp_i[37]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[37];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[37]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[37]_hldr*/
+
+} /* end of pin alert_rsp_i[37] */
+
+pin("alert_rsp_i[36]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[36];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[36]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[36]_hldr*/
+
+} /* end of pin alert_rsp_i[36] */
+
+pin("alert_rsp_i[35]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[35];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[35]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[35]_hldr*/
+
+} /* end of pin alert_rsp_i[35] */
+
+pin("alert_rsp_i[34]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[34];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[34]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[34]_hldr*/
+
+} /* end of pin alert_rsp_i[34] */
+
+pin("alert_rsp_i[33]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[33];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[33]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[33]_hldr*/
+
+} /* end of pin alert_rsp_i[33] */
+
+pin("alert_rsp_i[32]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[32];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[32]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[32]_hldr*/
+
+} /* end of pin alert_rsp_i[32] */
+
+pin("alert_rsp_i[31]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[31];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[31]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[31]_hldr*/
+
+} /* end of pin alert_rsp_i[31] */
+
+pin("alert_rsp_i[30]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[30];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[30]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[30]_hldr*/
+
+} /* end of pin alert_rsp_i[30] */
+
+pin("alert_rsp_i[29]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[29];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[29]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[29]_hldr*/
+
+} /* end of pin alert_rsp_i[29] */
+
+pin("alert_rsp_i[28]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[28];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[28]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[28]_hldr*/
+
+} /* end of pin alert_rsp_i[28] */
+
+pin("alert_rsp_i[27]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000591 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[27];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\
+ "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\
+ "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\
+ "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\
+ "0.860633, 0.798634, 0.691077, 0.712170, 0.968509");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\
+ "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\
+ "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\
+ "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\
+ "0.868870, 0.834430, 0.778706, 0.778804, 0.779997");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[27]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\
+ "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\
+ "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\
+ "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\
+ "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\
+ "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\
+ "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\
+ "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\
+ "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[27]_hldr*/
+
+} /* end of pin alert_rsp_i[27] */
+
+pin("alert_rsp_i[26]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000589 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[26];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\
+ "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\
+ "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\
+ "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\
+ "0.781727, 0.719289, 0.610887, 0.631753, 0.885337");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\
+ "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\
+ "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\
+ "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\
+ "0.915076, 0.879998, 0.824973, 0.825069, 0.826237");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[26]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\
+ "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\
+ "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\
+ "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\
+ "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\
+ "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\
+ "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\
+ "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\
+ "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[26]_hldr*/
+
+} /* end of pin alert_rsp_i[26] */
+
+pin("alert_rsp_i[25]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[25];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[25]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[25]_hldr*/
+
+} /* end of pin alert_rsp_i[25] */
+
+pin("alert_rsp_i[24]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[24];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[24]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[24]_hldr*/
+
+} /* end of pin alert_rsp_i[24] */
+
+pin("alert_rsp_i[23]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[23];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[23]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[23]_hldr*/
+
+} /* end of pin alert_rsp_i[23] */
+
+pin("alert_rsp_i[22]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[22];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[22]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[22]_hldr*/
+
+} /* end of pin alert_rsp_i[22] */
+
+pin("alert_rsp_i[21]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[21];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[21]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[21]_hldr*/
+
+} /* end of pin alert_rsp_i[21] */
+
+pin("alert_rsp_i[20]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[20];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[20]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[20]_hldr*/
+
+} /* end of pin alert_rsp_i[20] */
+
+pin("alert_rsp_i[19]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[19];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[19]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[19]_hldr*/
+
+} /* end of pin alert_rsp_i[19] */
+
+pin("alert_rsp_i[18]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[18];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[18]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[18]_hldr*/
+
+} /* end of pin alert_rsp_i[18] */
+
+pin("alert_rsp_i[17]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[17];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[17]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[17]_hldr*/
+
+} /* end of pin alert_rsp_i[17] */
+
+pin("alert_rsp_i[16]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[16];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[16]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[16]_hldr*/
+
+} /* end of pin alert_rsp_i[16] */
+
+pin("alert_rsp_i[15]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[15];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[15]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[15]_hldr*/
+
+} /* end of pin alert_rsp_i[15] */
+
+pin("alert_rsp_i[14]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[14];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[14]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[14]_hldr*/
+
+} /* end of pin alert_rsp_i[14] */
+
+pin("alert_rsp_i[13]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[13];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[13]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[13]_hldr*/
+
+} /* end of pin alert_rsp_i[13] */
+
+pin("alert_rsp_i[12]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[12];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[12]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[12]_hldr*/
+
+} /* end of pin alert_rsp_i[12] */
+
+pin("alert_rsp_i[11]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[11];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[11]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[11]_hldr*/
+
+} /* end of pin alert_rsp_i[11] */
+
+pin("alert_rsp_i[10]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[10];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[10]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[10]_hldr*/
+
+} /* end of pin alert_rsp_i[10] */
+
+pin("alert_rsp_i[9]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[9];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[9]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[9]_hldr*/
+
+} /* end of pin alert_rsp_i[9] */
+
+pin("alert_rsp_i[8]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[8];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[8]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[8]_hldr*/
+
+} /* end of pin alert_rsp_i[8] */
+
+pin("alert_rsp_i[7]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[7];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[7]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[7]_hldr*/
+
+} /* end of pin alert_rsp_i[7] */
+
+pin("alert_rsp_i[6]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[6];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[6]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[6]_hldr*/
+
+} /* end of pin alert_rsp_i[6] */
+
+pin("alert_rsp_i[5]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[5];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[5]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[5]_hldr*/
+
+} /* end of pin alert_rsp_i[5] */
+
+pin("alert_rsp_i[4]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[4];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[4]_hldr*/
+
+} /* end of pin alert_rsp_i[4] */
+
+pin("alert_rsp_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[3];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[3]_hldr*/
+
+} /* end of pin alert_rsp_i[3] */
+
+pin("alert_rsp_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[2];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[2]_hldr*/
+
+} /* end of pin alert_rsp_i[2] */
+
+pin("alert_rsp_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000448 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[1];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\
+ "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\
+ "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\
+ "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\
+ "0.782742, 0.746824, 0.692719, 0.692812, 0.693947");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\
+ "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\
+ "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\
+ "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\
+ "0.922412, 0.861156, 0.755022, 0.776496, 1.037479");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\
+ "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\
+ "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\
+ "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\
+ "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\
+ "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\
+ "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\
+ "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\
+ "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[1]_hldr*/
+
+} /* end of pin alert_rsp_i[1] */
+
+pin("alert_rsp_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000500 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_rsp_i[0];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\
+ "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\
+ "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\
+ "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\
+ "0.712779, 0.676837, 0.622759, 0.622852, 0.623986");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\
+ "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\
+ "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\
+ "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\
+ "0.877762, 0.816594, 0.710628, 0.732149, 0.993683");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\
+ "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\
+ "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\
+ "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\
+ "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\
+ "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\
+ "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\
+ "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\
+ "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_rsp_i[0]_hldr*/
+
+} /* end of pin alert_rsp_i[0] */
+} /* end of bus alert_rsp_i */
+bus ( alert_req_o ) {
+
+ bus_type : BUS26_type12 ;
+ direction : output ;
+
+pin("alert_req_o[25]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[25];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[25]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[25]_redg_min*/
+
+} /* end of pin alert_req_o[25] */
+
+pin("alert_req_o[24]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[24];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[24]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[24]_redg_min*/
+
+} /* end of pin alert_req_o[24] */
+
+pin("alert_req_o[23]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[23];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[23]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[23]_redg_min*/
+
+} /* end of pin alert_req_o[23] */
+
+pin("alert_req_o[22]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[22];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[22]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[22]_redg_min*/
+
+} /* end of pin alert_req_o[22] */
+
+pin("alert_req_o[21]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[21];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[21]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[21]_redg_min*/
+
+} /* end of pin alert_req_o[21] */
+
+pin("alert_req_o[20]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[20];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[20]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[20]_redg_min*/
+
+} /* end of pin alert_req_o[20] */
+
+pin("alert_req_o[19]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[19];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[19]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[19]_redg_min*/
+
+} /* end of pin alert_req_o[19] */
+
+pin("alert_req_o[18]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[18];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[18]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[18]_redg_min*/
+
+} /* end of pin alert_req_o[18] */
+
+pin("alert_req_o[17]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[17];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[17]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[17]_redg_min*/
+
+} /* end of pin alert_req_o[17] */
+
+pin("alert_req_o[16]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[16];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[16]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[16]_redg_min*/
+
+} /* end of pin alert_req_o[16] */
+
+pin("alert_req_o[15]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[15];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[15]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[15]_redg_min*/
+
+} /* end of pin alert_req_o[15] */
+
+pin("alert_req_o[14]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[14];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[14]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[14]_redg_min*/
+
+} /* end of pin alert_req_o[14] */
+
+pin("alert_req_o[13]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[13];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[13]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[13]_redg_min*/
+
+} /* end of pin alert_req_o[13] */
+
+pin("alert_req_o[12]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[12];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[12]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[12]_redg_min*/
+
+} /* end of pin alert_req_o[12] */
+
+pin("alert_req_o[11]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[11];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[11]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[11]_redg_min*/
+
+} /* end of pin alert_req_o[11] */
+
+pin("alert_req_o[10]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[10];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[10]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[10]_redg_min*/
+
+} /* end of pin alert_req_o[10] */
+
+pin("alert_req_o[9]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[9];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[9]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[9]_redg_min*/
+
+} /* end of pin alert_req_o[9] */
+
+pin("alert_req_o[8]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[8];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[8]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[8]_redg_min*/
+
+} /* end of pin alert_req_o[8] */
+
+pin("alert_req_o[7]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[7];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[7]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[7]_redg_min*/
+
+} /* end of pin alert_req_o[7] */
+
+pin("alert_req_o[6]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[6];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[6]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[6]_redg_min*/
+
+} /* end of pin alert_req_o[6] */
+
+pin("alert_req_o[5]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[5];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[5]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[5]_redg_min*/
+
+} /* end of pin alert_req_o[5] */
+
+pin("alert_req_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[4];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[4]_redg_min*/
+
+} /* end of pin alert_req_o[4] */
+
+pin("alert_req_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[3];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\
+ "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\
+ "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\
+ "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\
+ "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\
+ "0.043338, 0.097514, 0.190357, 0.340034, 1.494292");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\
+ "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\
+ "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\
+ "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\
+ "0.584903, 0.727700, 0.813314, 0.950396, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\
+ "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\
+ "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\
+ "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\
+ "0.135119, 0.207795, 0.342920, 0.559922, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\
+ "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\
+ "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\
+ "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\
+ "0.637044, 0.700813, 0.755435, 0.842904, 1.478811");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048");
+ values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\
+ "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\
+ "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\
+ "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\
+ "0.043338, 0.097514, 0.190357, 0.339166, 1.490219");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[3]_redg_min*/
+
+} /* end of pin alert_req_o[3] */
+
+pin("alert_req_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001149 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[2];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\
+ "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\
+ "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\
+ "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\
+ "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\
+ "0.043741, 0.097870, 0.190712, 0.340409, 1.494277");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\
+ "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\
+ "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\
+ "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\
+ "0.587490, 0.728041, 0.813655, 0.950730, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\
+ "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\
+ "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\
+ "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\
+ "0.136105, 0.208333, 0.343458, 0.560560, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\
+ "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\
+ "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\
+ "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\
+ "0.638051, 0.701022, 0.755644, 0.843111, 1.478802");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048");
+ values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\
+ "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\
+ "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\
+ "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\
+ "0.043741, 0.097870, 0.190712, 0.339540, 1.490204");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[2]_redg_min*/
+
+} /* end of pin alert_req_o[2] */
+
+pin("alert_req_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001011 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[1];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048");
+ values ( "0.054759, 0.128313, 0.213323, 0.349457, 1.341047",\
+ "0.111579, 0.185344, 0.270112, 0.405873, 1.402083",\
+ "0.250250, 0.333539, 0.418248, 0.553913, 1.548154",\
+ "0.283987, 0.371683, 0.456312, 0.591852, 1.586834",\
+ "0.585354, 0.727759, 0.813374, 0.950454, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048");
+ values ( "0.026541, 0.137190, 0.296770, 0.552376, 2.441059",\
+ "0.027722, 0.137535, 0.296770, 0.552376, 2.442441",\
+ "0.049082, 0.143999, 0.302126, 0.555458, 2.445574",\
+ "0.056237, 0.147407, 0.304051, 0.555458, 2.445574",\
+ "0.135291, 0.207889, 0.343014, 0.560034, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048");
+ values ( "0.074438, 0.127065, 0.181703, 0.269191, 0.901573",\
+ "0.135357, 0.187983, 0.242503, 0.329807, 0.964298",\
+ "0.278376, 0.331673, 0.386077, 0.473193, 1.104686",\
+ "0.313854, 0.367693, 0.422104, 0.509231, 1.140694",\
+ "0.637244, 0.700854, 0.755477, 0.842945, 1.478814");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048");
+ values ( "0.022386, 0.090122, 0.186194, 0.340109, 1.494298",\
+ "0.022386, 0.090236, 0.186194, 0.340109, 1.494298",\
+ "0.024466, 0.090482, 0.186194, 0.340109, 1.494298",\
+ "0.025646, 0.090844, 0.186194, 0.340109, 1.494298",\
+ "0.043418, 0.097585, 0.190427, 0.340109, 1.494298");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048");
+ values ( "0.054759, 0.128313, 0.213323, 0.349457, 1.341047",\
+ "0.111579, 0.185344, 0.270112, 0.405873, 1.402083",\
+ "0.250250, 0.333539, 0.418248, 0.553913, 1.548154",\
+ "0.283987, 0.371683, 0.456312, 0.591852, 1.586834",\
+ "0.585354, 0.727759, 0.813374, 0.950454, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048");
+ values ( "0.026541, 0.137190, 0.296764, 0.551818, 2.441059",\
+ "0.027722, 0.137535, 0.296764, 0.551818, 2.442441",\
+ "0.049082, 0.143999, 0.302126, 0.555040, 2.445574",\
+ "0.056237, 0.147407, 0.304051, 0.555040, 2.445574",\
+ "0.135291, 0.207889, 0.343014, 0.560034, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048");
+ values ( "0.074438, 0.127065, 0.181703, 0.269191, 0.901573",\
+ "0.135357, 0.187983, 0.242503, 0.329807, 0.964298",\
+ "0.278376, 0.331673, 0.386077, 0.473193, 1.104686",\
+ "0.313854, 0.367693, 0.422104, 0.509231, 1.140694",\
+ "0.637244, 0.700854, 0.755477, 0.842945, 1.478814");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048");
+ values ( "0.022386, 0.090122, 0.185722, 0.338326, 1.490226",\
+ "0.022386, 0.090236, 0.185722, 0.338326, 1.490226",\
+ "0.024466, 0.090482, 0.185722, 0.338326, 1.490226",\
+ "0.025646, 0.090844, 0.186005, 0.338489, 1.490226",\
+ "0.043418, 0.097585, 0.190427, 0.339240, 1.490226");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[1]_redg_min*/
+
+} /* end of pin alert_req_o[1] */
+
+pin("alert_req_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.634048 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000990 ;
+
+ /* Other user defined attributes. */
+ original_pin : alert_req_o[0];
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048");
+ values ( "0.054663, 0.128270, 0.213280, 0.349414, 1.341047",\
+ "0.111482, 0.185301, 0.270069, 0.405830, 1.402083",\
+ "0.250105, 0.333496, 0.418205, 0.553870, 1.548154",\
+ "0.283826, 0.371640, 0.456269, 0.591809, 1.586834",\
+ "0.585026, 0.727716, 0.813330, 0.950411, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048");
+ values ( "0.026453, 0.137109, 0.296689, 0.552294, 2.441059",\
+ "0.027638, 0.137454, 0.296689, 0.552294, 2.442441",\
+ "0.049002, 0.143919, 0.302046, 0.555377, 2.445574",\
+ "0.056155, 0.147327, 0.303971, 0.555377, 2.445574",\
+ "0.135166, 0.207821, 0.342945, 0.559953, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048");
+ values ( "0.074369, 0.127040, 0.181679, 0.269167, 0.901576",\
+ "0.135288, 0.187959, 0.242479, 0.329784, 0.964302",\
+ "0.278302, 0.331649, 0.386053, 0.473170, 1.104690",\
+ "0.313777, 0.367669, 0.422080, 0.509207, 1.140697",\
+ "0.637128, 0.700830, 0.755452, 0.842922, 1.478818");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048");
+ values ( "0.022335, 0.090079, 0.186151, 0.340065, 1.494304",\
+ "0.022335, 0.090194, 0.186151, 0.340065, 1.494304",\
+ "0.024413, 0.090440, 0.186151, 0.340065, 1.494304",\
+ "0.025595, 0.090802, 0.186151, 0.340065, 1.494304",\
+ "0.043371, 0.097543, 0.190386, 0.340065, 1.494304");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048");
+ values ( "0.054663, 0.128270, 0.213280, 0.349414, 1.341047",\
+ "0.111482, 0.185301, 0.270069, 0.405830, 1.402083",\
+ "0.250105, 0.333496, 0.418205, 0.553870, 1.548154",\
+ "0.283826, 0.371640, 0.456269, 0.591809, 1.586834",\
+ "0.585026, 0.727716, 0.813330, 0.950411, 1.938873");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048");
+ values ( "0.026453, 0.137109, 0.296683, 0.551737, 2.441059",\
+ "0.027638, 0.137454, 0.296683, 0.551737, 2.442441",\
+ "0.049002, 0.143919, 0.302046, 0.554959, 2.445574",\
+ "0.056155, 0.147327, 0.303971, 0.554959, 2.445574",\
+ "0.135166, 0.207821, 0.342945, 0.559953, 2.445574");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048");
+ values ( "0.074369, 0.127040, 0.181679, 0.269167, 0.901576",\
+ "0.135288, 0.187959, 0.242479, 0.329784, 0.964302",\
+ "0.278302, 0.331649, 0.386053, 0.473170, 1.104690",\
+ "0.313777, 0.367669, 0.422080, 0.509207, 1.140697",\
+ "0.637128, 0.700830, 0.755452, 0.842922, 1.478818");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048");
+ values ( "0.022335, 0.090079, 0.185679, 0.338282, 1.490232",\
+ "0.022335, 0.090194, 0.185679, 0.338282, 1.490232",\
+ "0.024413, 0.090440, 0.185679, 0.338282, 1.490232",\
+ "0.025595, 0.090802, 0.185963, 0.338445, 1.490232",\
+ "0.043371, 0.097543, 0.190386, 0.339197, 1.490232");
+ }
+
+ } /* end of arc clk_ast_alert_i_alert_req_o[0]_redg_min*/
+
+} /* end of pin alert_req_o[0] */
+} /* end of bus alert_req_o */
+bus ( dft_strap_test_i ) {
+
+ bus_type : BUS3_type13 ;
+ direction : input ;
+
+pin("dft_strap_test_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001120 ;
+
+ /* Other user defined attributes. */
+ original_pin : dft_strap_test_i[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.478706, 0.503228, 0.581052, 0.648637, 1.079464",\
+ "0.567148, 0.591670, 0.669494, 0.737079, 1.167906",\
+ "0.650074, 0.674596, 0.752419, 0.820004, 1.250831",\
+ "0.793078, 0.817600, 0.895423, 0.963008, 1.393835",\
+ "1.032445, 1.056946, 1.134770, 1.202355, 1.633182");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.463301, 0.380673, 0.305530, 0.271812, 0.239120",\
+ "0.556491, 0.473863, 0.398720, 0.365002, 0.332310",\
+ "0.646873, 0.564245, 0.489102, 0.455384, 0.422692",\
+ "0.811633, 0.729010, 0.653883, 0.620177, 0.587543",\
+ "1.181053, 1.098457, 1.023414, 0.989768, 0.957438");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_strap_test_i[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.265123, -0.222342, -0.186677, -0.161410, -0.033314",\
+ "-0.347654, -0.304874, -0.269208, -0.243941, -0.115845",\
+ "-0.437836, -0.395055, -0.359390, -0.334122, -0.206027",\
+ "-0.606076, -0.563289, -0.527626, -0.502359, -0.374263",\
+ "-0.890704, -0.847899, -0.812254, -0.786994, -0.658891");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.255864, -0.182785, -0.116647, -0.070567, 0.157553",\
+ "-0.349537, -0.279942, -0.213805, -0.167724, 0.060396",\
+ "-0.440910, -0.389678, -0.323541, -0.277461, -0.049341",\
+ "-0.599026, -0.557614, -0.524142, -0.478056, -0.249871",\
+ "-0.851183, -0.809770, -0.777053, -0.739869, -0.511712");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_strap_test_i[2]_hldr*/
+
+} /* end of pin dft_strap_test_i[2] */
+
+pin("dft_strap_test_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001321 ;
+
+ /* Other user defined attributes. */
+ original_pin : dft_strap_test_i[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.428035, 0.345406, 0.276171, 0.259388, 0.254027",\
+ "0.519710, 0.437082, 0.361939, 0.340063, 0.334702",\
+ "0.618532, 0.535904, 0.460761, 0.427043, 0.420880",\
+ "0.797361, 0.714733, 0.639590, 0.605872, 0.573180",\
+ "1.098214, 1.015590, 0.940461, 0.906752, 0.874108");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.453520, 0.478042, 0.555866, 0.623451, 1.054278",\
+ "0.538258, 0.562780, 0.640604, 0.708189, 1.139016",\
+ "0.651889, 0.676378, 0.754202, 0.821787, 1.252614",\
+ "0.864482, 0.889878, 0.967702, 1.035287, 1.466114",\
+ "1.235476, 1.260812, 1.338683, 1.406288, 1.837127");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_strap_test_i[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.221451, -0.180039, -0.147321, -0.110125, 0.118032",\
+ "-0.314428, -0.273016, -0.240298, -0.203102, 0.025055",\
+ "-0.409753, -0.368340, -0.335623, -0.298439, -0.070282",\
+ "-0.551259, -0.508465, -0.472804, -0.447539, -0.236382",\
+ "-0.757339, -0.714548, -0.679008, -0.653790, -0.510956");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.247877, -0.173125, -0.106987, -0.060907, 0.167213",\
+ "-0.342789, -0.268037, -0.201899, -0.155819, 0.072301",\
+ "-0.443799, -0.369047, -0.302909, -0.256829, -0.028709",\
+ "-0.627085, -0.552322, -0.486182, -0.440095, -0.211908",\
+ "-0.932472, -0.857684, -0.791539, -0.745437, -0.517093");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_strap_test_i[1]_hldr*/
+
+} /* end of pin dft_strap_test_i[1] */
+
+pin("dft_strap_test_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000495 ;
+
+ /* Other user defined attributes. */
+ original_pin : dft_strap_test_i[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.476989, 0.501509, 0.579333, 0.646918, 1.077745",\
+ "0.568510, 0.593031, 0.670855, 0.738440, 1.169267",\
+ "0.663180, 0.687701, 0.765525, 0.833110, 1.263937",\
+ "0.832054, 0.856556, 0.934380, 1.001965, 1.432792",\
+ "1.118659, 1.143116, 1.220940, 1.288525, 1.719352");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.474663, 0.392034, 0.328853, 0.312070, 0.306709",\
+ "0.571978, 0.489349, 0.424889, 0.408106, 0.402744",\
+ "0.676749, 0.594121, 0.529069, 0.512287, 0.506925",\
+ "0.856563, 0.773935, 0.708488, 0.691705, 0.686343",\
+ "1.151508, 1.068880, 1.004139, 0.987361, 0.981971");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_strap_test_i[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.289829, -0.215077, -0.148940, -0.102859, 0.125261",\
+ "-0.385674, -0.310922, -0.244784, -0.198704, 0.029416",\
+ "-0.484928, -0.410176, -0.344038, -0.297958, -0.069838",\
+ "-0.657145, -0.582393, -0.516256, -0.470176, -0.242056",\
+ "-0.943033, -0.868281, -0.802144, -0.756064, -0.527944");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.269424, -0.228012, -0.195294, -0.158099, 0.070058",\
+ "-0.366945, -0.325532, -0.292815, -0.255619, -0.027462",\
+ "-0.471935, -0.430523, -0.397805, -0.360610, -0.132453",\
+ "-0.650169, -0.608757, -0.576039, -0.538849, -0.310692",\
+ "-0.940386, -0.898973, -0.866256, -0.829075, -0.600918");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_strap_test_i[0]_hldr*/
+
+} /* end of pin dft_strap_test_i[0] */
+} /* end of bus dft_strap_test_i */
+bus ( lc_dft_en_i ) {
+
+ bus_type : BUS4_type6 ;
+ direction : input ;
+
+pin("lc_dft_en_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : lc_dft_en_i[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.116868, 0.046289, 0.009123, -0.011232, -0.072101",\
+ "0.130035, 0.060315, 0.022495, 0.001866, -0.059037",\
+ "0.171476, 0.101933, 0.064692, 0.043957, -0.021156",\
+ "0.330098, 0.263569, 0.222296, 0.198239, 0.112987",\
+ "0.772581, 0.713134, 0.646673, 0.609916, 0.496722");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.164832, 0.206226, 0.283518, 0.350873, 0.781571",\
+ "0.176771, 0.218346, 0.296254, 0.363875, 0.794722",\
+ "0.219963, 0.260510, 0.337961, 0.405191, 0.833567",\
+ "0.396019, 0.435268, 0.507744, 0.571712, 0.985407",\
+ "0.931350, 0.951153, 1.007354, 1.063861, 1.468564");
+ }
+
+ } /* end of arc clk_ast_tlul_i_lc_dft_en_i[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.015255, 0.029491, 0.060650, 0.081348, 0.176530",\
+ "-0.028040, 0.015174, 0.046352, 0.067152, 0.163478",\
+ "-0.067695, -0.029062, 0.006032, 0.028571, 0.126390",\
+ "-0.170614, -0.143005, -0.113142, -0.091864, 0.016864",\
+ "-0.388675, -0.412783, -0.403332, -0.388997, -0.262218");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.058687, -0.133819, -0.215174, -0.276149, -0.608913",\
+ "-0.070579, -0.145649, -0.226804, -0.287545, -0.618487",\
+ "-0.113780, -0.187774, -0.267897, -0.328130, -0.658063",\
+ "-0.257059, -0.339271, -0.416614, -0.475103, -0.797794",\
+ "-0.613549, -0.743897, -0.832843, -0.896262, -1.220625");
+ }
+
+ } /* end of arc clk_ast_tlul_i_lc_dft_en_i[3]_hldr*/
+
+} /* end of pin lc_dft_en_i[3] */
+
+pin("lc_dft_en_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : lc_dft_en_i[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\
+ "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\
+ "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\
+ "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\
+ "0.811131, 0.757315, 0.714144, 0.695925, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\
+ "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\
+ "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\
+ "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\
+ "0.983325, 0.898854, 0.822917, 0.782684, 0.674795");
+ }
+
+ } /* end of arc clk_ast_tlul_i_lc_dft_en_i[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\
+ "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\
+ "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\
+ "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\
+ "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\
+ "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\
+ "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\
+ "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\
+ "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923");
+ }
+
+ } /* end of arc clk_ast_tlul_i_lc_dft_en_i[2]_hldr*/
+
+} /* end of pin lc_dft_en_i[2] */
+
+pin("lc_dft_en_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : lc_dft_en_i[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.116868, 0.046289, 0.009123, -0.011232, -0.072101",\
+ "0.130035, 0.060315, 0.022495, 0.001866, -0.059037",\
+ "0.171476, 0.101933, 0.064692, 0.043957, -0.021156",\
+ "0.330098, 0.263569, 0.222296, 0.198239, 0.112987",\
+ "0.772581, 0.713134, 0.646673, 0.609916, 0.496722");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.164832, 0.206226, 0.283518, 0.350873, 0.781571",\
+ "0.176771, 0.218346, 0.296254, 0.363875, 0.794722",\
+ "0.219963, 0.260510, 0.337961, 0.405191, 0.833567",\
+ "0.396019, 0.435268, 0.507744, 0.571712, 0.985407",\
+ "0.931350, 0.951153, 1.007354, 1.063861, 1.468564");
+ }
+
+ } /* end of arc clk_ast_tlul_i_lc_dft_en_i[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.015255, 0.029491, 0.060650, 0.081348, 0.176530",\
+ "-0.028040, 0.015174, 0.046352, 0.067152, 0.163478",\
+ "-0.067695, -0.029062, 0.006032, 0.028571, 0.126390",\
+ "-0.170614, -0.143005, -0.113142, -0.091864, 0.016864",\
+ "-0.388675, -0.412783, -0.403332, -0.388997, -0.262218");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.058687, -0.133819, -0.215174, -0.276149, -0.608913",\
+ "-0.070579, -0.145649, -0.226804, -0.287545, -0.618487",\
+ "-0.113780, -0.187774, -0.267897, -0.328130, -0.658063",\
+ "-0.257059, -0.339271, -0.416614, -0.475103, -0.797794",\
+ "-0.613549, -0.743897, -0.832843, -0.896262, -1.220625");
+ }
+
+ } /* end of arc clk_ast_tlul_i_lc_dft_en_i[1]_hldr*/
+
+} /* end of pin lc_dft_en_i[1] */
+
+pin("lc_dft_en_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : lc_dft_en_i[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\
+ "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\
+ "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\
+ "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\
+ "0.811131, 0.757315, 0.714144, 0.695925, 0.691143");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\
+ "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\
+ "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\
+ "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\
+ "0.983325, 0.898854, 0.822917, 0.782684, 0.674795");
+ }
+
+ } /* end of arc clk_ast_tlul_i_lc_dft_en_i[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\
+ "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\
+ "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\
+ "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\
+ "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\
+ "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\
+ "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\
+ "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\
+ "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923");
+ }
+
+ } /* end of arc clk_ast_tlul_i_lc_dft_en_i[0]_hldr*/
+
+} /* end of pin lc_dft_en_i[0] */
+} /* end of bus lc_dft_en_i */
+bus ( fla_obs_i ) {
+
+ bus_type : BUS8_type14 ;
+ direction : input ;
+
+pin("fla_obs_i[7]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000492 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_obs_i[7];
+} /* end of pin fla_obs_i[7] */
+
+pin("fla_obs_i[6]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000492 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_obs_i[6];
+} /* end of pin fla_obs_i[6] */
+
+pin("fla_obs_i[5]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000492 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_obs_i[5];
+} /* end of pin fla_obs_i[5] */
+
+pin("fla_obs_i[4]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000492 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_obs_i[4];
+} /* end of pin fla_obs_i[4] */
+
+pin("fla_obs_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000492 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_obs_i[3];
+} /* end of pin fla_obs_i[3] */
+
+pin("fla_obs_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000492 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_obs_i[2];
+} /* end of pin fla_obs_i[2] */
+
+pin("fla_obs_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000492 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_obs_i[1];
+} /* end of pin fla_obs_i[1] */
+
+pin("fla_obs_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000492 ;
+
+ /* Other user defined attributes. */
+ original_pin : fla_obs_i[0];
+} /* end of pin fla_obs_i[0] */
+} /* end of bus fla_obs_i */
+bus ( otp_obs_i ) {
+
+ bus_type : BUS8_type14 ;
+ direction : input ;
+
+pin("otp_obs_i[7]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_obs_i[7];
+} /* end of pin otp_obs_i[7] */
+
+pin("otp_obs_i[6]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_obs_i[6];
+} /* end of pin otp_obs_i[6] */
+
+pin("otp_obs_i[5]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_obs_i[5];
+} /* end of pin otp_obs_i[5] */
+
+pin("otp_obs_i[4]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_obs_i[4];
+} /* end of pin otp_obs_i[4] */
+
+pin("otp_obs_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_obs_i[3];
+} /* end of pin otp_obs_i[3] */
+
+pin("otp_obs_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_obs_i[2];
+} /* end of pin otp_obs_i[2] */
+
+pin("otp_obs_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_obs_i[1];
+} /* end of pin otp_obs_i[1] */
+
+pin("otp_obs_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otp_obs_i[0];
+} /* end of pin otp_obs_i[0] */
+} /* end of bus otp_obs_i */
+bus ( otm_obs_i ) {
+
+ bus_type : BUS8_type14 ;
+ direction : input ;
+
+pin("otm_obs_i[7]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otm_obs_i[7];
+} /* end of pin otm_obs_i[7] */
+
+pin("otm_obs_i[6]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otm_obs_i[6];
+} /* end of pin otm_obs_i[6] */
+
+pin("otm_obs_i[5]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otm_obs_i[5];
+} /* end of pin otm_obs_i[5] */
+
+pin("otm_obs_i[4]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otm_obs_i[4];
+} /* end of pin otm_obs_i[4] */
+
+pin("otm_obs_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otm_obs_i[3];
+} /* end of pin otm_obs_i[3] */
+
+pin("otm_obs_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otm_obs_i[2];
+} /* end of pin otm_obs_i[2] */
+
+pin("otm_obs_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000506 ;
+
+ /* Other user defined attributes. */
+ original_pin : otm_obs_i[1];
+} /* end of pin otm_obs_i[1] */
+
+pin("otm_obs_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000492 ;
+
+ /* Other user defined attributes. */
+ original_pin : otm_obs_i[0];
+} /* end of pin otm_obs_i[0] */
+} /* end of bus otm_obs_i */
+
+pin("usb_obs_i") {
+ direction : input ;
+ max_transition : 5.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : usb_obs_i;
+} /* end of pin usb_obs_i */
+bus ( obs_ctrl_o ) {
+
+ bus_type : BUS12_type15 ;
+ direction : output ;
+
+pin("obs_ctrl_o[11]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.156168 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000605 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[11];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.551399, 0.731602, 0.919092, 1.221084, 1.804596",\
+ "0.583544, 0.763747, 0.951237, 1.253229, 1.836741",\
+ "0.655451, 0.835654, 1.023144, 1.325136, 1.908648",\
+ "0.911916, 1.092119, 1.279609, 1.581602, 2.165114",\
+ "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\
+ "0.636337, 0.816885, 1.005100, 1.307096, 1.890974",\
+ "0.668482, 0.849030, 1.037246, 1.339242, 1.923120",\
+ "0.740389, 0.920937, 1.109152, 1.411149, 1.995026",\
+ "0.996855, 1.177402, 1.365618, 1.667614, 2.251492",\
+ "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\
+ "0.712249, 0.892328, 1.079909, 1.381693, 1.965147",\
+ "0.744394, 0.924473, 1.112054, 1.413838, 1.997292",\
+ "0.816301, 0.996380, 1.183961, 1.485745, 2.069199",\
+ "1.072767, 1.252846, 1.440427, 1.742211, 2.325664",\
+ "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\
+ "0.766618, 0.946840, 1.134560, 1.436233, 2.019464",\
+ "0.798764, 0.978985, 1.166705, 1.468378, 2.051609",\
+ "0.870670, 1.050892, 1.238612, 1.540285, 2.123516",\
+ "1.127136, 1.307358, 1.495078, 1.796751, 2.379982",\
+ "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\
+ "1.048213, 1.232108, 1.418511, 1.719959, 2.302742",\
+ "1.080358, 1.264253, 1.450656, 1.752105, 2.334887",\
+ "1.152265, 1.336160, 1.522563, 1.824011, 2.406794",\
+ "1.408731, 1.592625, 1.779028, 2.080477, 2.663259",\
+ "2.327707, 2.511601, 2.698004, 2.999453, 3.582235");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.410192, 0.677978, 0.939558, 1.379255, 2.258650",\
+ "0.437946, 0.705732, 0.967312, 1.407009, 2.286404",\
+ "0.489378, 0.757164, 1.018744, 1.458441, 2.337836",\
+ "0.655862, 0.923647, 1.185227, 1.624924, 2.504319",\
+ "1.246932, 1.514718, 1.776298, 2.215995, 3.095390",\
+ "0.498896, 0.766053, 1.028199, 1.467484, 2.346055",\
+ "0.526650, 0.793807, 1.055953, 1.495238, 2.373809",\
+ "0.578082, 0.845239, 1.107385, 1.546670, 2.425241",\
+ "0.744566, 1.011722, 1.273868, 1.713154, 2.591724",\
+ "1.335636, 1.602793, 1.864939, 2.304224, 3.182795",\
+ "0.591838, 0.859198, 1.119924, 1.559648, 2.439097",\
+ "0.619592, 0.886952, 1.147678, 1.587402, 2.466851",\
+ "0.671024, 0.938384, 1.199110, 1.638834, 2.518283",\
+ "0.837508, 1.104867, 1.365594, 1.805318, 2.684766",\
+ "1.428578, 1.695938, 1.956664, 2.396388, 3.275837",\
+ "0.657682, 0.927762, 1.186944, 1.626498, 2.505608",\
+ "0.685436, 0.955516, 1.214698, 1.654252, 2.533362",\
+ "0.736868, 1.006948, 1.266130, 1.705685, 2.584794",\
+ "0.903352, 1.173432, 1.432614, 1.872168, 2.751277",\
+ "1.494422, 1.764502, 2.023684, 2.463239, 3.342348",\
+ "1.004203, 1.308598, 1.557607, 1.995652, 2.871743",\
+ "1.031957, 1.336352, 1.585361, 2.023406, 2.899497",\
+ "1.083390, 1.387784, 1.636793, 2.074838, 2.950930",\
+ "1.249873, 1.554267, 1.803276, 2.241322, 3.117413",\
+ "1.840944, 2.145338, 2.394347, 2.832392, 3.708484");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2706*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.459504, 0.723077, 0.999350, 1.468080, 2.405539",\
+ "0.491649, 0.755223, 1.031495, 1.500225, 2.437684",\
+ "0.563556, 0.827130, 1.103402, 1.572132, 2.509591",\
+ "0.820022, 1.083595, 1.359868, 1.828597, 2.766056",\
+ "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\
+ "0.547698, 0.810618, 1.086918, 1.554795, 2.491473",\
+ "0.579843, 0.842764, 1.119063, 1.586940, 2.523618",\
+ "0.651750, 0.914670, 1.190970, 1.658847, 2.595525",\
+ "0.908216, 1.171136, 1.447435, 1.915312, 2.851990",\
+ "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\
+ "0.636014, 0.899599, 1.174883, 1.642418, 2.578428",\
+ "0.668159, 0.931744, 1.207028, 1.674563, 2.610573",\
+ "0.740066, 1.003651, 1.278935, 1.746470, 2.682480",\
+ "0.996532, 1.260116, 1.535400, 2.002935, 2.938945",\
+ "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\
+ "0.698510, 0.965234, 1.239022, 1.706331, 2.641937",\
+ "0.730655, 0.997379, 1.271168, 1.738477, 2.674082",\
+ "0.802562, 1.069286, 1.343075, 1.810383, 2.745989",\
+ "1.059028, 1.325751, 1.599540, 2.066849, 3.002454",\
+ "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\
+ "1.027636, 1.329564, 1.590890, 2.055681, 2.987393",\
+ "1.059781, 1.361710, 1.623035, 2.087826, 3.019538",\
+ "1.131688, 1.433616, 1.694942, 2.159733, 3.091445",\
+ "1.388154, 1.690082, 1.951407, 2.416198, 3.347910",\
+ "2.307129, 2.609058, 2.870384, 3.335176, 4.266890");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.393145, 0.575577, 0.771969, 1.081022, 1.675830",\
+ "0.420899, 0.603331, 0.799723, 1.108776, 1.703585",\
+ "0.472331, 0.654763, 0.851155, 1.160208, 1.755017",\
+ "0.638815, 0.821247, 1.017638, 1.326692, 1.921499",\
+ "1.229885, 1.412317, 1.608709, 1.917762, 2.512568",\
+ "0.480560, 0.662962, 0.859462, 1.168327, 1.763184",\
+ "0.508314, 0.690716, 0.887216, 1.196081, 1.790938",\
+ "0.559746, 0.742149, 0.938648, 1.247514, 1.842370",\
+ "0.726229, 0.908632, 1.105132, 1.413997, 2.008852",\
+ "1.317300, 1.499703, 1.696202, 2.005067, 2.599921",\
+ "0.561436, 0.743299, 0.939489, 1.248356, 1.843215",\
+ "0.589190, 0.771053, 0.967243, 1.276110, 1.870970",\
+ "0.640622, 0.822485, 1.018675, 1.327542, 1.922402",\
+ "0.807106, 0.988969, 1.185158, 1.494025, 2.088884",\
+ "1.398176, 1.580039, 1.776229, 2.085095, 2.679953",\
+ "0.619083, 0.800848, 0.997033, 1.305601, 1.899863",\
+ "0.646837, 0.828601, 1.024787, 1.333355, 1.927617",\
+ "0.698269, 0.880034, 1.076219, 1.384787, 1.979049",\
+ "0.864752, 1.046517, 1.242702, 1.551270, 2.145531",\
+ "1.455823, 1.637588, 1.833773, 2.142340, 2.736601",\
+ "0.921290, 1.106072, 1.300666, 1.608616, 2.201710",\
+ "0.949044, 1.133826, 1.328420, 1.636370, 2.229464",\
+ "1.000476, 1.185258, 1.379853, 1.687802, 2.280896",\
+ "1.166960, 1.351742, 1.546336, 1.854285, 2.447378",\
+ "1.758030, 1.942812, 2.137407, 2.445355, 3.038447");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2637*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.455529, 0.715158, 0.987030, 1.443910, 2.357670",\
+ "0.487674, 0.747303, 1.019175, 1.476055, 2.389815",\
+ "0.559581, 0.819210, 1.091082, 1.547962, 2.461721",\
+ "0.816046, 1.075675, 1.347547, 1.804427, 2.718186",\
+ "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\
+ "0.543634, 0.802691, 1.074561, 1.530625, 2.443603",\
+ "0.575779, 0.834837, 1.106706, 1.562770, 2.475748",\
+ "0.647686, 0.906743, 1.178613, 1.634677, 2.547655",\
+ "0.904151, 1.163209, 1.435078, 1.891142, 2.804120",\
+ "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\
+ "0.631664, 0.891657, 1.162525, 1.618248, 2.530558",\
+ "0.663809, 0.923802, 1.194670, 1.650393, 2.562703",\
+ "0.735716, 0.995709, 1.266577, 1.722300, 2.634610",\
+ "0.992181, 1.252175, 1.523042, 1.978765, 2.891075",\
+ "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\
+ "0.693885, 0.957271, 1.226663, 1.682162, 2.594067",\
+ "0.726030, 0.989416, 1.258808, 1.714307, 2.626212",\
+ "0.797937, 1.061323, 1.330715, 1.786214, 2.698119",\
+ "1.054402, 1.317788, 1.587180, 2.042679, 2.954584",\
+ "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\
+ "1.021272, 1.321346, 1.578410, 2.031462, 2.939523",\
+ "1.053417, 1.353491, 1.610555, 2.063607, 2.971668",\
+ "1.125324, 1.425398, 1.682462, 2.135514, 3.043575",\
+ "1.381790, 1.681863, 1.938927, 2.391979, 3.300040",\
+ "2.300766, 2.600840, 2.857904, 3.310957, 4.219019");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\
+ "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\
+ "2.463890, 2.463889, 2.463888, 2.463885, 2.463879");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.391484, 0.574025, 0.770279, 1.079497, 1.674793",\
+ "0.419237, 0.601779, 0.798033, 1.107251, 1.702548",\
+ "0.470670, 0.653211, 0.849465, 1.158683, 1.753979",\
+ "0.637153, 0.819694, 1.015949, 1.325166, 1.920461",\
+ "1.228224, 1.410765, 1.607020, 1.916236, 2.511531",\
+ "0.478904, 0.661410, 0.857772, 1.166802, 1.762147",\
+ "0.506657, 0.689164, 0.885526, 1.194556, 1.789901",\
+ "0.558090, 0.740596, 0.936958, 1.245988, 1.841333",\
+ "0.724573, 0.907080, 1.103442, 1.412471, 2.007815",\
+ "1.315644, 1.498150, 1.694512, 2.003541, 2.598884",\
+ "0.559771, 0.741747, 0.937799, 1.246830, 1.842178",\
+ "0.587525, 0.769501, 0.965553, 1.274584, 1.869933",\
+ "0.638957, 0.820933, 1.016985, 1.326016, 1.921365",\
+ "0.805441, 0.987416, 1.183469, 1.492499, 2.087847",\
+ "1.396511, 1.578487, 1.774539, 2.083570, 2.678916",\
+ "0.617410, 0.799295, 0.995343, 1.304075, 1.898826",\
+ "0.645164, 0.827049, 1.023097, 1.331829, 1.926580",\
+ "0.696596, 0.878481, 1.074529, 1.383261, 1.978012",\
+ "0.863080, 1.044965, 1.241013, 1.549745, 2.144494",\
+ "1.454150, 1.636036, 1.832083, 2.140815, 2.735564",\
+ "0.919505, 1.104522, 1.298977, 1.607090, 2.200673",\
+ "0.947259, 1.132276, 1.326731, 1.634844, 2.228427",\
+ "0.998691, 1.183708, 1.378163, 1.686276, 2.279859",\
+ "1.165175, 1.350191, 1.544647, 1.852759, 2.446341",\
+ "1.756245, 1.941262, 2.135717, 2.443830, 3.037410");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\
+ "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523674");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2582*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.547812, 0.726239, 0.906500, 1.192706, 1.743823",\
+ "0.579958, 0.758384, 0.938645, 1.224851, 1.775968",\
+ "0.651865, 0.830291, 1.010552, 1.296758, 1.847875",\
+ "0.908330, 1.086757, 1.267017, 1.553223, 2.104340",\
+ "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\
+ "0.632751, 0.811512, 0.992415, 1.278626, 1.830201",\
+ "0.664896, 0.843657, 1.024560, 1.310771, 1.862346",\
+ "0.736803, 0.915564, 1.096467, 1.382678, 1.934253",\
+ "0.993268, 1.172029, 1.352932, 1.639144, 2.190719",\
+ "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\
+ "0.708657, 0.886955, 1.067224, 1.353223, 1.904374",\
+ "0.740802, 0.919100, 1.099369, 1.385368, 1.936519",\
+ "0.812709, 0.991007, 1.171276, 1.457275, 2.008426",\
+ "1.069174, 1.247472, 1.427741, 1.713740, 2.264891",\
+ "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\
+ "0.763009, 0.941467, 1.121875, 1.407763, 1.958691",\
+ "0.795154, 0.973612, 1.154020, 1.439908, 1.990836",\
+ "0.867061, 1.045519, 1.225927, 1.511815, 2.062743",\
+ "1.123527, 1.301984, 1.482392, 1.768280, 2.319208",\
+ "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\
+ "1.044431, 1.226694, 1.405825, 1.691489, 2.241968",\
+ "1.076576, 1.258839, 1.437970, 1.723634, 2.274114",\
+ "1.148483, 1.330746, 1.509877, 1.795541, 2.346020",\
+ "1.404948, 1.587211, 1.766343, 2.052006, 2.602486",\
+ "2.323924, 2.506187, 2.685318, 2.970983, 3.521462");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\
+ "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\
+ "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\
+ "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.408756, 0.673926, 0.933128, 1.369310, 2.241675",\
+ "0.436510, 0.701680, 0.960881, 1.397064, 2.269429",\
+ "0.487942, 0.753112, 1.012314, 1.448496, 2.320861",\
+ "0.654426, 0.919595, 1.178797, 1.614980, 2.487345",\
+ "1.245496, 1.510666, 1.769868, 2.206050, 3.078415",\
+ "0.497422, 0.762001, 1.021768, 1.457539, 2.329080",\
+ "0.525175, 0.789755, 1.049522, 1.485293, 2.356834",\
+ "0.576608, 0.841187, 1.100955, 1.536725, 2.408266",\
+ "0.743091, 1.007670, 1.267438, 1.703208, 2.574750",\
+ "1.334162, 1.598741, 1.858509, 2.294279, 3.165820",\
+ "0.590228, 0.855124, 1.113494, 1.549703, 2.422122",\
+ "0.617982, 0.882878, 1.141248, 1.577457, 2.449876",\
+ "0.669414, 0.934310, 1.192680, 1.628889, 2.501308",\
+ "0.835898, 1.100793, 1.359163, 1.795373, 2.667792",\
+ "1.426969, 1.691864, 1.950234, 2.386443, 3.258862",\
+ "0.655951, 0.923658, 1.180514, 1.616553, 2.488633",\
+ "0.683705, 0.951412, 1.208267, 1.644307, 2.516387",\
+ "0.735137, 1.002844, 1.259700, 1.695739, 2.567819",\
+ "0.901620, 1.169327, 1.426183, 1.862223, 2.734303",\
+ "1.492691, 1.760398, 2.017254, 2.453294, 3.325373",\
+ "1.001740, 1.304156, 1.551144, 1.985685, 2.854766",\
+ "1.029494, 1.331910, 1.578898, 2.013438, 2.882520",\
+ "1.080926, 1.383342, 1.630330, 2.064871, 2.933952",\
+ "1.247410, 1.549826, 1.796813, 2.231354, 3.100436",\
+ "1.838480, 2.140896, 2.387884, 2.822425, 3.691506");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\
+ "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\
+ "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\
+ "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\
+ "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\
+ "1.523676, 1.523676, 1.523676, 1.523676, 1.523677");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2520*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.315086, 0.347231, 0.419138, 0.675604, 1.594576",\
+ "0.402477, 0.434622, 0.506529, 0.762995, 1.681967",\
+ "0.483396, 0.515541, 0.587448, 0.843914, 1.762885",\
+ "0.541136, 0.573281, 0.645189, 0.901655, 1.820624",\
+ "0.843842, 0.875987, 0.947895, 1.204361, 2.123326");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.034927, 0.080178, 0.211197, 0.703303, 2.463871",\
+ "0.034927, 0.080178, 0.211262, 0.703303, 2.463871",\
+ "0.034927, 0.080178, 0.211506, 0.703303, 2.463871",\
+ "0.034928, 0.080178, 0.211506, 0.703303, 2.463871",\
+ "0.035124, 0.080207, 0.211847, 0.703316, 2.463884");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.288640, 0.316394, 0.367826, 0.534309, 1.125380",\
+ "0.376032, 0.403786, 0.455218, 0.621702, 1.212772",\
+ "0.456902, 0.484656, 0.536088, 0.702571, 1.293642",\
+ "0.514551, 0.542304, 0.593737, 0.760220, 1.351291",\
+ "0.817630, 0.845638, 0.897452, 1.064344, 1.655102");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.036752, 0.066655, 0.142211, 0.440316, 1.524426",\
+ "0.036752, 0.066655, 0.142211, 0.440316, 1.524426",\
+ "0.036752, 0.066655, 0.142211, 0.440316, 1.524300",\
+ "0.036752, 0.066655, 0.142211, 0.440316, 1.524064",\
+ "0.036746, 0.066581, 0.142211, 0.440310, 1.523676");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.499182, 0.679295, 0.866874, 1.168853, 1.751950",\
+ "0.529816, 0.709930, 0.897508, 1.199488, 1.782584",\
+ "0.601083, 0.781197, 0.968775, 1.270755, 1.853851",\
+ "0.856808, 1.036922, 1.224500, 1.526480, 2.109576",\
+ "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\
+ "0.584120, 0.764131, 0.951944, 1.254360, 1.838328",\
+ "0.614754, 0.794765, 0.982578, 1.284994, 1.868962",\
+ "0.686022, 0.866033, 1.053846, 1.356261, 1.940230",\
+ "0.941746, 1.121757, 1.309570, 1.611986, 2.195954",\
+ "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\
+ "0.660032, 0.839574, 1.026753, 1.328956, 1.912500",\
+ "0.690666, 0.870209, 1.057387, 1.359591, 1.943135",\
+ "0.761934, 0.941476, 1.128654, 1.430858, 2.014402",\
+ "1.017658, 1.197201, 1.384379, 1.686583, 2.270127",\
+ "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\
+ "0.714401, 0.894326, 1.081641, 1.383562, 1.966818",\
+ "0.745036, 0.924960, 1.112276, 1.414196, 1.997452",\
+ "0.816303, 0.996228, 1.183543, 1.485464, 2.068719",\
+ "1.072027, 1.251952, 1.439268, 1.741188, 2.324444",\
+ "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\
+ "0.995996, 1.179891, 1.365817, 1.667288, 2.250095",\
+ "1.026630, 1.210525, 1.396451, 1.697923, 2.280730",\
+ "1.097898, 1.281793, 1.467719, 1.769190, 2.351997",\
+ "1.353622, 1.537517, 1.723443, 2.024915, 2.607721",\
+ "2.270849, 2.454743, 2.640669, 2.942141, 3.524948");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.382273, 0.649883, 0.911284, 1.351061, 2.230222",\
+ "0.407140, 0.674750, 0.936142, 1.375888, 2.254987",\
+ "0.455457, 0.723068, 0.984460, 1.424205, 2.303304",\
+ "0.620747, 0.888357, 1.149749, 1.589495, 2.468594",\
+ "1.214576, 1.482187, 1.743588, 2.183365, 3.062526",\
+ "0.470977, 0.737958, 0.999925, 1.439290, 2.317627",\
+ "0.495844, 0.762825, 1.024783, 1.464117, 2.342392",\
+ "0.544161, 0.811142, 1.073101, 1.512434, 2.390709",\
+ "0.709451, 0.976432, 1.238390, 1.677724, 2.555999",\
+ "1.303280, 1.570262, 1.832229, 2.271594, 3.149931",\
+ "0.563919, 0.831278, 1.091970, 1.531536, 2.410669",\
+ "0.588786, 0.856145, 1.116828, 1.556363, 2.435434",\
+ "0.637103, 0.904463, 1.165145, 1.604680, 2.483751",\
+ "0.802393, 1.069752, 1.330435, 1.769970, 2.649041",\
+ "1.396222, 1.663582, 1.924273, 2.363840, 3.242973",\
+ "0.629763, 0.899843, 1.159026, 1.598547, 2.477591",\
+ "0.654629, 0.924710, 1.183884, 1.623374, 2.502355",\
+ "0.702947, 0.973027, 1.232201, 1.671691, 2.550673",\
+ "0.868237, 1.138317, 1.397491, 1.836981, 2.715962",\
+ "1.462066, 1.732146, 1.991329, 2.430851, 3.309894",\
+ "0.976284, 1.280678, 1.529696, 1.967773, 2.843926",\
+ "1.001151, 1.305545, 1.554554, 1.992599, 2.868690",\
+ "1.049468, 1.353863, 1.602872, 2.040917, 2.917008",\
+ "1.214758, 1.519152, 1.768161, 2.206207, 3.082298",\
+ "1.808588, 2.112982, 2.362000, 2.800076, 3.676230");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\
+ "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\
+ "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\
+ "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\
+ "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2461*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.407290, 0.670821, 0.946941, 1.415072, 2.350076",\
+ "0.437925, 0.701456, 0.977575, 1.445707, 2.380711",\
+ "0.509192, 0.772723, 1.048843, 1.516974, 2.451978",\
+ "0.764916, 1.028448, 1.304567, 1.772699, 2.707703",\
+ "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\
+ "0.495484, 0.758362, 1.034508, 1.501788, 2.436010",\
+ "0.526119, 0.788996, 1.065142, 1.532422, 2.466645",\
+ "0.597386, 0.860264, 1.136409, 1.603690, 2.537912",\
+ "0.853111, 1.115988, 1.392134, 1.859414, 2.793636",\
+ "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\
+ "0.583800, 0.847341, 1.122472, 1.589428, 2.522965",\
+ "0.614435, 0.877976, 1.153107, 1.620063, 2.553600",\
+ "0.685702, 0.949243, 1.224374, 1.691330, 2.624867",\
+ "0.941427, 1.204967, 1.480099, 1.947054, 2.880591",\
+ "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\
+ "0.646296, 0.912975, 1.186612, 1.653517, 2.586474",\
+ "0.676931, 0.943609, 1.217247, 1.684151, 2.617109",\
+ "0.748198, 1.014877, 1.288514, 1.755419, 2.688376",\
+ "1.003923, 1.270601, 1.544238, 2.011143, 2.944100",\
+ "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\
+ "0.975422, 1.277290, 1.538476, 2.002961, 2.931930",\
+ "1.006057, 1.307924, 1.569111, 2.033595, 2.962565",\
+ "1.077324, 1.379191, 1.640378, 2.104863, 3.033832",\
+ "1.333048, 1.634916, 1.896102, 2.360587, 3.289557",\
+ "2.250275, 2.552142, 2.813329, 3.277813, 4.206782");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.365228, 0.547285, 0.743519, 1.052700, 1.647184",\
+ "0.390093, 0.572150, 0.768283, 1.077415, 1.671868",\
+ "0.438410, 0.620468, 0.816601, 1.125732, 1.720186",\
+ "0.603700, 0.785757, 0.981890, 1.291023, 1.885478",\
+ "1.197531, 1.379589, 1.575822, 1.885003, 2.479486",\
+ "0.452642, 0.634604, 0.830800, 1.140005, 1.734538",\
+ "0.477507, 0.659469, 0.855564, 1.164720, 1.759222",\
+ "0.525825, 0.707786, 0.903881, 1.213037, 1.807539",\
+ "0.691115, 0.873076, 1.069171, 1.378328, 1.972831",\
+ "1.284946, 1.466908, 1.663103, 1.972308, 2.566839",\
+ "0.533519, 0.714940, 0.910827, 1.220034, 1.814569",\
+ "0.558384, 0.739805, 0.935591, 1.244748, 1.839253",\
+ "0.606701, 0.788123, 0.983908, 1.293066, 1.887571",\
+ "0.771991, 0.953413, 1.149198, 1.458356, 2.052863",\
+ "1.365822, 1.547244, 1.743130, 2.052336, 2.646871",\
+ "0.591165, 0.772777, 0.968562, 1.277504, 1.871665",\
+ "0.616030, 0.797642, 0.993326, 1.302219, 1.896349",\
+ "0.664348, 0.845960, 1.041644, 1.350536, 1.944667",\
+ "0.829637, 1.011249, 1.206933, 1.515826, 2.109958",\
+ "1.423469, 1.605081, 1.800866, 2.109807, 2.703966",\
+ "0.893373, 1.078154, 1.272226, 1.580711, 2.173983",\
+ "0.918238, 1.103019, 1.296990, 1.605426, 2.198667",\
+ "0.966555, 1.151337, 1.345307, 1.653743, 2.246984",\
+ "1.131845, 1.316627, 1.510597, 1.819033, 2.412276",\
+ "1.725676, 1.910458, 2.104529, 2.413014, 3.006285");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\
+ "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\
+ "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\
+ "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\
+ "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2383*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.403312, 0.662871, 0.934506, 1.390667, 2.301835",\
+ "0.433946, 0.693506, 0.965141, 1.421302, 2.332470",\
+ "0.505214, 0.764773, 1.036408, 1.492569, 2.403737",\
+ "0.760938, 1.020497, 1.292132, 1.748294, 2.659461",\
+ "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\
+ "0.491417, 0.750404, 1.022035, 1.477383, 2.387769",\
+ "0.522051, 0.781039, 1.052670, 1.508018, 2.418404",\
+ "0.593319, 0.852306, 1.123937, 1.579285, 2.489671",\
+ "0.849043, 1.108030, 1.379661, 1.835009, 2.745395",\
+ "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\
+ "0.579447, 0.839368, 1.109999, 1.565022, 2.474724",\
+ "0.610081, 0.870003, 1.140634, 1.595656, 2.505359",\
+ "0.681349, 0.941270, 1.211901, 1.666924, 2.576626",\
+ "0.937073, 1.196995, 1.467626, 1.922648, 2.832350",\
+ "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\
+ "0.641668, 0.904980, 1.174137, 1.629096, 2.538233",\
+ "0.672303, 0.935614, 1.204772, 1.659731, 2.568868",\
+ "0.743570, 1.006881, 1.276039, 1.730998, 2.640135",\
+ "0.999294, 1.262606, 1.531763, 1.986722, 2.895859",\
+ "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\
+ "0.969056, 1.269028, 1.525880, 1.978482, 2.883689",\
+ "0.999690, 1.299663, 1.556514, 2.009117, 2.914324",\
+ "1.070957, 1.370930, 1.627782, 2.080384, 2.985591",\
+ "1.326682, 1.626654, 1.883506, 2.336109, 3.241315",\
+ "2.243908, 2.543881, 2.800732, 3.253335, 4.158542");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.363564, 0.545731, 0.741830, 1.051168, 1.646128",\
+ "0.388431, 0.570598, 0.766595, 1.075888, 1.670830",\
+ "0.436748, 0.618916, 0.814913, 1.124206, 1.719148",\
+ "0.602038, 0.784206, 0.980202, 1.289496, 1.884440",\
+ "1.195867, 1.378035, 1.574133, 1.883471, 2.478430",\
+ "0.450984, 0.633050, 0.829111, 1.138473, 1.733482",\
+ "0.475851, 0.657917, 0.853876, 1.163193, 1.758184",\
+ "0.524168, 0.706235, 0.902193, 1.211511, 1.806502",\
+ "0.689458, 0.871524, 1.067483, 1.376801, 1.971793",\
+ "1.283288, 1.465354, 1.661414, 1.970776, 2.565784",\
+ "0.531851, 0.713387, 0.909137, 1.218501, 1.813514",\
+ "0.556719, 0.738254, 0.933903, 1.243222, 1.838215",\
+ "0.605036, 0.786572, 0.982220, 1.291539, 1.886533",\
+ "0.770326, 0.951861, 1.147510, 1.456830, 2.051825",\
+ "1.364155, 1.545691, 1.741441, 2.050804, 2.645815",\
+ "0.589490, 0.771224, 0.966873, 1.275972, 1.870610",\
+ "0.614358, 0.796091, 0.991638, 1.300693, 1.895312",\
+ "0.662675, 0.844408, 1.039955, 1.349010, 1.943630",\
+ "0.827965, 1.009698, 1.205245, 1.514301, 2.108922",\
+ "1.421794, 1.603527, 1.799176, 2.108275, 2.702911",\
+ "0.891585, 1.076602, 1.270536, 1.579180, 2.172930",\
+ "0.916453, 1.101469, 1.295302, 1.603900, 2.197631",\
+ "0.964770, 1.149787, 1.343619, 1.652218, 2.245949",\
+ "1.130060, 1.315076, 1.508909, 1.817508, 2.411241",\
+ "1.723889, 1.908906, 2.102840, 2.411483, 3.005231");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\
+ "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\
+ "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\
+ "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\
+ "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\
+ "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\
+ "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\
+ "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\
+ "1.519015, 1.519015, 1.519015, 1.519016, 1.519017");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2325*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.495595, 0.673935, 0.854281, 1.140468, 1.691221",\
+ "0.526230, 0.704569, 0.884916, 1.171102, 1.721856",\
+ "0.597497, 0.775836, 0.956183, 1.242370, 1.793123",\
+ "0.853221, 1.031561, 1.211908, 1.498094, 2.048847",\
+ "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\
+ "0.580534, 0.758770, 0.939351, 1.225974, 1.777599",\
+ "0.611168, 0.789405, 0.969986, 1.256609, 1.808234",\
+ "0.682435, 0.860672, 1.041253, 1.327876, 1.879501",\
+ "0.938160, 1.116397, 1.296978, 1.583601, 2.135226",\
+ "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\
+ "0.656440, 0.834214, 1.014160, 1.300571, 1.851772",\
+ "0.687074, 0.864848, 1.044795, 1.331205, 1.882406",\
+ "0.758341, 0.936116, 1.116062, 1.402473, 1.953674",\
+ "1.014066, 1.191840, 1.371787, 1.658197, 2.209398",\
+ "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\
+ "0.710792, 0.888959, 1.069026, 1.355165, 1.906089",\
+ "0.741426, 0.919594, 1.099660, 1.385799, 1.936724",\
+ "0.812694, 0.990861, 1.170928, 1.457067, 2.007991",\
+ "1.068418, 1.246586, 1.426652, 1.712791, 2.263715",\
+ "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\
+ "0.992214, 1.174477, 1.353179, 1.638891, 2.189367",\
+ "1.022848, 1.205111, 1.383813, 1.669525, 2.220001",\
+ "1.094115, 1.276379, 1.455081, 1.740793, 2.291269",\
+ "1.349840, 1.532103, 1.710805, 1.996517, 2.546993",\
+ "2.267066, 2.449329, 2.628031, 2.913743, 3.464219");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\
+ "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\
+ "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\
+ "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.380837, 0.645836, 0.904865, 1.341130, 2.213276",\
+ "0.405704, 0.670703, 0.929723, 1.365952, 2.238030",\
+ "0.454021, 0.719020, 0.978040, 1.414270, 2.286347",\
+ "0.619311, 0.884310, 1.143330, 1.579559, 2.451637",\
+ "1.213140, 1.478139, 1.737169, 2.173433, 3.045579",\
+ "0.469502, 0.733911, 0.993506, 1.429358, 2.300681",\
+ "0.494369, 0.758778, 1.018363, 1.454181, 2.325435",\
+ "0.542686, 0.807095, 1.066681, 1.502498, 2.373752",\
+ "0.707976, 0.972385, 1.231971, 1.667788, 2.539042",\
+ "1.301806, 1.566214, 1.825810, 2.261662, 3.132985",\
+ "0.562309, 0.827204, 1.085541, 1.521602, 2.393723",\
+ "0.587176, 0.852071, 1.110399, 1.546425, 2.418477",\
+ "0.635493, 0.900389, 1.158716, 1.594742, 2.466794",\
+ "0.800783, 1.065678, 1.324006, 1.760032, 2.632084",\
+ "1.394613, 1.659508, 1.917845, 2.353905, 3.226027",\
+ "0.628031, 0.895738, 1.152596, 1.588608, 2.460633",\
+ "0.652898, 0.920605, 1.177454, 1.613431, 2.485386",\
+ "0.701216, 0.968923, 1.225771, 1.661748, 2.533704",\
+ "0.866506, 1.134212, 1.391061, 1.827038, 2.698993",\
+ "1.460335, 1.728042, 1.984900, 2.420912, 3.292936",\
+ "0.973821, 1.276237, 1.523234, 1.957809, 2.826960",\
+ "0.998688, 1.301104, 1.548091, 1.982632, 2.851713",\
+ "1.047005, 1.349421, 1.596409, 2.030949, 2.900031",\
+ "1.212295, 1.514711, 1.761698, 2.196239, 3.065320",\
+ "1.806124, 2.108541, 2.355538, 2.790113, 3.659263");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\
+ "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\
+ "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\
+ "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\
+ "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\
+ "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\
+ "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\
+ "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\
+ "1.519015, 1.519015, 1.519015, 1.519015, 1.519015");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2267*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.132999, 0.164048, 0.235821, 0.492102, 1.411098",\
+ "0.221194, 0.252231, 0.324016, 0.580346, 1.499024",\
+ "0.309537, 0.340556, 0.412339, 0.668869, 1.587106",\
+ "0.372125, 0.403153, 0.474871, 0.731698, 1.650402",\
+ "0.701985, 0.733051, 0.804557, 1.061823, 1.982165");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\
+ "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\
+ "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\
+ "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\
+ "0.031515, 0.077660, 0.209649, 0.699350, 2.448223");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.172647, 0.198025, 0.247447, 0.413179, 1.004020",\
+ "0.260051, 0.285429, 0.334851, 0.500582, 1.091424",\
+ "0.340949, 0.366324, 0.415751, 0.581486, 1.172337",\
+ "0.398613, 0.423981, 0.473417, 0.639160, 1.230028",\
+ "0.700957, 0.726326, 0.775791, 0.941604, 1.532645");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.028580, 0.057560, 0.134856, 0.434927, 1.516730",\
+ "0.028580, 0.057560, 0.134856, 0.434927, 1.516730",\
+ "0.028580, 0.057560, 0.134856, 0.434975, 1.516730",\
+ "0.028580, 0.057560, 0.134856, 0.435062, 1.516730",\
+ "0.028580, 0.057561, 0.134856, 0.435749, 1.516730");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.079929, 0.111758, 0.183223, 0.439138, 1.359203",\
+ "0.167497, 0.199454, 0.270769, 0.526908, 1.444562",\
+ "0.264286, 0.298668, 0.370756, 0.626584, 1.547694",\
+ "0.439501, 0.480020, 0.554277, 0.809849, 1.732299",\
+ "0.736451, 0.793429, 0.877676, 1.133252, 2.048527");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.033688, 0.079103, 0.210853, 0.705450, 2.481454",\
+ "0.034938, 0.079398, 0.210853, 0.707160, 2.481454",\
+ "0.042553, 0.084403, 0.210853, 0.707160, 2.481454",\
+ "0.062025, 0.097740, 0.214926, 0.707160, 2.481454",\
+ "0.107816, 0.136398, 0.233803, 0.707160, 2.481454");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.118927, 0.147104, 0.198913, 0.365810, 0.957538",\
+ "0.198088, 0.226133, 0.277877, 0.444754, 1.035269",\
+ "0.300437, 0.331131, 0.384010, 0.550764, 1.143163",\
+ "0.474766, 0.514213, 0.573035, 0.741315, 1.332791",\
+ "0.755439, 0.816369, 0.892028, 1.065959, 1.655414");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.037147, 0.066922, 0.142202, 0.440625, 1.525476",\
+ "0.037147, 0.066922, 0.142202, 0.440625, 1.525476",\
+ "0.046795, 0.072955, 0.144989, 0.440625, 1.525476",\
+ "0.074873, 0.097054, 0.159133, 0.443319, 1.525476",\
+ "0.131163, 0.155817, 0.206305, 0.453921, 1.527125");
+ }
+
+ } /* end of arc padmux2ast_i[3]_obs_ctrl_o[11]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.076002, 0.106508, 0.177677, 0.433841, 1.352120",\
+ "0.163173, 0.193992, 0.265018, 0.521506, 1.439207",\
+ "0.258934, 0.291253, 0.363111, 0.618813, 1.536303",\
+ "0.430665, 0.469075, 0.541536, 0.798208, 1.718362",\
+ "0.721771, 0.774421, 0.855976, 1.109381, 2.025527");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.030664, 0.077525, 0.209536, 0.696987, 2.440521",\
+ "0.032038, 0.077878, 0.209536, 0.696987, 2.440521",\
+ "0.038668, 0.082173, 0.210178, 0.699757, 2.449750",\
+ "0.056119, 0.094147, 0.214335, 0.699757, 2.460771",\
+ "0.095850, 0.132052, 0.230566, 0.703608, 2.462313");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.085902, 0.110542, 0.159236, 0.324759, 0.917124",\
+ "0.171172, 0.195634, 0.244356, 0.409704, 1.001295",\
+ "0.269100, 0.297524, 0.347992, 0.513168, 1.105193",\
+ "0.434670, 0.473174, 0.529868, 0.695133, 1.285706",\
+ "0.702119, 0.762927, 0.838318, 1.010679, 1.597765");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168");
+ values ( "0.029180, 0.058574, 0.135500, 0.435380, 1.519944",\
+ "0.030330, 0.058789, 0.135664, 0.436655, 1.520555",\
+ "0.042270, 0.067457, 0.139493, 0.437267, 1.520555",\
+ "0.069987, 0.091747, 0.153270, 0.440379, 1.520568",\
+ "0.124960, 0.149736, 0.200354, 0.450127, 1.523278");
+ }
+
+ } /* end of arc padmux2ast_i[3]_obs_ctrl_o[11]_una_min*/
+
+} /* end of pin obs_ctrl_o[11] */
+
+pin("obs_ctrl_o[10]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.156168 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002440 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[10];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.570547, 0.750750, 0.938240, 1.240232, 1.823744",\
+ "0.598946, 0.779149, 0.966639, 1.268632, 1.852144",\
+ "0.670479, 0.850682, 1.038172, 1.340165, 1.923677",\
+ "0.926915, 1.107118, 1.294608, 1.596601, 2.180113",\
+ "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\
+ "0.655485, 0.836033, 1.024249, 1.326245, 1.910123",\
+ "0.683885, 0.864432, 1.052648, 1.354644, 1.938522",\
+ "0.755418, 0.935965, 1.124181, 1.426177, 2.010055",\
+ "1.011854, 1.192401, 1.380617, 1.682613, 2.266491",\
+ "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\
+ "0.731397, 0.911476, 1.099057, 1.400841, 1.984295",\
+ "0.759797, 0.939876, 1.127457, 1.429241, 2.012694",\
+ "0.831330, 1.011409, 1.198990, 1.500774, 2.084227",\
+ "1.087766, 1.267845, 1.455426, 1.757210, 2.340663",\
+ "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\
+ "0.785767, 0.965988, 1.153708, 1.455381, 2.038612",\
+ "0.814166, 0.994387, 1.182108, 1.483781, 2.067012",\
+ "0.885699, 1.065920, 1.253641, 1.555314, 2.138545",\
+ "1.142135, 1.322356, 1.510077, 1.811749, 2.394980",\
+ "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\
+ "1.067361, 1.251256, 1.437659, 1.739108, 2.321890",\
+ "1.095761, 1.279655, 1.466058, 1.767507, 2.350289",\
+ "1.167294, 1.351188, 1.537591, 1.839040, 2.421822",\
+ "1.423730, 1.607624, 1.794027, 2.095476, 2.678258",\
+ "2.327707, 2.511601, 2.698004, 2.999453, 3.582235");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.426873, 0.694659, 0.956239, 1.395936, 2.275331",\
+ "0.448702, 0.716487, 0.978067, 1.417764, 2.297159",\
+ "0.498842, 0.766628, 1.028208, 1.467905, 2.347300",\
+ "0.665219, 0.933004, 1.194584, 1.634281, 2.513676",\
+ "1.246642, 1.514428, 1.776008, 2.215705, 3.095100",\
+ "0.515577, 0.782734, 1.044880, 1.484165, 2.362736",\
+ "0.537406, 0.804562, 1.066708, 1.505994, 2.384564",\
+ "0.587546, 0.854703, 1.116849, 1.556134, 2.434705",\
+ "0.753923, 1.021079, 1.283225, 1.722511, 2.601081",\
+ "1.335346, 1.602503, 1.864649, 2.303934, 3.182505",\
+ "0.608520, 0.875879, 1.136606, 1.576329, 2.455778",\
+ "0.630348, 0.897707, 1.158434, 1.598158, 2.477606",\
+ "0.680488, 0.947848, 1.208574, 1.648298, 2.527747",\
+ "0.846865, 1.114224, 1.374951, 1.814675, 2.694123",\
+ "1.428288, 1.695648, 1.956374, 2.396098, 3.275547",\
+ "0.674363, 0.944443, 1.203625, 1.643180, 2.522289",\
+ "0.696192, 0.966272, 1.225454, 1.665008, 2.544117",\
+ "0.746332, 1.016412, 1.275594, 1.715149, 2.594258",\
+ "0.912709, 1.182789, 1.441971, 1.881525, 2.760634",\
+ "1.494132, 1.764212, 2.023394, 2.462949, 3.342058",\
+ "1.020885, 1.325279, 1.574288, 2.012334, 2.888425",\
+ "1.042713, 1.347107, 1.596116, 2.034162, 2.910253",\
+ "1.092854, 1.397248, 1.646257, 2.084302, 2.960393",\
+ "1.259230, 1.563624, 1.812633, 2.250679, 3.126770",\
+ "1.840654, 2.145048, 2.394057, 2.832103, 3.708194");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\
+ "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\
+ "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\
+ "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\
+ "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2689*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.478652, 0.742226, 1.018498, 1.487228, 2.424687",\
+ "0.507052, 0.770625, 1.046898, 1.515627, 2.453087",\
+ "0.578584, 0.842158, 1.118431, 1.587160, 2.524619",\
+ "0.835020, 1.098594, 1.374866, 1.843596, 2.781055",\
+ "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\
+ "0.566846, 0.829767, 1.106066, 1.573943, 2.510621",\
+ "0.595246, 0.858166, 1.134465, 1.602343, 2.539020",\
+ "0.666779, 0.929699, 1.205998, 1.673875, 2.610553",\
+ "0.923215, 1.186135, 1.462434, 1.930311, 2.866989",\
+ "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\
+ "0.655163, 0.918747, 1.194031, 1.661566, 2.597576",\
+ "0.683562, 0.947146, 1.222430, 1.689965, 2.625975",\
+ "0.755095, 1.018679, 1.293963, 1.761498, 2.697508",\
+ "1.011531, 1.275115, 1.550399, 2.017934, 2.953944",\
+ "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\
+ "0.717659, 0.984382, 1.258171, 1.725480, 2.661085",\
+ "0.746058, 1.012781, 1.286570, 1.753879, 2.689484",\
+ "0.817591, 1.084314, 1.358103, 1.825412, 2.761017",\
+ "1.074027, 1.340750, 1.614539, 2.081847, 3.017453",\
+ "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\
+ "1.046784, 1.348713, 1.610038, 2.074829, 3.006541",\
+ "1.075184, 1.377112, 1.638437, 2.103229, 3.034940",\
+ "1.146717, 1.448645, 1.709970, 2.174761, 3.106473",\
+ "1.403152, 1.705081, 1.966406, 2.431197, 3.362909",\
+ "2.307129, 2.609058, 2.870384, 3.335176, 4.266890");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.409826, 0.592258, 0.788650, 1.097704, 1.692512",\
+ "0.431655, 0.614087, 0.810479, 1.119532, 1.714340",\
+ "0.481795, 0.664227, 0.860619, 1.169672, 1.764480",\
+ "0.648172, 0.830604, 1.026996, 1.336049, 1.930856",\
+ "1.229595, 1.412027, 1.608419, 1.917472, 2.512278",\
+ "0.497241, 0.679644, 0.876143, 1.185009, 1.779865",\
+ "0.519070, 0.701472, 0.897972, 1.206837, 1.801694",\
+ "0.569210, 0.751613, 0.948112, 1.256977, 1.851834",\
+ "0.735586, 0.917989, 1.114489, 1.423354, 2.018209",\
+ "1.317010, 1.499413, 1.695912, 2.004777, 2.599632",\
+ "0.578118, 0.759980, 0.956170, 1.265037, 1.859897",\
+ "0.599946, 0.781809, 0.977999, 1.286866, 1.881726",\
+ "0.650086, 0.831949, 1.028139, 1.337006, 1.931865",\
+ "0.816463, 0.998326, 1.194516, 1.503382, 2.098241",\
+ "1.397886, 1.579749, 1.775939, 2.084805, 2.679663",\
+ "0.635764, 0.817529, 1.013714, 1.322282, 1.916544",\
+ "0.657592, 0.839357, 1.035542, 1.344111, 1.938373",\
+ "0.707733, 0.889498, 1.085683, 1.394251, 1.988513",\
+ "0.874109, 1.055874, 1.252059, 1.560627, 2.154888",\
+ "1.455533, 1.637298, 1.833483, 2.142051, 2.736311",\
+ "0.937972, 1.122753, 1.317348, 1.625297, 2.218391",\
+ "0.959800, 1.144582, 1.339176, 1.647125, 2.240220",\
+ "1.009940, 1.194722, 1.389317, 1.697266, 2.290360",\
+ "1.176317, 1.361099, 1.555693, 1.863642, 2.456735",\
+ "1.757740, 1.942522, 2.137117, 2.445065, 3.038157");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\
+ "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\
+ "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\
+ "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\
+ "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2623*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.474677, 0.734306, 1.006178, 1.463058, 2.376818",\
+ "0.503076, 0.762705, 1.034578, 1.491457, 2.405217",\
+ "0.574609, 0.834238, 1.106111, 1.562990, 2.476750",\
+ "0.831045, 1.090674, 1.362546, 1.819426, 2.733185",\
+ "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\
+ "0.562782, 0.821840, 1.093709, 1.549773, 2.462751",\
+ "0.591181, 0.850239, 1.122108, 1.578173, 2.491151",\
+ "0.662714, 0.921772, 1.193641, 1.649706, 2.562684",\
+ "0.919150, 1.178208, 1.450077, 1.906141, 2.819119",\
+ "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\
+ "0.650812, 0.910805, 1.181673, 1.637396, 2.549706",\
+ "0.679211, 0.939205, 1.210072, 1.665795, 2.578106",\
+ "0.750744, 1.010738, 1.281605, 1.737328, 2.649639",\
+ "1.007180, 1.267174, 1.538041, 1.993764, 2.906074",\
+ "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\
+ "0.713033, 0.976419, 1.245811, 1.701310, 2.613215",\
+ "0.741432, 1.004818, 1.274210, 1.729709, 2.641615",\
+ "0.812965, 1.076351, 1.345743, 1.801242, 2.713148",\
+ "1.069401, 1.332787, 1.602179, 2.057678, 2.969583",\
+ "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\
+ "1.040421, 1.340494, 1.597558, 2.050611, 2.958672",\
+ "1.068820, 1.368893, 1.625957, 2.079010, 2.987071",\
+ "1.140353, 1.440426, 1.697490, 2.150543, 3.058604",\
+ "1.396789, 1.696862, 1.953926, 2.406978, 3.315039",\
+ "2.300766, 2.600840, 2.857904, 3.310957, 4.219019");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\
+ "0.239906, 0.239905, 0.239905, 0.239905, 0.239905",\
+ "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\
+ "2.463890, 2.463889, 2.463888, 2.463885, 2.463879");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.408165, 0.590706, 0.786961, 1.096178, 1.691475",\
+ "0.429993, 0.612534, 0.808789, 1.118006, 1.713303",\
+ "0.480134, 0.662675, 0.858930, 1.168147, 1.763443",\
+ "0.646510, 0.829051, 1.025306, 1.334523, 1.929818",\
+ "1.227934, 1.410475, 1.606730, 1.915946, 2.511241",\
+ "0.495585, 0.678091, 0.874454, 1.183483, 1.778828",\
+ "0.517413, 0.699920, 0.896282, 1.205312, 1.800657",\
+ "0.567554, 0.750060, 0.946422, 1.255452, 1.850797",\
+ "0.733930, 0.916437, 1.112799, 1.421828, 2.017172",\
+ "1.315354, 1.497860, 1.694222, 2.003251, 2.598594",\
+ "0.576453, 0.758428, 0.954480, 1.263512, 1.858860",\
+ "0.598281, 0.780257, 0.976309, 1.285340, 1.880688",\
+ "0.648421, 0.830397, 1.026449, 1.335480, 1.930828",\
+ "0.814798, 0.996773, 1.192826, 1.501856, 2.097203",\
+ "1.396221, 1.578197, 1.774249, 2.083280, 2.678626",\
+ "0.634091, 0.815977, 1.012024, 1.320757, 1.915507",\
+ "0.655920, 0.837805, 1.033853, 1.342585, 1.937336",\
+ "0.706060, 0.887945, 1.083993, 1.392725, 1.987476",\
+ "0.872437, 1.054322, 1.250370, 1.559102, 2.153851",\
+ "1.453860, 1.635746, 1.831793, 2.140525, 2.735273",\
+ "0.936187, 1.121203, 1.315658, 1.623772, 2.217354",\
+ "0.958015, 1.143031, 1.337487, 1.645600, 2.239183",\
+ "1.008155, 1.193172, 1.387627, 1.695740, 2.289323",\
+ "1.174532, 1.359548, 1.554004, 1.862116, 2.455698",\
+ "1.755955, 1.940972, 2.135427, 2.443540, 3.037120");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\
+ "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\
+ "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\
+ "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\
+ "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\
+ "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\
+ "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523142");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2570*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.566961, 0.745387, 0.925648, 1.211854, 1.762971",\
+ "0.595360, 0.773787, 0.954047, 1.240253, 1.791370",\
+ "0.666893, 0.845320, 1.025580, 1.311786, 1.862903",\
+ "0.923329, 1.101756, 1.282016, 1.568222, 2.119339",\
+ "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\
+ "0.651899, 0.830660, 1.011563, 1.297774, 1.849349",\
+ "0.680298, 0.859059, 1.039962, 1.326174, 1.877749",\
+ "0.751831, 0.930592, 1.111495, 1.397707, 1.949282",\
+ "1.008267, 1.187028, 1.367931, 1.654143, 2.205718",\
+ "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\
+ "0.727805, 0.906103, 1.086372, 1.372371, 1.923522",\
+ "0.756204, 0.934502, 1.114771, 1.400770, 1.951921",\
+ "0.827737, 1.006035, 1.186304, 1.472303, 2.023454",\
+ "1.084173, 1.262471, 1.442740, 1.728739, 2.279890",\
+ "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\
+ "0.782157, 0.960615, 1.141023, 1.426911, 1.977839",\
+ "0.810557, 0.989014, 1.169422, 1.455310, 2.006238",\
+ "0.882089, 1.060547, 1.240955, 1.526843, 2.077771",\
+ "1.138525, 1.316983, 1.497391, 1.783279, 2.334207",\
+ "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\
+ "1.063579, 1.245842, 1.424973, 1.710637, 2.261117",\
+ "1.091979, 1.274241, 1.453373, 1.739037, 2.289516",\
+ "1.163512, 1.345774, 1.524906, 1.810570, 2.361049",\
+ "1.419947, 1.602210, 1.781342, 2.067005, 2.617485",\
+ "2.323924, 2.506187, 2.685318, 2.970983, 3.521462");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\
+ "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\
+ "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\
+ "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.425437, 0.690607, 0.949809, 1.385991, 2.258357",\
+ "0.447266, 0.712435, 0.971637, 1.407820, 2.280185",\
+ "0.497406, 0.762576, 1.021778, 1.457960, 2.330325",\
+ "0.663783, 0.928952, 1.188154, 1.624336, 2.496702",\
+ "1.245206, 1.510376, 1.769578, 2.205760, 3.078125",\
+ "0.514103, 0.778682, 1.038450, 1.474220, 2.345762",\
+ "0.535931, 0.800510, 1.060278, 1.496048, 2.367590",\
+ "0.586072, 0.850651, 1.110419, 1.546189, 2.417730",\
+ "0.752448, 1.017027, 1.276795, 1.712565, 2.584107",\
+ "1.333872, 1.598451, 1.858219, 2.293989, 3.165530",\
+ "0.606910, 0.871805, 1.130175, 1.566384, 2.438803",\
+ "0.628738, 0.893633, 1.152003, 1.588213, 2.460632",\
+ "0.678878, 0.943774, 1.202144, 1.638353, 2.510772",\
+ "0.845255, 1.110150, 1.368520, 1.804730, 2.677149",\
+ "1.426679, 1.691574, 1.949944, 2.386153, 3.258572",\
+ "0.672632, 0.940339, 1.197195, 1.633235, 2.505315",\
+ "0.694461, 0.962168, 1.219023, 1.655063, 2.527143",\
+ "0.744601, 1.012308, 1.269164, 1.705203, 2.577283",\
+ "0.910977, 1.178684, 1.435540, 1.871580, 2.743660",\
+ "1.492401, 1.760108, 2.016964, 2.453003, 3.325083",\
+ "1.018422, 1.320838, 1.567825, 2.002366, 2.871448",\
+ "1.040250, 1.342666, 1.589653, 2.024194, 2.893276",\
+ "1.090390, 1.392806, 1.639794, 2.074335, 2.943416",\
+ "1.256767, 1.559183, 1.806170, 2.240711, 3.109793",\
+ "1.838190, 2.140606, 2.387594, 2.822135, 3.691216");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\
+ "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\
+ "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\
+ "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\
+ "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\
+ "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\
+ "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\
+ "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\
+ "1.523144, 1.523144, 1.523144, 1.523144, 1.523144");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2508*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.334234, 0.362633, 0.434167, 0.690603, 1.594576",\
+ "0.421625, 0.450024, 0.521558, 0.777994, 1.681967",\
+ "0.502544, 0.530943, 0.602477, 0.858913, 1.762885",\
+ "0.560284, 0.588684, 0.660217, 0.916654, 1.820624",\
+ "0.862990, 0.891389, 0.962923, 1.219360, 2.123326");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.059999, 0.108036, 0.239907, 0.732038, 2.463871",\
+ "0.059999, 0.108053, 0.240000, 0.732038, 2.463871",\
+ "0.059999, 0.108094, 0.240218, 0.732038, 2.463871",\
+ "0.059999, 0.108094, 0.240218, 0.732038, 2.463871",\
+ "0.060087, 0.108094, 0.240545, 0.732051, 2.463884");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.305321, 0.327149, 0.377290, 0.543666, 1.125090",\
+ "0.392714, 0.414542, 0.464682, 0.631059, 1.212482",\
+ "0.473583, 0.495412, 0.545552, 0.711928, 1.293352",\
+ "0.531232, 0.553060, 0.603201, 0.769577, 1.351001",\
+ "0.834460, 0.856477, 0.906940, 1.073696, 1.654812");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.053502, 0.082236, 0.159102, 0.457392, 1.523894",\
+ "0.053502, 0.082236, 0.159102, 0.457392, 1.523894",\
+ "0.053502, 0.082236, 0.159102, 0.457392, 1.523767",\
+ "0.053502, 0.082236, 0.159102, 0.457392, 1.523532",\
+ "0.053458, 0.082179, 0.159102, 0.457388, 1.523144");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.517252, 0.697365, 0.884944, 1.186924, 1.770020",\
+ "0.545074, 0.725188, 0.912766, 1.214746, 1.797842",\
+ "0.616076, 0.796190, 0.983769, 1.285748, 1.868845",\
+ "0.871803, 1.051917, 1.239495, 1.541475, 2.124571",\
+ "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\
+ "0.602190, 0.782201, 0.970014, 1.272430, 1.856398",\
+ "0.630012, 0.810023, 0.997836, 1.300252, 1.884220",\
+ "0.701015, 0.881026, 1.068839, 1.371255, 1.955223",\
+ "0.956741, 1.136753, 1.324565, 1.626981, 2.210949",\
+ "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\
+ "0.678102, 0.857644, 1.044823, 1.347027, 1.930570",\
+ "0.705924, 0.885467, 1.072645, 1.374849, 1.958393",\
+ "0.776927, 0.956469, 1.143648, 1.445851, 2.029395",\
+ "1.032653, 1.212196, 1.399374, 1.701578, 2.285122",\
+ "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\
+ "0.732471, 0.912396, 1.099712, 1.401632, 1.984888",\
+ "0.760294, 0.940218, 1.127534, 1.429455, 2.012710",\
+ "0.831296, 1.011221, 1.198536, 1.500457, 2.083713",\
+ "1.087023, 1.266947, 1.454263, 1.756184, 2.339439",\
+ "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\
+ "1.014066, 1.197961, 1.383887, 1.685358, 2.268165",\
+ "1.041888, 1.225783, 1.411709, 1.713181, 2.295988",\
+ "1.112891, 1.296786, 1.482712, 1.784183, 2.366990",\
+ "1.368618, 1.552512, 1.738438, 2.039910, 2.622717",\
+ "2.270849, 2.454743, 2.640669, 2.942141, 3.524948");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.397272, 0.664882, 0.926275, 1.366020, 2.245119",\
+ "0.417207, 0.684818, 0.946210, 1.385955, 2.265054",\
+ "0.464850, 0.732461, 0.993853, 1.433599, 2.312697",\
+ "0.630183, 0.897793, 1.159185, 1.598931, 2.478030",\
+ "1.214286, 1.481897, 1.743298, 2.183075, 3.062236",\
+ "0.485976, 0.752957, 1.014915, 1.454249, 2.332524",\
+ "0.505911, 0.772893, 1.034851, 1.474185, 2.352459",\
+ "0.553554, 0.820536, 1.082494, 1.521828, 2.400102",\
+ "0.718887, 0.985868, 1.247826, 1.687160, 2.565435",\
+ "1.302990, 1.569972, 1.831939, 2.271304, 3.149641",\
+ "0.578918, 0.846278, 1.106960, 1.546495, 2.425566",\
+ "0.598853, 0.866213, 1.126895, 1.566430, 2.445501",\
+ "0.646497, 0.913856, 1.174538, 1.614074, 2.493144",\
+ "0.811829, 1.079188, 1.339871, 1.779406, 2.658477",\
+ "1.395933, 1.663292, 1.923983, 2.363550, 3.242683",\
+ "0.644762, 0.914842, 1.174016, 1.613506, 2.492487",\
+ "0.664697, 0.934777, 1.193951, 1.633442, 2.512423",\
+ "0.712340, 0.982420, 1.241595, 1.681085, 2.560066",\
+ "0.877673, 1.147753, 1.406927, 1.846417, 2.725398",\
+ "1.461776, 1.731856, 1.991039, 2.430561, 3.309604",\
+ "0.991283, 1.295677, 1.544687, 1.982732, 2.858823",\
+ "1.011218, 1.315613, 1.564622, 2.002667, 2.878758",\
+ "1.058862, 1.363256, 1.612265, 2.050310, 2.926401",\
+ "1.224194, 1.528588, 1.777597, 2.215642, 3.091733",\
+ "1.808298, 2.112692, 2.361710, 2.799787, 3.675940");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2444*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.425360, 0.688891, 0.965011, 1.433143, 2.368146",\
+ "0.453182, 0.716714, 0.992833, 1.460965, 2.395969",\
+ "0.524185, 0.787716, 1.063836, 1.531968, 2.466971",\
+ "0.779912, 1.043443, 1.319562, 1.787694, 2.722698",\
+ "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\
+ "0.513554, 0.776432, 1.052578, 1.519858, 2.454080",\
+ "0.541377, 0.804254, 1.080400, 1.547680, 2.481903",\
+ "0.612379, 0.875257, 1.151402, 1.618683, 2.552905",\
+ "0.868106, 1.130983, 1.407129, 1.874409, 2.808632",\
+ "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\
+ "0.601870, 0.865411, 1.140543, 1.607498, 2.541035",\
+ "0.629693, 0.893234, 1.168365, 1.635320, 2.568858",\
+ "0.700695, 0.964236, 1.239367, 1.706323, 2.639860",\
+ "0.956422, 1.219963, 1.495094, 1.962050, 2.895587",\
+ "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\
+ "0.664366, 0.931045, 1.204682, 1.671587, 2.604544",\
+ "0.692189, 0.958867, 1.232504, 1.699409, 2.632367",\
+ "0.763191, 1.029870, 1.303507, 1.770412, 2.703369",\
+ "1.018918, 1.285596, 1.559234, 2.026138, 2.959096",\
+ "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\
+ "0.993492, 1.295360, 1.556546, 2.021031, 2.950000",\
+ "1.021315, 1.323182, 1.584368, 2.048853, 2.977823",\
+ "1.092317, 1.394185, 1.655371, 2.119856, 3.048825",\
+ "1.348044, 1.649911, 1.911098, 2.375582, 3.304552",\
+ "2.250275, 2.552142, 2.813329, 3.277813, 4.206782");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.380225, 0.562282, 0.758415, 1.067547, 1.662000",\
+ "0.400160, 0.582218, 0.778351, 1.087482, 1.681936",\
+ "0.447803, 0.629861, 0.825994, 1.135126, 1.729579",\
+ "0.613136, 0.795193, 0.991326, 1.300459, 1.894914",\
+ "1.197241, 1.379299, 1.575532, 1.884713, 2.479196",\
+ "0.467640, 0.649601, 0.845696, 1.154852, 1.749354",\
+ "0.487575, 0.669536, 0.865631, 1.174787, 1.769289",\
+ "0.535218, 0.717180, 0.913275, 1.222431, 1.816933",\
+ "0.700550, 0.882512, 1.078607, 1.387764, 1.982267",\
+ "1.284656, 1.466618, 1.662813, 1.972018, 2.566549",\
+ "0.548516, 0.729938, 0.925723, 1.234881, 1.829386",\
+ "0.568451, 0.749873, 0.945658, 1.254816, 1.849321",\
+ "0.616094, 0.797516, 0.993302, 1.302459, 1.896965",\
+ "0.781427, 0.962848, 1.158634, 1.467792, 2.062299",\
+ "1.365532, 1.546954, 1.742840, 2.052047, 2.646581",\
+ "0.606162, 0.787775, 0.983459, 1.292351, 1.886481",\
+ "0.626098, 0.807710, 1.003394, 1.312286, 1.906416",\
+ "0.673741, 0.855353, 1.051037, 1.359930, 1.954060",\
+ "0.839073, 1.020685, 1.216369, 1.525263, 2.119395",\
+ "1.423179, 1.604791, 1.800576, 2.109517, 2.703676",\
+ "0.908370, 1.093152, 1.287122, 1.595558, 2.188799",\
+ "0.928305, 1.113087, 1.307057, 1.615493, 2.208735",\
+ "0.975949, 1.160730, 1.354700, 1.663137, 2.256378",\
+ "1.141281, 1.326062, 1.520033, 1.828470, 2.421713",\
+ "1.725386, 1.910168, 2.104239, 2.412724, 3.005995");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2368*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.421382, 0.680941, 0.952576, 1.408738, 2.319905",\
+ "0.449204, 0.708764, 0.980399, 1.436560, 2.347728",\
+ "0.520207, 0.779766, 1.051401, 1.507563, 2.418730",\
+ "0.775933, 1.035493, 1.307128, 1.763289, 2.674457",\
+ "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\
+ "0.509487, 0.768474, 1.040105, 1.495453, 2.405839",\
+ "0.537309, 0.796296, 1.067928, 1.523275, 2.433661",\
+ "0.608312, 0.867299, 1.138930, 1.594278, 2.504664",\
+ "0.864038, 1.123026, 1.394657, 1.850005, 2.760391",\
+ "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\
+ "0.597517, 0.857438, 1.128069, 1.583092, 2.492794",\
+ "0.625339, 0.885261, 1.155892, 1.610914, 2.520617",\
+ "0.696342, 0.956263, 1.226894, 1.681917, 2.591619",\
+ "0.952068, 1.211990, 1.482621, 1.937644, 2.847346",\
+ "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\
+ "0.659738, 0.923050, 1.192207, 1.647166, 2.556303",\
+ "0.687560, 0.950872, 1.220030, 1.674989, 2.584126",\
+ "0.758563, 1.021875, 1.291032, 1.745991, 2.655128",\
+ "1.014290, 1.277601, 1.546759, 2.001718, 2.910855",\
+ "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\
+ "0.987126, 1.287098, 1.543950, 1.996553, 2.901759",\
+ "1.014948, 1.314920, 1.571772, 2.024375, 2.929582",\
+ "1.085950, 1.385923, 1.642775, 2.095378, 3.000584",\
+ "1.341677, 1.641650, 1.898501, 2.351104, 3.256311",\
+ "2.243908, 2.543881, 2.800732, 3.253335, 4.158542");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\
+ "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\
+ "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\
+ "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\
+ "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\
+ "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\
+ "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\
+ "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.378563, 0.560731, 0.756728, 1.066021, 1.660963",\
+ "0.398499, 0.580666, 0.776663, 1.085956, 1.680898",\
+ "0.446142, 0.628309, 0.824306, 1.133599, 1.728542",\
+ "0.611474, 0.793641, 0.989638, 1.298932, 1.893877",\
+ "1.195578, 1.377745, 1.573843, 1.883181, 2.478140",\
+ "0.465983, 0.648049, 0.844008, 1.153326, 1.748316",\
+ "0.485919, 0.667985, 0.863944, 1.173261, 1.768251",\
+ "0.533562, 0.715628, 0.911587, 1.220904, 1.815895",\
+ "0.698894, 0.880960, 1.076919, 1.386237, 1.981230",\
+ "1.282998, 1.465064, 1.661124, 1.970486, 2.565494",\
+ "0.546851, 0.728386, 0.924035, 1.233354, 1.828348",\
+ "0.566786, 0.748322, 0.943970, 1.253289, 1.848283",\
+ "0.614429, 0.795965, 0.991614, 1.300933, 1.895927",\
+ "0.779762, 0.961297, 1.156946, 1.466266, 2.061262",\
+ "1.363865, 1.545401, 1.741151, 2.050514, 2.645525",\
+ "0.604490, 0.786223, 0.981770, 1.290825, 1.885444",\
+ "0.624425, 0.806158, 1.001706, 1.310760, 1.905379",\
+ "0.672068, 0.853802, 1.049349, 1.358404, 1.953023",\
+ "0.837401, 1.019134, 1.214681, 1.523737, 2.118358",\
+ "1.421504, 1.603237, 1.798886, 2.107985, 2.702621",\
+ "0.906585, 1.091602, 1.285434, 1.594033, 2.187764",\
+ "0.926520, 1.111537, 1.305369, 1.613968, 2.207699",\
+ "0.974163, 1.159180, 1.353012, 1.661611, 2.255342",\
+ "1.139496, 1.324512, 1.518345, 1.826944, 2.420678",\
+ "1.723599, 1.908616, 2.102550, 2.411193, 3.004941");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\
+ "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\
+ "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\
+ "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\
+ "1.518485, 1.518485, 1.518485, 1.518486, 1.518488");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2312*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.513665, 0.692005, 0.872351, 1.158538, 1.709291",\
+ "0.541488, 0.719827, 0.900174, 1.186360, 1.737113",\
+ "0.612490, 0.790830, 0.971176, 1.257363, 1.808116",\
+ "0.868217, 1.046556, 1.226903, 1.513090, 2.063843",\
+ "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\
+ "0.598604, 0.776840, 0.957422, 1.244044, 1.795670",\
+ "0.626426, 0.804663, 0.985244, 1.271867, 1.823492",\
+ "0.697429, 0.875665, 1.056247, 1.342869, 1.894494",\
+ "0.953155, 1.131392, 1.311973, 1.598596, 2.150221",\
+ "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\
+ "0.674510, 0.852284, 1.032230, 1.318641, 1.869842",\
+ "0.702332, 0.880106, 1.060053, 1.346463, 1.897664",\
+ "0.773335, 0.951109, 1.131055, 1.417466, 1.968667",\
+ "1.029061, 1.206835, 1.386782, 1.673193, 2.224393",\
+ "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\
+ "0.728862, 0.907029, 1.087096, 1.373235, 1.924159",\
+ "0.756684, 0.934852, 1.114918, 1.401057, 1.951982",\
+ "0.827687, 1.005854, 1.185921, 1.472059, 2.022984",\
+ "1.083413, 1.261581, 1.441647, 1.727786, 2.278711",\
+ "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\
+ "1.010284, 1.192547, 1.371249, 1.656961, 2.207437",\
+ "1.038106, 1.220369, 1.399071, 1.684783, 2.235259",\
+ "1.109109, 1.291372, 1.470074, 1.755786, 2.306262",\
+ "1.364835, 1.547098, 1.725800, 2.011513, 2.561988",\
+ "2.267066, 2.449329, 2.628031, 2.913743, 3.464219");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\
+ "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\
+ "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\
+ "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.395836, 0.660835, 0.919855, 1.356084, 2.228162",\
+ "0.415771, 0.680770, 0.939790, 1.376020, 2.248097",\
+ "0.463414, 0.728413, 0.987433, 1.423663, 2.295740",\
+ "0.628747, 0.893746, 1.152766, 1.588995, 2.461072",\
+ "1.212850, 1.477849, 1.736879, 2.173143, 3.045290",\
+ "0.484501, 0.748910, 1.008496, 1.444313, 2.315567",\
+ "0.504437, 0.768845, 1.028431, 1.464249, 2.335502",\
+ "0.552080, 0.816488, 1.076074, 1.511892, 2.383145",\
+ "0.717412, 0.981821, 1.241406, 1.677224, 2.548478",\
+ "1.301516, 1.565924, 1.825520, 2.261372, 3.132695",\
+ "0.577308, 0.842203, 1.100531, 1.536557, 2.408609",\
+ "0.597243, 0.862139, 1.120466, 1.556492, 2.428544",\
+ "0.644887, 0.909782, 1.168109, 1.604135, 2.476187",\
+ "0.810219, 1.075114, 1.333442, 1.769467, 2.641520",\
+ "1.394323, 1.659218, 1.917555, 2.353615, 3.225737",\
+ "0.643031, 0.910738, 1.167586, 1.603563, 2.475518",\
+ "0.662966, 0.930673, 1.187521, 1.623498, 2.495454",\
+ "0.710609, 0.978316, 1.235164, 1.671142, 2.543097",\
+ "0.875941, 1.143648, 1.400497, 1.836474, 2.708429",\
+ "1.460045, 1.727752, 1.984610, 2.420622, 3.292646",\
+ "0.988820, 1.291236, 1.538224, 1.972764, 2.841846",\
+ "1.008755, 1.311171, 1.558159, 1.992699, 2.861781",\
+ "1.056399, 1.358814, 1.605802, 2.040343, 2.909424",\
+ "1.221731, 1.524147, 1.771134, 2.205675, 3.074756",\
+ "1.805834, 2.108251, 2.355248, 2.789823, 3.658973");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\
+ "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\
+ "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\
+ "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\
+ "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\
+ "1.518485, 1.518485, 1.518485, 1.518485, 1.518485");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2754*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.151345, 0.179420, 0.250838, 0.507101, 1.411098",\
+ "0.239529, 0.267606, 0.339037, 0.595340, 1.499024",\
+ "0.327854, 0.355929, 0.427371, 0.683856, 1.587106",\
+ "0.390452, 0.418510, 0.489921, 0.746692, 1.650402",\
+ "0.720352, 0.748358, 0.819633, 1.076844, 1.982165");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\
+ "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\
+ "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\
+ "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\
+ "0.057228, 0.105834, 0.238478, 0.727955, 2.448223");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.187745, 0.208337, 0.256868, 0.422532, 1.003731",\
+ "0.275148, 0.295740, 0.344271, 0.509935, 1.091134",\
+ "0.356045, 0.376636, 0.425171, 0.590840, 1.172047",\
+ "0.413704, 0.434296, 0.482838, 0.648514, 1.229738",\
+ "0.716053, 0.736646, 0.785216, 0.950960, 1.532355");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.044579, 0.073509, 0.152008, 0.452080, 1.516200",\
+ "0.044579, 0.073509, 0.152008, 0.452080, 1.516200",\
+ "0.044579, 0.073509, 0.152008, 0.452124, 1.516200",\
+ "0.044579, 0.073509, 0.152008, 0.452204, 1.516200",\
+ "0.044579, 0.073509, 0.152008, 0.452924, 1.516200");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_falling ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.146298, 0.146298, 0.146298, 0.146298, 0.146298",\
+ "0.171440, 0.171440, 0.171440, 0.171440, 0.171440",\
+ "0.241225, 0.241225, 0.241225, 0.241225, 0.241225",\
+ "0.364369, 0.364369, 0.364369, 0.364369, 0.364369",\
+ "0.930611, 0.930611, 0.930611, 0.930611, 0.930611");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.419370, 0.419370, 0.419370, 0.419370, 0.419370",\
+ "0.439927, 0.439927, 0.439927, 0.439927, 0.439927",\
+ "0.498432, 0.498432, 0.498432, 0.498432, 0.498432",\
+ "0.607706, 0.607706, 0.607706, 0.607706, 0.607706",\
+ "1.345296, 1.345296, 1.345296, 1.345296, 1.345296");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_cgsf*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.138551, -0.138551, -0.138551, -0.138551, -0.138551",\
+ "-0.162150, -0.162150, -0.162150, -0.162150, -0.162150",\
+ "-0.233628, -0.233628, -0.233628, -0.233628, -0.233628",\
+ "-0.357370, -0.357370, -0.357370, -0.357370, -0.357370",\
+ "-0.923132, -0.923132, -0.923132, -0.923132, -0.923132");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.415516, -0.415516, -0.415516, -0.415516, -0.415516",\
+ "-0.432323, -0.432323, -0.432323, -0.432323, -0.432323",\
+ "-0.494548, -0.494548, -0.494548, -0.494548, -0.494548",\
+ "-0.603812, -0.603812, -0.603812, -0.603812, -0.603812",\
+ "-1.339799, -1.339799, -1.339799, -1.339799, -1.339799");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_cghr*/
+
+ timing () {
+ related_pin : "padmux2ast_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.098861, 0.127061, 0.198218, 0.454154, 1.359203",\
+ "0.186535, 0.214722, 0.285779, 0.541885, 1.444562",\
+ "0.285062, 0.314115, 0.385746, 0.641617, 1.547694",\
+ "0.464742, 0.495967, 0.569252, 0.824864, 1.732299",\
+ "0.773180, 0.811674, 0.892653, 1.148190, 2.048527");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.058877, 0.106972, 0.239632, 0.734291, 2.481454",\
+ "0.059452, 0.107162, 0.239653, 0.735798, 2.481454",\
+ "0.065492, 0.111214, 0.239653, 0.735798, 2.481454",\
+ "0.080964, 0.122543, 0.243345, 0.735798, 2.481454",\
+ "0.122739, 0.156713, 0.261409, 0.735798, 2.481454");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.135906, 0.157942, 0.208401, 0.375177, 0.957248",\
+ "0.214952, 0.236957, 0.287364, 0.454102, 1.034980",\
+ "0.319131, 0.342208, 0.393489, 0.560142, 1.142872",\
+ "0.499405, 0.526607, 0.582603, 0.750679, 1.332501",\
+ "0.794222, 0.832488, 0.901924, 1.075291, 1.655125");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.053775, 0.082436, 0.159158, 0.457799, 1.524944",\
+ "0.053775, 0.082436, 0.159158, 0.457799, 1.524944",\
+ "0.061142, 0.087763, 0.161724, 0.457799, 1.524944",\
+ "0.087222, 0.109690, 0.175261, 0.460373, 1.524944",\
+ "0.145864, 0.166027, 0.220323, 0.470910, 1.526598");
+ }
+
+ } /* end of arc padmux2ast_i[2]_obs_ctrl_o[10]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.094010, 0.121742, 0.192687, 0.448829, 1.352120",\
+ "0.181367, 0.209191, 0.280055, 0.536519, 1.439207",\
+ "0.278263, 0.306648, 0.378094, 0.633788, 1.536303",\
+ "0.454444, 0.484657, 0.556595, 0.813226, 1.718362",\
+ "0.755309, 0.792056, 0.870822, 1.124333, 2.025527");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.056753, 0.105860, 0.238203, 0.725444, 2.440521",\
+ "0.057457, 0.106111, 0.238203, 0.725444, 2.440521",\
+ "0.062809, 0.109450, 0.238891, 0.728499, 2.449750",\
+ "0.076809, 0.119663, 0.242773, 0.728499, 2.460771",\
+ "0.116537, 0.152614, 0.258265, 0.732313, 2.462313");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.100529, 0.120692, 0.168644, 0.334136, 0.916833",\
+ "0.185614, 0.205791, 0.253754, 0.419069, 1.001005",\
+ "0.286304, 0.308070, 0.357380, 0.522540, 1.104903",\
+ "0.458699, 0.485107, 0.539262, 0.704482, 1.285416",\
+ "0.740887, 0.778992, 0.848123, 1.019973, 1.597477");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168");
+ values ( "0.045486, 0.074449, 0.152541, 0.452549, 1.519412",\
+ "0.046012, 0.074648, 0.152769, 0.453825, 1.520024",\
+ "0.056013, 0.082252, 0.156413, 0.454416, 1.520024",\
+ "0.082035, 0.104246, 0.169572, 0.457496, 1.520040",\
+ "0.139812, 0.159966, 0.214496, 0.467116, 1.522752");
+ }
+
+ } /* end of arc padmux2ast_i[2]_obs_ctrl_o[10]_una_min*/
+
+} /* end of pin obs_ctrl_o[10] */
+
+pin("obs_ctrl_o[9]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.156168 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001432 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[9];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.560564, 0.740767, 0.928257, 1.230250, 1.813761",\
+ "0.590490, 0.770693, 0.958183, 1.260175, 1.843687",\
+ "0.662228, 0.842431, 1.029921, 1.331913, 1.915425",\
+ "0.918680, 1.098883, 1.286373, 1.588366, 2.171877",\
+ "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\
+ "0.645502, 0.826050, 1.014266, 1.316262, 1.900140",\
+ "0.675428, 0.855976, 1.044191, 1.346187, 1.930065",\
+ "0.747166, 0.927714, 1.115929, 1.417926, 2.001803",\
+ "1.003618, 1.184166, 1.372382, 1.674378, 2.258256",\
+ "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\
+ "0.721415, 0.901494, 1.089075, 1.390859, 1.974312",\
+ "0.751340, 0.931419, 1.119000, 1.420784, 2.004238",\
+ "0.823078, 1.003157, 1.190738, 1.492522, 2.075976",\
+ "1.079530, 1.259610, 1.447191, 1.748975, 2.332428",\
+ "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\
+ "0.775784, 0.956005, 1.143726, 1.445398, 2.028629",\
+ "0.805709, 0.985931, 1.173651, 1.475324, 2.058555",\
+ "0.877448, 1.057669, 1.245389, 1.547062, 2.130293",\
+ "1.133900, 1.314121, 1.501842, 1.803514, 2.386745",\
+ "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\
+ "1.057379, 1.241273, 1.427676, 1.729125, 2.311907",\
+ "1.087304, 1.271199, 1.457602, 1.759050, 2.341833",\
+ "1.159042, 1.342937, 1.529340, 1.830788, 2.413571",\
+ "1.415495, 1.599389, 1.785792, 2.087241, 2.670023",\
+ "2.327707, 2.511601, 2.698004, 2.999453, 3.582235");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.418380, 0.686166, 0.947746, 1.387443, 2.266838",\
+ "0.442754, 0.710540, 0.972120, 1.411817, 2.291212",\
+ "0.493609, 0.761395, 1.022975, 1.462672, 2.342067",\
+ "0.660045, 0.927830, 1.189410, 1.629108, 2.508502",\
+ "1.246765, 1.514551, 1.776131, 2.215828, 3.095223",\
+ "0.507084, 0.774241, 1.036387, 1.475672, 2.354243",\
+ "0.531458, 0.798615, 1.060761, 1.500046, 2.378617",\
+ "0.582313, 0.849470, 1.111616, 1.550901, 2.429472",\
+ "0.748749, 1.015905, 1.278051, 1.717337, 2.595908",\
+ "1.335469, 1.602626, 1.864772, 2.304057, 3.182628",\
+ "0.600027, 0.867386, 1.128112, 1.567836, 2.447285",\
+ "0.624401, 0.891760, 1.152486, 1.592211, 2.471659",\
+ "0.675255, 0.942615, 1.203341, 1.643065, 2.522514",\
+ "0.841691, 1.109051, 1.369777, 1.809501, 2.688950",\
+ "1.428411, 1.695771, 1.956497, 2.396221, 3.275670",\
+ "0.665870, 0.935950, 1.195132, 1.634687, 2.513796",\
+ "0.690244, 0.960324, 1.219506, 1.659061, 2.538170",\
+ "0.741099, 1.011179, 1.270361, 1.709916, 2.589025",\
+ "0.907535, 1.177615, 1.436797, 1.876351, 2.755461",\
+ "1.494255, 1.764335, 2.023517, 2.463071, 3.342181",\
+ "1.012392, 1.316786, 1.565795, 2.003840, 2.879932",\
+ "1.036766, 1.341160, 1.590169, 2.028214, 2.904306",\
+ "1.087620, 1.392015, 1.641024, 2.079069, 2.955161",\
+ "1.254056, 1.558450, 1.807460, 2.245505, 3.121596",\
+ "1.840776, 2.145171, 2.394180, 2.832225, 3.708317");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2714*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.468669, 0.732243, 1.008515, 1.477245, 2.414704",\
+ "0.498595, 0.762168, 1.038441, 1.507171, 2.444630",\
+ "0.570333, 0.833907, 1.110179, 1.578909, 2.516368",\
+ "0.826785, 1.090359, 1.366631, 1.835361, 2.772820",\
+ "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\
+ "0.556864, 0.819784, 1.096083, 1.563960, 2.500638",\
+ "0.586789, 0.849709, 1.126009, 1.593886, 2.530564",\
+ "0.658527, 0.921448, 1.197747, 1.665624, 2.602302",\
+ "0.914980, 1.177900, 1.454199, 1.922076, 2.858753",\
+ "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\
+ "0.645180, 0.908764, 1.184048, 1.651583, 2.587593",\
+ "0.675105, 0.938690, 1.213974, 1.681509, 2.617519",\
+ "0.746844, 1.010428, 1.285712, 1.753247, 2.689257",\
+ "1.003296, 1.266880, 1.542164, 2.009699, 2.945708",\
+ "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\
+ "0.707676, 0.974399, 1.248188, 1.715497, 2.651102",\
+ "0.737601, 1.004325, 1.278113, 1.745422, 2.681028",\
+ "0.809340, 1.076063, 1.349852, 1.817160, 2.752766",\
+ "1.065792, 1.332515, 1.606304, 2.073612, 3.009217",\
+ "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\
+ "1.036801, 1.338730, 1.600055, 2.064846, 2.996558",\
+ "1.066727, 1.368655, 1.629981, 2.094772, 3.026484",\
+ "1.138465, 1.440394, 1.701719, 2.166510, 3.098222",\
+ "1.394917, 1.696846, 1.958171, 2.422962, 3.354673",\
+ "2.307129, 2.609058, 2.870384, 3.335176, 4.266890");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.401333, 0.583765, 0.780157, 1.089211, 1.684018",\
+ "0.425707, 0.608139, 0.804531, 1.113585, 1.708393",\
+ "0.476562, 0.658994, 0.855386, 1.164439, 1.759248",\
+ "0.642998, 0.825430, 1.021822, 1.330875, 1.925682",\
+ "1.229718, 1.412150, 1.608542, 1.917595, 2.512401",\
+ "0.488748, 0.671151, 0.867650, 1.176516, 1.771372",\
+ "0.513122, 0.695525, 0.892024, 1.200890, 1.795747",\
+ "0.563977, 0.746379, 0.942879, 1.251745, 1.846601",\
+ "0.730413, 0.912815, 1.109315, 1.418180, 2.013035",\
+ "1.317133, 1.499535, 1.696035, 2.004900, 2.599754",\
+ "0.569624, 0.751487, 0.947677, 1.256544, 1.851403",\
+ "0.593999, 0.775861, 0.972051, 1.280918, 1.875778",\
+ "0.644853, 0.826716, 1.022906, 1.331773, 1.926633",\
+ "0.811289, 0.993152, 1.189342, 1.498208, 2.093067",\
+ "1.398009, 1.579872, 1.776062, 2.084928, 2.679786",\
+ "0.627271, 0.809036, 1.005221, 1.313789, 1.908051",\
+ "0.651645, 0.833410, 1.029595, 1.338163, 1.932426",\
+ "0.702500, 0.884265, 1.080450, 1.389018, 1.983280",\
+ "0.868935, 1.050700, 1.246886, 1.555453, 2.149714",\
+ "1.455656, 1.637420, 1.833606, 2.142173, 2.736434",\
+ "0.929479, 1.114260, 1.308855, 1.616804, 2.209898",\
+ "0.953853, 1.138634, 1.333229, 1.641178, 2.234272",\
+ "1.004707, 1.189489, 1.384084, 1.692033, 2.285127",\
+ "1.171143, 1.355925, 1.550519, 1.858468, 2.451561",\
+ "1.757863, 1.942645, 2.137239, 2.445188, 3.038280");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523368");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2644*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.464694, 0.724323, 0.996195, 1.453075, 2.366835",\
+ "0.494620, 0.754249, 1.026121, 1.483001, 2.396760",\
+ "0.566358, 0.825987, 1.097859, 1.554739, 2.468498",\
+ "0.822810, 1.082439, 1.354311, 1.811191, 2.724950",\
+ "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\
+ "0.552799, 0.811857, 1.083726, 1.539791, 2.452769",\
+ "0.582724, 0.841782, 1.113652, 1.569716, 2.482694",\
+ "0.654463, 0.913521, 1.185390, 1.641454, 2.554432",\
+ "0.910915, 1.169973, 1.441842, 1.897906, 2.810884",\
+ "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\
+ "0.640829, 0.900823, 1.171690, 1.627413, 2.539724",\
+ "0.670754, 0.930748, 1.201616, 1.657339, 2.569649",\
+ "0.742493, 1.002486, 1.273354, 1.729077, 2.641387",\
+ "0.998945, 1.258938, 1.529806, 1.985529, 2.897839",\
+ "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\
+ "0.703050, 0.966436, 1.235828, 1.691327, 2.603233",\
+ "0.732976, 0.996362, 1.265754, 1.721252, 2.633158",\
+ "0.804714, 1.068100, 1.337492, 1.792991, 2.704896",\
+ "1.061166, 1.324552, 1.593944, 2.049443, 2.961348",\
+ "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\
+ "1.030438, 1.330511, 1.587575, 2.040628, 2.948689",\
+ "1.060363, 1.360437, 1.617501, 2.070553, 2.978614",\
+ "1.132102, 1.432175, 1.689239, 2.142292, 3.050352",\
+ "1.388554, 1.688627, 1.945691, 2.398743, 3.306804",\
+ "2.300766, 2.600840, 2.857904, 3.310957, 4.219019");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224142, 0.224142, 0.224142, 0.224142",\
+ "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\
+ "2.463890, 2.463889, 2.463888, 2.463885, 2.463879");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.399672, 0.582213, 0.778468, 1.087685, 1.682981",\
+ "0.424046, 0.606587, 0.802842, 1.112059, 1.707356",\
+ "0.474901, 0.657442, 0.853696, 1.162914, 1.758210",\
+ "0.641336, 0.823877, 1.020132, 1.329349, 1.924644",\
+ "1.228057, 1.410598, 1.606853, 1.916069, 2.511364",\
+ "0.487092, 0.669598, 0.865960, 1.174990, 1.770335",\
+ "0.511466, 0.693972, 0.890334, 1.199364, 1.794710",\
+ "0.562321, 0.744827, 0.941189, 1.250219, 1.845564",\
+ "0.728756, 0.911263, 1.107625, 1.416654, 2.011998",\
+ "1.315477, 1.497983, 1.694345, 2.003374, 2.598717",\
+ "0.567959, 0.749935, 0.945987, 1.255018, 1.850366",\
+ "0.592334, 0.774309, 0.970361, 1.279393, 1.874741",\
+ "0.643188, 0.825164, 1.021216, 1.330247, 1.925596",\
+ "0.809624, 0.991600, 1.187652, 1.496683, 2.092030",\
+ "1.396344, 1.578320, 1.774372, 2.083403, 2.678749",\
+ "0.625598, 0.807484, 1.003531, 1.312263, 1.907014",\
+ "0.649972, 0.831858, 1.027905, 1.336638, 1.931389",\
+ "0.700827, 0.882712, 1.078760, 1.387492, 1.982243",\
+ "0.867263, 1.049148, 1.245196, 1.553928, 2.148677",\
+ "1.453983, 1.635868, 1.831916, 2.140648, 2.735396",\
+ "0.927693, 1.112710, 1.307165, 1.615278, 2.208861",\
+ "0.952068, 1.137084, 1.331539, 1.639653, 2.233236",\
+ "1.002922, 1.187939, 1.382394, 1.690507, 2.284090",\
+ "1.169358, 1.354374, 1.548830, 1.856943, 2.450524",\
+ "1.756078, 1.941095, 2.135550, 2.443663, 3.037243");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523367");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2587*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.556978, 0.735404, 0.915665, 1.201871, 1.752988",\
+ "0.586903, 0.765330, 0.945590, 1.231797, 1.782914",\
+ "0.658642, 0.837068, 1.017329, 1.303535, 1.854652",\
+ "0.915094, 1.093521, 1.273781, 1.559987, 2.111104",\
+ "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\
+ "0.641916, 0.820677, 1.001580, 1.287791, 1.839366",\
+ "0.671842, 0.850602, 1.031505, 1.317717, 1.869292",\
+ "0.743580, 0.922341, 1.103244, 1.389455, 1.941030",\
+ "1.000032, 1.178793, 1.359696, 1.645907, 2.197482",\
+ "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\
+ "0.717822, 0.896120, 1.076389, 1.362388, 1.913539",\
+ "0.747748, 0.926046, 1.106314, 1.392314, 1.943465",\
+ "0.819486, 0.997784, 1.178053, 1.464052, 2.015203",\
+ "1.075938, 1.254236, 1.434505, 1.720504, 2.271655",\
+ "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\
+ "0.772174, 0.950632, 1.131040, 1.416928, 1.967856",\
+ "0.802100, 0.980558, 1.160965, 1.446854, 1.997782",\
+ "0.873838, 1.052296, 1.232704, 1.518592, 2.069520",\
+ "1.130290, 1.308748, 1.489156, 1.775044, 2.325972",\
+ "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\
+ "1.053596, 1.235859, 1.414990, 1.700654, 2.251134",\
+ "1.083522, 1.265785, 1.444916, 1.730580, 2.281059",\
+ "1.155260, 1.337523, 1.516654, 1.802318, 2.352798",\
+ "1.411712, 1.593975, 1.773107, 2.058770, 2.609250",\
+ "2.323924, 2.506187, 2.685318, 2.970983, 3.521462");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\
+ "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\
+ "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\
+ "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.416944, 0.682114, 0.941316, 1.377498, 2.249863",\
+ "0.441318, 0.706488, 0.965690, 1.401872, 2.274237",\
+ "0.492173, 0.757343, 1.016545, 1.452727, 2.325092",\
+ "0.658609, 0.923779, 1.182980, 1.619163, 2.491528",\
+ "1.245329, 1.510499, 1.769700, 2.205883, 3.078248",\
+ "0.505610, 0.770189, 1.029957, 1.465727, 2.337268",\
+ "0.529984, 0.794563, 1.054331, 1.490101, 2.361642",\
+ "0.580839, 0.845418, 1.105186, 1.540956, 2.412497",\
+ "0.747274, 1.011853, 1.271621, 1.707392, 2.578933",\
+ "1.333995, 1.598574, 1.858341, 2.294112, 3.165653",\
+ "0.598417, 0.863312, 1.121682, 1.557891, 2.430310",\
+ "0.622791, 0.887686, 1.146056, 1.582265, 2.454684",\
+ "0.673645, 0.938541, 1.196911, 1.633120, 2.505539",\
+ "0.840081, 1.104976, 1.363346, 1.799556, 2.671975",\
+ "1.426801, 1.691697, 1.950067, 2.386276, 3.258695",\
+ "0.664139, 0.931846, 1.188702, 1.624742, 2.496821",\
+ "0.688513, 0.956220, 1.213076, 1.649116, 2.521195",\
+ "0.739368, 1.007075, 1.263931, 1.699970, 2.572050",\
+ "0.905804, 1.173511, 1.430366, 1.866406, 2.738486",\
+ "1.492524, 1.760231, 2.017087, 2.453126, 3.325206",\
+ "1.009929, 1.312345, 1.559332, 1.993873, 2.862955",\
+ "1.034303, 1.336719, 1.583706, 2.018247, 2.887329",\
+ "1.085157, 1.387573, 1.634561, 2.069102, 2.938183",\
+ "1.251593, 1.554009, 1.800997, 2.235537, 3.104619",\
+ "1.838313, 2.140729, 2.387717, 2.822258, 3.691339");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\
+ "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\
+ "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\
+ "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\
+ "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\
+ "1.523369, 1.523369, 1.523369, 1.523369, 1.523370");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2527*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.324251, 0.354177, 0.425915, 0.682368, 1.594576",\
+ "0.411642, 0.441568, 0.513306, 0.769759, 1.681967",\
+ "0.492561, 0.522487, 0.594225, 0.850678, 1.762885",\
+ "0.550301, 0.580227, 0.651966, 0.908419, 1.820624",\
+ "0.853007, 0.882932, 0.954672, 1.211125, 2.123326");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.046138, 0.092741, 0.224144, 0.716261, 2.463871",\
+ "0.046138, 0.092741, 0.224221, 0.716261, 2.463871",\
+ "0.046138, 0.092741, 0.224454, 0.716261, 2.463871",\
+ "0.046138, 0.092741, 0.224454, 0.716261, 2.463871",\
+ "0.046298, 0.092766, 0.224788, 0.716274, 2.463884");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.296828, 0.321202, 0.372057, 0.538492, 1.125213",\
+ "0.384221, 0.408595, 0.459449, 0.625885, 1.212605",\
+ "0.465090, 0.489464, 0.540319, 0.706755, 1.293475",\
+ "0.522739, 0.547113, 0.597968, 0.764403, 1.351124",\
+ "0.825878, 0.850484, 0.901694, 1.068525, 1.654935");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.044458, 0.073621, 0.149762, 0.447950, 1.524119",\
+ "0.044458, 0.073621, 0.149762, 0.447950, 1.524119",\
+ "0.044458, 0.073621, 0.149762, 0.447950, 1.523993",\
+ "0.044458, 0.073621, 0.149762, 0.447950, 1.523757",\
+ "0.044456, 0.073554, 0.149762, 0.447945, 1.523369");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.507754, 0.687868, 0.875446, 1.177426, 1.760522",\
+ "0.536697, 0.716810, 0.904389, 1.206369, 1.789465",\
+ "0.607845, 0.787958, 0.975537, 1.277516, 1.860613",\
+ "0.863570, 1.043684, 1.231262, 1.533242, 2.116338",\
+ "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\
+ "0.592692, 0.772703, 0.960516, 1.262932, 1.846900",\
+ "0.621635, 0.801646, 0.989459, 1.291875, 1.875843",\
+ "0.692783, 0.872794, 1.060607, 1.363023, 1.946991",\
+ "0.948508, 1.128520, 1.316332, 1.618748, 2.202716",\
+ "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\
+ "0.668604, 0.848147, 1.035325, 1.337529, 1.921072",\
+ "0.697547, 0.877090, 1.064268, 1.366472, 1.950015",\
+ "0.768695, 0.948237, 1.135416, 1.437619, 2.021163",\
+ "1.024420, 1.203963, 1.391141, 1.693345, 2.276889",\
+ "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\
+ "0.722973, 0.902898, 1.090214, 1.392134, 1.975390",\
+ "0.751916, 0.931841, 1.119157, 1.421077, 2.004333",\
+ "0.823064, 1.002989, 1.190305, 1.492225, 2.075481",\
+ "1.078790, 1.258714, 1.446030, 1.747951, 2.331206",\
+ "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\
+ "1.004568, 1.188463, 1.374389, 1.675861, 2.258667",\
+ "1.033511, 1.217406, 1.403332, 1.704803, 2.287610",\
+ "1.104659, 1.288554, 1.474480, 1.775951, 2.358758",\
+ "1.360384, 1.544279, 1.730205, 2.031677, 2.614483",\
+ "2.270849, 2.454743, 2.640669, 2.942141, 3.524948");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.389691, 0.657302, 0.918703, 1.358480, 2.237641",\
+ "0.411640, 0.679251, 0.940643, 1.380389, 2.259487",\
+ "0.459656, 0.727267, 0.988659, 1.428405, 2.307503",\
+ "0.624965, 0.892576, 1.153968, 1.593714, 2.472812",\
+ "1.214409, 1.482020, 1.743420, 2.183197, 3.062358",\
+ "0.478395, 0.745377, 1.007344, 1.446709, 2.325046",\
+ "0.500344, 0.767326, 1.029284, 1.468618, 2.346892",\
+ "0.548360, 0.815342, 1.077300, 1.516634, 2.394908",\
+ "0.713669, 0.980651, 1.242609, 1.681943, 2.560217",\
+ "1.303113, 1.570095, 1.832061, 2.271426, 3.149764",\
+ "0.571337, 0.838697, 1.099388, 1.538955, 2.418088",\
+ "0.593287, 0.860646, 1.121328, 1.560864, 2.439934",\
+ "0.641303, 0.908662, 1.169344, 1.608880, 2.487950",\
+ "0.806611, 1.073971, 1.334653, 1.774188, 2.653259",\
+ "1.396055, 1.663415, 1.924106, 2.363672, 3.242805",\
+ "0.637181, 0.907261, 1.166444, 1.605966, 2.485009",\
+ "0.659130, 0.929210, 1.188385, 1.627875, 2.506856",\
+ "0.707146, 0.977226, 1.236400, 1.675891, 2.554872",\
+ "0.872455, 1.142535, 1.401709, 1.841200, 2.720181",\
+ "1.461899, 1.731979, 1.991162, 2.430684, 3.309727",\
+ "0.983703, 1.288097, 1.537115, 1.975192, 2.851345",\
+ "1.005652, 1.310046, 1.559055, 1.997100, 2.873191",\
+ "1.053668, 1.358062, 1.607071, 2.045116, 2.921207",\
+ "1.218976, 1.523371, 1.772380, 2.210425, 3.086516",\
+ "1.808420, 2.112815, 2.361833, 2.799909, 3.676063");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2469*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.415862, 0.679394, 0.955513, 1.423645, 2.358649",\
+ "0.444805, 0.708336, 0.984456, 1.452588, 2.387592",\
+ "0.515953, 0.779484, 1.055604, 1.523736, 2.458740",\
+ "0.771678, 1.035210, 1.311329, 1.779461, 2.714465",\
+ "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\
+ "0.504057, 0.766934, 1.043080, 1.510360, 2.444582",\
+ "0.532999, 0.795877, 1.072023, 1.539303, 2.473526",\
+ "0.604147, 0.867025, 1.143171, 1.610451, 2.544673",\
+ "0.859873, 1.122750, 1.398896, 1.866176, 2.800399",\
+ "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\
+ "0.592373, 0.855914, 1.131045, 1.598000, 2.531538",\
+ "0.621315, 0.884856, 1.159988, 1.626943, 2.560481",\
+ "0.692463, 0.956004, 1.231135, 1.698091, 2.631628",\
+ "0.948189, 1.211730, 1.486861, 1.953817, 2.887354",\
+ "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\
+ "0.654869, 0.921547, 1.195184, 1.662089, 2.595047",\
+ "0.683811, 0.950490, 1.224127, 1.691032, 2.623990",\
+ "0.754959, 1.021638, 1.295275, 1.762180, 2.695137",\
+ "1.010685, 1.277363, 1.551000, 2.017905, 2.950863",\
+ "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\
+ "0.983994, 1.285862, 1.547048, 2.011533, 2.940503",\
+ "1.012937, 1.314805, 1.575991, 2.040476, 2.969446",\
+ "1.084085, 1.385953, 1.647139, 2.111624, 3.040593",\
+ "1.339811, 1.641678, 1.902864, 2.367349, 3.296319",\
+ "2.250275, 2.552142, 2.813329, 3.277813, 4.206782");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.043180, 0.043181, 0.043181, 0.043181, 0.043182",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.372646, 0.554704, 0.750937, 1.060114, 1.654586",\
+ "0.394593, 0.576651, 0.772784, 1.081916, 1.676369",\
+ "0.442609, 0.624667, 0.820800, 1.129932, 1.724385",\
+ "0.607918, 0.789976, 0.986109, 1.295241, 1.889696",\
+ "1.197364, 1.379422, 1.575655, 1.884836, 2.479319",\
+ "0.460061, 0.642022, 0.838218, 1.147419, 1.741940",\
+ "0.482008, 0.663970, 0.860065, 1.169221, 1.763722",\
+ "0.530024, 0.711986, 0.908081, 1.217237, 1.811739",\
+ "0.695333, 0.877294, 1.073389, 1.382546, 1.977050",\
+ "1.284779, 1.466740, 1.662936, 1.972141, 2.566672",\
+ "0.540937, 0.722359, 0.918245, 1.227448, 1.821971",\
+ "0.562884, 0.744306, 0.940092, 1.249249, 1.843754",\
+ "0.610900, 0.792322, 0.988108, 1.297265, 1.891770",\
+ "0.776209, 0.957631, 1.153416, 1.462574, 2.057081",\
+ "1.365655, 1.547077, 1.742963, 2.052169, 2.646704",\
+ "0.598584, 0.780196, 0.975981, 1.284918, 1.879067",\
+ "0.620531, 0.802143, 0.997827, 1.306720, 1.900850",\
+ "0.668547, 0.850159, 1.045843, 1.354736, 1.948866",\
+ "0.833856, 1.015468, 1.211152, 1.520045, 2.114177",\
+ "1.423301, 1.604914, 1.800699, 2.109640, 2.703799",\
+ "0.900791, 1.085573, 1.279644, 1.588125, 2.181385",\
+ "0.922739, 1.107520, 1.301491, 1.609926, 2.203168",\
+ "0.970755, 1.155536, 1.349506, 1.657943, 2.251184",\
+ "1.136063, 1.320845, 1.514815, 1.823252, 2.416495",\
+ "1.725509, 1.910291, 2.104362, 2.412847, 3.006117");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.035869, 0.035869, 0.035869, 0.035869, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\
+ "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\
+ "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2391*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.411884, 0.671443, 0.943078, 1.399240, 2.310408",\
+ "0.440827, 0.700386, 0.972021, 1.428183, 2.339350",\
+ "0.511975, 0.771534, 1.043169, 1.499331, 2.410498",\
+ "0.767700, 1.027260, 1.298895, 1.755056, 2.666224",\
+ "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\
+ "0.499989, 0.758976, 1.030607, 1.485955, 2.396341",\
+ "0.528932, 0.787919, 1.059550, 1.514898, 2.425284",\
+ "0.600080, 0.859067, 1.130698, 1.586046, 2.496432",\
+ "0.855805, 1.114792, 1.386424, 1.841771, 2.752157",\
+ "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\
+ "0.588019, 0.847941, 1.118572, 1.573594, 2.483296",\
+ "0.616962, 0.876883, 1.147514, 1.602537, 2.512239",\
+ "0.688110, 0.948031, 1.218662, 1.673685, 2.583387",\
+ "0.943835, 1.203757, 1.474388, 1.929410, 2.839113",\
+ "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\
+ "0.650240, 0.913552, 1.182709, 1.637669, 2.546805",\
+ "0.679183, 0.942495, 1.211652, 1.666611, 2.575748",\
+ "0.750331, 1.013643, 1.282800, 1.737759, 2.646896",\
+ "1.006057, 1.269368, 1.538526, 1.993485, 2.902622",\
+ "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\
+ "0.977628, 1.277600, 1.534452, 1.987055, 2.892262",\
+ "1.006571, 1.306543, 1.563395, 2.015998, 2.921204",\
+ "1.077719, 1.377691, 1.634543, 2.087146, 2.992352",\
+ "1.333444, 1.633417, 1.890268, 2.342871, 3.248078",\
+ "2.243908, 2.543881, 2.800732, 3.253335, 4.158542");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.370982, 0.553150, 0.749248, 1.058587, 1.653547",\
+ "0.392932, 0.575099, 0.771096, 1.080389, 1.675331",\
+ "0.440948, 0.623115, 0.819112, 1.128405, 1.723348",\
+ "0.606257, 0.788424, 0.984421, 1.293715, 1.888659",\
+ "1.195700, 1.377868, 1.573966, 1.883303, 2.478263",\
+ "0.458403, 0.640469, 0.836529, 1.145892, 1.740901",\
+ "0.480352, 0.662418, 0.858377, 1.167694, 1.762685",\
+ "0.528368, 0.710434, 0.906393, 1.215710, 1.810701",\
+ "0.693677, 0.875743, 1.071702, 1.381020, 1.976012",\
+ "1.283120, 1.465186, 1.661247, 1.970608, 2.565616",\
+ "0.539270, 0.720805, 0.916556, 1.225920, 1.820932",\
+ "0.561219, 0.742755, 0.938404, 1.247723, 1.842716",\
+ "0.609235, 0.790771, 0.986420, 1.295739, 1.890733",\
+ "0.774544, 0.956080, 1.151728, 1.461048, 2.056044",\
+ "1.363988, 1.545523, 1.741274, 2.050637, 2.645648",\
+ "0.596909, 0.778642, 0.974291, 1.283391, 1.878029",\
+ "0.618858, 0.800592, 0.996139, 1.305194, 1.899813",\
+ "0.666874, 0.848608, 1.044155, 1.353210, 1.947829",\
+ "0.832183, 1.013916, 1.209464, 1.518519, 2.113140",\
+ "1.421627, 1.603360, 1.799009, 2.108108, 2.702744",\
+ "0.899004, 1.084021, 1.277955, 1.586599, 2.180348",\
+ "0.920954, 1.105970, 1.299802, 1.608401, 2.202132",\
+ "0.968969, 1.153986, 1.347818, 1.656417, 2.250149",\
+ "1.134278, 1.319295, 1.513127, 1.821727, 2.415460",\
+ "1.723722, 1.908738, 2.102673, 2.411315, 3.005064");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\
+ "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\
+ "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\
+ "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\
+ "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\
+ "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\
+ "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\
+ "1.518709, 1.518709, 1.518710, 1.518710, 1.518712");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2332*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.504167, 0.682507, 0.862854, 1.149040, 1.699793",\
+ "0.533110, 0.711450, 0.891797, 1.177983, 1.728736",\
+ "0.604258, 0.782598, 0.962945, 1.249131, 1.799884",\
+ "0.859984, 1.038323, 1.218670, 1.504856, 2.055609",\
+ "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\
+ "0.589106, 0.767343, 0.947924, 1.234547, 1.786172",\
+ "0.618049, 0.796286, 0.976867, 1.263489, 1.815114",\
+ "0.689197, 0.867433, 1.048015, 1.334637, 1.886262",\
+ "0.944922, 1.123159, 1.303740, 1.590363, 2.141988",\
+ "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\
+ "0.665012, 0.842786, 1.022733, 1.309143, 1.860344",\
+ "0.693955, 0.871729, 1.051676, 1.338086, 1.889287",\
+ "0.765103, 0.942877, 1.122823, 1.409234, 1.960435",\
+ "1.020828, 1.198602, 1.378549, 1.664959, 2.216160",\
+ "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\
+ "0.719364, 0.897532, 1.077598, 1.363737, 1.914661",\
+ "0.748307, 0.926474, 1.106541, 1.392680, 1.943604",\
+ "0.819455, 0.997622, 1.177689, 1.463828, 2.014752",\
+ "1.075180, 1.253348, 1.433414, 1.719553, 2.270478",\
+ "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\
+ "1.000786, 1.183049, 1.361751, 1.647463, 2.197939",\
+ "1.029729, 1.211992, 1.390694, 1.676406, 2.226882",\
+ "1.100877, 1.283140, 1.461842, 1.747554, 2.298030",\
+ "1.356602, 1.538865, 1.717567, 2.003279, 2.553755",\
+ "2.267066, 2.449329, 2.628031, 2.913743, 3.464219");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\
+ "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\
+ "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\
+ "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.388255, 0.653254, 0.912284, 1.348548, 2.220695",\
+ "0.410204, 0.675204, 0.934223, 1.370453, 2.242530",\
+ "0.458220, 0.723220, 0.982239, 1.418469, 2.290546",\
+ "0.623529, 0.888528, 1.147548, 1.583778, 2.455855",\
+ "1.212973, 1.477972, 1.737002, 2.173266, 3.045412",\
+ "0.476921, 0.741329, 1.000925, 1.436777, 2.308100",\
+ "0.498870, 0.763278, 1.022864, 1.458682, 2.329936",\
+ "0.546886, 0.811294, 1.070880, 1.506698, 2.377952",\
+ "0.712195, 0.976603, 1.236189, 1.672007, 2.543260",\
+ "1.301638, 1.566047, 1.825642, 2.261495, 3.132817",\
+ "0.569727, 0.834623, 1.092960, 1.529020, 2.401142",\
+ "0.591677, 0.856572, 1.114899, 1.550925, 2.422977",\
+ "0.639693, 0.904588, 1.162915, 1.598941, 2.470994",\
+ "0.805001, 1.069897, 1.328224, 1.764250, 2.636302",\
+ "1.394445, 1.659341, 1.917678, 2.353738, 3.225859",\
+ "0.635450, 0.903157, 1.160015, 1.596027, 2.468051",\
+ "0.657399, 0.925106, 1.181954, 1.617932, 2.489887",\
+ "0.705415, 0.973122, 1.229970, 1.665948, 2.537903",\
+ "0.870724, 1.138431, 1.395279, 1.831257, 2.703212",\
+ "1.460168, 1.727875, 1.984733, 2.420745, 3.292769",\
+ "0.981239, 1.283655, 1.530653, 1.965228, 2.834378",\
+ "1.003189, 1.305605, 1.552592, 1.987133, 2.856214",\
+ "1.051205, 1.353621, 1.600608, 2.035149, 2.904230",\
+ "1.216513, 1.518929, 1.765917, 2.200458, 3.069539",\
+ "1.805957, 2.108373, 2.355371, 2.789946, 3.659096");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443429",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\
+ "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\
+ "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\
+ "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\
+ "0.443427, 0.443427, 0.443427, 0.443428, 0.443429",\
+ "1.518709, 1.518709, 1.518709, 1.518709, 1.518710");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2273*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.141721, 0.170980, 0.242593, 0.498866, 1.411098",\
+ "0.229906, 0.259165, 0.330790, 0.587108, 1.499024",\
+ "0.318231, 0.347489, 0.419118, 0.675627, 1.587106",\
+ "0.380823, 0.410078, 0.481658, 0.738460, 1.650402",\
+ "0.710704, 0.739954, 0.811356, 1.068597, 1.982165");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\
+ "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\
+ "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\
+ "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\
+ "0.043180, 0.090365, 0.222668, 0.712250, 2.448223");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.179981, 0.202635, 0.251659, 0.417360, 1.003853",\
+ "0.267384, 0.290039, 0.339062, 0.504764, 1.091257",\
+ "0.348282, 0.370934, 0.419962, 0.585668, 1.172170",\
+ "0.405945, 0.428592, 0.477629, 0.643342, 1.229861",\
+ "0.708302, 0.730939, 0.780004, 0.945787, 1.532477");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.035869, 0.064690, 0.142524, 0.442595, 1.516425",\
+ "0.035869, 0.064690, 0.142524, 0.442595, 1.516425",\
+ "0.035869, 0.064690, 0.142524, 0.442641, 1.516425",\
+ "0.035869, 0.064690, 0.142524, 0.442726, 1.516425",\
+ "0.035869, 0.064691, 0.142524, 0.443427, 1.516425");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_falling ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.146678, 0.146678, 0.146678, 0.146678, 0.146678",\
+ "0.165298, 0.165298, 0.165298, 0.165298, 0.165298",\
+ "0.241802, 0.241802, 0.241802, 0.241802, 0.241802",\
+ "0.367706, 0.367706, 0.367706, 0.367706, 0.367706",\
+ "0.946794, 0.946794, 0.946794, 0.946794, 0.946794");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.412191, 0.412191, 0.412191, 0.412191, 0.412191",\
+ "0.424880, 0.424880, 0.424880, 0.424880, 0.424880",\
+ "0.479563, 0.479563, 0.479563, 0.479563, 0.479563",\
+ "0.581996, 0.581996, 0.581996, 0.581996, 0.581996",\
+ "1.256928, 1.256928, 1.256928, 1.256928, 1.256928");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_cgsf*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.138937, -0.138937, -0.138937, -0.138937, -0.138937",\
+ "-0.155751, -0.155751, -0.155751, -0.155751, -0.155751",\
+ "-0.234216, -0.234216, -0.234216, -0.234216, -0.234216",\
+ "-0.360721, -0.360721, -0.360721, -0.360721, -0.360721",\
+ "-0.939265, -0.939265, -0.939265, -0.939265, -0.939265");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.408326, -0.408326, -0.408326, -0.408326, -0.408326",\
+ "-0.417967, -0.417967, -0.417967, -0.417967, -0.417967",\
+ "-0.475689, -0.475689, -0.475689, -0.475689, -0.475689",\
+ "-0.578062, -0.578062, -0.578062, -0.578062, -0.578062",\
+ "-1.250684, -1.250684, -1.250684, -1.250684, -1.250684");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_cghr*/
+
+ timing () {
+ related_pin : "padmux2ast_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.088963, 0.118659, 0.189985, 0.445909, 1.359203",\
+ "0.176595, 0.206339, 0.277538, 0.533662, 1.444562",\
+ "0.274330, 0.305634, 0.377516, 0.633363, 1.547694",\
+ "0.452110, 0.487212, 0.561030, 0.816620, 1.732299",\
+ "0.755237, 0.801656, 0.884430, 1.139988, 2.048527");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.044962, 0.091670, 0.223831, 0.718456, 2.481454",\
+ "0.045846, 0.091918, 0.223831, 0.720074, 2.481454",\
+ "0.052795, 0.096494, 0.223831, 0.720074, 2.481454",\
+ "0.070125, 0.108925, 0.227741, 0.720074, 2.481454",\
+ "0.113963, 0.145559, 0.246252, 0.720074, 2.481454");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.127301, 0.151950, 0.203155, 0.369998, 0.957371",\
+ "0.206362, 0.230972, 0.282119, 0.448933, 1.035102",\
+ "0.309711, 0.336083, 0.388248, 0.554957, 1.142995",\
+ "0.487304, 0.519754, 0.577312, 0.745501, 1.332624",\
+ "0.775221, 0.823575, 0.896452, 1.070131, 1.655247");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.044715, 0.073858, 0.149782, 0.448303, 1.525169",\
+ "0.044715, 0.073858, 0.149782, 0.448303, 1.525169",\
+ "0.053324, 0.079575, 0.152471, 0.448303, 1.525169",\
+ "0.080832, 0.102703, 0.166343, 0.450943, 1.525169",\
+ "0.138432, 0.160382, 0.212572, 0.461516, 1.526821");
+ }
+
+ } /* end of arc padmux2ast_i[1]_obs_ctrl_o[9]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.084586, 0.113378, 0.184446, 0.440600, 1.352120",\
+ "0.171768, 0.200846, 0.271799, 0.528276, 1.439207",\
+ "0.268285, 0.298195, 0.369868, 0.625566, 1.536303",\
+ "0.442396, 0.476138, 0.548327, 0.804981, 1.718362",\
+ "0.738546, 0.782374, 0.862671, 1.116124, 2.025527");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.042344, 0.090303, 0.222464, 0.709820, 2.440521",\
+ "0.043472, 0.090646, 0.222464, 0.709820, 2.440521",\
+ "0.049500, 0.094474, 0.223126, 0.712718, 2.449750",\
+ "0.065555, 0.105654, 0.227159, 0.712718, 2.460771",\
+ "0.105524, 0.141324, 0.243057, 0.716552, 2.462313");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.093008, 0.115079, 0.163442, 0.328951, 0.916956",\
+ "0.178087, 0.200175, 0.248558, 0.413891, 1.001128",\
+ "0.277566, 0.302239, 0.352189, 0.517358, 1.105026",\
+ "0.446802, 0.478509, 0.534068, 0.699312, 1.285539",\
+ "0.721986, 0.770109, 0.842702, 1.014834, 1.597599");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168");
+ values ( "0.036627, 0.065671, 0.143118, 0.443055, 1.519637",\
+ "0.037498, 0.065879, 0.143311, 0.444331, 1.520249",\
+ "0.048608, 0.074072, 0.147057, 0.444933, 1.520249",\
+ "0.075730, 0.097335, 0.160558, 0.448031, 1.520263",\
+ "0.132420, 0.154310, 0.206677, 0.457722, 1.522974");
+ }
+
+ } /* end of arc padmux2ast_i[1]_obs_ctrl_o[9]_una_min*/
+
+} /* end of pin obs_ctrl_o[9] */
+
+pin("obs_ctrl_o[8]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.156168 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001401 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[8];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.560256, 0.740460, 0.927949, 1.229942, 1.813454",\
+ "0.590229, 0.770432, 0.957922, 1.259915, 1.843426",\
+ "0.661974, 0.842177, 1.029667, 1.331659, 1.915171",\
+ "0.918426, 1.098629, 1.286119, 1.588112, 2.171624",\
+ "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\
+ "0.645195, 0.825743, 1.013958, 1.315954, 1.899832",\
+ "0.675168, 0.855715, 1.043931, 1.345927, 1.929805",\
+ "0.746912, 0.927460, 1.115675, 1.417671, 2.001549",\
+ "1.003365, 1.183912, 1.372128, 1.674124, 2.258002",\
+ "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\
+ "0.721107, 0.901186, 1.088767, 1.390551, 1.974005",\
+ "0.751079, 0.931159, 1.118740, 1.420524, 2.003977",\
+ "0.822824, 1.002903, 1.190484, 1.492268, 2.075722",\
+ "1.079277, 1.259356, 1.446937, 1.748721, 2.332174",\
+ "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\
+ "0.775476, 0.955698, 1.143418, 1.445091, 2.028322",\
+ "0.805449, 0.985670, 1.173391, 1.475063, 2.058295",\
+ "0.877193, 1.057415, 1.245135, 1.546808, 2.130039",\
+ "1.133646, 1.313868, 1.501588, 1.803261, 2.386492",\
+ "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\
+ "1.057071, 1.240966, 1.427369, 1.728817, 2.311599",\
+ "1.087044, 1.270938, 1.457341, 1.758790, 2.341572",\
+ "1.158788, 1.342683, 1.529086, 1.830534, 2.413317",\
+ "1.415241, 1.599136, 1.785538, 2.086987, 2.669769",\
+ "2.327707, 2.511601, 2.698004, 2.999453, 3.582235");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.418156, 0.685942, 0.947522, 1.387219, 2.266614",\
+ "0.442597, 0.710383, 0.971963, 1.411660, 2.291055",\
+ "0.493471, 0.761257, 1.022837, 1.462534, 2.341929",\
+ "0.659908, 0.927694, 1.189274, 1.628971, 2.508366",\
+ "1.246791, 1.514577, 1.776157, 2.215854, 3.095249",\
+ "0.506860, 0.774017, 1.036163, 1.475448, 2.354019",\
+ "0.531302, 0.798458, 1.060604, 1.499889, 2.378460",\
+ "0.582175, 0.849332, 1.111478, 1.550763, 2.429334",\
+ "0.748612, 1.015769, 1.277915, 1.717200, 2.595771",\
+ "1.335496, 1.602652, 1.864798, 2.304084, 3.182654",\
+ "0.599803, 0.867162, 1.127888, 1.567612, 2.447061",\
+ "0.624244, 0.891603, 1.152330, 1.592054, 2.471502",\
+ "0.675117, 0.942477, 1.203203, 1.642927, 2.522376",\
+ "0.841555, 1.108914, 1.369640, 1.809364, 2.688813",\
+ "1.428438, 1.695797, 1.956524, 2.396248, 3.275696",\
+ "0.665646, 0.935726, 1.194908, 1.634463, 2.513572",\
+ "0.690087, 0.960168, 1.219349, 1.658904, 2.538013",\
+ "0.740961, 1.011041, 1.270223, 1.709777, 2.588887",\
+ "0.907398, 1.177478, 1.436660, 1.876215, 2.755324",\
+ "1.494281, 1.764362, 2.023544, 2.463098, 3.342207",\
+ "1.012168, 1.316562, 1.565571, 2.003616, 2.879708",\
+ "1.036609, 1.341003, 1.590012, 2.028058, 2.904149",\
+ "1.087482, 1.391877, 1.640886, 2.078931, 2.955022",\
+ "1.253920, 1.558314, 1.807323, 2.245368, 3.121460",\
+ "1.840803, 2.145197, 2.394207, 2.832252, 3.708343");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2698*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.468362, 0.731935, 1.008208, 1.476938, 2.414397",\
+ "0.498334, 0.761908, 1.038180, 1.506910, 2.444369",\
+ "0.570079, 0.833652, 1.109925, 1.578655, 2.516114",\
+ "0.826532, 1.090105, 1.366378, 1.835107, 2.772566",\
+ "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\
+ "0.556556, 0.819476, 1.095776, 1.563653, 2.500330",\
+ "0.586529, 0.849449, 1.125748, 1.593625, 2.530303",\
+ "0.658273, 0.921193, 1.197493, 1.665370, 2.602047",\
+ "0.914726, 1.177646, 1.453945, 1.921822, 2.858500",\
+ "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\
+ "0.644872, 0.908457, 1.183741, 1.651275, 2.587286",\
+ "0.674845, 0.938429, 1.213713, 1.681248, 2.617258",\
+ "0.746589, 1.010174, 1.285458, 1.752992, 2.689003",\
+ "1.003042, 1.266626, 1.541910, 2.009445, 2.945455",\
+ "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\
+ "0.707368, 0.974091, 1.247880, 1.715189, 2.650795",\
+ "0.737341, 1.004064, 1.277853, 1.745162, 2.680767",\
+ "0.809085, 1.075809, 1.349597, 1.816906, 2.752512",\
+ "1.065538, 1.332261, 1.606050, 2.073359, 3.008964",\
+ "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\
+ "1.036494, 1.338422, 1.599747, 2.064539, 2.996251",\
+ "1.066466, 1.368395, 1.629720, 2.094511, 3.026223",\
+ "1.138211, 1.440139, 1.701465, 2.166256, 3.097968",\
+ "1.394664, 1.696592, 1.957917, 2.422708, 3.354420",\
+ "2.307129, 2.609058, 2.870384, 3.335176, 4.266890");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\
+ "2.463890, 2.463890, 2.463889, 2.463887, 2.463883");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.401109, 0.583541, 0.779933, 1.088987, 1.683794",\
+ "0.425551, 0.607982, 0.804374, 1.113428, 1.708236",\
+ "0.476424, 0.658856, 0.855248, 1.164301, 1.759109",\
+ "0.642861, 0.825293, 1.021685, 1.330738, 1.925545",\
+ "1.229745, 1.412177, 1.608569, 1.917621, 2.512428",\
+ "0.488524, 0.670927, 0.867426, 1.176292, 1.771148",\
+ "0.512965, 0.695368, 0.891868, 1.200733, 1.795590",\
+ "0.563839, 0.746242, 0.942741, 1.251606, 1.846463",\
+ "0.730276, 0.912679, 1.109178, 1.418043, 2.012899",\
+ "1.317160, 1.499562, 1.696062, 2.004926, 2.599781",\
+ "0.569400, 0.751263, 0.947453, 1.256320, 1.851179",\
+ "0.593842, 0.775705, 0.971894, 1.280761, 1.875621",\
+ "0.644715, 0.826578, 1.022768, 1.331635, 1.926494",\
+ "0.811152, 0.993015, 1.189205, 1.498072, 2.092930",\
+ "1.398036, 1.579899, 1.776089, 2.084955, 2.679813",\
+ "0.627047, 0.808812, 1.004997, 1.313565, 1.907827",\
+ "0.651488, 0.833253, 1.029438, 1.338006, 1.932269",\
+ "0.702362, 0.884127, 1.080312, 1.388880, 1.983142",\
+ "0.868799, 1.050564, 1.246749, 1.555317, 2.149578",\
+ "1.455682, 1.637447, 1.833632, 2.142200, 2.736460",\
+ "0.929255, 1.114036, 1.308631, 1.616580, 2.209674",\
+ "0.953696, 1.138477, 1.333072, 1.641021, 2.234116",\
+ "1.004569, 1.189351, 1.383945, 1.691895, 2.284989",\
+ "1.171007, 1.355788, 1.550383, 1.858332, 2.451425",\
+ "1.757890, 1.942672, 2.137266, 2.445215, 3.038307");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523417");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2629*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.464386, 0.724016, 0.995888, 1.452767, 2.366527",\
+ "0.494359, 0.753988, 1.025861, 1.482740, 2.396500",\
+ "0.566104, 0.825733, 1.097605, 1.554485, 2.468244",\
+ "0.822556, 1.082185, 1.354057, 1.810937, 2.724696",\
+ "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\
+ "0.552491, 0.811549, 1.083418, 1.539483, 2.452461",\
+ "0.582464, 0.841522, 1.113391, 1.569456, 2.482434",\
+ "0.654208, 0.913266, 1.185135, 1.641200, 2.554178",\
+ "0.910661, 1.169719, 1.441588, 1.897652, 2.810630",\
+ "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\
+ "0.640521, 0.900515, 1.171383, 1.627106, 2.539416",\
+ "0.670494, 0.930488, 1.201355, 1.657078, 2.569389",\
+ "0.742239, 1.002232, 1.273100, 1.728823, 2.641133",\
+ "0.998691, 1.258685, 1.529552, 1.985275, 2.897585",\
+ "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\
+ "0.702743, 0.966129, 1.235520, 1.691019, 2.602925",\
+ "0.732715, 0.996101, 1.265493, 1.720992, 2.632898",\
+ "0.804460, 1.067846, 1.337237, 1.792736, 2.704642",\
+ "1.060912, 1.324298, 1.593690, 2.049189, 2.961094",\
+ "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\
+ "1.030130, 1.330203, 1.587268, 2.040320, 2.948381",\
+ "1.060103, 1.360176, 1.617240, 2.070293, 2.978354",\
+ "1.131847, 1.431921, 1.688985, 2.142037, 3.050098",\
+ "1.388300, 1.688373, 1.945437, 2.398489, 3.306550",\
+ "2.300766, 2.600840, 2.857904, 3.310957, 4.219019");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\
+ "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\
+ "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\
+ "2.463890, 2.463889, 2.463888, 2.463885, 2.463879");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.399448, 0.581989, 0.778244, 1.087461, 1.682757",\
+ "0.423889, 0.606430, 0.802685, 1.111902, 1.707199",\
+ "0.474763, 0.657304, 0.853558, 1.162776, 1.758072",\
+ "0.641200, 0.823741, 1.019996, 1.329213, 1.924508",\
+ "1.228083, 1.410624, 1.606879, 1.916096, 2.511390",\
+ "0.486868, 0.669374, 0.865736, 1.174766, 1.770111",\
+ "0.511309, 0.693815, 0.890178, 1.199207, 1.794553",\
+ "0.562183, 0.744689, 0.941051, 1.250081, 1.845426",\
+ "0.728620, 0.911126, 1.107488, 1.416518, 2.011862",\
+ "1.315503, 1.498010, 1.694372, 2.003401, 2.598744",\
+ "0.567735, 0.749711, 0.945763, 1.254794, 1.850142",\
+ "0.592177, 0.774152, 0.970205, 1.279236, 1.874584",\
+ "0.643050, 0.825026, 1.021078, 1.330109, 1.925457",\
+ "0.809487, 0.991463, 1.187515, 1.496546, 2.091893",\
+ "1.396371, 1.578347, 1.774399, 2.083429, 2.678775",\
+ "0.625374, 0.807260, 1.003307, 1.312040, 1.906790",\
+ "0.649816, 0.831701, 1.027748, 1.336481, 1.931232",\
+ "0.700689, 0.882574, 1.078622, 1.387354, 1.982105",\
+ "0.867126, 1.049011, 1.245059, 1.553791, 2.148541",\
+ "1.454010, 1.635895, 1.831943, 2.140674, 2.735423",\
+ "0.927469, 1.112486, 1.306941, 1.615054, 2.208637",\
+ "0.951911, 1.136927, 1.331383, 1.639496, 2.233079",\
+ "1.002784, 1.187801, 1.382256, 1.690369, 2.283952",\
+ "1.169221, 1.354238, 1.548693, 1.856806, 2.450387",\
+ "1.756105, 1.941121, 2.135577, 2.443689, 3.037270");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\
+ "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523416");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2576*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.556670, 0.735097, 0.915357, 1.201564, 1.752681",\
+ "0.586643, 0.765069, 0.945330, 1.231536, 1.782653",\
+ "0.658387, 0.836814, 1.017074, 1.303281, 1.854398",\
+ "0.914840, 1.093267, 1.273527, 1.559734, 2.110850",\
+ "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\
+ "0.641609, 0.820369, 1.001272, 1.287484, 1.839059",\
+ "0.671581, 0.850342, 1.031245, 1.317456, 1.869031",\
+ "0.743326, 0.922086, 1.102990, 1.389201, 1.940776",\
+ "0.999778, 1.178539, 1.359442, 1.645654, 2.197229",\
+ "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\
+ "0.717515, 0.895813, 1.076081, 1.362081, 1.913231",\
+ "0.747487, 0.925785, 1.106054, 1.392053, 1.943204",\
+ "0.819232, 0.997530, 1.177799, 1.463798, 2.014948",\
+ "1.075685, 1.253982, 1.434251, 1.720250, 2.271401",\
+ "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\
+ "0.771867, 0.950324, 1.130732, 1.416620, 1.967548",\
+ "0.801839, 0.980297, 1.160705, 1.446593, 1.997521",\
+ "0.873584, 1.052042, 1.232450, 1.518338, 2.069266",\
+ "1.130037, 1.308494, 1.488902, 1.774790, 2.325718",\
+ "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\
+ "1.053289, 1.235552, 1.414683, 1.700347, 2.250826",\
+ "1.083261, 1.265524, 1.444655, 1.730319, 2.280799",\
+ "1.155006, 1.337269, 1.516400, 1.802064, 2.352543",\
+ "1.411458, 1.593722, 1.772853, 2.058517, 2.608996",\
+ "2.323924, 2.506187, 2.685318, 2.970983, 3.521462");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\
+ "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\
+ "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\
+ "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\
+ "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\
+ "2.463890, 2.463890, 2.463890, 2.463890, 2.463890");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.416720, 0.681890, 0.941092, 1.377274, 2.249640",\
+ "0.441162, 0.706331, 0.965533, 1.401715, 2.274081",\
+ "0.492035, 0.757205, 1.016407, 1.452589, 2.324954",\
+ "0.658472, 0.923642, 1.182844, 1.619026, 2.491391",\
+ "1.245356, 1.510525, 1.769727, 2.205910, 3.078275",\
+ "0.505386, 0.769965, 1.029733, 1.465503, 2.337044",\
+ "0.529827, 0.794406, 1.054174, 1.489944, 2.361485",\
+ "0.580701, 0.845280, 1.105047, 1.540818, 2.412359",\
+ "0.747138, 1.011717, 1.271485, 1.707255, 2.578796",\
+ "1.334021, 1.598600, 1.858368, 2.294138, 3.165680",\
+ "0.598193, 0.863088, 1.121458, 1.557667, 2.430086",\
+ "0.622634, 0.887529, 1.145899, 1.582108, 2.454527",\
+ "0.673507, 0.938403, 1.196773, 1.632982, 2.505401",\
+ "0.839945, 1.104840, 1.363210, 1.799419, 2.671838",\
+ "1.426828, 1.691723, 1.950093, 2.386303, 3.258722",\
+ "0.663915, 0.931622, 1.188478, 1.624518, 2.496598",\
+ "0.688356, 0.956063, 1.212919, 1.648959, 2.521039",\
+ "0.739230, 1.006937, 1.263793, 1.699832, 2.571912",\
+ "0.905667, 1.173374, 1.430230, 1.866270, 2.738349",\
+ "1.492550, 1.760257, 2.017113, 2.453153, 3.325233",\
+ "1.009705, 1.312121, 1.559108, 1.993649, 2.862731",\
+ "1.034146, 1.336562, 1.583549, 2.018090, 2.887172",\
+ "1.085019, 1.387435, 1.634423, 2.068964, 2.938045",\
+ "1.251456, 1.553873, 1.800860, 2.235401, 3.104483",\
+ "1.838340, 2.140756, 2.387743, 2.822284, 3.691366");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\
+ "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\
+ "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\
+ "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\
+ "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\
+ "1.523418, 1.523418, 1.523418, 1.523418, 1.523419");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2513*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.323944, 0.353916, 0.425661, 0.682114, 1.594576",\
+ "0.411334, 0.441307, 0.513052, 0.769505, 1.681967",\
+ "0.492253, 0.522226, 0.593971, 0.850424, 1.762885",\
+ "0.549994, 0.579967, 0.651712, 0.908165, 1.820624",\
+ "0.852699, 0.882672, 0.954417, 1.210871, 2.123326");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.045711, 0.092269, 0.223658, 0.715775, 2.463871",\
+ "0.045711, 0.092269, 0.223735, 0.715775, 2.463871",\
+ "0.045711, 0.092269, 0.223968, 0.715775, 2.463871",\
+ "0.045711, 0.092270, 0.223968, 0.715775, 2.463871",\
+ "0.045873, 0.092295, 0.224303, 0.715788, 2.463884");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.296604, 0.321045, 0.371919, 0.538356, 1.125239",\
+ "0.383997, 0.408438, 0.459311, 0.625749, 1.212632",\
+ "0.464866, 0.489307, 0.540181, 0.706618, 1.293501",\
+ "0.522515, 0.546956, 0.597830, 0.764267, 1.351150",\
+ "0.825652, 0.850326, 0.901556, 1.068388, 1.654962");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.044220, 0.073393, 0.149516, 0.447701, 1.524168",\
+ "0.044220, 0.073393, 0.149516, 0.447701, 1.524168",\
+ "0.044220, 0.073393, 0.149516, 0.447701, 1.524042",\
+ "0.044220, 0.073393, 0.149516, 0.447701, 1.523806",\
+ "0.044219, 0.073327, 0.149516, 0.447696, 1.523418");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.507461, 0.687575, 0.875153, 1.177133, 1.760229",\
+ "0.536439, 0.716552, 0.904131, 1.206110, 1.789207",\
+ "0.607591, 0.787705, 0.975283, 1.277263, 1.860359",\
+ "0.863316, 1.043430, 1.231008, 1.532988, 2.116084",\
+ "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\
+ "0.592400, 0.772411, 0.960223, 1.262639, 1.846608",\
+ "0.621377, 0.801388, 0.989201, 1.291617, 1.875585",\
+ "0.692529, 0.872540, 1.060353, 1.362769, 1.946737",\
+ "0.948255, 1.128266, 1.316078, 1.618494, 2.202463",\
+ "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\
+ "0.668312, 0.847854, 1.035032, 1.337236, 1.920780",\
+ "0.697289, 0.876831, 1.064010, 1.366214, 1.949757",\
+ "0.768441, 0.947984, 1.135162, 1.437366, 2.020910",\
+ "1.024167, 1.203709, 1.390887, 1.693091, 2.276635",\
+ "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\
+ "0.722681, 0.902605, 1.089921, 1.391842, 1.975097",\
+ "0.751658, 0.931583, 1.118899, 1.420819, 2.004075",\
+ "0.822811, 1.002735, 1.190051, 1.491971, 2.075227",\
+ "1.078536, 1.258460, 1.445776, 1.747697, 2.330952",\
+ "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\
+ "1.004276, 1.188170, 1.374097, 1.675568, 2.258375",\
+ "1.033253, 1.217148, 1.403074, 1.704545, 2.287352",\
+ "1.104405, 1.288300, 1.474226, 1.775698, 2.358505",\
+ "1.360131, 1.544025, 1.729952, 2.031423, 2.614230",\
+ "2.270849, 2.454743, 2.640669, 2.942141, 3.524948");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.389483, 0.657094, 0.918495, 1.358271, 2.237432",\
+ "0.411493, 0.679104, 0.940496, 1.380242, 2.259341",\
+ "0.459519, 0.727130, 0.988522, 1.428268, 2.307366",\
+ "0.624827, 0.892438, 1.153830, 1.593576, 2.472674",\
+ "1.214436, 1.482046, 1.743447, 2.183224, 3.062385",\
+ "0.478187, 0.745169, 1.007135, 1.446501, 2.324838",\
+ "0.500198, 0.767179, 1.029137, 1.468471, 2.346746",\
+ "0.548223, 0.815205, 1.077163, 1.516497, 2.394772",\
+ "0.713532, 0.980513, 1.242471, 1.681805, 2.560080",\
+ "1.303140, 1.570121, 1.832088, 2.271453, 3.149790",\
+ "0.571129, 0.838489, 1.099180, 1.538746, 2.417880",\
+ "0.593140, 0.860499, 1.121182, 1.560717, 2.439788",\
+ "0.641166, 0.908525, 1.169207, 1.608743, 2.487813",\
+ "0.806474, 1.073833, 1.334516, 1.774051, 2.653121",\
+ "1.396082, 1.663441, 1.924133, 2.363699, 3.242832",\
+ "0.636973, 0.907053, 1.166236, 1.605758, 2.484801",\
+ "0.658983, 0.929063, 1.188238, 1.627728, 2.506709",\
+ "0.707009, 0.977089, 1.236264, 1.675754, 2.554735",\
+ "0.872317, 1.142398, 1.401572, 1.841062, 2.720043",\
+ "1.461926, 1.732006, 1.991189, 2.430710, 3.309754",\
+ "0.983494, 1.287889, 1.536907, 1.974983, 2.851137",\
+ "1.005505, 1.309899, 1.558908, 1.996953, 2.873044",\
+ "1.053531, 1.357925, 1.606934, 2.044979, 2.921070",\
+ "1.218839, 1.523233, 1.772242, 2.210288, 3.086378",\
+ "1.808447, 2.112841, 2.361860, 2.799936, 3.676089");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2454*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.415570, 0.679101, 0.955220, 1.423352, 2.358356",\
+ "0.444547, 0.708078, 0.984198, 1.452330, 2.387333",\
+ "0.515699, 0.779231, 1.055350, 1.523482, 2.458486",\
+ "0.771425, 1.034956, 1.311076, 1.779207, 2.714211",\
+ "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\
+ "0.503764, 0.766641, 1.042787, 1.510067, 2.444290",\
+ "0.532741, 0.795619, 1.071764, 1.539045, 2.473267",\
+ "0.603894, 0.866771, 1.142917, 1.610197, 2.544420",\
+ "0.859619, 1.122496, 1.398642, 1.865922, 2.800145",\
+ "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\
+ "0.592080, 0.855621, 1.130752, 1.597708, 2.531245",\
+ "0.621057, 0.884598, 1.159729, 1.626685, 2.560222",\
+ "0.692210, 0.955751, 1.230882, 1.697837, 2.631375",\
+ "0.947935, 1.211476, 1.486607, 1.953563, 2.887100",\
+ "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\
+ "0.654576, 0.921255, 1.194892, 1.661796, 2.594754",\
+ "0.683553, 0.950232, 1.223869, 1.690774, 2.623731",\
+ "0.754706, 1.021384, 1.295022, 1.761926, 2.694884",\
+ "1.010431, 1.277110, 1.550747, 2.017652, 2.950609",\
+ "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\
+ "0.983702, 1.285569, 1.546756, 2.011240, 2.940210",\
+ "1.012679, 1.314547, 1.575733, 2.040218, 2.969187",\
+ "1.083832, 1.385699, 1.646886, 2.111370, 3.040340",\
+ "1.339557, 1.641424, 1.902611, 2.367095, 3.296065",\
+ "2.250275, 2.552142, 2.813329, 3.277813, 4.206782");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\
+ "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\
+ "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\
+ "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\
+ "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\
+ "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\
+ "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\
+ "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\
+ "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\
+ "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\
+ "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\
+ "2.448223, 2.448223, 2.448224, 2.448226, 2.448230");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.372438, 0.554496, 0.750729, 1.059908, 1.654385",\
+ "0.394447, 0.576504, 0.772637, 1.081769, 1.676222",\
+ "0.442472, 0.624530, 0.820663, 1.129795, 1.724248",\
+ "0.607781, 0.789838, 0.985971, 1.295103, 1.889559",\
+ "1.197391, 1.379448, 1.575682, 1.884862, 2.479345",\
+ "0.459853, 0.641814, 0.838010, 1.147213, 1.741738",\
+ "0.481861, 0.663823, 0.859918, 1.169074, 1.763576",\
+ "0.529887, 0.711849, 0.907944, 1.217100, 1.811602",\
+ "0.695195, 0.877157, 1.073252, 1.382408, 1.976912",\
+ "1.284805, 1.466767, 1.662963, 1.972167, 2.566699",\
+ "0.540729, 0.722151, 0.918037, 1.227241, 1.821770",\
+ "0.562738, 0.744159, 0.939945, 1.249102, 1.843607",\
+ "0.610763, 0.792185, 0.987971, 1.297128, 1.891634",\
+ "0.776072, 0.957493, 1.153279, 1.462437, 2.056944",\
+ "1.365682, 1.547103, 1.742990, 2.052196, 2.646730",\
+ "0.598376, 0.779988, 0.975773, 1.284712, 1.878866",\
+ "0.620384, 0.801996, 0.997680, 1.306573, 1.900703",\
+ "0.668410, 0.850022, 1.045706, 1.354599, 1.948729",\
+ "0.833718, 1.015330, 1.211014, 1.519907, 2.114039",\
+ "1.423328, 1.604940, 1.800725, 2.109667, 2.703826",\
+ "0.900583, 1.085365, 1.279436, 1.587919, 2.181184",\
+ "0.922592, 1.107373, 1.301344, 1.609780, 2.203021",\
+ "0.970618, 1.155399, 1.349370, 1.657806, 2.251047",\
+ "1.135926, 1.320707, 1.514678, 1.823114, 2.416358",\
+ "1.725536, 1.910317, 2.104389, 2.412873, 3.006144");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443183, 0.443195",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443183, 0.443195",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443183, 0.443195",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443183, 0.443196",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443183, 0.443196",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2376*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.411592, 0.671151, 0.942786, 1.398947, 2.310115",\
+ "0.440569, 0.700128, 0.971763, 1.427925, 2.339092",\
+ "0.511721, 0.771281, 1.042916, 1.499077, 2.410245",\
+ "0.767447, 1.027006, 1.298641, 1.754802, 2.665970",\
+ "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\
+ "0.499696, 0.758684, 1.030315, 1.485663, 2.396049",\
+ "0.528674, 0.787661, 1.059292, 1.514640, 2.425026",\
+ "0.599826, 0.858813, 1.130445, 1.585792, 2.496178",\
+ "0.855551, 1.114539, 1.386170, 1.841518, 2.751904",\
+ "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\
+ "0.587726, 0.847648, 1.118279, 1.573302, 2.483004",\
+ "0.616704, 0.876625, 1.147256, 1.602279, 2.511981",\
+ "0.687856, 0.947778, 1.218409, 1.673431, 2.583133",\
+ "0.943582, 1.203503, 1.474134, 1.929157, 2.838859",\
+ "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\
+ "0.649948, 0.913259, 1.182417, 1.637376, 2.546513",\
+ "0.678925, 0.942237, 1.211394, 1.666353, 2.575490",\
+ "0.750077, 1.013389, 1.282547, 1.737506, 2.646642",\
+ "1.005803, 1.269114, 1.538272, 1.993231, 2.902368",\
+ "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\
+ "0.977335, 1.277308, 1.534159, 1.986762, 2.891969",\
+ "1.006312, 1.306285, 1.563137, 2.015740, 2.920946",\
+ "1.077465, 1.377437, 1.634289, 2.086892, 2.992099",\
+ "1.333190, 1.633163, 1.890014, 2.342618, 3.247824",\
+ "2.243908, 2.543881, 2.800732, 3.253335, 4.158542");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\
+ "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\
+ "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\
+ "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\
+ "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\
+ "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\
+ "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\
+ "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\
+ "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\
+ "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\
+ "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\
+ "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\
+ "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\
+ "2.448223, 2.448223, 2.448225, 2.448228, 2.448234");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.370774, 0.552942, 0.749040, 1.058378, 1.653339",\
+ "0.392785, 0.574952, 0.770949, 1.080242, 1.675184",\
+ "0.440811, 0.622978, 0.818975, 1.128268, 1.723211",\
+ "0.606119, 0.788286, 0.984283, 1.293577, 1.888521",\
+ "1.195727, 1.377894, 1.573993, 1.883330, 2.478289",\
+ "0.458194, 0.640260, 0.836321, 1.145683, 1.740692",\
+ "0.480205, 0.662271, 0.858230, 1.167547, 1.762538",\
+ "0.528231, 0.710297, 0.906256, 1.215573, 1.810564",\
+ "0.693539, 0.875605, 1.071564, 1.380882, 1.975875",\
+ "1.283147, 1.465213, 1.661273, 1.970635, 2.565643",\
+ "0.539062, 0.720597, 0.916348, 1.225712, 1.820724",\
+ "0.561073, 0.742608, 0.938257, 1.247576, 1.842569",\
+ "0.609098, 0.790634, 0.986283, 1.295602, 1.890596",\
+ "0.774407, 0.955942, 1.151591, 1.460911, 2.055906",\
+ "1.364015, 1.545550, 1.741300, 2.050663, 2.645674",\
+ "0.596701, 0.778434, 0.974083, 1.283183, 1.877821",\
+ "0.618712, 0.800445, 0.995992, 1.305047, 1.899666",\
+ "0.666737, 0.848471, 1.044018, 1.353073, 1.947692",\
+ "0.832046, 1.013779, 1.209326, 1.518381, 2.113003",\
+ "1.421654, 1.603387, 1.799036, 2.108135, 2.702771",\
+ "0.898796, 1.083812, 1.277747, 1.586390, 2.180140",\
+ "0.920807, 1.105823, 1.299656, 1.608254, 2.201985",\
+ "0.968832, 1.153849, 1.347681, 1.656280, 2.250011",\
+ "1.134141, 1.319157, 1.512989, 1.821589, 2.415322",\
+ "1.723749, 1.908765, 2.102699, 2.411342, 3.005090");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\
+ "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\
+ "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\
+ "1.518758, 1.518758, 1.518758, 1.518759, 1.518761");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2318*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.503875, 0.682214, 0.862561, 1.148748, 1.699501",\
+ "0.532852, 0.711192, 0.891538, 1.177725, 1.728478",\
+ "0.604005, 0.782344, 0.962691, 1.248877, 1.799630",\
+ "0.859730, 1.038069, 1.218416, 1.504603, 2.055356",\
+ "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\
+ "0.588813, 0.767050, 0.947631, 1.234254, 1.785879",\
+ "0.617791, 0.796027, 0.976608, 1.263231, 1.814857",\
+ "0.688943, 0.867180, 1.047761, 1.334384, 1.886009",\
+ "0.944668, 1.122905, 1.303486, 1.590109, 2.141734",\
+ "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\
+ "0.664719, 0.842493, 1.022440, 1.308851, 1.860052",\
+ "0.693697, 0.871471, 1.051417, 1.337828, 1.889029",\
+ "0.764849, 0.942623, 1.122570, 1.408980, 1.960181",\
+ "1.020574, 1.198349, 1.378295, 1.664706, 2.215907",\
+ "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\
+ "0.719071, 0.897239, 1.077305, 1.363444, 1.914369",\
+ "0.748049, 0.926216, 1.106283, 1.392421, 1.943346",\
+ "0.819201, 0.997369, 1.177435, 1.463574, 2.014498",\
+ "1.074926, 1.253094, 1.433160, 1.719299, 2.270224",\
+ "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\
+ "1.000493, 1.182756, 1.361458, 1.647171, 2.197646",\
+ "1.029471, 1.211734, 1.390436, 1.676148, 2.226624",\
+ "1.100623, 1.282886, 1.461588, 1.747300, 2.297776",\
+ "1.356348, 1.538611, 1.717313, 2.003026, 2.553502",\
+ "2.267066, 2.449329, 2.628031, 2.913743, 3.464219");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\
+ "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\
+ "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\
+ "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\
+ "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\
+ "2.448223, 2.448223, 2.448223, 2.448223, 2.448223");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.388047, 0.653046, 0.912076, 1.348340, 2.220486",\
+ "0.410058, 0.675057, 0.934076, 1.370306, 2.242383",\
+ "0.458083, 0.723083, 0.982102, 1.418332, 2.290410",\
+ "0.623392, 0.888391, 1.147410, 1.583640, 2.455718",\
+ "1.213000, 1.477999, 1.737028, 2.173293, 3.045439",\
+ "0.476712, 0.741121, 1.000716, 1.436569, 2.307892",\
+ "0.498723, 0.763132, 1.022717, 1.458535, 2.329789",\
+ "0.546749, 0.811157, 1.070743, 1.506561, 2.377815",\
+ "0.712057, 0.976466, 1.236051, 1.671869, 2.543123",\
+ "1.301665, 1.566074, 1.825669, 2.261521, 3.132844",\
+ "0.569519, 0.834415, 1.092752, 1.528812, 2.400934",\
+ "0.591530, 0.856425, 1.114753, 1.550778, 2.422831",\
+ "0.639556, 0.904451, 1.162778, 1.598804, 2.470856",\
+ "0.804864, 1.069759, 1.328087, 1.764112, 2.636164",\
+ "1.394472, 1.659367, 1.917704, 2.353765, 3.225886",\
+ "0.635242, 0.902949, 1.159807, 1.595819, 2.467843",\
+ "0.657252, 0.924959, 1.181808, 1.617785, 2.489740",\
+ "0.705278, 0.972985, 1.229833, 1.665811, 2.537766",\
+ "0.870586, 1.138293, 1.395142, 1.831119, 2.703074",\
+ "1.460194, 1.727901, 1.984760, 2.420771, 3.292796",\
+ "0.981031, 1.283447, 1.530445, 1.965020, 2.834170",\
+ "1.003042, 1.305458, 1.552445, 1.986986, 2.856067",\
+ "1.051068, 1.353484, 1.600471, 2.035012, 2.904093",\
+ "1.216376, 1.518792, 1.765779, 2.200320, 3.069401",\
+ "1.805984, 2.108400, 2.355398, 2.789973, 3.659123");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\
+ "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\
+ "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\
+ "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\
+ "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\
+ "1.518758, 1.518758, 1.518758, 1.518758, 1.518758");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2260*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.141425, 0.170720, 0.242339, 0.498612, 1.411098",\
+ "0.229610, 0.258905, 0.330536, 0.586854, 1.499024",\
+ "0.317934, 0.347229, 0.418864, 0.675374, 1.587106",\
+ "0.380526, 0.409818, 0.481403, 0.738206, 1.650402",\
+ "0.710407, 0.739695, 0.811101, 1.068343, 1.982165");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\
+ "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\
+ "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\
+ "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\
+ "0.042748, 0.089888, 0.222179, 0.711766, 2.448223");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.179776, 0.202485, 0.251521, 0.417224, 1.003880",\
+ "0.267179, 0.289888, 0.338925, 0.504627, 1.091283",\
+ "0.348077, 0.370784, 0.419825, 0.585531, 1.172197",\
+ "0.405741, 0.428442, 0.477491, 0.643206, 1.229887",\
+ "0.708098, 0.730789, 0.779867, 0.945650, 1.532504");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.035639, 0.064458, 0.142274, 0.442345, 1.516474",\
+ "0.035639, 0.064458, 0.142274, 0.442345, 1.516474",\
+ "0.035639, 0.064458, 0.142274, 0.442391, 1.516474",\
+ "0.035639, 0.064458, 0.142274, 0.442476, 1.516474",\
+ "0.035639, 0.064458, 0.142274, 0.443177, 1.516474");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_falling ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.454726, 0.454726, 0.454726, 0.454726, 0.454726",\
+ "0.473076, 0.473076, 0.473076, 0.473076, 0.473076",\
+ "0.545703, 0.545703, 0.545703, 0.545703, 0.545703",\
+ "0.640171, 0.640171, 0.640171, 0.640171, 0.640171",\
+ "1.087704, 1.087704, 1.087704, 1.087704, 1.087704");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.201983, 0.201983, 0.201983, 0.201983, 0.201983",\
+ "0.219410, 0.219410, 0.219410, 0.219410, 0.219410",\
+ "0.296741, 0.296741, 0.296741, 0.296741, 0.296741",\
+ "0.405665, 0.405665, 0.405665, 0.405665, 0.405665",\
+ "0.925258, 0.925258, 0.925258, 0.925258, 0.925258");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_cgsf*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.450859, -0.450859, -0.450859, -0.450859, -0.450859",\
+ "-0.467474, -0.467474, -0.467474, -0.467474, -0.467474",\
+ "-0.541835, -0.541835, -0.541835, -0.541835, -0.541835",\
+ "-0.636302, -0.636302, -0.636302, -0.636302, -0.636302",\
+ "-1.083807, -1.083807, -1.083807, -1.083807, -1.083807");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.194280, -0.194280, -0.194280, -0.194280, -0.194280",\
+ "-0.207626, -0.207626, -0.207626, -0.207626, -0.207626",\
+ "-0.289038, -0.289038, -0.289038, -0.289038, -0.289038",\
+ "-0.398036, -0.398036, -0.398036, -0.398036, -0.398036",\
+ "-0.918416, -0.918416, -0.918416, -0.918416, -0.918416");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_cghr*/
+
+ timing () {
+ related_pin : "padmux2ast_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.088658, 0.118400, 0.189731, 0.445655, 1.359203",\
+ "0.176289, 0.206081, 0.277284, 0.533409, 1.444562",\
+ "0.273999, 0.305373, 0.377262, 0.633109, 1.547694",\
+ "0.451720, 0.486942, 0.560777, 0.816366, 1.732299",\
+ "0.754684, 0.801348, 0.884176, 1.139736, 2.048527");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.044533, 0.091199, 0.223344, 0.717968, 2.481454",\
+ "0.045427, 0.091448, 0.223344, 0.719590, 2.481454",\
+ "0.052404, 0.096040, 0.223344, 0.719590, 2.481454",\
+ "0.069791, 0.108505, 0.227261, 0.719590, 2.481454",\
+ "0.113693, 0.145215, 0.245785, 0.719590, 2.481454");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.127074, 0.151791, 0.203016, 0.369861, 0.957397",\
+ "0.206135, 0.230814, 0.281980, 0.448797, 1.035129",\
+ "0.309463, 0.335921, 0.388109, 0.554820, 1.143022",\
+ "0.486985, 0.519573, 0.577173, 0.745365, 1.332651",\
+ "0.774720, 0.823340, 0.896308, 1.069995, 1.655274");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.044476, 0.073631, 0.149535, 0.448052, 1.525218",\
+ "0.044476, 0.073631, 0.149535, 0.448052, 1.525218",\
+ "0.053117, 0.079360, 0.152226, 0.448052, 1.525218",\
+ "0.080664, 0.102519, 0.166108, 0.450694, 1.525218",\
+ "0.138236, 0.160233, 0.212368, 0.461268, 1.526869");
+ }
+
+ } /* end of arc padmux2ast_i[0]_obs_ctrl_o[8]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.084296, 0.113120, 0.184192, 0.440347, 1.352120",\
+ "0.171472, 0.200589, 0.271545, 0.528022, 1.439207",\
+ "0.267978, 0.297935, 0.369614, 0.625313, 1.536303",\
+ "0.442024, 0.475873, 0.548072, 0.804727, 1.718362",\
+ "0.738029, 0.782075, 0.862420, 1.115871, 2.025527");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.041900, 0.089823, 0.221979, 0.709338, 2.440521",\
+ "0.043039, 0.090167, 0.221979, 0.709338, 2.440521",\
+ "0.049089, 0.094012, 0.222641, 0.712232, 2.449750",\
+ "0.065208, 0.105222, 0.226678, 0.712232, 2.460771",\
+ "0.105185, 0.140977, 0.242589, 0.716067, 2.462313");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.092809, 0.114931, 0.163305, 0.328814, 0.916983",\
+ "0.177889, 0.200026, 0.248421, 0.413754, 1.001155",\
+ "0.277335, 0.302085, 0.352052, 0.517221, 1.105053",\
+ "0.446489, 0.478335, 0.533931, 0.699176, 1.285565",\
+ "0.721488, 0.769874, 0.842559, 1.014698, 1.597625");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168");
+ values ( "0.036394, 0.065440, 0.142870, 0.442805, 1.519686",\
+ "0.037274, 0.065647, 0.143061, 0.444080, 1.520298",\
+ "0.048413, 0.073856, 0.146810, 0.444683, 1.520298",\
+ "0.075564, 0.097153, 0.160320, 0.447782, 1.520312",\
+ "0.132225, 0.154160, 0.206470, 0.457474, 1.523023");
+ }
+
+ } /* end of arc padmux2ast_i[0]_obs_ctrl_o[8]_una_min*/
+
+} /* end of pin obs_ctrl_o[8] */
+
+pin("obs_ctrl_o[7]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.094370 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001120 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[7];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.560132, 0.740335, 0.927825, 1.229818, 1.813330",\
+ "0.598058, 0.778261, 0.965751, 1.267744, 1.851256",\
+ "0.679713, 0.859917, 1.047406, 1.349399, 1.932911",\
+ "0.950162, 1.130366, 1.317855, 1.619848, 2.203360",\
+ "1.836798, 2.017001, 2.204491, 2.506483, 3.089995",\
+ "0.645071, 0.825618, 1.013834, 1.315830, 1.899708",\
+ "0.682997, 0.863544, 1.051760, 1.353756, 1.937634",\
+ "0.764652, 0.945200, 1.133415, 1.435411, 2.019289",\
+ "1.035101, 1.215649, 1.403864, 1.705860, 2.289738",\
+ "1.921736, 2.102284, 2.290499, 2.592495, 3.176373",\
+ "0.720983, 0.901062, 1.088643, 1.390427, 1.973880",\
+ "0.758909, 0.938988, 1.126569, 1.428353, 2.011806",\
+ "0.840564, 1.020643, 1.208224, 1.510008, 2.093462",\
+ "1.111013, 1.291092, 1.478673, 1.780457, 2.363911",\
+ "1.997648, 2.177727, 2.365308, 2.667092, 3.250545",\
+ "0.775352, 0.955573, 1.143294, 1.444967, 2.028198",\
+ "0.813278, 0.993499, 1.181220, 1.482893, 2.066123",\
+ "0.894933, 1.075155, 1.262875, 1.564548, 2.147779",\
+ "1.165382, 1.345604, 1.533324, 1.834997, 2.418228",\
+ "2.052018, 2.232239, 2.419959, 2.721632, 3.304862",\
+ "1.056947, 1.240841, 1.427244, 1.728693, 2.311475",\
+ "1.094873, 1.278767, 1.465170, 1.766619, 2.349401",\
+ "1.176528, 1.360423, 1.546826, 1.848274, 2.431056",\
+ "1.446977, 1.630872, 1.817275, 2.118723, 2.701505",\
+ "2.333612, 2.517507, 2.703910, 3.005358, 3.588140");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.442149, 0.709934, 0.971514, 1.411211, 2.290606",\
+ "0.473003, 0.740789, 1.002369, 1.442066, 2.321460",\
+ "0.534512, 0.802297, 1.063877, 1.503574, 2.382968",\
+ "0.730402, 0.998188, 1.259768, 1.699465, 2.578859",\
+ "1.368610, 1.636396, 1.897976, 2.337672, 3.217067",\
+ "0.530853, 0.798009, 1.060155, 1.499440, 2.378011",\
+ "0.561708, 0.828864, 1.091010, 1.530295, 2.408865",\
+ "0.623216, 0.890372, 1.152518, 1.591803, 2.470374",\
+ "0.819106, 1.086263, 1.348409, 1.787694, 2.666264",\
+ "1.457314, 1.724471, 1.986617, 2.425902, 3.304472",\
+ "0.623795, 0.891154, 1.151881, 1.591604, 2.471052",\
+ "0.654650, 0.922009, 1.182735, 1.622459, 2.501907",\
+ "0.716158, 0.983517, 1.244244, 1.683967, 2.563416",\
+ "0.912048, 1.179408, 1.440134, 1.879858, 2.759306",\
+ "1.550256, 1.817616, 2.078342, 2.518066, 3.397514",\
+ "0.689639, 0.959719, 1.218900, 1.658455, 2.537564",\
+ "0.720493, 0.990574, 1.249755, 1.689310, 2.568418",\
+ "0.782001, 1.052082, 1.311263, 1.750818, 2.629927",\
+ "0.977892, 1.247972, 1.507154, 1.946708, 2.825817",\
+ "1.616100, 1.886180, 2.145362, 2.584916, 3.464025",\
+ "1.036160, 1.340554, 1.589563, 2.027608, 2.903699",\
+ "1.067015, 1.371409, 1.620418, 2.058463, 2.934554",\
+ "1.128523, 1.432917, 1.681926, 2.119972, 2.996062",\
+ "1.324414, 1.628808, 1.877817, 2.315862, 3.191953",\
+ "1.962622, 2.267016, 2.516025, 2.954070, 3.830161");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\
+ "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\
+ "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\
+ "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\
+ "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2746*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.468238, 0.731811, 1.008084, 1.476814, 2.414274",\
+ "0.506163, 0.769737, 1.046010, 1.514740, 2.452199",\
+ "0.587819, 0.851392, 1.127665, 1.596395, 2.533855",\
+ "0.858268, 1.121841, 1.398114, 1.866844, 2.804303",\
+ "1.744903, 2.008476, 2.284747, 2.753474, 3.690928",\
+ "0.556432, 0.819352, 1.095652, 1.563529, 2.500207",\
+ "0.594358, 0.857278, 1.133578, 1.601455, 2.538133",\
+ "0.676013, 0.938933, 1.215233, 1.683110, 2.619789",\
+ "0.946462, 1.209382, 1.485682, 1.953559, 2.890237",\
+ "1.833097, 2.096017, 2.372314, 2.840189, 3.776862",\
+ "0.644748, 0.908332, 1.183617, 1.651152, 2.587162",\
+ "0.682674, 0.946258, 1.221542, 1.689077, 2.625088",\
+ "0.764329, 1.027914, 1.303198, 1.770733, 2.706744",\
+ "1.034778, 1.298362, 1.573647, 2.041182, 2.977192",\
+ "1.921414, 2.184997, 2.460279, 2.927812, 3.863817",\
+ "0.707244, 0.973967, 1.247756, 1.715065, 2.650671",\
+ "0.745170, 1.011893, 1.285682, 1.752991, 2.688597",\
+ "0.826825, 1.093549, 1.367337, 1.834647, 2.770253",\
+ "1.097274, 1.363997, 1.637786, 2.105095, 3.040701",\
+ "1.983909, 2.250632, 2.524419, 2.991725, 3.927326",\
+ "1.036370, 1.338298, 1.599624, 2.064415, 2.996128",\
+ "1.074296, 1.376224, 1.637549, 2.102341, 3.034053",\
+ "1.155951, 1.457879, 1.719205, 2.183996, 3.115709",\
+ "1.426400, 1.728328, 1.989653, 2.454445, 3.386157",\
+ "2.313035, 2.614962, 2.876286, 3.341075, 4.272782");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\
+ "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\
+ "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\
+ "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\
+ "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\
+ "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.425102, 0.607534, 0.803925, 1.112984, 1.707807",\
+ "0.455957, 0.638388, 0.834779, 1.143839, 1.738662",\
+ "0.517465, 0.699897, 0.896288, 1.205346, 1.800168",\
+ "0.713355, 0.895787, 1.092178, 1.401236, 1.996057",\
+ "1.351563, 1.533995, 1.730386, 2.039446, 2.634272",\
+ "0.512517, 0.694919, 0.891418, 1.200289, 1.795161",\
+ "0.543371, 0.725774, 0.922273, 1.231144, 1.826015",\
+ "0.604879, 0.787282, 0.983781, 1.292651, 1.887522",\
+ "0.800770, 0.983173, 1.179671, 1.488541, 2.083410",\
+ "1.438978, 1.621381, 1.817879, 2.126751, 2.721625",\
+ "0.593393, 0.775256, 0.971445, 1.280318, 1.875192",\
+ "0.624248, 0.806111, 1.002299, 1.311172, 1.906047",\
+ "0.685756, 0.867619, 1.063808, 1.372680, 1.967553",\
+ "0.881646, 1.063509, 1.259698, 1.568570, 2.163442",\
+ "1.519854, 1.701717, 1.897906, 2.206779, 2.801657",\
+ "0.651039, 0.832804, 1.028988, 1.337563, 1.931840",\
+ "0.681894, 0.863659, 1.059843, 1.368417, 1.962695",\
+ "0.743402, 0.925167, 1.121351, 1.429925, 2.024201",\
+ "0.939293, 1.121058, 1.317242, 1.625815, 2.220089",\
+ "1.577501, 1.759266, 1.955450, 2.264025, 2.858304",\
+ "0.953247, 1.138029, 1.332622, 1.640577, 2.233686",\
+ "0.984102, 1.168883, 1.363477, 1.671432, 2.264541",\
+ "1.045610, 1.230392, 1.424985, 1.732940, 2.326047",\
+ "1.241500, 1.426282, 1.620876, 1.928830, 2.521936",\
+ "1.879708, 2.064490, 2.259084, 2.567039, 3.160151");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\
+ "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\
+ "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\
+ "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\
+ "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718751");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2673*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.464262, 0.723892, 0.995764, 1.452644, 2.366404",\
+ "0.502188, 0.761817, 1.033690, 1.490570, 2.404330",\
+ "0.583843, 0.843473, 1.115345, 1.572225, 2.485985",\
+ "0.854292, 1.113922, 1.385794, 1.842674, 2.756433",\
+ "1.740928, 2.000556, 2.272425, 2.729303, 3.643060",\
+ "0.552367, 0.811425, 1.083295, 1.539359, 2.452338",\
+ "0.590293, 0.849351, 1.121220, 1.577285, 2.490263",\
+ "0.671948, 0.931006, 1.202876, 1.658941, 2.571919",\
+ "0.942397, 1.201455, 1.473325, 1.929389, 2.842367",\
+ "1.829032, 2.088089, 2.359956, 2.816019, 3.728994",\
+ "0.640397, 0.900391, 1.171259, 1.626982, 2.539293",\
+ "0.678323, 0.938317, 1.209185, 1.664908, 2.577219",\
+ "0.759978, 1.019972, 1.290840, 1.746563, 2.658874",\
+ "1.030427, 1.290421, 1.561289, 2.017012, 2.929322",\
+ "1.917063, 2.177055, 2.447920, 2.903641, 3.815949",\
+ "0.702618, 0.966004, 1.235397, 1.690896, 2.602802",\
+ "0.740544, 1.003930, 1.273322, 1.728822, 2.640728",\
+ "0.822200, 1.085586, 1.354978, 1.810477, 2.722383",\
+ "1.092649, 1.356035, 1.625427, 2.080925, 2.992831",\
+ "1.979284, 2.242668, 2.512058, 2.967555, 3.879458",\
+ "1.030006, 1.330079, 1.587144, 2.040197, 2.948258",\
+ "1.067932, 1.368005, 1.625070, 2.078122, 2.986184",\
+ "1.149587, 1.449661, 1.706725, 2.159778, 3.067839",\
+ "1.420036, 1.720109, 1.977174, 2.430226, 3.338287",\
+ "2.306671, 2.606743, 2.863805, 3.316856, 4.224914");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\
+ "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\
+ "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\
+ "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\
+ "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\
+ "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468304");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.423440, 0.605981, 0.802235, 1.111459, 1.706773",\
+ "0.454295, 0.636836, 0.833090, 1.142314, 1.737628",\
+ "0.515803, 0.698344, 0.894598, 1.203821, 1.799134",\
+ "0.711694, 0.894235, 1.090489, 1.399711, 1.995022",\
+ "1.349902, 1.532443, 1.728697, 2.037921, 2.633238",\
+ "0.510860, 0.693367, 0.889728, 1.198764, 1.794126",\
+ "0.541715, 0.724221, 0.920583, 1.229619, 1.824981",\
+ "0.603223, 0.785730, 0.982091, 1.291126, 1.886487",\
+ "0.799114, 0.981620, 1.177981, 1.487016, 2.082375",\
+ "1.437322, 1.619828, 1.816189, 2.125226, 2.720591",\
+ "0.591728, 0.773704, 0.969755, 1.278793, 1.874158",\
+ "0.622583, 0.804558, 1.000610, 1.309647, 1.905013",\
+ "0.684091, 0.866066, 1.062118, 1.371155, 1.966519",\
+ "0.879981, 1.061957, 1.258008, 1.567045, 2.162407",\
+ "1.518189, 1.700165, 1.896216, 2.205255, 2.800623",\
+ "0.649367, 0.831252, 1.027299, 1.336038, 1.930805",\
+ "0.680222, 0.862107, 1.058154, 1.366893, 1.961660",\
+ "0.741730, 0.923615, 1.119662, 1.428400, 2.023166",\
+ "0.937620, 1.119505, 1.315552, 1.624290, 2.219054",\
+ "1.575828, 1.757713, 1.953760, 2.262500, 2.857270",\
+ "0.951462, 1.136478, 1.330933, 1.639053, 2.232652",\
+ "0.982317, 1.167333, 1.361788, 1.669907, 2.263507",\
+ "1.043825, 1.228841, 1.423296, 1.731415, 2.325013",\
+ "1.239715, 1.424732, 1.619186, 1.927305, 2.520901",\
+ "1.877923, 2.062940, 2.257394, 2.565515, 3.159117");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\
+ "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\
+ "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\
+ "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\
+ "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\
+ "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\
+ "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\
+ "1.718736, 1.718736, 1.718736, 1.718741, 1.718753");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2611*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.556546, 0.734973, 0.915233, 1.201439, 1.752556",\
+ "0.594472, 0.772898, 0.953159, 1.239365, 1.790482",\
+ "0.676127, 0.854554, 1.034814, 1.321021, 1.872138",\
+ "0.946576, 1.125003, 1.305263, 1.591470, 2.142586",\
+ "1.833212, 2.011638, 2.191898, 2.478105, 3.029221",\
+ "0.641484, 0.820245, 1.001148, 1.287360, 1.838935",\
+ "0.679410, 0.858171, 1.039074, 1.325286, 1.876861",\
+ "0.761066, 0.939826, 1.120729, 1.406941, 1.958516",\
+ "1.031515, 1.210275, 1.391178, 1.677390, 2.228965",\
+ "1.918150, 2.096910, 2.277814, 2.564025, 3.115599",\
+ "0.717390, 0.895688, 1.075957, 1.361957, 1.913107",\
+ "0.755316, 0.933614, 1.113883, 1.399882, 1.951033",\
+ "0.836972, 1.015270, 1.195538, 1.481538, 2.032688",\
+ "1.107421, 1.285719, 1.465987, 1.751987, 2.303137",\
+ "1.994056, 2.172354, 2.352623, 2.638622, 3.189771",\
+ "0.771742, 0.950200, 1.130608, 1.416496, 1.967424",\
+ "0.809668, 0.988126, 1.168534, 1.454422, 2.005350",\
+ "0.891324, 1.069781, 1.250189, 1.536077, 2.087006",\
+ "1.161773, 1.340230, 1.520638, 1.806526, 2.357455",\
+ "2.048408, 2.226866, 2.407274, 2.693161, 3.244089",\
+ "1.053164, 1.235427, 1.414559, 1.700223, 2.250702",\
+ "1.091090, 1.273353, 1.452485, 1.738148, 2.288628",\
+ "1.172746, 1.355009, 1.534140, 1.819804, 2.370283",\
+ "1.443195, 1.625458, 1.804589, 2.090253, 2.640732",\
+ "2.329830, 2.512093, 2.691224, 2.976888, 3.527366");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\
+ "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\
+ "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\
+ "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\
+ "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\
+ "2.468303, 2.468303, 2.468303, 2.468303, 2.468303");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.440713, 0.705883, 0.965084, 1.401266, 2.273631",\
+ "0.471568, 0.736737, 0.995939, 1.432121, 2.304486",\
+ "0.533076, 0.798245, 1.057447, 1.493629, 2.365994",\
+ "0.728966, 0.994136, 1.253338, 1.689520, 2.561884",\
+ "1.367174, 1.632344, 1.891546, 2.327728, 3.200092",\
+ "0.529378, 0.793957, 1.053725, 1.489495, 2.361036",\
+ "0.560233, 0.824812, 1.084580, 1.520350, 2.391891",\
+ "0.621741, 0.886320, 1.146088, 1.581858, 2.453399",\
+ "0.817632, 1.082211, 1.341978, 1.777749, 2.649290",\
+ "1.455840, 1.720419, 1.980186, 2.415956, 3.287497",\
+ "0.622185, 0.887080, 1.145450, 1.581659, 2.454078",\
+ "0.653040, 0.917935, 1.176305, 1.612514, 2.484932",\
+ "0.714548, 0.979443, 1.237813, 1.674022, 2.546441",\
+ "0.910438, 1.175334, 1.433704, 1.869913, 2.742332",\
+ "1.548646, 1.813542, 2.071912, 2.508121, 3.380539",\
+ "0.687908, 0.955615, 1.212470, 1.648510, 2.520589",\
+ "0.718762, 0.986469, 1.243325, 1.679364, 2.551444",\
+ "0.780270, 1.047977, 1.304833, 1.740873, 2.612952",\
+ "0.976161, 1.243868, 1.500724, 1.936763, 2.808843",\
+ "1.614369, 1.882076, 2.138932, 2.574971, 3.447050",\
+ "1.033697, 1.336113, 1.583101, 2.017641, 2.886722",\
+ "1.064552, 1.366968, 1.613955, 2.048496, 2.917577",\
+ "1.126060, 1.428476, 1.675463, 2.110004, 2.979085",\
+ "1.321950, 1.624366, 1.871354, 2.305894, 3.174975",\
+ "1.960158, 2.262574, 2.509562, 2.944102, 3.813183");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\
+ "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\
+ "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\
+ "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\
+ "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\
+ "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\
+ "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\
+ "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\
+ "1.718736, 1.718736, 1.718736, 1.718736, 1.718736");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2557*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "380001.875000, 380001.906250, 380002.000000, 380002.250000, 380003.156250",\
+ "380001.968750, 380002.000000, 380002.093750, 380002.343750, 380003.250000",\
+ "380002.031250, 380002.062500, 380002.156250, 380002.406250, 380003.312500",\
+ "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\
+ "380002.406250, 380002.437500, 380002.531250, 380002.781250, 380003.687500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.060312, 0.120043, 0.268889, 0.790048, 2.471058",\
+ "0.060312, 0.120043, 0.268889, 0.790048, 2.471058",\
+ "0.060312, 0.120043, 0.268889, 0.790048, 2.471058",\
+ "0.060311, 0.120043, 0.268889, 0.790048, 2.471058",\
+ "0.060311, 0.120043, 0.268889, 0.790048, 2.468313");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "380003.906250, 380003.937500, 380004.000000, 380004.187500, 380004.843750",\
+ "380004.000000, 380004.031250, 380004.093750, 380004.281250, 380004.937500",\
+ "380004.093750, 380004.125000, 380004.187500, 380004.375000, 380005.031250",\
+ "380004.156250, 380004.187500, 380004.250000, 380004.437500, 380005.093750",\
+ "380004.500000, 380004.531250, 380004.593750, 380004.781250, 380005.437500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\
+ "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\
+ "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\
+ "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\
+ "0.050984, 0.092651, 0.193203, 0.549286, 1.721959");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.544292, 0.724406, 0.911984, 1.213964, 1.797060",\
+ "0.582447, 0.762561, 0.950139, 1.252119, 1.835215",\
+ "0.664874, 0.844988, 1.032566, 1.334546, 1.917642",\
+ "0.936033, 1.116146, 1.303725, 1.605704, 2.188801",\
+ "1.821919, 2.002032, 2.189611, 2.491591, 3.074687",\
+ "0.629231, 0.809242, 0.997054, 1.299470, 1.883439",\
+ "0.667386, 0.847397, 1.035209, 1.337625, 1.921593",\
+ "0.749812, 0.929824, 1.117636, 1.420052, 2.004020",\
+ "1.020971, 1.200982, 1.388795, 1.691211, 2.275179",\
+ "1.906857, 2.086868, 2.274681, 2.577097, 3.161065",\
+ "0.705143, 0.884685, 1.071863, 1.374067, 1.957611",\
+ "0.743298, 0.922840, 1.110018, 1.412222, 1.995766",\
+ "0.825724, 1.005267, 1.192445, 1.494649, 2.078193",\
+ "1.096883, 1.276425, 1.463604, 1.765808, 2.349351",\
+ "1.982769, 2.162312, 2.349490, 2.651694, 3.235237",\
+ "0.759512, 0.939436, 1.126752, 1.428673, 2.011928",\
+ "0.797667, 0.977591, 1.164907, 1.466828, 2.050083",\
+ "0.880094, 1.060018, 1.247334, 1.549255, 2.132510",\
+ "1.151252, 1.331177, 1.518492, 1.820413, 2.403668",\
+ "2.037138, 2.217063, 2.404379, 2.706299, 3.289555",\
+ "1.041107, 1.225001, 1.410928, 1.712399, 2.295206",\
+ "1.079262, 1.263156, 1.449083, 1.750554, 2.333361",\
+ "1.161688, 1.345583, 1.531509, 1.832981, 2.415788",\
+ "1.432847, 1.616742, 1.802668, 2.104139, 2.686946",\
+ "2.318733, 2.502628, 2.688554, 2.990026, 3.572832");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\
+ "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\
+ "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\
+ "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\
+ "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446672");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.363069, 0.630679, 0.892080, 1.331857, 2.211017",\
+ "0.391013, 0.658624, 0.920025, 1.359801, 2.238962",\
+ "0.450465, 0.718075, 0.979476, 1.419253, 2.298413",\
+ "0.646065, 0.913676, 1.175077, 1.614853, 2.494013",\
+ "1.283402, 1.551012, 1.812413, 2.252190, 3.131351",\
+ "0.451773, 0.718754, 0.980721, 1.420086, 2.298422",\
+ "0.479717, 0.746699, 1.008666, 1.448030, 2.326367",\
+ "0.539169, 0.806150, 1.068117, 1.507482, 2.385818",\
+ "0.734769, 1.001751, 1.263718, 1.703082, 2.581419",\
+ "1.372106, 1.639087, 1.901054, 2.340420, 3.218756",\
+ "0.544715, 0.812075, 1.072766, 1.512332, 2.391464",\
+ "0.572660, 0.840019, 1.100710, 1.540276, 2.419409",\
+ "0.632111, 0.899470, 1.160161, 1.599728, 2.478860",\
+ "0.827712, 1.095071, 1.355762, 1.795328, 2.674460",\
+ "1.465048, 1.732408, 1.993099, 2.432665, 3.311798",\
+ "0.610559, 0.880639, 1.139822, 1.579343, 2.458386",\
+ "0.638503, 0.908583, 1.167766, 1.607288, 2.486331",\
+ "0.697955, 0.968035, 1.227218, 1.666739, 2.545782",\
+ "0.893555, 1.163635, 1.422818, 1.862339, 2.741382",\
+ "1.530892, 1.800972, 2.060155, 2.499676, 3.378720",\
+ "0.957080, 1.261474, 1.510493, 1.948569, 2.824721",\
+ "0.985025, 1.289419, 1.538437, 1.976513, 2.852666",\
+ "1.044476, 1.348870, 1.597888, 2.035964, 2.912117",\
+ "1.240077, 1.544471, 1.793489, 2.231565, 3.107717",\
+ "1.877413, 2.181808, 2.430826, 2.868902, 3.745055");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\
+ "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\
+ "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\
+ "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\
+ "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2500*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.452401, 0.715932, 0.992051, 1.460182, 2.395185",\
+ "0.490556, 0.754087, 1.030206, 1.498337, 2.433340",\
+ "0.572982, 0.836514, 1.112633, 1.580764, 2.515767",\
+ "0.844141, 1.107672, 1.383791, 1.851923, 2.786925",\
+ "1.730027, 1.993558, 2.269678, 2.737809, 3.672812",\
+ "0.540595, 0.803472, 1.079618, 1.546898, 2.481119",\
+ "0.578750, 0.841627, 1.117773, 1.585052, 2.519274",\
+ "0.661177, 0.924054, 1.200200, 1.667479, 2.601700",\
+ "0.932335, 1.195213, 1.471358, 1.938638, 2.872859",\
+ "1.818222, 2.081099, 2.357244, 2.824524, 3.758746",\
+ "0.628911, 0.892452, 1.167583, 1.634538, 2.568074",\
+ "0.667066, 0.930607, 1.205738, 1.672693, 2.606229",\
+ "0.749493, 1.013034, 1.288164, 1.755120, 2.688655",\
+ "1.020651, 1.284192, 1.559323, 2.026278, 2.959814",\
+ "1.906538, 2.170078, 2.445210, 2.912164, 3.845701",\
+ "0.691407, 0.958086, 1.231722, 1.698627, 2.631583",\
+ "0.729562, 0.996240, 1.269877, 1.736781, 2.669738",\
+ "0.811989, 1.078667, 1.352304, 1.819208, 2.752164",\
+ "1.083147, 1.349826, 1.623463, 2.090367, 3.023323",\
+ "1.969034, 2.235712, 2.509349, 2.976254, 3.909210",\
+ "1.020533, 1.322400, 1.583586, 2.048070, 2.977039",\
+ "1.058688, 1.360555, 1.621741, 2.086226, 3.015194",\
+ "1.141114, 1.442982, 1.704168, 2.168652, 3.097620",\
+ "1.412273, 1.714141, 1.975327, 2.439811, 3.368779",\
+ "2.298159, 2.600027, 2.861213, 3.325697, 4.254666");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\
+ "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\
+ "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\
+ "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\
+ "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446670, 2.446673, 2.446677, 2.446682, 2.446693");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.346024, 0.528081, 0.724314, 1.033489, 1.627960",\
+ "0.373968, 0.556026, 0.752258, 1.061434, 1.655906",\
+ "0.433420, 0.615477, 0.811710, 1.120886, 1.715360",\
+ "0.629020, 0.811078, 1.007310, 1.316483, 1.910951",\
+ "1.266357, 1.448414, 1.644648, 1.953829, 2.548313",\
+ "0.433439, 0.615400, 0.811595, 1.120794, 1.715314",\
+ "0.461383, 0.643345, 0.839539, 1.148739, 1.743259",\
+ "0.520834, 0.702796, 0.898991, 1.208191, 1.802713",\
+ "0.716435, 0.898396, 1.094591, 1.403789, 1.998304",\
+ "1.353772, 1.535733, 1.731929, 2.041134, 2.635666",\
+ "0.514315, 0.695737, 0.891622, 1.200823, 1.795345",\
+ "0.542259, 0.723681, 0.919566, 1.228768, 1.823291",\
+ "0.601711, 0.783132, 0.979018, 1.288220, 1.882745",\
+ "0.797311, 0.978733, 1.174618, 1.483817, 2.078336",\
+ "1.434648, 1.616070, 1.811956, 2.121162, 2.715698",\
+ "0.571961, 0.753573, 0.949357, 1.258293, 1.852441",\
+ "0.599906, 0.781518, 0.977302, 1.286238, 1.880386",\
+ "0.659357, 0.840969, 1.036753, 1.345690, 1.939840",\
+ "0.854958, 1.036570, 1.232353, 1.541288, 2.135431",\
+ "1.492294, 1.673906, 1.869692, 2.178633, 2.772793",\
+ "0.874169, 1.058951, 1.253021, 1.561500, 2.154759",\
+ "0.902114, 1.086895, 1.280965, 1.589445, 2.182705",\
+ "0.961565, 1.146346, 1.340417, 1.648897, 2.242158",\
+ "1.157166, 1.341947, 1.536017, 1.844495, 2.437749",\
+ "1.794502, 1.979284, 2.173355, 2.481840, 3.075111");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\
+ "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\
+ "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\
+ "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\
+ "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\
+ "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\
+ "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\
+ "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\
+ "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\
+ "1.713838, 1.713838, 1.713836, 1.713827, 1.713805");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2425*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.448423, 0.707982, 0.979616, 1.435777, 2.346942",\
+ "0.486578, 0.746137, 1.017771, 1.473932, 2.385097",\
+ "0.569004, 0.828563, 1.100198, 1.556358, 2.467524",\
+ "0.840163, 1.099722, 1.371357, 1.827517, 2.738683",\
+ "1.726049, 1.985608, 2.257243, 2.713404, 3.624570",\
+ "0.536527, 0.795515, 1.067145, 1.522492, 2.432876",\
+ "0.574682, 0.833670, 1.105300, 1.560647, 2.471031",\
+ "0.657109, 0.916096, 1.187727, 1.643074, 2.553458",\
+ "0.928268, 1.187255, 1.458886, 1.914232, 2.824616",\
+ "1.814154, 2.073141, 2.344772, 2.800119, 3.710504",\
+ "0.624558, 0.884479, 1.155110, 1.610131, 2.519831",\
+ "0.662712, 0.922634, 1.193264, 1.648286, 2.557986",\
+ "0.745139, 1.005061, 1.275691, 1.730713, 2.640413",\
+ "1.016298, 1.276219, 1.546850, 2.001871, 2.911571",\
+ "1.902184, 2.162105, 2.432736, 2.887758, 3.797459",\
+ "0.686779, 0.950090, 1.219247, 1.674205, 2.583340",\
+ "0.724934, 0.988245, 1.257402, 1.712360, 2.621495",\
+ "0.807361, 1.070672, 1.339829, 1.794787, 2.703922",\
+ "1.078519, 1.341830, 1.610988, 2.065946, 2.975080",\
+ "1.964405, 2.227717, 2.496874, 2.951832, 3.860968",\
+ "1.014166, 1.314139, 1.570990, 2.023592, 2.928796",\
+ "1.052321, 1.352293, 1.609145, 2.061747, 2.966951",\
+ "1.134748, 1.434720, 1.691572, 2.144174, 3.049378",\
+ "1.405907, 1.705879, 1.962730, 2.415332, 3.320536",\
+ "2.291793, 2.591765, 2.848617, 3.301219, 4.206424");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\
+ "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\
+ "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\
+ "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\
+ "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446675, 2.446680, 2.446683, 2.446690");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.344360, 0.526527, 0.722625, 1.031957, 1.626903",\
+ "0.372305, 0.554472, 0.750569, 1.059901, 1.654848",\
+ "0.431756, 0.613923, 0.810021, 1.119354, 1.714302",\
+ "0.627357, 0.809524, 1.005621, 1.314951, 1.909892",\
+ "1.264693, 1.446861, 1.642959, 1.952297, 2.547257",\
+ "0.431780, 0.613846, 0.809906, 1.119262, 1.714256",\
+ "0.459725, 0.641791, 0.837850, 1.147207, 1.742202",\
+ "0.519176, 0.701242, 0.897302, 1.206659, 1.801656",\
+ "0.714777, 0.896843, 1.092902, 1.402256, 1.997246",\
+ "1.352113, 1.534179, 1.730240, 2.039602, 2.634611",\
+ "0.512648, 0.694183, 0.889933, 1.199290, 1.794288",\
+ "0.540592, 0.722128, 0.917877, 1.227235, 1.822234",\
+ "0.600044, 0.781579, 0.977328, 1.286687, 1.881687",\
+ "0.795644, 0.977180, 1.172929, 1.482284, 2.077278",\
+ "1.432981, 1.614516, 1.810267, 2.119630, 2.714642",\
+ "0.570287, 0.752020, 0.947668, 1.256761, 1.851384",\
+ "0.598231, 0.779964, 0.975612, 1.284706, 1.879330",\
+ "0.657682, 0.839416, 1.035064, 1.344158, 1.938784",\
+ "0.853283, 1.035016, 1.230664, 1.539755, 2.134374",\
+ "1.490620, 1.672353, 1.868002, 2.177101, 2.771739",\
+ "0.872382, 1.057398, 1.251331, 1.559969, 2.153704",\
+ "0.900326, 1.085343, 1.279276, 1.587914, 2.181649",\
+ "0.959778, 1.144794, 1.338727, 1.647366, 2.241103",\
+ "1.155378, 1.340395, 1.534328, 1.842963, 2.436693",\
+ "1.792715, 1.977731, 2.171666, 2.480309, 3.074058");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\
+ "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\
+ "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\
+ "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\
+ "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\
+ "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\
+ "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\
+ "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\
+ "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\
+ "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\
+ "1.713838, 1.713838, 1.713836, 1.713826, 1.713802");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2354*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.540706, 0.719045, 0.899392, 1.185579, 1.736332",\
+ "0.578861, 0.757200, 0.937547, 1.223734, 1.774487",\
+ "0.661288, 0.839627, 1.019974, 1.306160, 1.856914",\
+ "0.932446, 1.110786, 1.291132, 1.577319, 2.128072",\
+ "1.818332, 1.996672, 2.177019, 2.463205, 3.013958",\
+ "0.625644, 0.803881, 0.984462, 1.271085, 1.822710",\
+ "0.663799, 0.842036, 1.022617, 1.309240, 1.860865",\
+ "0.746226, 0.924463, 1.105044, 1.391667, 1.943292",\
+ "1.017385, 1.195621, 1.376203, 1.662825, 2.214450",\
+ "1.903271, 2.081508, 2.262089, 2.548712, 3.100337",\
+ "0.701550, 0.879325, 1.059271, 1.345682, 1.896883",\
+ "0.739705, 0.917479, 1.097426, 1.383837, 1.935037",\
+ "0.822132, 0.999906, 1.179853, 1.466263, 2.017464",\
+ "1.093291, 1.271065, 1.451011, 1.737422, 2.288623",\
+ "1.979177, 2.156951, 2.336898, 2.623308, 3.174509",\
+ "0.755902, 0.934070, 1.114136, 1.400275, 1.951200",\
+ "0.794057, 0.972225, 1.152291, 1.438430, 1.989355",\
+ "0.876484, 1.054652, 1.234718, 1.520857, 2.071782",\
+ "1.147643, 1.325810, 1.505877, 1.792016, 2.342940",\
+ "2.033529, 2.211697, 2.391763, 2.677902, 3.228827",\
+ "1.037324, 1.219587, 1.398289, 1.684002, 2.234478",\
+ "1.075479, 1.257742, 1.436444, 1.722157, 2.272632",\
+ "1.157906, 1.340169, 1.518871, 1.804583, 2.355059",\
+ "1.429065, 1.611328, 1.790030, 2.075742, 2.626218",\
+ "2.314951, 2.497214, 2.675916, 2.961628, 3.512104");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\
+ "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\
+ "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\
+ "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\
+ "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\
+ "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\
+ "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\
+ "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\
+ "2.446671, 2.446671, 2.446671, 2.446671, 2.446673");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.361633, 0.626632, 0.885661, 1.321925, 2.194071",\
+ "0.389577, 0.654577, 0.913606, 1.349870, 2.222015",\
+ "0.449029, 0.714028, 0.973057, 1.409321, 2.281467",\
+ "0.644629, 0.909628, 1.168658, 1.604922, 2.477067",\
+ "1.281966, 1.546965, 1.805995, 2.242259, 3.114405",\
+ "0.450298, 0.714707, 0.974302, 1.410154, 2.281476",\
+ "0.478243, 0.742651, 1.002247, 1.438099, 2.309421",\
+ "0.537694, 0.802103, 1.061698, 1.497550, 2.368872",\
+ "0.733295, 0.997703, 1.257299, 1.693150, 2.564472",\
+ "1.370631, 1.635040, 1.894635, 2.330488, 3.201810",\
+ "0.543105, 0.808000, 1.066338, 1.502398, 2.374518",\
+ "0.571050, 0.835945, 1.094282, 1.530342, 2.402462",\
+ "0.630501, 0.895396, 1.153733, 1.589793, 2.461914",\
+ "0.826102, 1.090997, 1.349334, 1.785394, 2.657514",\
+ "1.463438, 1.728334, 1.986671, 2.422731, 3.294852",\
+ "0.608828, 0.876535, 1.133393, 1.569404, 2.441428",\
+ "0.636772, 0.904479, 1.161337, 1.597349, 2.469372",\
+ "0.696223, 0.963930, 1.220788, 1.656800, 2.528824",\
+ "0.891824, 1.159531, 1.416389, 1.852400, 2.724424",\
+ "1.529161, 1.796868, 2.053726, 2.489738, 3.361762",\
+ "0.954617, 1.257033, 1.504031, 1.938605, 2.807755",\
+ "0.982561, 1.284978, 1.531975, 1.966550, 2.835699",\
+ "1.042013, 1.344429, 1.591426, 2.026001, 2.895151",\
+ "1.237613, 1.540030, 1.787027, 2.221601, 3.090751",\
+ "1.874950, 2.177366, 2.424364, 2.858939, 3.728089");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\
+ "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\
+ "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\
+ "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\
+ "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\
+ "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\
+ "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\
+ "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\
+ "1.713838, 1.713838, 1.713838, 1.713837, 1.713836");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2300*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.138985, 0.175019, 0.256111, 0.526543, 1.410212",\
+ "0.227168, 0.263197, 0.344286, 0.614601, 1.498111",\
+ "0.315465, 0.351510, 0.432605, 0.702794, 1.585954",\
+ "0.378070, 0.414099, 0.495228, 0.765687, 1.648712",\
+ "0.707467, 0.743520, 0.824710, 1.095700, 1.978611");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.049671, 0.111941, 0.264026, 0.776079, 2.446670",\
+ "0.049671, 0.111941, 0.264026, 0.776079, 2.446670",\
+ "0.049671, 0.111941, 0.264026, 0.776079, 2.446670",\
+ "0.049683, 0.111941, 0.264026, 0.776079, 2.446670",\
+ "0.050112, 0.112175, 0.264026, 0.776079, 2.446670");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.157324, 0.185053, 0.244293, 0.439369, 1.077476",\
+ "0.244729, 0.272457, 0.331698, 0.526774, 1.164879",\
+ "0.325583, 0.353311, 0.412545, 0.607616, 1.245783",\
+ "0.383167, 0.410894, 0.470117, 0.665176, 1.303456",\
+ "0.684927, 0.712665, 0.771862, 0.966921, 1.606322");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.040467, 0.082696, 0.186546, 0.543770, 1.713948",\
+ "0.040467, 0.082696, 0.186546, 0.543770, 1.713948",\
+ "0.040467, 0.082696, 0.186546, 0.543770, 1.713916",\
+ "0.040467, 0.082696, 0.186546, 0.543770, 1.713853",\
+ "0.040452, 0.082696, 0.186546, 0.543770, 1.713838");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "380001.750000, 380001.781250, 380001.875000, 380002.125000, 380003.031250",\
+ "380001.843750, 380001.875000, 380001.968750, 380002.218750, 380003.125000",\
+ "380001.937500, 380001.968750, 380002.062500, 380002.312500, 380003.218750",\
+ "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\
+ "380002.343750, 380002.375000, 380002.468750, 380002.718750, 380003.625000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\
+ "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\
+ "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\
+ "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\
+ "0.060263, 0.120010, 0.268885, 0.784134, 2.468360");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "380003.812500, 380003.843750, 380003.906250, 380004.093750, 380004.750000",\
+ "380003.906250, 380003.937500, 380004.000000, 380004.187500, 380004.843750",\
+ "380004.031250, 380004.062500, 380004.125000, 380004.312500, 380004.968750",\
+ "380004.218750, 380004.250000, 380004.312500, 380004.500000, 380005.156250",\
+ "380004.531250, 380004.562500, 380004.625000, 380004.812500, 380005.468750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\
+ "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\
+ "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\
+ "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\
+ "0.050461, 0.092299, 0.192599, 0.548730, 1.719198");
+ }
+
+ } /* end of arc padmux2ast_i[4]_obs_ctrl_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "380001.718750, 380001.781250, 380001.843750, 380002.125000, 380003.000000",\
+ "380001.812500, 380001.875000, 380001.937500, 380002.218750, 380003.093750",\
+ "380001.875000, 380001.937500, 380002.000000, 380002.281250, 380003.156250",\
+ "380002.031250, 380002.093750, 380002.156250, 380002.437500, 380003.312500",\
+ "380002.250000, 380002.312500, 380002.375000, 380002.656250, 380003.531250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\
+ "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\
+ "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\
+ "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\
+ "0.057179, 0.117947, 0.268265, 0.782312, 2.467599");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "380003.781250, 380003.812500, 380003.875000, 380004.062500, 380004.718750",\
+ "380003.875000, 380003.906250, 380003.968750, 380004.156250, 380004.812500",\
+ "380003.968750, 380004.000000, 380004.062500, 380004.250000, 380004.906250",\
+ "380004.156250, 380004.187500, 380004.250000, 380004.437500, 380005.093750",\
+ "380004.406250, 380004.437500, 380004.500000, 380004.687500, 380005.343750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\
+ "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\
+ "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\
+ "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\
+ "0.044680, 0.086652, 0.188447, 0.546028, 1.713947");
+ }
+
+ } /* end of arc padmux2ast_i[4]_obs_ctrl_o[7]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[7]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.138119, 0.177193, 0.260095, 0.531430, 1.418639",\
+ "0.215767, 0.254860, 0.337696, 0.608981, 1.495289",\
+ "0.308294, 0.348212, 0.431364, 0.702849, 1.589224",\
+ "0.484710, 0.527128, 0.611576, 0.883003, 1.767226",\
+ "0.797982, 0.847958, 0.937201, 1.208546, 2.091260");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.060518, 0.120076, 0.268511, 0.784628, 2.471116",\
+ "0.060518, 0.120081, 0.268991, 0.784628, 2.471116",\
+ "0.064343, 0.122204, 0.269307, 0.784628, 2.471116",\
+ "0.074832, 0.129870, 0.272085, 0.785309, 2.471116",\
+ "0.105095, 0.152930, 0.282207, 0.790964, 2.471949");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.152585, 0.183883, 0.246071, 0.443151, 1.081549",\
+ "0.241411, 0.272612, 0.334887, 0.531878, 1.170082",\
+ "0.351515, 0.383367, 0.445997, 0.642143, 1.279910",\
+ "0.559588, 0.595140, 0.660416, 0.857529, 1.494932",\
+ "0.931509, 0.975339, 1.048816, 1.248062, 1.886353");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.051005, 0.093001, 0.193536, 0.550167, 1.721145",\
+ "0.051005, 0.093079, 0.193536, 0.550167, 1.721145",\
+ "0.053874, 0.094487, 0.193931, 0.550167, 1.721145",\
+ "0.067061, 0.106340, 0.200874, 0.550167, 1.721145",\
+ "0.100525, 0.137944, 0.221526, 0.555674, 1.721145");
+ }
+
+ } /* end of arc padmux2ast_i[7]_obs_ctrl_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[7]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.132088, 0.170250, 0.252738, 0.523558, 1.410267",\
+ "0.209647, 0.247859, 0.330344, 0.601532, 1.487547",\
+ "0.301602, 0.340448, 0.423118, 0.694391, 1.578063",\
+ "0.475914, 0.516815, 0.600289, 0.871567, 1.757498",\
+ "0.784086, 0.831711, 0.918475, 1.188577, 2.072675");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.057008, 0.117873, 0.266652, 0.780708, 2.463387",\
+ "0.057108, 0.118176, 0.268442, 0.782366, 2.463387",\
+ "0.060610, 0.120100, 0.268442, 0.782366, 2.463387",\
+ "0.069995, 0.126826, 0.271258, 0.783468, 2.466000",\
+ "0.096521, 0.148240, 0.280183, 0.788214, 2.471217");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.124161, 0.153974, 0.214961, 0.411830, 1.047717",\
+ "0.215312, 0.245079, 0.306058, 0.501475, 1.140252",\
+ "0.327970, 0.358765, 0.420242, 0.616480, 1.254494",\
+ "0.533590, 0.569301, 0.634108, 0.830328, 1.467817",\
+ "0.890972, 0.936721, 1.011690, 1.210135, 1.847934");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370");
+ values ( "0.045487, 0.087234, 0.188597, 0.544901, 1.712083",\
+ "0.045487, 0.087327, 0.189348, 0.546097, 1.714089",\
+ "0.050060, 0.090091, 0.189686, 0.546097, 1.714380",\
+ "0.065339, 0.103967, 0.197580, 0.546097, 1.714380",\
+ "0.095856, 0.132931, 0.220241, 0.552890, 1.714380");
+ }
+
+ } /* end of arc padmux2ast_i[7]_obs_ctrl_o[7]_una_min*/
+
+} /* end of pin obs_ctrl_o[7] */
+
+pin("obs_ctrl_o[6]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.156168 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000997 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[6];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.556254, 0.736457, 0.923947, 1.225939, 1.809451",\
+ "0.586838, 0.767041, 0.954531, 1.256524, 1.840036",\
+ "0.658665, 0.838868, 1.026358, 1.328351, 1.911863",\
+ "0.915124, 1.095327, 1.282817, 1.584810, 2.168322",\
+ "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\
+ "0.641192, 0.821740, 1.009955, 1.311951, 1.895829",\
+ "0.671777, 0.852324, 1.040540, 1.342536, 1.926414",\
+ "0.743604, 0.924151, 1.112367, 1.414363, 1.998241",\
+ "1.000063, 1.180610, 1.368826, 1.670822, 2.254700",\
+ "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\
+ "0.717104, 0.897183, 1.084764, 1.386548, 1.970002",\
+ "0.747689, 0.927768, 1.115349, 1.417133, 2.000586",\
+ "0.819516, 0.999595, 1.187176, 1.488960, 2.072413",\
+ "1.075975, 1.256054, 1.443635, 1.745419, 2.328872",\
+ "1.991743, 2.171822, 2.359403, 2.661187, 3.244641",\
+ "0.771473, 0.951695, 1.139415, 1.441088, 2.024319",\
+ "0.802058, 0.982279, 1.170000, 1.471673, 2.054904",\
+ "0.873885, 1.054106, 1.241827, 1.543499, 2.126730",\
+ "1.130344, 1.310565, 1.498286, 1.799959, 2.383190",\
+ "2.046112, 2.226333, 2.414054, 2.715727, 3.298958",\
+ "1.053068, 1.236963, 1.423366, 1.724814, 2.307597",\
+ "1.083653, 1.267547, 1.453950, 1.755399, 2.338181",\
+ "1.155480, 1.339374, 1.525777, 1.827226, 2.410008",\
+ "1.411939, 1.595834, 1.782236, 2.083685, 2.666467",\
+ "2.327707, 2.511601, 2.698004, 2.999453, 3.582235");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.426883, 0.694669, 0.956249, 1.395946, 2.275341",\
+ "0.452678, 0.720463, 0.982044, 1.421741, 2.301136",\
+ "0.504089, 0.771875, 1.033455, 1.473152, 2.352547",\
+ "0.670899, 0.938685, 1.200265, 1.639962, 2.519357",\
+ "1.261153, 1.528939, 1.790519, 2.230216, 3.109611",\
+ "0.515587, 0.782744, 1.044890, 1.484175, 2.362746",\
+ "0.541382, 0.808538, 1.070684, 1.509970, 2.388541",\
+ "0.592793, 0.859950, 1.122096, 1.561381, 2.439952",\
+ "0.759603, 1.026760, 1.288906, 1.728191, 2.606762",\
+ "1.349858, 1.617014, 1.879160, 2.318445, 3.197016",\
+ "0.608530, 0.875889, 1.136616, 1.576339, 2.455788",\
+ "0.634324, 0.901683, 1.162410, 1.602134, 2.481582",\
+ "0.685735, 0.953095, 1.213821, 1.653545, 2.532994",\
+ "0.852545, 1.119905, 1.380631, 1.820355, 2.699804",\
+ "1.442800, 1.710159, 1.970885, 2.410609, 3.290058",\
+ "0.674373, 0.944453, 1.203635, 1.643190, 2.522299",\
+ "0.700168, 0.970248, 1.229430, 1.668984, 2.548094",\
+ "0.751579, 1.021659, 1.280841, 1.720395, 2.599505",\
+ "0.918389, 1.188469, 1.447651, 1.887205, 2.766315",\
+ "1.508643, 1.778723, 2.037905, 2.477460, 3.356569",\
+ "1.020895, 1.325289, 1.574298, 2.012344, 2.888435",\
+ "1.046689, 1.351083, 1.600093, 2.038138, 2.914229",\
+ "1.098100, 1.402495, 1.651504, 2.089549, 2.965641",\
+ "1.264910, 1.569304, 1.818314, 2.256359, 3.132450",\
+ "1.855165, 2.159559, 2.408568, 2.846614, 3.722705");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\
+ "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\
+ "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\
+ "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\
+ "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2739*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.464359, 0.727932, 1.004205, 1.472935, 2.410394",\
+ "0.494943, 0.758517, 1.034790, 1.503519, 2.440979",\
+ "0.566770, 0.830344, 1.106616, 1.575346, 2.512805",\
+ "0.823229, 1.086803, 1.363075, 1.831805, 2.769264",\
+ "1.738998, 2.002571, 2.278845, 2.747575, 3.685036",\
+ "0.552553, 0.815473, 1.091773, 1.559650, 2.496328",\
+ "0.583138, 0.846058, 1.122357, 1.590235, 2.526912",\
+ "0.654965, 0.917885, 1.194184, 1.662061, 2.598739",\
+ "0.911424, 1.174344, 1.450643, 1.918520, 2.855197",\
+ "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\
+ "0.640869, 0.904454, 1.179738, 1.647273, 2.583283",\
+ "0.671454, 0.935038, 1.210322, 1.677857, 2.613867",\
+ "0.743281, 1.006865, 1.282149, 1.749684, 2.685694",\
+ "0.999740, 1.263324, 1.538608, 2.006143, 2.942153",\
+ "1.915508, 2.179093, 2.454377, 2.921913, 3.857924",\
+ "0.703365, 0.970089, 1.243877, 1.711186, 2.646792",\
+ "0.733950, 1.000673, 1.274462, 1.741771, 2.677376",\
+ "0.805777, 1.072500, 1.346289, 1.813598, 2.749203",\
+ "1.062236, 1.328959, 1.602748, 2.070056, 3.005661",\
+ "1.978004, 2.244728, 2.518517, 2.985826, 3.921433",\
+ "1.032491, 1.334419, 1.595745, 2.060536, 2.992248",\
+ "1.063076, 1.365004, 1.626329, 2.091120, 3.022832",\
+ "1.134902, 1.436831, 1.698156, 2.162947, 3.094659",\
+ "1.391361, 1.693290, 1.954615, 2.419406, 3.351118",\
+ "2.307130, 2.609058, 2.870384, 3.335176, 4.266890");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\
+ "0.715483, 0.715483, 0.715482, 0.715478, 0.715471",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\
+ "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\
+ "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\
+ "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\
+ "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.409837, 0.592268, 0.788660, 1.097713, 1.692519",\
+ "0.435631, 0.618063, 0.814455, 1.123508, 1.718315",\
+ "0.487042, 0.669474, 0.865866, 1.174919, 1.769726",\
+ "0.653852, 0.836284, 1.032676, 1.341729, 1.936536",\
+ "1.244107, 1.426538, 1.622930, 1.931983, 2.526791",\
+ "0.497251, 0.679654, 0.876154, 1.185018, 1.779872",\
+ "0.523046, 0.705448, 0.901948, 1.210813, 1.805669",\
+ "0.574457, 0.756860, 0.953359, 1.262224, 1.857080",\
+ "0.741267, 0.923669, 1.120169, 1.429034, 2.023889",\
+ "1.331521, 1.513924, 1.710423, 2.019289, 2.614144",\
+ "0.578128, 0.759990, 0.956180, 1.265047, 1.859904",\
+ "0.603922, 0.785785, 0.981975, 1.290841, 1.885700",\
+ "0.655333, 0.837196, 1.033386, 1.342253, 1.937111",\
+ "0.822143, 1.004006, 1.200196, 1.509062, 2.103921",\
+ "1.412398, 1.594260, 1.790450, 2.099317, 2.694176",\
+ "0.635774, 0.817539, 1.013724, 1.322292, 1.916552",\
+ "0.661568, 0.843333, 1.039518, 1.348086, 1.942348",\
+ "0.712980, 0.894745, 1.090930, 1.399498, 1.993759",\
+ "0.879789, 1.061554, 1.257740, 1.566308, 2.160568",\
+ "1.470044, 1.651809, 1.847994, 2.156562, 2.750823",\
+ "0.937982, 1.122763, 1.317358, 1.625306, 2.218398",\
+ "0.963776, 1.148558, 1.343152, 1.651101, 2.244195",\
+ "1.015187, 1.199969, 1.394563, 1.702512, 2.295605",\
+ "1.181997, 1.366779, 1.561373, 1.869322, 2.462415",\
+ "1.772252, 1.957033, 2.151628, 2.459577, 3.052670");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\
+ "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\
+ "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\
+ "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\
+ "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523857");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2665*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.460384, 0.720013, 0.991885, 1.448765, 2.362525",\
+ "0.490968, 0.750597, 1.022470, 1.479349, 2.393109",\
+ "0.562795, 0.822424, 1.094296, 1.551176, 2.464936",\
+ "0.819254, 1.078883, 1.350755, 1.807635, 2.721394",\
+ "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\
+ "0.548488, 0.807546, 1.079415, 1.535480, 2.448458",\
+ "0.579073, 0.838131, 1.110000, 1.566065, 2.479043",\
+ "0.650900, 0.909958, 1.181827, 1.637892, 2.550869",\
+ "0.907359, 1.166417, 1.438286, 1.894350, 2.807328",\
+ "1.823127, 2.082186, 2.354055, 2.810120, 3.723099",\
+ "0.636518, 0.896512, 1.167380, 1.623103, 2.535413",\
+ "0.667103, 0.927097, 1.197964, 1.653687, 2.565998",\
+ "0.738930, 0.998924, 1.269791, 1.725514, 2.637825",\
+ "0.995389, 1.255383, 1.526250, 1.981973, 2.894283",\
+ "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\
+ "0.698740, 0.962126, 1.231518, 1.687016, 2.598922",\
+ "0.729324, 0.992710, 1.262102, 1.717601, 2.629507",\
+ "0.801151, 1.064537, 1.333929, 1.789428, 2.701334",\
+ "1.057610, 1.320996, 1.590388, 2.045887, 2.957792",\
+ "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\
+ "1.026127, 1.326200, 1.583265, 2.036317, 2.944378",\
+ "1.056712, 1.356785, 1.613849, 2.066902, 2.974963",\
+ "1.128539, 1.428612, 1.685676, 2.138729, 3.046790",\
+ "1.384998, 1.685071, 1.942135, 2.395187, 3.303248",\
+ "2.300766, 2.600840, 2.857905, 3.310958, 4.219019");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.408175, 0.590716, 0.786971, 1.096187, 1.691482",\
+ "0.433969, 0.616510, 0.812765, 1.121982, 1.717278",\
+ "0.485381, 0.667922, 0.864176, 1.173393, 1.768689",\
+ "0.652191, 0.834732, 1.030986, 1.340203, 1.935498",\
+ "1.242445, 1.424986, 1.621241, 1.930458, 2.525753",\
+ "0.495595, 0.678101, 0.874464, 1.183492, 1.778835",\
+ "0.521389, 0.703896, 0.900258, 1.209287, 1.804631",\
+ "0.572801, 0.755307, 0.951669, 1.260698, 1.856043",\
+ "0.739611, 0.922117, 1.118479, 1.427508, 2.022852",\
+ "1.329865, 1.512371, 1.708734, 2.017763, 2.613107",\
+ "0.576463, 0.758438, 0.954491, 1.263521, 1.858867",\
+ "0.602257, 0.784232, 0.980285, 1.289316, 1.884663",\
+ "0.653668, 0.835644, 1.031696, 1.340727, 1.936074",\
+ "0.820478, 1.002454, 1.198506, 1.507537, 2.102884",\
+ "1.410733, 1.592708, 1.788760, 2.097791, 2.693139",\
+ "0.634101, 0.815987, 1.012035, 1.320766, 1.915514",\
+ "0.659896, 0.841781, 1.037829, 1.346561, 1.941311",\
+ "0.711307, 0.893192, 1.089240, 1.397972, 1.992722",\
+ "0.878117, 1.060002, 1.256050, 1.564782, 2.159531",\
+ "1.468371, 1.650257, 1.846304, 2.155036, 2.749786",\
+ "0.936197, 1.121213, 1.315669, 1.623781, 2.217361",\
+ "0.961991, 1.147007, 1.341463, 1.649576, 2.243157",\
+ "1.013402, 1.198419, 1.392874, 1.700987, 2.294569",\
+ "1.180212, 1.365229, 1.559684, 1.867797, 2.461378",\
+ "1.770467, 1.955483, 2.149939, 2.458051, 3.051633");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\
+ "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\
+ "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\
+ "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\
+ "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523854, 1.523858");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2605*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.552667, 0.731094, 0.911354, 1.197561, 1.748678",\
+ "0.583252, 0.761679, 0.941939, 1.228145, 1.779262",\
+ "0.655079, 0.833506, 1.013766, 1.299972, 1.851089",\
+ "0.911538, 1.089965, 1.270225, 1.556431, 2.107548",\
+ "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\
+ "0.637606, 0.816366, 0.997269, 1.283481, 1.835056",\
+ "0.668190, 0.846951, 1.027854, 1.314066, 1.865641",\
+ "0.740017, 0.918778, 1.099681, 1.385893, 1.937468",\
+ "0.996476, 1.175237, 1.356140, 1.642352, 2.193927",\
+ "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\
+ "0.713512, 0.891810, 1.072078, 1.358078, 1.909228",\
+ "0.744096, 0.922394, 1.102663, 1.388662, 1.939813",\
+ "0.815923, 0.994221, 1.174490, 1.460489, 2.011640",\
+ "1.072382, 1.250680, 1.430949, 1.716949, 2.268099",\
+ "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\
+ "0.767864, 0.946321, 1.126729, 1.412617, 1.963546",\
+ "0.798448, 0.976906, 1.157314, 1.443202, 1.994130",\
+ "0.870275, 1.048733, 1.229141, 1.515029, 2.065957",\
+ "1.126734, 1.305192, 1.485600, 1.771488, 2.322416",\
+ "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\
+ "1.049286, 1.231549, 1.410680, 1.696344, 2.246823",\
+ "1.079870, 1.262133, 1.441265, 1.726928, 2.277408",\
+ "1.151697, 1.333960, 1.513092, 1.798755, 2.349235",\
+ "1.408157, 1.590420, 1.769551, 2.055214, 2.605694",\
+ "2.323925, 2.506187, 2.685319, 2.970983, 3.521462");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\
+ "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\
+ "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\
+ "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.425447, 0.690617, 0.949819, 1.386001, 2.258367",\
+ "0.451242, 0.716412, 0.975613, 1.411796, 2.284161",\
+ "0.502653, 0.767823, 1.027025, 1.463207, 2.335572",\
+ "0.669463, 0.934633, 1.193834, 1.630017, 2.502382",\
+ "1.259717, 1.524887, 1.784089, 2.220271, 3.092637",\
+ "0.514113, 0.778692, 1.038460, 1.474230, 2.345772",\
+ "0.539907, 0.804487, 1.064254, 1.500025, 2.371566",\
+ "0.591319, 0.855898, 1.115665, 1.551436, 2.422977",\
+ "0.758128, 1.022708, 1.282475, 1.718246, 2.589787",\
+ "1.348383, 1.612962, 1.872730, 2.308500, 3.180042",\
+ "0.606920, 0.871815, 1.130185, 1.566394, 2.438814",\
+ "0.632714, 0.897609, 1.155979, 1.592189, 2.464608",\
+ "0.684125, 0.949021, 1.207391, 1.643600, 2.516019",\
+ "0.850935, 1.115831, 1.374201, 1.810410, 2.682829",\
+ "1.441190, 1.706085, 1.964455, 2.400664, 3.273083",\
+ "0.672642, 0.940349, 1.197205, 1.633245, 2.505325",\
+ "0.698436, 0.966144, 1.222999, 1.659039, 2.531119",\
+ "0.749848, 1.017555, 1.274411, 1.710450, 2.582530",\
+ "0.916658, 1.184365, 1.441221, 1.877260, 2.749340",\
+ "1.506912, 1.774619, 2.031475, 2.467515, 3.339595",\
+ "1.018432, 1.320848, 1.567835, 2.002376, 2.871458",\
+ "1.044226, 1.346642, 1.593630, 2.028170, 2.897252",\
+ "1.095637, 1.398053, 1.645041, 2.079582, 2.948663",\
+ "1.262447, 1.564863, 1.811851, 2.246391, 3.115473",\
+ "1.852702, 2.155118, 2.402105, 2.836646, 3.705728");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\
+ "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\
+ "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\
+ "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\
+ "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\
+ "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\
+ "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\
+ "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\
+ "1.523853, 1.523853, 1.523853, 1.523852, 1.523852");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2550*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.319941, 0.350525, 0.422353, 0.678812, 1.594576",\
+ "0.407332, 0.437916, 0.509743, 0.766203, 1.681967",\
+ "0.488251, 0.518835, 0.590662, 0.847122, 1.762885",\
+ "0.545991, 0.576576, 0.648403, 0.904863, 1.820624",\
+ "0.849304, 0.879623, 0.951109, 1.207569, 2.123717");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.040153, 0.086136, 0.217338, 0.715446, 2.463218",\
+ "0.040153, 0.086136, 0.217409, 0.715446, 2.463218",\
+ "0.040153, 0.086136, 0.217647, 0.715446, 2.463317",\
+ "0.040153, 0.086137, 0.217647, 0.715446, 2.463317",\
+ "0.040344, 0.086164, 0.217985, 0.715471, 2.463779");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.305331, 0.331125, 0.382537, 0.549347, 1.139601",\
+ "0.392724, 0.418518, 0.469929, 0.636739, 1.226994",\
+ "0.473593, 0.499388, 0.550799, 0.717609, 1.307863",\
+ "0.531242, 0.557036, 0.608448, 0.775257, 1.365512",\
+ "0.833898, 0.859693, 0.911104, 1.077914, 1.668168");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\
+ "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\
+ "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\
+ "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\
+ "0.040602, 0.069933, 0.145764, 0.443908, 1.524252");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.513147, 0.693261, 0.880839, 1.182819, 1.765915",\
+ "0.542599, 0.722713, 0.910291, 1.212271, 1.795367",\
+ "0.613669, 0.793782, 0.981361, 1.283341, 1.866437",\
+ "0.869896, 1.050010, 1.237589, 1.539568, 2.122664",\
+ "1.786688, 1.966802, 2.154380, 2.456360, 3.039456",\
+ "0.598086, 0.778097, 0.965909, 1.268325, 1.852293",\
+ "0.627537, 0.807548, 0.995361, 1.297777, 1.881745",\
+ "0.698607, 0.878618, 1.066431, 1.368847, 1.952815",\
+ "0.954835, 1.134846, 1.322659, 1.625075, 2.209043",\
+ "1.871626, 2.051637, 2.239450, 2.541866, 3.125834",\
+ "0.673998, 0.853540, 1.040718, 1.342922, 1.926466",\
+ "0.703449, 0.882992, 1.070170, 1.372374, 1.955918",\
+ "0.774519, 0.954062, 1.141240, 1.443444, 2.026988",\
+ "1.030747, 1.210289, 1.397468, 1.699671, 2.283215",\
+ "1.947538, 2.127081, 2.314259, 2.616463, 3.200007",\
+ "0.728367, 0.908291, 1.095607, 1.397528, 1.980783",\
+ "0.757819, 0.937743, 1.125059, 1.426980, 2.010235",\
+ "0.828888, 1.008813, 1.196129, 1.498049, 2.081305",\
+ "1.085116, 1.265041, 1.452356, 1.754277, 2.337533",\
+ "2.001908, 2.181832, 2.369148, 2.671069, 3.254324",\
+ "1.009962, 1.193856, 1.379783, 1.681254, 2.264061",\
+ "1.039413, 1.223308, 1.409234, 1.710706, 2.293513",\
+ "1.110483, 1.294378, 1.480304, 1.781775, 2.364582",\
+ "1.366711, 1.550606, 1.736532, 2.038003, 2.620810",\
+ "2.283502, 2.467397, 2.653323, 2.954795, 3.537601");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.386312, 0.653923, 0.915324, 1.355101, 2.234262",\
+ "0.410188, 0.677799, 0.939200, 1.378977, 2.258138",\
+ "0.459747, 0.727358, 0.988759, 1.428536, 2.307697",\
+ "0.625673, 0.893283, 1.154685, 1.594462, 2.473623",\
+ "1.214481, 1.482092, 1.743493, 2.183270, 3.062431",\
+ "0.475016, 0.741998, 1.003965, 1.443330, 2.321667",\
+ "0.498892, 0.765874, 1.027841, 1.467206, 2.345543",\
+ "0.548452, 0.815433, 1.077400, 1.516765, 2.395102",\
+ "0.714377, 0.981359, 1.243325, 1.682691, 2.561028",\
+ "1.303185, 1.570167, 1.832134, 2.271499, 3.149836",\
+ "0.567959, 0.835318, 1.096009, 1.535576, 2.414709",\
+ "0.591835, 0.859194, 1.119885, 1.559452, 2.438585",\
+ "0.641394, 0.908753, 1.169445, 1.609011, 2.488144",\
+ "0.807319, 1.074679, 1.335370, 1.774936, 2.654070",\
+ "1.396127, 1.663487, 1.924178, 2.363745, 3.242877",\
+ "0.633802, 0.903882, 1.163065, 1.602587, 2.481630",\
+ "0.657678, 0.927758, 1.186941, 1.626463, 2.505507",\
+ "0.707237, 0.977318, 1.236501, 1.676022, 2.555066",\
+ "0.873163, 1.143243, 1.402426, 1.841948, 2.720992",\
+ "1.461971, 1.732051, 1.991234, 2.430756, 3.309799",\
+ "0.980324, 1.284718, 1.533736, 1.971813, 2.847966",\
+ "1.004200, 1.308594, 1.557612, 1.995689, 2.871842",\
+ "1.053759, 1.358153, 1.607171, 2.045248, 2.921401",\
+ "1.219684, 1.524079, 1.773097, 2.211174, 3.087327",\
+ "1.808493, 2.112887, 2.361905, 2.799982, 3.676135");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\
+ "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\
+ "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\
+ "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\
+ "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2492*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.421256, 0.684787, 0.960907, 1.429039, 2.364044",\
+ "0.450707, 0.714239, 0.990358, 1.458491, 2.393496",\
+ "0.521777, 0.785309, 1.061428, 1.529561, 2.464566",\
+ "0.778005, 1.041536, 1.317656, 1.785789, 2.720794",\
+ "1.694797, 1.958328, 2.234447, 2.702580, 3.637585",\
+ "0.509450, 0.772327, 1.048474, 1.515754, 2.449978",\
+ "0.538902, 0.801779, 1.077925, 1.545206, 2.479430",\
+ "0.609972, 0.872849, 1.148995, 1.616276, 2.550500",\
+ "0.866199, 1.129077, 1.405223, 1.872504, 2.806728",\
+ "1.782991, 2.045868, 2.322014, 2.789295, 3.723519",\
+ "0.597766, 0.861307, 1.136438, 1.603395, 2.536933",\
+ "0.627218, 0.890759, 1.165890, 1.632846, 2.566385",\
+ "0.698288, 0.961829, 1.236960, 1.703916, 2.637455",\
+ "0.954515, 1.218056, 1.493188, 1.960144, 2.893683",\
+ "1.871307, 2.134848, 2.409979, 2.876935, 3.810474",\
+ "0.660262, 0.926941, 1.200578, 1.667483, 2.600442",\
+ "0.689714, 0.956392, 1.230030, 1.696935, 2.629894",\
+ "0.760784, 1.027462, 1.301100, 1.768005, 2.700964",\
+ "1.017011, 1.283690, 1.557327, 2.024233, 2.957192",\
+ "1.933803, 2.200481, 2.474119, 2.941024, 3.873983",\
+ "0.989388, 1.291255, 1.552442, 2.016927, 2.945898",\
+ "1.018839, 1.320707, 1.581894, 2.046379, 2.975350",\
+ "1.089909, 1.391777, 1.652964, 2.117449, 3.046420",\
+ "1.346137, 1.648005, 1.909191, 2.373677, 3.302648",\
+ "2.262928, 2.564796, 2.825983, 3.290468, 4.219439");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\
+ "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\
+ "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\
+ "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\
+ "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.369267, 0.551325, 0.747559, 1.056740, 1.651224",\
+ "0.393143, 0.575201, 0.771435, 1.080616, 1.675100",\
+ "0.442703, 0.624760, 0.820994, 1.130175, 1.724659",\
+ "0.608628, 0.790685, 0.986919, 1.296102, 1.890590",\
+ "1.197436, 1.379494, 1.575727, 1.884908, 2.479391",\
+ "0.456682, 0.638644, 0.834839, 1.144045, 1.738577",\
+ "0.480558, 0.662519, 0.858715, 1.167921, 1.762453",\
+ "0.530117, 0.712079, 0.908275, 1.217480, 1.812012",\
+ "0.696043, 0.878004, 1.074200, 1.383407, 1.977943",\
+ "1.284851, 1.466812, 1.663008, 1.972213, 2.566744",\
+ "0.537558, 0.718980, 0.914866, 1.224073, 1.818609",\
+ "0.561434, 0.742856, 0.938742, 1.247949, 1.842485",\
+ "0.610994, 0.792415, 0.988301, 1.297508, 1.892044",\
+ "0.776919, 0.958341, 1.154227, 1.463436, 2.057975",\
+ "1.365727, 1.547149, 1.743035, 2.052242, 2.646776",\
+ "0.595205, 0.776817, 0.972602, 1.281544, 1.875705",\
+ "0.619081, 0.800693, 0.996478, 1.305420, 1.899580",\
+ "0.668640, 0.850252, 1.046037, 1.354979, 1.949140",\
+ "0.834565, 1.016178, 1.211963, 1.520906, 2.115070",\
+ "1.423374, 1.604986, 1.800771, 2.109712, 2.703871",\
+ "0.897412, 1.082194, 1.276265, 1.584751, 2.178023",\
+ "0.921288, 1.106070, 1.300141, 1.608627, 2.201899",\
+ "0.970848, 1.155629, 1.349701, 1.658186, 2.251458",\
+ "1.136773, 1.321555, 1.515626, 1.824113, 2.417389",\
+ "1.725581, 1.910363, 2.104434, 2.412919, 3.006190");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\
+ "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\
+ "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\
+ "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\
+ "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2414*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.417278, 0.676837, 0.948472, 1.404635, 2.315804",\
+ "0.446729, 0.706289, 0.977924, 1.434087, 2.345256",\
+ "0.517799, 0.777359, 1.048994, 1.505156, 2.416326",\
+ "0.774027, 1.033586, 1.305222, 1.761384, 2.672554",\
+ "1.690818, 1.950378, 2.222013, 2.678176, 3.589346",\
+ "0.505382, 0.764370, 1.036001, 1.491350, 2.401738",\
+ "0.534834, 0.793822, 1.065453, 1.520802, 2.431190",\
+ "0.605904, 0.864891, 1.136523, 1.591872, 2.502260",\
+ "0.862132, 1.121119, 1.392751, 1.848100, 2.758488",\
+ "1.778923, 2.037910, 2.309542, 2.764891, 3.675279",\
+ "0.593413, 0.853334, 1.123966, 1.578989, 2.488693",\
+ "0.622864, 0.882786, 1.153417, 1.608441, 2.518145",\
+ "0.693934, 0.953856, 1.224487, 1.679511, 2.589215",\
+ "0.950162, 1.210083, 1.480715, 1.935739, 2.845443",\
+ "1.866953, 2.126875, 2.397506, 2.852530, 3.762234",\
+ "0.655634, 0.918945, 1.188103, 1.643063, 2.552202",\
+ "0.685085, 0.948397, 1.217555, 1.672515, 2.581654",\
+ "0.756155, 1.019467, 1.288625, 1.743585, 2.652724",\
+ "1.012383, 1.275695, 1.544853, 1.999813, 2.908952",\
+ "1.929174, 2.192486, 2.461644, 2.916605, 3.825743",\
+ "0.983021, 1.282994, 1.539846, 1.992450, 2.897658",\
+ "1.012473, 1.312446, 1.569298, 2.021902, 2.927110",\
+ "1.083543, 1.383515, 1.640368, 2.092972, 2.998180",\
+ "1.339770, 1.639743, 1.896595, 2.349199, 3.254408",\
+ "2.256562, 2.556535, 2.813387, 3.265991, 4.171200");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\
+ "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\
+ "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\
+ "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\
+ "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\
+ "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\
+ "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\
+ "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\
+ "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\
+ "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\
+ "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\
+ "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\
+ "2.456797, 2.456796, 2.456792, 2.456784, 2.456766");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.367604, 0.549771, 0.745869, 1.055208, 1.650168",\
+ "0.391480, 0.573647, 0.769745, 1.079083, 1.674044",\
+ "0.441039, 0.623206, 0.819305, 1.128643, 1.723603",\
+ "0.606964, 0.789132, 0.985230, 1.294570, 1.889535",\
+ "1.195773, 1.377940, 1.574038, 1.883376, 2.478335",\
+ "0.455024, 0.637090, 0.833150, 1.142513, 1.737522",\
+ "0.478900, 0.660966, 0.857026, 1.166389, 1.761397",\
+ "0.528459, 0.710525, 0.906585, 1.215948, 1.810957",\
+ "0.694384, 0.876450, 1.072511, 1.381875, 1.976888",\
+ "1.283193, 1.465259, 1.661319, 1.970681, 2.565688",\
+ "0.535891, 0.717427, 0.913177, 1.222541, 1.817554",\
+ "0.559767, 0.741302, 0.937053, 1.246417, 1.841429",\
+ "0.609326, 0.790862, 0.986612, 1.295976, 1.890988",\
+ "0.775252, 0.956787, 1.152538, 1.461904, 2.056920",\
+ "1.364060, 1.545596, 1.741346, 2.050709, 2.645720",\
+ "0.593530, 0.775263, 0.970912, 1.280012, 1.874650",\
+ "0.617406, 0.799139, 0.994788, 1.303888, 1.898526",\
+ "0.666965, 0.848699, 1.044348, 1.353447, 1.948085",\
+ "0.832891, 1.014624, 1.210274, 1.519375, 2.114016",\
+ "1.421699, 1.603432, 1.799081, 2.108180, 2.702816",\
+ "0.895625, 1.080642, 1.274576, 1.583220, 2.176970",\
+ "0.919501, 1.104518, 1.298452, 1.607095, 2.200845",\
+ "0.969060, 1.154077, 1.348011, 1.656655, 2.250404",\
+ "1.134986, 1.320002, 1.513937, 1.822582, 2.416336",\
+ "1.723794, 1.908811, 2.102745, 2.411388, 3.005136");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\
+ "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\
+ "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\
+ "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\
+ "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\
+ "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\
+ "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\
+ "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\
+ "1.518841, 1.518841, 1.518841, 1.518842, 1.518844");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2348*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.509561, 0.687900, 0.868247, 1.154434, 1.705187",\
+ "0.539012, 0.717352, 0.897699, 1.183885, 1.734638",\
+ "0.610082, 0.788422, 0.968769, 1.254955, 1.805708",\
+ "0.866310, 1.044649, 1.224996, 1.511183, 2.061936",\
+ "1.783102, 1.961441, 2.141788, 2.427974, 2.978728",\
+ "0.594499, 0.772736, 0.953317, 1.239940, 1.791565",\
+ "0.623951, 0.802188, 0.982769, 1.269392, 1.821017",\
+ "0.695021, 0.873258, 1.053839, 1.340461, 1.892087",\
+ "0.951248, 1.129485, 1.310066, 1.596689, 2.148314",\
+ "1.868040, 2.046277, 2.226858, 2.513481, 3.065106",\
+ "0.670405, 0.848179, 1.028126, 1.314537, 1.865738",\
+ "0.699857, 0.877631, 1.057578, 1.343988, 1.895189",\
+ "0.770927, 0.948701, 1.128648, 1.415058, 1.966259",\
+ "1.027155, 1.204929, 1.384875, 1.671286, 2.222487",\
+ "1.943946, 2.121720, 2.301667, 2.588078, 3.139278",\
+ "0.724757, 0.902925, 1.082991, 1.369130, 1.920055",\
+ "0.754209, 0.932377, 1.112443, 1.398582, 1.949507",\
+ "0.825279, 1.003447, 1.183513, 1.469652, 2.020576",\
+ "1.081507, 1.259674, 1.439741, 1.725880, 2.276804",\
+ "1.998298, 2.176466, 2.356532, 2.642671, 3.193595",\
+ "1.006179, 1.188442, 1.367144, 1.652857, 2.203332",\
+ "1.035631, 1.217894, 1.396596, 1.682308, 2.232784",\
+ "1.106701, 1.288964, 1.467666, 1.753378, 2.303854",\
+ "1.362929, 1.545192, 1.723894, 2.009606, 2.560082",\
+ "2.279720, 2.461983, 2.640685, 2.926397, 3.476873");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\
+ "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\
+ "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\
+ "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.384876, 0.649875, 0.908905, 1.345169, 2.217316",\
+ "0.408752, 0.673751, 0.932781, 1.369045, 2.241192",\
+ "0.458311, 0.723311, 0.982340, 1.418604, 2.290751",\
+ "0.624237, 0.889236, 1.148266, 1.584530, 2.456676",\
+ "1.213045, 1.478044, 1.737074, 2.173338, 3.045485",\
+ "0.473542, 0.737950, 0.997546, 1.433398, 2.304721",\
+ "0.497418, 0.761826, 1.021422, 1.457274, 2.328597",\
+ "0.546977, 0.811386, 1.070981, 1.506833, 2.378156",\
+ "0.712902, 0.977311, 1.236907, 1.672759, 2.544082",\
+ "1.301711, 1.566119, 1.825715, 2.261567, 3.132890",\
+ "0.566349, 0.831244, 1.089581, 1.525641, 2.397763",\
+ "0.590225, 0.855120, 1.113457, 1.549517, 2.421639",\
+ "0.639784, 0.904679, 1.163016, 1.599077, 2.471198",\
+ "0.805709, 1.070605, 1.328942, 1.765002, 2.637124",\
+ "1.394518, 1.659413, 1.917750, 2.353810, 3.225932",\
+ "0.632071, 0.899778, 1.156636, 1.592648, 2.464673",\
+ "0.655947, 0.923654, 1.180512, 1.616524, 2.488548",\
+ "0.705506, 0.973213, 1.230071, 1.666083, 2.538108",\
+ "0.871432, 1.139139, 1.395997, 1.832009, 2.704033",\
+ "1.460240, 1.727947, 1.984805, 2.420817, 3.292841",\
+ "0.977860, 1.280277, 1.527274, 1.961849, 2.830999",\
+ "1.001736, 1.304152, 1.551150, 1.985725, 2.854876",\
+ "1.051296, 1.353712, 1.600709, 2.035285, 2.904435",\
+ "1.217221, 1.519637, 1.766635, 2.201210, 3.070360",\
+ "1.806029, 2.108445, 2.355443, 2.790018, 3.659168");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\
+ "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\
+ "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\
+ "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\
+ "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\
+ "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\
+ "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\
+ "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\
+ "1.518841, 1.518841, 1.518841, 1.518841, 1.518841");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2294*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.137566, 0.167336, 0.239033, 0.495310, 1.411098",\
+ "0.225751, 0.255520, 0.327229, 0.583553, 1.499024",\
+ "0.314076, 0.343844, 0.415554, 0.672074, 1.587106",\
+ "0.376665, 0.406437, 0.478090, 0.734905, 1.650403",\
+ "0.706539, 0.736325, 0.807782, 1.065036, 1.982165");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\
+ "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\
+ "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\
+ "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\
+ "0.036606, 0.083622, 0.215854, 0.705773, 2.456797");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.176657, 0.200194, 0.249429, 0.415146, 1.003925",\
+ "0.264061, 0.287598, 0.336833, 0.502550, 1.091329",\
+ "0.344959, 0.368493, 0.417732, 0.583454, 1.172242",\
+ "0.402624, 0.426151, 0.475399, 0.641128, 1.229933",\
+ "0.704984, 0.728497, 0.777773, 0.943572, 1.532550");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.032799, 0.061344, 0.138999, 0.438536, 1.518306",\
+ "0.032799, 0.061344, 0.138999, 0.438535, 1.518306",\
+ "0.032799, 0.061344, 0.138999, 0.438535, 1.518105",\
+ "0.032799, 0.061344, 0.138999, 0.438535, 1.517729",\
+ "0.032799, 0.061344, 0.138998, 0.438535, 1.516557");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.078864, 0.108975, 0.180232, 0.436421, 1.354955",\
+ "0.161216, 0.191623, 0.263062, 0.519150, 1.434794",\
+ "0.248912, 0.281774, 0.353596, 0.609294, 1.527520",\
+ "0.395567, 0.436700, 0.511657, 0.767118, 1.680857",\
+ "0.628444, 0.688613, 0.779970, 1.032241, 1.943170");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.039377, 0.084977, 0.216447, 0.713042, 2.472405",\
+ "0.040943, 0.085824, 0.216786, 0.713478, 2.472405",\
+ "0.053222, 0.092507, 0.217591, 0.713478, 2.472405",\
+ "0.083456, 0.114560, 0.223431, 0.713478, 2.472405",\
+ "0.146897, 0.173026, 0.257773, 0.713478, 2.472405");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.111091, 0.136344, 0.187602, 0.354583, 0.943175",\
+ "0.190778, 0.216967, 0.268153, 0.434275, 1.024748",\
+ "0.290508, 0.318338, 0.371105, 0.537415, 1.127562",\
+ "0.459624, 0.495257, 0.553492, 0.720404, 1.308180",\
+ "0.729304, 0.783232, 0.859550, 1.032706, 1.617889");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.039826, 0.069221, 0.145259, 0.444902, 1.525117",\
+ "0.040254, 0.069221, 0.145259, 0.444902, 1.525117",\
+ "0.050781, 0.076552, 0.148038, 0.444902, 1.525117",\
+ "0.080540, 0.101538, 0.163724, 0.445523, 1.525117",\
+ "0.141255, 0.162992, 0.212369, 0.458214, 1.525117");
+ }
+
+ } /* end of arc padmux2ast_i[6]_obs_ctrl_o[6]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.074357, 0.103835, 0.175088, 0.430040, 1.346996",\
+ "0.156284, 0.185798, 0.256925, 0.512689, 1.426492",\
+ "0.240577, 0.272242, 0.343453, 0.599199, 1.515415",\
+ "0.383466, 0.422274, 0.495817, 0.750018, 1.664121",\
+ "0.607663, 0.663725, 0.751347, 1.002896, 1.912977");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.036939, 0.083563, 0.215464, 0.698603, 2.446539",\
+ "0.038445, 0.084260, 0.215464, 0.704042, 2.446539",\
+ "0.049297, 0.090259, 0.216941, 0.705803, 2.446539",\
+ "0.076679, 0.110998, 0.222061, 0.706283, 2.457507",\
+ "0.134063, 0.165740, 0.252770, 0.710864, 2.457507");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.080261, 0.102858, 0.151114, 0.316434, 0.906304",\
+ "0.165732, 0.188510, 0.236836, 0.401880, 0.995903",\
+ "0.261156, 0.287506, 0.337668, 0.502550, 1.091127",\
+ "0.420973, 0.455458, 0.511965, 0.676394, 1.262831",\
+ "0.677498, 0.731290, 0.807033, 0.979368, 1.563209");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168");
+ values ( "0.032396, 0.061186, 0.138642, 0.440176, 1.520011",\
+ "0.033582, 0.061465, 0.138784, 0.440176, 1.520011",\
+ "0.046234, 0.071020, 0.142472, 0.440176, 1.520011",\
+ "0.075362, 0.096304, 0.158284, 0.443536, 1.520011",\
+ "0.135524, 0.156881, 0.206007, 0.453845, 1.520011");
+ }
+
+ } /* end of arc padmux2ast_i[6]_obs_ctrl_o[6]_una_min*/
+
+} /* end of pin obs_ctrl_o[6] */
+
+pin("obs_ctrl_o[5]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.156168 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001502 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[5];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.561257, 0.741460, 0.928950, 1.230943, 1.814455",\
+ "0.591077, 0.771280, 0.958770, 1.260762, 1.844274",\
+ "0.662801, 0.843004, 1.030494, 1.332487, 1.915998",\
+ "0.919252, 1.099455, 1.286945, 1.588937, 2.172449",\
+ "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\
+ "0.646196, 0.826743, 1.014959, 1.316955, 1.900833",\
+ "0.676015, 0.856563, 1.044779, 1.346775, 1.930653",\
+ "0.747739, 0.928287, 1.116503, 1.418499, 2.002377",\
+ "1.004190, 1.184738, 1.372953, 1.674950, 2.258828",\
+ "1.915830, 2.096378, 2.284594, 2.586590, 3.170468",\
+ "0.722108, 0.902187, 1.089768, 1.391552, 1.975005",\
+ "0.751927, 0.932006, 1.119587, 1.421371, 2.004825",\
+ "0.823651, 1.003731, 1.191312, 1.493096, 2.076549",\
+ "1.080102, 1.260181, 1.447762, 1.749547, 2.333000",\
+ "1.991742, 2.171822, 2.359402, 2.661187, 3.244640",\
+ "0.776477, 0.956699, 1.144419, 1.446092, 2.029323",\
+ "0.806297, 0.986518, 1.174238, 1.475911, 2.059142",\
+ "0.878021, 1.058242, 1.245963, 1.547635, 2.130867",\
+ "1.134472, 1.314693, 1.502414, 1.804086, 2.387317",\
+ "2.046112, 2.226333, 2.414053, 2.715726, 3.298958",\
+ "1.058072, 1.241966, 1.428370, 1.729818, 2.312600",\
+ "1.087891, 1.271786, 1.458189, 1.759638, 2.342420",\
+ "1.159616, 1.343510, 1.529913, 1.831362, 2.414144",\
+ "1.416066, 1.599961, 1.786364, 2.087812, 2.670595",\
+ "2.327706, 2.511601, 2.698004, 2.999453, 3.582235");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.431434, 0.699219, 0.960799, 1.400496, 2.279891",\
+ "0.455832, 0.723618, 0.985198, 1.424895, 2.304290",\
+ "0.506856, 0.774642, 1.036222, 1.475919, 2.355314",\
+ "0.673635, 0.941421, 1.203001, 1.642698, 2.522093",\
+ "1.261229, 1.529015, 1.790595, 2.230292, 3.109687",\
+ "0.520138, 0.787294, 1.049440, 1.488726, 2.367296",\
+ "0.544536, 0.811693, 1.073839, 1.513124, 2.391695",\
+ "0.595560, 0.862717, 1.124863, 1.564148, 2.442719",\
+ "0.762339, 1.029496, 1.291642, 1.730927, 2.609498",\
+ "1.349933, 1.617090, 1.879236, 2.318521, 3.197092",\
+ "0.613080, 0.880439, 1.141166, 1.580890, 2.460338",\
+ "0.637479, 0.904838, 1.165565, 1.605289, 2.484737",\
+ "0.688503, 0.955862, 1.216588, 1.656312, 2.535761",\
+ "0.855281, 1.122641, 1.383367, 1.823091, 2.702539",\
+ "1.442875, 1.710235, 1.970961, 2.410685, 3.290133",\
+ "0.678924, 0.949004, 1.208186, 1.647740, 2.526850",\
+ "0.703322, 0.973402, 1.232584, 1.672139, 2.551248",\
+ "0.754346, 1.024426, 1.283608, 1.723163, 2.602272",\
+ "0.921125, 1.191205, 1.450387, 1.889941, 2.769051",\
+ "1.508719, 1.778799, 2.037981, 2.477535, 3.356645",\
+ "1.025445, 1.329839, 1.578848, 2.016894, 2.892985",\
+ "1.049844, 1.354238, 1.603247, 2.041293, 2.917384",\
+ "1.100868, 1.405262, 1.654271, 2.092317, 2.968408",\
+ "1.267646, 1.572041, 1.821050, 2.259095, 3.135186",\
+ "1.855240, 2.159635, 2.408644, 2.846689, 3.722780");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2732*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.469363, 0.732936, 1.009209, 1.477938, 2.415398",\
+ "0.499182, 0.762756, 1.039028, 1.507758, 2.445217",\
+ "0.570906, 0.834480, 1.110752, 1.579482, 2.516941",\
+ "0.827357, 1.090931, 1.367203, 1.835933, 2.773392",\
+ "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\
+ "0.557557, 0.820477, 1.096777, 1.564654, 2.501331",\
+ "0.587376, 0.850296, 1.126596, 1.594473, 2.531151",\
+ "0.659100, 0.922021, 1.198320, 1.666197, 2.602875",\
+ "0.915551, 1.178471, 1.454771, 1.922648, 2.859325",\
+ "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\
+ "0.645873, 0.909457, 1.184741, 1.652276, 2.588286",\
+ "0.675692, 0.939277, 1.214561, 1.682096, 2.618106",\
+ "0.747417, 1.011001, 1.286285, 1.753820, 2.689830",\
+ "1.003868, 1.267452, 1.542736, 2.010271, 2.946280",\
+ "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\
+ "0.708369, 0.975092, 1.248881, 1.716190, 2.651795",\
+ "0.738189, 1.004912, 1.278701, 1.746009, 2.681615",\
+ "0.809913, 1.076636, 1.350425, 1.817733, 2.753339",\
+ "1.066364, 1.333087, 1.606875, 2.074184, 3.009789",\
+ "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\
+ "1.037495, 1.339423, 1.600748, 2.065540, 2.997252",\
+ "1.067314, 1.369243, 1.630568, 2.095359, 3.027071",\
+ "1.139038, 1.440967, 1.702292, 2.167083, 3.098795",\
+ "1.395489, 1.697417, 1.958743, 2.423534, 3.355246",\
+ "2.307129, 2.609058, 2.870384, 3.335176, 4.266890");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\
+ "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\
+ "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\
+ "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\
+ "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\
+ "2.463217, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.414387, 0.596819, 0.793211, 1.102263, 1.697070",\
+ "0.438785, 0.621217, 0.817609, 1.126662, 1.721470",\
+ "0.489809, 0.672241, 0.868633, 1.177686, 1.772493",\
+ "0.656588, 0.839020, 1.035412, 1.344465, 1.939272",\
+ "1.244182, 1.426614, 1.623006, 1.932059, 2.526866",\
+ "0.501801, 0.684204, 0.880704, 1.189568, 1.784423",\
+ "0.526200, 0.708603, 0.905102, 1.213968, 1.808823",\
+ "0.577224, 0.759627, 0.956126, 1.264991, 1.859847",\
+ "0.744003, 0.926405, 1.122905, 1.431770, 2.026625",\
+ "1.331597, 1.513999, 1.710499, 2.019364, 2.614220",\
+ "0.582678, 0.764541, 0.960731, 1.269597, 1.864455",\
+ "0.607077, 0.788939, 0.985129, 1.293996, 1.888855",\
+ "0.658100, 0.839963, 1.036153, 1.345020, 1.939878",\
+ "0.824879, 1.006742, 1.202932, 1.511798, 2.106657",\
+ "1.412473, 1.594336, 1.790526, 2.099392, 2.694252",\
+ "0.640324, 0.822089, 1.018274, 1.326842, 1.921102",\
+ "0.664723, 0.846488, 1.042673, 1.351241, 1.945503",\
+ "0.715747, 0.897512, 1.093697, 1.402265, 1.996526",\
+ "0.882525, 1.064290, 1.260476, 1.569043, 2.163304",\
+ "1.470119, 1.651884, 1.848070, 2.156638, 2.750899",\
+ "0.942532, 1.127314, 1.321908, 1.629857, 2.222949",\
+ "0.966931, 1.151712, 1.346307, 1.654256, 2.247349",\
+ "1.017955, 1.202736, 1.397331, 1.705280, 2.298373",\
+ "1.184733, 1.369515, 1.564109, 1.872058, 2.465151",\
+ "1.772327, 1.957109, 2.151703, 2.459652, 3.052746");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523992, 1.523996");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2657*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.465387, 0.725016, 0.996889, 1.453768, 2.367528",\
+ "0.495207, 0.754836, 1.026708, 1.483588, 2.397348",\
+ "0.566931, 0.826560, 1.098432, 1.555312, 2.469071",\
+ "0.823382, 1.083011, 1.354883, 1.811763, 2.725522",\
+ "1.735022, 1.994652, 2.266525, 2.723405, 3.637165",\
+ "0.553492, 0.812550, 1.084419, 1.540484, 2.453462",\
+ "0.583312, 0.842370, 1.114239, 1.570303, 2.483281",\
+ "0.655036, 0.914094, 1.185963, 1.642027, 2.555005",\
+ "0.911487, 1.170545, 1.442413, 1.898478, 2.811456",\
+ "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\
+ "0.641522, 0.901516, 1.172383, 1.628106, 2.540417",\
+ "0.671342, 0.931335, 1.202203, 1.657926, 2.570236",\
+ "0.743066, 1.003059, 1.273927, 1.729650, 2.641960",\
+ "0.999517, 1.259510, 1.530378, 1.986101, 2.898411",\
+ "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\
+ "0.703743, 0.967129, 1.236521, 1.692020, 2.603926",\
+ "0.733563, 0.996949, 1.266341, 1.721840, 2.633745",\
+ "0.805287, 1.068673, 1.338065, 1.793564, 2.705469",\
+ "1.061738, 1.325124, 1.594516, 2.050014, 2.961920",\
+ "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\
+ "1.031131, 1.331204, 1.588269, 2.041321, 2.949382",\
+ "1.060951, 1.361024, 1.618088, 2.071141, 2.979202",\
+ "1.132675, 1.432748, 1.689812, 2.142864, 3.050925",\
+ "1.389125, 1.689199, 1.946263, 2.399315, 3.307376",\
+ "2.300766, 2.600840, 2.857904, 3.310957, 4.219019");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723332, 0.723329, 0.723323, 0.723311",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047099, 0.047099, 0.047099, 0.047099",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\
+ "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.412725, 0.595266, 0.791521, 1.100738, 1.696032",\
+ "0.437124, 0.619665, 0.815920, 1.125137, 1.720433",\
+ "0.488148, 0.670689, 0.866944, 1.176161, 1.771456",\
+ "0.654926, 0.837467, 1.033722, 1.342939, 1.938234",\
+ "1.242520, 1.425061, 1.621316, 1.930533, 2.525829",\
+ "0.500145, 0.682652, 0.879014, 1.188043, 1.783386",\
+ "0.524544, 0.707050, 0.903413, 1.212442, 1.807786",\
+ "0.575568, 0.758074, 0.954436, 1.263466, 1.858810",\
+ "0.742347, 0.924853, 1.121215, 1.430244, 2.025588",\
+ "1.329941, 1.512447, 1.708809, 2.017838, 2.613183",\
+ "0.581013, 0.762988, 0.959041, 1.268071, 1.863418",\
+ "0.605412, 0.787387, 0.983440, 1.292470, 1.887818",\
+ "0.656435, 0.838411, 1.034463, 1.343494, 1.938841",\
+ "0.823214, 1.005190, 1.201242, 1.510273, 2.105619",\
+ "1.410808, 1.592784, 1.788836, 2.097867, 2.693214",\
+ "0.638652, 0.820537, 1.016585, 1.325316, 1.920065",\
+ "0.663050, 0.844936, 1.040983, 1.349715, 1.944465",\
+ "0.714074, 0.895960, 1.092007, 1.400739, 1.995489",\
+ "0.880853, 1.062738, 1.258786, 1.567518, 2.162267",\
+ "1.468447, 1.650332, 1.846380, 2.155112, 2.749862",\
+ "0.940747, 1.125763, 1.320219, 1.628331, 2.221912",\
+ "0.965146, 1.150162, 1.344617, 1.652730, 2.246312",\
+ "1.016169, 1.201186, 1.395641, 1.703754, 2.297336",\
+ "1.182948, 1.367965, 1.562420, 1.870533, 2.464114",\
+ "1.770542, 1.955559, 2.150014, 2.458127, 3.051709");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523993, 1.523996");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2600*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.557671, 0.736098, 0.916358, 1.202564, 1.753681",\
+ "0.587491, 0.765917, 0.946178, 1.232384, 1.783501",\
+ "0.659215, 0.837641, 1.017902, 1.304108, 1.855225",\
+ "0.915666, 1.094092, 1.274353, 1.560559, 2.111676",\
+ "1.827306, 2.005732, 2.185993, 2.472199, 3.023316",\
+ "0.642609, 0.821370, 1.002273, 1.288485, 1.840060",\
+ "0.672429, 0.851190, 1.032093, 1.318304, 1.869879",\
+ "0.744153, 0.922914, 1.103817, 1.390028, 1.941603",\
+ "1.000604, 1.179365, 1.360268, 1.646479, 2.198054",\
+ "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\
+ "0.718516, 0.896813, 1.077082, 1.363081, 1.914232",\
+ "0.748335, 0.926633, 1.106902, 1.392901, 1.944052",\
+ "0.820059, 0.998357, 1.178626, 1.464625, 2.015776",\
+ "1.076510, 1.254808, 1.435077, 1.721076, 2.272227",\
+ "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\
+ "0.772868, 0.951325, 1.131733, 1.417621, 1.968549",\
+ "0.802687, 0.981145, 1.161553, 1.447441, 1.998369",\
+ "0.874411, 1.052869, 1.233277, 1.519165, 2.070093",\
+ "1.130862, 1.309320, 1.489728, 1.775616, 2.326544",\
+ "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\
+ "1.054290, 1.236552, 1.415684, 1.701348, 2.251827",\
+ "1.084109, 1.266372, 1.445503, 1.731167, 2.281647",\
+ "1.155833, 1.338096, 1.517227, 1.802891, 2.353371",\
+ "1.412284, 1.594547, 1.773678, 2.059342, 2.609822",\
+ "2.323924, 2.506187, 2.685318, 2.970982, 3.521462");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\
+ "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\
+ "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\
+ "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.429998, 0.695167, 0.954369, 1.390552, 2.262917",\
+ "0.454396, 0.719566, 0.978768, 1.414950, 2.287315",\
+ "0.505420, 0.770590, 1.029792, 1.465974, 2.338339",\
+ "0.672199, 0.937369, 1.196570, 1.632753, 2.505118",\
+ "1.259793, 1.524963, 1.784164, 2.220347, 3.092712",\
+ "0.518663, 0.783242, 1.043010, 1.478781, 2.350322",\
+ "0.543062, 0.807641, 1.067409, 1.503179, 2.374721",\
+ "0.594086, 0.858665, 1.118433, 1.554203, 2.425745",\
+ "0.760864, 1.025444, 1.285211, 1.720982, 2.592523",\
+ "1.348459, 1.613038, 1.872805, 2.308576, 3.180117",\
+ "0.611470, 0.876365, 1.134735, 1.570945, 2.443364",\
+ "0.635869, 0.900764, 1.159134, 1.595343, 2.467762",\
+ "0.686893, 0.951788, 1.210158, 1.646367, 2.518786",\
+ "0.853671, 1.118567, 1.376937, 1.813146, 2.685565",\
+ "1.441265, 1.706161, 1.964531, 2.400740, 3.273159",\
+ "0.677192, 0.944899, 1.201755, 1.637795, 2.509875",\
+ "0.701591, 0.969298, 1.226154, 1.662194, 2.534274",\
+ "0.752615, 1.020322, 1.277178, 1.713217, 2.585298",\
+ "0.919394, 1.187101, 1.443956, 1.879996, 2.752076",\
+ "1.506988, 1.774695, 2.031551, 2.467590, 3.339670",\
+ "1.022982, 1.325398, 1.572386, 2.006926, 2.876008",\
+ "1.047381, 1.349797, 1.596784, 2.031325, 2.900407",\
+ "1.098405, 1.400820, 1.647808, 2.082349, 2.951431",\
+ "1.265183, 1.567599, 1.814587, 2.249127, 3.118209",\
+ "1.852777, 2.155193, 2.402181, 2.836721, 3.705803");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\
+ "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\
+ "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\
+ "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\
+ "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\
+ "1.523991, 1.523991, 1.523991, 1.523991, 1.523991");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2542*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.324944, 0.354764, 0.426488, 0.682940, 1.594576",\
+ "0.412335, 0.442155, 0.513879, 0.770331, 1.681967",\
+ "0.493254, 0.523074, 0.594798, 0.851250, 1.762885",\
+ "0.550995, 0.580814, 0.652539, 0.908991, 1.820623",\
+ "0.854260, 0.883835, 0.955245, 1.211697, 2.123717");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.047100, 0.093803, 0.225238, 0.723294, 2.463217",\
+ "0.047100, 0.093803, 0.225317, 0.723294, 2.463217",\
+ "0.047100, 0.093803, 0.225549, 0.723294, 2.463317",\
+ "0.047101, 0.093803, 0.225549, 0.723294, 2.463317",\
+ "0.047256, 0.093828, 0.225883, 0.723320, 2.463779");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.309881, 0.334280, 0.385304, 0.552083, 1.139677",\
+ "0.397274, 0.421673, 0.472696, 0.639475, 1.227069",\
+ "0.478143, 0.502542, 0.553566, 0.720345, 1.307939",\
+ "0.535792, 0.560191, 0.611215, 0.777993, 1.365587",\
+ "0.838449, 0.862847, 0.913871, 1.080650, 1.668244");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.045359, 0.074479, 0.150693, 0.448891, 1.524390",\
+ "0.045359, 0.074479, 0.150693, 0.448891, 1.524390",\
+ "0.045359, 0.074479, 0.150693, 0.448891, 1.524264",\
+ "0.045359, 0.074479, 0.150693, 0.448891, 1.524028",\
+ "0.045353, 0.074413, 0.150693, 0.448886, 1.523991");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.517919, 0.698033, 0.885611, 1.187591, 1.770688",\
+ "0.546784, 0.726898, 0.914476, 1.216456, 1.799552",\
+ "0.617826, 0.797940, 0.985519, 1.287498, 1.870595",\
+ "0.874029, 1.054142, 1.241721, 1.543701, 2.126797",\
+ "1.786688, 1.966801, 2.154380, 2.456360, 3.039456",\
+ "0.602858, 0.782869, 0.970682, 1.273098, 1.857066",\
+ "0.631723, 0.811734, 0.999546, 1.301962, 1.885931",\
+ "0.702765, 0.882776, 1.070589, 1.373005, 1.956973",\
+ "0.958967, 1.138978, 1.326791, 1.629207, 2.213175",\
+ "1.871626, 2.051637, 2.239450, 2.541866, 3.125834",\
+ "0.678770, 0.858312, 1.045491, 1.347694, 1.931238",\
+ "0.707635, 0.887177, 1.074355, 1.376559, 1.960103",\
+ "0.778677, 0.958219, 1.145398, 1.447601, 2.031145",\
+ "1.034879, 1.214422, 1.401600, 1.703804, 2.287347",\
+ "1.947538, 2.127081, 2.314259, 2.616463, 3.200006",\
+ "0.733139, 0.913064, 1.100379, 1.402300, 1.985556",\
+ "0.762004, 0.941928, 1.129244, 1.431165, 2.014421",\
+ "0.833046, 1.012970, 1.200286, 1.502207, 2.085463",\
+ "1.089248, 1.269173, 1.456489, 1.758409, 2.341665",\
+ "2.001907, 2.181832, 2.369148, 2.671068, 3.254324",\
+ "1.014734, 1.198629, 1.384555, 1.686026, 2.268833",\
+ "1.043599, 1.227494, 1.413420, 1.714891, 2.297698",\
+ "1.114641, 1.298536, 1.484462, 1.785933, 2.368740",\
+ "1.370843, 1.554738, 1.740664, 2.042135, 2.624942",\
+ "2.283502, 2.467397, 2.653323, 2.954794, 3.537601");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.390477, 0.658088, 0.919489, 1.359266, 2.238427",\
+ "0.413219, 0.680829, 0.942230, 1.382007, 2.261168",\
+ "0.462500, 0.730110, 0.991511, 1.431288, 2.310449",\
+ "0.628402, 0.896013, 1.157414, 1.597191, 2.476352",\
+ "1.214556, 1.482167, 1.743568, 2.183345, 3.062506",\
+ "0.479181, 0.746163, 1.008130, 1.447495, 2.325832",\
+ "0.501923, 0.768904, 1.030871, 1.470236, 2.348573",\
+ "0.551204, 0.818185, 1.080152, 1.519517, 2.397854",\
+ "0.717106, 0.984088, 1.246055, 1.685420, 2.563757",\
+ "1.303261, 1.570242, 1.832209, 2.271574, 3.149911",\
+ "0.572124, 0.839483, 1.100174, 1.539741, 2.418874",\
+ "0.594865, 0.862224, 1.122916, 1.562482, 2.441615",\
+ "0.644146, 0.911506, 1.172197, 1.611763, 2.490896",\
+ "0.810049, 1.077408, 1.338099, 1.777666, 2.656799",\
+ "1.396203, 1.663562, 1.924254, 2.363820, 3.242953",\
+ "0.637967, 0.908047, 1.167230, 1.606752, 2.485795",\
+ "0.660708, 0.930789, 1.189972, 1.629493, 2.508537",\
+ "0.709990, 0.980070, 1.239253, 1.678774, 2.557818",\
+ "0.875892, 1.145972, 1.405155, 1.844677, 2.723721",\
+ "1.462046, 1.732126, 1.991310, 2.430831, 3.309875",\
+ "0.984489, 1.288883, 1.537901, 1.975978, 2.852131",\
+ "1.007230, 1.311624, 1.560642, 1.998719, 2.874872",\
+ "1.056511, 1.360905, 1.609924, 2.048000, 2.924153",\
+ "1.222414, 1.526808, 1.775826, 2.213903, 3.090056",\
+ "1.808568, 2.112962, 2.361980, 2.800057, 3.676210");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\
+ "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\
+ "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\
+ "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\
+ "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2483*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.426028, 0.689559, 0.965679, 1.433811, 2.368817",\
+ "0.454893, 0.718424, 0.994544, 1.462676, 2.397682",\
+ "0.525935, 0.789466, 1.065586, 1.533718, 2.468724",\
+ "0.782137, 1.045668, 1.321788, 1.789921, 2.724926",\
+ "1.694796, 1.958328, 2.234447, 2.702580, 3.637585",\
+ "0.514222, 0.777100, 1.053246, 1.520527, 2.454750",\
+ "0.543087, 0.805965, 1.082111, 1.549392, 2.483615",\
+ "0.614129, 0.877007, 1.153153, 1.620434, 2.554657",\
+ "0.870331, 1.133209, 1.409355, 1.876636, 2.810860",\
+ "1.782991, 2.045868, 2.322014, 2.789295, 3.723519",\
+ "0.602538, 0.866079, 1.141211, 1.608167, 2.541705",\
+ "0.631403, 0.894944, 1.170076, 1.637032, 2.570570",\
+ "0.702445, 0.965986, 1.241118, 1.708074, 2.641613",\
+ "0.958647, 1.222188, 1.497320, 1.964276, 2.897815",\
+ "1.871307, 2.134848, 2.409979, 2.876935, 3.810474",\
+ "0.665034, 0.931713, 1.205350, 1.672256, 2.605214",\
+ "0.693899, 0.960578, 1.234215, 1.701121, 2.634079",\
+ "0.764941, 1.031620, 1.305257, 1.772163, 2.705122",\
+ "1.021144, 1.287822, 1.561460, 2.028365, 2.961324",\
+ "1.933803, 2.200481, 2.474119, 2.941024, 3.873983",\
+ "0.994160, 1.296028, 1.557214, 2.021699, 2.950670",\
+ "1.023025, 1.324893, 1.586079, 2.050565, 2.979536",\
+ "1.094067, 1.395935, 1.657121, 2.121607, 3.050578",\
+ "1.350269, 1.652137, 1.913324, 2.377809, 3.306780",\
+ "2.262928, 2.564796, 2.825983, 3.290468, 4.219439");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\
+ "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\
+ "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\
+ "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\
+ "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\
+ "2.456796, 2.456796, 2.456794, 2.456788, 2.456778");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.373432, 0.555490, 0.751724, 1.060905, 1.655389",\
+ "0.396174, 0.578231, 0.774465, 1.083646, 1.678130",\
+ "0.445455, 0.627512, 0.823746, 1.132927, 1.727411",\
+ "0.611357, 0.793415, 0.989649, 1.298831, 1.893319",\
+ "1.197512, 1.379569, 1.575803, 1.884983, 2.479466",\
+ "0.460847, 0.642809, 0.839005, 1.148210, 1.742743",\
+ "0.483588, 0.665550, 0.861746, 1.170951, 1.765483",\
+ "0.532870, 0.714831, 0.911027, 1.220232, 1.814765",\
+ "0.698772, 0.880733, 1.076930, 1.386137, 1.980672",\
+ "1.284926, 1.466888, 1.663084, 1.972288, 2.566819",\
+ "0.541724, 0.723145, 0.919032, 1.228239, 1.822774",\
+ "0.564465, 0.745886, 0.941773, 1.250980, 1.845515",\
+ "0.613746, 0.795168, 0.991054, 1.300261, 1.894796",\
+ "0.779648, 0.961070, 1.156957, 1.466165, 2.060704",\
+ "1.365803, 1.547224, 1.743111, 2.052317, 2.646851",\
+ "0.599370, 0.780982, 0.976767, 1.285709, 1.879870",\
+ "0.622111, 0.803723, 0.999508, 1.308450, 1.902611",\
+ "0.671392, 0.853004, 1.048790, 1.357731, 1.951892",\
+ "0.837295, 1.018907, 1.214692, 1.523636, 2.117800",\
+ "1.423449, 1.605061, 1.800846, 2.109787, 2.703947",\
+ "0.901578, 1.086359, 1.280431, 1.588916, 2.182188",\
+ "0.924319, 1.109100, 1.303172, 1.611657, 2.204929",\
+ "0.973600, 1.158382, 1.352453, 1.660938, 2.254210",\
+ "1.139503, 1.324284, 1.518356, 1.826843, 2.420118",\
+ "1.725657, 1.910438, 2.104510, 2.412994, 3.006265");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\
+ "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\
+ "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\
+ "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\
+ "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518981");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2405*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.422050, 0.681609, 0.953245, 1.409407, 2.320577",\
+ "0.450915, 0.710474, 0.982110, 1.438272, 2.349442",\
+ "0.521957, 0.781516, 1.053152, 1.509314, 2.420484",\
+ "0.778159, 1.037718, 1.309354, 1.765517, 2.676687",\
+ "1.690818, 1.950378, 2.222013, 2.678175, 3.589345",\
+ "0.510155, 0.769142, 1.040774, 1.496122, 2.406510",\
+ "0.539020, 0.798007, 1.069638, 1.524987, 2.435376",\
+ "0.610062, 0.869049, 1.140681, 1.596030, 2.506418",\
+ "0.866264, 1.125251, 1.396883, 1.852232, 2.762620",\
+ "1.778923, 2.037910, 2.309542, 2.764891, 3.675279",\
+ "0.598185, 0.858106, 1.128738, 1.583761, 2.493465",\
+ "0.627050, 0.886971, 1.157603, 1.612626, 2.522331",\
+ "0.698092, 0.958013, 1.228645, 1.683668, 2.593373",\
+ "0.954294, 1.214216, 1.484847, 1.939871, 2.849576",\
+ "1.866953, 2.126875, 2.397506, 2.852530, 3.762234",\
+ "0.660406, 0.923718, 1.192876, 1.647836, 2.556974",\
+ "0.689271, 0.952582, 1.221740, 1.676701, 2.585840",\
+ "0.760313, 1.023625, 1.292783, 1.747743, 2.656882",\
+ "1.016515, 1.279827, 1.548985, 2.003945, 2.913085",\
+ "1.929174, 2.192486, 2.461644, 2.916604, 3.825743",\
+ "0.987793, 1.287766, 1.544618, 1.997222, 2.902431",\
+ "1.016658, 1.316631, 1.573483, 2.026087, 2.931296",\
+ "1.087700, 1.387673, 1.644525, 2.097129, 3.002338",\
+ "1.343903, 1.643875, 1.900728, 2.353332, 3.258541",\
+ "2.256562, 2.556535, 2.813386, 3.265991, 4.171199");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\
+ "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\
+ "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\
+ "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\
+ "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\
+ "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\
+ "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\
+ "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\
+ "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\
+ "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\
+ "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\
+ "2.456796, 2.456795, 2.456792, 2.456783, 2.456766");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.371769, 0.553936, 0.750035, 1.059373, 1.654333",\
+ "0.394510, 0.576677, 0.772776, 1.082114, 1.677074",\
+ "0.443791, 0.625958, 0.822057, 1.131395, 1.726356",\
+ "0.609694, 0.791861, 0.987960, 1.297299, 1.892264",\
+ "1.195848, 1.378015, 1.574114, 1.883451, 2.478410",\
+ "0.459189, 0.641255, 0.837315, 1.146678, 1.741687",\
+ "0.481930, 0.663996, 0.860057, 1.169419, 1.764428",\
+ "0.531211, 0.713277, 0.909338, 1.218700, 1.813709",\
+ "0.697114, 0.879180, 1.075240, 1.384604, 1.979617",\
+ "1.283268, 1.465334, 1.661394, 1.970756, 2.565764",\
+ "0.540056, 0.721592, 0.917342, 1.226706, 1.821719",\
+ "0.562797, 0.744333, 0.940084, 1.249447, 1.844460",\
+ "0.612079, 0.793614, 0.989365, 1.298728, 1.893741",\
+ "0.777981, 0.959517, 1.155267, 1.464633, 2.059649",\
+ "1.364136, 1.545671, 1.741421, 2.050785, 2.645795",\
+ "0.597695, 0.779428, 0.975078, 1.284177, 1.878815",\
+ "0.620436, 0.802170, 0.997819, 1.306918, 1.901556",\
+ "0.669718, 0.851451, 1.047100, 1.356200, 1.950837",\
+ "0.835620, 1.017353, 1.213003, 1.522104, 2.116745",\
+ "1.421774, 1.603508, 1.799157, 2.108255, 2.702892",\
+ "0.899790, 1.084807, 1.278741, 1.587385, 2.181135",\
+ "0.922531, 1.107548, 1.301482, 1.610126, 2.203876",\
+ "0.971813, 1.156829, 1.350764, 1.659407, 2.253157",\
+ "1.137715, 1.322732, 1.516666, 1.825311, 2.419065",\
+ "1.723870, 1.908886, 2.102820, 2.411463, 3.005211");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\
+ "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\
+ "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\
+ "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\
+ "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\
+ "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\
+ "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\
+ "1.518979, 1.518979, 1.518979, 1.518980, 1.518982");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2343*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.514333, 0.692672, 0.873019, 1.159206, 1.709959",\
+ "0.543198, 0.721537, 0.901884, 1.188071, 1.738824",\
+ "0.614240, 0.792579, 0.972926, 1.259113, 1.809866",\
+ "0.870442, 1.048782, 1.229129, 1.515315, 2.066068",\
+ "1.783101, 1.961441, 2.141788, 2.427974, 2.978728",\
+ "0.599271, 0.777508, 0.958089, 1.244712, 1.796337",\
+ "0.628136, 0.806373, 0.986954, 1.273577, 1.825202",\
+ "0.699178, 0.877415, 1.057996, 1.344619, 1.896244",\
+ "0.955381, 1.133618, 1.314199, 1.600821, 2.152447",\
+ "1.868040, 2.046277, 2.226858, 2.513480, 3.065106",\
+ "0.675178, 0.852952, 1.032898, 1.319309, 1.870510",\
+ "0.704042, 0.881817, 1.061763, 1.348174, 1.899375",\
+ "0.775084, 0.952859, 1.132805, 1.419216, 1.970417",\
+ "1.031287, 1.209061, 1.389008, 1.675418, 2.226619",\
+ "1.943946, 2.121720, 2.301667, 2.588077, 3.139278",\
+ "0.729530, 0.907697, 1.087764, 1.373903, 1.924827",\
+ "0.758394, 0.936562, 1.116628, 1.402767, 1.953692",\
+ "0.829437, 1.007604, 1.187670, 1.473809, 2.024734",\
+ "1.085639, 1.263806, 1.443873, 1.730012, 2.280936",\
+ "1.998298, 2.176466, 2.356532, 2.642671, 3.193595",\
+ "1.010952, 1.193215, 1.371917, 1.657629, 2.208105",\
+ "1.039816, 1.222079, 1.400781, 1.686494, 2.236969",\
+ "1.110858, 1.293122, 1.471824, 1.757536, 2.308012",\
+ "1.367061, 1.549324, 1.728026, 2.013738, 2.564214",\
+ "2.279720, 2.461983, 2.640685, 2.926397, 3.476873");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\
+ "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\
+ "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\
+ "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\
+ "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\
+ "2.456796, 2.456796, 2.456796, 2.456796, 2.456796");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.389041, 0.654041, 0.913070, 1.349334, 2.221481",\
+ "0.411783, 0.676782, 0.935811, 1.372076, 2.244222",\
+ "0.461064, 0.726063, 0.985092, 1.421357, 2.293503",\
+ "0.626966, 0.891965, 1.150995, 1.587259, 2.459406",\
+ "1.213121, 1.478120, 1.737149, 2.173413, 3.045560",\
+ "0.477707, 0.742116, 1.001711, 1.437563, 2.308886",\
+ "0.500448, 0.764857, 1.024452, 1.460304, 2.331627",\
+ "0.549729, 0.814138, 1.073733, 1.509586, 2.380908",\
+ "0.715632, 0.980040, 1.239636, 1.675488, 2.546811",\
+ "1.301786, 1.566195, 1.825790, 2.261642, 3.132965",\
+ "0.570514, 0.835409, 1.093746, 1.529807, 2.401928",\
+ "0.593255, 0.858150, 1.116487, 1.552548, 2.424669",\
+ "0.642536, 0.907431, 1.165769, 1.601829, 2.473950",\
+ "0.808439, 1.073334, 1.331671, 1.767732, 2.639853",\
+ "1.394593, 1.659488, 1.917825, 2.353886, 3.226007",\
+ "0.636236, 0.903943, 1.160801, 1.596813, 2.468838",\
+ "0.658977, 0.926684, 1.183542, 1.619554, 2.491579",\
+ "0.708259, 0.975966, 1.232824, 1.668836, 2.540860",\
+ "0.874161, 1.141868, 1.398726, 1.834738, 2.706763",\
+ "1.460315, 1.728022, 1.984880, 2.420892, 3.292917",\
+ "0.982026, 1.284442, 1.531439, 1.966014, 2.835165",\
+ "1.004767, 1.307183, 1.554181, 1.988755, 2.857906",\
+ "1.054048, 1.356464, 1.603462, 2.038037, 2.907187",\
+ "1.219950, 1.522366, 1.769364, 2.203939, 3.073090",\
+ "1.806105, 2.108521, 2.355518, 2.790093, 3.659244");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\
+ "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\
+ "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\
+ "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\
+ "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\
+ "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\
+ "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\
+ "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\
+ "1.518979, 1.518979, 1.518979, 1.518979, 1.518979");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2288*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.142389, 0.171566, 0.243166, 0.499437, 1.411098",\
+ "0.230574, 0.259751, 0.331362, 0.587680, 1.499024",\
+ "0.318899, 0.348075, 0.419691, 0.676199, 1.587106",\
+ "0.381491, 0.410664, 0.482232, 0.739031, 1.650402",\
+ "0.711374, 0.740537, 0.811930, 1.069170, 1.982165");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\
+ "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\
+ "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\
+ "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\
+ "0.043742, 0.091388, 0.223754, 0.713686, 2.456796");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.180754, 0.203203, 0.252178, 0.417875, 1.004001",\
+ "0.268158, 0.290607, 0.339581, 0.505279, 1.091404",\
+ "0.349055, 0.371502, 0.420481, 0.586183, 1.172317",\
+ "0.406718, 0.429160, 0.478148, 0.643857, 1.230008",\
+ "0.709074, 0.731508, 0.780524, 0.946302, 1.532625");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.037339, 0.066008, 0.143979, 0.443541, 1.518445",\
+ "0.037339, 0.066008, 0.143979, 0.443540, 1.518445",\
+ "0.037339, 0.066008, 0.143979, 0.443540, 1.518243",\
+ "0.037339, 0.066008, 0.143979, 0.443540, 1.517867",\
+ "0.037339, 0.066008, 0.143978, 0.443540, 1.516694");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.083777, 0.113177, 0.184363, 0.440561, 1.354954",\
+ "0.166191, 0.195837, 0.267192, 0.523277, 1.434794",\
+ "0.254428, 0.286014, 0.357719, 0.613433, 1.527519",\
+ "0.402853, 0.441150, 0.515777, 0.771236, 1.680856",\
+ "0.639529, 0.694162, 0.784036, 1.036347, 1.943170");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.046241, 0.092638, 0.224458, 0.720967, 2.472405",\
+ "0.047673, 0.093421, 0.224642, 0.721323, 2.472405",\
+ "0.058846, 0.099756, 0.225481, 0.721323, 2.472405",\
+ "0.087693, 0.120786, 0.231211, 0.721323, 2.472405",\
+ "0.150701, 0.177706, 0.265097, 0.721323, 2.472405");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.115523, 0.139488, 0.190373, 0.357311, 0.943250",\
+ "0.195424, 0.220107, 0.270909, 0.437012, 1.024824",\
+ "0.295483, 0.321586, 0.373863, 0.540151, 1.127638",\
+ "0.466222, 0.498877, 0.556261, 0.723129, 1.308255",\
+ "0.739560, 0.788071, 0.862427, 1.035419, 1.617964");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.044606, 0.073777, 0.150227, 0.449909, 1.525255",\
+ "0.044880, 0.073777, 0.150227, 0.449909, 1.525255",\
+ "0.054859, 0.080811, 0.152895, 0.449909, 1.525255",\
+ "0.083786, 0.105188, 0.168383, 0.450518, 1.525255",\
+ "0.145006, 0.165847, 0.216404, 0.463154, 1.525255");
+ }
+
+ } /* end of arc padmux2ast_i[5]_obs_ctrl_o[5]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.079158, 0.108043, 0.179215, 0.434173, 1.346996",\
+ "0.161067, 0.189991, 0.261053, 0.516828, 1.426491",\
+ "0.245841, 0.276441, 0.347577, 0.603328, 1.515415",\
+ "0.390269, 0.426632, 0.499915, 0.754138, 1.664120",\
+ "0.617992, 0.669105, 0.755401, 1.006998, 1.912977");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.043983, 0.091336, 0.223341, 0.706536, 2.446538",\
+ "0.045333, 0.091976, 0.223341, 0.711950, 2.446538",\
+ "0.055328, 0.097699, 0.224823, 0.713717, 2.446538",\
+ "0.081572, 0.117377, 0.229870, 0.714277, 2.457507",\
+ "0.139013, 0.170652, 0.260149, 0.718737, 2.457507");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.084172, 0.105801, 0.153856, 0.319168, 0.906380",\
+ "0.169681, 0.191458, 0.239573, 0.404634, 0.995979",\
+ "0.265868, 0.290580, 0.340403, 0.505279, 1.091202",\
+ "0.427357, 0.458965, 0.514692, 0.679112, 1.262906",\
+ "0.687739, 0.736091, 0.809895, 0.982075, 1.563284");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168");
+ values ( "0.037000, 0.065831, 0.143664, 0.445190, 1.520147",\
+ "0.037985, 0.066094, 0.143861, 0.445190, 1.520147",\
+ "0.050092, 0.075267, 0.147407, 0.445190, 1.520147",\
+ "0.078605, 0.099932, 0.163006, 0.448532, 1.520147",\
+ "0.139198, 0.159714, 0.210091, 0.458787, 1.520147");
+ }
+
+ } /* end of arc padmux2ast_i[5]_obs_ctrl_o[5]_una_min*/
+
+} /* end of pin obs_ctrl_o[5] */
+
+pin("obs_ctrl_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.156168 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000989 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[4];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.556168, 0.736371, 0.923861, 1.225854, 1.809366",\
+ "0.586766, 0.766969, 0.954459, 1.256451, 1.839963",\
+ "0.658595, 0.838798, 1.026288, 1.328280, 1.911792",\
+ "0.915054, 1.095257, 1.282747, 1.584739, 2.168251",\
+ "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\
+ "0.641107, 0.821654, 1.009870, 1.311866, 1.895744",\
+ "0.671704, 0.852252, 1.040468, 1.342464, 1.926342",\
+ "0.743533, 0.924081, 1.112296, 1.414292, 1.998170",\
+ "0.999992, 1.180540, 1.368755, 1.670752, 2.254630",\
+ "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\
+ "0.717019, 0.897098, 1.084679, 1.386463, 1.969916",\
+ "0.747616, 0.927695, 1.115276, 1.417060, 2.000514",\
+ "0.819445, 0.999524, 1.187105, 1.488889, 2.072343",\
+ "1.075904, 1.255983, 1.443564, 1.745348, 2.328802",\
+ "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\
+ "0.771388, 0.951609, 1.139330, 1.441003, 2.024234",\
+ "0.801986, 0.982207, 1.169927, 1.471600, 2.054831",\
+ "0.873814, 1.054036, 1.241756, 1.543429, 2.126660",\
+ "1.130274, 1.310495, 1.498215, 1.799888, 2.383119",\
+ "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\
+ "1.052983, 1.236877, 1.423280, 1.724729, 2.307511",\
+ "1.083580, 1.267475, 1.453878, 1.755327, 2.338109",\
+ "1.155409, 1.339304, 1.525707, 1.827155, 2.409937",\
+ "1.411868, 1.595763, 1.782166, 2.083614, 2.666397",\
+ "2.327707, 2.511601, 2.698004, 2.999453, 3.582235");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.426989, 0.694775, 0.956355, 1.396052, 2.275447",\
+ "0.452751, 0.720537, 0.982117, 1.421814, 2.301209",\
+ "0.504153, 0.771939, 1.033519, 1.473216, 2.352611",\
+ "0.670963, 0.938748, 1.200328, 1.640025, 2.519420",\
+ "1.261262, 1.529048, 1.790628, 2.230325, 3.109720",\
+ "0.515693, 0.782850, 1.044996, 1.484281, 2.362852",\
+ "0.541455, 0.808612, 1.070758, 1.510043, 2.388614",\
+ "0.592858, 0.860014, 1.122160, 1.561445, 2.440016",\
+ "0.759667, 1.026823, 1.288969, 1.728255, 2.606825",\
+ "1.349967, 1.617123, 1.879269, 2.318554, 3.197125",\
+ "0.608636, 0.875995, 1.136721, 1.576445, 2.455894",\
+ "0.634398, 0.901757, 1.162483, 1.602207, 2.481656",\
+ "0.685800, 0.953159, 1.213886, 1.653610, 2.533058",\
+ "0.852609, 1.119968, 1.380695, 1.820419, 2.699867",\
+ "1.442909, 1.710268, 1.970994, 2.410718, 3.290167",\
+ "0.674479, 0.944559, 1.203741, 1.643296, 2.522405",\
+ "0.700241, 0.970321, 1.229503, 1.669058, 2.548167",\
+ "0.751643, 1.021724, 1.280905, 1.720460, 2.599569",\
+ "0.918453, 1.188533, 1.447715, 1.887269, 2.766378",\
+ "1.508752, 1.778832, 2.038014, 2.477569, 3.356678",\
+ "1.021001, 1.325395, 1.574404, 2.012450, 2.888541",\
+ "1.046763, 1.351157, 1.600166, 2.038211, 2.914303",\
+ "1.098165, 1.402559, 1.651568, 2.089614, 2.965705",\
+ "1.264974, 1.569368, 1.818377, 2.256423, 3.132514",\
+ "1.855274, 2.159668, 2.408677, 2.846723, 3.722814");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\
+ "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\
+ "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\
+ "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\
+ "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2724*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.464273, 0.727847, 1.004120, 1.472849, 2.410309",\
+ "0.494871, 0.758445, 1.034717, 1.503447, 2.440906",\
+ "0.566700, 0.830273, 1.106546, 1.575275, 2.512735",\
+ "0.823159, 1.086733, 1.363005, 1.831734, 2.769193",\
+ "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\
+ "0.552468, 0.815388, 1.091687, 1.559565, 2.496242",\
+ "0.583065, 0.845985, 1.122285, 1.590162, 2.526840",\
+ "0.654894, 0.917814, 1.194114, 1.661991, 2.598668",\
+ "0.911353, 1.174273, 1.450573, 1.918450, 2.855127",\
+ "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\
+ "0.640784, 0.904368, 1.179652, 1.647187, 2.583197",\
+ "0.671381, 0.934966, 1.210250, 1.677785, 2.613795",\
+ "0.743210, 1.006795, 1.282079, 1.749613, 2.685623",\
+ "0.999669, 1.263254, 1.538538, 2.006072, 2.942082",\
+ "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\
+ "0.703280, 0.970003, 1.243792, 1.711101, 2.646706",\
+ "0.733877, 1.000601, 1.274390, 1.741699, 2.677304",\
+ "0.805706, 1.072430, 1.346218, 1.813527, 2.749132",\
+ "1.062165, 1.328889, 1.602677, 2.069986, 3.005591",\
+ "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\
+ "1.032405, 1.334334, 1.595659, 2.060451, 2.992162",\
+ "1.063003, 1.364932, 1.626257, 2.091048, 3.022760",\
+ "1.134832, 1.436760, 1.698085, 2.162877, 3.094589",\
+ "1.391291, 1.693219, 1.954545, 2.419336, 3.351047",\
+ "2.307129, 2.609058, 2.870384, 3.335176, 4.266890");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.409942, 0.592374, 0.788766, 1.097819, 1.692625",\
+ "0.435704, 0.618136, 0.814528, 1.123581, 1.718389",\
+ "0.487107, 0.669538, 0.865930, 1.174984, 1.769791",\
+ "0.653916, 0.836348, 1.032740, 1.341792, 1.936599",\
+ "1.244215, 1.426647, 1.623039, 1.932092, 2.526900",\
+ "0.497357, 0.679760, 0.876259, 1.185124, 1.779979",\
+ "0.523119, 0.705522, 0.902021, 1.210886, 1.805742",\
+ "0.574521, 0.756924, 0.953424, 1.262289, 1.857144",\
+ "0.741330, 0.923733, 1.120233, 1.429098, 2.023953",\
+ "1.331630, 1.514033, 1.710532, 2.019397, 2.614253",\
+ "0.578233, 0.760096, 0.956286, 1.265153, 1.860010",\
+ "0.603995, 0.785858, 0.982048, 1.290915, 1.885774",\
+ "0.655398, 0.837260, 1.033450, 1.342317, 1.937176",\
+ "0.822207, 1.004070, 1.200260, 1.509126, 2.103984",\
+ "1.412507, 1.594369, 1.790559, 2.099426, 2.694285",\
+ "0.635880, 0.817645, 1.013830, 1.322398, 1.916658",\
+ "0.661642, 0.843407, 1.039592, 1.348160, 1.942421",\
+ "0.713044, 0.894809, 1.090994, 1.399562, 1.993823",\
+ "0.879853, 1.061618, 1.257803, 1.566371, 2.160632",\
+ "1.470153, 1.651918, 1.848103, 2.156671, 2.750932",\
+ "0.938088, 1.122869, 1.317464, 1.625412, 2.218504",\
+ "0.963849, 1.148631, 1.343226, 1.651175, 2.244268",\
+ "1.015252, 1.200033, 1.394628, 1.702577, 2.295670",\
+ "1.182061, 1.366843, 1.561437, 1.869386, 2.462479",\
+ "1.772361, 1.957142, 2.151737, 2.459686, 3.052779");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\
+ "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\
+ "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\
+ "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\
+ "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524057");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2651*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.460298, 0.719927, 0.991800, 1.448679, 2.362439",\
+ "0.490896, 0.750525, 1.022397, 1.479277, 2.393037",\
+ "0.562724, 0.822354, 1.094226, 1.551105, 2.464865",\
+ "0.819184, 1.078813, 1.350685, 1.807564, 2.721324",\
+ "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\
+ "0.548403, 0.807461, 1.079330, 1.535395, 2.448373",\
+ "0.579001, 0.838059, 1.109928, 1.565992, 2.478970",\
+ "0.650829, 0.909887, 1.181756, 1.637821, 2.550799",\
+ "0.907289, 1.166346, 1.438215, 1.894280, 2.807258",\
+ "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\
+ "0.636433, 0.896427, 1.167294, 1.623017, 2.535328",\
+ "0.667031, 0.927024, 1.197892, 1.653615, 2.565925",\
+ "0.738859, 0.998853, 1.269721, 1.725444, 2.637754",\
+ "0.995319, 1.255312, 1.526180, 1.981903, 2.894213",\
+ "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\
+ "0.698654, 0.962040, 1.231432, 1.686931, 2.598837",\
+ "0.729252, 0.992638, 1.262030, 1.717529, 2.629434",\
+ "0.801081, 1.064467, 1.333858, 1.789357, 2.701263",\
+ "1.057540, 1.320926, 1.590317, 2.045816, 2.957722",\
+ "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\
+ "1.026042, 1.326115, 1.583179, 2.036232, 2.944293",\
+ "1.056639, 1.356713, 1.613777, 2.066829, 2.974890",\
+ "1.128468, 1.428541, 1.685606, 2.138658, 3.046719",\
+ "1.384927, 1.685001, 1.942065, 2.395117, 3.303178",\
+ "2.300766, 2.600840, 2.857904, 3.310957, 4.219019");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\
+ "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.408281, 0.590822, 0.787077, 1.096293, 1.691588",\
+ "0.434043, 0.616584, 0.812839, 1.122056, 1.717351",\
+ "0.485445, 0.667986, 0.864241, 1.173458, 1.768753",\
+ "0.652254, 0.834795, 1.031050, 1.340267, 1.935562",\
+ "1.242554, 1.425095, 1.621350, 1.930567, 2.525863",\
+ "0.495701, 0.678207, 0.874570, 1.183598, 1.778941",\
+ "0.521463, 0.703969, 0.900331, 1.209361, 1.804705",\
+ "0.572865, 0.755371, 0.951734, 1.260763, 1.856107",\
+ "0.739674, 0.922180, 1.118543, 1.427572, 2.022916",\
+ "1.329974, 1.512480, 1.708843, 2.017872, 2.613216",\
+ "0.576569, 0.758544, 0.954597, 1.263627, 1.858973",\
+ "0.602330, 0.784306, 0.980358, 1.289389, 1.884737",\
+ "0.653733, 0.835708, 1.031761, 1.340791, 1.936139",\
+ "0.820542, 1.002517, 1.198570, 1.507600, 2.102947",\
+ "1.410842, 1.592817, 1.788870, 2.097900, 2.693248",\
+ "0.634207, 0.816093, 1.012141, 1.320872, 1.915620",\
+ "0.659969, 0.841854, 1.037902, 1.346634, 1.941384",\
+ "0.711372, 0.893257, 1.089304, 1.398036, 1.992786",\
+ "0.878181, 1.060066, 1.256114, 1.564846, 2.159595",\
+ "1.468480, 1.650366, 1.846413, 2.155146, 2.749895",\
+ "0.936303, 1.121319, 1.315774, 1.623887, 2.217467",\
+ "0.962064, 1.147081, 1.341536, 1.649649, 2.243231",\
+ "1.013467, 1.198483, 1.392939, 1.701051, 2.294633",\
+ "1.180276, 1.365292, 1.559748, 1.867860, 2.461442",\
+ "1.770576, 1.955592, 2.150048, 2.458160, 3.051742");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\
+ "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\
+ "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\
+ "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\
+ "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524054, 1.524058");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2594*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.552582, 0.731009, 0.911269, 1.197475, 1.748592",\
+ "0.583180, 0.761606, 0.941867, 1.228073, 1.779190",\
+ "0.655008, 0.833435, 1.013695, 1.299902, 1.851019",\
+ "0.911468, 1.089894, 1.270155, 1.556361, 2.107478",\
+ "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\
+ "0.637520, 0.816281, 0.997184, 1.283396, 1.834971",\
+ "0.668118, 0.846879, 1.027782, 1.313993, 1.865568",\
+ "0.739947, 0.918707, 1.099610, 1.385822, 1.937397",\
+ "0.996406, 1.175167, 1.356070, 1.642281, 2.193856",\
+ "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\
+ "0.713426, 0.891724, 1.071993, 1.357992, 1.909143",\
+ "0.744024, 0.922322, 1.102591, 1.388590, 1.939741",\
+ "0.815853, 0.994151, 1.174419, 1.460419, 2.011569",\
+ "1.072312, 1.250610, 1.430879, 1.716878, 2.268029",\
+ "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\
+ "0.767778, 0.946236, 1.126644, 1.412532, 1.963460",\
+ "0.798376, 0.976834, 1.157242, 1.443130, 1.994058",\
+ "0.870205, 1.048662, 1.229070, 1.514959, 2.065886",\
+ "1.126664, 1.305122, 1.485530, 1.771418, 2.322346",\
+ "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\
+ "1.049200, 1.231463, 1.410595, 1.696259, 2.246738",\
+ "1.079798, 1.262061, 1.441192, 1.726856, 2.277336",\
+ "1.151627, 1.333890, 1.513021, 1.798685, 2.349164",\
+ "1.408086, 1.590349, 1.769480, 2.055144, 2.605623",\
+ "2.323924, 2.506187, 2.685318, 2.970983, 3.521462");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\
+ "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\
+ "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\
+ "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\
+ "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\
+ "2.463218, 2.463218, 2.463218, 2.463218, 2.463218");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.425553, 0.690723, 0.949925, 1.386107, 2.258472",\
+ "0.451315, 0.716485, 0.975687, 1.411869, 2.284234",\
+ "0.502717, 0.767887, 1.027089, 1.463271, 2.335637",\
+ "0.669527, 0.934696, 1.193898, 1.630080, 2.502446",\
+ "1.259826, 1.524996, 1.784198, 2.220380, 3.092745",\
+ "0.514219, 0.778798, 1.038566, 1.474336, 2.345878",\
+ "0.539981, 0.804560, 1.064327, 1.500098, 2.371639",\
+ "0.591383, 0.855962, 1.115730, 1.551500, 2.423042",\
+ "0.758192, 1.022771, 1.282539, 1.718309, 2.589851",\
+ "1.348492, 1.613071, 1.872839, 2.308609, 3.180151",\
+ "0.607026, 0.871921, 1.130291, 1.566500, 2.438920",\
+ "0.632787, 0.897683, 1.156053, 1.592262, 2.464681",\
+ "0.684190, 0.949085, 1.207455, 1.643664, 2.516083",\
+ "0.850999, 1.115894, 1.374264, 1.810474, 2.682893",\
+ "1.441299, 1.706194, 1.964564, 2.400774, 3.273192",\
+ "0.672748, 0.940455, 1.197311, 1.633351, 2.505431",\
+ "0.698510, 0.966217, 1.223073, 1.659112, 2.531192",\
+ "0.749912, 1.017619, 1.274475, 1.710515, 2.582595",\
+ "0.916721, 1.184428, 1.441284, 1.877324, 2.749404",\
+ "1.507021, 1.774728, 2.031584, 2.467624, 3.339704",\
+ "1.018538, 1.320954, 1.567941, 2.002482, 2.871564",\
+ "1.044299, 1.346715, 1.593703, 2.028244, 2.897326",\
+ "1.095702, 1.398118, 1.645105, 2.079646, 2.948728",\
+ "1.262511, 1.564927, 1.811914, 2.246455, 3.115537",\
+ "1.852811, 2.155227, 2.402214, 2.836755, 3.705837");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\
+ "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\
+ "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\
+ "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\
+ "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\
+ "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\
+ "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\
+ "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\
+ "1.524052, 1.524052, 1.524052, 1.524052, 1.524052");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2534*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.319855, 0.350453, 0.422282, 0.678742, 1.594576",\
+ "0.407246, 0.437844, 0.509673, 0.766133, 1.681967",\
+ "0.488165, 0.518763, 0.590592, 0.847052, 1.762885",\
+ "0.545906, 0.576503, 0.648333, 0.904793, 1.820624",\
+ "0.849219, 0.879552, 0.951038, 1.207499, 2.123717");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.040034, 0.086005, 0.217203, 0.715311, 2.463217",\
+ "0.040034, 0.086005, 0.217274, 0.715311, 2.463217",\
+ "0.040034, 0.086006, 0.217512, 0.715311, 2.463317",\
+ "0.040035, 0.086006, 0.217512, 0.715311, 2.463317",\
+ "0.040226, 0.086033, 0.217850, 0.715337, 2.463779");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.305437, 0.331199, 0.382601, 0.549410, 1.139710",\
+ "0.392830, 0.418591, 0.469994, 0.636803, 1.227103",\
+ "0.473699, 0.499461, 0.550863, 0.717672, 1.307972",\
+ "0.531348, 0.557110, 0.608512, 0.775321, 1.365621",\
+ "0.834004, 0.859766, 0.911168, 1.077978, 1.668277");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\
+ "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\
+ "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\
+ "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\
+ "0.040713, 0.070039, 0.145879, 0.444024, 1.524451");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.513066, 0.693179, 0.880758, 1.182738, 1.765834",\
+ "0.542527, 0.722641, 0.910219, 1.212199, 1.795295",\
+ "0.613598, 0.793711, 0.981290, 1.283270, 1.866366",\
+ "0.869826, 1.049940, 1.237518, 1.539498, 2.122594",\
+ "1.786688, 1.966801, 2.154380, 2.456360, 3.039456",\
+ "0.598004, 0.778015, 0.965828, 1.268244, 1.852212",\
+ "0.627466, 0.807477, 0.995290, 1.297706, 1.881674",\
+ "0.698536, 0.878547, 1.066360, 1.368776, 1.952744",\
+ "0.954764, 1.134775, 1.322588, 1.625004, 2.208972",\
+ "1.871626, 2.051637, 2.239450, 2.541866, 3.125834",\
+ "0.673916, 0.853459, 1.040637, 1.342841, 1.926384",\
+ "0.703378, 0.882920, 1.070099, 1.372302, 1.955846",\
+ "0.774448, 0.953991, 1.141169, 1.443373, 2.026917",\
+ "1.030676, 1.210219, 1.397397, 1.699601, 2.283145",\
+ "1.947538, 2.127081, 2.314259, 2.616463, 3.200006",\
+ "0.728285, 0.908210, 1.095526, 1.397446, 1.980702",\
+ "0.757747, 0.937672, 1.124987, 1.426908, 2.010164",\
+ "0.828817, 1.008742, 1.196058, 1.497978, 2.081234",\
+ "1.085046, 1.264970, 1.452286, 1.754207, 2.337462",\
+ "2.001907, 2.181832, 2.369148, 2.671068, 3.254324",\
+ "1.009880, 1.193775, 1.379701, 1.681172, 2.263979",\
+ "1.039342, 1.223237, 1.409163, 1.710634, 2.293441",\
+ "1.110412, 1.294307, 1.480233, 1.781705, 2.364511",\
+ "1.366640, 1.550535, 1.736461, 2.037933, 2.620739",\
+ "2.283502, 2.467397, 2.653323, 2.954794, 3.537601");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\
+ "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456797, 2.456796");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.386409, 0.654020, 0.915421, 1.355198, 2.234359",\
+ "0.410259, 0.677869, 0.939270, 1.379047, 2.258208",\
+ "0.459812, 0.727422, 0.988823, 1.428600, 2.307761",\
+ "0.625736, 0.893347, 1.154748, 1.594525, 2.473686",\
+ "1.214590, 1.482201, 1.743601, 2.183378, 3.062539",\
+ "0.475113, 0.742095, 1.004062, 1.443427, 2.321764",\
+ "0.498963, 0.765944, 1.027911, 1.467276, 2.345613",\
+ "0.548516, 0.815497, 1.077464, 1.516829, 2.395166",\
+ "0.714441, 0.981422, 1.243389, 1.682754, 2.561091",\
+ "1.303294, 1.570276, 1.832242, 2.271607, 3.149944",\
+ "0.568056, 0.835415, 1.096106, 1.535673, 2.414806",\
+ "0.591905, 0.859264, 1.119956, 1.559522, 2.438655",\
+ "0.641458, 0.908817, 1.169509, 1.609075, 2.488208",\
+ "0.807383, 1.074742, 1.335433, 1.775000, 2.654133",\
+ "1.396236, 1.663596, 1.924287, 2.363853, 3.242986",\
+ "0.633899, 0.903979, 1.163162, 1.602684, 2.481728",\
+ "0.657749, 0.927829, 1.187012, 1.626534, 2.505577",\
+ "0.707301, 0.977382, 1.236565, 1.676086, 2.555130",\
+ "0.873226, 1.143306, 1.402490, 1.842011, 2.721055",\
+ "1.462080, 1.732160, 1.991343, 2.430865, 3.309908",\
+ "0.980421, 1.284815, 1.533833, 1.971910, 2.848063",\
+ "1.004270, 1.308664, 1.557683, 1.995759, 2.871912",\
+ "1.053823, 1.358217, 1.607235, 2.045312, 2.921465",\
+ "1.219748, 1.524142, 1.773160, 2.211237, 3.087390",\
+ "1.808601, 2.112996, 2.362014, 2.800090, 3.676243");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\
+ "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\
+ "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\
+ "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\
+ "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2475*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.421174, 0.684705, 0.960825, 1.428958, 2.363963",\
+ "0.450636, 0.714167, 0.990287, 1.458419, 2.393425",\
+ "0.521706, 0.785238, 1.061357, 1.529490, 2.464495",\
+ "0.777934, 1.041466, 1.317585, 1.785718, 2.720724",\
+ "1.694796, 1.958328, 2.234447, 2.702580, 3.637585",\
+ "0.509368, 0.772246, 1.048392, 1.515673, 2.449897",\
+ "0.538830, 0.801708, 1.077854, 1.545135, 2.479358",\
+ "0.609900, 0.872778, 1.148924, 1.616205, 2.550429",\
+ "0.866129, 1.129006, 1.405152, 1.872433, 2.806657",\
+ "1.782991, 2.045868, 2.322014, 2.789295, 3.723519",\
+ "0.597685, 0.861225, 1.136357, 1.603313, 2.536852",\
+ "0.627146, 0.890687, 1.165819, 1.632775, 2.566314",\
+ "0.698217, 0.961758, 1.236889, 1.703845, 2.637384",\
+ "0.954445, 1.217986, 1.493117, 1.960074, 2.893612",\
+ "1.871307, 2.134848, 2.409979, 2.876935, 3.810474",\
+ "0.660181, 0.926859, 1.200497, 1.667402, 2.600361",\
+ "0.689642, 0.956321, 1.229958, 1.696864, 2.629822",\
+ "0.760713, 1.027391, 1.301029, 1.767934, 2.700893",\
+ "1.016941, 1.283619, 1.557257, 2.024162, 2.957121",\
+ "1.933803, 2.200481, 2.474119, 2.941024, 3.873983",\
+ "0.989306, 1.291174, 1.552361, 2.016846, 2.945817",\
+ "1.018768, 1.320636, 1.581822, 2.046308, 2.975279",\
+ "1.089838, 1.391706, 1.652893, 2.117378, 3.046349",\
+ "1.346066, 1.647934, 1.909121, 2.373606, 3.302577",\
+ "2.262928, 2.564796, 2.825983, 3.290468, 4.219439");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\
+ "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\
+ "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\
+ "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\
+ "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\
+ "2.456797, 2.456796, 2.456794, 2.456789, 2.456778");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.369364, 0.551422, 0.747656, 1.056837, 1.651321",\
+ "0.393214, 0.575271, 0.771505, 1.080686, 1.675170",\
+ "0.442767, 0.624824, 0.821058, 1.130239, 1.724723",\
+ "0.608691, 0.790749, 0.986983, 1.296166, 1.890653",\
+ "1.197545, 1.379603, 1.575836, 1.885017, 2.479500",\
+ "0.456779, 0.638740, 0.834936, 1.144142, 1.738674",\
+ "0.480629, 0.662590, 0.858786, 1.167991, 1.762524",\
+ "0.530181, 0.712143, 0.908339, 1.217544, 1.812076",\
+ "0.696106, 0.878068, 1.074264, 1.383471, 1.978007",\
+ "1.284960, 1.466921, 1.663117, 1.972322, 2.566853",\
+ "0.537655, 0.719077, 0.914963, 1.224170, 1.818706",\
+ "0.561505, 0.742927, 0.938813, 1.248020, 1.842555",\
+ "0.611058, 0.792479, 0.988366, 1.297573, 1.892108",\
+ "0.776982, 0.958404, 1.154291, 1.463499, 2.058038",\
+ "1.365836, 1.547258, 1.743144, 2.052350, 2.646885",\
+ "0.595302, 0.776914, 0.972699, 1.281641, 1.875802",\
+ "0.619151, 0.800763, 0.996549, 1.305490, 1.899651",\
+ "0.668704, 0.850316, 1.046101, 1.355043, 1.949204",\
+ "0.834629, 1.016241, 1.212026, 1.520970, 2.115134",\
+ "1.423483, 1.605095, 1.800880, 2.109821, 2.703980",\
+ "0.897509, 1.082291, 1.276362, 1.584848, 2.178120",\
+ "0.921359, 1.106141, 1.300212, 1.608697, 2.201969",\
+ "0.970912, 1.155693, 1.349765, 1.658250, 2.251522",\
+ "1.136837, 1.321618, 1.515690, 1.824177, 2.417452",\
+ "1.725690, 1.910472, 2.104543, 2.413028, 3.006299");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\
+ "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\
+ "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\
+ "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\
+ "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519042");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2397*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.417196, 0.676755, 0.948391, 1.404553, 2.315723",\
+ "0.446658, 0.706217, 0.977853, 1.434015, 2.345185",\
+ "0.517728, 0.777287, 1.048923, 1.505085, 2.416255",\
+ "0.773956, 1.033516, 1.305151, 1.761314, 2.672484",\
+ "1.690818, 1.950378, 2.222013, 2.678175, 3.589345",\
+ "0.505301, 0.764288, 1.035920, 1.491269, 2.401657",\
+ "0.534763, 0.793750, 1.065382, 1.520731, 2.431119",\
+ "0.605833, 0.864820, 1.136452, 1.591801, 2.502189",\
+ "0.862061, 1.121048, 1.392680, 1.848029, 2.758418",\
+ "1.778923, 2.037910, 2.309542, 2.764891, 3.675279",\
+ "0.593331, 0.853252, 1.123884, 1.578908, 2.488612",\
+ "0.622793, 0.882714, 1.153346, 1.608370, 2.518074",\
+ "0.693863, 0.953785, 1.224416, 1.679440, 2.589144",\
+ "0.950091, 1.210013, 1.480644, 1.935668, 2.845373",\
+ "1.866953, 2.126875, 2.397506, 2.852530, 3.762234",\
+ "0.655552, 0.918864, 1.188022, 1.642982, 2.552121",\
+ "0.685014, 0.948326, 1.217484, 1.672444, 2.581583",\
+ "0.756084, 1.019396, 1.288554, 1.743514, 2.652653",\
+ "1.012312, 1.275624, 1.544782, 1.999743, 2.908882",\
+ "1.929174, 2.192486, 2.461644, 2.916604, 3.825743",\
+ "0.982940, 1.282912, 1.539764, 1.992368, 2.897577",\
+ "1.012401, 1.312374, 1.569226, 2.021830, 2.927039",\
+ "1.083472, 1.383444, 1.640296, 2.092901, 2.998109",\
+ "1.339700, 1.639673, 1.896525, 2.349129, 3.254338",\
+ "2.256562, 2.556535, 2.813386, 3.265991, 4.171199");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\
+ "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\
+ "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\
+ "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\
+ "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\
+ "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\
+ "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\
+ "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\
+ "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\
+ "0.705638, 0.705639, 0.705641, 0.705645, 0.705653",\
+ "2.456797, 2.456795, 2.456792, 2.456783, 2.456766");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.367701, 0.549868, 0.745966, 1.055305, 1.650265",\
+ "0.391550, 0.573717, 0.769816, 1.079154, 1.674115",\
+ "0.441103, 0.623270, 0.819369, 1.128707, 1.723667",\
+ "0.607028, 0.789195, 0.985294, 1.294634, 1.889598",\
+ "1.195881, 1.378049, 1.574147, 1.883484, 2.478444",\
+ "0.455121, 0.637187, 0.833247, 1.142610, 1.737619",\
+ "0.478970, 0.661036, 0.857097, 1.166459, 1.761468",\
+ "0.528523, 0.710589, 0.906649, 1.216012, 1.811021",\
+ "0.694448, 0.876514, 1.072575, 1.381939, 1.976952",\
+ "1.283301, 1.465367, 1.661428, 1.970789, 2.565797",\
+ "0.535988, 0.717524, 0.913274, 1.222638, 1.817651",\
+ "0.559838, 0.741373, 0.937124, 1.246487, 1.841500",\
+ "0.609390, 0.790926, 0.986676, 1.296040, 1.891052",\
+ "0.775315, 0.956851, 1.152602, 1.461967, 2.056983",\
+ "1.364169, 1.545704, 1.741455, 2.050818, 2.645829",\
+ "0.593627, 0.775360, 0.971009, 1.280109, 1.874747",\
+ "0.617477, 0.799210, 0.994859, 1.303958, 1.898596",\
+ "0.667029, 0.848763, 1.044412, 1.353511, 1.948149",\
+ "0.832954, 1.014688, 1.210337, 1.519438, 2.114080",\
+ "1.421808, 1.603541, 1.799190, 2.108289, 2.702925",\
+ "0.895722, 1.080739, 1.274673, 1.583317, 2.177067",\
+ "0.919572, 1.104588, 1.298523, 1.607166, 2.200916",\
+ "0.969124, 1.154141, 1.348075, 1.656719, 2.250468",\
+ "1.135049, 1.320066, 1.514001, 1.822646, 2.416399",\
+ "1.723903, 1.908919, 2.102854, 2.411496, 3.005245");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\
+ "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\
+ "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\
+ "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\
+ "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\
+ "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\
+ "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\
+ "1.519040, 1.519040, 1.519040, 1.519041, 1.519043");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2338*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ related_output_pin : "obs_ctrl_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.509479, 0.687819, 0.868166, 1.154352, 1.705105",\
+ "0.538941, 0.717281, 0.897627, 1.183814, 1.734567",\
+ "0.610011, 0.788351, 0.968698, 1.254884, 1.805637",\
+ "0.866239, 1.044579, 1.224926, 1.511112, 2.061866",\
+ "1.783101, 1.961441, 2.141788, 2.427974, 2.978728",\
+ "0.594418, 0.772655, 0.953236, 1.239858, 1.791484",\
+ "0.623879, 0.802116, 0.982697, 1.269320, 1.820946",\
+ "0.694950, 0.873187, 1.053768, 1.340390, 1.892016",\
+ "0.951178, 1.129415, 1.309996, 1.596619, 2.148244",\
+ "1.868040, 2.046277, 2.226858, 2.513480, 3.065106",\
+ "0.670324, 0.848098, 1.028045, 1.314455, 1.865656",\
+ "0.699786, 0.877560, 1.057506, 1.343917, 1.895118",\
+ "0.770856, 0.948630, 1.128577, 1.414987, 1.966188",\
+ "1.027084, 1.204858, 1.384805, 1.671215, 2.222416",\
+ "1.943946, 2.121720, 2.301667, 2.588077, 3.139278",\
+ "0.724676, 0.902843, 1.082910, 1.369049, 1.919973",\
+ "0.754138, 0.932305, 1.112372, 1.398511, 1.949435",\
+ "0.825208, 1.003376, 1.183442, 1.469581, 2.020505",\
+ "1.081436, 1.259604, 1.439670, 1.725809, 2.276733",\
+ "1.998298, 2.176466, 2.356532, 2.642671, 3.193595",\
+ "1.006098, 1.188361, 1.367063, 1.652775, 2.203251",\
+ "1.035560, 1.217823, 1.396525, 1.682237, 2.232713",\
+ "1.106630, 1.288893, 1.467595, 1.753307, 2.303783",\
+ "1.362858, 1.545121, 1.723823, 2.009535, 2.560011",\
+ "2.279720, 2.461983, 2.640685, 2.926397, 3.476873");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\
+ "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\
+ "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\
+ "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\
+ "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\
+ "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\
+ "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\
+ "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\
+ "2.456797, 2.456797, 2.456797, 2.456796, 2.456796");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.384973, 0.649972, 0.909002, 1.345266, 2.217413",\
+ "0.408823, 0.673822, 0.932851, 1.369116, 2.241262",\
+ "0.458376, 0.723375, 0.982404, 1.418669, 2.290815",\
+ "0.624300, 0.889300, 1.148329, 1.584594, 2.456740",\
+ "1.213154, 1.478153, 1.737183, 2.173447, 3.045593",\
+ "0.473639, 0.738047, 0.997643, 1.433495, 2.304818",\
+ "0.497488, 0.761897, 1.021492, 1.457345, 2.328667",\
+ "0.547041, 0.811450, 1.071045, 1.506897, 2.378220",\
+ "0.712966, 0.977375, 1.236970, 1.672822, 2.544145",\
+ "1.301819, 1.566228, 1.825824, 2.261676, 3.132998",\
+ "0.566446, 0.831341, 1.089678, 1.525738, 2.397860",\
+ "0.590295, 0.855190, 1.113528, 1.549588, 2.421709",\
+ "0.639848, 0.904743, 1.163080, 1.599141, 2.471262",\
+ "0.805773, 1.070668, 1.329005, 1.765066, 2.637187",\
+ "1.394626, 1.659522, 1.917859, 2.353919, 3.226040",\
+ "0.632168, 0.899875, 1.156733, 1.592745, 2.464769",\
+ "0.656018, 0.923725, 1.180583, 1.616595, 2.488619",\
+ "0.705570, 0.973277, 1.230135, 1.666147, 2.538172",\
+ "0.871495, 1.139202, 1.396060, 1.832072, 2.704097",\
+ "1.460349, 1.728056, 1.984914, 2.420926, 3.292950",\
+ "0.977957, 1.280373, 1.527371, 1.961946, 2.831096",\
+ "1.001807, 1.304223, 1.551221, 1.985796, 2.854946",\
+ "1.051360, 1.353776, 1.600773, 2.035348, 2.904499",\
+ "1.217285, 1.519701, 1.766698, 2.201273, 3.070424",\
+ "1.806138, 2.108554, 2.355552, 2.790127, 3.659277");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\
+ "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\
+ "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\
+ "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\
+ "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\
+ "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\
+ "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\
+ "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\
+ "1.519040, 1.519040, 1.519040, 1.519040, 1.519040");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2281*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.137483, 0.167263, 0.238963, 0.495239, 1.411098",\
+ "0.225669, 0.255448, 0.327158, 0.583483, 1.499024",\
+ "0.313993, 0.343772, 0.415484, 0.672004, 1.587106",\
+ "0.376583, 0.406365, 0.478019, 0.734834, 1.650402",\
+ "0.706456, 0.736253, 0.807711, 1.064965, 1.982165");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\
+ "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\
+ "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\
+ "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\
+ "0.036484, 0.083490, 0.215720, 0.705638, 2.456797");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.176752, 0.200264, 0.249493, 0.415210, 1.004034",\
+ "0.264156, 0.287668, 0.336897, 0.502613, 1.091438",\
+ "0.345055, 0.368563, 0.417796, 0.583517, 1.172351",\
+ "0.402719, 0.426221, 0.475463, 0.641191, 1.230042",\
+ "0.705079, 0.728567, 0.777838, 0.943636, 1.532658");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.032905, 0.061452, 0.139114, 0.438652, 1.518506",\
+ "0.032905, 0.061452, 0.139114, 0.438651, 1.518506",\
+ "0.032905, 0.061452, 0.139114, 0.438651, 1.518304",\
+ "0.032905, 0.061452, 0.139114, 0.438651, 1.517928",\
+ "0.032905, 0.061452, 0.139114, 0.438651, 1.516755");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.078780, 0.108904, 0.180162, 0.436350, 1.354954",\
+ "0.161131, 0.191551, 0.262992, 0.519079, 1.434794",\
+ "0.248818, 0.281701, 0.353526, 0.609224, 1.527520",\
+ "0.395442, 0.436624, 0.511587, 0.767048, 1.680857",\
+ "0.628254, 0.688519, 0.779900, 1.032171, 1.943170");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.039260, 0.084846, 0.216310, 0.712907, 2.472405",\
+ "0.040828, 0.085695, 0.216652, 0.713345, 2.472405",\
+ "0.053126, 0.092383, 0.217457, 0.713345, 2.472405",\
+ "0.083384, 0.114454, 0.223298, 0.713345, 2.472405",\
+ "0.146832, 0.172946, 0.257648, 0.713345, 2.472405");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.111195, 0.136417, 0.187667, 0.354647, 0.943283",\
+ "0.190886, 0.217040, 0.268217, 0.434338, 1.024857",\
+ "0.290624, 0.318413, 0.371169, 0.537479, 1.127671",\
+ "0.459778, 0.495342, 0.553556, 0.720468, 1.308289",\
+ "0.729543, 0.783345, 0.859617, 1.032769, 1.617997");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.039937, 0.069327, 0.145375, 0.445019, 1.525316",\
+ "0.040361, 0.069327, 0.145375, 0.445019, 1.525316",\
+ "0.050876, 0.076651, 0.148151, 0.445019, 1.525316",\
+ "0.080615, 0.101623, 0.163833, 0.445639, 1.525316",\
+ "0.141343, 0.163058, 0.212463, 0.458329, 1.525316");
+ }
+
+ } /* end of arc padmux2ast_i[4]_obs_ctrl_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.074275, 0.103763, 0.175018, 0.429970, 1.346996",\
+ "0.156202, 0.185726, 0.256855, 0.512618, 1.426492",\
+ "0.240487, 0.272170, 0.343383, 0.599128, 1.515415",\
+ "0.383350, 0.422200, 0.495747, 0.749948, 1.664120",\
+ "0.607487, 0.663633, 0.751277, 1.002826, 1.912977");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.036818, 0.083430, 0.215329, 0.698468, 2.446538",\
+ "0.038327, 0.084129, 0.215329, 0.703907, 2.446538",\
+ "0.049194, 0.090132, 0.216807, 0.705668, 2.446538",\
+ "0.076596, 0.110889, 0.221927, 0.706146, 2.457507",\
+ "0.133978, 0.165656, 0.252644, 0.710730, 2.457507");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.080352, 0.102927, 0.151178, 0.316498, 0.906413",\
+ "0.165823, 0.188579, 0.236900, 0.401944, 0.996012",\
+ "0.261266, 0.287577, 0.337732, 0.502614, 1.091236",\
+ "0.421122, 0.455539, 0.512029, 0.676457, 1.262940",\
+ "0.677737, 0.731402, 0.807099, 0.979432, 1.563317");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168");
+ values ( "0.032503, 0.061295, 0.138759, 0.440292, 1.520208",\
+ "0.033685, 0.061572, 0.138902, 0.440292, 1.520208",\
+ "0.046324, 0.071119, 0.142587, 0.440292, 1.520208",\
+ "0.075437, 0.096388, 0.158394, 0.443652, 1.520208",\
+ "0.135609, 0.156947, 0.206102, 0.453960, 1.520208");
+ }
+
+ } /* end of arc padmux2ast_i[4]_obs_ctrl_o[4]_una_min*/
+
+} /* end of pin obs_ctrl_o[4] */
+
+pin("obs_ctrl_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.644672 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001495 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.055709, 0.210088, 0.384212, 0.703085, 1.340832",\
+ "0.142647, 0.298162, 0.472853, 0.791314, 1.428237",\
+ "0.229323, 0.390455, 0.564578, 0.883479, 1.521279",\
+ "0.289539, 0.457859, 0.631598, 0.950329, 1.587790",\
+ "0.602001, 0.825705, 1.001142, 1.318707, 1.953837");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.024618, 0.296918, 0.628376, 1.238420, 2.458509",\
+ "0.028418, 0.296918, 0.628376, 1.238420, 2.458509",\
+ "0.041905, 0.299457, 0.628376, 1.238420, 2.458509",\
+ "0.054019, 0.302915, 0.628376, 1.238420, 2.458509",\
+ "0.127335, 0.341609, 0.634026, 1.242336, 2.458956");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.067216, 0.173388, 0.285052, 0.487701, 0.892999",\
+ "0.152154, 0.258224, 0.370122, 0.573207, 0.979377",\
+ "0.227820, 0.333667, 0.444931, 0.647804, 1.053549",\
+ "0.281475, 0.388179, 0.499582, 0.702344, 1.107867",\
+ "0.555896, 0.671760, 0.783533, 0.986070, 1.391144");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.022975, 0.185702, 0.382816, 0.754065, 1.496563",\
+ "0.022975, 0.186685, 0.385279, 0.756173, 1.496563",\
+ "0.023515, 0.186685, 0.385279, 0.756173, 1.496563",\
+ "0.025086, 0.186685, 0.385279, 0.756173, 1.496563",\
+ "0.040851, 0.190393, 0.385279, 0.756173, 1.496563");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.055709, 0.210088, 0.384212, 0.703085, 1.340832",\
+ "0.142647, 0.298162, 0.472853, 0.791314, 1.428237",\
+ "0.229323, 0.390455, 0.564578, 0.883479, 1.521279",\
+ "0.289539, 0.457859, 0.631598, 0.950329, 1.587790",\
+ "0.602001, 0.825705, 1.001142, 1.318707, 1.953837");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.024618, 0.296396, 0.626543, 1.236834, 2.455429",\
+ "0.028418, 0.296396, 0.626543, 1.236834, 2.455429",\
+ "0.041905, 0.299457, 0.628154, 1.237245, 2.455429",\
+ "0.054019, 0.302915, 0.628337, 1.238058, 2.457501",\
+ "0.127335, 0.341609, 0.634026, 1.242336, 2.458956");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.067216, 0.173388, 0.285052, 0.487701, 0.892999",\
+ "0.152154, 0.258224, 0.370122, 0.573207, 0.979377",\
+ "0.227820, 0.333667, 0.444931, 0.647804, 1.053549",\
+ "0.281475, 0.388179, 0.499582, 0.702344, 1.107867",\
+ "0.555896, 0.671760, 0.783533, 0.986070, 1.391144");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672");
+ values ( "0.022975, 0.185506, 0.382814, 0.754047, 1.494909",\
+ "0.022975, 0.185506, 0.382814, 0.754047, 1.494909",\
+ "0.023515, 0.185506, 0.382814, 0.754047, 1.494909",\
+ "0.025086, 0.186032, 0.383438, 0.754322, 1.494909",\
+ "0.040851, 0.190393, 0.384028, 0.754322, 1.494909");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024618, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.205304, 0.155898, 0.121844, 0.108632, 0.118959",\
+ "0.213705, 0.164299, 0.130245, 0.117033, 0.127360",\
+ "0.286247, 0.236842, 0.202788, 0.189576, 0.199902",\
+ "0.377880, 0.328444, 0.294355, 0.281122, 0.291373",\
+ "0.826990, 0.777305, 0.742923, 0.729519, 0.739150");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022975, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.253248, 0.179609, 0.114078, 0.098860, 0.242765",\
+ "0.260428, 0.186789, 0.121258, 0.106040, 0.249945",\
+ "0.338311, 0.264672, 0.199141, 0.183923, 0.327828",\
+ "0.439285, 0.365564, 0.300030, 0.284860, 0.429362",\
+ "0.945572, 0.871138, 0.805582, 0.790828, 0.940493");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024618, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131653, -0.089547, -0.055448, -0.032345, 0.077315",\
+ "-0.140054, -0.097948, -0.063849, -0.040746, 0.068914",\
+ "-0.212597, -0.170490, -0.136392, -0.113288, -0.003629",\
+ "-0.304160, -0.262036, -0.227893, -0.204765, -0.095035",\
+ "-0.752635, -0.710363, -0.675857, -0.652532, -0.542218");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022975, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.160975, -0.096153, -0.041987, -0.003573, 0.191467",\
+ "-0.168149, -0.103327, -0.049161, -0.010747, 0.184293",\
+ "-0.246073, -0.181251, -0.127085, -0.088671, 0.106369",\
+ "-0.346978, -0.282082, -0.227737, -0.189269, 0.005504",\
+ "-0.852619, -0.787096, -0.731202, -0.692284, -0.499800");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_hldr*/
+
+} /* end of pin obs_ctrl_o[3] */
+
+pin("obs_ctrl_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001426 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.046598, 0.200037, 0.375695, 0.698745, 1.344843",\
+ "0.132827, 0.287212, 0.462802, 0.785460, 1.430777",\
+ "0.215641, 0.375341, 0.550758, 0.873083, 1.517732",\
+ "0.273163, 0.439738, 0.614874, 0.936996, 1.581241",\
+ "0.570794, 0.789601, 0.965263, 1.285741, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.021974, 0.297548, 0.631352, 1.248422, 2.482564",\
+ "0.026714, 0.298523, 0.633308, 1.248422, 2.482564",\
+ "0.039895, 0.300798, 0.633344, 1.248422, 2.482564",\
+ "0.051772, 0.304107, 0.633444, 1.248422, 2.482564",\
+ "0.126971, 0.342744, 0.639709, 1.250989, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.066407, 0.172211, 0.283842, 0.488142, 0.896743",\
+ "0.153827, 0.259530, 0.371123, 0.575447, 0.984097",\
+ "0.234160, 0.339867, 0.451150, 0.655476, 1.064128",\
+ "0.290795, 0.397415, 0.508694, 0.712721, 1.120776",\
+ "0.584007, 0.700750, 0.812328, 1.015736, 1.422553");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.023136, 0.186125, 0.386812, 0.759343, 1.504406",\
+ "0.023136, 0.186266, 0.387317, 0.759343, 1.504406",\
+ "0.024272, 0.186266, 0.387317, 0.759343, 1.504406",\
+ "0.026405, 0.186266, 0.387317, 0.759343, 1.504406",\
+ "0.045271, 0.190284, 0.387317, 0.759343, 1.504686");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.046598, 0.200037, 0.375695, 0.698745, 1.344843",\
+ "0.132827, 0.287212, 0.462802, 0.785460, 1.430777",\
+ "0.215641, 0.375341, 0.550758, 0.873083, 1.517732",\
+ "0.273163, 0.439738, 0.614874, 0.936996, 1.581241",\
+ "0.570794, 0.789601, 0.965263, 1.285741, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.021974, 0.297548, 0.631352, 1.247199, 2.473548",\
+ "0.026714, 0.298523, 0.633308, 1.247199, 2.473548",\
+ "0.039895, 0.300798, 0.633344, 1.247274, 2.473548",\
+ "0.051772, 0.304107, 0.633444, 1.248017, 2.473548",\
+ "0.126971, 0.342744, 0.639709, 1.250989, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.066407, 0.172211, 0.283842, 0.488142, 0.896743",\
+ "0.153827, 0.259530, 0.371123, 0.575447, 0.984097",\
+ "0.234160, 0.339867, 0.451150, 0.655476, 1.064128",\
+ "0.290795, 0.397415, 0.508694, 0.712721, 1.120776",\
+ "0.584007, 0.700750, 0.812328, 1.015736, 1.422553");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011");
+ values ( "0.023136, 0.185331, 0.385307, 0.757114, 1.500729",\
+ "0.023136, 0.185331, 0.385307, 0.757114, 1.500729",\
+ "0.024272, 0.185331, 0.385307, 0.757114, 1.500729",\
+ "0.026405, 0.185943, 0.385763, 0.758015, 1.502520",\
+ "0.045271, 0.190284, 0.385833, 0.758784, 1.504686");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.021974, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215002, 0.169073, 0.138873, 0.127530, 0.141215",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023136, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.249950, 0.174629, 0.106470, 0.083503, 0.146416",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.021974, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.146929, -0.104512, -0.070025, -0.030602, 0.275445",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023136, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163106, -0.097191, -0.039532, 0.002429, 0.223037",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_hldr*/
+
+} /* end of pin obs_ctrl_o[2] */
+
+pin("obs_ctrl_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001497 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.046791, 0.200181, 0.375803, 0.698817, 1.344843",\
+ "0.133030, 0.287356, 0.462909, 0.785532, 1.430777",\
+ "0.215892, 0.375484, 0.550866, 0.873154, 1.517732",\
+ "0.273461, 0.439881, 0.614982, 0.937068, 1.581241",\
+ "0.571381, 0.789745, 0.965369, 1.285812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.022232, 0.297820, 0.631558, 1.248559, 2.482564",\
+ "0.026946, 0.298797, 0.633513, 1.248559, 2.482564",\
+ "0.040098, 0.301070, 0.633549, 1.248559, 2.482564",\
+ "0.051979, 0.304374, 0.633649, 1.248559, 2.482564",\
+ "0.127230, 0.342977, 0.639913, 1.251125, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.066637, 0.172312, 0.283920, 0.488198, 0.896753",\
+ "0.154052, 0.259631, 0.371201, 0.575503, 0.984106",\
+ "0.234393, 0.339967, 0.451228, 0.655531, 1.064138",\
+ "0.291040, 0.397516, 0.508771, 0.712776, 1.120786",\
+ "0.584372, 0.700851, 0.812405, 1.015791, 1.422562");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.023343, 0.186306, 0.386954, 0.759444, 1.504424",\
+ "0.023343, 0.186447, 0.387459, 0.759444, 1.504424",\
+ "0.024480, 0.186447, 0.387459, 0.759444, 1.504424",\
+ "0.026601, 0.186447, 0.387459, 0.759444, 1.504424",\
+ "0.045445, 0.190459, 0.387459, 0.759444, 1.504704");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.046791, 0.200181, 0.375803, 0.698817, 1.344843",\
+ "0.133030, 0.287356, 0.462909, 0.785532, 1.430777",\
+ "0.215892, 0.375484, 0.550866, 0.873154, 1.517732",\
+ "0.273461, 0.439881, 0.614982, 0.937068, 1.581241",\
+ "0.571381, 0.789745, 0.965369, 1.285812, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.022232, 0.297820, 0.631558, 1.247336, 2.473548",\
+ "0.026946, 0.298797, 0.633513, 1.247336, 2.473548",\
+ "0.040098, 0.301070, 0.633549, 1.247411, 2.473548",\
+ "0.051979, 0.304374, 0.633649, 1.248154, 2.473548",\
+ "0.127230, 0.342977, 0.639913, 1.251125, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.066637, 0.172312, 0.283920, 0.488198, 0.896753",\
+ "0.154052, 0.259631, 0.371201, 0.575503, 0.984106",\
+ "0.234393, 0.339967, 0.451228, 0.655531, 1.064138",\
+ "0.291040, 0.397516, 0.508771, 0.712776, 1.120786",\
+ "0.584372, 0.700851, 0.812405, 1.015791, 1.422562");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011");
+ values ( "0.023343, 0.185511, 0.385448, 0.757215, 1.500747",\
+ "0.023343, 0.185511, 0.385448, 0.757215, 1.500747",\
+ "0.024480, 0.185511, 0.385448, 0.757215, 1.500747",\
+ "0.026601, 0.186123, 0.385904, 0.758116, 1.502538",\
+ "0.045445, 0.190459, 0.385975, 0.758885, 1.504704");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022232, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215122, 0.169193, 0.138993, 0.127649, 0.141334",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023343, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250044, 0.174723, 0.106564, 0.083596, 0.146510",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022232, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147049, -0.104632, -0.070145, -0.030722, 0.275326",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.023343, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163200, -0.097285, -0.039626, 0.002335, 0.222943",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_hldr*/
+
+} /* end of pin obs_ctrl_o[1] */
+
+pin("obs_ctrl_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.644672 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.001493 ;
+
+ /* Other user defined attributes. */
+ original_pin : obs_ctrl_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.055703, 0.210083, 0.384209, 0.703083, 1.340832",\
+ "0.142641, 0.298158, 0.472850, 0.791312, 1.428237",\
+ "0.229315, 0.390451, 0.564575, 0.883476, 1.521279",\
+ "0.289529, 0.457854, 0.631595, 0.950327, 1.587790",\
+ "0.601982, 0.825701, 1.001139, 1.318705, 1.953837");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.024610, 0.296910, 0.628369, 1.238416, 2.458509",\
+ "0.028411, 0.296910, 0.628369, 1.238416, 2.458509",\
+ "0.041899, 0.299449, 0.628369, 1.238416, 2.458509",\
+ "0.054012, 0.302907, 0.628369, 1.238416, 2.458509",\
+ "0.127326, 0.341602, 0.634020, 1.242332, 2.458956");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.067218, 0.173389, 0.285054, 0.487703, 0.893002",\
+ "0.152156, 0.258225, 0.370124, 0.573210, 0.979381",\
+ "0.227822, 0.333668, 0.444933, 0.647806, 1.053553",\
+ "0.281477, 0.388180, 0.499584, 0.702346, 1.107870",\
+ "0.555899, 0.671761, 0.783535, 0.986072, 1.391148");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.022977, 0.185704, 0.382820, 0.754070, 1.496570",\
+ "0.022977, 0.186687, 0.385282, 0.756178, 1.496570",\
+ "0.023517, 0.186687, 0.385282, 0.756178, 1.496570",\
+ "0.025088, 0.186687, 0.385282, 0.756178, 1.496570",\
+ "0.040853, 0.190395, 0.385282, 0.756178, 1.496570");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.055703, 0.210083, 0.384209, 0.703083, 1.340832",\
+ "0.142641, 0.298158, 0.472850, 0.791312, 1.428237",\
+ "0.229315, 0.390451, 0.564575, 0.883476, 1.521279",\
+ "0.289529, 0.457854, 0.631595, 0.950327, 1.587790",\
+ "0.601982, 0.825701, 1.001139, 1.318705, 1.953837");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.024610, 0.296388, 0.626537, 1.236829, 2.455429",\
+ "0.028411, 0.296388, 0.626537, 1.236829, 2.455429",\
+ "0.041899, 0.299449, 0.628148, 1.237241, 2.455429",\
+ "0.054012, 0.302907, 0.628330, 1.238054, 2.457501",\
+ "0.127326, 0.341602, 0.634020, 1.242332, 2.458956");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.067218, 0.173389, 0.285054, 0.487703, 0.893002",\
+ "0.152156, 0.258225, 0.370124, 0.573210, 0.979381",\
+ "0.227822, 0.333668, 0.444933, 0.647806, 1.053553",\
+ "0.281477, 0.388180, 0.499584, 0.702346, 1.107870",\
+ "0.555899, 0.671761, 0.783535, 0.986072, 1.391148");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672");
+ values ( "0.022977, 0.185508, 0.382818, 0.754052, 1.494916",\
+ "0.022977, 0.185508, 0.382818, 0.754052, 1.494916",\
+ "0.023517, 0.185508, 0.382818, 0.754052, 1.494916",\
+ "0.025088, 0.186034, 0.383442, 0.754326, 1.494916",\
+ "0.040853, 0.190395, 0.384031, 0.754326, 1.494916");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.205304, 0.155898, 0.121844, 0.108632, 0.118959",\
+ "0.213701, 0.164296, 0.130242, 0.117030, 0.127356",\
+ "0.286247, 0.236842, 0.202788, 0.189576, 0.199902",\
+ "0.377880, 0.328444, 0.294355, 0.281122, 0.291373",\
+ "0.826990, 0.777305, 0.742923, 0.729519, 0.739150");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022977, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.253248, 0.179609, 0.114078, 0.098860, 0.242765",\
+ "0.260429, 0.186790, 0.121259, 0.106041, 0.249946",\
+ "0.338311, 0.264672, 0.199141, 0.183923, 0.327828",\
+ "0.439285, 0.365564, 0.300030, 0.284860, 0.429362",\
+ "0.945572, 0.871138, 0.805582, 0.790828, 0.940493");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.131653, -0.089547, -0.055448, -0.032345, 0.077315",\
+ "-0.140051, -0.097944, -0.063846, -0.040742, 0.068917",\
+ "-0.212597, -0.170490, -0.136392, -0.113288, -0.003629",\
+ "-0.304160, -0.262036, -0.227893, -0.204765, -0.095035",\
+ "-0.752635, -0.710363, -0.675857, -0.652532, -0.542218");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.022977, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.160975, -0.096153, -0.041987, -0.003573, 0.191467",\
+ "-0.168150, -0.103328, -0.049162, -0.010747, 0.184292",\
+ "-0.246073, -0.181251, -0.127085, -0.088671, 0.106369",\
+ "-0.346978, -0.282082, -0.227737, -0.189269, 0.005504",\
+ "-0.852619, -0.787096, -0.731202, -0.692284, -0.499800");
+ }
+
+ } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_hldr*/
+
+} /* end of pin obs_ctrl_o[0] */
+} /* end of bus obs_ctrl_o */
+bus ( padmux2ast_i ) {
+
+ bus_type : BUS9_type16 ;
+ direction : input ;
+
+pin("padmux2ast_i[8]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001547 ;
+
+ /* Other user defined attributes. */
+ original_pin : padmux2ast_i[8];
+} /* end of pin padmux2ast_i[8] */
+
+pin("padmux2ast_i[7]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001037 ;
+
+ /* Other user defined attributes. */
+ original_pin : padmux2ast_i[7];
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.599931, 0.560765, 0.510135, 0.511231, 0.524547",\
+ "0.684459, 0.645293, 0.594663, 0.595759, 0.609075",\
+ "0.775549, 0.736383, 0.685753, 0.686849, 0.700165",\
+ "0.937661, 0.898495, 0.847865, 0.848961, 0.862277",\
+ "1.209352, 1.170186, 1.119556, 1.120651, 1.133968");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.507406, 0.449725, 0.394624, 0.395719, 0.409035",\
+ "0.595359, 0.537678, 0.482576, 0.483672, 0.496988",\
+ "0.695327, 0.637646, 0.582544, 0.583640, 0.596956",\
+ "0.879705, 0.822024, 0.766922, 0.768018, 0.781334",\
+ "1.197915, 1.140234, 1.085132, 1.086228, 1.099544");
+ }
+
+ } /* end of arc clk_ast_usb_i_padmux2ast_i[7]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.288273, -0.255190, -0.196555, -0.182927, -0.017307",\
+ "-0.372801, -0.339718, -0.281083, -0.267455, -0.101836",\
+ "-0.463895, -0.430812, -0.372177, -0.358549, -0.192930",\
+ "-0.625950, -0.592867, -0.534232, -0.520604, -0.354985",\
+ "-0.897654, -0.864571, -0.805936, -0.792308, -0.626688");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-0.249551, -0.198552, -0.102091, -0.083944, 0.136600",\
+ "-0.337500, -0.286501, -0.190040, -0.171892, 0.048652",\
+ "-0.437474, -0.386475, -0.290014, -0.271866, -0.051323",\
+ "-0.621823, -0.570824, -0.474363, -0.456216, -0.235672",\
+ "-0.940049, -0.889050, -0.792589, -0.774441, -0.553897");
+ }
+
+ } /* end of arc clk_ast_usb_i_padmux2ast_i[7]_hldr*/
+
+} /* end of pin padmux2ast_i[7] */
+
+pin("padmux2ast_i[6]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001036 ;
+
+ /* Other user defined attributes. */
+ original_pin : padmux2ast_i[6];
+} /* end of pin padmux2ast_i[6] */
+
+pin("padmux2ast_i[5]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001070 ;
+
+ /* Other user defined attributes. */
+ original_pin : padmux2ast_i[5];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "590008.937500, 590008.875000, 590008.812500, 590008.812500, 590008.812500",\
+ "590009.062500, 590009.000000, 590008.937500, 590008.937500, 590008.937500",\
+ "590009.062500, 590009.000000, 590008.937500, 590008.937500, 590008.937500",\
+ "590009.187500, 590009.125000, 590009.062500, 590009.062500, 590009.062500",\
+ "590009.437500, 590009.375000, 590009.312500, 590009.312500, 590009.312500");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "590007.187500, 590007.125000, 590007.062500, 590007.062500, 590007.062500",\
+ "590007.312500, 590007.250000, 590007.187500, 590007.187500, 590007.187500",\
+ "590007.437500, 590007.375000, 590007.312500, 590007.312500, 590007.312500",\
+ "590007.562500, 590007.500000, 590007.437500, 590007.437500, 590007.437500",\
+ "590007.937500, 590007.875000, 590007.812500, 590007.812500, 590007.812500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-590008.312500, -590008.250000, -590008.250000, -590008.125000, -590007.875000",\
+ "-590008.312500, -590008.250000, -590008.250000, -590008.125000, -590007.875000",\
+ "-590008.437500, -590008.375000, -590008.375000, -590008.250000, -590008.000000",\
+ "-590008.562500, -590008.500000, -590008.500000, -590008.375000, -590008.125000",\
+ "-590008.812500, -590008.750000, -590008.750000, -590008.625000, -590008.375000");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-590006.625000, -590006.562500, -590006.500000, -590006.375000, -590006.250000",\
+ "-590006.750000, -590006.687500, -590006.625000, -590006.500000, -590006.375000",\
+ "-590006.875000, -590006.812500, -590006.750000, -590006.625000, -590006.500000",\
+ "-590007.000000, -590006.937500, -590006.875000, -590006.750000, -590006.625000",\
+ "-590007.250000, -590007.187500, -590007.125000, -590007.000000, -590006.875000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_hldr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "590008.812500, 590008.750000, 590008.750000, 590008.750000, 590008.750000",\
+ "590008.937500, 590008.875000, 590008.875000, 590008.875000, 590008.875000",\
+ "590008.937500, 590008.875000, 590008.875000, 590008.875000, 590008.875000",\
+ "590009.062500, 590009.000000, 590009.000000, 590009.000000, 590009.000000",\
+ "590009.312500, 590009.250000, 590009.250000, 590009.250000, 590009.250000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "590007.312500, 590007.312500, 590007.250000, 590007.250000, 590007.312500",\
+ "590007.437500, 590007.437500, 590007.375000, 590007.375000, 590007.437500",\
+ "590007.562500, 590007.562500, 590007.500000, 590007.500000, 590007.562500",\
+ "590007.687500, 590007.687500, 590007.625000, 590007.625000, 590007.687500",\
+ "590008.062500, 590008.062500, 590008.000000, 590008.000000, 590008.062500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_recfr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-590007.250000, -590007.250000, -590007.187500, -590007.125000, -590007.000000",\
+ "-590007.250000, -590007.250000, -590007.187500, -590007.125000, -590007.000000",\
+ "-590007.375000, -590007.375000, -590007.312500, -590007.250000, -590007.125000",\
+ "-590007.500000, -590007.500000, -590007.437500, -590007.375000, -590007.250000",\
+ "-590007.750000, -590007.750000, -590007.687500, -590007.625000, -590007.500000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-590007.125000, -590007.125000, -590007.062500, -590007.000000, -590006.875000",\
+ "-590007.250000, -590007.250000, -590007.187500, -590007.125000, -590007.000000",\
+ "-590007.375000, -590007.375000, -590007.312500, -590007.250000, -590007.125000",\
+ "-590007.500000, -590007.500000, -590007.437500, -590007.375000, -590007.250000",\
+ "-590007.750000, -590007.750000, -590007.687500, -590007.625000, -590007.500000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_remfr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "590008.437500, 590008.437500, 590008.437500, 590008.500000, 590008.812500",\
+ "590008.562500, 590008.562500, 590008.562500, 590008.625000, 590008.937500",\
+ "590008.562500, 590008.562500, 590008.562500, 590008.625000, 590008.937500",\
+ "590008.687500, 590008.687500, 590008.687500, 590008.750000, 590009.062500",\
+ "590008.937500, 590008.937500, 590008.937500, 590009.000000, 590009.312500");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "590006.687500, 590006.687500, 590006.687500, 590006.687500, 590006.687500",\
+ "590006.812500, 590006.812500, 590006.812500, 590006.812500, 590006.812500",\
+ "590006.937500, 590006.937500, 590006.937500, 590006.937500, 590006.937500",\
+ "590007.062500, 590007.062500, 590007.062500, 590007.062500, 590007.062500",\
+ "590007.437500, 590007.437500, 590007.437500, 590007.437500, 590007.437500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cgsr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_falling ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "590008.250000, 590008.250000, 590008.250000, 590008.250000, 590008.250000",\
+ "590008.375000, 590008.375000, 590008.375000, 590008.375000, 590008.375000",\
+ "590008.375000, 590008.375000, 590008.375000, 590008.375000, 590008.375000",\
+ "590008.500000, 590008.500000, 590008.500000, 590008.500000, 590008.500000",\
+ "590008.750000, 590008.750000, 590008.750000, 590008.750000, 590008.750000");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "590006.562500, 590006.562500, 590006.562500, 590006.562500, 590006.562500",\
+ "590006.687500, 590006.687500, 590006.687500, 590006.687500, 590006.687500",\
+ "590006.812500, 590006.812500, 590006.812500, 590006.812500, 590006.812500",\
+ "590006.937500, 590006.937500, 590006.937500, 590006.937500, 590006.937500",\
+ "590007.312500, 590007.312500, 590007.312500, 590007.312500, 590007.312500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cgsf*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-590008.250000, -590008.250000, -590008.250000, -590008.187500, -590008.062500",\
+ "-590008.250000, -590008.250000, -590008.250000, -590008.187500, -590008.062500",\
+ "-590008.375000, -590008.375000, -590008.375000, -590008.312500, -590008.187500",\
+ "-590008.500000, -590008.500000, -590008.500000, -590008.437500, -590008.312500",\
+ "-590008.750000, -590008.750000, -590008.750000, -590008.687500, -590008.562500");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-590006.562500, -590006.562500, -590006.437500, -590006.312500, -590006.062500",\
+ "-590006.687500, -590006.687500, -590006.562500, -590006.437500, -590006.187500",\
+ "-590006.812500, -590006.812500, -590006.687500, -590006.562500, -590006.312500",\
+ "-590006.937500, -590006.937500, -590006.812500, -590006.687500, -590006.437500",\
+ "-590007.187500, -590007.187500, -590007.062500, -590006.937500, -590006.687500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cghr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_falling ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-590008.250000, -590008.250000, -590008.250000, -590008.250000, -590008.250000",\
+ "-590008.250000, -590008.250000, -590008.250000, -590008.250000, -590008.250000",\
+ "-590008.375000, -590008.375000, -590008.375000, -590008.375000, -590008.375000",\
+ "-590008.500000, -590008.500000, -590008.500000, -590008.500000, -590008.500000",\
+ "-590008.750000, -590008.750000, -590008.750000, -590008.750000, -590008.750000");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-590006.562500, -590006.562500, -590006.562500, -590006.562500, -590006.562500",\
+ "-590006.687500, -590006.687500, -590006.687500, -590006.687500, -590006.687500",\
+ "-590006.812500, -590006.812500, -590006.812500, -590006.812500, -590006.812500",\
+ "-590006.937500, -590006.937500, -590006.937500, -590006.937500, -590006.937500",\
+ "-590007.187500, -590007.187500, -590007.187500, -590007.187500, -590007.187500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cghf*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "590011.500000, 590010.062500, 590009.187500, 590008.812500, 590008.750000",\
+ "590011.625000, 590010.187500, 590009.312500, 590008.937500, 590008.875000",\
+ "590011.625000, 590010.187500, 590009.312500, 590008.937500, 590008.875000",\
+ "590011.750000, 590010.312500, 590009.437500, 590009.062500, 590009.000000",\
+ "590012.000000, 590010.562500, 590009.687500, 590009.312500, 590009.250000");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[5]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-590006.562500, -590006.437500, -590006.375000, -590006.375000, -590006.312500",\
+ "-590006.562500, -590006.437500, -590006.375000, -590006.375000, -590006.312500",\
+ "-590006.687500, -590006.562500, -590006.500000, -590006.500000, -590006.437500",\
+ "-590006.812500, -590006.687500, -590006.625000, -590006.625000, -590006.562500",\
+ "-590007.062500, -590006.937500, -590006.875000, -590006.875000, -590006.812500");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[5]_remrr*/
+
+} /* end of pin padmux2ast_i[5] */
+
+pin("padmux2ast_i[4]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001489 ;
+
+ /* Other user defined attributes. */
+ original_pin : padmux2ast_i[4];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "970007.437500, 970007.375000, 970007.312500, 970007.312500, 970007.312500",\
+ "970007.562500, 970007.500000, 970007.437500, 970007.437500, 970007.437500",\
+ "970007.562500, 970007.500000, 970007.437500, 970007.437500, 970007.437500",\
+ "970007.812500, 970007.750000, 970007.687500, 970007.687500, 970007.687500",\
+ "970008.062500, 970008.000000, 970007.937500, 970007.937500, 970007.937500");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "970010.562500, 970010.500000, 970010.437500, 970010.437500, 970010.437500",\
+ "970010.687500, 970010.625000, 970010.562500, 970010.562500, 970010.562500",\
+ "970010.812500, 970010.750000, 970010.687500, 970010.687500, 970010.687500",\
+ "970011.062500, 970011.000000, 970010.937500, 970010.937500, 970010.937500",\
+ "970011.312500, 970011.250000, 970011.187500, 970011.187500, 970011.187500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_falling ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "380000.312500, 380000.312500, 380000.312500, 380000.312500, 380000.312500",\
+ "380000.406250, 380000.406250, 380000.406250, 380000.406250, 380000.406250",\
+ "380000.500000, 380000.500000, 380000.500000, 380000.500000, 380000.500000",\
+ "380000.656250, 380000.656250, 380000.656250, 380000.656250, 380000.656250",\
+ "380000.906250, 380000.906250, 380000.906250, 380000.906250, 380000.906250");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "380001.843750, 380001.843750, 380001.843750, 380001.843750, 380001.843750",\
+ "380001.937500, 380001.937500, 380001.937500, 380001.937500, 380001.937500",\
+ "380002.062500, 380002.062500, 380002.062500, 380002.062500, 380002.062500",\
+ "380002.250000, 380002.250000, 380002.250000, 380002.250000, 380002.250000",\
+ "380002.562500, 380002.562500, 380002.562500, 380002.562500, 380002.562500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_stupf*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380000.375000, -380000.312500, -380000.281250, -380000.187500, -379999.906250",\
+ "-380000.468750, -380000.406250, -380000.375000, -380000.281250, -380000.000000",\
+ "-380000.531250, -380000.468750, -380000.437500, -380000.343750, -380000.062500",\
+ "-380000.687500, -380000.625000, -380000.593750, -380000.500000, -380000.218750",\
+ "-380000.906250, -380000.843750, -380000.812500, -380000.718750, -380000.437500");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380001.750000, -380001.687500, -380001.656250, -380001.562500, -380001.375000",\
+ "-380001.843750, -380001.781250, -380001.750000, -380001.656250, -380001.468750",\
+ "-380001.937500, -380001.875000, -380001.843750, -380001.750000, -380001.562500",\
+ "-380002.125000, -380002.062500, -380002.031250, -380001.937500, -380001.750000",\
+ "-380002.375000, -380002.312500, -380002.281250, -380002.187500, -380002.000000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_hldr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_falling ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380000.281250, -380000.281250, -380000.281250, -380000.281250, -380000.281250",\
+ "-380000.375000, -380000.375000, -380000.375000, -380000.375000, -380000.375000",\
+ "-380000.437500, -380000.437500, -380000.437500, -380000.437500, -380000.437500",\
+ "-380000.593750, -380000.593750, -380000.593750, -380000.593750, -380000.593750",\
+ "-380000.812500, -380000.812500, -380000.812500, -380000.812500, -380000.812500");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380001.750000, -380001.750000, -380001.750000, -380001.750000, -380001.750000",\
+ "-380001.843750, -380001.843750, -380001.843750, -380001.843750, -380001.843750",\
+ "-380001.937500, -380001.937500, -380001.937500, -380001.937500, -380001.937500",\
+ "-380002.125000, -380002.125000, -380002.125000, -380002.125000, -380002.125000",\
+ "-380002.375000, -380002.375000, -380002.375000, -380002.375000, -380002.375000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_hldf*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "970007.625000, 970007.562500, 970007.500000, 970007.500000, 970007.562500",\
+ "970007.750000, 970007.687500, 970007.625000, 970007.625000, 970007.687500",\
+ "970007.750000, 970007.687500, 970007.625000, 970007.625000, 970007.687500",\
+ "970008.000000, 970007.937500, 970007.875000, 970007.875000, 970007.937500",\
+ "970008.250000, 970008.187500, 970008.125000, 970008.125000, 970008.187500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "970010.437500, 970010.375000, 970010.375000, 970010.375000, 970010.375000",\
+ "970010.562500, 970010.500000, 970010.500000, 970010.500000, 970010.500000",\
+ "970010.687500, 970010.625000, 970010.625000, 970010.625000, 970010.625000",\
+ "970010.937500, 970010.875000, 970010.875000, 970010.875000, 970010.875000",\
+ "970011.187500, 970011.125000, 970011.125000, 970011.125000, 970011.125000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recfr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_falling ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "380000.500000, 380000.500000, 380000.500000, 380000.500000, 380000.500000",\
+ "380000.593750, 380000.593750, 380000.593750, 380000.593750, 380000.593750",\
+ "380000.687500, 380000.687500, 380000.687500, 380000.687500, 380000.687500",\
+ "380000.843750, 380000.843750, 380000.843750, 380000.843750, 380000.843750",\
+ "380001.093750, 380001.093750, 380001.093750, 380001.093750, 380001.093750");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recrf*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_falling ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "380001.937500, 380001.937500, 380001.937500, 380001.937500, 380001.937500",\
+ "380002.031250, 380002.031250, 380002.031250, 380002.031250, 380002.031250",\
+ "380002.156250, 380002.156250, 380002.156250, 380002.156250, 380002.156250",\
+ "380002.343750, 380002.343750, 380002.343750, 380002.343750, 380002.343750",\
+ "380002.656250, 380002.656250, 380002.656250, 380002.656250, 380002.656250");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recff*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380000.375000, -380000.343750, -380000.281250, -380000.250000, -380000.125000",\
+ "-380000.468750, -380000.437500, -380000.375000, -380000.343750, -380000.218750",\
+ "-380000.531250, -380000.500000, -380000.437500, -380000.406250, -380000.281250",\
+ "-380000.687500, -380000.656250, -380000.593750, -380000.562500, -380000.437500",\
+ "-380000.906250, -380000.875000, -380000.812500, -380000.781250, -380000.656250");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380001.812500, -380001.781250, -380001.718750, -380001.687500, -380001.593750",\
+ "-380001.906250, -380001.875000, -380001.812500, -380001.781250, -380001.687500",\
+ "-380002.000000, -380001.968750, -380001.906250, -380001.875000, -380001.781250",\
+ "-380002.187500, -380002.156250, -380002.093750, -380002.062500, -380001.968750",\
+ "-380002.437500, -380002.406250, -380002.343750, -380002.312500, -380002.218750");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remfr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_falling ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380000.312500, -380000.312500, -380000.312500, -380000.312500, -380000.312500",\
+ "-380000.406250, -380000.406250, -380000.406250, -380000.406250, -380000.406250",\
+ "-380000.468750, -380000.468750, -380000.468750, -380000.468750, -380000.468750",\
+ "-380000.625000, -380000.625000, -380000.625000, -380000.625000, -380000.625000",\
+ "-380000.843750, -380000.843750, -380000.843750, -380000.843750, -380000.843750");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remrf*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_falling ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380001.750000, -380001.750000, -380001.750000, -380001.750000, -380001.750000",\
+ "-380001.843750, -380001.843750, -380001.843750, -380001.843750, -380001.843750",\
+ "-380001.937500, -380001.937500, -380001.937500, -380001.937500, -380001.937500",\
+ "-380002.125000, -380002.125000, -380002.125000, -380002.125000, -380002.125000",\
+ "-380002.375000, -380002.375000, -380002.375000, -380002.375000, -380002.375000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remff*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "970006.937500, 970006.937500, 970006.937500, 970006.937500, 970006.937500",\
+ "970007.062500, 970007.062500, 970007.062500, 970007.062500, 970007.062500",\
+ "970007.062500, 970007.062500, 970007.062500, 970007.062500, 970007.062500",\
+ "970007.312500, 970007.312500, 970007.312500, 970007.312500, 970007.312500",\
+ "970007.562500, 970007.562500, 970007.562500, 970007.562500, 970007.562500");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "970010.062500, 970010.062500, 970010.062500, 970010.125000, 970010.437500",\
+ "970010.187500, 970010.187500, 970010.187500, 970010.250000, 970010.562500",\
+ "970010.312500, 970010.312500, 970010.312500, 970010.375000, 970010.687500",\
+ "970010.562500, 970010.562500, 970010.562500, 970010.625000, 970010.937500",\
+ "970010.812500, 970010.812500, 970010.812500, 970010.875000, 970011.187500");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cgsr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_falling ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "970006.812500, 970006.812500, 970006.812500, 970006.812500, 970006.812500",\
+ "970006.937500, 970006.937500, 970006.937500, 970006.937500, 970006.937500",\
+ "970006.937500, 970006.937500, 970006.937500, 970006.937500, 970006.937500",\
+ "970007.187500, 970007.187500, 970007.187500, 970007.187500, 970007.187500",\
+ "970007.437500, 970007.437500, 970007.437500, 970007.437500, 970007.437500");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "970009.875000, 970009.875000, 970009.875000, 970009.875000, 970009.875000",\
+ "970010.000000, 970010.000000, 970010.000000, 970010.000000, 970010.000000",\
+ "970010.125000, 970010.125000, 970010.125000, 970010.125000, 970010.125000",\
+ "970010.375000, 970010.375000, 970010.375000, 970010.375000, 970010.375000",\
+ "970010.625000, 970010.625000, 970010.625000, 970010.625000, 970010.625000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cgsf*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380000.281250, -380000.218750, -380000.187500, -380000.125000, -380000.000000",\
+ "-380000.375000, -380000.312500, -380000.281250, -380000.218750, -380000.093750",\
+ "-380000.437500, -380000.375000, -380000.343750, -380000.281250, -380000.156250",\
+ "-380000.593750, -380000.531250, -380000.500000, -380000.437500, -380000.312500",\
+ "-380000.812500, -380000.750000, -380000.718750, -380000.656250, -380000.531250");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380001.718750, -380001.625000, -380001.531250, -380001.406250, -380001.125000",\
+ "-380001.812500, -380001.718750, -380001.625000, -380001.500000, -380001.218750",\
+ "-380001.906250, -380001.812500, -380001.718750, -380001.593750, -380001.312500",\
+ "-380002.093750, -380002.000000, -380001.906250, -380001.781250, -380001.500000",\
+ "-380002.343750, -380002.250000, -380002.156250, -380002.031250, -380001.750000");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cghr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_falling ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380000.312500, -380000.312500, -380000.312500, -380000.312500, -380000.312500",\
+ "-380000.406250, -380000.406250, -380000.406250, -380000.406250, -380000.406250",\
+ "-380000.468750, -380000.468750, -380000.468750, -380000.468750, -380000.468750",\
+ "-380000.625000, -380000.625000, -380000.625000, -380000.625000, -380000.625000",\
+ "-380000.843750, -380000.843750, -380000.843750, -380000.843750, -380000.843750");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380001.718750, -380001.718750, -380001.718750, -380001.718750, -380001.718750",\
+ "-380001.812500, -380001.812500, -380001.812500, -380001.812500, -380001.812500",\
+ "-380001.906250, -380001.906250, -380001.906250, -380001.906250, -380001.906250",\
+ "-380002.093750, -380002.093750, -380002.093750, -380002.093750, -380002.093750",\
+ "-380002.343750, -380002.343750, -380002.343750, -380002.343750, -380002.343750");
+ }
+
+ } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cghf*/
+
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "380000.500000, 380000.468750, 380000.406250, 380000.406250, 380000.468750",\
+ "380000.593750, 380000.562500, 380000.500000, 380000.500000, 380000.562500",\
+ "380000.687500, 380000.656250, 380000.593750, 380000.593750, 380000.656250",\
+ "380000.843750, 380000.812500, 380000.750000, 380000.750000, 380000.812500",\
+ "380001.093750, 380001.062500, 380001.000000, 380001.000000, 380001.062500");
+ }
+
+ } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : recovery_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "380001.968750, 380001.937500, 380001.875000, 380001.875000, 380001.937500",\
+ "380002.062500, 380002.031250, 380001.968750, 380001.968750, 380002.031250",\
+ "380002.187500, 380002.156250, 380002.093750, 380002.093750, 380002.156250",\
+ "380002.375000, 380002.343750, 380002.281250, 380002.281250, 380002.343750",\
+ "380002.687500, 380002.656250, 380002.593750, 380002.593750, 380002.656250");
+ }
+
+ } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_recfr*/
+
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-380000.343750, -380000.312500, -380000.250000, -380000.218750, -380000.093750",\
+ "-380000.437500, -380000.406250, -380000.343750, -380000.312500, -380000.187500",\
+ "-380000.500000, -380000.468750, -380000.406250, -380000.375000, -380000.250000",\
+ "-380000.656250, -380000.625000, -380000.562500, -380000.531250, -380000.406250",\
+ "-380000.875000, -380000.843750, -380000.781250, -380000.750000, -380000.625000");
+ }
+
+ } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ timing_type : removal_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-380001.812500, -380001.781250, -380001.718750, -380001.687500, -380001.562500",\
+ "-380001.906250, -380001.875000, -380001.812500, -380001.781250, -380001.656250",\
+ "-380002.000000, -380001.968750, -380001.906250, -380001.875000, -380001.750000",\
+ "-380002.187500, -380002.156250, -380002.093750, -380002.062500, -380001.937500",\
+ "-380002.437500, -380002.406250, -380002.343750, -380002.312500, -380002.187500");
+ }
+
+ } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_remfr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "380000.843750, 380000.750000, 380000.687500, 380000.687500, 380000.656250",\
+ "380000.937500, 380000.843750, 380000.781250, 380000.781250, 380000.750000",\
+ "380001.031250, 380000.937500, 380000.875000, 380000.875000, 380000.843750",\
+ "380001.187500, 380001.093750, 380001.031250, 380001.031250, 380001.000000",\
+ "380001.437500, 380001.343750, 380001.281250, 380001.281250, 380001.250000");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "380002.312500, 380002.218750, 380002.250000, 380002.343750, 380002.750000",\
+ "380002.406250, 380002.312500, 380002.343750, 380002.437500, 380002.843750",\
+ "380002.531250, 380002.437500, 380002.468750, 380002.562500, 380002.968750",\
+ "380002.718750, 380002.625000, 380002.656250, 380002.750000, 380003.156250",\
+ "380003.031250, 380002.937500, 380002.968750, 380003.062500, 380003.468750");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-380000.312500, -380000.281250, -380000.250000, -380000.218750, -380000.093750",\
+ "-380000.406250, -380000.375000, -380000.343750, -380000.312500, -380000.187500",\
+ "-380000.468750, -380000.437500, -380000.406250, -380000.375000, -380000.250000",\
+ "-380000.625000, -380000.593750, -380000.562500, -380000.531250, -380000.406250",\
+ "-380000.843750, -380000.812500, -380000.781250, -380000.750000, -380000.625000");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-380001.781250, -380001.718750, -380001.656250, -380001.593750, -380001.375000",\
+ "-380001.875000, -380001.812500, -380001.750000, -380001.687500, -380001.468750",\
+ "-380001.968750, -380001.906250, -380001.843750, -380001.781250, -380001.562500",\
+ "-380002.156250, -380002.093750, -380002.031250, -380001.968750, -380001.750000",\
+ "-380002.406250, -380002.343750, -380002.281250, -380002.218750, -380002.000000");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_hldr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "380011.406250, 380010.000000, 380009.125000, 380008.718750, 380008.656250",\
+ "380011.500000, 380010.093750, 380009.218750, 380008.812500, 380008.750000",\
+ "380011.593750, 380010.187500, 380009.312500, 380008.906250, 380008.843750",\
+ "380011.750000, 380010.343750, 380009.468750, 380009.062500, 380009.000000",\
+ "380012.000000, 380010.593750, 380009.718750, 380009.312500, 380009.250000");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : recovery_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "970013.125000, 970011.687500, 970010.875000, 970010.437500, 970010.375000",\
+ "970013.250000, 970011.812500, 970011.000000, 970010.562500, 970010.500000",\
+ "970013.375000, 970011.937500, 970011.125000, 970010.687500, 970010.625000",\
+ "970013.625000, 970012.187500, 970011.375000, 970010.937500, 970010.875000",\
+ "970013.875000, 970012.437500, 970011.625000, 970011.187500, 970011.125000");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_recfr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-380000.343750, -380000.312500, -380000.250000, -380000.187500, -379999.843750",\
+ "-380000.437500, -380000.406250, -380000.343750, -380000.281250, -379999.937500",\
+ "-380000.500000, -380000.468750, -380000.406250, -380000.343750, -380000.000000",\
+ "-380000.656250, -380000.625000, -380000.562500, -380000.500000, -380000.156250",\
+ "-380000.875000, -380000.843750, -380000.781250, -380000.718750, -380000.375000");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : removal_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-380001.812500, -380001.781250, -380001.687500, -380001.625000, -380001.281250",\
+ "-380001.906250, -380001.875000, -380001.781250, -380001.718750, -380001.375000",\
+ "-380002.000000, -380001.968750, -380001.875000, -380001.812500, -380001.468750",\
+ "-380002.187500, -380002.156250, -380002.062500, -380002.000000, -380001.656250",\
+ "-380002.437500, -380002.406250, -380002.312500, -380002.250000, -380001.906250");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_remfr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "380001.343750, 380001.343750, 380001.343750, 380001.343750, 380001.343750",\
+ "380001.437500, 380001.437500, 380001.437500, 380001.437500, 380001.437500",\
+ "380001.531250, 380001.531250, 380001.531250, 380001.531250, 380001.531250",\
+ "380001.687500, 380001.687500, 380001.687500, 380001.687500, 380001.687500",\
+ "380001.937500, 380001.937500, 380001.937500, 380001.937500, 380001.937500");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "380003.062500, 380003.062500, 380003.062500, 380003.062500, 380003.062500",\
+ "380003.156250, 380003.156250, 380003.156250, 380003.156250, 380003.156250",\
+ "380003.281250, 380003.281250, 380003.281250, 380003.281250, 380003.281250",\
+ "380003.468750, 380003.468750, 380003.468750, 380003.468750, 380003.468750",\
+ "380003.781250, 380003.781250, 380003.781250, 380003.781250, 380003.781250");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_cgsr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_falling ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380001.343750, -380001.343750, -380001.343750, -380001.343750, -380001.343750",\
+ "-380001.437500, -380001.437500, -380001.437500, -380001.437500, -380001.437500",\
+ "-380001.500000, -380001.500000, -380001.500000, -380001.500000, -380001.500000",\
+ "-380001.656250, -380001.656250, -380001.656250, -380001.656250, -380001.656250",\
+ "-380001.875000, -380001.875000, -380001.875000, -380001.875000, -380001.875000");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-380003.062500, -380003.062500, -380003.062500, -380003.062500, -380003.062500",\
+ "-380003.156250, -380003.156250, -380003.156250, -380003.156250, -380003.156250",\
+ "-380003.250000, -380003.250000, -380003.250000, -380003.250000, -380003.250000",\
+ "-380003.437500, -380003.437500, -380003.437500, -380003.437500, -380003.437500",\
+ "-380003.687500, -380003.687500, -380003.687500, -380003.687500, -380003.687500");
+ }
+
+ } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_cghf*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "380002.218750, 380002.156250, 380002.125000, 380002.125000, 380002.125000",\
+ "380002.312500, 380002.250000, 380002.218750, 380002.218750, 380002.218750",\
+ "380002.406250, 380002.343750, 380002.312500, 380002.312500, 380002.312500",\
+ "380002.562500, 380002.500000, 380002.468750, 380002.468750, 380002.468750",\
+ "380002.812500, 380002.750000, 380002.718750, 380002.718750, 380002.718750");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "380004.218750, 380004.156250, 380004.125000, 380004.125000, 380004.125000",\
+ "380004.312500, 380004.250000, 380004.218750, 380004.218750, 380004.218750",\
+ "380004.437500, 380004.375000, 380004.343750, 380004.343750, 380004.343750",\
+ "380004.625000, 380004.562500, 380004.531250, 380004.531250, 380004.531250",\
+ "380004.937500, 380004.875000, 380004.843750, 380004.843750, 380004.843750");
+ }
+
+ } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-380001.781250, -380001.718750, -380001.625000, -380001.593750, -380001.375000",\
+ "-380001.875000, -380001.812500, -380001.718750, -380001.687500, -380001.468750",\
+ "-380001.937500, -380001.875000, -380001.781250, -380001.750000, -380001.531250",\
+ "-380002.093750, -380002.031250, -380001.937500, -380001.906250, -380001.687500",\
+ "-380002.312500, -380002.250000, -380002.156250, -380002.125000, -380001.906250");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-380003.906250, -380003.843750, -380003.750000, -380003.718750, -380003.500000",\
+ "-380004.000000, -380003.937500, -380003.843750, -380003.812500, -380003.593750",\
+ "-380004.093750, -380004.031250, -380003.937500, -380003.906250, -380003.687500",\
+ "-380004.281250, -380004.218750, -380004.125000, -380004.093750, -380003.875000",\
+ "-380004.531250, -380004.468750, -380004.375000, -380004.343750, -380004.125000");
+ }
+
+ } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_hldr*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "380000.593750, 380000.562500, 380000.500000, 380000.500000, 380000.562500",\
+ "380000.687500, 380000.656250, 380000.593750, 380000.593750, 380000.656250",\
+ "380000.781250, 380000.750000, 380000.687500, 380000.687500, 380000.750000",\
+ "380000.937500, 380000.906250, 380000.843750, 380000.843750, 380000.906250",\
+ "380001.187500, 380001.156250, 380001.093750, 380001.093750, 380001.156250");
+ }
+
+ } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : recovery_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "380002.031250, 380002.000000, 380001.937500, 380001.937500, 380002.000000",\
+ "380002.125000, 380002.093750, 380002.031250, 380002.031250, 380002.093750",\
+ "380002.250000, 380002.218750, 380002.156250, 380002.156250, 380002.218750",\
+ "380002.437500, 380002.406250, 380002.343750, 380002.343750, 380002.406250",\
+ "380002.750000, 380002.718750, 380002.656250, 380002.656250, 380002.718750");
+ }
+
+ } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_recfr*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-380000.437500, -380000.406250, -380000.343750, -380000.312500, -380000.187500",\
+ "-380000.531250, -380000.500000, -380000.437500, -380000.406250, -380000.281250",\
+ "-380000.593750, -380000.562500, -380000.500000, -380000.468750, -380000.343750",\
+ "-380000.750000, -380000.718750, -380000.656250, -380000.625000, -380000.500000",\
+ "-380000.968750, -380000.937500, -380000.875000, -380000.843750, -380000.718750");
+ }
+
+ } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_usb_i" ;
+ timing_type : removal_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-380001.875000, -380001.843750, -380001.781250, -380001.750000, -380001.625000",\
+ "-380001.968750, -380001.937500, -380001.875000, -380001.843750, -380001.718750",\
+ "-380002.062500, -380002.031250, -380001.968750, -380001.937500, -380001.812500",\
+ "-380002.250000, -380002.218750, -380002.156250, -380002.125000, -380002.000000",\
+ "-380002.500000, -380002.468750, -380002.406250, -380002.375000, -380002.250000");
+ }
+
+ } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_remfr*/
+
+} /* end of pin padmux2ast_i[4] */
+
+pin("padmux2ast_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001527 ;
+
+ /* Other user defined attributes. */
+ original_pin : padmux2ast_i[3];
+} /* end of pin padmux2ast_i[3] */
+
+pin("padmux2ast_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001451 ;
+
+ /* Other user defined attributes. */
+ original_pin : padmux2ast_i[2];
+} /* end of pin padmux2ast_i[2] */
+
+pin("padmux2ast_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.002579 ;
+
+ /* Other user defined attributes. */
+ original_pin : padmux2ast_i[1];
+} /* end of pin padmux2ast_i[1] */
+
+pin("padmux2ast_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001032 ;
+
+ /* Other user defined attributes. */
+ original_pin : padmux2ast_i[0];
+} /* end of pin padmux2ast_i[0] */
+} /* end of bus padmux2ast_i */
+bus ( ast2padmux_o ) {
+
+ bus_type : BUS9_type16 ;
+ direction : output ;
+
+pin("ast2padmux_o[8]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.159377 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2padmux_o[8];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380004.343750, 380004.375000, 380004.437500, 380004.718750, 380005.625000",\
+ "380004.437500, 380004.468750, 380004.531250, 380004.812500, 380005.718750",\
+ "380004.531250, 380004.562500, 380004.625000, 380004.906250, 380005.812500",\
+ "380004.593750, 380004.625000, 380004.687500, 380004.968750, 380005.875000",\
+ "380004.937500, 380004.968750, 380005.031250, 380005.312500, 380006.218750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380002.437500, 380002.468750, 380002.531250, 380002.687500, 380003.281250",\
+ "380002.531250, 380002.562500, 380002.625000, 380002.781250, 380003.375000",\
+ "380002.593750, 380002.625000, 380002.687500, 380002.843750, 380003.437500",\
+ "380002.656250, 380002.687500, 380002.750000, 380002.906250, 380003.500000",\
+ "380003.000000, 380003.031250, 380003.093750, 380003.250000, 380003.843750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027375, 0.057503, 0.133586, 0.436974, 1.549209");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.198420, 0.230953, 0.301455, 0.556384, 1.484645",\
+ "0.286701, 0.319234, 0.389735, 0.644664, 1.572926",\
+ "0.375268, 0.407801, 0.478303, 0.733232, 1.661493",\
+ "0.437972, 0.470506, 0.541007, 0.795935, 1.724196",\
+ "0.757115, 0.789659, 0.860255, 1.115081, 2.043332");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\
+ "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\
+ "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\
+ "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\
+ "0.020935, 0.066607, 0.198712, 0.685847, 2.460401");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.211851, 0.238498, 0.286799, 0.453464, 1.060488",\
+ "0.299253, 0.325901, 0.374202, 0.540867, 1.147891",\
+ "0.380126, 0.406773, 0.455075, 0.621740, 1.228763",\
+ "0.437748, 0.464395, 0.512697, 0.679362, 1.286385",\
+ "0.739921, 0.766569, 0.814870, 0.981535, 1.588558");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\
+ "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\
+ "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\
+ "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\
+ "0.020406, 0.050336, 0.128964, 0.434733, 1.544003");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.408924, 0.441470, 0.512070, 0.766936, 1.695386",\
+ "0.493120, 0.525666, 0.596266, 0.851132, 1.779583",\
+ "0.583441, 0.615988, 0.686587, 0.941453, 1.869904",\
+ "0.653401, 0.685947, 0.756547, 1.011413, 1.939865",\
+ "1.044013, 1.076560, 1.147159, 1.402024, 2.330486");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.020948, 0.066625, 0.198722, 0.685958, 2.464075",\
+ "0.020948, 0.066625, 0.198722, 0.685958, 2.464075",\
+ "0.020948, 0.066625, 0.198722, 0.685958, 2.464075",\
+ "0.020948, 0.066625, 0.198723, 0.685958, 2.464075",\
+ "0.020946, 0.066625, 0.198725, 0.685957, 2.464076");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.438271, 0.469168, 0.519837, 0.687755, 1.292925",\
+ "0.526383, 0.557280, 0.607949, 0.775866, 1.381036",\
+ "0.628083, 0.658980, 0.709649, 0.877567, 1.482737",\
+ "0.819336, 0.850238, 0.900907, 1.068829, 1.674009",\
+ "1.156747, 1.187659, 1.238328, 1.406259, 2.011461");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.027368, 0.057498, 0.133582, 0.436963, 1.549160",\
+ "0.027368, 0.057498, 0.133582, 0.436963, 1.549160",\
+ "0.027368, 0.057498, 0.133582, 0.436963, 1.549160",\
+ "0.027371, 0.057501, 0.133584, 0.436969, 1.549186",\
+ "0.027379, 0.057507, 0.133588, 0.436980, 1.549240");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.398110, 0.430656, 0.501253, 0.756075, 1.684372",\
+ "0.482288, 0.514834, 0.585431, 0.840253, 1.768550",\
+ "0.572606, 0.605152, 0.675749, 0.930571, 1.858868",\
+ "0.642450, 0.674996, 0.745593, 1.000414, 1.928712",\
+ "1.032124, 1.064670, 1.135267, 1.390089, 2.318387");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.463750");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.427883, 0.458770, 0.509441, 0.677352, 1.282498",\
+ "0.516006, 0.546892, 0.597564, 0.765475, 1.370620",\
+ "0.617659, 0.648546, 0.699217, 0.867128, 1.472274",\
+ "0.808079, 0.838969, 0.889641, 1.057554, 1.662708",\
+ "1.144522, 1.175420, 1.226092, 1.394011, 1.999181");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.027342, 0.057489, 0.133570, 0.436937, 1.549078",\
+ "0.027342, 0.057489, 0.133570, 0.436937, 1.549078",\
+ "0.027342, 0.057489, 0.133570, 0.436937, 1.549078",\
+ "0.027344, 0.057490, 0.133572, 0.436941, 1.549096",\
+ "0.027347, 0.057494, 0.133575, 0.436950, 1.549136");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380000.718750, 380000.750000, 380000.812500, 380001.093750, 380002.000000",\
+ "380000.812500, 380000.843750, 380000.906250, 380001.187500, 380002.093750",\
+ "380000.906250, 380000.937500, 380001.000000, 380001.281250, 380002.187500",\
+ "380001.062500, 380001.093750, 380001.156250, 380001.437500, 380002.343750",\
+ "380001.312500, 380001.343750, 380001.406250, 380001.687500, 380002.593750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380002.125000, 380002.156250, 380002.218750, 380002.375000, 380002.968750",\
+ "380002.218750, 380002.250000, 380002.312500, 380002.468750, 380003.062500",\
+ "380002.343750, 380002.375000, 380002.437500, 380002.593750, 380003.187500",\
+ "380002.531250, 380002.562500, 380002.625000, 380002.781250, 380003.375000",\
+ "380002.843750, 380002.875000, 380002.937500, 380003.093750, 380003.687500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380000.687500, 380000.718750, 380000.781250, 380001.062500, 380001.968750",\
+ "380000.781250, 380000.812500, 380000.875000, 380001.156250, 380002.062500",\
+ "380000.843750, 380000.875000, 380000.937500, 380001.218750, 380002.125000",\
+ "380001.000000, 380001.031250, 380001.093750, 380001.375000, 380002.281250",\
+ "380001.218750, 380001.250000, 380001.312500, 380001.593750, 380002.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.460022");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380002.125000, 380002.156250, 380002.187500, 380002.375000, 380002.968750",\
+ "380002.218750, 380002.250000, 380002.281250, 380002.468750, 380003.062500",\
+ "380002.312500, 380002.343750, 380002.375000, 380002.562500, 380003.156250",\
+ "380002.500000, 380002.531250, 380002.562500, 380002.750000, 380003.343750",\
+ "380002.750000, 380002.781250, 380002.812500, 380003.000000, 380003.593750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\
+ "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\
+ "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\
+ "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\
+ "0.020492, 0.050440, 0.128935, 0.434235, 1.546080");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380002.312500, 380002.343750, 380002.406250, 380002.562500, 380003.156250",\
+ "380002.406250, 380002.437500, 380002.500000, 380002.656250, 380003.250000",\
+ "380002.500000, 380002.531250, 380002.593750, 380002.750000, 380003.343750",\
+ "380002.656250, 380002.687500, 380002.750000, 380002.906250, 380003.500000",\
+ "380002.906250, 380002.937500, 380003.000000, 380003.156250, 380003.750000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\
+ "0.027368, 0.057498, 0.133582, 0.436964, 1.549163");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380004.250000, 380004.281250, 380004.343750, 380004.625000, 380005.531250",\
+ "380004.343750, 380004.375000, 380004.437500, 380004.718750, 380005.625000",\
+ "380004.468750, 380004.500000, 380004.562500, 380004.843750, 380005.750000",\
+ "380004.656250, 380004.687500, 380004.750000, 380005.031250, 380005.937500",\
+ "380004.968750, 380005.000000, 380005.062500, 380005.343750, 380006.250000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\
+ "0.021241, 0.066861, 0.199049, 0.687205, 2.464075");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380000.687500, 380000.718750, 380000.750000, 380000.937500, 380001.531250",\
+ "380000.781250, 380000.812500, 380000.843750, 380001.031250, 380001.625000",\
+ "380000.843750, 380000.875000, 380000.906250, 380001.093750, 380001.687500",\
+ "380001.000000, 380001.031250, 380001.062500, 380001.250000, 380001.843750",\
+ "380001.218750, 380001.250000, 380001.281250, 380001.468750, 380002.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\
+ "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\
+ "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\
+ "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\
+ "0.020492, 0.050440, 0.128935, 0.434235, 1.546080");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "380002.062500, 380002.093750, 380002.156250, 380002.437500, 380003.343750",\
+ "380002.156250, 380002.187500, 380002.250000, 380002.531250, 380003.437500",\
+ "380002.250000, 380002.281250, 380002.343750, 380002.625000, 380003.531250",\
+ "380002.437500, 380002.468750, 380002.531250, 380002.812500, 380003.718750",\
+ "380002.687500, 380002.718750, 380002.781250, 380003.062500, 380003.968750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377");
+ values ( "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\
+ "0.020932, 0.066607, 0.198719, 0.685843, 2.460022");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_inv_min*/
+
+} /* end of pin ast2padmux_o[8] */
+
+pin("ast2padmux_o[7]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.028584 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2padmux_o[7];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\
+ "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\
+ "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\
+ "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\
+ "0.073824, 0.189425, 0.393252, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\
+ "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\
+ "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[7]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\
+ "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\
+ "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\
+ "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\
+ "0.643636, 0.699058, 0.793671, 1.054205, 1.742813");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\
+ "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\
+ "0.054820, 0.149920, 0.315966, 0.770514, 1.988361");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\
+ "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\
+ "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\
+ "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\
+ "0.630702, 0.654723, 0.683267, 0.752219, 0.936438");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\
+ "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[7]_redg_min*/
+
+ timing () {
+ related_pin : "fla_obs_i[7]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\
+ "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\
+ "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\
+ "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\
+ "0.629434, 0.713469, 0.835221, 1.155234, 2.004311");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\
+ "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\
+ "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\
+ "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\
+ "0.099054, 0.205738, 0.390315, 0.940320, 2.425200");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\
+ "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\
+ "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\
+ "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\
+ "0.668936, 0.733428, 0.809479, 0.962224, 1.340585");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\
+ "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\
+ "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\
+ "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\
+ "0.118581, 0.174509, 0.240947, 0.445113, 1.092793");
+ }
+
+ } /* end of arc fla_obs_i[7]_ast2padmux_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "fla_obs_i[7]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\
+ "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\
+ "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\
+ "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\
+ "0.610985, 0.691263, 0.810230, 1.128954, 1.977655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\
+ "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\
+ "0.093347, 0.198994, 0.384563, 0.939701, 2.425563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\
+ "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\
+ "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\
+ "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\
+ "0.615736, 0.679130, 0.754042, 0.905113, 1.283136");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\
+ "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\
+ "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\
+ "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\
+ "0.116096, 0.171326, 0.236992, 0.441817, 1.092511");
+ }
+
+ } /* end of arc fla_obs_i[7]_ast2padmux_o[7]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.495682, 0.527114, 0.579822, 0.722175, 1.100772",\
+ "0.520857, 0.552289, 0.604997, 0.747350, 1.125947",\
+ "0.590847, 0.622279, 0.674987, 0.817340, 1.195937",\
+ "0.713975, 0.745406, 0.798114, 0.940467, 1.319064",\
+ "1.300896, 1.332327, 1.385036, 1.527389, 1.905985");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.673247, 0.740150, 0.856588, 1.176256, 2.031462",\
+ "0.693898, 0.760801, 0.877239, 1.196908, 2.052114",\
+ "0.752520, 0.819423, 0.935861, 1.255530, 2.110735",\
+ "0.862063, 0.928966, 1.045403, 1.365072, 2.220278",\
+ "1.621675, 1.688580, 1.805019, 2.124689, 2.979892");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073039, 0.188935, 0.391846, 0.949113, 2.441342");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[7]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.342569, 0.373981, 0.426627, 0.569042, 0.947686",\
+ "0.366027, 0.397440, 0.450085, 0.592500, 0.971144",\
+ "0.437124, 0.468537, 0.521182, 0.663597, 1.042241",\
+ "0.562321, 0.593734, 0.646379, 0.788794, 1.167438",\
+ "1.165783, 1.197195, 1.249841, 1.392256, 1.770899");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.657383, 0.724274, 0.840701, 1.160369, 2.015589",\
+ "0.673535, 0.740426, 0.856853, 1.176521, 2.031741",\
+ "0.736621, 0.803512, 0.919939, 1.239607, 2.094827",\
+ "0.845856, 0.912747, 1.029174, 1.348842, 2.204062",\
+ "1.602693, 1.669584, 1.786011, 2.105679, 2.960899");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[7]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\
+ "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\
+ "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\
+ "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\
+ "0.975060, 1.010086, 1.063144, 1.205732, 1.584486");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\
+ "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\
+ "0.049347, 0.094034, 0.180868, 0.429355, 1.091896");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\
+ "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\
+ "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\
+ "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\
+ "1.319722, 1.387140, 1.503696, 1.823662, 2.678811");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\
+ "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\
+ "0.075399, 0.189282, 0.392442, 0.951039, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[7]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\
+ "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\
+ "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\
+ "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\
+ "0.945167, 0.979651, 1.032663, 1.175209, 1.553933");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\
+ "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\
+ "0.047820, 0.093501, 0.180675, 0.429352, 1.091629");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\
+ "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\
+ "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\
+ "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\
+ "1.312551, 1.379913, 1.496487, 1.816396, 2.671496");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\
+ "0.074954, 0.189124, 0.392388, 0.950917, 2.441454");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[7]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\
+ "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\
+ "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\
+ "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\
+ "1.108576, 1.175805, 1.292423, 1.612190, 2.467167");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\
+ "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\
+ "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\
+ "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\
+ "1.013269, 1.044421, 1.097036, 1.239541, 1.618177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\
+ "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\
+ "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\
+ "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\
+ "0.949078, 1.015776, 1.132136, 1.448920, 2.298678");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\
+ "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\
+ "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\
+ "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\
+ "0.909442, 0.940877, 0.993596, 1.135938, 1.514527");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\
+ "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\
+ "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\
+ "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\
+ "0.918190, 0.949342, 1.001956, 1.144462, 1.523098");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\
+ "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\
+ "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\
+ "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\
+ "1.006927, 1.073706, 1.190415, 1.507149, 2.356620");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\
+ "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\
+ "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\
+ "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\
+ "0.893831, 0.925076, 0.977718, 1.120154, 1.498834");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\
+ "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\
+ "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\
+ "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\
+ "1.002245, 1.068944, 1.185303, 1.502088, 2.351846");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\
+ "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\
+ "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\
+ "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\
+ "0.997007, 1.063817, 1.180658, 1.497372, 2.346736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\
+ "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\
+ "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\
+ "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\
+ "1.004117, 1.035227, 1.087829, 1.230366, 1.608983");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\
+ "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\
+ "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\
+ "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\
+ "0.957622, 1.024367, 1.140929, 1.457685, 2.307276");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\
+ "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\
+ "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\
+ "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\
+ "0.955028, 0.986237, 1.038869, 1.181331, 1.559995");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\
+ "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\
+ "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\
+ "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\
+ "0.961790, 0.996912, 1.049978, 1.192575, 1.571334");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\
+ "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\
+ "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\
+ "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\
+ "1.332501, 1.399969, 1.516508, 1.836528, 2.691724");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\
+ "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\
+ "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\
+ "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\
+ "0.931678, 0.966257, 1.019278, 1.161831, 1.540560");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\
+ "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\
+ "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\
+ "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\
+ "1.324350, 1.391756, 1.508316, 1.828270, 2.683409");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\
+ "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\
+ "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\
+ "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\
+ "0.876566, 0.943791, 1.060410, 1.380173, 2.235147");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\
+ "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\
+ "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\
+ "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\
+ "0.808201, 0.839636, 0.892354, 1.034697, 1.413287");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\
+ "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\
+ "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\
+ "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\
+ "0.852482, 0.919491, 1.036016, 1.355692, 2.210772");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\
+ "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\
+ "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\
+ "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\
+ "0.786063, 0.817479, 0.870138, 1.012540, 1.391174");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\
+ "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\
+ "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\
+ "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\
+ "0.984655, 1.015818, 1.068436, 1.210933, 1.589574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\
+ "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\
+ "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\
+ "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\
+ "1.273667, 1.340892, 1.457511, 1.777274, 2.632248");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\
+ "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\
+ "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\
+ "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\
+ "0.929777, 0.961193, 1.013852, 1.156254, 1.534888");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\
+ "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\
+ "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\
+ "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\
+ "1.131911, 1.198614, 1.314996, 1.631778, 2.481517");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\
+ "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\
+ "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\
+ "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\
+ "0.999580, 1.030743, 1.083361, 1.225858, 1.604500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\
+ "0.042004, 0.091469, 0.180867, 0.429340, 1.092504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\
+ "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\
+ "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\
+ "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\
+ "1.375793, 1.443018, 1.559637, 1.879400, 2.734374");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[7]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\
+ "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\
+ "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\
+ "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\
+ "0.825559, 0.856975, 0.909634, 1.052036, 1.430670");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039038, 0.090323, 0.180168, 0.428941, 1.091519");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\
+ "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\
+ "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\
+ "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\
+ "1.141953, 1.209132, 1.325766, 1.645481, 2.500414");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067601, 0.184550, 0.382483, 0.937044, 2.417691");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[7]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.690094, 0.756997, 0.873435, 1.193104, 2.048309",\
+ "0.708444, 0.775347, 0.891784, 1.211453, 2.066659",\
+ "0.778290, 0.845193, 0.961630, 1.281299, 2.136505",\
+ "0.871001, 0.937904, 1.054342, 1.374010, 2.229216",\
+ "1.316481, 1.383384, 1.499822, 1.819491, 2.674696");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452197, 0.483629, 0.536337, 0.678690, 1.057287",\
+ "0.469625, 0.501056, 0.553764, 0.696117, 1.074714",\
+ "0.546991, 0.578423, 0.631131, 0.773484, 1.152081",\
+ "0.655363, 0.686795, 0.739503, 0.881856, 1.260453",\
+ "1.172095, 1.203526, 1.256235, 1.398588, 1.777184");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.682055, 0.748946, 0.865373, 1.185041, 2.040261",\
+ "0.698671, 0.765561, 0.881989, 1.201657, 2.056877",\
+ "0.770251, 0.837141, 0.953569, 1.273237, 2.128457",\
+ "0.862962, 0.929853, 1.046280, 1.365948, 2.221168",\
+ "1.308443, 1.375334, 1.491761, 1.811429, 2.666649");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.393282, 0.424695, 0.477340, 0.619755, 0.998399",\
+ "0.406628, 0.438041, 0.490686, 0.633102, 1.011745",\
+ "0.488076, 0.519489, 0.572134, 0.714549, 1.093193",\
+ "0.596558, 0.627970, 0.680616, 0.823031, 1.201674",\
+ "1.114468, 1.145880, 1.198526, 1.340941, 1.719585");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.501059, 0.532491, 0.585199, 0.727552, 1.106149",\
+ "0.519617, 0.551049, 0.603757, 0.746110, 1.124707",\
+ "0.596986, 0.628417, 0.681126, 0.823478, 1.202075",\
+ "0.726207, 0.757638, 0.810347, 0.952700, 1.331296",\
+ "1.349983, 1.381414, 1.434123, 1.576475, 1.955072");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.672551, 0.739454, 0.855892, 1.175561, 2.030766",\
+ "0.690451, 0.757354, 0.873791, 1.193460, 2.048666",\
+ "0.751450, 0.818353, 0.934791, 1.254459, 2.109665",\
+ "0.853899, 0.920802, 1.037239, 1.356908, 2.212114",\
+ "1.570440, 1.637343, 1.753780, 2.073449, 2.928655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.403368, 0.434780, 0.487426, 0.629841, 1.008485",\
+ "0.420114, 0.451526, 0.504172, 0.646587, 1.025230",\
+ "0.499560, 0.530972, 0.583618, 0.726033, 1.104676",\
+ "0.629829, 0.661242, 0.713887, 0.856302, 1.234946",\
+ "1.257639, 1.289051, 1.341697, 1.484112, 1.862756");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.659894, 0.726785, 0.843212, 1.162880, 2.018100",\
+ "0.674063, 0.740954, 0.857382, 1.177050, 2.032269",\
+ "0.738792, 0.805683, 0.922111, 1.241779, 2.096998",\
+ "0.841228, 0.908118, 1.024546, 1.344214, 2.199434",\
+ "1.556835, 1.623726, 1.740153, 2.059821, 2.915041");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.701899, 0.768802, 0.885240, 1.204909, 2.060114",\
+ "0.720452, 0.787355, 0.903793, 1.223462, 2.078667",\
+ "0.793150, 0.860053, 0.976490, 1.296159, 2.151365",\
+ "0.888367, 0.955270, 1.071708, 1.391377, 2.246583",\
+ "1.341174, 1.408077, 1.524515, 1.844184, 2.699389");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.458590, 0.490021, 0.542729, 0.685082, 1.063679",\
+ "0.476132, 0.507563, 0.560272, 0.702625, 1.081221",\
+ "0.553461, 0.584892, 0.637601, 0.779954, 1.158551",\
+ "0.662931, 0.694363, 0.747071, 0.889424, 1.268021",\
+ "1.187512, 1.218943, 1.271652, 1.414004, 1.792601");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.693852, 0.760742, 0.877170, 1.196838, 2.052058",\
+ "0.710673, 0.777564, 0.893991, 1.213659, 2.068879",\
+ "0.785102, 0.851993, 0.968420, 1.288088, 2.143308",\
+ "0.880320, 0.947210, 1.063638, 1.383306, 2.238526",\
+ "1.333127, 1.400018, 1.516445, 1.836113, 2.691333");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.399735, 0.431148, 0.483793, 0.626208, 1.004852",\
+ "0.413192, 0.444604, 0.497250, 0.639665, 1.018308",\
+ "0.494607, 0.526019, 0.578665, 0.721080, 1.099723",\
+ "0.604175, 0.635587, 0.688233, 0.830648, 1.209292",\
+ "1.129895, 1.161308, 1.213953, 1.356368, 1.735012");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.496000, 0.527432, 0.580140, 0.722493, 1.101090",\
+ "0.514620, 0.546052, 0.598760, 0.741113, 1.119710",\
+ "0.591411, 0.622842, 0.675550, 0.817903, 1.196500",\
+ "0.717296, 0.748727, 0.801436, 0.943789, 1.322386",\
+ "1.315738, 1.347169, 1.399878, 1.542231, 1.920827");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.666141, 0.733044, 0.849482, 1.169151, 2.024356",\
+ "0.678814, 0.745717, 0.862155, 1.181824, 2.037030",\
+ "0.733584, 0.800487, 0.916924, 1.236593, 2.091799",\
+ "0.837061, 0.903964, 1.020401, 1.340070, 2.195276",\
+ "1.538248, 1.605151, 1.721588, 2.041257, 2.896463");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.398263, 0.429676, 0.482321, 0.624736, 1.003380",\
+ "0.415077, 0.446490, 0.499135, 0.641550, 1.020194",\
+ "0.493940, 0.525353, 0.577998, 0.720414, 1.099057",\
+ "0.620916, 0.652328, 0.704974, 0.847389, 1.226032",\
+ "1.223414, 1.254826, 1.307472, 1.449887, 1.828531");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\
+ "0.039011, 0.090734, 0.180376, 0.429203, 1.091692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.653476, 0.720367, 0.836794, 1.156462, 2.011682",\
+ "0.663102, 0.729992, 0.846420, 1.166088, 2.021308",\
+ "0.720914, 0.787805, 0.904232, 1.223900, 2.079120",\
+ "0.824356, 0.891247, 1.007674, 1.327342, 2.182562",\
+ "1.523659, 1.590550, 1.706977, 2.026645, 2.881865");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\
+ "0.073030, 0.188914, 0.391814, 0.949025, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_inv_min*/
+
+ timing () {
+ related_pin : "otm_obs_i[7]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\
+ "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\
+ "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\
+ "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\
+ "0.695902, 0.774527, 0.893732, 1.214148, 2.069560");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\
+ "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\
+ "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\
+ "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\
+ "0.098084, 0.204137, 0.393542, 0.951076, 2.441498");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\
+ "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\
+ "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\
+ "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\
+ "0.825607, 0.870622, 0.930343, 1.075147, 1.454209");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\
+ "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\
+ "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\
+ "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\
+ "0.068556, 0.114740, 0.192215, 0.429716, 1.093122");
+ }
+
+ } /* end of arc otm_obs_i[7]_ast2padmux_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otm_obs_i[7]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\
+ "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\
+ "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\
+ "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\
+ "0.662107, 0.738115, 0.856688, 1.177023, 2.032395");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\
+ "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\
+ "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\
+ "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\
+ "0.092938, 0.200557, 0.393255, 0.950255, 2.441468");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\
+ "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\
+ "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\
+ "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\
+ "0.777508, 0.822171, 0.881623, 1.026340, 1.405392");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\
+ "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\
+ "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\
+ "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\
+ "0.067933, 0.113945, 0.191732, 0.429701, 1.093101");
+ }
+
+ } /* end of arc otm_obs_i[7]_ast2padmux_o[7]_una_min*/
+
+ timing () {
+ related_pin : "otp_obs_i[7]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\
+ "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\
+ "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\
+ "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\
+ "0.699992, 0.780922, 0.900058, 1.218756, 2.067549");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\
+ "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\
+ "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\
+ "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\
+ "0.094401, 0.199857, 0.384817, 0.940410, 2.426093");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\
+ "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\
+ "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\
+ "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\
+ "0.820213, 0.870292, 0.933027, 1.077593, 1.455130");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\
+ "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\
+ "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\
+ "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\
+ "0.087354, 0.133744, 0.204884, 0.431205, 1.092443");
+ }
+
+ } /* end of arc otp_obs_i[7]_ast2padmux_o[7]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_obs_i[7]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\
+ "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\
+ "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\
+ "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\
+ "0.667813, 0.745674, 0.864272, 1.183300, 2.031636");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\
+ "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\
+ "0.089380, 0.196045, 0.384240, 0.939859, 2.423100");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\
+ "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\
+ "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\
+ "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\
+ "0.773733, 0.823401, 0.885774, 1.030256, 1.407808");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\
+ "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\
+ "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\
+ "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\
+ "0.086478, 0.132591, 0.204027, 0.431125, 1.092425");
+ }
+
+ } /* end of arc otp_obs_i[7]_ast2padmux_o[7]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\
+ "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\
+ "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\
+ "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[7]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\
+ "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\
+ "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\
+ "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\
+ "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\
+ "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\
+ "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[7]_inv_min*/
+
+} /* end of pin ast2padmux_o[7] */
+
+pin("ast2padmux_o[6]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.028584 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2padmux_o[6];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\
+ "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\
+ "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\
+ "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\
+ "0.073824, 0.189425, 0.393252, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\
+ "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\
+ "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[6]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\
+ "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\
+ "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\
+ "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\
+ "0.643636, 0.699058, 0.793671, 1.054205, 1.742813");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\
+ "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\
+ "0.054820, 0.149920, 0.315966, 0.770514, 1.988361");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\
+ "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\
+ "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\
+ "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\
+ "0.630702, 0.654723, 0.683267, 0.752219, 0.936438");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\
+ "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[6]_redg_min*/
+
+ timing () {
+ related_pin : "fla_obs_i[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\
+ "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\
+ "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\
+ "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\
+ "0.629434, 0.713469, 0.835221, 1.155234, 2.004311");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\
+ "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\
+ "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\
+ "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\
+ "0.099054, 0.205738, 0.390315, 0.940320, 2.425200");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\
+ "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\
+ "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\
+ "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\
+ "0.668936, 0.733428, 0.809479, 0.962224, 1.340585");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\
+ "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\
+ "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\
+ "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\
+ "0.118581, 0.174509, 0.240947, 0.445113, 1.092793");
+ }
+
+ } /* end of arc fla_obs_i[6]_ast2padmux_o[6]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "fla_obs_i[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\
+ "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\
+ "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\
+ "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\
+ "0.610985, 0.691263, 0.810230, 1.128954, 1.977655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\
+ "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\
+ "0.093347, 0.198994, 0.384563, 0.939701, 2.425563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\
+ "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\
+ "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\
+ "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\
+ "0.615736, 0.679130, 0.754042, 0.905113, 1.283136");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\
+ "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\
+ "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\
+ "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\
+ "0.116096, 0.171326, 0.236992, 0.441817, 1.092511");
+ }
+
+ } /* end of arc fla_obs_i[6]_ast2padmux_o[6]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.401444, 0.432876, 0.485584, 0.627937, 1.006534",\
+ "0.426514, 0.457945, 0.510653, 0.653006, 1.031603",\
+ "0.495788, 0.527220, 0.579928, 0.722281, 1.100878",\
+ "0.620121, 0.651552, 0.704261, 0.846613, 1.225210",\
+ "1.225494, 1.256926, 1.309634, 1.451987, 1.830584");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.665410, 0.732314, 0.848751, 1.168420, 2.023626",\
+ "0.685984, 0.752887, 0.869324, 1.188993, 2.044199",\
+ "0.744648, 0.811551, 0.927989, 1.247657, 2.102863",\
+ "0.853883, 0.920786, 1.037224, 1.356892, 2.212098",\
+ "1.621675, 1.688580, 1.805019, 2.124689, 2.979892");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073039, 0.188935, 0.391846, 0.949113, 2.441342");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[6]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.345553, 0.376966, 0.429613, 0.572027, 0.950669",\
+ "0.369011, 0.400424, 0.453071, 0.595485, 0.974127",\
+ "0.440108, 0.471521, 0.524168, 0.666582, 1.045224",\
+ "0.565305, 0.596718, 0.649365, 0.791779, 1.170421",\
+ "1.171631, 1.203044, 1.255693, 1.398105, 1.776746");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039018, 0.090728, 0.180391, 0.429207, 1.091650");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.663782, 0.730673, 0.847101, 1.166770, 2.021989",\
+ "0.679934, 0.746826, 0.863254, 1.182922, 2.038141",\
+ "0.743020, 0.809911, 0.926339, 1.246007, 2.101227",\
+ "0.852255, 0.919146, 1.035574, 1.355242, 2.210462",\
+ "1.620317, 1.687211, 1.803640, 2.123309, 2.978526");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073030, 0.188915, 0.391817, 0.949051, 2.441332");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[6]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\
+ "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\
+ "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\
+ "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\
+ "0.975060, 1.010086, 1.063144, 1.205732, 1.584486");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\
+ "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\
+ "0.049347, 0.094034, 0.180868, 0.429355, 1.091896");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\
+ "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\
+ "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\
+ "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\
+ "1.319722, 1.387140, 1.503696, 1.823662, 2.678811");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\
+ "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\
+ "0.075399, 0.189282, 0.392442, 0.951039, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[6]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\
+ "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\
+ "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\
+ "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\
+ "0.945167, 0.979651, 1.032663, 1.175209, 1.553933");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\
+ "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\
+ "0.047820, 0.093501, 0.180675, 0.429352, 1.091629");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\
+ "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\
+ "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\
+ "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\
+ "1.312551, 1.379913, 1.496487, 1.816396, 2.671496");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\
+ "0.074954, 0.189124, 0.392388, 0.950917, 2.441454");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[6]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\
+ "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\
+ "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\
+ "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\
+ "1.108576, 1.175805, 1.292423, 1.612190, 2.467167");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\
+ "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\
+ "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\
+ "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\
+ "1.013269, 1.044421, 1.097036, 1.239541, 1.618177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\
+ "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\
+ "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\
+ "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\
+ "0.949078, 1.015776, 1.132136, 1.448920, 2.298678");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\
+ "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\
+ "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\
+ "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\
+ "0.909442, 0.940877, 0.993596, 1.135938, 1.514527");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\
+ "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\
+ "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\
+ "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\
+ "0.918190, 0.949342, 1.001956, 1.144462, 1.523098");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\
+ "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\
+ "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\
+ "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\
+ "1.006927, 1.073706, 1.190415, 1.507149, 2.356620");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\
+ "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\
+ "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\
+ "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\
+ "0.893831, 0.925076, 0.977718, 1.120154, 1.498834");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\
+ "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\
+ "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\
+ "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\
+ "1.002245, 1.068944, 1.185303, 1.502088, 2.351846");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\
+ "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\
+ "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\
+ "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\
+ "0.997007, 1.063817, 1.180658, 1.497372, 2.346736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\
+ "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\
+ "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\
+ "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\
+ "1.004117, 1.035227, 1.087829, 1.230366, 1.608983");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\
+ "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\
+ "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\
+ "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\
+ "0.957622, 1.024367, 1.140929, 1.457685, 2.307276");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\
+ "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\
+ "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\
+ "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\
+ "0.955028, 0.986237, 1.038869, 1.181331, 1.559995");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\
+ "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\
+ "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\
+ "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\
+ "0.961790, 0.996912, 1.049978, 1.192575, 1.571334");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\
+ "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\
+ "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\
+ "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\
+ "1.332501, 1.399969, 1.516508, 1.836528, 2.691724");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\
+ "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\
+ "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\
+ "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\
+ "0.931678, 0.966257, 1.019278, 1.161831, 1.540560");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\
+ "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\
+ "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\
+ "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\
+ "1.324350, 1.391756, 1.508316, 1.828270, 2.683409");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\
+ "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\
+ "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\
+ "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\
+ "0.876566, 0.943791, 1.060410, 1.380173, 2.235147");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\
+ "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\
+ "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\
+ "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\
+ "0.808201, 0.839636, 0.892354, 1.034697, 1.413287");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\
+ "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\
+ "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\
+ "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\
+ "0.852482, 0.919491, 1.036016, 1.355692, 2.210772");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\
+ "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\
+ "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\
+ "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\
+ "0.786063, 0.817479, 0.870138, 1.012540, 1.391174");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\
+ "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\
+ "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\
+ "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\
+ "0.984655, 1.015818, 1.068436, 1.210933, 1.589574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\
+ "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\
+ "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\
+ "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\
+ "1.273667, 1.340892, 1.457511, 1.777274, 2.632248");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\
+ "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\
+ "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\
+ "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\
+ "0.929777, 0.961193, 1.013852, 1.156254, 1.534888");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\
+ "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\
+ "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\
+ "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\
+ "1.131911, 1.198614, 1.314996, 1.631778, 2.481517");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\
+ "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\
+ "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\
+ "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\
+ "0.999580, 1.030743, 1.083361, 1.225858, 1.604500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\
+ "0.042004, 0.091469, 0.180867, 0.429340, 1.092504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\
+ "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\
+ "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\
+ "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\
+ "1.375793, 1.443018, 1.559637, 1.879400, 2.734374");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[6]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\
+ "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\
+ "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\
+ "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\
+ "0.825559, 0.856975, 0.909634, 1.052036, 1.430670");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039038, 0.090323, 0.180168, 0.428941, 1.091519");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\
+ "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\
+ "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\
+ "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\
+ "1.141953, 1.209132, 1.325766, 1.645481, 2.500414");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067601, 0.184550, 0.382483, 0.937044, 2.417691");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[6]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.690094, 0.756997, 0.873435, 1.193104, 2.048309",\
+ "0.708444, 0.775347, 0.891784, 1.211453, 2.066659",\
+ "0.778290, 0.845193, 0.961630, 1.281299, 2.136505",\
+ "0.871001, 0.937904, 1.054342, 1.374010, 2.229216",\
+ "1.316481, 1.383384, 1.499822, 1.819491, 2.674696");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452134, 0.483566, 0.536274, 0.678627, 1.057224",\
+ "0.469561, 0.500993, 0.553701, 0.696054, 1.074651",\
+ "0.546928, 0.578360, 0.631068, 0.773421, 1.152018",\
+ "0.655300, 0.686732, 0.739440, 0.881793, 1.260390",\
+ "1.172032, 1.203463, 1.256172, 1.398524, 1.777121");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[6]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.688464, 0.755356, 0.871784, 1.191452, 2.046671",\
+ "0.705080, 0.771971, 0.888399, 1.208067, 2.063287",\
+ "0.776660, 0.843551, 0.959979, 1.279647, 2.134867",\
+ "0.869371, 0.936263, 1.052691, 1.372359, 2.227578",\
+ "1.314852, 1.381744, 1.498172, 1.817840, 2.673059");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.396265, 0.427678, 0.480325, 0.622739, 1.001381",\
+ "0.409612, 0.441025, 0.493672, 0.636085, 1.014728",\
+ "0.491059, 0.522472, 0.575119, 0.717533, 1.096175",\
+ "0.599541, 0.630954, 0.683601, 0.826015, 1.204657",\
+ "1.117451, 1.148864, 1.201511, 1.343925, 1.722567");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[6]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.701899, 0.768802, 0.885240, 1.204909, 2.060114",\
+ "0.720452, 0.787355, 0.903793, 1.223462, 2.078667",\
+ "0.793150, 0.860053, 0.976490, 1.296159, 2.151365",\
+ "0.888367, 0.955270, 1.071708, 1.391377, 2.246583",\
+ "1.341174, 1.408077, 1.524515, 1.844184, 2.699389");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.458526, 0.489958, 0.542666, 0.685019, 1.063616",\
+ "0.476069, 0.507500, 0.560208, 0.702561, 1.081158",\
+ "0.553398, 0.584829, 0.637537, 0.779890, 1.158487",\
+ "0.662868, 0.694299, 0.747008, 0.889361, 1.267957",\
+ "1.187448, 1.218880, 1.271588, 1.413941, 1.792538");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[6]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.700268, 0.767160, 0.883588, 1.203256, 2.058475",\
+ "0.717089, 0.783981, 0.900409, 1.220077, 2.075296",\
+ "0.791519, 0.858410, 0.974838, 1.294506, 2.149726",\
+ "0.886736, 0.953628, 1.070056, 1.389724, 2.244943",\
+ "1.339543, 1.406435, 1.522863, 1.842531, 2.697751");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.402716, 0.434129, 0.486776, 0.629190, 1.007832",\
+ "0.416173, 0.447586, 0.500233, 0.642646, 1.021289",\
+ "0.497588, 0.529001, 0.581648, 0.724061, 1.102704",\
+ "0.607156, 0.638569, 0.691216, 0.833630, 1.212272",\
+ "1.132876, 1.164289, 1.216936, 1.359350, 1.737992");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[6]_una_min*/
+
+ timing () {
+ related_pin : "otm_obs_i[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\
+ "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\
+ "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\
+ "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\
+ "0.695902, 0.774527, 0.893732, 1.214148, 2.069560");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\
+ "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\
+ "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\
+ "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\
+ "0.098084, 0.204137, 0.393542, 0.951076, 2.441498");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\
+ "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\
+ "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\
+ "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\
+ "0.825607, 0.870622, 0.930343, 1.075147, 1.454209");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\
+ "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\
+ "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\
+ "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\
+ "0.068556, 0.114740, 0.192215, 0.429716, 1.093122");
+ }
+
+ } /* end of arc otm_obs_i[6]_ast2padmux_o[6]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otm_obs_i[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\
+ "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\
+ "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\
+ "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\
+ "0.662107, 0.738115, 0.856688, 1.177023, 2.032395");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\
+ "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\
+ "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\
+ "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\
+ "0.092938, 0.200557, 0.393255, 0.950255, 2.441468");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\
+ "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\
+ "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\
+ "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\
+ "0.777508, 0.822171, 0.881623, 1.026340, 1.405392");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\
+ "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\
+ "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\
+ "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\
+ "0.067933, 0.113945, 0.191732, 0.429701, 1.093101");
+ }
+
+ } /* end of arc otm_obs_i[6]_ast2padmux_o[6]_una_min*/
+
+ timing () {
+ related_pin : "otp_obs_i[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\
+ "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\
+ "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\
+ "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\
+ "0.699992, 0.780922, 0.900058, 1.218756, 2.067549");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\
+ "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\
+ "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\
+ "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\
+ "0.094401, 0.199857, 0.384817, 0.940410, 2.426093");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\
+ "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\
+ "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\
+ "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\
+ "0.820213, 0.870292, 0.933027, 1.077593, 1.455130");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\
+ "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\
+ "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\
+ "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\
+ "0.087354, 0.133744, 0.204884, 0.431205, 1.092443");
+ }
+
+ } /* end of arc otp_obs_i[6]_ast2padmux_o[6]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_obs_i[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\
+ "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\
+ "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\
+ "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\
+ "0.667813, 0.745674, 0.864272, 1.183300, 2.031636");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\
+ "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\
+ "0.089380, 0.196045, 0.384240, 0.939859, 2.423100");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\
+ "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\
+ "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\
+ "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\
+ "0.773733, 0.823401, 0.885774, 1.030256, 1.407808");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\
+ "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\
+ "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\
+ "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\
+ "0.086478, 0.132591, 0.204027, 0.431125, 1.092425");
+ }
+
+ } /* end of arc otp_obs_i[6]_ast2padmux_o[6]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\
+ "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\
+ "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\
+ "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[6]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\
+ "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\
+ "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\
+ "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\
+ "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\
+ "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\
+ "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[6]_inv_min*/
+
+} /* end of pin ast2padmux_o[6] */
+
+pin("ast2padmux_o[5]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.028584 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2padmux_o[5];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\
+ "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\
+ "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\
+ "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\
+ "0.073824, 0.189425, 0.393252, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\
+ "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\
+ "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[5]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\
+ "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\
+ "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\
+ "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\
+ "0.643636, 0.699058, 0.793671, 1.054205, 1.742813");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\
+ "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\
+ "0.054820, 0.149920, 0.315966, 0.770514, 1.988361");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\
+ "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\
+ "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\
+ "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\
+ "0.630702, 0.654723, 0.683267, 0.752219, 0.936438");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\
+ "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[5]_redg_min*/
+
+ timing () {
+ related_pin : "fla_obs_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\
+ "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\
+ "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\
+ "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\
+ "0.629434, 0.713469, 0.835221, 1.155234, 2.004311");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\
+ "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\
+ "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\
+ "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\
+ "0.099054, 0.205738, 0.390315, 0.940320, 2.425200");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\
+ "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\
+ "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\
+ "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\
+ "0.668936, 0.733428, 0.809479, 0.962224, 1.340585");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\
+ "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\
+ "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\
+ "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\
+ "0.118581, 0.174509, 0.240947, 0.445113, 1.092793");
+ }
+
+ } /* end of arc fla_obs_i[5]_ast2padmux_o[5]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "fla_obs_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\
+ "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\
+ "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\
+ "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\
+ "0.610985, 0.691263, 0.810230, 1.128954, 1.977655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\
+ "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\
+ "0.093347, 0.198994, 0.384563, 0.939701, 2.425563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\
+ "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\
+ "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\
+ "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\
+ "0.615736, 0.679130, 0.754042, 0.905113, 1.283136");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\
+ "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\
+ "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\
+ "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\
+ "0.116096, 0.171326, 0.236992, 0.441817, 1.092511");
+ }
+
+ } /* end of arc fla_obs_i[5]_ast2padmux_o[5]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.401444, 0.432876, 0.485584, 0.627937, 1.006534",\
+ "0.426514, 0.457945, 0.510653, 0.653006, 1.031603",\
+ "0.495788, 0.527220, 0.579928, 0.722281, 1.100878",\
+ "0.620121, 0.651552, 0.704261, 0.846613, 1.225210",\
+ "1.225494, 1.256926, 1.309634, 1.451987, 1.830584");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.665410, 0.732314, 0.848751, 1.168420, 2.023626",\
+ "0.685984, 0.752887, 0.869324, 1.188993, 2.044199",\
+ "0.744648, 0.811551, 0.927989, 1.247657, 2.102863",\
+ "0.853883, 0.920786, 1.037224, 1.356892, 2.212098",\
+ "1.621675, 1.688580, 1.805019, 2.124689, 2.979892");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073039, 0.188935, 0.391846, 0.949113, 2.441342");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[5]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.345553, 0.376966, 0.429613, 0.572027, 0.950669",\
+ "0.369011, 0.400424, 0.453071, 0.595485, 0.974127",\
+ "0.440108, 0.471521, 0.524168, 0.666582, 1.045224",\
+ "0.565305, 0.596718, 0.649365, 0.791779, 1.170421",\
+ "1.171631, 1.203044, 1.255693, 1.398105, 1.776746");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039018, 0.090728, 0.180391, 0.429207, 1.091650");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.663782, 0.730673, 0.847101, 1.166770, 2.021989",\
+ "0.679934, 0.746826, 0.863254, 1.182922, 2.038141",\
+ "0.743020, 0.809911, 0.926339, 1.246007, 2.101227",\
+ "0.852255, 0.919146, 1.035574, 1.355242, 2.210462",\
+ "1.620317, 1.687211, 1.803640, 2.123309, 2.978526");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073030, 0.188915, 0.391817, 0.949051, 2.441332");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[5]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\
+ "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\
+ "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\
+ "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\
+ "0.975060, 1.010086, 1.063144, 1.205732, 1.584486");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\
+ "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\
+ "0.049347, 0.094034, 0.180868, 0.429355, 1.091896");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\
+ "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\
+ "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\
+ "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\
+ "1.319722, 1.387140, 1.503696, 1.823662, 2.678811");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\
+ "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\
+ "0.075399, 0.189282, 0.392442, 0.951039, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[5]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\
+ "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\
+ "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\
+ "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\
+ "0.945167, 0.979651, 1.032663, 1.175209, 1.553933");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\
+ "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\
+ "0.047820, 0.093501, 0.180675, 0.429352, 1.091629");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\
+ "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\
+ "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\
+ "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\
+ "1.312551, 1.379913, 1.496487, 1.816396, 2.671496");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\
+ "0.074954, 0.189124, 0.392388, 0.950917, 2.441454");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[5]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\
+ "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\
+ "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\
+ "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\
+ "1.108576, 1.175805, 1.292423, 1.612190, 2.467167");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\
+ "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\
+ "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\
+ "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\
+ "1.013269, 1.044421, 1.097036, 1.239541, 1.618177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\
+ "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\
+ "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\
+ "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\
+ "0.949078, 1.015776, 1.132136, 1.448920, 2.298678");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\
+ "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\
+ "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\
+ "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\
+ "0.909442, 0.940877, 0.993596, 1.135938, 1.514527");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\
+ "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\
+ "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\
+ "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\
+ "0.918190, 0.949342, 1.001956, 1.144462, 1.523098");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\
+ "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\
+ "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\
+ "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\
+ "1.006927, 1.073706, 1.190415, 1.507149, 2.356620");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\
+ "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\
+ "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\
+ "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\
+ "0.893831, 0.925076, 0.977718, 1.120154, 1.498834");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\
+ "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\
+ "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\
+ "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\
+ "1.002245, 1.068944, 1.185303, 1.502088, 2.351846");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\
+ "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\
+ "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\
+ "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\
+ "0.997007, 1.063817, 1.180658, 1.497372, 2.346736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\
+ "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\
+ "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\
+ "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\
+ "1.004117, 1.035227, 1.087829, 1.230366, 1.608983");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\
+ "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\
+ "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\
+ "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\
+ "0.957622, 1.024367, 1.140929, 1.457685, 2.307276");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\
+ "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\
+ "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\
+ "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\
+ "0.955028, 0.986237, 1.038869, 1.181331, 1.559995");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\
+ "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\
+ "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\
+ "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\
+ "0.961790, 0.996912, 1.049978, 1.192575, 1.571334");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\
+ "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\
+ "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\
+ "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\
+ "1.332501, 1.399969, 1.516508, 1.836528, 2.691724");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\
+ "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\
+ "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\
+ "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\
+ "0.931678, 0.966257, 1.019278, 1.161831, 1.540560");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\
+ "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\
+ "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\
+ "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\
+ "1.324350, 1.391756, 1.508316, 1.828270, 2.683409");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\
+ "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\
+ "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\
+ "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\
+ "0.876566, 0.943791, 1.060410, 1.380173, 2.235147");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\
+ "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\
+ "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\
+ "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\
+ "0.808201, 0.839636, 0.892354, 1.034697, 1.413287");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\
+ "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\
+ "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\
+ "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\
+ "0.852482, 0.919491, 1.036016, 1.355692, 2.210772");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\
+ "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\
+ "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\
+ "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\
+ "0.786063, 0.817479, 0.870138, 1.012540, 1.391174");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\
+ "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\
+ "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\
+ "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\
+ "0.984655, 1.015818, 1.068436, 1.210933, 1.589574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\
+ "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\
+ "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\
+ "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\
+ "1.273667, 1.340892, 1.457511, 1.777274, 2.632248");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\
+ "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\
+ "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\
+ "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\
+ "0.929777, 0.961193, 1.013852, 1.156254, 1.534888");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\
+ "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\
+ "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\
+ "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\
+ "1.131911, 1.198614, 1.314996, 1.631778, 2.481517");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\
+ "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\
+ "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\
+ "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\
+ "0.999580, 1.030743, 1.083361, 1.225858, 1.604500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\
+ "0.042004, 0.091469, 0.180867, 0.429340, 1.092504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\
+ "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\
+ "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\
+ "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\
+ "1.375793, 1.443018, 1.559637, 1.879400, 2.734374");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[5]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\
+ "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\
+ "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\
+ "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\
+ "0.825559, 0.856975, 0.909634, 1.052036, 1.430670");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039038, 0.090323, 0.180168, 0.428941, 1.091519");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\
+ "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\
+ "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\
+ "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\
+ "1.141953, 1.209132, 1.325766, 1.645481, 2.500414");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067601, 0.184550, 0.382483, 0.937044, 2.417691");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[5]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.690094, 0.756997, 0.873435, 1.193104, 2.048309",\
+ "0.708444, 0.775347, 0.891784, 1.211453, 2.066659",\
+ "0.778290, 0.845193, 0.961630, 1.281299, 2.136505",\
+ "0.871001, 0.937904, 1.054342, 1.374010, 2.229216",\
+ "1.316481, 1.383384, 1.499822, 1.819491, 2.674696");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452134, 0.483566, 0.536274, 0.678627, 1.057224",\
+ "0.469561, 0.500993, 0.553701, 0.696054, 1.074651",\
+ "0.546928, 0.578360, 0.631068, 0.773421, 1.152018",\
+ "0.655300, 0.686732, 0.739440, 0.881793, 1.260390",\
+ "1.172032, 1.203463, 1.256172, 1.398524, 1.777121");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[5]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.688464, 0.755356, 0.871784, 1.191452, 2.046671",\
+ "0.705080, 0.771971, 0.888399, 1.208067, 2.063287",\
+ "0.776660, 0.843551, 0.959979, 1.279647, 2.134867",\
+ "0.869371, 0.936263, 1.052691, 1.372359, 2.227578",\
+ "1.314852, 1.381744, 1.498172, 1.817840, 2.673059");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.396265, 0.427678, 0.480325, 0.622739, 1.001381",\
+ "0.409612, 0.441025, 0.493672, 0.636085, 1.014728",\
+ "0.491059, 0.522472, 0.575119, 0.717533, 1.096175",\
+ "0.599541, 0.630954, 0.683601, 0.826015, 1.204657",\
+ "1.117451, 1.148864, 1.201511, 1.343925, 1.722567");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[5]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.701899, 0.768802, 0.885240, 1.204909, 2.060114",\
+ "0.720452, 0.787355, 0.903793, 1.223462, 2.078667",\
+ "0.793150, 0.860053, 0.976490, 1.296159, 2.151365",\
+ "0.888367, 0.955270, 1.071708, 1.391377, 2.246583",\
+ "1.341174, 1.408077, 1.524515, 1.844184, 2.699389");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\
+ "0.073037, 0.188931, 0.391841, 0.949101, 2.441340");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.458526, 0.489958, 0.542666, 0.685019, 1.063616",\
+ "0.476069, 0.507500, 0.560208, 0.702561, 1.081158",\
+ "0.553398, 0.584829, 0.637537, 0.779890, 1.158487",\
+ "0.662868, 0.694299, 0.747008, 0.889361, 1.267957",\
+ "1.187448, 1.218880, 1.271588, 1.413941, 1.792538");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[5]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.700268, 0.767160, 0.883588, 1.203256, 2.058475",\
+ "0.717089, 0.783981, 0.900409, 1.220077, 2.075296",\
+ "0.791519, 0.858410, 0.974838, 1.294506, 2.149726",\
+ "0.886736, 0.953628, 1.070056, 1.389724, 2.244943",\
+ "1.339543, 1.406435, 1.522863, 1.842531, 2.697751");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\
+ "0.073029, 0.188911, 0.391812, 0.949040, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.402716, 0.434129, 0.486776, 0.629190, 1.007832",\
+ "0.416173, 0.447586, 0.500233, 0.642646, 1.021289",\
+ "0.497588, 0.529001, 0.581648, 0.724061, 1.102704",\
+ "0.607156, 0.638569, 0.691216, 0.833630, 1.212272",\
+ "1.132876, 1.164289, 1.216936, 1.359350, 1.737992");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\
+ "0.039014, 0.090731, 0.180384, 0.429205, 1.091671");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[5]_una_min*/
+
+ timing () {
+ related_pin : "otm_obs_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\
+ "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\
+ "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\
+ "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\
+ "0.695902, 0.774527, 0.893732, 1.214148, 2.069560");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\
+ "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\
+ "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\
+ "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\
+ "0.098084, 0.204137, 0.393542, 0.951076, 2.441498");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\
+ "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\
+ "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\
+ "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\
+ "0.825607, 0.870622, 0.930343, 1.075147, 1.454209");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\
+ "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\
+ "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\
+ "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\
+ "0.068556, 0.114740, 0.192215, 0.429716, 1.093122");
+ }
+
+ } /* end of arc otm_obs_i[5]_ast2padmux_o[5]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otm_obs_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\
+ "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\
+ "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\
+ "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\
+ "0.662107, 0.738115, 0.856688, 1.177023, 2.032395");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\
+ "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\
+ "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\
+ "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\
+ "0.092938, 0.200557, 0.393255, 0.950255, 2.441468");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\
+ "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\
+ "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\
+ "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\
+ "0.777508, 0.822171, 0.881623, 1.026340, 1.405392");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\
+ "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\
+ "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\
+ "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\
+ "0.067933, 0.113945, 0.191732, 0.429701, 1.093101");
+ }
+
+ } /* end of arc otm_obs_i[5]_ast2padmux_o[5]_una_min*/
+
+ timing () {
+ related_pin : "otp_obs_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\
+ "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\
+ "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\
+ "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\
+ "0.699992, 0.780922, 0.900058, 1.218756, 2.067549");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\
+ "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\
+ "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\
+ "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\
+ "0.094401, 0.199857, 0.384817, 0.940410, 2.426093");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\
+ "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\
+ "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\
+ "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\
+ "0.820213, 0.870292, 0.933027, 1.077593, 1.455130");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\
+ "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\
+ "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\
+ "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\
+ "0.087354, 0.133744, 0.204884, 0.431205, 1.092443");
+ }
+
+ } /* end of arc otp_obs_i[5]_ast2padmux_o[5]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_obs_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\
+ "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\
+ "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\
+ "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\
+ "0.667813, 0.745674, 0.864272, 1.183300, 2.031636");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\
+ "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\
+ "0.089380, 0.196045, 0.384240, 0.939859, 2.423100");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\
+ "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\
+ "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\
+ "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\
+ "0.773733, 0.823401, 0.885774, 1.030256, 1.407808");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\
+ "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\
+ "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\
+ "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\
+ "0.086478, 0.132591, 0.204027, 0.431125, 1.092425");
+ }
+
+ } /* end of arc otp_obs_i[5]_ast2padmux_o[5]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\
+ "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\
+ "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\
+ "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[5]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\
+ "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\
+ "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\
+ "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\
+ "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\
+ "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\
+ "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[5]_inv_min*/
+
+} /* end of pin ast2padmux_o[5] */
+
+pin("ast2padmux_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.028584 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2padmux_o[4];
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_b_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.256137, 0.526101, 0.791807, 1.233240, 2.116106",\
+ "0.323038, 0.593004, 0.858715, 1.300159, 2.183047",\
+ "0.439474, 0.709441, 0.975156, 1.416609, 2.299516",\
+ "0.759143, 1.029110, 1.294825, 1.736279, 2.619187",\
+ "1.614351, 1.884316, 2.150025, 2.591466, 3.474348",\
+ "0.314712, 0.584612, 0.850579, 1.290946, 2.172213",\
+ "0.381613, 0.651515, 0.917487, 1.357865, 2.239154",\
+ "0.498049, 0.767952, 1.033928, 1.474316, 2.355623",\
+ "0.817718, 1.087621, 1.353598, 1.793986, 2.675294",\
+ "1.672926, 1.942827, 2.208797, 2.649173, 3.530455",\
+ "0.459188, 0.730385, 0.994470, 1.434701, 2.315946",\
+ "0.526089, 0.797288, 1.061378, 1.501621, 2.382887",\
+ "0.642525, 0.913725, 1.177819, 1.618071, 2.499355",\
+ "0.962194, 1.233394, 1.497489, 1.937741, 2.819027",\
+ "1.817402, 2.088600, 2.352689, 2.792928, 3.674187",\
+ "0.495112, 0.768133, 1.031389, 1.471493, 2.352504",\
+ "0.562013, 0.835036, 1.098297, 1.538412, 2.419445",\
+ "0.678449, 0.951473, 1.214738, 1.654862, 2.535913",\
+ "0.998118, 1.271142, 1.534407, 1.974532, 2.855585",\
+ "1.853326, 2.126348, 2.389607, 2.829719, 3.710746",\
+ "0.823805, 1.131731, 1.382980, 1.820732, 2.697960",\
+ "0.890706, 1.198635, 1.449888, 1.887651, 2.764901",\
+ "1.007142, 1.315072, 1.566330, 2.004102, 2.881370",\
+ "1.326811, 1.634741, 1.885999, 2.323771, 3.201041",\
+ "2.182019, 2.489947, 2.741199, 3.178958, 4.056201");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\
+ "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\
+ "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\
+ "0.949092, 0.949099, 0.949128, 0.949187, 0.949305",\
+ "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\
+ "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\
+ "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\
+ "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\
+ "0.949092, 0.949099, 0.949128, 0.949187, 0.949305",\
+ "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\
+ "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\
+ "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\
+ "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\
+ "0.949092, 0.949100, 0.949128, 0.949187, 0.949305",\
+ "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\
+ "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\
+ "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\
+ "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\
+ "0.949092, 0.949100, 0.949128, 0.949187, 0.949305",\
+ "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\
+ "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\
+ "0.188928, 0.188932, 0.188940, 0.188959, 0.188997",\
+ "0.391836, 0.391842, 0.391854, 0.391881, 0.391936",\
+ "0.949092, 0.949103, 0.949129, 0.949187, 0.949305",\
+ "2.441339, 2.441340, 2.441345, 2.441355, 2.441374");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.300809, 0.483950, 0.676379, 0.983182, 1.575800",\
+ "0.332240, 0.515381, 0.707810, 1.014614, 1.607232",\
+ "0.384949, 0.568090, 0.760519, 1.067323, 1.659944",\
+ "0.527301, 0.710443, 0.902872, 1.209675, 1.802294",\
+ "0.905898, 1.089039, 1.281469, 1.588271, 2.180888",\
+ "0.360720, 0.543848, 0.736331, 1.042962, 1.635417",\
+ "0.392152, 0.575280, 0.767762, 1.074394, 1.666849",\
+ "0.444860, 0.627988, 0.820471, 1.127103, 1.719561",\
+ "0.587213, 0.770341, 0.962824, 1.269455, 1.861911",\
+ "0.965810, 1.148938, 1.341421, 1.648051, 2.240505",\
+ "0.493463, 0.676099, 0.868214, 1.174820, 1.767224",\
+ "0.524895, 0.707531, 0.899645, 1.206252, 1.798657",\
+ "0.577603, 0.760239, 0.952354, 1.258961, 1.851368",\
+ "0.719956, 0.902592, 1.094707, 1.401313, 1.993718",\
+ "1.098553, 1.281189, 1.473303, 1.779909, 2.372313",\
+ "0.526601, 0.709226, 0.901339, 1.207772, 1.799833",\
+ "0.558032, 0.740658, 0.932770, 1.239204, 1.831265",\
+ "0.610741, 0.793366, 0.985478, 1.291914, 1.883977",\
+ "0.753093, 0.935719, 1.127831, 1.434265, 2.026326",\
+ "1.131690, 1.314316, 1.506428, 1.812862, 2.404921",\
+ "0.827685, 1.014449, 1.204974, 1.510788, 2.101678",\
+ "0.859116, 1.045881, 1.236405, 1.542220, 2.133111",\
+ "0.911824, 1.098589, 1.289114, 1.594929, 2.185822",\
+ "1.054177, 1.240942, 1.431466, 1.737281, 2.328172",\
+ "1.432774, 1.619539, 1.810063, 2.115877, 2.706767");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_b_o[3]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.252605, 0.520760, 0.784538, 1.222585, 2.097608",\
+ "0.319496, 0.587651, 0.851435, 1.289491, 2.164534",\
+ "0.435923, 0.704079, 0.967867, 1.405931, 2.280990",\
+ "0.755591, 1.023747, 1.287535, 1.725600, 2.600661",\
+ "1.610811, 1.878966, 2.142749, 2.580802, 3.455839",\
+ "0.311166, 0.579267, 0.843303, 1.280291, 2.153714",\
+ "0.378057, 0.646158, 0.910200, 1.347198, 2.220641",\
+ "0.494484, 0.762586, 1.026632, 1.463638, 2.337097",\
+ "0.814152, 1.082254, 1.346300, 1.783307, 2.656768",\
+ "1.669372, 1.937473, 2.201514, 2.638509, 3.511946",\
+ "0.455502, 0.725014, 0.987191, 1.424095, 2.297447",\
+ "0.522393, 0.791906, 1.054087, 1.491001, 2.364373",\
+ "0.638820, 0.908334, 1.170519, 1.607441, 2.480830",\
+ "0.958488, 1.228002, 1.490188, 1.927111, 2.800500",\
+ "1.813708, 2.083220, 2.345402, 2.782313, 3.655679",\
+ "0.491381, 0.762750, 1.024109, 1.460966, 2.334005",\
+ "0.558271, 0.829641, 1.091006, 1.527872, 2.400932",\
+ "0.674699, 0.946069, 1.207438, 1.644312, 2.517388",\
+ "0.994367, 1.265738, 1.527106, 1.963982, 2.837059",\
+ "1.849586, 2.120956, 2.382320, 2.819183, 3.692237",\
+ "0.819578, 1.126098, 1.375669, 1.810266, 2.679461",\
+ "0.886469, 1.192990, 1.442565, 1.877173, 2.746387",\
+ "1.002896, 1.309418, 1.558997, 1.993613, 2.862844",\
+ "1.322564, 1.629086, 1.878666, 2.313282, 3.182515",\
+ "2.177784, 2.484305, 2.733880, 3.168484, 4.037693");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\
+ "2.441330, 2.441331, 2.441334, 2.441343, 2.441361");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.262934, 0.448489, 0.641595, 0.948297, 1.539521",\
+ "0.294346, 0.479902, 0.673008, 0.979711, 1.570936",\
+ "0.346992, 0.532548, 0.725656, 1.032361, 1.623593",\
+ "0.489407, 0.674962, 0.868069, 1.174772, 1.765997",\
+ "0.868050, 1.053605, 1.246711, 1.553412, 2.144632",\
+ "0.322845, 0.508317, 0.701440, 1.008066, 1.599138",\
+ "0.354258, 0.539729, 0.732853, 1.039480, 1.630553",\
+ "0.406904, 0.592376, 0.785500, 1.092130, 1.683210",\
+ "0.549319, 0.734790, 0.927914, 1.234540, 1.825614",\
+ "0.927962, 1.113433, 1.306556, 1.613180, 2.204249",\
+ "0.455621, 0.640568, 0.833323, 1.139923, 1.730945",\
+ "0.487034, 0.671981, 0.864736, 1.171337, 1.762361",\
+ "0.539679, 0.724627, 0.917383, 1.223988, 1.815017",\
+ "0.682094, 0.867041, 1.059797, 1.366398, 1.957422",\
+ "1.060737, 1.245684, 1.438439, 1.745038, 2.336057",\
+ "0.488779, 0.673866, 0.866553, 1.173003, 1.763806",\
+ "0.520192, 0.705279, 0.897966, 1.204417, 1.795222",\
+ "0.572837, 0.757925, 0.950613, 1.257067, 1.847878",\
+ "0.715252, 0.900339, 1.093027, 1.399478, 1.990283",\
+ "1.093896, 1.278982, 1.471669, 1.778118, 2.368918",\
+ "0.790171, 0.979313, 1.170216, 1.476207, 2.066113",\
+ "0.821584, 1.010726, 1.201629, 1.507621, 2.097529",\
+ "0.874230, 1.063372, 1.254276, 1.560271, 2.150186",\
+ "1.016645, 1.205787, 1.396689, 1.702681, 2.292590",\
+ "1.395288, 1.584430, 1.775331, 2.081321, 2.671225");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\
+ "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180432",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\
+ "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180432",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\
+ "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180432",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\
+ "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180433",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\
+ "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\
+ "0.180378, 0.180379, 0.180385, 0.180400, 0.180433",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091687, 1.091683, 1.091668, 1.091627, 1.091540");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[4]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "970002.000000, 970002.062500, 970002.187500, 970002.500000, 970003.375000",\
+ "970002.125000, 970002.187500, 970002.312500, 970002.625000, 970003.500000",\
+ "970002.250000, 970002.312500, 970002.437500, 970002.750000, 970003.625000",\
+ "970002.250000, 970002.312500, 970002.437500, 970002.750000, 970003.625000",\
+ "970002.625000, 970002.687500, 970002.812500, 970003.125000, 970004.000000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\
+ "0.073824, 0.189425, 0.393252, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "970001.187500, 970001.187500, 970001.250000, 970001.437500, 970001.812500",\
+ "970001.312500, 970001.312500, 970001.375000, 970001.562500, 970001.937500",\
+ "970001.312500, 970001.312500, 970001.375000, 970001.562500, 970001.937500",\
+ "970001.437500, 970001.437500, 970001.500000, 970001.687500, 970002.062500",\
+ "970001.687500, 970001.687500, 970001.750000, 970001.937500, 970002.312500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\
+ "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\
+ "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\
+ "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\
+ "0.643636, 0.699058, 0.793671, 1.054205, 1.742813");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\
+ "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\
+ "0.054820, 0.149920, 0.315966, 0.770514, 1.988361");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\
+ "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\
+ "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\
+ "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\
+ "0.630702, 0.654723, 0.683267, 0.752219, 0.936438");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\
+ "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.231764, 0.298665, 0.415101, 0.734770, 1.589978",\
+ "0.323073, 0.389976, 0.506413, 0.826082, 1.681288",\
+ "0.433906, 0.500813, 0.617254, 0.936923, 1.792124",\
+ "0.514021, 0.580932, 0.697376, 1.017045, 1.872241",\
+ "0.917338, 0.984292, 1.100771, 1.420444, 2.275589");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073036, 0.188928, 0.391836, 0.949092, 2.441339",\
+ "0.073037, 0.188930, 0.391839, 0.949098, 2.441340",\
+ "0.073040, 0.188938, 0.391851, 0.949124, 2.441344",\
+ "0.073043, 0.188945, 0.391861, 0.949145, 2.441347",\
+ "0.073075, 0.189019, 0.391969, 0.949375, 2.441386");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.336061, 0.367493, 0.420201, 0.562554, 0.941151",\
+ "0.422827, 0.454258, 0.506967, 0.649320, 1.027916",\
+ "0.529568, 0.561000, 0.613708, 0.756061, 1.134658",\
+ "0.742022, 0.773454, 0.826162, 0.968515, 1.347112",\
+ "1.127927, 1.159358, 1.212067, 1.354419, 1.733016");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039144, 0.090610, 0.180696, 0.429275, 1.090836");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.221966, 0.288856, 0.405284, 0.724952, 1.580171",\
+ "0.311631, 0.378522, 0.494949, 0.814617, 1.669837",\
+ "0.414337, 0.481231, 0.597661, 0.917329, 1.772546",\
+ "0.488653, 0.555550, 0.671983, 0.991651, 1.846864",\
+ "0.868804, 0.935731, 1.052188, 1.371858, 2.227036");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188915, 0.391815, 0.949015, 2.441330",\
+ "0.073032, 0.188915, 0.391815, 0.949022, 2.441330",\
+ "0.073032, 0.188916, 0.391818, 0.949053, 2.441332",\
+ "0.073033, 0.188921, 0.391826, 0.949069, 2.441335",\
+ "0.073055, 0.188972, 0.391900, 0.949227, 2.441361");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.247879, 0.279292, 0.331938, 0.474353, 0.852996",\
+ "0.337796, 0.369209, 0.421855, 0.564270, 0.942913",\
+ "0.451084, 0.482497, 0.535144, 0.677558, 1.056200",\
+ "0.662499, 0.693912, 0.746561, 0.888973, 1.267614",\
+ "1.032523, 1.063938, 1.116591, 1.258999, 1.637636");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180379, 0.429204, 1.091684",\
+ "0.039012, 0.090733, 0.180379, 0.429204, 1.091684",\
+ "0.039014, 0.090731, 0.180383, 0.429205, 1.091673",\
+ "0.039019, 0.090727, 0.180394, 0.429207, 1.091643",\
+ "0.039029, 0.090717, 0.180418, 0.429213, 1.091579");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "fla_obs_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\
+ "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\
+ "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\
+ "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\
+ "0.629434, 0.713469, 0.835221, 1.155234, 2.004311");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\
+ "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\
+ "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\
+ "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\
+ "0.099054, 0.205738, 0.390315, 0.940320, 2.425200");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\
+ "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\
+ "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\
+ "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\
+ "0.668936, 0.733428, 0.809479, 0.962224, 1.340585");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\
+ "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\
+ "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\
+ "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\
+ "0.118581, 0.174509, 0.240947, 0.445113, 1.092793");
+ }
+
+ } /* end of arc fla_obs_i[4]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "fla_obs_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\
+ "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\
+ "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\
+ "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\
+ "0.610985, 0.691263, 0.810230, 1.128954, 1.977655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\
+ "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\
+ "0.093347, 0.198994, 0.384563, 0.939701, 2.425563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\
+ "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\
+ "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\
+ "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\
+ "0.615736, 0.679130, 0.754042, 0.905113, 1.283136");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\
+ "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\
+ "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\
+ "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\
+ "0.116096, 0.171326, 0.236992, 0.441817, 1.092511");
+ }
+
+ } /* end of arc fla_obs_i[4]_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\
+ "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\
+ "0.521995, 0.588899, 0.705338, 1.025007, 1.880211",\
+ "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\
+ "1.134534, 1.201443, 1.317885, 1.637554, 2.492753");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073042, 0.188941, 0.391856, 0.949133, 2.441345");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\
+ "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\
+ "0.579334, 0.610765, 0.663474, 0.805826, 1.184423",\
+ "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\
+ "1.246693, 1.278125, 1.330833, 1.473186, 1.851783");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\
+ "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\
+ "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\
+ "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\
+ "1.077990, 1.144880, 1.261307, 1.580975, 2.436195");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.392866, 0.424278, 0.476924, 0.619339, 0.997982",\
+ "0.410271, 0.441684, 0.494330, 0.636744, 1.015388",\
+ "0.482841, 0.514253, 0.566899, 0.709314, 1.087957",\
+ "0.595475, 0.626888, 0.679534, 0.821949, 1.200592",\
+ "1.122503, 1.153916, 1.206562, 1.348976, 1.727620");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\
+ "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\
+ "0.531700, 0.563132, 0.615840, 0.758193, 1.136790",\
+ "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\
+ "1.286840, 1.318272, 1.370980, 1.513333, 1.891930");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\
+ "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\
+ "0.754790, 0.821694, 0.938133, 1.257802, 2.113006",\
+ "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\
+ "1.641748, 1.708657, 1.825099, 2.144769, 2.999968");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073042, 0.188941, 0.391856, 0.949133, 2.441345");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.284420, 0.315833, 0.368479, 0.510893, 0.889537",\
+ "0.308019, 0.339432, 0.392078, 0.534493, 0.913136",\
+ "0.380089, 0.411502, 0.464148, 0.606562, 0.985206",\
+ "0.506286, 0.537698, 0.590344, 0.732759, 1.111402",\
+ "1.081944, 1.113356, 1.166002, 1.308417, 1.687060");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.601029, 0.667919, 0.784346, 1.104014, 1.959234",\
+ "0.617835, 0.684726, 0.801153, 1.120821, 1.976041",\
+ "0.680343, 0.747234, 0.863661, 1.183329, 2.038548",\
+ "0.789694, 0.856584, 0.973011, 1.292679, 2.147899",\
+ "1.539211, 1.606101, 1.722528, 2.042196, 2.897416");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\
+ "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\
+ "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\
+ "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\
+ "0.975060, 1.010086, 1.063144, 1.205732, 1.584486");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\
+ "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\
+ "0.049347, 0.094034, 0.180868, 0.429355, 1.091896");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\
+ "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\
+ "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\
+ "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\
+ "1.319722, 1.387140, 1.503696, 1.823662, 2.678811");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\
+ "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\
+ "0.075399, 0.189282, 0.392442, 0.951039, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[4]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\
+ "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\
+ "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\
+ "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\
+ "0.945167, 0.979651, 1.032663, 1.175209, 1.553933");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\
+ "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\
+ "0.047820, 0.093501, 0.180675, 0.429352, 1.091629");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\
+ "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\
+ "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\
+ "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\
+ "1.312551, 1.379913, 1.496487, 1.816396, 2.671496");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\
+ "0.074954, 0.189124, 0.392388, 0.950917, 2.441454");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[4]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\
+ "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\
+ "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\
+ "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\
+ "1.108576, 1.175805, 1.292423, 1.612190, 2.467167");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\
+ "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\
+ "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\
+ "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\
+ "1.013269, 1.044421, 1.097036, 1.239541, 1.618177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\
+ "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\
+ "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\
+ "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\
+ "0.949078, 1.015776, 1.132136, 1.448920, 2.298678");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\
+ "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\
+ "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\
+ "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\
+ "0.909442, 0.940877, 0.993596, 1.135938, 1.514527");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\
+ "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\
+ "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\
+ "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\
+ "0.918190, 0.949342, 1.001956, 1.144462, 1.523098");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\
+ "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\
+ "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\
+ "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\
+ "1.006927, 1.073706, 1.190415, 1.507149, 2.356620");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\
+ "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\
+ "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\
+ "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\
+ "0.893831, 0.925076, 0.977718, 1.120154, 1.498834");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\
+ "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\
+ "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\
+ "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\
+ "1.002245, 1.068944, 1.185303, 1.502088, 2.351846");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\
+ "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\
+ "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\
+ "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\
+ "0.997007, 1.063817, 1.180658, 1.497372, 2.346736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\
+ "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\
+ "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\
+ "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\
+ "1.004117, 1.035227, 1.087829, 1.230366, 1.608983");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\
+ "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\
+ "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\
+ "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\
+ "0.957622, 1.024367, 1.140929, 1.457685, 2.307276");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\
+ "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\
+ "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\
+ "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\
+ "0.955028, 0.986237, 1.038869, 1.181331, 1.559995");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\
+ "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\
+ "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\
+ "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\
+ "0.961790, 0.996912, 1.049978, 1.192575, 1.571334");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\
+ "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\
+ "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\
+ "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\
+ "1.332501, 1.399969, 1.516508, 1.836528, 2.691724");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\
+ "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\
+ "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\
+ "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\
+ "0.931678, 0.966257, 1.019278, 1.161831, 1.540560");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\
+ "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\
+ "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\
+ "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\
+ "1.324350, 1.391756, 1.508316, 1.828270, 2.683409");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\
+ "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\
+ "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\
+ "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\
+ "0.876566, 0.943791, 1.060410, 1.380173, 2.235147");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\
+ "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\
+ "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\
+ "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\
+ "0.808201, 0.839636, 0.892354, 1.034697, 1.413287");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\
+ "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\
+ "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\
+ "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\
+ "0.852482, 0.919491, 1.036016, 1.355692, 2.210772");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\
+ "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\
+ "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\
+ "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\
+ "0.786063, 0.817479, 0.870138, 1.012540, 1.391174");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\
+ "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\
+ "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\
+ "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\
+ "0.984655, 1.015818, 1.068436, 1.210933, 1.589574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\
+ "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\
+ "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\
+ "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\
+ "1.273667, 1.340892, 1.457511, 1.777274, 2.632248");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\
+ "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\
+ "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\
+ "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\
+ "0.929777, 0.961193, 1.013852, 1.156254, 1.534888");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\
+ "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\
+ "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\
+ "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\
+ "1.131911, 1.198614, 1.314996, 1.631778, 2.481517");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\
+ "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\
+ "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\
+ "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\
+ "0.999580, 1.030743, 1.083361, 1.225858, 1.604500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\
+ "0.042004, 0.091469, 0.180867, 0.429340, 1.092504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\
+ "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\
+ "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\
+ "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\
+ "1.375793, 1.443018, 1.559637, 1.879400, 2.734374");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[4]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\
+ "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\
+ "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\
+ "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\
+ "0.825559, 0.856975, 0.909634, 1.052036, 1.430670");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039038, 0.090323, 0.180168, 0.428941, 1.091519");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\
+ "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\
+ "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\
+ "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\
+ "1.141953, 1.209132, 1.325766, 1.645481, 2.500414");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067601, 0.184550, 0.382483, 0.937044, 2.417691");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[4]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\
+ "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\
+ "0.789289, 0.856194, 0.972632, 1.292301, 2.147506",\
+ "0.881295, 0.948199, 1.064638, 1.384307, 2.239511",\
+ "1.366874, 1.433786, 1.550230, 1.869900, 2.725095");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073043, 0.188945, 0.391861, 0.949146, 2.441348");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\
+ "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\
+ "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\
+ "0.691218, 0.722650, 0.775358, 0.917711, 1.296308",\
+ "1.240839, 1.272271, 1.324979, 1.467332, 1.845928");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\
+ "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\
+ "0.727479, 0.794369, 0.910796, 1.230464, 2.085684",\
+ "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\
+ "1.269718, 1.336608, 1.453035, 1.772703, 2.627923");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.340324, 0.371736, 0.424382, 0.566797, 0.945440",\
+ "0.353670, 0.385083, 0.437728, 0.580143, 0.958786",\
+ "0.435082, 0.466495, 0.519140, 0.661555, 1.040198",\
+ "0.544387, 0.575800, 0.628446, 0.770861, 1.149504",\
+ "1.068007, 1.099420, 1.152066, 1.294481, 1.673124");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\
+ "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\
+ "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\
+ "0.714879, 0.746311, 0.799019, 0.941372, 1.319969",\
+ "1.235698, 1.267130, 1.319839, 1.462191, 1.840788");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\
+ "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\
+ "0.718674, 0.785579, 0.902017, 1.221686, 2.076890",\
+ "0.820628, 0.887532, 1.003971, 1.323640, 2.178844",\
+ "1.548479, 1.615391, 1.731835, 2.051504, 2.906700");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073043, 0.188945, 0.391861, 0.949146, 2.441348");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.305082, 0.336495, 0.389141, 0.531556, 0.910199",\
+ "0.321682, 0.353095, 0.405741, 0.548156, 0.926799",\
+ "0.400692, 0.432104, 0.484750, 0.627165, 1.005808",\
+ "0.527571, 0.558983, 0.611629, 0.754044, 1.132687",\
+ "1.082115, 1.113528, 1.166173, 1.308588, 1.687232");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\
+ "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\
+ "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\
+ "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\
+ "1.120855, 1.187745, 1.304172, 1.623840, 2.479060");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\
+ "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\
+ "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\
+ "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\
+ "1.355292, 1.422199, 1.538640, 1.858309, 2.713511");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073040, 0.188938, 0.391851, 0.949122, 2.441344");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\
+ "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\
+ "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\
+ "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\
+ "1.224584, 1.256016, 1.308724, 1.451077, 1.829674");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\
+ "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\
+ "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\
+ "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\
+ "1.307789, 1.374679, 1.491106, 1.810774, 2.665994");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.361796, 0.393209, 0.445854, 0.588269, 0.966913",\
+ "0.375252, 0.406665, 0.459311, 0.601726, 0.980369",\
+ "0.456673, 0.488086, 0.540731, 0.683146, 1.061790",\
+ "0.566647, 0.598060, 0.650706, 0.793121, 1.171764",\
+ "1.092083, 1.123496, 1.176142, 1.318556, 1.697200");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\
+ "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\
+ "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\
+ "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\
+ "1.187533, 1.218965, 1.271673, 1.414026, 1.792623");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.604133, 0.671037, 0.787476, 1.107145, 1.962349",\
+ "0.616822, 0.683727, 0.800165, 1.119834, 1.975038",\
+ "0.671505, 0.738410, 0.854848, 1.174517, 2.029721",\
+ "0.774589, 0.841493, 0.957932, 1.277601, 2.132805",\
+ "1.473004, 1.539911, 1.656352, 1.976021, 2.831222");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073040, 0.188938, 0.391851, 0.949122, 2.441344");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.284809, 0.316222, 0.368868, 0.511283, 0.889926",\
+ "0.301623, 0.333036, 0.385681, 0.528096, 0.906739",\
+ "0.380088, 0.411501, 0.464146, 0.606561, 0.985205",\
+ "0.509697, 0.541110, 0.593756, 0.736170, 1.114814",\
+ "1.092277, 1.123690, 1.176336, 1.318751, 1.697394");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091686");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\
+ "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\
+ "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\
+ "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\
+ "1.119877, 1.186768, 1.303195, 1.622863, 2.478083");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_inv_min*/
+
+ timing () {
+ related_pin : "otm_obs_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\
+ "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\
+ "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\
+ "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\
+ "0.695902, 0.774527, 0.893732, 1.214148, 2.069560");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\
+ "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\
+ "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\
+ "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\
+ "0.098084, 0.204137, 0.393542, 0.951076, 2.441498");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\
+ "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\
+ "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\
+ "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\
+ "0.825607, 0.870622, 0.930343, 1.075147, 1.454209");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\
+ "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\
+ "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\
+ "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\
+ "0.068556, 0.114740, 0.192215, 0.429716, 1.093122");
+ }
+
+ } /* end of arc otm_obs_i[4]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otm_obs_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\
+ "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\
+ "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\
+ "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\
+ "0.662107, 0.738115, 0.856688, 1.177023, 2.032395");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\
+ "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\
+ "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\
+ "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\
+ "0.092938, 0.200557, 0.393255, 0.950255, 2.441468");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\
+ "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\
+ "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\
+ "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\
+ "0.777508, 0.822171, 0.881623, 1.026340, 1.405392");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\
+ "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\
+ "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\
+ "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\
+ "0.067933, 0.113945, 0.191732, 0.429701, 1.093101");
+ }
+
+ } /* end of arc otm_obs_i[4]_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "otp_obs_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\
+ "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\
+ "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\
+ "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\
+ "0.699992, 0.780922, 0.900058, 1.218756, 2.067549");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\
+ "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\
+ "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\
+ "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\
+ "0.094401, 0.199857, 0.384817, 0.940410, 2.426093");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\
+ "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\
+ "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\
+ "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\
+ "0.820213, 0.870292, 0.933027, 1.077593, 1.455130");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\
+ "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\
+ "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\
+ "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\
+ "0.087354, 0.133744, 0.204884, 0.431205, 1.092443");
+ }
+
+ } /* end of arc otp_obs_i[4]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_obs_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\
+ "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\
+ "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\
+ "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\
+ "0.667813, 0.745674, 0.864272, 1.183300, 2.031636");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\
+ "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\
+ "0.089380, 0.196045, 0.384240, 0.939859, 2.423100");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\
+ "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\
+ "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\
+ "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\
+ "0.773733, 0.823401, 0.885774, 1.030256, 1.407808");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\
+ "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\
+ "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\
+ "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\
+ "0.086478, 0.132591, 0.204027, 0.431125, 1.092425");
+ }
+
+ } /* end of arc otp_obs_i[4]_ast2padmux_o[4]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "970001.062500, 970001.062500, 970001.125000, 970001.312500, 970001.687500",\
+ "970001.187500, 970001.187500, 970001.250000, 970001.437500, 970001.812500",\
+ "970001.187500, 970001.187500, 970001.250000, 970001.437500, 970001.812500",\
+ "970001.437500, 970001.437500, 970001.500000, 970001.687500, 970002.062500",\
+ "970001.687500, 970001.687500, 970001.750000, 970001.937500, 970002.312500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "970001.875000, 970001.937500, 970002.062500, 970002.375000, 970003.250000",\
+ "970002.000000, 970002.062500, 970002.187500, 970002.500000, 970003.375000",\
+ "970002.125000, 970002.187500, 970002.312500, 970002.625000, 970003.500000",\
+ "970002.375000, 970002.437500, 970002.562500, 970002.875000, 970003.750000",\
+ "970002.625000, 970002.687500, 970002.812500, 970003.125000, 970004.000000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[4]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\
+ "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\
+ "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\
+ "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\
+ "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\
+ "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\
+ "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[4]_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "590000.250000, 590000.312500, 590000.437500, 590000.750000, 590001.625000",\
+ "590000.375000, 590000.437500, 590000.562500, 590000.875000, 590001.750000",\
+ "590000.375000, 590000.437500, 590000.562500, 590000.875000, 590001.750000",\
+ "590000.500000, 590000.562500, 590000.687500, 590001.000000, 590001.875000",\
+ "590000.750000, 590000.812500, 590000.937500, 590001.250000, 590002.125000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "590000.812500, 590000.812500, 590000.875000, 590001.062500, 590001.437500",\
+ "590000.937500, 590000.937500, 590001.000000, 590001.187500, 590001.562500",\
+ "590001.062500, 590001.062500, 590001.125000, 590001.312500, 590001.687500",\
+ "590001.187500, 590001.187500, 590001.250000, 590001.437500, 590001.812500",\
+ "590001.562500, 590001.562500, 590001.625000, 590001.812500, 590002.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast2padmux_o[4]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "590000.187500, 590000.250000, 590000.375000, 590000.687500, 590001.562500",\
+ "590000.187500, 590000.250000, 590000.375000, 590000.687500, 590001.562500",\
+ "590000.312500, 590000.375000, 590000.500000, 590000.812500, 590001.687500",\
+ "590000.437500, 590000.500000, 590000.625000, 590000.937500, 590001.812500",\
+ "590000.687500, 590000.750000, 590000.875000, 590001.187500, 590002.062500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\
+ "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\
+ "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\
+ "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\
+ "0.067834, 0.184682, 0.382509, 0.937727, 2.417507");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "590000.812500, 590000.812500, 590000.875000, 590001.000000, 590001.437500",\
+ "590000.937500, 590000.937500, 590001.000000, 590001.125000, 590001.562500",\
+ "590001.062500, 590001.062500, 590001.125000, 590001.250000, 590001.687500",\
+ "590001.187500, 590001.187500, 590001.250000, 590001.375000, 590001.812500",\
+ "590001.437500, 590001.437500, 590001.500000, 590001.625000, 590002.062500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\
+ "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\
+ "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\
+ "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\
+ "0.039013, 0.090351, 0.180124, 0.429131, 1.091682");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast2padmux_o[4]_una_min*/
+
+} /* end of pin ast2padmux_o[4] */
+
+pin("ast2padmux_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.028584 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2padmux_o[3];
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_b_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.257031, 0.528778, 0.797030, 1.242767, 2.134242",\
+ "0.323932, 0.595681, 0.863940, 1.309691, 2.201193",\
+ "0.440368, 0.712118, 0.980382, 1.426145, 2.317669",\
+ "0.760037, 1.031787, 1.300052, 1.745815, 2.637342",\
+ "1.615245, 1.886993, 2.155250, 2.600997, 3.492491",\
+ "0.315617, 0.587294, 0.855812, 1.300474, 2.190349",\
+ "0.382518, 0.654197, 0.922722, 1.367397, 2.257300",\
+ "0.498954, 0.770634, 1.039164, 1.483851, 2.373776",\
+ "0.818623, 1.090303, 1.358834, 1.803522, 2.693449",\
+ "1.673831, 1.945509, 2.214032, 2.658703, 3.548597",\
+ "0.460207, 0.733101, 0.999707, 1.444229, 2.334082",\
+ "0.527108, 0.800004, 1.066617, 1.511152, 2.401032",\
+ "0.643544, 0.916442, 1.183060, 1.627606, 2.517509",\
+ "0.963213, 1.236110, 1.502729, 1.947277, 2.837182",\
+ "1.818421, 2.091316, 2.357927, 2.802459, 3.692330",\
+ "0.496168, 0.770865, 1.036627, 1.481020, 2.370640",\
+ "0.563069, 0.837768, 1.103536, 1.547944, 2.437591",\
+ "0.679505, 0.954206, 1.219979, 1.664398, 2.554067",\
+ "0.999174, 1.273875, 1.539648, 1.984068, 2.873740",\
+ "1.854382, 2.129080, 2.394846, 2.839250, 3.728889",\
+ "0.825262, 1.134787, 1.388262, 1.830277, 2.716096",\
+ "0.892164, 1.201690, 1.455172, 1.897201, 2.783047",\
+ "1.008600, 1.318128, 1.571615, 2.013655, 2.899523",\
+ "1.328269, 1.637797, 1.891284, 2.333325, 3.219196",\
+ "2.183476, 2.493002, 2.746482, 3.188507, 4.074345");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073038, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188932, 0.188943, 0.188966, 0.189013",\
+ "0.391836, 0.391843, 0.391858, 0.391892, 0.391961",\
+ "0.949092, 0.949105, 0.949137, 0.949210, 0.949357",\
+ "2.441339, 2.441341, 2.441346, 2.441358, 2.441383");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.308725, 0.491796, 0.685627, 0.996163, 1.596700",\
+ "0.340157, 0.523228, 0.717058, 1.027595, 1.628132",\
+ "0.392865, 0.575936, 0.769767, 1.080304, 1.680844",\
+ "0.535218, 0.718289, 0.912119, 1.222656, 1.823194",\
+ "0.913815, 1.096886, 1.290716, 1.601252, 2.201788",\
+ "0.368637, 0.551695, 0.745581, 1.055944, 1.656317",\
+ "0.400068, 0.583126, 0.777012, 1.087376, 1.687749",\
+ "0.452777, 0.635835, 0.829721, 1.140085, 1.740461",\
+ "0.595130, 0.778187, 0.972073, 1.282437, 1.882811",\
+ "0.973727, 1.156784, 1.350670, 1.661033, 2.261405",\
+ "0.501379, 0.683946, 0.877464, 1.187801, 1.788124",\
+ "0.532811, 0.715378, 0.908895, 1.219233, 1.819557",\
+ "0.585519, 0.768086, 0.961603, 1.271942, 1.872268",\
+ "0.727872, 0.910439, 1.103956, 1.414294, 2.014618",\
+ "1.106469, 1.289036, 1.482553, 1.792891, 2.393212",\
+ "0.534516, 0.717073, 0.910588, 1.220754, 1.820733",\
+ "0.565947, 0.748505, 0.942020, 1.252186, 1.852165",\
+ "0.618656, 0.801213, 0.994728, 1.304895, 1.904876",\
+ "0.761009, 0.943566, 1.137081, 1.447247, 2.047226",\
+ "1.139605, 1.322163, 1.515678, 1.825843, 2.425821",\
+ "0.835592, 1.022294, 1.214223, 1.523770, 2.122581",\
+ "0.867023, 1.053726, 1.245655, 1.555202, 2.154014",\
+ "0.919731, 1.106434, 1.298363, 1.607911, 2.206725",\
+ "1.062084, 1.248787, 1.440716, 1.750263, 2.349075",\
+ "1.440681, 1.627384, 1.819313, 2.128859, 2.727669");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_b_o[2]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.252558, 0.520745, 0.784515, 1.222569, 2.097608",\
+ "0.319449, 0.587637, 0.851411, 1.289475, 2.164534",\
+ "0.435876, 0.704065, 0.967843, 1.405915, 2.280990",\
+ "0.755544, 1.023733, 1.287511, 1.725584, 2.600661",\
+ "1.610764, 1.878952, 2.142725, 2.580786, 3.455839",\
+ "0.311120, 0.579252, 0.843280, 1.280275, 2.153714",\
+ "0.378011, 0.646143, 0.910176, 1.347182, 2.220640",\
+ "0.494438, 0.762572, 1.026608, 1.463622, 2.337097",\
+ "0.814106, 1.082240, 1.346276, 1.783291, 2.656767",\
+ "1.669326, 1.937458, 2.201490, 2.638493, 3.511946",\
+ "0.455460, 0.724999, 0.987167, 1.424079, 2.297447",\
+ "0.522351, 0.791891, 1.054064, 1.490985, 2.364373",\
+ "0.638778, 0.908319, 1.170496, 1.607426, 2.480830",\
+ "0.958446, 1.227987, 1.490164, 1.927095, 2.800500",\
+ "1.813666, 2.083206, 2.345378, 2.782297, 3.655679",\
+ "0.491341, 0.762735, 1.024086, 1.460950, 2.334005",\
+ "0.558231, 0.829626, 1.090982, 1.527856, 2.400931",\
+ "0.674659, 0.946054, 1.207414, 1.644296, 2.517388",\
+ "0.994327, 1.265722, 1.527082, 1.963966, 2.837059",\
+ "1.849546, 2.120941, 2.382296, 2.819168, 3.692237",\
+ "0.819555, 1.126080, 1.375645, 1.810251, 2.679461",\
+ "0.886446, 1.192972, 1.442542, 1.877157, 2.746387",\
+ "1.002873, 1.309400, 1.558974, 1.993597, 2.862844",\
+ "1.322541, 1.629068, 1.878642, 2.313266, 3.182515",\
+ "2.177761, 2.484287, 2.733856, 3.168468, 4.037693");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\
+ "2.441330, 2.441331, 2.441334, 2.441343, 2.441361");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.262934, 0.448489, 0.641595, 0.948064, 1.538713",\
+ "0.294346, 0.479902, 0.673008, 0.979478, 1.570129",\
+ "0.346992, 0.532548, 0.725656, 1.032128, 1.622785",\
+ "0.489407, 0.674962, 0.868069, 1.174539, 1.765190",\
+ "0.868050, 1.053605, 1.246711, 1.553179, 2.143825",\
+ "0.322845, 0.508317, 0.701440, 1.007833, 1.598330",\
+ "0.354258, 0.539729, 0.732853, 1.039247, 1.629746",\
+ "0.406904, 0.592376, 0.785500, 1.091897, 1.682402",\
+ "0.549319, 0.734790, 0.927914, 1.234307, 1.824806",\
+ "0.927962, 1.113433, 1.306556, 1.612947, 2.203442",\
+ "0.455621, 0.640568, 0.833323, 1.139690, 1.730137",\
+ "0.487034, 0.671981, 0.864736, 1.171104, 1.761553",\
+ "0.539679, 0.724627, 0.917383, 1.223754, 1.814209",\
+ "0.682094, 0.867041, 1.059797, 1.366165, 1.956614",\
+ "1.060737, 1.245684, 1.438439, 1.744805, 2.335249",\
+ "0.488779, 0.673866, 0.866553, 1.172770, 1.762998",\
+ "0.520192, 0.705279, 0.897966, 1.204184, 1.794413",\
+ "0.572837, 0.757925, 0.950613, 1.256834, 1.847070",\
+ "0.715252, 0.900339, 1.093027, 1.399244, 1.989474",\
+ "1.093896, 1.278982, 1.471669, 1.777884, 2.368110",\
+ "0.790171, 0.979313, 1.170216, 1.475973, 2.065303",\
+ "0.821584, 1.010726, 1.201629, 1.507387, 2.096719",\
+ "0.874230, 1.063372, 1.254276, 1.560037, 2.149375",\
+ "1.016645, 1.205787, 1.396689, 1.702447, 2.291780",\
+ "1.395288, 1.584430, 1.775331, 2.081088, 2.670415");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\
+ "0.180378, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091687, 1.091683, 1.091668, 1.091628, 1.091545");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\
+ "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\
+ "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\
+ "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\
+ "0.073824, 0.189425, 0.393252, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.562500, 380001.593750, 380001.656250, 380001.781250, 380002.156250",\
+ "380001.656250, 380001.687500, 380001.750000, 380001.875000, 380002.250000",\
+ "380001.750000, 380001.781250, 380001.843750, 380001.968750, 380002.343750",\
+ "380001.812500, 380001.843750, 380001.906250, 380002.031250, 380002.406250",\
+ "380002.156250, 380002.187500, 380002.250000, 380002.375000, 380002.750000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\
+ "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\
+ "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\
+ "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\
+ "0.643636, 0.699058, 0.793671, 1.054205, 1.742813");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\
+ "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\
+ "0.054820, 0.149920, 0.315966, 0.770514, 1.988361");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\
+ "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\
+ "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\
+ "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\
+ "0.630702, 0.654723, 0.683267, 0.752219, 0.936438");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\
+ "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "fla_obs_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\
+ "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\
+ "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\
+ "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\
+ "0.629434, 0.713469, 0.835221, 1.155234, 2.004311");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\
+ "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\
+ "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\
+ "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\
+ "0.099054, 0.205738, 0.390315, 0.940320, 2.425200");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\
+ "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\
+ "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\
+ "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\
+ "0.668936, 0.733428, 0.809479, 0.962224, 1.340585");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\
+ "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\
+ "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\
+ "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\
+ "0.118581, 0.174509, 0.240947, 0.445113, 1.092793");
+ }
+
+ } /* end of arc fla_obs_i[3]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "fla_obs_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\
+ "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\
+ "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\
+ "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\
+ "0.610985, 0.691263, 0.810230, 1.128954, 1.977655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\
+ "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\
+ "0.093347, 0.198994, 0.384563, 0.939701, 2.425563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\
+ "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\
+ "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\
+ "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\
+ "0.615736, 0.679130, 0.754042, 0.905113, 1.283136");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\
+ "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\
+ "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\
+ "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\
+ "0.116096, 0.171326, 0.236992, 0.441817, 1.092511");
+ }
+
+ } /* end of arc fla_obs_i[3]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\
+ "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\
+ "0.522299, 0.589203, 0.705642, 1.025311, 1.880515",\
+ "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\
+ "1.134534, 1.201443, 1.317885, 1.637554, 2.492753");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073042, 0.188941, 0.391856, 0.949133, 2.441345");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\
+ "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\
+ "0.579305, 0.610737, 0.663445, 0.805798, 1.184395",\
+ "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\
+ "1.248357, 1.279789, 1.332497, 1.474850, 1.853447");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\
+ "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\
+ "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\
+ "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\
+ "1.077990, 1.144880, 1.261307, 1.580975, 2.436195");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.392762, 0.424174, 0.476820, 0.619235, 0.997878",\
+ "0.410167, 0.441580, 0.494226, 0.636641, 1.015284",\
+ "0.482737, 0.514149, 0.566795, 0.709210, 1.087853",\
+ "0.595371, 0.626784, 0.679430, 0.821845, 1.200488",\
+ "1.122399, 1.153812, 1.206458, 1.348872, 1.727516");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\
+ "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\
+ "0.531672, 0.563103, 0.615812, 0.758164, 1.136761",\
+ "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\
+ "1.288504, 1.319936, 1.372644, 1.514997, 1.893594");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\
+ "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\
+ "0.755094, 0.821998, 0.938437, 1.258106, 2.113310",\
+ "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\
+ "1.641748, 1.708657, 1.825099, 2.144769, 2.999968");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073042, 0.188941, 0.391856, 0.949133, 2.441345");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262392, 0.293804, 0.346450, 0.488865, 0.867508",\
+ "0.286002, 0.317414, 0.370060, 0.512475, 0.891118",\
+ "0.357340, 0.388753, 0.441399, 0.583814, 0.962457",\
+ "0.477148, 0.508560, 0.561206, 0.703621, 1.082264",\
+ "1.022245, 1.053658, 1.106303, 1.248718, 1.627362");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.582342, 0.649232, 0.765660, 1.085328, 1.940547",\
+ "0.599034, 0.665924, 0.782351, 1.102020, 1.957239",\
+ "0.661428, 0.728319, 0.844746, 1.164414, 2.019634",\
+ "0.770818, 0.837708, 0.954135, 1.273803, 2.129023",\
+ "1.507966, 1.574856, 1.691283, 2.010951, 2.866171");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\
+ "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\
+ "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\
+ "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\
+ "0.975060, 1.010086, 1.063144, 1.205732, 1.584486");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\
+ "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\
+ "0.049347, 0.094034, 0.180868, 0.429355, 1.091896");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\
+ "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\
+ "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\
+ "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\
+ "1.319722, 1.387140, 1.503696, 1.823662, 2.678811");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\
+ "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\
+ "0.075399, 0.189282, 0.392442, 0.951039, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[3]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\
+ "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\
+ "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\
+ "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\
+ "0.945167, 0.979651, 1.032663, 1.175209, 1.553933");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\
+ "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\
+ "0.047820, 0.093501, 0.180675, 0.429352, 1.091629");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\
+ "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\
+ "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\
+ "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\
+ "1.312551, 1.379913, 1.496487, 1.816396, 2.671496");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\
+ "0.074954, 0.189124, 0.392388, 0.950917, 2.441454");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[3]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\
+ "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\
+ "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\
+ "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\
+ "1.108576, 1.175805, 1.292423, 1.612190, 2.467167");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\
+ "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\
+ "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\
+ "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\
+ "1.013269, 1.044421, 1.097036, 1.239541, 1.618177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\
+ "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\
+ "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\
+ "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\
+ "0.949078, 1.015776, 1.132136, 1.448920, 2.298678");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\
+ "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\
+ "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\
+ "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\
+ "0.909442, 0.940877, 0.993596, 1.135938, 1.514527");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\
+ "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\
+ "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\
+ "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\
+ "0.918190, 0.949342, 1.001956, 1.144462, 1.523098");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\
+ "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\
+ "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\
+ "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\
+ "1.006927, 1.073706, 1.190415, 1.507149, 2.356620");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\
+ "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\
+ "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\
+ "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\
+ "0.893831, 0.925076, 0.977718, 1.120154, 1.498834");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\
+ "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\
+ "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\
+ "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\
+ "1.002245, 1.068944, 1.185303, 1.502088, 2.351846");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\
+ "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\
+ "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\
+ "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\
+ "0.997007, 1.063817, 1.180658, 1.497372, 2.346736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\
+ "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\
+ "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\
+ "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\
+ "1.004117, 1.035227, 1.087829, 1.230366, 1.608983");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\
+ "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\
+ "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\
+ "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\
+ "0.957622, 1.024367, 1.140929, 1.457685, 2.307276");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\
+ "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\
+ "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\
+ "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\
+ "0.955028, 0.986237, 1.038869, 1.181331, 1.559995");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\
+ "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\
+ "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\
+ "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\
+ "0.961790, 0.996912, 1.049978, 1.192575, 1.571334");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\
+ "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\
+ "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\
+ "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\
+ "1.332501, 1.399969, 1.516508, 1.836528, 2.691724");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\
+ "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\
+ "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\
+ "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\
+ "0.931678, 0.966257, 1.019278, 1.161831, 1.540560");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\
+ "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\
+ "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\
+ "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\
+ "1.324350, 1.391756, 1.508316, 1.828270, 2.683409");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\
+ "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\
+ "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\
+ "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\
+ "0.876566, 0.943791, 1.060410, 1.380173, 2.235147");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\
+ "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\
+ "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\
+ "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\
+ "0.808201, 0.839636, 0.892354, 1.034697, 1.413287");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\
+ "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\
+ "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\
+ "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\
+ "0.852482, 0.919491, 1.036016, 1.355692, 2.210772");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\
+ "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\
+ "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\
+ "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\
+ "0.786063, 0.817479, 0.870138, 1.012540, 1.391174");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\
+ "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\
+ "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\
+ "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\
+ "0.984655, 1.015818, 1.068436, 1.210933, 1.589574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\
+ "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\
+ "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\
+ "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\
+ "1.273667, 1.340892, 1.457511, 1.777274, 2.632248");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\
+ "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\
+ "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\
+ "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\
+ "0.929777, 0.961193, 1.013852, 1.156254, 1.534888");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\
+ "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\
+ "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\
+ "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\
+ "1.131911, 1.198614, 1.314996, 1.631778, 2.481517");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\
+ "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\
+ "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\
+ "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\
+ "0.999580, 1.030743, 1.083361, 1.225858, 1.604500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\
+ "0.042004, 0.091469, 0.180867, 0.429340, 1.092504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\
+ "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\
+ "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\
+ "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\
+ "1.375793, 1.443018, 1.559637, 1.879400, 2.734374");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[3]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\
+ "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\
+ "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\
+ "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\
+ "0.825559, 0.856975, 0.909634, 1.052036, 1.430670");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039038, 0.090323, 0.180168, 0.428941, 1.091519");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\
+ "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\
+ "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\
+ "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\
+ "1.141953, 1.209132, 1.325766, 1.645481, 2.500414");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067601, 0.184550, 0.382483, 0.937044, 2.417691");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[3]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\
+ "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\
+ "0.789396, 0.856300, 0.972739, 1.292408, 2.147612",\
+ "0.881867, 0.948772, 1.065210, 1.384879, 2.240083",\
+ "1.366874, 1.433786, 1.550230, 1.869900, 2.725095");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073043, 0.188945, 0.391861, 0.949146, 2.441348");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\
+ "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\
+ "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\
+ "0.691204, 0.722635, 0.775344, 0.917696, 1.296293",\
+ "1.242374, 1.273805, 1.326514, 1.468867, 1.847463");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\
+ "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\
+ "0.727539, 0.794429, 0.910857, 1.230525, 2.085744",\
+ "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\
+ "1.269718, 1.336608, 1.453035, 1.772703, 2.627923");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.339768, 0.371181, 0.423827, 0.566242, 0.944885",\
+ "0.353114, 0.384527, 0.437173, 0.579588, 0.958231",\
+ "0.435092, 0.466504, 0.519150, 0.661565, 1.040208",\
+ "0.544311, 0.575724, 0.628370, 0.770784, 1.149428",\
+ "1.067931, 1.099343, 1.151989, 1.294404, 1.673047");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\
+ "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\
+ "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\
+ "0.714865, 0.746296, 0.799004, 0.941357, 1.319954",\
+ "1.237234, 1.268665, 1.321373, 1.463726, 1.842323");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\
+ "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\
+ "0.718781, 0.785685, 0.902124, 1.221793, 2.076997",\
+ "0.821201, 0.888105, 1.004544, 1.324213, 2.179417",\
+ "1.548479, 1.615391, 1.731835, 2.051504, 2.906700");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073043, 0.188945, 0.391861, 0.949146, 2.441348");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.267796, 0.299208, 0.351854, 0.494269, 0.872912",\
+ "0.284541, 0.315954, 0.368600, 0.511015, 0.889658",\
+ "0.362798, 0.394211, 0.446856, 0.589271, 0.967914",\
+ "0.486677, 0.518090, 0.570736, 0.713151, 1.091794",\
+ "1.055266, 1.086678, 1.139324, 1.281739, 1.660382");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\
+ "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\
+ "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\
+ "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\
+ "1.120855, 1.187745, 1.304172, 1.623840, 2.479060");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\
+ "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\
+ "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\
+ "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\
+ "1.358120, 1.425029, 1.541471, 1.861141, 2.716340");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073041, 0.188941, 0.391855, 0.949133, 2.441345");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\
+ "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\
+ "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\
+ "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\
+ "1.229663, 1.261095, 1.313803, 1.456156, 1.834753");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\
+ "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\
+ "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\
+ "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\
+ "1.307789, 1.374679, 1.491106, 1.810774, 2.665994");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.361699, 0.393111, 0.445757, 0.588172, 0.966815",\
+ "0.375155, 0.406568, 0.459214, 0.601628, 0.980272",\
+ "0.456576, 0.487988, 0.540634, 0.683049, 1.061692",\
+ "0.566550, 0.597963, 0.650609, 0.793024, 1.171667",\
+ "1.091986, 1.123399, 1.176044, 1.318459, 1.697102");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\
+ "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\
+ "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\
+ "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\
+ "1.192613, 1.224045, 1.276753, 1.419106, 1.797703");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.606303, 0.673207, 0.789646, 1.109315, 1.964519",\
+ "0.618992, 0.685897, 0.802335, 1.122004, 1.977208",\
+ "0.673763, 0.740668, 0.857106, 1.176775, 2.031980",\
+ "0.776802, 0.843707, 0.960145, 1.279814, 2.135018",\
+ "1.483718, 1.550627, 1.667069, 1.986738, 2.841937");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073041, 0.188941, 0.391855, 0.949133, 2.441345");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262699, 0.294112, 0.346758, 0.489173, 0.867816",\
+ "0.279513, 0.310926, 0.363572, 0.505987, 0.884630",\
+ "0.357852, 0.389264, 0.441910, 0.584325, 0.962968",\
+ "0.480383, 0.511796, 0.564441, 0.706856, 1.085500",\
+ "1.037548, 1.068961, 1.121607, 1.264022, 1.642665");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\
+ "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\
+ "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\
+ "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\
+ "1.119877, 1.186768, 1.303195, 1.622863, 2.478083");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_inv_min*/
+
+ timing () {
+ related_pin : "otm_obs_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\
+ "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\
+ "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\
+ "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\
+ "0.695902, 0.774527, 0.893732, 1.214148, 2.069560");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\
+ "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\
+ "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\
+ "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\
+ "0.098084, 0.204137, 0.393542, 0.951076, 2.441498");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\
+ "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\
+ "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\
+ "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\
+ "0.825607, 0.870622, 0.930343, 1.075147, 1.454209");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\
+ "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\
+ "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\
+ "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\
+ "0.068556, 0.114740, 0.192215, 0.429716, 1.093122");
+ }
+
+ } /* end of arc otm_obs_i[3]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otm_obs_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\
+ "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\
+ "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\
+ "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\
+ "0.662107, 0.738115, 0.856688, 1.177023, 2.032395");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\
+ "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\
+ "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\
+ "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\
+ "0.092938, 0.200557, 0.393255, 0.950255, 2.441468");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\
+ "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\
+ "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\
+ "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\
+ "0.777508, 0.822171, 0.881623, 1.026340, 1.405392");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\
+ "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\
+ "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\
+ "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\
+ "0.067933, 0.113945, 0.191732, 0.429701, 1.093101");
+ }
+
+ } /* end of arc otm_obs_i[3]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "otp_obs_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\
+ "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\
+ "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\
+ "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\
+ "0.699992, 0.780922, 0.900058, 1.218756, 2.067549");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\
+ "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\
+ "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\
+ "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\
+ "0.094401, 0.199857, 0.384817, 0.940410, 2.426093");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\
+ "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\
+ "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\
+ "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\
+ "0.820213, 0.870292, 0.933027, 1.077593, 1.455130");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\
+ "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\
+ "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\
+ "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\
+ "0.087354, 0.133744, 0.204884, 0.431205, 1.092443");
+ }
+
+ } /* end of arc otp_obs_i[3]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_obs_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\
+ "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\
+ "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\
+ "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\
+ "0.667813, 0.745674, 0.864272, 1.183300, 2.031636");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\
+ "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\
+ "0.089380, 0.196045, 0.384240, 0.939859, 2.423100");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\
+ "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\
+ "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\
+ "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\
+ "0.773733, 0.823401, 0.885774, 1.030256, 1.407808");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\
+ "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\
+ "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\
+ "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\
+ "0.086478, 0.132591, 0.204027, 0.431125, 1.092425");
+ }
+
+ } /* end of arc otp_obs_i[3]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "379999.875000, 379999.937500, 380000.062500, 380000.375000, 380001.218750",\
+ "379999.968750, 380000.031250, 380000.156250, 380000.468750, 380001.312500",\
+ "380000.062500, 380000.125000, 380000.250000, 380000.562500, 380001.406250",\
+ "380000.218750, 380000.281250, 380000.406250, 380000.718750, 380001.562500",\
+ "380000.468750, 380000.531250, 380000.656250, 380000.968750, 380001.812500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.468750, 380001.500000, 380001.562500, 380001.687500, 380002.062500",\
+ "380001.562500, 380001.593750, 380001.656250, 380001.781250, 380002.156250",\
+ "380001.687500, 380001.718750, 380001.781250, 380001.906250, 380002.281250",\
+ "380001.875000, 380001.906250, 380001.968750, 380002.093750, 380002.468750",\
+ "380002.187500, 380002.218750, 380002.281250, 380002.406250, 380002.781250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "379999.843750, 379999.906250, 380000.031250, 380000.343750, 380001.187500",\
+ "379999.937500, 380000.000000, 380000.125000, 380000.437500, 380001.281250",\
+ "380000.000000, 380000.062500, 380000.187500, 380000.500000, 380001.343750",\
+ "380000.156250, 380000.218750, 380000.343750, 380000.656250, 380001.500000",\
+ "380000.375000, 380000.437500, 380000.562500, 380000.875000, 380001.718750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.375000, 380001.406250, 380001.437500, 380001.593750, 380001.968750",\
+ "380001.468750, 380001.500000, 380001.531250, 380001.687500, 380002.062500",\
+ "380001.562500, 380001.593750, 380001.625000, 380001.781250, 380002.156250",\
+ "380001.750000, 380001.781250, 380001.812500, 380001.968750, 380002.343750",\
+ "380002.000000, 380002.031250, 380002.062500, 380002.218750, 380002.593750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\
+ "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\
+ "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\
+ "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\
+ "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\
+ "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\
+ "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\
+ "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\
+ "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\
+ "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_inv_min*/
+
+} /* end of pin ast2padmux_o[3] */
+
+pin("ast2padmux_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.028584 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2padmux_o[2];
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_b_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.257031, 0.528778, 0.797030, 1.242767, 2.134242",\
+ "0.323932, 0.595681, 0.863940, 1.309691, 2.201193",\
+ "0.440368, 0.712118, 0.980382, 1.426145, 2.317669",\
+ "0.760037, 1.031787, 1.300052, 1.745815, 2.637342",\
+ "1.615245, 1.886993, 2.155250, 2.600997, 3.492491",\
+ "0.315617, 0.587294, 0.855812, 1.300474, 2.190349",\
+ "0.382518, 0.654197, 0.922722, 1.367397, 2.257300",\
+ "0.498954, 0.770634, 1.039164, 1.483851, 2.373776",\
+ "0.818623, 1.090303, 1.358834, 1.803522, 2.693449",\
+ "1.673831, 1.945509, 2.214032, 2.658703, 3.548597",\
+ "0.460207, 0.733101, 0.999707, 1.444229, 2.334082",\
+ "0.527108, 0.800004, 1.066617, 1.511152, 2.401032",\
+ "0.643544, 0.916442, 1.183060, 1.627606, 2.517509",\
+ "0.963213, 1.236110, 1.502729, 1.947277, 2.837182",\
+ "1.818421, 2.091316, 2.357927, 2.802459, 3.692330",\
+ "0.496168, 0.770865, 1.036627, 1.481020, 2.370640",\
+ "0.563069, 0.837768, 1.103536, 1.547944, 2.437591",\
+ "0.679505, 0.954206, 1.219979, 1.664398, 2.554067",\
+ "0.999174, 1.273875, 1.539648, 1.984068, 2.873740",\
+ "1.854382, 2.129080, 2.394846, 2.839250, 3.728889",\
+ "0.825262, 1.134787, 1.388262, 1.830277, 2.716096",\
+ "0.892164, 1.201690, 1.455172, 1.897201, 2.783047",\
+ "1.008600, 1.318128, 1.571615, 2.013655, 2.899523",\
+ "1.328269, 1.637797, 1.891284, 2.333325, 3.219196",\
+ "2.183476, 2.493002, 2.746482, 3.188507, 4.074345");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073038, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188932, 0.188943, 0.188966, 0.189013",\
+ "0.391836, 0.391843, 0.391858, 0.391892, 0.391961",\
+ "0.949092, 0.949105, 0.949137, 0.949210, 0.949357",\
+ "2.441339, 2.441341, 2.441346, 2.441358, 2.441383");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.308725, 0.491796, 0.685627, 0.996163, 1.596700",\
+ "0.340157, 0.523228, 0.717058, 1.027595, 1.628132",\
+ "0.392865, 0.575936, 0.769767, 1.080304, 1.680844",\
+ "0.535218, 0.718289, 0.912119, 1.222656, 1.823194",\
+ "0.913815, 1.096886, 1.290716, 1.601252, 2.201788",\
+ "0.368637, 0.551695, 0.745581, 1.055944, 1.656317",\
+ "0.400068, 0.583126, 0.777012, 1.087376, 1.687749",\
+ "0.452777, 0.635835, 0.829721, 1.140085, 1.740461",\
+ "0.595130, 0.778187, 0.972073, 1.282437, 1.882811",\
+ "0.973727, 1.156784, 1.350670, 1.661033, 2.261405",\
+ "0.501379, 0.683946, 0.877464, 1.187801, 1.788124",\
+ "0.532811, 0.715378, 0.908895, 1.219233, 1.819557",\
+ "0.585519, 0.768086, 0.961603, 1.271942, 1.872268",\
+ "0.727872, 0.910439, 1.103956, 1.414294, 2.014618",\
+ "1.106469, 1.289036, 1.482553, 1.792891, 2.393212",\
+ "0.534516, 0.717073, 0.910588, 1.220754, 1.820733",\
+ "0.565947, 0.748505, 0.942020, 1.252186, 1.852165",\
+ "0.618656, 0.801213, 0.994728, 1.304895, 1.904876",\
+ "0.761009, 0.943566, 1.137081, 1.447247, 2.047226",\
+ "1.139605, 1.322163, 1.515678, 1.825843, 2.425821",\
+ "0.835592, 1.022294, 1.214223, 1.523770, 2.122581",\
+ "0.867023, 1.053726, 1.245655, 1.555202, 2.154014",\
+ "0.919731, 1.106434, 1.298363, 1.607911, 2.206725",\
+ "1.062084, 1.248787, 1.440716, 1.750263, 2.349075",\
+ "1.440681, 1.627384, 1.819313, 2.128859, 2.727669");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_b_o[1]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.252558, 0.520745, 0.784515, 1.222569, 2.097608",\
+ "0.319449, 0.587637, 0.851411, 1.289475, 2.164534",\
+ "0.435876, 0.704065, 0.967843, 1.405915, 2.280990",\
+ "0.755544, 1.023733, 1.287511, 1.725584, 2.600661",\
+ "1.610764, 1.878952, 2.142725, 2.580786, 3.455839",\
+ "0.311120, 0.579252, 0.843280, 1.280275, 2.153714",\
+ "0.378011, 0.646143, 0.910176, 1.347182, 2.220640",\
+ "0.494438, 0.762572, 1.026608, 1.463622, 2.337097",\
+ "0.814106, 1.082240, 1.346276, 1.783291, 2.656767",\
+ "1.669326, 1.937458, 2.201490, 2.638493, 3.511946",\
+ "0.455460, 0.724999, 0.987167, 1.424079, 2.297447",\
+ "0.522351, 0.791891, 1.054064, 1.490985, 2.364373",\
+ "0.638778, 0.908319, 1.170496, 1.607426, 2.480830",\
+ "0.958446, 1.227987, 1.490164, 1.927095, 2.800500",\
+ "1.813666, 2.083206, 2.345378, 2.782297, 3.655679",\
+ "0.491341, 0.762735, 1.024086, 1.460950, 2.334005",\
+ "0.558231, 0.829626, 1.090982, 1.527856, 2.400931",\
+ "0.674659, 0.946054, 1.207414, 1.644296, 2.517388",\
+ "0.994327, 1.265722, 1.527082, 1.963966, 2.837059",\
+ "1.849546, 2.120941, 2.382296, 2.819168, 3.692237",\
+ "0.819555, 1.126080, 1.375645, 1.810251, 2.679461",\
+ "0.886446, 1.192972, 1.442542, 1.877157, 2.746387",\
+ "1.002873, 1.309400, 1.558974, 1.993597, 2.862844",\
+ "1.322541, 1.629068, 1.878642, 2.313266, 3.182515",\
+ "2.177761, 2.484287, 2.733856, 3.168468, 4.037693");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\
+ "2.441330, 2.441331, 2.441334, 2.441343, 2.441361");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.262934, 0.448489, 0.641595, 0.948064, 1.538713",\
+ "0.294346, 0.479902, 0.673008, 0.979478, 1.570129",\
+ "0.346992, 0.532548, 0.725656, 1.032128, 1.622785",\
+ "0.489407, 0.674962, 0.868069, 1.174539, 1.765190",\
+ "0.868050, 1.053605, 1.246711, 1.553179, 2.143825",\
+ "0.322845, 0.508317, 0.701440, 1.007833, 1.598330",\
+ "0.354258, 0.539729, 0.732853, 1.039247, 1.629746",\
+ "0.406904, 0.592376, 0.785500, 1.091897, 1.682402",\
+ "0.549319, 0.734790, 0.927914, 1.234307, 1.824806",\
+ "0.927962, 1.113433, 1.306556, 1.612947, 2.203442",\
+ "0.455621, 0.640568, 0.833323, 1.139690, 1.730137",\
+ "0.487034, 0.671981, 0.864736, 1.171104, 1.761553",\
+ "0.539679, 0.724627, 0.917383, 1.223754, 1.814209",\
+ "0.682094, 0.867041, 1.059797, 1.366165, 1.956614",\
+ "1.060737, 1.245684, 1.438439, 1.744805, 2.335249",\
+ "0.488779, 0.673866, 0.866553, 1.172770, 1.762998",\
+ "0.520192, 0.705279, 0.897966, 1.204184, 1.794413",\
+ "0.572837, 0.757925, 0.950613, 1.256834, 1.847070",\
+ "0.715252, 0.900339, 1.093027, 1.399244, 1.989474",\
+ "1.093896, 1.278982, 1.471669, 1.777884, 2.368110",\
+ "0.790171, 0.979313, 1.170216, 1.475973, 2.065303",\
+ "0.821584, 1.010726, 1.201629, 1.507387, 2.096719",\
+ "0.874230, 1.063372, 1.254276, 1.560037, 2.149375",\
+ "1.016645, 1.205787, 1.396689, 1.702447, 2.291780",\
+ "1.395288, 1.584430, 1.775331, 2.081088, 2.670415");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\
+ "0.180378, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091687, 1.091683, 1.091668, 1.091628, 1.091545");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\
+ "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\
+ "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\
+ "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\
+ "0.073824, 0.189425, 0.393252, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\
+ "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\
+ "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\
+ "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\
+ "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\
+ "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\
+ "0.643636, 0.699058, 0.793671, 1.054205, 1.742813");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\
+ "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\
+ "0.054820, 0.149920, 0.315966, 0.770514, 1.988361");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\
+ "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\
+ "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\
+ "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\
+ "0.630702, 0.654723, 0.683267, 0.752219, 0.936438");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\
+ "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "fla_obs_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\
+ "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\
+ "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\
+ "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\
+ "0.629434, 0.713469, 0.835221, 1.155234, 2.004311");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\
+ "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\
+ "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\
+ "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\
+ "0.099054, 0.205738, 0.390315, 0.940320, 2.425200");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\
+ "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\
+ "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\
+ "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\
+ "0.668936, 0.733428, 0.809479, 0.962224, 1.340585");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\
+ "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\
+ "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\
+ "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\
+ "0.118581, 0.174509, 0.240947, 0.445113, 1.092793");
+ }
+
+ } /* end of arc fla_obs_i[2]_ast2padmux_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "fla_obs_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\
+ "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\
+ "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\
+ "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\
+ "0.610985, 0.691263, 0.810230, 1.128954, 1.977655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\
+ "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\
+ "0.093347, 0.198994, 0.384563, 0.939701, 2.425563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\
+ "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\
+ "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\
+ "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\
+ "0.615736, 0.679130, 0.754042, 0.905113, 1.283136");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\
+ "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\
+ "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\
+ "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\
+ "0.116096, 0.171326, 0.236992, 0.441817, 1.092511");
+ }
+
+ } /* end of arc fla_obs_i[2]_ast2padmux_o[2]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\
+ "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\
+ "0.522299, 0.589203, 0.705642, 1.025311, 1.880515",\
+ "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\
+ "1.134534, 1.201443, 1.317885, 1.637554, 2.492753");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073042, 0.188941, 0.391856, 0.949133, 2.441345");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\
+ "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\
+ "0.579305, 0.610737, 0.663445, 0.805798, 1.184395",\
+ "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\
+ "1.248357, 1.279789, 1.332497, 1.474850, 1.853447");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\
+ "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\
+ "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\
+ "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\
+ "1.077990, 1.144880, 1.261307, 1.580975, 2.436195");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.392762, 0.424174, 0.476820, 0.619235, 0.997878",\
+ "0.410167, 0.441580, 0.494226, 0.636641, 1.015284",\
+ "0.482737, 0.514149, 0.566795, 0.709210, 1.087853",\
+ "0.595371, 0.626784, 0.679430, 0.821845, 1.200488",\
+ "1.122399, 1.153812, 1.206458, 1.348872, 1.727516");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\
+ "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\
+ "0.531672, 0.563103, 0.615812, 0.758164, 1.136761",\
+ "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\
+ "1.288504, 1.319936, 1.372644, 1.514997, 1.893594");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\
+ "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\
+ "0.755094, 0.821998, 0.938437, 1.258106, 2.113310",\
+ "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\
+ "1.641748, 1.708657, 1.825099, 2.144769, 2.999968");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073042, 0.188941, 0.391856, 0.949133, 2.441345");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262392, 0.293804, 0.346450, 0.488865, 0.867508",\
+ "0.286002, 0.317414, 0.370060, 0.512475, 0.891118",\
+ "0.357340, 0.388753, 0.441399, 0.583814, 0.962457",\
+ "0.477148, 0.508560, 0.561206, 0.703621, 1.082264",\
+ "1.022245, 1.053658, 1.106303, 1.248718, 1.627362");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.582342, 0.649232, 0.765660, 1.085328, 1.940547",\
+ "0.599034, 0.665924, 0.782351, 1.102020, 1.957239",\
+ "0.661428, 0.728319, 0.844746, 1.164414, 2.019634",\
+ "0.770818, 0.837708, 0.954135, 1.273803, 2.129023",\
+ "1.507966, 1.574856, 1.691283, 2.010951, 2.866171");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\
+ "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\
+ "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\
+ "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\
+ "0.975060, 1.010086, 1.063144, 1.205732, 1.584486");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\
+ "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\
+ "0.049347, 0.094034, 0.180868, 0.429355, 1.091896");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\
+ "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\
+ "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\
+ "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\
+ "1.319722, 1.387140, 1.503696, 1.823662, 2.678811");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\
+ "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\
+ "0.075399, 0.189282, 0.392442, 0.951039, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[2]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\
+ "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\
+ "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\
+ "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\
+ "0.945167, 0.979651, 1.032663, 1.175209, 1.553933");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\
+ "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\
+ "0.047820, 0.093501, 0.180675, 0.429352, 1.091629");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\
+ "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\
+ "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\
+ "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\
+ "1.312551, 1.379913, 1.496487, 1.816396, 2.671496");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\
+ "0.074954, 0.189124, 0.392388, 0.950917, 2.441454");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[2]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\
+ "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\
+ "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\
+ "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\
+ "1.108576, 1.175805, 1.292423, 1.612190, 2.467167");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\
+ "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\
+ "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\
+ "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\
+ "1.013269, 1.044421, 1.097036, 1.239541, 1.618177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\
+ "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\
+ "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\
+ "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\
+ "0.949078, 1.015776, 1.132136, 1.448920, 2.298678");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\
+ "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\
+ "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\
+ "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\
+ "0.909442, 0.940877, 0.993596, 1.135938, 1.514527");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\
+ "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\
+ "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\
+ "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\
+ "0.918190, 0.949342, 1.001956, 1.144462, 1.523098");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\
+ "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\
+ "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\
+ "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\
+ "1.006927, 1.073706, 1.190415, 1.507149, 2.356620");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\
+ "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\
+ "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\
+ "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\
+ "0.893831, 0.925076, 0.977718, 1.120154, 1.498834");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\
+ "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\
+ "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\
+ "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\
+ "1.002245, 1.068944, 1.185303, 1.502088, 2.351846");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\
+ "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\
+ "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\
+ "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\
+ "0.997007, 1.063817, 1.180658, 1.497372, 2.346736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\
+ "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\
+ "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\
+ "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\
+ "1.004117, 1.035227, 1.087829, 1.230366, 1.608983");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\
+ "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\
+ "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\
+ "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\
+ "0.957622, 1.024367, 1.140929, 1.457685, 2.307276");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\
+ "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\
+ "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\
+ "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\
+ "0.955028, 0.986237, 1.038869, 1.181331, 1.559995");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\
+ "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\
+ "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\
+ "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\
+ "0.961790, 0.996912, 1.049978, 1.192575, 1.571334");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\
+ "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\
+ "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\
+ "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\
+ "1.332501, 1.399969, 1.516508, 1.836528, 2.691724");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\
+ "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\
+ "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\
+ "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\
+ "0.931678, 0.966257, 1.019278, 1.161831, 1.540560");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\
+ "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\
+ "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\
+ "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\
+ "1.324350, 1.391756, 1.508316, 1.828270, 2.683409");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\
+ "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\
+ "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\
+ "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\
+ "0.876566, 0.943791, 1.060410, 1.380173, 2.235147");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\
+ "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\
+ "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\
+ "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\
+ "0.808201, 0.839636, 0.892354, 1.034697, 1.413287");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\
+ "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\
+ "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\
+ "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\
+ "0.852482, 0.919491, 1.036016, 1.355692, 2.210772");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\
+ "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\
+ "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\
+ "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\
+ "0.786063, 0.817479, 0.870138, 1.012540, 1.391174");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\
+ "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\
+ "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\
+ "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\
+ "0.984655, 1.015818, 1.068436, 1.210933, 1.589574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\
+ "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\
+ "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\
+ "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\
+ "1.273667, 1.340892, 1.457511, 1.777274, 2.632248");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\
+ "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\
+ "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\
+ "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\
+ "0.929777, 0.961193, 1.013852, 1.156254, 1.534888");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\
+ "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\
+ "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\
+ "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\
+ "1.131911, 1.198614, 1.314996, 1.631778, 2.481517");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\
+ "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\
+ "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\
+ "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\
+ "0.999580, 1.030743, 1.083361, 1.225858, 1.604500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\
+ "0.042004, 0.091469, 0.180867, 0.429340, 1.092504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\
+ "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\
+ "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\
+ "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\
+ "1.375793, 1.443018, 1.559637, 1.879400, 2.734374");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[2]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\
+ "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\
+ "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\
+ "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\
+ "0.825559, 0.856975, 0.909634, 1.052036, 1.430670");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039038, 0.090323, 0.180168, 0.428941, 1.091519");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\
+ "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\
+ "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\
+ "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\
+ "1.141953, 1.209132, 1.325766, 1.645481, 2.500414");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067601, 0.184550, 0.382483, 0.937044, 2.417691");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[2]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\
+ "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\
+ "0.789396, 0.856300, 0.972739, 1.292408, 2.147612",\
+ "0.881867, 0.948772, 1.065210, 1.384879, 2.240083",\
+ "1.366874, 1.433786, 1.550230, 1.869900, 2.725095");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073043, 0.188945, 0.391861, 0.949146, 2.441348");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\
+ "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\
+ "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\
+ "0.691204, 0.722635, 0.775344, 0.917696, 1.296293",\
+ "1.242374, 1.273805, 1.326514, 1.468867, 1.847463");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\
+ "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\
+ "0.727539, 0.794429, 0.910857, 1.230525, 2.085744",\
+ "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\
+ "1.269718, 1.336608, 1.453035, 1.772703, 2.627923");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.339768, 0.371181, 0.423827, 0.566242, 0.944885",\
+ "0.353114, 0.384527, 0.437173, 0.579588, 0.958231",\
+ "0.435092, 0.466504, 0.519150, 0.661565, 1.040208",\
+ "0.544311, 0.575724, 0.628370, 0.770784, 1.149428",\
+ "1.067931, 1.099343, 1.151989, 1.294404, 1.673047");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\
+ "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\
+ "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\
+ "0.714865, 0.746296, 0.799004, 0.941357, 1.319954",\
+ "1.237234, 1.268665, 1.321373, 1.463726, 1.842323");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\
+ "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\
+ "0.718781, 0.785685, 0.902124, 1.221793, 2.076997",\
+ "0.821201, 0.888105, 1.004544, 1.324213, 2.179417",\
+ "1.548479, 1.615391, 1.731835, 2.051504, 2.906700");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073043, 0.188945, 0.391861, 0.949146, 2.441348");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.267796, 0.299208, 0.351854, 0.494269, 0.872912",\
+ "0.284541, 0.315954, 0.368600, 0.511015, 0.889658",\
+ "0.362798, 0.394211, 0.446856, 0.589271, 0.967914",\
+ "0.486677, 0.518090, 0.570736, 0.713151, 1.091794",\
+ "1.055266, 1.086678, 1.139324, 1.281739, 1.660382");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\
+ "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\
+ "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\
+ "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\
+ "1.120855, 1.187745, 1.304172, 1.623840, 2.479060");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\
+ "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\
+ "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\
+ "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\
+ "1.358120, 1.425029, 1.541471, 1.861141, 2.716340");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073041, 0.188941, 0.391855, 0.949133, 2.441345");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\
+ "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\
+ "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\
+ "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\
+ "1.229663, 1.261095, 1.313803, 1.456156, 1.834753");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\
+ "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\
+ "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\
+ "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\
+ "1.307789, 1.374679, 1.491106, 1.810774, 2.665994");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.361699, 0.393111, 0.445757, 0.588172, 0.966815",\
+ "0.375155, 0.406568, 0.459214, 0.601628, 0.980272",\
+ "0.456576, 0.487988, 0.540634, 0.683049, 1.061692",\
+ "0.566550, 0.597963, 0.650609, 0.793024, 1.171667",\
+ "1.091986, 1.123399, 1.176044, 1.318459, 1.697102");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\
+ "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\
+ "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\
+ "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\
+ "1.192613, 1.224045, 1.276753, 1.419106, 1.797703");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.606303, 0.673207, 0.789646, 1.109315, 1.964519",\
+ "0.618992, 0.685897, 0.802335, 1.122004, 1.977208",\
+ "0.673763, 0.740668, 0.857106, 1.176775, 2.031980",\
+ "0.776802, 0.843707, 0.960145, 1.279814, 2.135018",\
+ "1.483718, 1.550627, 1.667069, 1.986738, 2.841937");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073041, 0.188941, 0.391855, 0.949133, 2.441345");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262699, 0.294112, 0.346758, 0.489173, 0.867816",\
+ "0.279513, 0.310926, 0.363572, 0.505987, 0.884630",\
+ "0.357852, 0.389264, 0.441910, 0.584325, 0.962968",\
+ "0.480383, 0.511796, 0.564441, 0.706856, 1.085500",\
+ "1.037548, 1.068961, 1.121607, 1.264022, 1.642665");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\
+ "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\
+ "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\
+ "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\
+ "1.119877, 1.186768, 1.303195, 1.622863, 2.478083");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_inv_min*/
+
+ timing () {
+ related_pin : "otm_obs_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\
+ "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\
+ "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\
+ "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\
+ "0.695902, 0.774527, 0.893732, 1.214148, 2.069560");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\
+ "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\
+ "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\
+ "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\
+ "0.098084, 0.204137, 0.393542, 0.951076, 2.441498");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\
+ "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\
+ "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\
+ "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\
+ "0.825607, 0.870622, 0.930343, 1.075147, 1.454209");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\
+ "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\
+ "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\
+ "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\
+ "0.068556, 0.114740, 0.192215, 0.429716, 1.093122");
+ }
+
+ } /* end of arc otm_obs_i[2]_ast2padmux_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otm_obs_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\
+ "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\
+ "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\
+ "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\
+ "0.662107, 0.738115, 0.856688, 1.177023, 2.032395");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\
+ "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\
+ "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\
+ "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\
+ "0.092938, 0.200557, 0.393255, 0.950255, 2.441468");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\
+ "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\
+ "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\
+ "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\
+ "0.777508, 0.822171, 0.881623, 1.026340, 1.405392");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\
+ "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\
+ "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\
+ "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\
+ "0.067933, 0.113945, 0.191732, 0.429701, 1.093101");
+ }
+
+ } /* end of arc otm_obs_i[2]_ast2padmux_o[2]_una_min*/
+
+ timing () {
+ related_pin : "otp_obs_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\
+ "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\
+ "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\
+ "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\
+ "0.699992, 0.780922, 0.900058, 1.218756, 2.067549");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\
+ "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\
+ "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\
+ "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\
+ "0.094401, 0.199857, 0.384817, 0.940410, 2.426093");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\
+ "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\
+ "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\
+ "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\
+ "0.820213, 0.870292, 0.933027, 1.077593, 1.455130");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\
+ "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\
+ "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\
+ "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\
+ "0.087354, 0.133744, 0.204884, 0.431205, 1.092443");
+ }
+
+ } /* end of arc otp_obs_i[2]_ast2padmux_o[2]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_obs_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\
+ "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\
+ "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\
+ "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\
+ "0.667813, 0.745674, 0.864272, 1.183300, 2.031636");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\
+ "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\
+ "0.089380, 0.196045, 0.384240, 0.939859, 2.423100");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\
+ "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\
+ "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\
+ "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\
+ "0.773733, 0.823401, 0.885774, 1.030256, 1.407808");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\
+ "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\
+ "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\
+ "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\
+ "0.086478, 0.132591, 0.204027, 0.431125, 1.092425");
+ }
+
+ } /* end of arc otp_obs_i[2]_ast2padmux_o[2]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\
+ "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\
+ "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\
+ "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[2]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\
+ "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\
+ "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\
+ "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\
+ "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\
+ "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\
+ "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[2]_inv_min*/
+
+} /* end of pin ast2padmux_o[2] */
+
+pin("ast2padmux_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.028584 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2padmux_o[1];
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_b_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.257031, 0.528778, 0.797030, 1.242767, 2.134242",\
+ "0.323932, 0.595681, 0.863940, 1.309691, 2.201193",\
+ "0.440368, 0.712118, 0.980382, 1.426145, 2.317669",\
+ "0.760037, 1.031787, 1.300052, 1.745815, 2.637342",\
+ "1.615245, 1.886993, 2.155250, 2.600997, 3.492491",\
+ "0.315617, 0.587294, 0.855812, 1.300474, 2.190349",\
+ "0.382518, 0.654197, 0.922722, 1.367397, 2.257300",\
+ "0.498954, 0.770634, 1.039164, 1.483851, 2.373776",\
+ "0.818623, 1.090303, 1.358834, 1.803522, 2.693449",\
+ "1.673831, 1.945509, 2.214032, 2.658703, 3.548597",\
+ "0.460207, 0.733101, 0.999707, 1.444229, 2.334082",\
+ "0.527108, 0.800004, 1.066617, 1.511152, 2.401032",\
+ "0.643544, 0.916442, 1.183060, 1.627606, 2.517509",\
+ "0.963213, 1.236110, 1.502729, 1.947277, 2.837182",\
+ "1.818421, 2.091316, 2.357927, 2.802459, 3.692330",\
+ "0.496168, 0.770865, 1.036627, 1.481020, 2.370640",\
+ "0.563069, 0.837768, 1.103536, 1.547944, 2.437591",\
+ "0.679505, 0.954206, 1.219979, 1.664398, 2.554067",\
+ "0.999174, 1.273875, 1.539648, 1.984068, 2.873740",\
+ "1.854382, 2.129080, 2.394846, 2.839250, 3.728889",\
+ "0.825262, 1.134787, 1.388262, 1.830277, 2.716096",\
+ "0.892164, 1.201690, 1.455172, 1.897201, 2.783047",\
+ "1.008600, 1.318128, 1.571615, 2.013655, 2.899523",\
+ "1.328269, 1.637797, 1.891284, 2.333325, 3.219196",\
+ "2.183476, 2.493002, 2.746482, 3.188507, 4.074345");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\
+ "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\
+ "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\
+ "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\
+ "0.073036, 0.073038, 0.073042, 0.073052, 0.073073",\
+ "0.188928, 0.188932, 0.188943, 0.188966, 0.189013",\
+ "0.391836, 0.391843, 0.391858, 0.391892, 0.391961",\
+ "0.949092, 0.949105, 0.949137, 0.949210, 0.949357",\
+ "2.441339, 2.441341, 2.441346, 2.441358, 2.441383");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.308725, 0.491796, 0.685627, 0.996163, 1.596700",\
+ "0.340157, 0.523228, 0.717058, 1.027595, 1.628132",\
+ "0.392865, 0.575936, 0.769767, 1.080304, 1.680844",\
+ "0.535218, 0.718289, 0.912119, 1.222656, 1.823194",\
+ "0.913815, 1.096886, 1.290716, 1.601252, 2.201788",\
+ "0.368637, 0.551695, 0.745581, 1.055944, 1.656317",\
+ "0.400068, 0.583126, 0.777012, 1.087376, 1.687749",\
+ "0.452777, 0.635835, 0.829721, 1.140085, 1.740461",\
+ "0.595130, 0.778187, 0.972073, 1.282437, 1.882811",\
+ "0.973727, 1.156784, 1.350670, 1.661033, 2.261405",\
+ "0.501379, 0.683946, 0.877464, 1.187801, 1.788124",\
+ "0.532811, 0.715378, 0.908895, 1.219233, 1.819557",\
+ "0.585519, 0.768086, 0.961603, 1.271942, 1.872268",\
+ "0.727872, 0.910439, 1.103956, 1.414294, 2.014618",\
+ "1.106469, 1.289036, 1.482553, 1.792891, 2.393212",\
+ "0.534516, 0.717073, 0.910588, 1.220754, 1.820733",\
+ "0.565947, 0.748505, 0.942020, 1.252186, 1.852165",\
+ "0.618656, 0.801213, 0.994728, 1.304895, 1.904876",\
+ "0.761009, 0.943566, 1.137081, 1.447247, 2.047226",\
+ "1.139605, 1.322163, 1.515678, 1.825843, 2.425821",\
+ "0.835592, 1.022294, 1.214223, 1.523770, 2.122581",\
+ "0.867023, 1.053726, 1.245655, 1.555202, 2.154014",\
+ "0.919731, 1.106434, 1.298363, 1.607911, 2.206725",\
+ "1.062084, 1.248787, 1.440716, 1.750263, 2.349075",\
+ "1.440681, 1.627384, 1.819313, 2.128859, 2.727669");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\
+ "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\
+ "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\
+ "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\
+ "1.090837, 1.090837, 1.090837, 1.090825, 1.090796");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_b_o[0]" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.252558, 0.520745, 0.784515, 1.222569, 2.097608",\
+ "0.319449, 0.587637, 0.851411, 1.289475, 2.164534",\
+ "0.435876, 0.704065, 0.967843, 1.405915, 2.280990",\
+ "0.755544, 1.023733, 1.287511, 1.725584, 2.600661",\
+ "1.610764, 1.878952, 2.142725, 2.580786, 3.455839",\
+ "0.311120, 0.579252, 0.843280, 1.280275, 2.153714",\
+ "0.378011, 0.646143, 0.910176, 1.347182, 2.220640",\
+ "0.494438, 0.762572, 1.026608, 1.463622, 2.337097",\
+ "0.814106, 1.082240, 1.346276, 1.783291, 2.656767",\
+ "1.669326, 1.937458, 2.201490, 2.638493, 3.511946",\
+ "0.455460, 0.724999, 0.987167, 1.424079, 2.297447",\
+ "0.522351, 0.791891, 1.054064, 1.490985, 2.364373",\
+ "0.638778, 0.908319, 1.170496, 1.607426, 2.480830",\
+ "0.958446, 1.227987, 1.490164, 1.927095, 2.800500",\
+ "1.813666, 2.083206, 2.345378, 2.782297, 3.655679",\
+ "0.491341, 0.762735, 1.024086, 1.460950, 2.334005",\
+ "0.558231, 0.829626, 1.090982, 1.527856, 2.400931",\
+ "0.674659, 0.946054, 1.207414, 1.644296, 2.517388",\
+ "0.994327, 1.265722, 1.527082, 1.963966, 2.837059",\
+ "1.849546, 2.120941, 2.382296, 2.819168, 3.692237",\
+ "0.819555, 1.126080, 1.375645, 1.810251, 2.679461",\
+ "0.886446, 1.192972, 1.442542, 1.877157, 2.746387",\
+ "1.002873, 1.309400, 1.558974, 1.993597, 2.862844",\
+ "1.322541, 1.629068, 1.878642, 2.313266, 3.182515",\
+ "2.177761, 2.484287, 2.733856, 3.168468, 4.037693");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\
+ "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\
+ "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\
+ "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\
+ "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\
+ "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\
+ "2.441330, 2.441331, 2.441334, 2.441343, 2.441361");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.262934, 0.448489, 0.641595, 0.948064, 1.538713",\
+ "0.294346, 0.479902, 0.673008, 0.979478, 1.570129",\
+ "0.346992, 0.532548, 0.725656, 1.032128, 1.622785",\
+ "0.489407, 0.674962, 0.868069, 1.174539, 1.765190",\
+ "0.868050, 1.053605, 1.246711, 1.553179, 2.143825",\
+ "0.322845, 0.508317, 0.701440, 1.007833, 1.598330",\
+ "0.354258, 0.539729, 0.732853, 1.039247, 1.629746",\
+ "0.406904, 0.592376, 0.785500, 1.091897, 1.682402",\
+ "0.549319, 0.734790, 0.927914, 1.234307, 1.824806",\
+ "0.927962, 1.113433, 1.306556, 1.612947, 2.203442",\
+ "0.455621, 0.640568, 0.833323, 1.139690, 1.730137",\
+ "0.487034, 0.671981, 0.864736, 1.171104, 1.761553",\
+ "0.539679, 0.724627, 0.917383, 1.223754, 1.814209",\
+ "0.682094, 0.867041, 1.059797, 1.366165, 1.956614",\
+ "1.060737, 1.245684, 1.438439, 1.744805, 2.335249",\
+ "0.488779, 0.673866, 0.866553, 1.172770, 1.762998",\
+ "0.520192, 0.705279, 0.897966, 1.204184, 1.794413",\
+ "0.572837, 0.757925, 0.950613, 1.256834, 1.847070",\
+ "0.715252, 0.900339, 1.093027, 1.399244, 1.989474",\
+ "1.093896, 1.278982, 1.471669, 1.777884, 2.368110",\
+ "0.790171, 0.979313, 1.170216, 1.475973, 2.065303",\
+ "0.821584, 1.010726, 1.201629, 1.507387, 2.096719",\
+ "0.874230, 1.063372, 1.254276, 1.560037, 2.149375",\
+ "1.016645, 1.205787, 1.396689, 1.702447, 2.291780",\
+ "1.395288, 1.584430, 1.775331, 2.081088, 2.670415");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011");
+ values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\
+ "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\
+ "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\
+ "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\
+ "0.180378, 0.180379, 0.180385, 0.180400, 0.180431",\
+ "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\
+ "1.091687, 1.091683, 1.091668, 1.091628, 1.091545");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "970008.750000, 970008.812500, 970008.937500, 970009.250000, 970010.125000",\
+ "970008.875000, 970008.937500, 970009.062500, 970009.375000, 970010.250000",\
+ "970009.000000, 970009.062500, 970009.187500, 970009.500000, 970010.375000",\
+ "970009.000000, 970009.062500, 970009.187500, 970009.500000, 970010.375000",\
+ "970009.375000, 970009.437500, 970009.562500, 970009.875000, 970010.750000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\
+ "0.073824, 0.189425, 0.393252, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "970006.125000, 970006.187500, 970006.250000, 970006.375000, 970006.750000",\
+ "970006.250000, 970006.312500, 970006.375000, 970006.500000, 970006.875000",\
+ "970006.250000, 970006.312500, 970006.375000, 970006.500000, 970006.875000",\
+ "970006.375000, 970006.437500, 970006.500000, 970006.625000, 970007.000000",\
+ "970006.625000, 970006.687500, 970006.750000, 970006.875000, 970007.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\
+ "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\
+ "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\
+ "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\
+ "0.643636, 0.699058, 0.793671, 1.054205, 1.742813");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\
+ "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\
+ "0.054820, 0.149920, 0.315966, 0.770514, 1.988361");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\
+ "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\
+ "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\
+ "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\
+ "0.630702, 0.654723, 0.683267, 0.752219, 0.936438");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\
+ "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "fla_obs_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\
+ "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\
+ "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\
+ "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\
+ "0.629434, 0.713469, 0.835221, 1.155234, 2.004311");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\
+ "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\
+ "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\
+ "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\
+ "0.099054, 0.205738, 0.390315, 0.940320, 2.425200");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\
+ "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\
+ "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\
+ "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\
+ "0.668936, 0.733428, 0.809479, 0.962224, 1.340585");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\
+ "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\
+ "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\
+ "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\
+ "0.118581, 0.174509, 0.240947, 0.445113, 1.092793");
+ }
+
+ } /* end of arc fla_obs_i[1]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "fla_obs_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\
+ "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\
+ "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\
+ "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\
+ "0.610985, 0.691263, 0.810230, 1.128954, 1.977655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\
+ "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\
+ "0.093347, 0.198994, 0.384563, 0.939701, 2.425563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\
+ "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\
+ "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\
+ "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\
+ "0.615736, 0.679130, 0.754042, 0.905113, 1.283136");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\
+ "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\
+ "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\
+ "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\
+ "0.116096, 0.171326, 0.236992, 0.441817, 1.092511");
+ }
+
+ } /* end of arc fla_obs_i[1]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\
+ "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\
+ "0.522299, 0.589203, 0.705642, 1.025311, 1.880515",\
+ "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\
+ "1.134534, 1.201443, 1.317885, 1.637554, 2.492753");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073042, 0.188941, 0.391856, 0.949133, 2.441345");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\
+ "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\
+ "0.579305, 0.610737, 0.663445, 0.805798, 1.184395",\
+ "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\
+ "1.248357, 1.279789, 1.332497, 1.474850, 1.853447");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\
+ "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\
+ "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\
+ "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\
+ "1.077990, 1.144880, 1.261307, 1.580975, 2.436195");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.392762, 0.424174, 0.476820, 0.619235, 0.997878",\
+ "0.410167, 0.441580, 0.494226, 0.636641, 1.015284",\
+ "0.482737, 0.514149, 0.566795, 0.709210, 1.087853",\
+ "0.595371, 0.626784, 0.679430, 0.821845, 1.200488",\
+ "1.122399, 1.153812, 1.206458, 1.348872, 1.727516");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\
+ "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\
+ "0.531672, 0.563103, 0.615812, 0.758164, 1.136761",\
+ "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\
+ "1.288504, 1.319936, 1.372644, 1.514997, 1.893594");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\
+ "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\
+ "0.755094, 0.821998, 0.938437, 1.258106, 2.113310",\
+ "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\
+ "1.641748, 1.708657, 1.825099, 2.144769, 2.999968");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\
+ "0.073042, 0.188941, 0.391856, 0.949133, 2.441345");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262392, 0.293804, 0.346450, 0.488865, 0.867508",\
+ "0.286002, 0.317414, 0.370060, 0.512475, 0.891118",\
+ "0.357340, 0.388753, 0.441399, 0.583814, 0.962457",\
+ "0.477148, 0.508560, 0.561206, 0.703621, 1.082264",\
+ "1.022245, 1.053658, 1.106303, 1.248718, 1.627362");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.582342, 0.649232, 0.765660, 1.085328, 1.940547",\
+ "0.599034, 0.665924, 0.782351, 1.102020, 1.957239",\
+ "0.661428, 0.728319, 0.844746, 1.164414, 2.019634",\
+ "0.770818, 0.837708, 0.954135, 1.273803, 2.129023",\
+ "1.507966, 1.574856, 1.691283, 2.010951, 2.866171");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\
+ "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\
+ "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\
+ "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\
+ "0.975060, 1.010086, 1.063144, 1.205732, 1.584486");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\
+ "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\
+ "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\
+ "0.049347, 0.094034, 0.180868, 0.429355, 1.091896");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\
+ "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\
+ "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\
+ "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\
+ "1.319722, 1.387140, 1.503696, 1.823662, 2.678811");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\
+ "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\
+ "0.075399, 0.189282, 0.392442, 0.951039, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\
+ "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\
+ "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\
+ "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\
+ "0.945167, 0.979651, 1.032663, 1.175209, 1.553933");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\
+ "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\
+ "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\
+ "0.047820, 0.093501, 0.180675, 0.429352, 1.091629");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\
+ "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\
+ "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\
+ "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\
+ "1.312551, 1.379913, 1.496487, 1.816396, 2.671496");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\
+ "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\
+ "0.074954, 0.189124, 0.392388, 0.950917, 2.441454");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\
+ "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\
+ "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\
+ "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\
+ "1.108576, 1.175805, 1.292423, 1.612190, 2.467167");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\
+ "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\
+ "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\
+ "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\
+ "1.013269, 1.044421, 1.097036, 1.239541, 1.618177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\
+ "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\
+ "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\
+ "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\
+ "0.949078, 1.015776, 1.132136, 1.448920, 2.298678");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\
+ "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\
+ "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\
+ "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\
+ "0.909442, 0.940877, 0.993596, 1.135938, 1.514527");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\
+ "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\
+ "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\
+ "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\
+ "0.918190, 0.949342, 1.001956, 1.144462, 1.523098");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\
+ "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\
+ "0.040922, 0.090525, 0.180916, 0.429325, 1.092539");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\
+ "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\
+ "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\
+ "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\
+ "1.006927, 1.073706, 1.190415, 1.507149, 2.356620");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073848, 0.189277, 0.392440, 0.950615, 2.441524");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\
+ "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\
+ "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\
+ "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\
+ "0.893831, 0.925076, 0.977718, 1.120154, 1.498834");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\
+ "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\
+ "0.039166, 0.090324, 0.180166, 0.428948, 1.090692");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\
+ "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\
+ "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\
+ "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\
+ "1.002245, 1.068944, 1.185303, 1.502088, 2.351846");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\
+ "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\
+ "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\
+ "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\
+ "0.997007, 1.063817, 1.180658, 1.497372, 2.346736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\
+ "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\
+ "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\
+ "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\
+ "1.004117, 1.035227, 1.087829, 1.230366, 1.608983");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\
+ "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\
+ "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\
+ "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\
+ "0.957622, 1.024367, 1.140929, 1.457685, 2.307276");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\
+ "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\
+ "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\
+ "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\
+ "0.955028, 0.986237, 1.038869, 1.181331, 1.559995");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\
+ "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\
+ "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\
+ "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\
+ "0.961790, 0.996912, 1.049978, 1.192575, 1.571334");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\
+ "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\
+ "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\
+ "0.049622, 0.094130, 0.180871, 0.429356, 1.092666");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\
+ "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\
+ "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\
+ "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\
+ "1.332501, 1.399969, 1.516508, 1.836528, 2.691724");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\
+ "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\
+ "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\
+ "0.075818, 0.189005, 0.392348, 0.951153, 2.441399");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\
+ "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\
+ "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\
+ "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\
+ "0.931678, 0.966257, 1.019278, 1.161831, 1.540560");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\
+ "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.091676");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\
+ "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\
+ "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\
+ "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\
+ "1.324350, 1.391756, 1.508316, 1.828270, 2.683409");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\
+ "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\
+ "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\
+ "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\
+ "0.876566, 0.943791, 1.060410, 1.380173, 2.235147");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\
+ "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\
+ "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\
+ "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\
+ "0.808201, 0.839636, 0.892354, 1.034697, 1.413287");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\
+ "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\
+ "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\
+ "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\
+ "0.852482, 0.919491, 1.036016, 1.355692, 2.210772");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\
+ "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\
+ "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\
+ "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\
+ "0.786063, 0.817479, 0.870138, 1.012540, 1.391174");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\
+ "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\
+ "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\
+ "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\
+ "0.984655, 1.015818, 1.068436, 1.210933, 1.589574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040785, 0.090610, 0.180744, 0.429286, 1.092505");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\
+ "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\
+ "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\
+ "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\
+ "1.273667, 1.340892, 1.457511, 1.777274, 2.632248");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189281, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\
+ "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\
+ "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\
+ "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\
+ "0.929777, 0.961193, 1.013852, 1.156254, 1.534888");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039039, 0.090322, 0.180169, 0.428938, 1.091513");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\
+ "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\
+ "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\
+ "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\
+ "1.131911, 1.198614, 1.314996, 1.631778, 2.481517");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\
+ "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\
+ "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\
+ "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\
+ "0.999580, 1.030743, 1.083361, 1.225858, 1.604500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\
+ "0.042004, 0.091469, 0.180867, 0.429340, 1.092504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\
+ "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\
+ "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\
+ "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\
+ "1.375793, 1.443018, 1.559637, 1.879400, 2.734374");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\
+ "0.073817, 0.189281, 0.392442, 0.950607, 2.441526");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\
+ "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\
+ "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\
+ "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\
+ "0.825559, 0.856975, 0.909634, 1.052036, 1.430670");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\
+ "0.039038, 0.090323, 0.180168, 0.428941, 1.091519");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\
+ "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\
+ "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\
+ "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\
+ "1.141953, 1.209132, 1.325766, 1.645481, 2.500414");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067601, 0.184550, 0.382483, 0.937044, 2.417691");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\
+ "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\
+ "0.789396, 0.856300, 0.972739, 1.292408, 2.147612",\
+ "0.881867, 0.948772, 1.065210, 1.384879, 2.240083",\
+ "1.366874, 1.433786, 1.550230, 1.869900, 2.725095");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073043, 0.188945, 0.391861, 0.949146, 2.441348");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\
+ "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\
+ "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\
+ "0.691204, 0.722635, 0.775344, 0.917696, 1.296293",\
+ "1.242374, 1.273805, 1.326514, 1.468867, 1.847463");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\
+ "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\
+ "0.727539, 0.794429, 0.910857, 1.230525, 2.085744",\
+ "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\
+ "1.269718, 1.336608, 1.453035, 1.772703, 2.627923");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.339768, 0.371181, 0.423827, 0.566242, 0.944885",\
+ "0.353114, 0.384527, 0.437173, 0.579588, 0.958231",\
+ "0.435092, 0.466504, 0.519150, 0.661565, 1.040208",\
+ "0.544311, 0.575724, 0.628370, 0.770784, 1.149428",\
+ "1.067931, 1.099343, 1.151989, 1.294404, 1.673047");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\
+ "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\
+ "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\
+ "0.714865, 0.746296, 0.799004, 0.941357, 1.319954",\
+ "1.237234, 1.268665, 1.321373, 1.463726, 1.842323");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\
+ "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\
+ "0.718781, 0.785685, 0.902124, 1.221793, 2.076997",\
+ "0.821201, 0.888105, 1.004544, 1.324213, 2.179417",\
+ "1.548479, 1.615391, 1.731835, 2.051504, 2.906700");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073043, 0.188945, 0.391861, 0.949146, 2.441348");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.267796, 0.299208, 0.351854, 0.494269, 0.872912",\
+ "0.284541, 0.315954, 0.368600, 0.511015, 0.889658",\
+ "0.362798, 0.394211, 0.446856, 0.589271, 0.967914",\
+ "0.486677, 0.518090, 0.570736, 0.713151, 1.091794",\
+ "1.055266, 1.086678, 1.139324, 1.281739, 1.660382");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\
+ "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\
+ "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\
+ "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\
+ "1.120855, 1.187745, 1.304172, 1.623840, 2.479060");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\
+ "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\
+ "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\
+ "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\
+ "1.358120, 1.425029, 1.541471, 1.861141, 2.716340");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073041, 0.188941, 0.391855, 0.949133, 2.441345");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\
+ "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\
+ "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\
+ "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\
+ "1.229663, 1.261095, 1.313803, 1.456156, 1.834753");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\
+ "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\
+ "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\
+ "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\
+ "1.307789, 1.374679, 1.491106, 1.810774, 2.665994");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.361699, 0.393111, 0.445757, 0.588172, 0.966815",\
+ "0.375155, 0.406568, 0.459214, 0.601628, 0.980272",\
+ "0.456576, 0.487988, 0.540634, 0.683049, 1.061692",\
+ "0.566550, 0.597963, 0.650609, 0.793024, 1.171667",\
+ "1.091986, 1.123399, 1.176044, 1.318459, 1.697102");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\
+ "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\
+ "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\
+ "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\
+ "1.192613, 1.224045, 1.276753, 1.419106, 1.797703");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\
+ "0.039143, 0.090610, 0.180695, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.606303, 0.673207, 0.789646, 1.109315, 1.964519",\
+ "0.618992, 0.685897, 0.802335, 1.122004, 1.977208",\
+ "0.673763, 0.740668, 0.857106, 1.176775, 2.031980",\
+ "0.776802, 0.843707, 0.960145, 1.279814, 2.135018",\
+ "1.483718, 1.550627, 1.667069, 1.986738, 2.841937");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\
+ "0.073041, 0.188941, 0.391855, 0.949133, 2.441345");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.262699, 0.294112, 0.346758, 0.489173, 0.867816",\
+ "0.279513, 0.310926, 0.363572, 0.505987, 0.884630",\
+ "0.357852, 0.389264, 0.441910, 0.584325, 0.962968",\
+ "0.480383, 0.511796, 0.564441, 0.706856, 1.085500",\
+ "1.037548, 1.068961, 1.121607, 1.264022, 1.642665");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\
+ "0.039012, 0.090733, 0.180378, 0.429204, 1.091687");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\
+ "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\
+ "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\
+ "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\
+ "1.119877, 1.186768, 1.303195, 1.622863, 2.478083");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\
+ "0.073032, 0.188916, 0.391816, 0.949015, 2.441330");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "otm_obs_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\
+ "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\
+ "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\
+ "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\
+ "0.695902, 0.774527, 0.893732, 1.214148, 2.069560");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\
+ "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\
+ "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\
+ "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\
+ "0.098084, 0.204137, 0.393542, 0.951076, 2.441498");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\
+ "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\
+ "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\
+ "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\
+ "0.825607, 0.870622, 0.930343, 1.075147, 1.454209");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\
+ "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\
+ "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\
+ "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\
+ "0.068556, 0.114740, 0.192215, 0.429716, 1.093122");
+ }
+
+ } /* end of arc otm_obs_i[1]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otm_obs_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\
+ "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\
+ "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\
+ "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\
+ "0.662107, 0.738115, 0.856688, 1.177023, 2.032395");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\
+ "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\
+ "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\
+ "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\
+ "0.092938, 0.200557, 0.393255, 0.950255, 2.441468");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\
+ "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\
+ "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\
+ "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\
+ "0.777508, 0.822171, 0.881623, 1.026340, 1.405392");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\
+ "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\
+ "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\
+ "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\
+ "0.067933, 0.113945, 0.191732, 0.429701, 1.093101");
+ }
+
+ } /* end of arc otm_obs_i[1]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "otp_obs_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\
+ "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\
+ "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\
+ "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\
+ "0.699992, 0.780922, 0.900058, 1.218756, 2.067549");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\
+ "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\
+ "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\
+ "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\
+ "0.094401, 0.199857, 0.384817, 0.940410, 2.426093");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\
+ "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\
+ "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\
+ "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\
+ "0.820213, 0.870292, 0.933027, 1.077593, 1.455130");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\
+ "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\
+ "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\
+ "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\
+ "0.087354, 0.133744, 0.204884, 0.431205, 1.092443");
+ }
+
+ } /* end of arc otp_obs_i[1]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_obs_i[1]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\
+ "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\
+ "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\
+ "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\
+ "0.667813, 0.745674, 0.864272, 1.183300, 2.031636");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\
+ "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\
+ "0.089380, 0.196045, 0.384240, 0.939859, 2.423100");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\
+ "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\
+ "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\
+ "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\
+ "0.773733, 0.823401, 0.885774, 1.030256, 1.407808");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\
+ "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\
+ "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\
+ "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\
+ "0.086478, 0.132591, 0.204027, 0.431125, 1.092425");
+ }
+
+ } /* end of arc otp_obs_i[1]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380006.843750, 380006.906250, 380007.031250, 380007.343750, 380008.187500",\
+ "380006.937500, 380007.000000, 380007.125000, 380007.437500, 380008.281250",\
+ "380007.031250, 380007.093750, 380007.218750, 380007.531250, 380008.375000",\
+ "380007.187500, 380007.250000, 380007.375000, 380007.687500, 380008.531250",\
+ "380007.437500, 380007.500000, 380007.625000, 380007.937500, 380008.781250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380006.562500, 380006.593750, 380006.656250, 380006.812500, 380007.187500",\
+ "380006.656250, 380006.687500, 380006.750000, 380006.906250, 380007.281250",\
+ "380006.781250, 380006.812500, 380006.875000, 380007.031250, 380007.406250",\
+ "380006.968750, 380007.000000, 380007.062500, 380007.218750, 380007.593750",\
+ "380007.281250, 380007.312500, 380007.375000, 380007.531250, 380007.906250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380006.781250, 380006.843750, 380006.968750, 380007.281250, 380008.125000",\
+ "380006.875000, 380006.937500, 380007.062500, 380007.375000, 380008.218750",\
+ "380006.937500, 380007.000000, 380007.125000, 380007.437500, 380008.281250",\
+ "380007.093750, 380007.156250, 380007.281250, 380007.593750, 380008.437500",\
+ "380007.312500, 380007.375000, 380007.500000, 380007.812500, 380008.656250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380006.437500, 380006.468750, 380006.500000, 380006.656250, 380007.031250",\
+ "380006.531250, 380006.562500, 380006.593750, 380006.750000, 380007.125000",\
+ "380006.625000, 380006.656250, 380006.687500, 380006.843750, 380007.218750",\
+ "380006.812500, 380006.843750, 380006.875000, 380007.031250, 380007.406250",\
+ "380007.062500, 380007.093750, 380007.125000, 380007.281250, 380007.656250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "970006.000000, 970006.062500, 970006.125000, 970006.250000, 970006.625000",\
+ "970006.125000, 970006.187500, 970006.250000, 970006.375000, 970006.750000",\
+ "970006.125000, 970006.187500, 970006.250000, 970006.375000, 970006.750000",\
+ "970006.375000, 970006.437500, 970006.500000, 970006.625000, 970007.000000",\
+ "970006.625000, 970006.687500, 970006.750000, 970006.875000, 970007.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "970008.625000, 970008.687500, 970008.812500, 970009.125000, 970010.000000",\
+ "970008.750000, 970008.812500, 970008.937500, 970009.250000, 970010.125000",\
+ "970008.875000, 970008.937500, 970009.062500, 970009.375000, 970010.250000",\
+ "970009.125000, 970009.187500, 970009.312500, 970009.625000, 970010.500000",\
+ "970009.375000, 970009.437500, 970009.562500, 970009.875000, 970010.750000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\
+ "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\
+ "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\
+ "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\
+ "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\
+ "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\
+ "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_inv_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "590007.000000, 590007.062500, 590007.187500, 590007.500000, 590008.375000",\
+ "590007.125000, 590007.187500, 590007.312500, 590007.625000, 590008.500000",\
+ "590007.125000, 590007.187500, 590007.312500, 590007.625000, 590008.500000",\
+ "590007.250000, 590007.312500, 590007.437500, 590007.750000, 590008.625000",\
+ "590007.500000, 590007.562500, 590007.687500, 590008.000000, 590008.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\
+ "0.073824, 0.189280, 0.392442, 0.950608, 2.441526");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "590005.750000, 590005.812500, 590005.875000, 590006.000000, 590006.375000",\
+ "590005.875000, 590005.937500, 590006.000000, 590006.125000, 590006.500000",\
+ "590006.000000, 590006.062500, 590006.125000, 590006.250000, 590006.625000",\
+ "590006.125000, 590006.187500, 590006.250000, 590006.375000, 590006.750000",\
+ "590006.500000, 590006.562500, 590006.625000, 590006.750000, 590007.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\
+ "0.041204, 0.091190, 0.180893, 0.429338, 1.092497");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast2padmux_o[1]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "590006.875000, 590006.937500, 590007.062500, 590007.375000, 590008.187500",\
+ "590006.875000, 590006.937500, 590007.062500, 590007.375000, 590008.187500",\
+ "590007.000000, 590007.062500, 590007.187500, 590007.500000, 590008.312500",\
+ "590007.125000, 590007.187500, 590007.312500, 590007.625000, 590008.437500",\
+ "590007.375000, 590007.437500, 590007.562500, 590007.875000, 590008.687500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\
+ "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\
+ "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\
+ "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\
+ "0.067834, 0.184682, 0.382509, 0.937727, 2.417507");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "590005.687500, 590005.687500, 590005.750000, 590005.875000, 590006.312500",\
+ "590005.812500, 590005.812500, 590005.875000, 590006.000000, 590006.437500",\
+ "590005.937500, 590005.937500, 590006.000000, 590006.125000, 590006.562500",\
+ "590006.062500, 590006.062500, 590006.125000, 590006.250000, 590006.687500",\
+ "590006.312500, 590006.312500, 590006.375000, 590006.500000, 590006.937500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\
+ "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\
+ "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\
+ "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\
+ "0.039018, 0.090351, 0.180124, 0.429131, 1.091647");
+ }
+
+ } /* end of arc padmux2ast_i[5]_ast2padmux_o[1]_una_min*/
+
+} /* end of pin ast2padmux_o[1] */
+
+pin("ast2padmux_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.028584 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2padmux_o[0];
+ timing () {
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_val_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.265266, 0.537827, 0.806617, 1.252725, 2.144939",\
+ "0.332206, 0.604767, 0.873561, 1.319677, 2.211910",\
+ "0.448674, 0.721235, 0.990031, 1.436155, 2.328403",\
+ "0.768345, 1.040907, 1.309703, 1.755827, 2.648076",\
+ "1.623507, 1.896068, 2.164861, 2.610974, 3.503201",\
+ "0.323816, 0.596337, 0.865402, 1.310432, 2.201046",\
+ "0.390756, 0.663277, 0.932346, 1.377385, 2.268016",\
+ "0.507224, 0.779745, 1.048816, 1.493863, 2.384509",\
+ "0.826895, 1.099417, 1.368488, 1.813535, 2.704183",\
+ "1.682057, 1.954579, 2.223646, 2.668682, 3.559309",\
+ "0.467311, 0.742155, 1.009298, 1.454188, 2.344779",\
+ "0.534251, 0.809095, 1.076241, 1.521140, 2.411749",\
+ "0.650718, 0.925563, 1.192712, 1.637618, 2.528242",\
+ "0.970390, 1.245234, 1.512384, 1.957291, 2.847916",\
+ "1.825552, 2.100396, 2.367542, 2.812438, 3.703041",\
+ "0.502881, 0.779924, 1.046217, 1.490979, 2.381337",\
+ "0.569821, 0.846864, 1.113161, 1.557931, 2.448308",\
+ "0.686289, 0.963332, 1.229631, 1.674409, 2.564800",\
+ "1.005960, 1.283003, 1.549303, 1.994082, 2.884474",\
+ "1.861122, 2.138165, 2.404461, 2.849229, 3.739599",\
+ "0.827836, 1.143899, 1.397858, 1.840240, 2.726793",\
+ "0.894775, 1.210839, 1.464802, 1.907193, 2.793763",\
+ "1.011243, 1.327307, 1.581273, 2.023671, 2.910256",\
+ "1.330914, 1.646978, 1.900944, 2.343343, 3.229930",\
+ "2.186077, 2.502140, 2.756102, 3.198490, 4.085055");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\
+ "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\
+ "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\
+ "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\
+ "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\
+ "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\
+ "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\
+ "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\
+ "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\
+ "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\
+ "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\
+ "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\
+ "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\
+ "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\
+ "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\
+ "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\
+ "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\
+ "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\
+ "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\
+ "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\
+ "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\
+ "0.188995, 0.188996, 0.189001, 0.189017, 0.189048",\
+ "0.391933, 0.391935, 0.391943, 0.391965, 0.392010",\
+ "0.949299, 0.949302, 0.949319, 0.949367, 0.949463",\
+ "2.441373, 2.441374, 2.441376, 2.441385, 2.441401");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.321682, 0.506101, 0.700572, 1.011955, 1.613898",\
+ "0.353113, 0.537532, 0.732004, 1.043387, 1.645330",\
+ "0.405822, 0.590241, 0.784712, 1.096096, 1.698039",\
+ "0.548175, 0.732594, 0.927065, 1.238448, 1.840391",\
+ "0.926771, 1.111190, 1.305661, 1.617045, 2.218987",\
+ "0.381626, 0.565998, 0.760527, 1.071737, 1.673515",\
+ "0.413058, 0.597430, 0.791958, 1.103168, 1.704947",\
+ "0.465766, 0.650139, 0.844667, 1.155877, 1.757656",\
+ "0.608119, 0.792491, 0.987020, 1.298229, 1.900008",\
+ "0.986715, 1.171088, 1.365616, 1.676826, 2.278605",\
+ "0.514234, 0.698252, 0.892410, 1.203594, 1.805323",\
+ "0.545665, 0.729684, 0.923841, 1.235026, 1.836754",\
+ "0.598374, 0.782393, 0.976550, 1.287735, 1.889464",\
+ "0.740726, 0.924745, 1.118903, 1.430087, 2.031816",\
+ "1.119323, 1.303342, 1.497499, 1.808684, 2.410412",\
+ "0.547325, 0.731379, 0.925535, 1.236547, 1.837931",\
+ "0.578757, 0.762811, 0.956967, 1.267979, 1.869363",\
+ "0.631466, 0.815519, 1.009675, 1.320688, 1.922072",\
+ "0.773818, 0.957872, 1.152028, 1.463040, 2.064424",\
+ "1.152415, 1.336468, 1.530624, 1.841637, 2.443020",\
+ "0.847275, 1.036618, 1.229172, 1.539564, 2.139780",\
+ "0.878707, 1.068050, 1.260603, 1.570995, 2.171212",\
+ "0.931415, 1.120758, 1.313312, 1.623704, 2.223921",\
+ "1.073768, 1.263111, 1.455664, 1.766057, 2.366273",\
+ "1.452364, 1.641707, 1.834261, 2.144653, 2.744869");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\
+ "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\
+ "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\
+ "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\
+ "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\
+ "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\
+ "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\
+ "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\
+ "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\
+ "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\
+ "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\
+ "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\
+ "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\
+ "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\
+ "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\
+ "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\
+ "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\
+ "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\
+ "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\
+ "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\
+ "1.090832, 1.090832, 1.090832, 1.090832, 1.090832");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_rng_i" ;
+ related_output_pin : "rng_val_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.258488, 0.527564, 0.791863, 1.230215, 2.105847",\
+ "0.325417, 0.594493, 0.858794, 1.297152, 2.172797",\
+ "0.441875, 0.710952, 0.975255, 1.413618, 2.289272",\
+ "0.761546, 1.030622, 1.294926, 1.733289, 2.608944",\
+ "1.616721, 1.885797, 2.150098, 2.588454, 3.464095",\
+ "0.317013, 0.586065, 0.850631, 1.287923, 2.161954",\
+ "0.383942, 0.652994, 0.917562, 1.354860, 2.228903",\
+ "0.500401, 0.769453, 1.034023, 1.471326, 2.345379",\
+ "0.820072, 1.089123, 1.353694, 1.790997, 2.665051",\
+ "1.675247, 1.944298, 2.208866, 2.646162, 3.520202",\
+ "0.460262, 0.731823, 0.994519, 1.431727, 2.305687",\
+ "0.527191, 0.798752, 1.061450, 1.498664, 2.372636",\
+ "0.643650, 0.915210, 1.177911, 1.615129, 2.489112",\
+ "0.963321, 1.234881, 1.497581, 1.934801, 2.808784",\
+ "1.818496, 2.090056, 2.352754, 2.789966, 3.663935",\
+ "0.495756, 0.769563, 1.031437, 1.468598, 2.342245",\
+ "0.562684, 0.836492, 1.098369, 1.535535, 2.409194",\
+ "0.679143, 0.952951, 1.214829, 1.652000, 2.525670",\
+ "0.998814, 1.272622, 1.534500, 1.971672, 2.845342",\
+ "1.853989, 2.127797, 2.389672, 2.826837, 3.700493",\
+ "0.819862, 1.132963, 1.383002, 1.817902, 2.687701",\
+ "0.886791, 1.199892, 1.449933, 1.884839, 2.754651",\
+ "1.003250, 1.316351, 1.566393, 2.001304, 2.871126",\
+ "1.322921, 1.636022, 1.886065, 2.320976, 3.190798",\
+ "2.178096, 2.491197, 2.741237, 3.176141, 4.045949");
+ }
+ rise_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\
+ "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\
+ "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\
+ "0.949239, 0.949241, 0.949252, 0.949284, 0.949349",\
+ "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\
+ "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\
+ "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\
+ "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\
+ "0.949239, 0.949241, 0.949252, 0.949284, 0.949349",\
+ "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\
+ "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\
+ "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\
+ "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\
+ "0.949239, 0.949241, 0.949252, 0.949284, 0.949349",\
+ "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\
+ "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\
+ "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\
+ "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\
+ "0.949239, 0.949241, 0.949252, 0.949285, 0.949349",\
+ "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\
+ "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\
+ "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\
+ "0.391905, 0.391906, 0.391912, 0.391927, 0.391957",\
+ "0.949239, 0.949241, 0.949252, 0.949285, 0.949349",\
+ "2.441363, 2.441364, 2.441365, 2.441371, 2.441381");
+ }
+ cell_fall( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.280172, 0.467016, 0.660531, 0.967486, 1.558860",\
+ "0.311589, 0.498432, 0.691948, 0.998903, 1.590277",\
+ "0.364248, 0.551092, 0.744607, 1.051563, 1.642938",\
+ "0.506650, 0.693493, 0.887008, 1.193964, 1.785338",\
+ "0.885283, 1.072126, 1.265642, 1.572596, 2.163970",\
+ "0.340116, 0.526843, 0.720376, 1.027255, 1.618477",\
+ "0.371533, 0.558260, 0.751792, 1.058672, 1.649894",\
+ "0.424192, 0.610919, 0.804452, 1.111332, 1.702555",\
+ "0.566594, 0.753321, 0.946853, 1.253732, 1.844955",\
+ "0.945227, 1.131954, 1.325486, 1.632365, 2.223587",\
+ "0.472755, 0.659097, 0.852258, 1.159112, 1.750284",\
+ "0.504172, 0.690514, 0.883675, 1.190529, 1.781701",\
+ "0.556831, 0.743173, 0.936334, 1.243189, 1.834362",\
+ "0.699233, 0.885575, 1.078736, 1.385590, 1.976762",\
+ "1.077866, 1.264208, 1.457369, 1.764223, 2.355394",\
+ "0.505869, 0.692396, 0.885489, 1.192192, 1.783144",\
+ "0.537286, 0.723812, 0.916906, 1.223609, 1.814562",\
+ "0.589945, 0.776472, 0.969565, 1.276269, 1.867223",\
+ "0.732346, 0.918873, 1.111966, 1.418670, 2.009622",\
+ "1.110980, 1.297506, 1.490599, 1.797303, 2.388254",\
+ "0.806127, 0.997856, 1.189152, 1.495396, 2.085451",\
+ "0.837544, 1.029273, 1.220569, 1.526813, 2.116868",\
+ "0.890203, 1.081932, 1.273229, 1.579473, 2.169529",\
+ "1.032604, 1.224334, 1.415630, 1.721874, 2.311929",\
+ "1.411238, 1.602967, 1.794263, 2.100507, 2.690561");
+ }
+ fall_transition( f_itrans_ocap_rcap ){
+ index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011");
+ values ( "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\
+ "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\
+ "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\
+ "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\
+ "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\
+ "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\
+ "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\
+ "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\
+ "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\
+ "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\
+ "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\
+ "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\
+ "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\
+ "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\
+ "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\
+ "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\
+ "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\
+ "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\
+ "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\
+ "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\
+ "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\
+ "0.090706, 0.090706, 0.090706, 0.090705, 0.090703",\
+ "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\
+ "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\
+ "1.091504, 1.091503, 1.091503, 1.091496, 1.091479");
+ }
+
+ } /* end of arc clk_ast_rng_i_ast2padmux_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\
+ "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\
+ "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\
+ "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073650, 0.189354, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189354, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189365, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189385, 0.392560, 0.950561, 2.441537",\
+ "0.073650, 0.189425, 0.393252, 0.950561, 2.441537");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\
+ "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\
+ "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\
+ "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\
+ "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\
+ "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\
+ "0.643636, 0.699058, 0.793671, 1.054205, 1.742813");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\
+ "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\
+ "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\
+ "0.054820, 0.149920, 0.315966, 0.770514, 1.988361");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\
+ "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\
+ "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\
+ "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\
+ "0.630702, 0.654723, 0.683267, 0.752219, 0.936438");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\
+ "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2padmux_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "fla_obs_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\
+ "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\
+ "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\
+ "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\
+ "0.629434, 0.713469, 0.835221, 1.155234, 2.004311");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\
+ "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\
+ "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\
+ "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\
+ "0.099054, 0.205738, 0.390315, 0.940320, 2.425200");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\
+ "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\
+ "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\
+ "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\
+ "0.668936, 0.733428, 0.809479, 0.962224, 1.340585");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\
+ "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\
+ "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\
+ "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\
+ "0.118581, 0.174509, 0.240947, 0.445113, 1.092793");
+ }
+
+ } /* end of arc fla_obs_i[0]_ast2padmux_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "fla_obs_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\
+ "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\
+ "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\
+ "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\
+ "0.610985, 0.691263, 0.810230, 1.128954, 1.977655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\
+ "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\
+ "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\
+ "0.093347, 0.198994, 0.384563, 0.939701, 2.425563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\
+ "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\
+ "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\
+ "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\
+ "0.615736, 0.679130, 0.754042, 0.905113, 1.283136");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\
+ "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\
+ "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\
+ "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\
+ "0.116096, 0.171326, 0.236992, 0.441817, 1.092511");
+ }
+
+ } /* end of arc fla_obs_i[0]_ast2padmux_o[0]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.454321, 0.521261, 0.637729, 0.957401, 1.812562",\
+ "0.476584, 0.543525, 0.659993, 0.979665, 1.834826",\
+ "0.532978, 0.599918, 0.716386, 1.036058, 1.891219",\
+ "0.630840, 0.697781, 0.814249, 1.133921, 1.989082",\
+ "1.144998, 1.211940, 1.328409, 1.648081, 2.503240");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073066, 0.188998, 0.391939, 0.949310, 2.441375");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.506462, 0.537893, 0.590602, 0.732954, 1.111551",\
+ "0.527996, 0.559427, 0.612136, 0.754488, 1.133085",\
+ "0.595181, 0.626613, 0.679322, 0.821674, 1.200271",\
+ "0.705480, 0.736911, 0.789620, 0.931973, 1.310569",\
+ "1.265269, 1.296700, 1.349409, 1.491761, 1.870358");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090610, 0.180696, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.421371, 0.488300, 0.604758, 0.924429, 1.779604",\
+ "0.442149, 0.509077, 0.625536, 0.945207, 1.800382",\
+ "0.499740, 0.566669, 0.683127, 1.002798, 1.857973",\
+ "0.597685, 0.664614, 0.781072, 1.100743, 1.955918",\
+ "1.086534, 1.153463, 1.269921, 1.589592, 2.444767");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.412434, 0.443851, 0.496510, 0.638912, 1.017545",\
+ "0.429840, 0.461257, 0.513916, 0.656317, 1.034951",\
+ "0.502410, 0.533827, 0.586486, 0.728887, 1.107521",\
+ "0.615047, 0.646463, 0.699123, 0.841524, 1.220157",\
+ "1.142076, 1.173492, 1.226152, 1.368553, 1.747186");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.453258, 0.484690, 0.537398, 0.679751, 1.058348",\
+ "0.478327, 0.509759, 0.562468, 0.704820, 1.083417",\
+ "0.547548, 0.578980, 0.631688, 0.774041, 1.152637",\
+ "0.671779, 0.703211, 0.755919, 0.898272, 1.276869",\
+ "1.305416, 1.336847, 1.389556, 1.531909, 1.910505");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090610, 0.180696, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.686438, 0.753379, 0.869847, 1.189519, 2.044680",\
+ "0.706913, 0.773853, 0.890321, 1.209993, 2.065154",\
+ "0.765773, 0.832713, 0.949182, 1.268853, 2.124014",\
+ "0.875012, 0.941953, 1.058421, 1.378093, 2.233254",\
+ "1.652212, 1.719154, 1.835623, 2.155295, 3.010454");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073066, 0.188998, 0.391939, 0.949310, 2.441375");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[10]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.282064, 0.313481, 0.366140, 0.508541, 0.887175",\
+ "0.305674, 0.337091, 0.389750, 0.532151, 0.910785",\
+ "0.377014, 0.408430, 0.461090, 0.603491, 0.982124",\
+ "0.496822, 0.528239, 0.580898, 0.723300, 1.101933",\
+ "1.041943, 1.073360, 1.126019, 1.268421, 1.647054");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.590884, 0.657812, 0.774271, 1.093942, 1.949117",\
+ "0.607576, 0.674504, 0.790963, 1.110634, 1.965809",\
+ "0.669970, 0.736899, 0.853357, 1.173028, 2.028203",\
+ "0.779360, 0.846288, 0.962747, 1.282418, 2.137593",\
+ "1.516501, 1.583430, 1.699888, 2.019559, 2.874734");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363");
+ }
+
+ } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.197401, 0.228828, 0.281523, 0.423889, 0.802496",\
+ "0.210783, 0.242210, 0.294905, 0.437272, 0.815878",\
+ "0.293723, 0.325151, 0.377848, 0.520213, 0.898818",\
+ "0.418374, 0.449806, 0.502515, 0.644867, 1.023463",\
+ "1.005445, 1.038016, 1.090870, 1.233261, 1.611881");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039115, 0.090636, 0.180627, 0.429260, 1.091020",\
+ "0.039115, 0.090636, 0.180627, 0.429260, 1.091020",\
+ "0.039119, 0.090636, 0.180636, 0.429262, 1.091020",\
+ "0.039145, 0.090636, 0.180699, 0.429276, 1.091020",\
+ "0.042423, 0.091616, 0.180853, 0.429341, 1.091020");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.483196, 0.550400, 0.667026, 0.986767, 1.841721",\
+ "0.495454, 0.562658, 0.679284, 0.999025, 1.853979",\
+ "0.559644, 0.626847, 0.743473, 1.063213, 1.918167",\
+ "0.662607, 0.729816, 0.846440, 1.166186, 2.021145",\
+ "1.344671, 1.412041, 1.528612, 1.848528, 2.703634");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073644, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073644, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073644, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073683, 0.189305, 0.392450, 0.950570, 2.441537",\
+ "0.075005, 0.189305, 0.392450, 0.950931, 2.441537");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[11]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.178015, 0.209429, 0.262079, 0.404490, 0.783130",\
+ "0.189390, 0.220804, 0.273454, 0.415865, 0.794505",\
+ "0.274579, 0.305993, 0.358646, 0.501054, 0.879692",\
+ "0.400471, 0.431892, 0.484565, 0.626953, 1.005576",\
+ "0.985792, 1.018105, 1.070937, 1.213308, 1.591914");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090679, 0.180398, 0.429208, 1.090559",\
+ "0.039020, 0.090679, 0.180398, 0.429208, 1.090559",\
+ "0.039027, 0.090679, 0.180413, 0.429212, 1.090559",\
+ "0.039069, 0.090679, 0.180517, 0.429235, 1.090559",\
+ "0.041694, 0.091361, 0.180877, 0.429339, 1.090559");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.476048, 0.543228, 0.659862, 0.979577, 1.834510",\
+ "0.484692, 0.551872, 0.668506, 0.988221, 1.843154",\
+ "0.552511, 0.619690, 0.736325, 1.056039, 1.910971",\
+ "0.655347, 0.722531, 0.839164, 1.158884, 2.013820",\
+ "1.333397, 1.400722, 1.517308, 1.837177, 2.692242");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073446, 0.189167, 0.392403, 0.950504, 2.441474",\
+ "0.073446, 0.189167, 0.392403, 0.950504, 2.441474",\
+ "0.073446, 0.189167, 0.392403, 0.950504, 2.441474",\
+ "0.073481, 0.189167, 0.392403, 0.950515, 2.441474",\
+ "0.074640, 0.189167, 0.392403, 0.950831, 2.441474");
+ }
+
+ } /* end of arc obs_ctrl_o[11]_ast2padmux_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.518600, 0.585804, 0.702430, 1.022170, 1.877124",\
+ "0.534366, 0.601569, 0.718195, 1.037936, 1.892890",\
+ "0.608476, 0.675680, 0.792306, 1.112046, 1.967001",\
+ "0.699697, 0.766901, 0.883527, 1.203267, 2.058222",\
+ "1.126490, 1.193697, 1.310322, 1.630066, 2.485023");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073643, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073671, 0.189301, 0.392449, 0.950567, 2.441536");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\
+ "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\
+ "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\
+ "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\
+ "1.013269, 1.044421, 1.097036, 1.239541, 1.618177");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\
+ "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\
+ "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\
+ "0.040759, 0.090635, 0.180631, 0.429261, 1.092499",\
+ "0.040922, 0.090603, 0.180713, 0.429279, 1.092539");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\
+ "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\
+ "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\
+ "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\
+ "0.949078, 1.015776, 1.132136, 1.448920, 2.298678");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.228794, 0.260208, 0.312858, 0.455269, 0.833909",\
+ "0.240665, 0.272079, 0.324729, 0.467140, 0.845780",\
+ "0.323160, 0.354574, 0.407224, 0.549635, 0.928275",\
+ "0.428120, 0.459534, 0.512186, 0.654595, 1.033234",\
+ "0.930331, 0.961753, 1.014431, 1.156814, 1.535434");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039024, 0.090327, 0.180161, 0.428971, 1.091612",\
+ "0.039078, 0.090324, 0.180166, 0.428948, 1.091257");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\
+ "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\
+ "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\
+ "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\
+ "0.918190, 0.949342, 1.001956, 1.144462, 1.523098");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\
+ "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\
+ "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\
+ "0.040759, 0.090635, 0.180631, 0.429261, 1.092499",\
+ "0.040922, 0.090603, 0.180713, 0.429279, 1.092539");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\
+ "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\
+ "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\
+ "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\
+ "1.006927, 1.073706, 1.190415, 1.507149, 2.356620");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073643, 0.189305, 0.392450, 0.950559, 2.441537",\
+ "0.073671, 0.189301, 0.392449, 0.950567, 2.441536");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\
+ "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\
+ "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\
+ "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\
+ "0.893831, 0.925076, 0.977718, 1.120154, 1.498834");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039024, 0.090327, 0.180161, 0.428971, 1.091612",\
+ "0.039078, 0.090324, 0.180166, 0.428948, 1.091257");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\
+ "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\
+ "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\
+ "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\
+ "1.002245, 1.068944, 1.185303, 1.502088, 2.351846");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\
+ "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\
+ "0.067604, 0.184551, 0.382483, 0.937052, 2.417689");
+ }
+
+ } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\
+ "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\
+ "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\
+ "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\
+ "0.997007, 1.063817, 1.180658, 1.497372, 2.346736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\
+ "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\
+ "0.073641, 0.189305, 0.392450, 0.950559, 2.441538",\
+ "0.073704, 0.189296, 0.392447, 0.950576, 2.441534",\
+ "0.075364, 0.189067, 0.392369, 0.951029, 2.441428");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\
+ "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\
+ "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\
+ "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\
+ "1.004117, 1.035227, 1.087829, 1.230366, 1.608983");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\
+ "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\
+ "0.040752, 0.090636, 0.180636, 0.429262, 1.092497",\
+ "0.040771, 0.090636, 0.180700, 0.429276, 1.092502",\
+ "0.042582, 0.091671, 0.180848, 0.429341, 1.092666");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\
+ "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\
+ "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\
+ "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\
+ "0.957622, 1.024367, 1.140929, 1.457685, 2.307276");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\
+ "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\
+ "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\
+ "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\
+ "0.955028, 0.986237, 1.038869, 1.181331, 1.559995");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091594",\
+ "0.039070, 0.090324, 0.180167, 0.428947, 1.091311",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.090589");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.194141, 0.225569, 0.278263, 0.420630, 0.799236",\
+ "0.213398, 0.244825, 0.297520, 0.439886, 0.818493",\
+ "0.291110, 0.322538, 0.375235, 0.517599, 0.896205",\
+ "0.414666, 0.446098, 0.498807, 0.641159, 1.019755",\
+ "0.992685, 1.025312, 1.078170, 1.220567, 1.599190");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\
+ "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\
+ "0.040752, 0.090636, 0.180636, 0.429262, 1.092497",\
+ "0.040771, 0.090636, 0.180700, 0.429276, 1.092502",\
+ "0.042582, 0.091671, 0.180848, 0.429341, 1.092666");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.473555, 0.540758, 0.657385, 0.977125, 1.832079",\
+ "0.486694, 0.553897, 0.670524, 0.990264, 1.845218",\
+ "0.549031, 0.616234, 0.732861, 1.052601, 1.907555",\
+ "0.658256, 0.725467, 0.842091, 1.161839, 2.016800",\
+ "1.359176, 1.426589, 1.543146, 1.863108, 2.718254");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\
+ "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\
+ "0.073641, 0.189305, 0.392450, 0.950559, 2.441538",\
+ "0.073704, 0.189296, 0.392447, 0.950576, 2.441534",\
+ "0.075364, 0.189067, 0.392369, 0.951029, 2.441428");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[5]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.174738, 0.206152, 0.258801, 0.401212, 0.779853",\
+ "0.192387, 0.223801, 0.276451, 0.418861, 0.797502",\
+ "0.271960, 0.303374, 0.356027, 0.498435, 0.877073",\
+ "0.396781, 0.428202, 0.480875, 0.623262, 1.001885",\
+ "0.972879, 1.005251, 1.058088, 1.200464, 1.579073");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039026, 0.090327, 0.180161, 0.428971, 1.091594",\
+ "0.039070, 0.090324, 0.180167, 0.428947, 1.091311",\
+ "0.040211, 0.090294, 0.180212, 0.428752, 1.090589");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.466421, 0.533601, 0.650235, 0.969950, 1.824882",\
+ "0.476202, 0.543381, 0.660016, 0.979730, 1.834662",\
+ "0.541892, 0.609071, 0.725705, 1.045420, 1.900352",\
+ "0.650936, 0.718122, 0.834754, 1.154476, 2.009415",\
+ "1.346760, 1.414122, 1.530696, 1.850604, 2.705703");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\
+ "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\
+ "0.067439, 0.184458, 0.382464, 0.936568, 2.417820");
+ }
+
+ } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.313610, 0.380815, 0.497441, 0.817182, 1.672137",\
+ "0.329358, 0.396562, 0.513188, 0.832930, 1.687885",\
+ "0.393235, 0.460439, 0.577065, 0.896806, 1.751761",\
+ "0.471556, 0.538760, 0.655386, 0.975126, 1.830081",\
+ "0.862244, 0.929448, 1.046074, 1.365815, 2.220770");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189305, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189305, 0.392450, 0.950561, 2.441537");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.191794, 0.223225, 0.275933, 0.418286, 0.796883",\
+ "0.207675, 0.239106, 0.291815, 0.434167, 0.812764",\
+ "0.277023, 0.308454, 0.361162, 0.503515, 0.882112",\
+ "0.365690, 0.397121, 0.449830, 0.592182, 0.970779",\
+ "0.790485, 0.821927, 0.874671, 1.016989, 1.395559");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040785, 0.090539, 0.180878, 0.429316, 1.092505");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.289937, 0.356887, 0.473363, 0.793036, 1.648185",\
+ "0.304047, 0.370997, 0.487474, 0.807146, 1.662295",\
+ "0.369617, 0.436567, 0.553044, 0.872716, 1.727865",\
+ "0.448151, 0.515103, 0.631581, 0.951254, 1.806401",\
+ "0.842717, 0.909715, 1.026232, 1.345907, 2.200999");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.167066, 0.198479, 0.251128, 0.393540, 0.772181",\
+ "0.179068, 0.210482, 0.263130, 0.405543, 0.784184",\
+ "0.252467, 0.283881, 0.336530, 0.478942, 0.857582",\
+ "0.341502, 0.372916, 0.425566, 0.567976, 0.946617",\
+ "0.759790, 0.791205, 0.843857, 0.986265, 1.364904");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\
+ "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\
+ "0.039019, 0.090327, 0.180161, 0.428971, 1.091642",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039025, 0.090322, 0.180169, 0.428938, 1.091600");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\
+ "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\
+ "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\
+ "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\
+ "0.984655, 1.015818, 1.068436, 1.210933, 1.589574");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040785, 0.090539, 0.180878, 0.429316, 1.092505");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.614118, 0.681322, 0.797948, 1.117689, 1.972644",\
+ "0.626922, 0.694126, 0.810752, 1.130493, 1.985448",\
+ "0.694897, 0.762101, 0.878727, 1.198468, 2.053423",\
+ "0.806557, 0.873761, 0.990387, 1.310127, 2.165082",\
+ "1.291436, 1.358640, 1.475266, 1.795007, 2.649961");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189305, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189305, 0.392450, 0.950561, 2.441537");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[6]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.270718, 0.301966, 0.354610, 0.497042, 0.875725",\
+ "0.284868, 0.316117, 0.368760, 0.511193, 0.889875",\
+ "0.364362, 0.395610, 0.448254, 0.590687, 0.969369",\
+ "0.465503, 0.496751, 0.549395, 0.691827, 1.070510",\
+ "0.941451, 0.972693, 1.025335, 1.167772, 1.546452");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\
+ "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\
+ "0.039019, 0.090327, 0.180161, 0.428971, 1.091642",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039025, 0.090322, 0.180169, 0.428938, 1.091600");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\
+ "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\
+ "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\
+ "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\
+ "1.131911, 1.198614, 1.314996, 1.631778, 2.481517");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067586, 0.184541, 0.382481, 0.936998, 2.417704");
+ }
+
+ } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\
+ "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\
+ "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\
+ "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\
+ "1.020553, 1.055041, 1.108054, 1.250599, 1.629324");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\
+ "0.040752, 0.090610, 0.180832, 0.429306, 1.092497",\
+ "0.047830, 0.093504, 0.180832, 0.429352, 1.092504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.615123, 0.682328, 0.798954, 1.118695, 1.973650",\
+ "0.635870, 0.703074, 0.819700, 1.139442, 1.994397",\
+ "0.701192, 0.768396, 0.885022, 1.204764, 2.059719",\
+ "0.815370, 0.882574, 0.999200, 1.318941, 2.173895",\
+ "1.395166, 1.462382, 1.579004, 1.898758, 2.753724");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189305, 0.392450, 0.950561, 2.441537",\
+ "0.073748, 0.189305, 0.392450, 0.950588, 2.441537");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[7]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.132284, 0.163698, 0.216345, 0.358758, 0.737400",\
+ "0.152768, 0.184181, 0.236829, 0.379242, 0.757883",\
+ "0.226947, 0.258361, 0.311010, 0.453421, 0.832062",\
+ "0.328095, 0.359509, 0.412158, 0.554569, 0.933209",\
+ "0.769672, 0.801087, 0.853739, 0.996148, 1.374786");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039016, 0.090327, 0.180161, 0.428971, 1.091660",\
+ "0.039016, 0.090327, 0.180161, 0.428971, 1.091660",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\
+ "0.039025, 0.090323, 0.180168, 0.428941, 1.091602");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.268552, 0.335503, 0.451979, 0.771651, 1.626801",\
+ "0.284564, 0.351514, 0.467990, 0.787663, 1.642812",\
+ "0.357242, 0.424196, 0.540676, 0.860348, 1.715493",\
+ "0.477594, 0.544576, 0.661079, 0.980754, 1.835865",\
+ "1.125477, 1.192657, 1.309291, 1.629006, 2.483939");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\
+ "0.067601, 0.184550, 0.382483, 0.937044, 2.417691");
+ }
+
+ } /* end of arc obs_ctrl_o[7]_ast2padmux_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.711181, 0.778121, 0.894590, 1.214261, 2.069422",\
+ "0.729530, 0.796471, 0.912939, 1.232611, 2.087772",\
+ "0.800074, 0.867014, 0.983483, 1.303154, 2.158315",\
+ "0.892545, 0.959485, 1.075954, 1.395625, 2.250786",\
+ "1.377232, 1.444175, 1.560645, 1.880316, 2.735475");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073067, 0.188999, 0.391940, 0.949314, 2.441375");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.503942, 0.535373, 0.588082, 0.730435, 1.109031",\
+ "0.521369, 0.552801, 0.605509, 0.747862, 1.126459",\
+ "0.598766, 0.630198, 0.682907, 0.825259, 1.203856",\
+ "0.707080, 0.738512, 0.791220, 0.933573, 1.312169",\
+ "1.259288, 1.290720, 1.343428, 1.485781, 1.864378");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090610, 0.180696, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.645044, 0.711973, 0.828431, 1.148102, 2.003277",\
+ "0.661659, 0.728588, 0.845047, 1.164717, 2.019893",\
+ "0.736081, 0.803009, 0.919468, 1.239139, 2.094314",\
+ "0.830502, 0.897430, 1.013889, 1.333560, 2.188735",\
+ "1.278260, 1.345188, 1.461647, 1.781317, 2.636493");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.359441, 0.390858, 0.443517, 0.585919, 0.964552",\
+ "0.372788, 0.404204, 0.456864, 0.599265, 0.977898",\
+ "0.454765, 0.486182, 0.538841, 0.681242, 1.059876",\
+ "0.563985, 0.595401, 0.648061, 0.790462, 1.169096",\
+ "1.087607, 1.119023, 1.171683, 1.314084, 1.692717");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.540276, 0.571708, 0.624416, 0.766769, 1.145365",\
+ "0.558625, 0.590057, 0.642766, 0.785118, 1.163715",\
+ "0.632481, 0.663913, 0.716621, 0.858974, 1.237571",\
+ "0.730741, 0.762172, 0.814881, 0.957234, 1.335830",\
+ "1.254148, 1.285579, 1.338288, 1.480641, 1.859237");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090610, 0.180696, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.661922, 0.728863, 0.845331, 1.165002, 2.020164",\
+ "0.674544, 0.741485, 0.857953, 1.177625, 2.032786",\
+ "0.729459, 0.796399, 0.912867, 1.232539, 2.087700",\
+ "0.831878, 0.898819, 1.015287, 1.334959, 2.190120",\
+ "1.558837, 1.625780, 1.742250, 2.061921, 2.917080");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073067, 0.188999, 0.391940, 0.949314, 2.441375");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[8]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.287469, 0.318885, 0.371545, 0.513946, 0.892579",\
+ "0.304214, 0.335631, 0.388290, 0.530692, 0.909325",\
+ "0.382471, 0.413888, 0.466547, 0.608949, 0.987582",\
+ "0.506351, 0.537768, 0.590427, 0.732828, 1.111462",\
+ "1.074942, 1.106358, 1.159018, 1.301419, 1.680052");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.464880, 0.531808, 0.648267, 0.967938, 1.823113",\
+ "0.478226, 0.545155, 0.661613, 0.981284, 1.836459",\
+ "0.556365, 0.623294, 0.739753, 1.059423, 1.914599",\
+ "0.657544, 0.724473, 0.840931, 1.160602, 2.015777",\
+ "1.129399, 1.196328, 1.312786, 1.632457, 2.487632");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363");
+ }
+
+ } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.722991, 0.789932, 0.906400, 1.226072, 2.081233",\
+ "0.741544, 0.808485, 0.924953, 1.244625, 2.099786",\
+ "0.814242, 0.881183, 0.997651, 1.317322, 2.172483",\
+ "0.909467, 0.976408, 1.092876, 1.412548, 2.267709",\
+ "1.368597, 1.435539, 1.552008, 1.871680, 2.726840");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073066, 0.188998, 0.391938, 0.949310, 2.441375");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.510317, 0.541749, 0.594457, 0.736810, 1.115407",\
+ "0.527859, 0.559291, 0.612000, 0.754352, 1.132949",\
+ "0.605188, 0.636620, 0.689329, 0.831681, 1.210278",\
+ "0.714634, 0.746065, 0.798774, 0.941126, 1.319723",\
+ "1.246573, 1.278005, 1.330713, 1.473066, 1.851663");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090610, 0.180696, 0.429275, 1.090836");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.677174, 0.744103, 0.860561, 1.180232, 2.035407",\
+ "0.693995, 0.760924, 0.877382, 1.197053, 2.052228",\
+ "0.768427, 0.835355, 0.951814, 1.271485, 2.126660",\
+ "0.863682, 0.930611, 1.047069, 1.366740, 2.221915",\
+ "1.316333, 1.383262, 1.499720, 1.819391, 2.674566");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.381372, 0.412788, 0.465448, 0.607849, 0.986482",\
+ "0.394828, 0.426245, 0.478904, 0.621306, 0.999939",\
+ "0.476249, 0.507665, 0.560325, 0.702726, 1.081359",\
+ "0.586223, 0.617640, 0.670299, 0.812701, 1.191334",\
+ "1.111662, 1.143078, 1.195738, 1.338139, 1.716772");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_una_min*/
+
+ timing () {
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.544142, 0.575574, 0.628282, 0.770635, 1.149231",\
+ "0.562695, 0.594126, 0.646835, 0.789188, 1.167784",\
+ "0.636753, 0.668185, 0.720893, 0.863246, 1.241843",\
+ "0.735854, 0.767286, 0.819994, 0.962347, 1.340943",\
+ "1.209522, 1.240954, 1.293662, 1.436015, 1.814612");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\
+ "0.039144, 0.090610, 0.180696, 0.429275, 1.090836");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.616983, 0.683923, 0.800391, 1.120063, 1.975224",\
+ "0.629672, 0.696613, 0.813081, 1.132753, 1.987914",\
+ "0.684443, 0.751384, 0.867852, 1.187524, 2.042685",\
+ "0.787482, 0.854422, 0.970891, 1.290562, 2.145723",\
+ "1.494185, 1.561127, 1.677597, 1.997268, 2.852428");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\
+ "0.073066, 0.188998, 0.391938, 0.949310, 2.441375");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "obs_ctrl_o[9]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.282372, 0.313788, 0.366448, 0.508849, 0.887482",\
+ "0.299186, 0.330603, 0.383262, 0.525663, 0.904297",\
+ "0.377525, 0.408942, 0.461601, 0.604002, 0.982636",\
+ "0.500058, 0.531475, 0.584134, 0.726535, 1.105169",\
+ "1.057248, 1.088664, 1.141323, 1.283725, 1.662358");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\
+ "0.039040, 0.090706, 0.180446, 0.429219, 1.091504");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.472156, 0.539085, 0.655543, 0.975214, 1.830389",\
+ "0.485612, 0.552541, 0.669000, 0.988670, 1.843846",\
+ "0.563901, 0.630829, 0.747288, 1.066959, 1.922134",\
+ "0.663577, 0.730506, 0.846965, 1.166635, 2.021811",\
+ "1.128422, 1.195350, 1.311809, 1.631480, 2.486655");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\
+ "0.073056, 0.188976, 0.391905, 0.949239, 2.441363");
+ }
+
+ } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_inv_min*/
+
+ timing () {
+ related_pin : "otm_obs_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.113025, 0.179927, 0.296363, 0.616032, 1.471239",\
+ "0.197499, 0.264597, 0.381195, 0.700878, 1.555851",\
+ "0.280076, 0.347397, 0.463985, 0.783849, 1.638912",\
+ "0.416433, 0.486812, 0.604025, 0.924187, 1.779474",\
+ "0.624246, 0.705773, 0.827408, 1.148979, 2.004448");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073036, 0.188929, 0.391837, 0.949094, 2.441339",\
+ "0.073183, 0.189268, 0.392332, 0.950151, 2.441515",\
+ "0.074613, 0.189268, 0.392404, 0.950824, 2.441515",\
+ "0.081868, 0.192856, 0.392640, 0.950928, 2.441515",\
+ "0.102993, 0.209850, 0.398253, 0.950928, 2.441550");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.102851, 0.134278, 0.186974, 0.329339, 0.707946",\
+ "0.188654, 0.220274, 0.273049, 0.415364, 0.793932",\
+ "0.283232, 0.317549, 0.370548, 0.513080, 0.891796",\
+ "0.439854, 0.481254, 0.538206, 0.682122, 1.061087",\
+ "0.686111, 0.743348, 0.813206, 0.964006, 1.344314");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039116, 0.090635, 0.180630, 0.429260, 1.091011",\
+ "0.039742, 0.090679, 0.180942, 0.429335, 1.091011",\
+ "0.047350, 0.093337, 0.180942, 0.429351, 1.091547",\
+ "0.062153, 0.106580, 0.187253, 0.429567, 1.092904",\
+ "0.090069, 0.142497, 0.212830, 0.435355, 1.093832");
+ }
+
+ } /* end of arc otm_obs_i[0]_ast2padmux_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otm_obs_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.111805, 0.178694, 0.295120, 0.614788, 1.470008",\
+ "0.195286, 0.262361, 0.378939, 0.698621, 1.553622",\
+ "0.274742, 0.342025, 0.458625, 0.778449, 1.633475",\
+ "0.405125, 0.474114, 0.590991, 0.911111, 1.766377",\
+ "0.603219, 0.681326, 0.800406, 1.120805, 1.976209");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073037, 0.188925, 0.391823, 0.948978, 2.441330",\
+ "0.073166, 0.189215, 0.392273, 0.950004, 2.441389",\
+ "0.074291, 0.189215, 0.392420, 0.950004, 2.441389",\
+ "0.079135, 0.190954, 0.392488, 0.950004, 2.441389",\
+ "0.097064, 0.203428, 0.393485, 0.950004, 2.441492");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.077369, 0.108778, 0.161412, 0.303838, 0.682490",\
+ "0.166731, 0.198172, 0.250911, 0.393234, 0.771808",\
+ "0.254923, 0.288717, 0.341672, 0.484162, 0.862849",\
+ "0.400634, 0.441041, 0.497234, 0.640906, 1.019844",\
+ "0.631133, 0.687293, 0.756057, 0.905549, 1.285508");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.038988, 0.090550, 0.180320, 0.429191, 1.090420",\
+ "0.039208, 0.090550, 0.180739, 0.429310, 1.090420",\
+ "0.045872, 0.092820, 0.180739, 0.429348, 1.091289",\
+ "0.060397, 0.104342, 0.185891, 0.429526, 1.092845",\
+ "0.088207, 0.140006, 0.210014, 0.433521, 1.093776");
+ }
+
+ } /* end of arc otm_obs_i[0]_ast2padmux_o[0]_una_min*/
+
+ timing () {
+ related_pin : "otp_obs_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\
+ "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\
+ "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\
+ "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\
+ "0.699992, 0.780922, 0.900058, 1.218756, 2.067549");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\
+ "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\
+ "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\
+ "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\
+ "0.094401, 0.199857, 0.384817, 0.940410, 2.426093");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\
+ "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\
+ "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\
+ "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\
+ "0.820213, 0.870292, 0.933027, 1.077593, 1.455130");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\
+ "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\
+ "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\
+ "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\
+ "0.087354, 0.133744, 0.204884, 0.431205, 1.092443");
+ }
+
+ } /* end of arc otp_obs_i[0]_ast2padmux_o[0]_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "otp_obs_i[0]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\
+ "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\
+ "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\
+ "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\
+ "0.667813, 0.745674, 0.864272, 1.183300, 2.031636");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\
+ "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\
+ "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\
+ "0.089380, 0.196045, 0.384240, 0.939859, 2.423100");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\
+ "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\
+ "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\
+ "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\
+ "0.773733, 0.823401, 0.885774, 1.030256, 1.407808");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\
+ "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\
+ "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\
+ "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\
+ "0.086478, 0.132591, 0.204027, 0.431125, 1.092425");
+ }
+
+ } /* end of arc otp_obs_i[0]_ast2padmux_o[0]_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\
+ "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\
+ "0.040752, 0.090609, 0.180697, 0.429275, 1.092497");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\
+ "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\
+ "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\
+ "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\
+ "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\
+ "0.073650, 0.189304, 0.392450, 0.950561, 2.441537");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[0]_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\
+ "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\
+ "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\
+ "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\
+ "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\
+ "0.015905, 0.041179, 0.085652, 0.207740, 0.535967");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\
+ "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\
+ "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\
+ "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\
+ "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584");
+ values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\
+ "0.055484, 0.149920, 0.315966, 0.772511, 1.992169");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2padmux_o[0]_inv_min*/
+
+} /* end of pin ast2padmux_o[0] */
+} /* end of bus ast2padmux_o */
+
+pin("ast2pad_t0_ao") {
+ direction : output ;
+ max_transition : 5.000000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.340000 ;
+ min_capacitance : 0.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2pad_t0_ao;
+} /* end of pin ast2pad_t0_ao */
+
+pin("ast2pad_t1_ao") {
+ direction : output ;
+ max_transition : 5.000000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 64.000000 ;
+ min_capacitance : 0.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : ast2pad_t1_ao;
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000");
+ values ( "380005.937500, 380010.968750, 380015.437500, 380024.343750, 380042.031250",\
+ "380006.031250, 380011.062500, 380015.531250, 380024.437500, 380042.125000",\
+ "380006.125000, 380011.156250, 380015.625000, 380024.531250, 380042.218750",\
+ "380006.187500, 380011.218750, 380015.687500, 380024.593750, 380042.281250",\
+ "380006.531250, 380011.562500, 380016.031250, 380024.937500, 380042.625000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000");
+ values ( "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\
+ "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\
+ "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\
+ "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\
+ "0.131672, 1.724206, 3.350886, 6.646091, 13.236232");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2pad_t1_ao_redgf*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000");
+ values ( "3.958968, 8.968638, 13.431835, 22.333540, 40.062149",\
+ "4.046352, 9.056024, 13.519220, 22.420925, 40.149536",\
+ "4.127131, 9.136803, 13.599998, 22.501705, 40.230312",\
+ "4.184652, 9.194324, 13.657520, 22.559225, 40.287834",\
+ "4.486489, 9.496161, 13.959356, 22.861061, 40.589668");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000");
+ values ( "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\
+ "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\
+ "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\
+ "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\
+ "0.000000, 0.000000, 0.000000, 0.000000, 0.000000");
+ }
+
+ } /* end of arc clk_ast_tlul_i_ast2pad_t1_ao_redgf_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : three_state_enable_fall ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000");
+ values ( "380005.843750, 380010.875000, 380015.343750, 380024.250000, 380041.937500",\
+ "380005.937500, 380010.968750, 380015.437500, 380024.343750, 380042.031250",\
+ "380006.062500, 380011.093750, 380015.562500, 380024.468750, 380042.156250",\
+ "380006.250000, 380011.281250, 380015.750000, 380024.656250, 380042.343750",\
+ "380006.562500, 380011.593750, 380016.062500, 380024.968750, 380042.656250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000");
+ values ( "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\
+ "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\
+ "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\
+ "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\
+ "0.131672, 1.724206, 3.350886, 6.646091, 13.236232");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2pad_t1_ao_enlf*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : three_state_enable_fall ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000");
+ values ( "380005.843750, 380010.875000, 380015.343750, 380024.250000, 380041.937500",\
+ "380005.937500, 380010.968750, 380015.437500, 380024.343750, 380042.031250",\
+ "380006.031250, 380011.062500, 380015.531250, 380024.437500, 380042.125000",\
+ "380006.218750, 380011.250000, 380015.718750, 380024.625000, 380042.312500",\
+ "380006.468750, 380011.500000, 380015.968750, 380024.875000, 380042.562500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000");
+ values ( "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\
+ "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\
+ "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\
+ "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\
+ "0.000000, 0.000000, 0.000000, 0.000000, 0.000000");
+ }
+
+ } /* end of arc padmux2ast_i[4]_ast2pad_t1_ao_enlf_min*/
+
+} /* end of pin ast2pad_t1_ao */
+bus ( ext_freq_is_96m_i ) {
+
+ bus_type : BUS4_type6 ;
+ direction : input ;
+
+pin("ext_freq_is_96m_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : ext_freq_is_96m_i[3];
+} /* end of pin ext_freq_is_96m_i[3] */
+
+pin("ext_freq_is_96m_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : ext_freq_is_96m_i[2];
+} /* end of pin ext_freq_is_96m_i[2] */
+
+pin("ext_freq_is_96m_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : ext_freq_is_96m_i[1];
+} /* end of pin ext_freq_is_96m_i[1] */
+
+pin("ext_freq_is_96m_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : ext_freq_is_96m_i[0];
+} /* end of pin ext_freq_is_96m_i[0] */
+} /* end of bus ext_freq_is_96m_i */
+bus ( all_clk_byp_req_i ) {
+
+ bus_type : BUS4_type6 ;
+ direction : input ;
+
+pin("all_clk_byp_req_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : all_clk_byp_req_i[3];
+} /* end of pin all_clk_byp_req_i[3] */
+
+pin("all_clk_byp_req_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : all_clk_byp_req_i[2];
+} /* end of pin all_clk_byp_req_i[2] */
+
+pin("all_clk_byp_req_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : all_clk_byp_req_i[1];
+} /* end of pin all_clk_byp_req_i[1] */
+
+pin("all_clk_byp_req_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : all_clk_byp_req_i[0];
+} /* end of pin all_clk_byp_req_i[0] */
+} /* end of bus all_clk_byp_req_i */
+bus ( all_clk_byp_ack_o ) {
+
+ bus_type : BUS4_type6 ;
+ direction : output ;
+
+pin("all_clk_byp_ack_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : all_clk_byp_ack_o[3];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\
+ "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\
+ "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\
+ "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.016716, 0.317340, 0.625771, 1.239746, 2.466601");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\
+ "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\
+ "0.034639, 0.196727, 0.379890, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\
+ "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\
+ "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\
+ "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\
+ "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\
+ "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\
+ "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.016716, 0.317340, 0.625211, 1.239292, 2.466325");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\
+ "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\
+ "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\
+ "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\
+ "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\
+ "0.034639, 0.196727, 0.378735, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_src_io_o_all_clk_byp_ack_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\
+ "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\
+ "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\
+ "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\
+ "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\
+ "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\
+ "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_src_io_o_all_clk_byp_ack_o[3]_redg_min*/
+
+} /* end of pin all_clk_byp_ack_o[3] */
+
+pin("all_clk_byp_ack_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : all_clk_byp_ack_o[2];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\
+ "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\
+ "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\
+ "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\
+ "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\
+ "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\
+ "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\
+ "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\
+ "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\
+ "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.041734, 0.154598, 0.389479, 0.764390, 1.515348");
+ }
+
+ } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\
+ "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\
+ "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\
+ "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\
+ "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\
+ "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\
+ "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\
+ "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\
+ "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\
+ "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\
+ "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\
+ "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\
+ "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\
+ "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\
+ "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\
+ "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\
+ "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\
+ "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\
+ "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.041734, 0.154598, 0.389568, 0.764056, 1.513362");
+ }
+
+ } /* end of arc clk_src_io_o_all_clk_byp_ack_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\
+ "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\
+ "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\
+ "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\
+ "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\
+ "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\
+ "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_src_io_o_all_clk_byp_ack_o[2]_redg_min*/
+
+} /* end of pin all_clk_byp_ack_o[2] */
+
+pin("all_clk_byp_ack_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : all_clk_byp_ack_o[1];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\
+ "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\
+ "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\
+ "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\
+ "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\
+ "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\
+ "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\
+ "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\
+ "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\
+ "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.041734, 0.154598, 0.389479, 0.764390, 1.515348");
+ }
+
+ } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\
+ "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\
+ "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\
+ "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\
+ "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\
+ "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\
+ "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\
+ "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\
+ "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\
+ "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\
+ "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\
+ "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\
+ "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\
+ "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\
+ "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\
+ "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\
+ "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\
+ "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\
+ "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.041734, 0.154598, 0.389568, 0.764056, 1.513362");
+ }
+
+ } /* end of arc clk_src_io_o_all_clk_byp_ack_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\
+ "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\
+ "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\
+ "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\
+ "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\
+ "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\
+ "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_src_io_o_all_clk_byp_ack_o[1]_redg_min*/
+
+} /* end of pin all_clk_byp_ack_o[1] */
+
+pin("all_clk_byp_ack_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : all_clk_byp_ack_o[0];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\
+ "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\
+ "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\
+ "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.016716, 0.317340, 0.625771, 1.239746, 2.466601");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\
+ "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\
+ "0.034639, 0.196727, 0.379890, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\
+ "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\
+ "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\
+ "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\
+ "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\
+ "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\
+ "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.016716, 0.317340, 0.625211, 1.239292, 2.466325");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\
+ "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\
+ "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\
+ "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\
+ "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\
+ "0.034639, 0.196727, 0.378735, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_src_io_o_all_clk_byp_ack_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\
+ "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\
+ "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\
+ "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\
+ "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\
+ "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\
+ "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_src_io_o_all_clk_byp_ack_o[0]_redg_min*/
+
+} /* end of pin all_clk_byp_ack_o[0] */
+} /* end of bus all_clk_byp_ack_o */
+bus ( io_clk_byp_req_i ) {
+
+ bus_type : BUS4_type6 ;
+ direction : input ;
+
+pin("io_clk_byp_req_i[3]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : io_clk_byp_req_i[3];
+} /* end of pin io_clk_byp_req_i[3] */
+
+pin("io_clk_byp_req_i[2]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : io_clk_byp_req_i[2];
+} /* end of pin io_clk_byp_req_i[2] */
+
+pin("io_clk_byp_req_i[1]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.001189 ;
+
+ /* Other user defined attributes. */
+ original_pin : io_clk_byp_req_i[1];
+} /* end of pin io_clk_byp_req_i[1] */
+
+pin("io_clk_byp_req_i[0]") {
+ direction : input ;
+ max_transition : 2.480000 ;
+ capacitance : 0.000648 ;
+
+ /* Other user defined attributes. */
+ original_pin : io_clk_byp_req_i[0];
+} /* end of pin io_clk_byp_req_i[0] */
+} /* end of bus io_clk_byp_req_i */
+bus ( io_clk_byp_ack_o ) {
+
+ bus_type : BUS4_type6 ;
+ direction : output ;
+
+pin("io_clk_byp_ack_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : io_clk_byp_ack_o[3];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\
+ "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\
+ "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\
+ "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.016716, 0.317340, 0.625771, 1.239746, 2.466601");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\
+ "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\
+ "0.034639, 0.196727, 0.379890, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\
+ "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\
+ "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\
+ "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\
+ "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\
+ "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\
+ "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.016716, 0.317340, 0.625211, 1.239292, 2.466325");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\
+ "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\
+ "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\
+ "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\
+ "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\
+ "0.034639, 0.196727, 0.378735, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_src_io_o_io_clk_byp_ack_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\
+ "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\
+ "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\
+ "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\
+ "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\
+ "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\
+ "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_src_io_o_io_clk_byp_ack_o[3]_redg_min*/
+
+} /* end of pin io_clk_byp_ack_o[3] */
+
+pin("io_clk_byp_ack_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : io_clk_byp_ack_o[2];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\
+ "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\
+ "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\
+ "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\
+ "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\
+ "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\
+ "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\
+ "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\
+ "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\
+ "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.041734, 0.154598, 0.389479, 0.764390, 1.515348");
+ }
+
+ } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\
+ "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\
+ "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\
+ "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\
+ "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\
+ "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\
+ "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\
+ "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\
+ "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\
+ "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\
+ "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\
+ "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\
+ "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\
+ "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\
+ "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\
+ "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\
+ "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\
+ "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\
+ "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.041734, 0.154598, 0.389568, 0.764056, 1.513362");
+ }
+
+ } /* end of arc clk_src_io_o_io_clk_byp_ack_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\
+ "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\
+ "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\
+ "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\
+ "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\
+ "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\
+ "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_src_io_o_io_clk_byp_ack_o[2]_redg_min*/
+
+} /* end of pin io_clk_byp_ack_o[2] */
+
+pin("io_clk_byp_ack_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : io_clk_byp_ack_o[1];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\
+ "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\
+ "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\
+ "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\
+ "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\
+ "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\
+ "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\
+ "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\
+ "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\
+ "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\
+ "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\
+ "0.041734, 0.154598, 0.389479, 0.764390, 1.515348");
+ }
+
+ } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\
+ "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\
+ "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\
+ "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\
+ "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\
+ "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\
+ "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\
+ "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\
+ "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\
+ "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\
+ "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\
+ "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\
+ "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\
+ "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\
+ "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\
+ "0.601931, 0.834236, 1.042645, 1.363437, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\
+ "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\
+ "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\
+ "0.123088, 0.289704, 0.642858, 1.251241, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\
+ "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\
+ "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\
+ "0.607343, 0.718683, 0.852150, 1.057410, 1.467133");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\
+ "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\
+ "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\
+ "0.041734, 0.154598, 0.389568, 0.764056, 1.513362");
+ }
+
+ } /* end of arc clk_src_io_o_io_clk_byp_ack_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\
+ "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\
+ "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\
+ "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\
+ "0.601899, 0.834203, 1.042596, 1.363402, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\
+ "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\
+ "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\
+ "0.122913, 0.289395, 0.639350, 1.248196, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\
+ "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\
+ "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\
+ "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\
+ "0.607308, 0.718634, 0.852099, 1.057372, 1.467127");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177");
+ values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\
+ "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\
+ "0.041668, 0.154530, 0.388178, 0.761934, 1.511090");
+ }
+
+ } /* end of arc clk_src_io_o_io_clk_byp_ack_o[1]_redg_min*/
+
+} /* end of pin io_clk_byp_ack_o[1] */
+
+pin("io_clk_byp_ack_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000000 ;
+
+ /* Other user defined attributes. */
+ original_pin : io_clk_byp_ack_o[0];
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\
+ "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\
+ "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\
+ "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\
+ "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\
+ "0.016716, 0.317340, 0.625771, 1.239746, 2.466601");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\
+ "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\
+ "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\
+ "0.034639, 0.196727, 0.379890, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\
+ "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\
+ "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\
+ "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\
+ "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\
+ "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\
+ "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\
+ "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\
+ "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\
+ "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\
+ "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\
+ "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\
+ "0.580400, 0.747044, 0.907773, 1.228098, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\
+ "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\
+ "0.016716, 0.317340, 0.625211, 1.239292, 2.466325");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\
+ "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\
+ "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\
+ "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\
+ "0.586485, 0.719001, 0.819955, 1.021830, 1.425575");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\
+ "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\
+ "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\
+ "0.034639, 0.196727, 0.378735, 0.748439, 1.491839");
+ }
+
+ } /* end of arc clk_src_io_o_io_clk_byp_ack_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_src_io_o" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\
+ "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\
+ "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\
+ "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\
+ "0.580173, 0.746795, 0.907585, 1.227594, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\
+ "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\
+ "0.016700, 0.316929, 0.623370, 1.236473, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\
+ "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\
+ "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\
+ "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\
+ "0.586485, 0.718955, 0.819794, 1.021516, 1.424967");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000");
+ index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713");
+ values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\
+ "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\
+ "0.033893, 0.196557, 0.377640, 0.746288, 1.484937");
+ }
+
+ } /* end of arc clk_src_io_o_io_clk_byp_ack_o[0]_redg_min*/
+
+} /* end of pin io_clk_byp_ack_o[0] */
+} /* end of bus io_clk_byp_ack_o */
+bus ( flash_bist_en_o ) {
+
+ bus_type : BUS4_type6 ;
+ direction : output ;
+
+pin("flash_bist_en_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000495 ;
+
+ /* Other user defined attributes. */
+ original_pin : flash_bist_en_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.106472, 0.270169, 0.430032, 0.749578, 1.388635",\
+ "0.190222, 0.353899, 0.513753, 0.833681, 1.473578",\
+ "0.265754, 0.429446, 0.589380, 0.909602, 1.550114",\
+ "0.318401, 0.482257, 0.642376, 0.962527, 1.602811",\
+ "0.586143, 0.750487, 0.910724, 1.230057, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\
+ "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\
+ "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\
+ "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\
+ "0.023510, 0.323927, 0.631438, 1.243501, 2.466601");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.093077, 0.204486, 0.305612, 0.507263, 0.910452",\
+ "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\
+ "0.252842, 0.364735, 0.465162, 0.665985, 1.067625",\
+ "0.308854, 0.422028, 0.522554, 0.723398, 1.125048",\
+ "0.595772, 0.721100, 0.821745, 1.023002, 1.425511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.020965, 0.197814, 0.383189, 0.749876, 1.482771",\
+ "0.021088, 0.197814, 0.383189, 0.749876, 1.485086",\
+ "0.022399, 0.197814, 0.383189, 0.749876, 1.485086",\
+ "0.024352, 0.197814, 0.383189, 0.749876, 1.485086",\
+ "0.039819, 0.200489, 0.383189, 0.750597, 1.491722");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.106274, 0.270052, 0.429845, 0.749374, 1.388420",\
+ "0.190221, 0.353898, 0.513750, 0.833679, 1.473578",\
+ "0.265727, 0.429421, 0.589372, 0.909573, 1.550030",\
+ "0.318289, 0.482010, 0.641868, 0.961850, 1.601865",\
+ "0.585943, 0.750239, 0.910537, 1.229551, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\
+ "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\
+ "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\
+ "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\
+ "0.023422, 0.323493, 0.628996, 1.240225, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.093062, 0.204485, 0.305607, 0.507203, 0.910270",\
+ "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\
+ "0.252842, 0.364735, 0.465162, 0.665949, 1.067509",\
+ "0.308854, 0.422028, 0.522554, 0.723377, 1.124981",\
+ "0.595772, 0.721051, 0.821582, 1.022687, 1.424903");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.020958, 0.196798, 0.379897, 0.747224, 1.481125",\
+ "0.021082, 0.196798, 0.379897, 0.747224, 1.481487",\
+ "0.022349, 0.196798, 0.379897, 0.747224, 1.481970",\
+ "0.024295, 0.197033, 0.379979, 0.747224, 1.481970",\
+ "0.039434, 0.200322, 0.380851, 0.748432, 1.484821");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[3]_redg_min*/
+
+} /* end of pin flash_bist_en_o[3] */
+
+pin("flash_bist_en_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000933 ;
+
+ /* Other user defined attributes. */
+ original_pin : flash_bist_en_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177");
+ values ( "0.068360, 0.193376, 0.398624, 0.718055, 1.356390",\
+ "0.155472, 0.280749, 0.486028, 0.806244, 1.446276",\
+ "0.245378, 0.375639, 0.580639, 0.900669, 1.540369",\
+ "0.309418, 0.446887, 0.651675, 0.971433, 1.610599",\
+ "0.645820, 0.841934, 1.048418, 1.367213, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177");
+ values ( "0.036908, 0.252893, 0.642777, 1.254340, 2.477274",\
+ "0.039249, 0.252893, 0.642777, 1.254340, 2.477274",\
+ "0.052853, 0.254696, 0.642777, 1.254340, 2.477473",\
+ "0.066089, 0.258077, 0.642777, 1.254340, 2.478527",\
+ "0.148778, 0.302748, 0.652641, 1.258483, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177");
+ values ( "0.095441, 0.187812, 0.320023, 0.524480, 0.932830",\
+ "0.183363, 0.275751, 0.407999, 0.612464, 1.020822",\
+ "0.264739, 0.356733, 0.488814, 0.693266, 1.101639",\
+ "0.322419, 0.414777, 0.546811, 0.751146, 1.159276",\
+ "0.625473, 0.723477, 0.855712, 1.059693, 1.467001");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177");
+ values ( "0.038391, 0.160114, 0.394156, 0.767483, 1.515105",\
+ "0.038391, 0.160334, 0.395597, 0.767483, 1.515105",\
+ "0.038391, 0.160334, 0.395837, 0.768571, 1.515105",\
+ "0.039404, 0.160334, 0.395837, 0.768571, 1.515105",\
+ "0.052962, 0.163010, 0.395837, 0.768571, 1.515105");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177");
+ values ( "0.068360, 0.193375, 0.398624, 0.718048, 1.356368",\
+ "0.155472, 0.280716, 0.485750, 0.805145, 1.443459",\
+ "0.245377, 0.375636, 0.580621, 0.900655, 1.540369",\
+ "0.309416, 0.446884, 0.651665, 0.971425, 1.610599",\
+ "0.645736, 0.841900, 1.048369, 1.367178, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177");
+ values ( "0.036903, 0.252768, 0.641334, 1.253096, 2.477107",\
+ "0.039197, 0.252768, 0.641334, 1.253096, 2.477170",\
+ "0.052850, 0.254678, 0.641334, 1.253096, 2.477473",\
+ "0.066086, 0.258066, 0.641335, 1.253096, 2.478218",\
+ "0.148778, 0.302321, 0.649044, 1.255451, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177");
+ values ( "0.095441, 0.187812, 0.320023, 0.524479, 0.932827",\
+ "0.183333, 0.275707, 0.407917, 0.612369, 1.020708",\
+ "0.264498, 0.356474, 0.488538, 0.692993, 1.101375",\
+ "0.322270, 0.414621, 0.546643, 0.750947, 1.159015",\
+ "0.625416, 0.723429, 0.855662, 1.059656, 1.466994");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177");
+ values ( "0.038382, 0.159650, 0.394147, 0.766109, 1.510420",\
+ "0.038382, 0.159650, 0.394269, 0.766109, 1.510420",\
+ "0.038382, 0.159650, 0.394269, 0.766109, 1.510848",\
+ "0.039368, 0.159819, 0.394269, 0.766109, 1.510848",\
+ "0.052940, 0.162923, 0.394414, 0.766109, 1.510848");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.036908, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.389662, 0.307033, 0.231889, 0.198170, 0.165471",\
+ "0.404008, 0.321379, 0.246234, 0.212515, 0.179817",\
+ "0.484046, 0.401418, 0.326273, 0.292554, 0.259856",\
+ "0.581919, 0.499290, 0.424146, 0.390427, 0.357729",\
+ "1.023710, 0.941089, 0.865969, 0.832267, 0.799656");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.038391, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.456800, 0.480507, 0.558316, 0.625895, 1.056719",\
+ "0.470804, 0.494511, 0.572320, 0.639899, 1.070723",\
+ "0.534795, 0.558499, 0.636308, 0.703887, 1.134711",\
+ "0.638862, 0.662815, 0.740625, 0.808204, 1.239027",\
+ "1.201475, 1.225922, 1.303731, 1.371310, 1.802133");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.036903, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.194420, -0.153007, -0.120290, -0.084607, 0.143547",\
+ "-0.208763, -0.167350, -0.134633, -0.098950, 0.129204",\
+ "-0.288800, -0.247387, -0.214670, -0.178991, 0.049163",\
+ "-0.387771, -0.346358, -0.313641, -0.276864, -0.048710",\
+ "-0.830571, -0.789157, -0.756441, -0.718639, -0.490440");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.038382, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.332777, -0.310549, -0.274864, -0.249589, -0.121504",\
+ "-0.346777, -0.324549, -0.288864, -0.263590, -0.135504",\
+ "-0.410769, -0.388544, -0.352859, -0.327585, -0.199499",\
+ "-0.515085, -0.492611, -0.456925, -0.431651, -0.303566",\
+ "-1.078191, -1.055218, -1.019535, -0.994261, -0.866175");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_hldr*/
+
+} /* end of pin flash_bist_en_o[2] */
+
+pin("flash_bist_en_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000982 ;
+
+ /* Other user defined attributes. */
+ original_pin : flash_bist_en_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177");
+ values ( "0.068874, 0.193784, 0.398930, 0.718257, 1.356391",\
+ "0.155991, 0.281157, 0.486334, 0.806447, 1.446276",\
+ "0.245977, 0.376046, 0.580944, 0.900871, 1.540369",\
+ "0.310114, 0.447294, 0.651980, 0.971635, 1.610599",\
+ "0.647142, 0.842344, 1.048726, 1.367414, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177");
+ values ( "0.037694, 0.253668, 0.643358, 1.254727, 2.477274",\
+ "0.040003, 0.253668, 0.643358, 1.254727, 2.477274",\
+ "0.053519, 0.255465, 0.643358, 1.254727, 2.477474",\
+ "0.066746, 0.258839, 0.643358, 1.254727, 2.478527",\
+ "0.149647, 0.303443, 0.653162, 1.258869, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177");
+ values ( "0.095870, 0.188047, 0.320193, 0.524583, 0.932804",\
+ "0.183791, 0.275986, 0.408168, 0.612567, 1.020795",\
+ "0.265166, 0.356968, 0.488983, 0.693368, 1.101612",\
+ "0.322850, 0.415012, 0.546981, 0.751248, 1.159250",\
+ "0.625969, 0.723713, 0.855882, 1.059795, 1.466974");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177");
+ values ( "0.038860, 0.160530, 0.394456, 0.767671, 1.515056",\
+ "0.038860, 0.160753, 0.395899, 0.767671, 1.515056",\
+ "0.038860, 0.160753, 0.396141, 0.768758, 1.515056",\
+ "0.039865, 0.160753, 0.396141, 0.768758, 1.515056",\
+ "0.053336, 0.163423, 0.396141, 0.768758, 1.515056");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177");
+ values ( "0.068873, 0.193783, 0.398930, 0.718250, 1.356368",\
+ "0.155991, 0.281124, 0.486056, 0.805347, 1.443459",\
+ "0.245976, 0.376044, 0.580926, 0.900857, 1.540369",\
+ "0.310112, 0.447291, 0.651970, 0.971627, 1.610599",\
+ "0.647058, 0.842310, 1.048677, 1.367379, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177");
+ values ( "0.037688, 0.253541, 0.641906, 1.253483, 2.477107",\
+ "0.039952, 0.253541, 0.641906, 1.253483, 2.477170",\
+ "0.053515, 0.255446, 0.641906, 1.253483, 2.477474",\
+ "0.066744, 0.258828, 0.641906, 1.253483, 2.478218",\
+ "0.149647, 0.303009, 0.649561, 1.255837, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177");
+ values ( "0.095870, 0.188047, 0.320193, 0.524582, 0.932800",\
+ "0.183761, 0.275942, 0.408087, 0.612471, 1.020681",\
+ "0.264924, 0.356709, 0.488708, 0.693095, 1.101348",\
+ "0.322701, 0.414856, 0.546813, 0.751050, 1.158988",\
+ "0.625912, 0.723664, 0.855831, 1.059758, 1.466968");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177");
+ values ( "0.038851, 0.160069, 0.394447, 0.766295, 1.510371",\
+ "0.038851, 0.160069, 0.394570, 0.766295, 1.510371",\
+ "0.038851, 0.160069, 0.394570, 0.766295, 1.510800",\
+ "0.039829, 0.160236, 0.394570, 0.766295, 1.510800",\
+ "0.053313, 0.163335, 0.394711, 0.766295, 1.510800");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.037694, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.387207, 0.304578, 0.229434, 0.195714, 0.163016",\
+ "0.401633, 0.319004, 0.243859, 0.210140, 0.177442",\
+ "0.477915, 0.395287, 0.320142, 0.286423, 0.253725",\
+ "0.569150, 0.486521, 0.411377, 0.377658, 0.344959",\
+ "0.968197, 0.885576, 0.810456, 0.776755, 0.744146");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.038860, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.458514, 0.482233, 0.560042, 0.627621, 1.058444",\
+ "0.470955, 0.494673, 0.572482, 0.640062, 1.070885",\
+ "0.535510, 0.559226, 0.637035, 0.704614, 1.135437",\
+ "0.647291, 0.671342, 0.749152, 0.816731, 1.247554",\
+ "1.199795, 1.224990, 1.302845, 1.370443, 1.801277");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.037688, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.191963, -0.150550, -0.117833, -0.082151, 0.146002",\
+ "-0.206387, -0.164973, -0.132257, -0.096575, 0.131579",\
+ "-0.282671, -0.241257, -0.208540, -0.172860, 0.055294",\
+ "-0.374978, -0.333564, -0.300848, -0.264095, -0.035941",\
+ "-0.775028, -0.733615, -0.700898, -0.663125, -0.434925");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.038851, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.334502, -0.312263, -0.276578, -0.251304, -0.123218",\
+ "-0.346939, -0.324701, -0.289015, -0.263741, -0.135656",\
+ "-0.411495, -0.389259, -0.353574, -0.328299, -0.200214",\
+ "-0.523612, -0.501040, -0.465355, -0.440080, -0.311995",\
+ "-1.077244, -1.053536, -1.017853, -0.992580, -0.864493");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_hldr*/
+
+} /* end of pin flash_bist_en_o[1] */
+
+pin("flash_bist_en_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.000495 ;
+
+ /* Other user defined attributes. */
+ original_pin : flash_bist_en_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.106472, 0.270169, 0.430032, 0.749578, 1.388635",\
+ "0.190222, 0.353899, 0.513753, 0.833681, 1.473578",\
+ "0.265754, 0.429446, 0.589380, 0.909602, 1.550114",\
+ "0.318401, 0.482257, 0.642376, 0.962527, 1.602811",\
+ "0.586143, 0.750487, 0.910724, 1.230057, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\
+ "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\
+ "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\
+ "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\
+ "0.023510, 0.323927, 0.631438, 1.243501, 2.466601");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.093077, 0.204486, 0.305612, 0.507263, 0.910452",\
+ "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\
+ "0.252842, 0.364735, 0.465162, 0.665985, 1.067625",\
+ "0.308854, 0.422028, 0.522554, 0.723398, 1.125048",\
+ "0.595772, 0.721100, 0.821745, 1.023002, 1.425511");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.020965, 0.197814, 0.383189, 0.749876, 1.482771",\
+ "0.021088, 0.197814, 0.383189, 0.749876, 1.485086",\
+ "0.022399, 0.197814, 0.383189, 0.749876, 1.485086",\
+ "0.024352, 0.197814, 0.383189, 0.749876, 1.485086",\
+ "0.039819, 0.200489, 0.383189, 0.750597, 1.491722");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.106274, 0.270052, 0.429845, 0.749374, 1.388420",\
+ "0.190221, 0.353898, 0.513750, 0.833679, 1.473578",\
+ "0.265727, 0.429421, 0.589372, 0.909573, 1.550030",\
+ "0.318289, 0.482010, 0.641868, 0.961850, 1.601865",\
+ "0.585943, 0.750239, 0.910537, 1.229551, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\
+ "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\
+ "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\
+ "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\
+ "0.023422, 0.323493, 0.628996, 1.240225, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.093062, 0.204485, 0.305607, 0.507203, 0.910270",\
+ "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\
+ "0.252842, 0.364735, 0.465162, 0.665949, 1.067509",\
+ "0.308854, 0.422028, 0.522554, 0.723377, 1.124981",\
+ "0.595772, 0.721051, 0.821582, 1.022687, 1.424903");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713");
+ values ( "0.020958, 0.196798, 0.379897, 0.747224, 1.481125",\
+ "0.021082, 0.196798, 0.379897, 0.747224, 1.481487",\
+ "0.022349, 0.196798, 0.379897, 0.747224, 1.481970",\
+ "0.024295, 0.197033, 0.379979, 0.747224, 1.481970",\
+ "0.039434, 0.200322, 0.380851, 0.748432, 1.484821");
+ }
+
+ } /* end of arc clk_ast_tlul_i_flash_bist_en_o[0]_redg_min*/
+
+} /* end of pin flash_bist_en_o[0] */
+} /* end of bus flash_bist_en_o */
+bus ( dpram_rmf_o ) {
+
+ bus_type : BUS10_type8 ;
+ direction : output ;
+
+pin("dpram_rmf_o[9]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002475 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[9];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\
+ "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\
+ "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\
+ "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\
+ "0.579442, 0.791721, 0.966837, 1.286790, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025782, 0.301558, 0.634384, 1.250443, 2.482564",\
+ "0.030125, 0.302556, 0.636324, 1.250443, 2.482564",\
+ "0.042888, 0.304795, 0.636360, 1.250443, 2.482564",\
+ "0.054816, 0.308050, 0.636463, 1.250443, 2.482564",\
+ "0.130787, 0.346172, 0.642713, 1.252991, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\
+ "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\
+ "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\
+ "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\
+ "0.587713, 0.702042, 0.813273, 1.016348, 1.422499");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025687, 0.188435, 0.388543, 0.760465, 1.504307",\
+ "0.025687, 0.188583, 0.389046, 0.760465, 1.504307",\
+ "0.026721, 0.188583, 0.389046, 0.760465, 1.504307",\
+ "0.028743, 0.188583, 0.389046, 0.760465, 1.504307",\
+ "0.047139, 0.192514, 0.389046, 0.760465, 1.504587");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\
+ "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\
+ "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\
+ "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\
+ "0.579442, 0.791721, 0.966837, 1.286790, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025782, 0.301558, 0.634384, 1.249210, 2.473548",\
+ "0.030125, 0.302556, 0.636324, 1.249210, 2.473548",\
+ "0.042888, 0.304795, 0.636360, 1.249285, 2.473548",\
+ "0.054816, 0.308050, 0.636463, 1.250030, 2.473548",\
+ "0.130787, 0.346172, 0.642713, 1.252991, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\
+ "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\
+ "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\
+ "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\
+ "0.587713, 0.702042, 0.813273, 1.016348, 1.422499");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\
+ "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\
+ "0.026721, 0.187631, 0.387035, 0.758233, 1.500630",\
+ "0.028743, 0.188240, 0.387493, 0.759136, 1.502422",\
+ "0.047139, 0.192514, 0.387566, 0.759907, 1.504587");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216765, 0.170836, 0.140637, 0.129293, 0.142978",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251111, 0.175790, 0.107631, 0.084664, 0.147578",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148693, -0.106276, -0.071789, -0.032365, 0.273682",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164267, -0.098352, -0.040693, 0.001268, 0.221876",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_hldr*/
+
+} /* end of pin dpram_rmf_o[9] */
+
+pin("dpram_rmf_o[8]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002026 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[8];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\
+ "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\
+ "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\
+ "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\
+ "0.575742, 0.790814, 0.966163, 1.286341, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\
+ "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\
+ "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\
+ "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\
+ "0.129154, 0.344706, 0.641428, 1.252134, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\
+ "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\
+ "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\
+ "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\
+ "0.586152, 0.701486, 0.812865, 1.016083, 1.422518");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\
+ "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.046348, 0.191554, 0.388300, 0.759979, 1.504623");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\
+ "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\
+ "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\
+ "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\
+ "0.575742, 0.790814, 0.966163, 1.286341, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\
+ "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\
+ "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\
+ "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\
+ "0.129154, 0.344706, 0.641428, 1.252134, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\
+ "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\
+ "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\
+ "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\
+ "0.586152, 0.701486, 0.812865, 1.016083, 1.422518");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\
+ "0.046348, 0.191554, 0.386818, 0.759420, 1.504623");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_hldr*/
+
+} /* end of pin dpram_rmf_o[8] */
+
+pin("dpram_rmf_o[7]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002475 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[7];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\
+ "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\
+ "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\
+ "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\
+ "0.579442, 0.791721, 0.966837, 1.286790, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025782, 0.301558, 0.634384, 1.250443, 2.482564",\
+ "0.030125, 0.302556, 0.636324, 1.250443, 2.482564",\
+ "0.042888, 0.304795, 0.636360, 1.250443, 2.482564",\
+ "0.054816, 0.308050, 0.636463, 1.250443, 2.482564",\
+ "0.130787, 0.346172, 0.642713, 1.252991, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\
+ "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\
+ "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\
+ "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\
+ "0.587713, 0.702042, 0.813273, 1.016348, 1.422499");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025687, 0.188435, 0.388543, 0.760465, 1.504307",\
+ "0.025687, 0.188583, 0.389046, 0.760465, 1.504307",\
+ "0.026721, 0.188583, 0.389046, 0.760465, 1.504307",\
+ "0.028743, 0.188583, 0.389046, 0.760465, 1.504307",\
+ "0.047139, 0.192514, 0.389046, 0.760465, 1.504587");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\
+ "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\
+ "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\
+ "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\
+ "0.579442, 0.791721, 0.966837, 1.286790, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025782, 0.301558, 0.634384, 1.249210, 2.473548",\
+ "0.030125, 0.302556, 0.636324, 1.249210, 2.473548",\
+ "0.042888, 0.304795, 0.636360, 1.249285, 2.473548",\
+ "0.054816, 0.308050, 0.636463, 1.250030, 2.473548",\
+ "0.130787, 0.346172, 0.642713, 1.252991, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\
+ "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\
+ "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\
+ "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\
+ "0.587713, 0.702042, 0.813273, 1.016348, 1.422499");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\
+ "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\
+ "0.026721, 0.187631, 0.387035, 0.758233, 1.500630",\
+ "0.028743, 0.188240, 0.387493, 0.759136, 1.502422",\
+ "0.047139, 0.192514, 0.387566, 0.759907, 1.504587");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216765, 0.170836, 0.140637, 0.129293, 0.142978",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251111, 0.175790, 0.107631, 0.084664, 0.147578",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148693, -0.106276, -0.071789, -0.032365, 0.273682",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164267, -0.098352, -0.040693, 0.001268, 0.221876",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_hldr*/
+
+} /* end of pin dpram_rmf_o[7] */
+
+pin("dpram_rmf_o[6]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002493 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[6];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011");
+ values ( "0.049484, 0.202188, 0.377310, 0.699821, 1.344843",\
+ "0.135872, 0.289362, 0.464414, 0.786535, 1.430777",\
+ "0.219397, 0.377489, 0.552369, 0.874157, 1.517732",\
+ "0.277634, 0.441882, 0.616484, 0.938070, 1.581241",\
+ "0.579590, 0.791757, 0.966864, 1.286808, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011");
+ values ( "0.025847, 0.301627, 0.634436, 1.250478, 2.482563",\
+ "0.030184, 0.302625, 0.636376, 1.250478, 2.482563",\
+ "0.042939, 0.304864, 0.636412, 1.250478, 2.482563",\
+ "0.054868, 0.308118, 0.636515, 1.250478, 2.482563",\
+ "0.130853, 0.346231, 0.642764, 1.253025, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011");
+ values ( "0.068955, 0.173526, 0.284810, 0.488770, 0.896690",\
+ "0.156363, 0.260844, 0.372091, 0.576075, 0.984043",\
+ "0.236740, 0.341176, 0.452118, 0.656103, 1.064075",\
+ "0.293480, 0.398725, 0.509660, 0.713348, 1.120723",\
+ "0.587780, 0.702066, 0.813291, 1.016361, 1.422500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011");
+ values ( "0.025734, 0.188477, 0.388576, 0.760487, 1.504309",\
+ "0.025734, 0.188626, 0.389079, 0.760487, 1.504309",\
+ "0.026766, 0.188626, 0.389079, 0.760487, 1.504309",\
+ "0.028786, 0.188626, 0.389079, 0.760487, 1.504309",\
+ "0.047173, 0.192555, 0.389079, 0.760487, 1.504589");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011");
+ values ( "0.049484, 0.202188, 0.377310, 0.699821, 1.344843",\
+ "0.135872, 0.289362, 0.464414, 0.786535, 1.430777",\
+ "0.219397, 0.377489, 0.552369, 0.874157, 1.517732",\
+ "0.277634, 0.441882, 0.616484, 0.938070, 1.581241",\
+ "0.579590, 0.791757, 0.966864, 1.286808, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011");
+ values ( "0.025847, 0.301627, 0.634436, 1.249244, 2.473548",\
+ "0.030184, 0.302625, 0.636376, 1.249244, 2.473548",\
+ "0.042939, 0.304864, 0.636412, 1.249320, 2.473548",\
+ "0.054868, 0.308118, 0.636515, 1.250065, 2.473548",\
+ "0.130853, 0.346231, 0.642764, 1.253025, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011");
+ values ( "0.068955, 0.173526, 0.284810, 0.488770, 0.896690",\
+ "0.156363, 0.260844, 0.372091, 0.576075, 0.984043",\
+ "0.236740, 0.341176, 0.452118, 0.656103, 1.064075",\
+ "0.293480, 0.398725, 0.509660, 0.713348, 1.120723",\
+ "0.587780, 0.702066, 0.813291, 1.016361, 1.422500");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011");
+ values ( "0.025734, 0.187674, 0.387068, 0.758256, 1.500632",\
+ "0.025734, 0.187674, 0.387068, 0.758256, 1.500632",\
+ "0.026766, 0.187674, 0.387068, 0.758256, 1.500632",\
+ "0.028786, 0.188283, 0.387526, 0.759158, 1.502423",\
+ "0.047173, 0.192555, 0.387599, 0.759929, 1.504589");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025847, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216796, 0.170867, 0.140667, 0.129323, 0.143008",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025734, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251133, 0.175811, 0.107652, 0.084685, 0.147599",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025847, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148723, -0.106306, -0.071819, -0.032395, 0.273652",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025734, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164288, -0.098373, -0.040714, 0.001247, 0.221854",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_hldr*/
+
+} /* end of pin dpram_rmf_o[6] */
+
+pin("dpram_rmf_o[5]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002464 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[5];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011");
+ values ( "0.049406, 0.202130, 0.377266, 0.699792, 1.344843",\
+ "0.135790, 0.289304, 0.464371, 0.786506, 1.430777",\
+ "0.219296, 0.377431, 0.552325, 0.874128, 1.517732",\
+ "0.277514, 0.441824, 0.616441, 0.938041, 1.581241",\
+ "0.579353, 0.791699, 0.966821, 1.286780, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011");
+ values ( "0.025743, 0.301517, 0.634353, 1.250423, 2.482564",\
+ "0.030090, 0.302515, 0.636293, 1.250423, 2.482564",\
+ "0.042857, 0.304754, 0.636329, 1.250423, 2.482564",\
+ "0.054785, 0.308010, 0.636433, 1.250423, 2.482564",\
+ "0.130748, 0.346137, 0.642682, 1.252970, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011");
+ values ( "0.068893, 0.173494, 0.284787, 0.488756, 0.896694",\
+ "0.156301, 0.260812, 0.372068, 0.576061, 0.984048",\
+ "0.236678, 0.341144, 0.452094, 0.656090, 1.064079",\
+ "0.293415, 0.398693, 0.509637, 0.713334, 1.120727",\
+ "0.587689, 0.702034, 0.813268, 1.016347, 1.422504");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011");
+ values ( "0.025670, 0.188420, 0.388534, 0.760462, 1.504317",\
+ "0.025670, 0.188568, 0.389037, 0.760462, 1.504317",\
+ "0.026706, 0.188568, 0.389037, 0.760462, 1.504317",\
+ "0.028728, 0.188568, 0.389037, 0.760462, 1.504317",\
+ "0.047127, 0.192499, 0.389037, 0.760462, 1.504597");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011");
+ values ( "0.049406, 0.202130, 0.377266, 0.699792, 1.344843",\
+ "0.135790, 0.289304, 0.464371, 0.786506, 1.430777",\
+ "0.219296, 0.377431, 0.552325, 0.874128, 1.517732",\
+ "0.277514, 0.441824, 0.616441, 0.938041, 1.581241",\
+ "0.579353, 0.791699, 0.966821, 1.286780, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011");
+ values ( "0.025743, 0.301517, 0.634353, 1.249189, 2.473548",\
+ "0.030090, 0.302515, 0.636293, 1.249189, 2.473548",\
+ "0.042857, 0.304754, 0.636329, 1.249264, 2.473548",\
+ "0.054785, 0.308010, 0.636433, 1.250010, 2.473548",\
+ "0.130748, 0.346137, 0.642682, 1.252970, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011");
+ values ( "0.068893, 0.173494, 0.284787, 0.488756, 0.896694",\
+ "0.156301, 0.260812, 0.372068, 0.576061, 0.984048",\
+ "0.236678, 0.341144, 0.452094, 0.656090, 1.064079",\
+ "0.293415, 0.398693, 0.509637, 0.713334, 1.120727",\
+ "0.587689, 0.702034, 0.813268, 1.016347, 1.422504");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011");
+ values ( "0.025670, 0.187616, 0.387026, 0.758231, 1.500640",\
+ "0.025670, 0.187616, 0.387026, 0.758231, 1.500640",\
+ "0.026706, 0.187616, 0.387026, 0.758231, 1.500640",\
+ "0.028728, 0.188225, 0.387484, 0.759133, 1.502431",\
+ "0.047127, 0.192499, 0.387557, 0.759904, 1.504597");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025743, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216747, 0.170818, 0.140619, 0.129275, 0.142960",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025670, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251104, 0.175782, 0.107623, 0.084656, 0.147570",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025743, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148675, -0.106258, -0.071771, -0.032347, 0.273700",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025670, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164259, -0.098344, -0.040686, 0.001276, 0.221883",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_hldr*/
+
+} /* end of pin dpram_rmf_o[5] */
+
+pin("dpram_rmf_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002015 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[4];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\
+ "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\
+ "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\
+ "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\
+ "0.575653, 0.790792, 0.966147, 1.286330, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\
+ "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\
+ "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\
+ "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\
+ "0.129115, 0.344671, 0.641397, 1.252114, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\
+ "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\
+ "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\
+ "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\
+ "0.586128, 0.701477, 0.812860, 1.016081, 1.422524");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\
+ "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.046336, 0.191539, 0.388291, 0.759976, 1.504633");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\
+ "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\
+ "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\
+ "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\
+ "0.575653, 0.790792, 0.966147, 1.286330, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\
+ "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\
+ "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\
+ "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\
+ "0.129115, 0.344671, 0.641397, 1.252114, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\
+ "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\
+ "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\
+ "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\
+ "0.586128, 0.701477, 0.812860, 1.016081, 1.422524");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\
+ "0.046336, 0.191539, 0.386809, 0.759417, 1.504633");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_hldr*/
+
+} /* end of pin dpram_rmf_o[4] */
+
+pin("dpram_rmf_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002005 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\
+ "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\
+ "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\
+ "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\
+ "0.575569, 0.790772, 0.966132, 1.286320, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\
+ "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\
+ "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\
+ "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\
+ "0.129078, 0.344637, 0.641368, 1.252094, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\
+ "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\
+ "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\
+ "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\
+ "0.586096, 0.701465, 0.812852, 1.016076, 1.422525");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\
+ "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.046319, 0.191519, 0.388276, 0.759966, 1.504636");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\
+ "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\
+ "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\
+ "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\
+ "0.575569, 0.790772, 0.966132, 1.286320, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\
+ "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\
+ "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\
+ "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\
+ "0.129078, 0.344637, 0.641368, 1.252094, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\
+ "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\
+ "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\
+ "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\
+ "0.586096, 0.701465, 0.812852, 1.016076, 1.422525");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\
+ "0.046319, 0.191519, 0.386794, 0.759408, 1.504636");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_hldr*/
+
+} /* end of pin dpram_rmf_o[3] */
+
+pin("dpram_rmf_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002015 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\
+ "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\
+ "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\
+ "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\
+ "0.575653, 0.790792, 0.966147, 1.286330, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\
+ "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\
+ "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\
+ "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\
+ "0.129115, 0.344671, 0.641397, 1.252114, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\
+ "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\
+ "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\
+ "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\
+ "0.586128, 0.701477, 0.812860, 1.016081, 1.422524");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\
+ "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.046336, 0.191539, 0.388291, 0.759976, 1.504633");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\
+ "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\
+ "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\
+ "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\
+ "0.575653, 0.790792, 0.966147, 1.286330, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\
+ "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\
+ "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\
+ "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\
+ "0.129115, 0.344671, 0.641397, 1.252114, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\
+ "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\
+ "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\
+ "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\
+ "0.586128, 0.701477, 0.812860, 1.016081, 1.422524");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\
+ "0.046336, 0.191539, 0.386809, 0.759417, 1.504633");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_hldr*/
+
+} /* end of pin dpram_rmf_o[2] */
+
+pin("dpram_rmf_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003002 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\
+ "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\
+ "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\
+ "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\
+ "0.583788, 0.792786, 0.967628, 1.287318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.027696, 0.303573, 0.635907, 1.251459, 2.482564",\
+ "0.031840, 0.304583, 0.637840, 1.251459, 2.482564",\
+ "0.044392, 0.306804, 0.637876, 1.251459, 2.482564",\
+ "0.056346, 0.310032, 0.637981, 1.251459, 2.482564",\
+ "0.132705, 0.347895, 0.644222, 1.253997, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\
+ "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\
+ "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\
+ "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\
+ "0.589569, 0.702704, 0.813760, 1.016668, 1.422484");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.026989, 0.189618, 0.389436, 0.761051, 1.504280",\
+ "0.026989, 0.189769, 0.389937, 0.761051, 1.504280",\
+ "0.027967, 0.189769, 0.389937, 0.761051, 1.504280",\
+ "0.029933, 0.189769, 0.389937, 0.761051, 1.504280",\
+ "0.048080, 0.193656, 0.389937, 0.761051, 1.504560");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\
+ "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\
+ "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\
+ "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\
+ "0.583788, 0.792786, 0.967628, 1.287318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.027696, 0.303573, 0.635907, 1.250220, 2.473548",\
+ "0.031840, 0.304583, 0.637840, 1.250220, 2.473548",\
+ "0.044392, 0.306804, 0.637876, 1.250296, 2.473548",\
+ "0.056346, 0.310032, 0.637981, 1.251042, 2.473548",\
+ "0.132705, 0.347895, 0.644222, 1.253997, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\
+ "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\
+ "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\
+ "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\
+ "0.589569, 0.702704, 0.813760, 1.016668, 1.422484");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\
+ "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\
+ "0.027967, 0.188809, 0.387926, 0.758818, 1.500603",\
+ "0.029933, 0.189417, 0.388385, 0.759721, 1.502395",\
+ "0.048080, 0.193656, 0.388460, 0.760493, 1.504560");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.217652, 0.171723, 0.141523, 0.130179, 0.143864",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251704, 0.176383, 0.108224, 0.085257, 0.148171",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.149579, -0.107162, -0.072675, -0.033251, 0.272796",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164860, -0.098945, -0.041286, 0.000675, 0.221283",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_hldr*/
+
+} /* end of pin dpram_rmf_o[1] */
+
+pin("dpram_rmf_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002026 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rmf_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\
+ "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\
+ "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\
+ "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\
+ "0.575742, 0.790814, 0.966163, 1.286341, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\
+ "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\
+ "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\
+ "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\
+ "0.129154, 0.344706, 0.641428, 1.252134, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\
+ "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\
+ "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\
+ "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\
+ "0.586152, 0.701486, 0.812865, 1.016083, 1.422518");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\
+ "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.046348, 0.191554, 0.388300, 0.759979, 1.504623");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\
+ "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\
+ "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\
+ "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\
+ "0.575742, 0.790814, 0.966163, 1.286341, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\
+ "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\
+ "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\
+ "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\
+ "0.129154, 0.344706, 0.641428, 1.252134, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\
+ "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\
+ "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\
+ "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\
+ "0.586152, 0.701486, 0.812865, 1.016083, 1.422518");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\
+ "0.046348, 0.191554, 0.386818, 0.759420, 1.504623");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_hldr*/
+
+} /* end of pin dpram_rmf_o[0] */
+} /* end of bus dpram_rmf_o */
+bus ( dpram_rml_o ) {
+
+ bus_type : BUS10_type8 ;
+ direction : output ;
+
+pin("dpram_rml_o[9]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003142 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[9];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011");
+ values ( "0.051240, 0.203496, 0.378292, 0.700476, 1.344843",\
+ "0.137724, 0.290671, 0.465395, 0.787189, 1.430777",\
+ "0.221682, 0.378796, 0.553349, 0.874810, 1.517732",\
+ "0.280355, 0.443186, 0.617463, 0.938722, 1.581241",\
+ "0.584942, 0.793069, 0.967839, 1.287458, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011");
+ values ( "0.028205, 0.304109, 0.636312, 1.251729, 2.482563",\
+ "0.032295, 0.305121, 0.638243, 1.251729, 2.482563",\
+ "0.044791, 0.307337, 0.638279, 1.251729, 2.482563",\
+ "0.056753, 0.310558, 0.638384, 1.251729, 2.482563",\
+ "0.133215, 0.348353, 0.644623, 1.254264, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011");
+ values ( "0.070508, 0.174340, 0.285412, 0.489165, 0.896671",\
+ "0.157911, 0.261657, 0.372693, 0.576470, 0.984024",\
+ "0.238313, 0.341986, 0.452720, 0.656498, 1.064056",\
+ "0.295115, 0.399536, 0.510261, 0.713742, 1.120703",\
+ "0.590063, 0.702880, 0.813890, 1.016754, 1.422480");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011");
+ values ( "0.027336, 0.189933, 0.389674, 0.761207, 1.504274",\
+ "0.027336, 0.190085, 0.390175, 0.761207, 1.504274",\
+ "0.028299, 0.190085, 0.390175, 0.761207, 1.504274",\
+ "0.030250, 0.190085, 0.390175, 0.761207, 1.504274",\
+ "0.048330, 0.193960, 0.390175, 0.761207, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011");
+ values ( "0.051240, 0.203496, 0.378292, 0.700476, 1.344843",\
+ "0.137724, 0.290671, 0.465395, 0.787189, 1.430777",\
+ "0.221682, 0.378796, 0.553349, 0.874810, 1.517732",\
+ "0.280355, 0.443186, 0.617463, 0.938722, 1.581241",\
+ "0.584942, 0.793069, 0.967839, 1.287458, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011");
+ values ( "0.028205, 0.304109, 0.636312, 1.250489, 2.473548",\
+ "0.032295, 0.305121, 0.638243, 1.250489, 2.473548",\
+ "0.044791, 0.307337, 0.638279, 1.250564, 2.473548",\
+ "0.056753, 0.310558, 0.638384, 1.251310, 2.473548",\
+ "0.133215, 0.348353, 0.644623, 1.254264, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011");
+ values ( "0.070508, 0.174340, 0.285412, 0.489165, 0.896671",\
+ "0.157911, 0.261657, 0.372693, 0.576470, 0.984024",\
+ "0.238313, 0.341986, 0.452720, 0.656498, 1.064056",\
+ "0.295115, 0.399536, 0.510261, 0.713742, 1.120703",\
+ "0.590063, 0.702880, 0.813890, 1.016754, 1.422480");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011");
+ values ( "0.027336, 0.189123, 0.388163, 0.758974, 1.500597",\
+ "0.027336, 0.189123, 0.388163, 0.758974, 1.500597",\
+ "0.028299, 0.189123, 0.388163, 0.758974, 1.500597",\
+ "0.030250, 0.189730, 0.388622, 0.759878, 1.502388",\
+ "0.048330, 0.193960, 0.388698, 0.760650, 1.504554");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028205, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.217887, 0.171958, 0.141759, 0.130415, 0.144100",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027336, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251862, 0.176541, 0.108382, 0.085415, 0.148328",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028205, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.149814, -0.107397, -0.072910, -0.033487, 0.272560",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027336, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.165018, -0.099103, -0.041444, 0.000517, 0.221125",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_hldr*/
+
+} /* end of pin dpram_rml_o[9] */
+
+pin("dpram_rml_o[8]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002583 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[8];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011");
+ values ( "0.049728, 0.202370, 0.377446, 0.699912, 1.344843",\
+ "0.136129, 0.289544, 0.464550, 0.786626, 1.430777",\
+ "0.219715, 0.377671, 0.552505, 0.874247, 1.517732",\
+ "0.278013, 0.442063, 0.616620, 0.938160, 1.581241",\
+ "0.580334, 0.791940, 0.967000, 1.286899, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011");
+ values ( "0.026175, 0.301972, 0.634697, 1.250652, 2.482564",\
+ "0.030477, 0.302972, 0.636635, 1.250652, 2.482564",\
+ "0.043197, 0.305208, 0.636672, 1.250652, 2.482564",\
+ "0.055131, 0.308457, 0.636775, 1.250652, 2.482564",\
+ "0.131181, 0.346526, 0.643023, 1.253198, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011");
+ values ( "0.069162, 0.173635, 0.284889, 0.488820, 0.896683",\
+ "0.156569, 0.260953, 0.372170, 0.576125, 0.984036",\
+ "0.236950, 0.341284, 0.452197, 0.656154, 1.064068",\
+ "0.293698, 0.398833, 0.509739, 0.713398, 1.120715",\
+ "0.588084, 0.702174, 0.813370, 1.016411, 1.422492");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011");
+ values ( "0.025948, 0.188671, 0.388720, 0.760579, 1.504295",\
+ "0.025948, 0.188820, 0.389223, 0.760579, 1.504295",\
+ "0.026971, 0.188820, 0.389223, 0.760579, 1.504295",\
+ "0.028981, 0.188820, 0.389223, 0.760579, 1.504295",\
+ "0.047327, 0.192742, 0.389223, 0.760579, 1.504576");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011");
+ values ( "0.049728, 0.202370, 0.377446, 0.699912, 1.344843",\
+ "0.136129, 0.289544, 0.464550, 0.786626, 1.430777",\
+ "0.219715, 0.377671, 0.552505, 0.874247, 1.517732",\
+ "0.278013, 0.442063, 0.616620, 0.938160, 1.581241",\
+ "0.580334, 0.791940, 0.967000, 1.286899, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011");
+ values ( "0.026175, 0.301972, 0.634697, 1.249417, 2.473548",\
+ "0.030477, 0.302972, 0.636635, 1.249417, 2.473548",\
+ "0.043197, 0.305208, 0.636672, 1.249493, 2.473548",\
+ "0.055131, 0.308457, 0.636775, 1.250238, 2.473548",\
+ "0.131181, 0.346526, 0.643023, 1.253198, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011");
+ values ( "0.069162, 0.173635, 0.284889, 0.488820, 0.896683",\
+ "0.156569, 0.260953, 0.372170, 0.576125, 0.984036",\
+ "0.236950, 0.341284, 0.452197, 0.656154, 1.064068",\
+ "0.293698, 0.398833, 0.509739, 0.713398, 1.120715",\
+ "0.588084, 0.702174, 0.813370, 1.016411, 1.422492");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011");
+ values ( "0.025948, 0.187867, 0.387212, 0.758347, 1.500618",\
+ "0.025948, 0.187867, 0.387212, 0.758347, 1.500618",\
+ "0.026971, 0.187867, 0.387212, 0.758347, 1.500618",\
+ "0.028981, 0.188476, 0.387670, 0.759250, 1.502410",\
+ "0.047327, 0.192742, 0.387744, 0.760021, 1.504576");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026175, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216947, 0.171018, 0.140819, 0.129475, 0.143160",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025948, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251230, 0.175909, 0.107750, 0.084782, 0.147696",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026175, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148875, -0.106458, -0.071971, -0.032547, 0.273500",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025948, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164386, -0.098471, -0.040812, 0.001149, 0.221757",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_hldr*/
+
+} /* end of pin dpram_rml_o[8] */
+
+pin("dpram_rml_o[7]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002594 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[7];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011");
+ values ( "0.049757, 0.202391, 0.377463, 0.699923, 1.344843",\
+ "0.136160, 0.289566, 0.464567, 0.786637, 1.430777",\
+ "0.219753, 0.377693, 0.552521, 0.874258, 1.517732",\
+ "0.278058, 0.442085, 0.616637, 0.938171, 1.581241",\
+ "0.580424, 0.791962, 0.967016, 1.286910, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011");
+ values ( "0.026215, 0.302013, 0.634728, 1.250673, 2.482563",\
+ "0.030513, 0.303014, 0.636667, 1.250673, 2.482563",\
+ "0.043228, 0.305249, 0.636703, 1.250673, 2.482563",\
+ "0.055162, 0.308498, 0.636806, 1.250673, 2.482563",\
+ "0.131221, 0.346562, 0.643054, 1.253218, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011");
+ values ( "0.069192, 0.173650, 0.284901, 0.488829, 0.896685",\
+ "0.156600, 0.260968, 0.372182, 0.576134, 0.984038",\
+ "0.236980, 0.341300, 0.452209, 0.656163, 1.064070",\
+ "0.293730, 0.398849, 0.509751, 0.713407, 1.120717",\
+ "0.588129, 0.702190, 0.813382, 1.016419, 1.422494");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011");
+ values ( "0.025979, 0.188700, 0.388743, 0.760595, 1.504299",\
+ "0.025979, 0.188849, 0.389245, 0.760595, 1.504299",\
+ "0.027001, 0.188849, 0.389245, 0.760595, 1.504299",\
+ "0.029010, 0.188849, 0.389245, 0.760595, 1.504299",\
+ "0.047350, 0.192770, 0.389245, 0.760595, 1.504579");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011");
+ values ( "0.049757, 0.202391, 0.377463, 0.699923, 1.344843",\
+ "0.136160, 0.289566, 0.464567, 0.786637, 1.430777",\
+ "0.219753, 0.377693, 0.552521, 0.874258, 1.517732",\
+ "0.278058, 0.442085, 0.616637, 0.938171, 1.581241",\
+ "0.580424, 0.791962, 0.967016, 1.286910, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011");
+ values ( "0.026215, 0.302013, 0.634728, 1.249438, 2.473548",\
+ "0.030513, 0.303014, 0.636667, 1.249438, 2.473548",\
+ "0.043228, 0.305249, 0.636703, 1.249514, 2.473548",\
+ "0.055162, 0.308498, 0.636806, 1.250259, 2.473548",\
+ "0.131221, 0.346562, 0.643054, 1.253218, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011");
+ values ( "0.069192, 0.173650, 0.284901, 0.488829, 0.896685",\
+ "0.156600, 0.260968, 0.372182, 0.576134, 0.984038",\
+ "0.236980, 0.341300, 0.452209, 0.656163, 1.064070",\
+ "0.293730, 0.398849, 0.509751, 0.713407, 1.120717",\
+ "0.588129, 0.702190, 0.813382, 1.016419, 1.422494");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011");
+ values ( "0.025979, 0.187895, 0.387234, 0.758363, 1.500622",\
+ "0.025979, 0.187895, 0.387234, 0.758363, 1.500622",\
+ "0.027001, 0.187895, 0.387234, 0.758363, 1.500622",\
+ "0.029010, 0.188504, 0.387692, 0.759266, 1.502414",\
+ "0.047350, 0.192770, 0.387766, 0.760037, 1.504579");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026215, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216966, 0.171037, 0.140837, 0.129493, 0.143178",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025979, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251244, 0.175923, 0.107764, 0.084797, 0.147711",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026215, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148893, -0.106476, -0.071989, -0.032565, 0.273482",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025979, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164400, -0.098485, -0.040826, 0.001135, 0.221743",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_hldr*/
+
+} /* end of pin dpram_rml_o[7] */
+
+pin("dpram_rml_o[6]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002460 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[6];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011");
+ values ( "0.049394, 0.202121, 0.377259, 0.699787, 1.344843",\
+ "0.135777, 0.289295, 0.464364, 0.786501, 1.430777",\
+ "0.219280, 0.377422, 0.552318, 0.874123, 1.517732",\
+ "0.277495, 0.441815, 0.616434, 0.938036, 1.581241",\
+ "0.579315, 0.791690, 0.966814, 1.286775, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011");
+ values ( "0.025727, 0.301499, 0.634339, 1.250414, 2.482564",\
+ "0.030075, 0.302497, 0.636280, 1.250414, 2.482564",\
+ "0.042844, 0.304737, 0.636316, 1.250414, 2.482564",\
+ "0.054772, 0.307992, 0.636419, 1.250414, 2.482564",\
+ "0.130732, 0.346122, 0.642669, 1.252962, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011");
+ values ( "0.068872, 0.173483, 0.284777, 0.488748, 0.896689",\
+ "0.156281, 0.260801, 0.372058, 0.576053, 0.984043",\
+ "0.236656, 0.341133, 0.452085, 0.656082, 1.064075",\
+ "0.293393, 0.398682, 0.509628, 0.713326, 1.120722",\
+ "0.587658, 0.702023, 0.813259, 1.016339, 1.422499");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011");
+ values ( "0.025649, 0.188400, 0.388517, 0.760448, 1.504308",\
+ "0.025649, 0.188548, 0.389020, 0.760448, 1.504308",\
+ "0.026685, 0.188548, 0.389020, 0.760448, 1.504308",\
+ "0.028708, 0.188548, 0.389020, 0.760448, 1.504308",\
+ "0.047111, 0.192480, 0.389020, 0.760448, 1.504588");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011");
+ values ( "0.049394, 0.202121, 0.377259, 0.699787, 1.344843",\
+ "0.135777, 0.289295, 0.464364, 0.786501, 1.430777",\
+ "0.219280, 0.377422, 0.552318, 0.874123, 1.517732",\
+ "0.277495, 0.441815, 0.616434, 0.938036, 1.581241",\
+ "0.579315, 0.791690, 0.966814, 1.286775, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011");
+ values ( "0.025727, 0.301499, 0.634339, 1.249181, 2.473548",\
+ "0.030075, 0.302497, 0.636280, 1.249181, 2.473548",\
+ "0.042844, 0.304737, 0.636316, 1.249256, 2.473548",\
+ "0.054772, 0.307992, 0.636419, 1.250001, 2.473548",\
+ "0.130732, 0.346122, 0.642669, 1.252962, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011");
+ values ( "0.068872, 0.173483, 0.284777, 0.488748, 0.896689",\
+ "0.156281, 0.260801, 0.372058, 0.576053, 0.984043",\
+ "0.236656, 0.341133, 0.452085, 0.656082, 1.064075",\
+ "0.293393, 0.398682, 0.509628, 0.713326, 1.120722",\
+ "0.587658, 0.702023, 0.813259, 1.016339, 1.422499");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011");
+ values ( "0.025649, 0.187597, 0.387009, 0.758216, 1.500631",\
+ "0.025649, 0.187597, 0.387009, 0.758216, 1.500631",\
+ "0.026685, 0.187597, 0.387009, 0.758216, 1.500631",\
+ "0.028708, 0.188206, 0.387467, 0.759119, 1.502422",\
+ "0.047111, 0.192480, 0.387540, 0.759889, 1.504588");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025727, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216740, 0.170811, 0.140611, 0.129267, 0.142952",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025649, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251094, 0.175772, 0.107614, 0.084646, 0.147560",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025727, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148667, -0.106250, -0.071763, -0.032339, 0.273708",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025649, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164250, -0.098335, -0.040676, 0.001285, 0.221893",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_hldr*/
+
+} /* end of pin dpram_rml_o[6] */
+
+pin("dpram_rml_o[5]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002976 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[5];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011");
+ values ( "0.050791, 0.203162, 0.378041, 0.700308, 1.344843",\
+ "0.137251, 0.290336, 0.465144, 0.787022, 1.430777",\
+ "0.221098, 0.378462, 0.553098, 0.874643, 1.517732",\
+ "0.279660, 0.442853, 0.617213, 0.938556, 1.581241",\
+ "0.583574, 0.792734, 0.967589, 1.287292, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011");
+ values ( "0.027602, 0.303474, 0.635832, 1.251409, 2.482564",\
+ "0.031755, 0.304483, 0.637765, 1.251409, 2.482564",\
+ "0.044318, 0.306705, 0.637801, 1.251409, 2.482564",\
+ "0.056271, 0.309934, 0.637906, 1.251409, 2.482564",\
+ "0.132611, 0.347810, 0.644148, 1.253948, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011");
+ values ( "0.070108, 0.174130, 0.285256, 0.489062, 0.896674",\
+ "0.157512, 0.261448, 0.372537, 0.576367, 0.984027",\
+ "0.237907, 0.341777, 0.452564, 0.656396, 1.064059",\
+ "0.294694, 0.399327, 0.510106, 0.713639, 1.120707",\
+ "0.589475, 0.702670, 0.813735, 1.016652, 1.422484");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011");
+ values ( "0.026923, 0.189558, 0.389390, 0.761020, 1.504280",\
+ "0.026923, 0.189709, 0.389892, 0.761020, 1.504280",\
+ "0.027904, 0.189709, 0.389892, 0.761020, 1.504280",\
+ "0.029873, 0.189709, 0.389892, 0.761020, 1.504280",\
+ "0.048032, 0.193598, 0.389892, 0.761020, 1.504560");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011");
+ values ( "0.050791, 0.203162, 0.378041, 0.700308, 1.344843",\
+ "0.137251, 0.290336, 0.465144, 0.787022, 1.430777",\
+ "0.221098, 0.378462, 0.553098, 0.874643, 1.517732",\
+ "0.279660, 0.442853, 0.617213, 0.938556, 1.581241",\
+ "0.583574, 0.792734, 0.967589, 1.287292, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011");
+ values ( "0.027602, 0.303474, 0.635832, 1.250171, 2.473548",\
+ "0.031755, 0.304483, 0.637765, 1.250171, 2.473548",\
+ "0.044318, 0.306705, 0.637801, 1.250246, 2.473548",\
+ "0.056271, 0.309934, 0.637906, 1.250992, 2.473548",\
+ "0.132611, 0.347810, 0.644148, 1.253948, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011");
+ values ( "0.070108, 0.174130, 0.285256, 0.489062, 0.896674",\
+ "0.157512, 0.261448, 0.372537, 0.576367, 0.984027",\
+ "0.237907, 0.341777, 0.452564, 0.656396, 1.064059",\
+ "0.294694, 0.399327, 0.510106, 0.713639, 1.120707",\
+ "0.589475, 0.702670, 0.813735, 1.016652, 1.422484");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011");
+ values ( "0.026923, 0.188750, 0.387880, 0.758788, 1.500602",\
+ "0.026923, 0.188750, 0.387880, 0.758788, 1.500602",\
+ "0.027904, 0.188750, 0.387880, 0.758788, 1.500602",\
+ "0.029873, 0.189357, 0.388339, 0.759691, 1.502394",\
+ "0.048032, 0.193598, 0.388414, 0.760463, 1.504560");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027602, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.217608, 0.171679, 0.141479, 0.130136, 0.143821",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026923, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251674, 0.176353, 0.108194, 0.085227, 0.148140",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027602, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.149535, -0.107118, -0.072631, -0.033208, 0.272839",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026923, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164830, -0.098915, -0.041256, 0.000705, 0.221313",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_hldr*/
+
+} /* end of pin dpram_rml_o[5] */
+
+pin("dpram_rml_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.004037 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[4];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\
+ "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\
+ "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\
+ "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\
+ "0.592316, 0.794877, 0.969181, 1.288353, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.031452, 0.307528, 0.638897, 1.253452, 2.482564",\
+ "0.035203, 0.308560, 0.640814, 1.253452, 2.482564",\
+ "0.047343, 0.310745, 0.640850, 1.253452, 2.482564",\
+ "0.059348, 0.313921, 0.640958, 1.253452, 2.482564",\
+ "0.136469, 0.351276, 0.647183, 1.255971, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\
+ "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\
+ "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\
+ "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\
+ "0.593185, 0.703993, 0.814708, 1.017287, 1.422446");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.029527, 0.191922, 0.391170, 0.762184, 1.504210",\
+ "0.029527, 0.192081, 0.391669, 0.762184, 1.504210",\
+ "0.030394, 0.192081, 0.391669, 0.762184, 1.504210",\
+ "0.032251, 0.192081, 0.391669, 0.762184, 1.504210",\
+ "0.049913, 0.195880, 0.391669, 0.762184, 1.504490");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\
+ "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\
+ "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\
+ "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\
+ "0.592316, 0.794877, 0.969181, 1.288353, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.031452, 0.307528, 0.638897, 1.252203, 2.473548",\
+ "0.035203, 0.308560, 0.640814, 1.252203, 2.473548",\
+ "0.047343, 0.310745, 0.640850, 1.252279, 2.473548",\
+ "0.059348, 0.313921, 0.640958, 1.253027, 2.473548",\
+ "0.136469, 0.351276, 0.647183, 1.255971, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\
+ "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\
+ "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\
+ "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\
+ "0.593185, 0.703993, 0.814708, 1.017287, 1.422446");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\
+ "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\
+ "0.030394, 0.191105, 0.389657, 0.759949, 1.500533",\
+ "0.032251, 0.191709, 0.390118, 0.760853, 1.502324",\
+ "0.049913, 0.195880, 0.390196, 0.761627, 1.504490");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.219390, 0.173461, 0.143262, 0.131918, 0.145603",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.252859, 0.177538, 0.109379, 0.086412, 0.149326",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.151318, -0.108901, -0.074414, -0.034990, 0.271057",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.166015, -0.100100, -0.042441, -0.000480, 0.220128",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_hldr*/
+
+} /* end of pin dpram_rml_o[4] */
+
+pin("dpram_rml_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002031 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\
+ "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\
+ "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\
+ "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\
+ "0.575781, 0.790824, 0.966170, 1.286346, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.024170, 0.299860, 0.633100, 1.249588, 2.482563",\
+ "0.028681, 0.300849, 0.635047, 1.249588, 2.482563",\
+ "0.041621, 0.303103, 0.635083, 1.249588, 2.482563",\
+ "0.053528, 0.306381, 0.635185, 1.249588, 2.482563",\
+ "0.129172, 0.344721, 0.641441, 1.252143, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\
+ "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\
+ "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\
+ "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\
+ "0.586178, 0.701495, 0.812873, 1.016089, 1.422521");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.024610, 0.187457, 0.387810, 0.759990, 1.504349",\
+ "0.024610, 0.187602, 0.388314, 0.759990, 1.504349",\
+ "0.025692, 0.187602, 0.388314, 0.759990, 1.504349",\
+ "0.027759, 0.187602, 0.388314, 0.759990, 1.504349",\
+ "0.046361, 0.191570, 0.388314, 0.759990, 1.504629");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\
+ "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\
+ "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\
+ "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\
+ "0.575781, 0.790824, 0.966170, 1.286346, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.024170, 0.299860, 0.633100, 1.248359, 2.473548",\
+ "0.028681, 0.300849, 0.635047, 1.248359, 2.473548",\
+ "0.041621, 0.303103, 0.635083, 1.248434, 2.473548",\
+ "0.053528, 0.306381, 0.635185, 1.249178, 2.473548",\
+ "0.129172, 0.344721, 0.641441, 1.252143, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\
+ "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\
+ "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\
+ "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\
+ "0.586178, 0.701495, 0.812873, 1.016089, 1.422521");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\
+ "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\
+ "0.025692, 0.186657, 0.386303, 0.757760, 1.500672",\
+ "0.027759, 0.187268, 0.386760, 0.758661, 1.502463",\
+ "0.046361, 0.191570, 0.386832, 0.759431, 1.504629");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216019, 0.170090, 0.139890, 0.128547, 0.142232",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250621, 0.175300, 0.107141, 0.084173, 0.147087",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147946, -0.105529, -0.071042, -0.031619, 0.274428",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163777, -0.097862, -0.040203, 0.001758, 0.222366",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_hldr*/
+
+} /* end of pin dpram_rml_o[3] */
+
+pin("dpram_rml_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003654 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\
+ "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\
+ "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\
+ "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\
+ "0.589159, 0.794103, 0.968606, 1.287970, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.030062, 0.306064, 0.637790, 1.252714, 2.482564",\
+ "0.033958, 0.307087, 0.639713, 1.252714, 2.482564",\
+ "0.046250, 0.309286, 0.639749, 1.252714, 2.482564",\
+ "0.058237, 0.312481, 0.639856, 1.252714, 2.482564",\
+ "0.135075, 0.350024, 0.646087, 1.255240, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\
+ "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\
+ "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\
+ "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\
+ "0.591837, 0.703513, 0.814354, 1.017055, 1.422457");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.028581, 0.191064, 0.390523, 0.761759, 1.504230",\
+ "0.028581, 0.191220, 0.391022, 0.761759, 1.504230",\
+ "0.029490, 0.191220, 0.391022, 0.761759, 1.504230",\
+ "0.031388, 0.191220, 0.391022, 0.761759, 1.504230",\
+ "0.049229, 0.195051, 0.391022, 0.761759, 1.504510");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\
+ "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\
+ "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\
+ "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\
+ "0.589159, 0.794103, 0.968606, 1.287970, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.030062, 0.306064, 0.637790, 1.251469, 2.473548",\
+ "0.033958, 0.307087, 0.639713, 1.251469, 2.473548",\
+ "0.046250, 0.309286, 0.639749, 1.251544, 2.473548",\
+ "0.058237, 0.312481, 0.639856, 1.252292, 2.473548",\
+ "0.135075, 0.350024, 0.646087, 1.255240, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\
+ "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\
+ "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\
+ "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\
+ "0.591837, 0.703513, 0.814354, 1.017055, 1.422457");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\
+ "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\
+ "0.029490, 0.190249, 0.389010, 0.759525, 1.500553",\
+ "0.031388, 0.190855, 0.389471, 0.760429, 1.502345",\
+ "0.049229, 0.195051, 0.389548, 0.761202, 1.504510");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.218747, 0.172818, 0.142618, 0.131274, 0.144959",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.252429, 0.177108, 0.108949, 0.085981, 0.148895",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.150674, -0.108257, -0.073770, -0.034347, 0.271701",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.165584, -0.099669, -0.042010, -0.000049, 0.220558",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_hldr*/
+
+} /* end of pin dpram_rml_o[2] */
+
+pin("dpram_rml_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002005 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\
+ "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\
+ "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\
+ "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\
+ "0.575569, 0.790772, 0.966132, 1.286320, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\
+ "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\
+ "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\
+ "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\
+ "0.129078, 0.344637, 0.641368, 1.252094, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\
+ "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\
+ "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\
+ "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\
+ "0.586096, 0.701465, 0.812852, 1.016076, 1.422525");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\
+ "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.046319, 0.191519, 0.388276, 0.759966, 1.504636");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\
+ "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\
+ "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\
+ "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\
+ "0.575569, 0.790772, 0.966132, 1.286320, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\
+ "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\
+ "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\
+ "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\
+ "0.129078, 0.344637, 0.641368, 1.252094, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\
+ "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\
+ "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\
+ "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\
+ "0.586096, 0.701465, 0.812852, 1.016076, 1.422525");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\
+ "0.046319, 0.191519, 0.386794, 0.759408, 1.504636");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_hldr*/
+
+} /* end of pin dpram_rml_o[1] */
+
+pin("dpram_rml_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002547 ;
+
+ /* Other user defined attributes. */
+ original_pin : dpram_rml_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\
+ "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\
+ "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\
+ "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\
+ "0.580033, 0.791866, 0.966945, 1.286862, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.026043, 0.301832, 0.634591, 1.250582, 2.482563",\
+ "0.030358, 0.302831, 0.636530, 1.250582, 2.482563",\
+ "0.043092, 0.305068, 0.636566, 1.250582, 2.482563",\
+ "0.055024, 0.308320, 0.636670, 1.250582, 2.482563",\
+ "0.131048, 0.346407, 0.642918, 1.253128, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\
+ "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\
+ "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\
+ "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\
+ "0.587968, 0.702133, 0.813340, 1.016393, 1.422498");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.025866, 0.188597, 0.388667, 0.760546, 1.504306",\
+ "0.025866, 0.188746, 0.389169, 0.760546, 1.504306",\
+ "0.026893, 0.188746, 0.389169, 0.760546, 1.504306",\
+ "0.028907, 0.188746, 0.389169, 0.760546, 1.504306",\
+ "0.047268, 0.192671, 0.389169, 0.760546, 1.504586");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\
+ "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\
+ "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\
+ "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\
+ "0.580033, 0.791866, 0.966945, 1.286862, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.026043, 0.301832, 0.634591, 1.249347, 2.473548",\
+ "0.030358, 0.302831, 0.636530, 1.249347, 2.473548",\
+ "0.043092, 0.305068, 0.636566, 1.249423, 2.473548",\
+ "0.055024, 0.308320, 0.636670, 1.250168, 2.473548",\
+ "0.131048, 0.346407, 0.642918, 1.253128, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\
+ "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\
+ "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\
+ "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\
+ "0.587968, 0.702133, 0.813340, 1.016393, 1.422498");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\
+ "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\
+ "0.026893, 0.187793, 0.387158, 0.758315, 1.500628",\
+ "0.028907, 0.188402, 0.387616, 0.759217, 1.502420",\
+ "0.047268, 0.192671, 0.387690, 0.759988, 1.504586");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216886, 0.170957, 0.140757, 0.129414, 0.143099",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251193, 0.175871, 0.107712, 0.084745, 0.147659",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148813, -0.106396, -0.071909, -0.032486, 0.273561",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164349, -0.098434, -0.040775, 0.001186, 0.221794",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_hldr*/
+
+} /* end of pin dpram_rml_o[0] */
+} /* end of bus dpram_rml_o */
+bus ( spram_rm_o ) {
+
+ bus_type : BUS5_type4 ;
+ direction : output ;
+
+pin("spram_rm_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002015 ;
+
+ /* Other user defined attributes. */
+ original_pin : spram_rm_o[4];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\
+ "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\
+ "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\
+ "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\
+ "0.575653, 0.790792, 0.966147, 1.286330, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\
+ "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\
+ "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\
+ "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\
+ "0.129115, 0.344671, 0.641397, 1.252114, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\
+ "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\
+ "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\
+ "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\
+ "0.586128, 0.701477, 0.812860, 1.016081, 1.422524");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\
+ "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.046336, 0.191539, 0.388291, 0.759976, 1.504633");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\
+ "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\
+ "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\
+ "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\
+ "0.575653, 0.790792, 0.966147, 1.286330, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\
+ "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\
+ "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\
+ "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\
+ "0.129115, 0.344671, 0.641397, 1.252114, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\
+ "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\
+ "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\
+ "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\
+ "0.586128, 0.701477, 0.812860, 1.016081, 1.422524");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\
+ "0.046336, 0.191539, 0.386809, 0.759417, 1.504633");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_hldr*/
+
+} /* end of pin spram_rm_o[4] */
+
+pin("spram_rm_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002005 ;
+
+ /* Other user defined attributes. */
+ original_pin : spram_rm_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\
+ "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\
+ "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\
+ "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\
+ "0.575569, 0.790772, 0.966132, 1.286320, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\
+ "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\
+ "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\
+ "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\
+ "0.129078, 0.344637, 0.641368, 1.252094, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\
+ "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\
+ "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\
+ "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\
+ "0.586096, 0.701465, 0.812852, 1.016076, 1.422525");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\
+ "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.046319, 0.191519, 0.388276, 0.759966, 1.504636");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\
+ "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\
+ "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\
+ "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\
+ "0.575569, 0.790772, 0.966132, 1.286320, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\
+ "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\
+ "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\
+ "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\
+ "0.129078, 0.344637, 0.641368, 1.252094, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\
+ "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\
+ "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\
+ "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\
+ "0.586096, 0.701465, 0.812852, 1.016076, 1.422525");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\
+ "0.046319, 0.191519, 0.386794, 0.759408, 1.504636");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_hldr*/
+
+} /* end of pin spram_rm_o[3] */
+
+pin("spram_rm_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002015 ;
+
+ /* Other user defined attributes. */
+ original_pin : spram_rm_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\
+ "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\
+ "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\
+ "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\
+ "0.575653, 0.790792, 0.966147, 1.286330, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\
+ "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\
+ "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\
+ "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\
+ "0.129115, 0.344671, 0.641397, 1.252114, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\
+ "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\
+ "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\
+ "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\
+ "0.586128, 0.701477, 0.812860, 1.016081, 1.422524");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\
+ "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\
+ "0.046336, 0.191539, 0.388291, 0.759976, 1.504633");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\
+ "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\
+ "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\
+ "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\
+ "0.575653, 0.790792, 0.966147, 1.286330, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\
+ "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\
+ "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\
+ "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\
+ "0.129115, 0.344671, 0.641397, 1.252114, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\
+ "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\
+ "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\
+ "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\
+ "0.586128, 0.701477, 0.812860, 1.016081, 1.422524");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011");
+ values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\
+ "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\
+ "0.046336, 0.191539, 0.386809, 0.759417, 1.504633");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_hldr*/
+
+} /* end of pin spram_rm_o[2] */
+
+pin("spram_rm_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003002 ;
+
+ /* Other user defined attributes. */
+ original_pin : spram_rm_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\
+ "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\
+ "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\
+ "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\
+ "0.583788, 0.792786, 0.967628, 1.287318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.027696, 0.303573, 0.635907, 1.251459, 2.482564",\
+ "0.031840, 0.304583, 0.637840, 1.251459, 2.482564",\
+ "0.044392, 0.306804, 0.637876, 1.251459, 2.482564",\
+ "0.056346, 0.310032, 0.637981, 1.251459, 2.482564",\
+ "0.132705, 0.347895, 0.644222, 1.253997, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\
+ "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\
+ "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\
+ "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\
+ "0.589569, 0.702704, 0.813760, 1.016668, 1.422484");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.026989, 0.189618, 0.389436, 0.761051, 1.504280",\
+ "0.026989, 0.189769, 0.389937, 0.761051, 1.504280",\
+ "0.027967, 0.189769, 0.389937, 0.761051, 1.504280",\
+ "0.029933, 0.189769, 0.389937, 0.761051, 1.504280",\
+ "0.048080, 0.193656, 0.389937, 0.761051, 1.504560");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\
+ "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\
+ "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\
+ "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\
+ "0.583788, 0.792786, 0.967628, 1.287318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.027696, 0.303573, 0.635907, 1.250220, 2.473548",\
+ "0.031840, 0.304583, 0.637840, 1.250220, 2.473548",\
+ "0.044392, 0.306804, 0.637876, 1.250296, 2.473548",\
+ "0.056346, 0.310032, 0.637981, 1.251042, 2.473548",\
+ "0.132705, 0.347895, 0.644222, 1.253997, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\
+ "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\
+ "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\
+ "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\
+ "0.589569, 0.702704, 0.813760, 1.016668, 1.422484");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\
+ "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\
+ "0.027967, 0.188809, 0.387926, 0.758818, 1.500603",\
+ "0.029933, 0.189417, 0.388385, 0.759721, 1.502395",\
+ "0.048080, 0.193656, 0.388460, 0.760493, 1.504560");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.217652, 0.171723, 0.141523, 0.130179, 0.143864",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251704, 0.176383, 0.108224, 0.085257, 0.148171",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.149579, -0.107162, -0.072675, -0.033251, 0.272796",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164860, -0.098945, -0.041286, 0.000675, 0.221283",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_hldr*/
+
+} /* end of pin spram_rm_o[1] */
+
+pin("spram_rm_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002026 ;
+
+ /* Other user defined attributes. */
+ original_pin : spram_rm_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\
+ "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\
+ "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\
+ "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\
+ "0.575742, 0.790814, 0.966163, 1.286341, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\
+ "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\
+ "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\
+ "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\
+ "0.129154, 0.344706, 0.641428, 1.252134, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\
+ "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\
+ "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\
+ "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\
+ "0.586152, 0.701486, 0.812865, 1.016083, 1.422518");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\
+ "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.046348, 0.191554, 0.388300, 0.759979, 1.504623");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\
+ "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\
+ "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\
+ "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\
+ "0.575742, 0.790814, 0.966163, 1.286341, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\
+ "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\
+ "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\
+ "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\
+ "0.129154, 0.344706, 0.641428, 1.252134, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\
+ "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\
+ "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\
+ "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\
+ "0.586152, 0.701486, 0.812865, 1.016083, 1.422518");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\
+ "0.046348, 0.191554, 0.386818, 0.759420, 1.504623");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_hldr*/
+
+} /* end of pin spram_rm_o[0] */
+} /* end of bus spram_rm_o */
+bus ( sprgf_rm_o ) {
+
+ bus_type : BUS5_type4 ;
+ direction : output ;
+
+pin("sprgf_rm_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.004037 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprgf_rm_o[4];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\
+ "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\
+ "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\
+ "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\
+ "0.592316, 0.794877, 0.969181, 1.288353, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.031452, 0.307528, 0.638897, 1.253452, 2.482564",\
+ "0.035203, 0.308560, 0.640814, 1.253452, 2.482564",\
+ "0.047343, 0.310745, 0.640850, 1.253452, 2.482564",\
+ "0.059348, 0.313921, 0.640958, 1.253452, 2.482564",\
+ "0.136469, 0.351276, 0.647183, 1.255971, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\
+ "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\
+ "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\
+ "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\
+ "0.593185, 0.703993, 0.814708, 1.017287, 1.422446");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.029527, 0.191922, 0.391170, 0.762184, 1.504210",\
+ "0.029527, 0.192081, 0.391669, 0.762184, 1.504210",\
+ "0.030394, 0.192081, 0.391669, 0.762184, 1.504210",\
+ "0.032251, 0.192081, 0.391669, 0.762184, 1.504210",\
+ "0.049913, 0.195880, 0.391669, 0.762184, 1.504490");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\
+ "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\
+ "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\
+ "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\
+ "0.592316, 0.794877, 0.969181, 1.288353, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.031452, 0.307528, 0.638897, 1.252203, 2.473548",\
+ "0.035203, 0.308560, 0.640814, 1.252203, 2.473548",\
+ "0.047343, 0.310745, 0.640850, 1.252279, 2.473548",\
+ "0.059348, 0.313921, 0.640958, 1.253027, 2.473548",\
+ "0.136469, 0.351276, 0.647183, 1.255971, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\
+ "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\
+ "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\
+ "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\
+ "0.593185, 0.703993, 0.814708, 1.017287, 1.422446");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011");
+ values ( "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\
+ "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\
+ "0.030394, 0.191105, 0.389657, 0.759949, 1.500533",\
+ "0.032251, 0.191709, 0.390118, 0.760853, 1.502324",\
+ "0.049913, 0.195880, 0.390196, 0.761627, 1.504490");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.219390, 0.173461, 0.143262, 0.131918, 0.145603",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.252859, 0.177538, 0.109379, 0.086412, 0.149326",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.151318, -0.108901, -0.074414, -0.034990, 0.271057",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.166015, -0.100100, -0.042441, -0.000480, 0.220128",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_hldr*/
+
+} /* end of pin sprgf_rm_o[4] */
+
+pin("sprgf_rm_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002031 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprgf_rm_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\
+ "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\
+ "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\
+ "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\
+ "0.575781, 0.790824, 0.966170, 1.286346, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.024170, 0.299860, 0.633100, 1.249588, 2.482563",\
+ "0.028681, 0.300849, 0.635047, 1.249588, 2.482563",\
+ "0.041621, 0.303103, 0.635083, 1.249588, 2.482563",\
+ "0.053528, 0.306381, 0.635185, 1.249588, 2.482563",\
+ "0.129172, 0.344721, 0.641441, 1.252143, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\
+ "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\
+ "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\
+ "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\
+ "0.586178, 0.701495, 0.812873, 1.016089, 1.422521");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.024610, 0.187457, 0.387810, 0.759990, 1.504349",\
+ "0.024610, 0.187602, 0.388314, 0.759990, 1.504349",\
+ "0.025692, 0.187602, 0.388314, 0.759990, 1.504349",\
+ "0.027759, 0.187602, 0.388314, 0.759990, 1.504349",\
+ "0.046361, 0.191570, 0.388314, 0.759990, 1.504629");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\
+ "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\
+ "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\
+ "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\
+ "0.575781, 0.790824, 0.966170, 1.286346, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.024170, 0.299860, 0.633100, 1.248359, 2.473548",\
+ "0.028681, 0.300849, 0.635047, 1.248359, 2.473548",\
+ "0.041621, 0.303103, 0.635083, 1.248434, 2.473548",\
+ "0.053528, 0.306381, 0.635185, 1.249178, 2.473548",\
+ "0.129172, 0.344721, 0.641441, 1.252143, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\
+ "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\
+ "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\
+ "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\
+ "0.586178, 0.701495, 0.812873, 1.016089, 1.422521");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011");
+ values ( "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\
+ "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\
+ "0.025692, 0.186657, 0.386303, 0.757760, 1.500672",\
+ "0.027759, 0.187268, 0.386760, 0.758661, 1.502463",\
+ "0.046361, 0.191570, 0.386832, 0.759431, 1.504629");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216019, 0.170090, 0.139890, 0.128547, 0.142232",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250621, 0.175300, 0.107141, 0.084173, 0.147087",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147946, -0.105529, -0.071042, -0.031619, 0.274428",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163777, -0.097862, -0.040203, 0.001758, 0.222366",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_hldr*/
+
+} /* end of pin sprgf_rm_o[3] */
+
+pin("sprgf_rm_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003654 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprgf_rm_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\
+ "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\
+ "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\
+ "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\
+ "0.589159, 0.794103, 0.968606, 1.287970, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.030062, 0.306064, 0.637790, 1.252714, 2.482564",\
+ "0.033958, 0.307087, 0.639713, 1.252714, 2.482564",\
+ "0.046250, 0.309286, 0.639749, 1.252714, 2.482564",\
+ "0.058237, 0.312481, 0.639856, 1.252714, 2.482564",\
+ "0.135075, 0.350024, 0.646087, 1.255240, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\
+ "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\
+ "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\
+ "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\
+ "0.591837, 0.703513, 0.814354, 1.017055, 1.422457");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.028581, 0.191064, 0.390523, 0.761759, 1.504230",\
+ "0.028581, 0.191220, 0.391022, 0.761759, 1.504230",\
+ "0.029490, 0.191220, 0.391022, 0.761759, 1.504230",\
+ "0.031388, 0.191220, 0.391022, 0.761759, 1.504230",\
+ "0.049229, 0.195051, 0.391022, 0.761759, 1.504510");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\
+ "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\
+ "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\
+ "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\
+ "0.589159, 0.794103, 0.968606, 1.287970, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.030062, 0.306064, 0.637790, 1.251469, 2.473548",\
+ "0.033958, 0.307087, 0.639713, 1.251469, 2.473548",\
+ "0.046250, 0.309286, 0.639749, 1.251544, 2.473548",\
+ "0.058237, 0.312481, 0.639856, 1.252292, 2.473548",\
+ "0.135075, 0.350024, 0.646087, 1.255240, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\
+ "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\
+ "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\
+ "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\
+ "0.591837, 0.703513, 0.814354, 1.017055, 1.422457");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011");
+ values ( "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\
+ "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\
+ "0.029490, 0.190249, 0.389010, 0.759525, 1.500553",\
+ "0.031388, 0.190855, 0.389471, 0.760429, 1.502345",\
+ "0.049229, 0.195051, 0.389548, 0.761202, 1.504510");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.218747, 0.172818, 0.142618, 0.131274, 0.144959",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.252429, 0.177108, 0.108949, 0.085981, 0.148895",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.150674, -0.108257, -0.073770, -0.034347, 0.271701",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.165584, -0.099669, -0.042010, -0.000049, 0.220558",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_hldr*/
+
+} /* end of pin sprgf_rm_o[2] */
+
+pin("sprgf_rm_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002005 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprgf_rm_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\
+ "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\
+ "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\
+ "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\
+ "0.575569, 0.790772, 0.966132, 1.286320, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\
+ "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\
+ "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\
+ "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\
+ "0.129078, 0.344637, 0.641368, 1.252094, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\
+ "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\
+ "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\
+ "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\
+ "0.586096, 0.701465, 0.812852, 1.016076, 1.422525");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\
+ "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\
+ "0.046319, 0.191519, 0.388276, 0.759966, 1.504636");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\
+ "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\
+ "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\
+ "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\
+ "0.575569, 0.790772, 0.966132, 1.286320, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\
+ "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\
+ "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\
+ "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\
+ "0.129078, 0.344637, 0.641368, 1.252094, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\
+ "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\
+ "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\
+ "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\
+ "0.586096, 0.701465, 0.812852, 1.016076, 1.422525");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011");
+ values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\
+ "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\
+ "0.046319, 0.191519, 0.386794, 0.759408, 1.504636");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_hldr*/
+
+} /* end of pin sprgf_rm_o[1] */
+
+pin("sprgf_rm_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002547 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprgf_rm_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\
+ "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\
+ "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\
+ "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\
+ "0.580033, 0.791866, 0.966945, 1.286862, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.026043, 0.301832, 0.634591, 1.250582, 2.482563",\
+ "0.030358, 0.302831, 0.636530, 1.250582, 2.482563",\
+ "0.043092, 0.305068, 0.636566, 1.250582, 2.482563",\
+ "0.055024, 0.308320, 0.636670, 1.250582, 2.482563",\
+ "0.131048, 0.346407, 0.642918, 1.253128, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\
+ "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\
+ "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\
+ "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\
+ "0.587968, 0.702133, 0.813340, 1.016393, 1.422498");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.025866, 0.188597, 0.388667, 0.760546, 1.504306",\
+ "0.025866, 0.188746, 0.389169, 0.760546, 1.504306",\
+ "0.026893, 0.188746, 0.389169, 0.760546, 1.504306",\
+ "0.028907, 0.188746, 0.389169, 0.760546, 1.504306",\
+ "0.047268, 0.192671, 0.389169, 0.760546, 1.504586");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\
+ "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\
+ "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\
+ "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\
+ "0.580033, 0.791866, 0.966945, 1.286862, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.026043, 0.301832, 0.634591, 1.249347, 2.473548",\
+ "0.030358, 0.302831, 0.636530, 1.249347, 2.473548",\
+ "0.043092, 0.305068, 0.636566, 1.249423, 2.473548",\
+ "0.055024, 0.308320, 0.636670, 1.250168, 2.473548",\
+ "0.131048, 0.346407, 0.642918, 1.253128, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\
+ "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\
+ "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\
+ "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\
+ "0.587968, 0.702133, 0.813340, 1.016393, 1.422498");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011");
+ values ( "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\
+ "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\
+ "0.026893, 0.187793, 0.387158, 0.758315, 1.500628",\
+ "0.028907, 0.188402, 0.387616, 0.759217, 1.502420",\
+ "0.047268, 0.192671, 0.387690, 0.759988, 1.504586");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216886, 0.170957, 0.140757, 0.129414, 0.143099",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251193, 0.175871, 0.107712, 0.084745, 0.147659",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148813, -0.106396, -0.071909, -0.032486, 0.273561",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164349, -0.098434, -0.040775, 0.001186, 0.221794",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_hldr*/
+
+} /* end of pin sprgf_rm_o[0] */
+} /* end of bus sprgf_rm_o */
+bus ( sprom_rm_o ) {
+
+ bus_type : BUS5_type4 ;
+ direction : output ;
+
+pin("sprom_rm_o[4]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003002 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprom_rm_o[4];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\
+ "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\
+ "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\
+ "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\
+ "0.583788, 0.792786, 0.967628, 1.287318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.027696, 0.303573, 0.635907, 1.251459, 2.482564",\
+ "0.031840, 0.304583, 0.637840, 1.251459, 2.482564",\
+ "0.044392, 0.306804, 0.637876, 1.251459, 2.482564",\
+ "0.056346, 0.310032, 0.637981, 1.251459, 2.482564",\
+ "0.132705, 0.347895, 0.644222, 1.253997, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\
+ "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\
+ "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\
+ "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\
+ "0.589569, 0.702704, 0.813760, 1.016668, 1.422484");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.026989, 0.189618, 0.389436, 0.761051, 1.504280",\
+ "0.026989, 0.189769, 0.389937, 0.761051, 1.504280",\
+ "0.027967, 0.189769, 0.389937, 0.761051, 1.504280",\
+ "0.029933, 0.189769, 0.389937, 0.761051, 1.504280",\
+ "0.048080, 0.193656, 0.389937, 0.761051, 1.504560");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\
+ "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\
+ "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\
+ "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\
+ "0.583788, 0.792786, 0.967628, 1.287318, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.027696, 0.303573, 0.635907, 1.250220, 2.473548",\
+ "0.031840, 0.304583, 0.637840, 1.250220, 2.473548",\
+ "0.044392, 0.306804, 0.637876, 1.250296, 2.473548",\
+ "0.056346, 0.310032, 0.637981, 1.251042, 2.473548",\
+ "0.132705, 0.347895, 0.644222, 1.253997, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\
+ "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\
+ "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\
+ "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\
+ "0.589569, 0.702704, 0.813760, 1.016668, 1.422484");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011");
+ values ( "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\
+ "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\
+ "0.027967, 0.188809, 0.387926, 0.758818, 1.500603",\
+ "0.029933, 0.189417, 0.388385, 0.759721, 1.502395",\
+ "0.048080, 0.193656, 0.388460, 0.760493, 1.504560");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.217652, 0.171723, 0.141523, 0.130179, 0.143864",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251704, 0.176383, 0.108224, 0.085257, 0.148171",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.149579, -0.107162, -0.072675, -0.033251, 0.272796",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164860, -0.098945, -0.041286, 0.000675, 0.221283",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_hldr*/
+
+} /* end of pin sprom_rm_o[4] */
+
+pin("sprom_rm_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002553 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprom_rm_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011");
+ values ( "0.049647, 0.202309, 0.377401, 0.699882, 1.344843",\
+ "0.136044, 0.289484, 0.464505, 0.786596, 1.430777",\
+ "0.219609, 0.377611, 0.552460, 0.874217, 1.517732",\
+ "0.277887, 0.442003, 0.616575, 0.938130, 1.581241",\
+ "0.580088, 0.791879, 0.966955, 1.286869, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011");
+ values ( "0.026067, 0.301857, 0.634610, 1.250594, 2.482563",\
+ "0.030380, 0.302857, 0.636549, 1.250594, 2.482563",\
+ "0.043111, 0.305094, 0.636586, 1.250594, 2.482563",\
+ "0.055044, 0.308345, 0.636689, 1.250594, 2.482563",\
+ "0.131072, 0.346429, 0.642937, 1.253140, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011");
+ values ( "0.069111, 0.173607, 0.284871, 0.488812, 0.896694",\
+ "0.156518, 0.260926, 0.372152, 0.576117, 0.984047",\
+ "0.236897, 0.341257, 0.452179, 0.656146, 1.064079",\
+ "0.293644, 0.398806, 0.509722, 0.713390, 1.120727",\
+ "0.588008, 0.702147, 0.813352, 1.016403, 1.422503");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011");
+ values ( "0.025894, 0.188623, 0.388689, 0.760565, 1.504316",\
+ "0.025894, 0.188772, 0.389191, 0.760565, 1.504316",\
+ "0.026920, 0.188772, 0.389191, 0.760565, 1.504316",\
+ "0.028933, 0.188772, 0.389191, 0.760565, 1.504316",\
+ "0.047288, 0.192696, 0.389191, 0.760565, 1.504596");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011");
+ values ( "0.049647, 0.202309, 0.377401, 0.699882, 1.344843",\
+ "0.136044, 0.289484, 0.464505, 0.786596, 1.430777",\
+ "0.219609, 0.377611, 0.552460, 0.874217, 1.517732",\
+ "0.277887, 0.442003, 0.616575, 0.938130, 1.581241",\
+ "0.580088, 0.791879, 0.966955, 1.286869, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011");
+ values ( "0.026067, 0.301857, 0.634610, 1.249360, 2.473548",\
+ "0.030380, 0.302857, 0.636549, 1.249360, 2.473548",\
+ "0.043111, 0.305094, 0.636586, 1.249435, 2.473548",\
+ "0.055044, 0.308345, 0.636689, 1.250180, 2.473548",\
+ "0.131072, 0.346429, 0.642937, 1.253140, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011");
+ values ( "0.069111, 0.173607, 0.284871, 0.488812, 0.896694",\
+ "0.156518, 0.260926, 0.372152, 0.576117, 0.984047",\
+ "0.236897, 0.341257, 0.452179, 0.656146, 1.064079",\
+ "0.293644, 0.398806, 0.509722, 0.713390, 1.120727",\
+ "0.588008, 0.702147, 0.813352, 1.016403, 1.422503");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011");
+ values ( "0.025894, 0.187819, 0.387180, 0.758333, 1.500639",\
+ "0.025894, 0.187819, 0.387180, 0.758333, 1.500639",\
+ "0.026920, 0.187819, 0.387180, 0.758333, 1.500639",\
+ "0.028933, 0.188428, 0.387638, 0.759236, 1.502430",\
+ "0.047288, 0.192696, 0.387712, 0.760007, 1.504596");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026067, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216897, 0.170968, 0.140769, 0.129425, 0.143110",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025894, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251206, 0.175884, 0.107725, 0.084758, 0.147672",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.026067, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148824, -0.106407, -0.071920, -0.032497, 0.273550",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025894, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164361, -0.098446, -0.040787, 0.001174, 0.221781",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_hldr*/
+
+} /* end of pin sprom_rm_o[3] */
+
+pin("sprom_rm_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.004615 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprom_rm_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011");
+ values ( "0.055222, 0.206463, 0.380520, 0.701961, 1.344843",\
+ "0.141926, 0.293637, 0.467620, 0.788672, 1.430777",\
+ "0.226864, 0.381760, 0.555571, 0.876292, 1.517732",\
+ "0.286525, 0.446144, 0.619684, 0.940203, 1.581241",\
+ "0.597080, 0.796044, 0.970048, 1.288931, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011");
+ values ( "0.033550, 0.309737, 0.640567, 1.254566, 2.482564",\
+ "0.037083, 0.310781, 0.642475, 1.254566, 2.482564",\
+ "0.048991, 0.312947, 0.642512, 1.254566, 2.482564",\
+ "0.061025, 0.316093, 0.642622, 1.254566, 2.482564",\
+ "0.138571, 0.353164, 0.648838, 1.257074, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011");
+ values ( "0.073991, 0.176164, 0.286756, 0.490040, 0.896607",\
+ "0.161383, 0.263480, 0.374037, 0.577345, 0.983960",\
+ "0.241839, 0.343803, 0.454064, 0.657373, 1.063992",\
+ "0.298782, 0.401353, 0.511604, 0.714616, 1.120639",\
+ "0.595184, 0.704706, 0.815229, 1.017625, 1.422416");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011");
+ values ( "0.030929, 0.193196, 0.392126, 0.762803, 1.504157",\
+ "0.030929, 0.193359, 0.392623, 0.762803, 1.504157",\
+ "0.031735, 0.193359, 0.392623, 0.762803, 1.504157",\
+ "0.033533, 0.193359, 0.392623, 0.762803, 1.504157",\
+ "0.050926, 0.197109, 0.392623, 0.762803, 1.504437");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011");
+ values ( "0.055222, 0.206463, 0.380520, 0.701961, 1.344843",\
+ "0.141926, 0.293637, 0.467620, 0.788672, 1.430777",\
+ "0.226864, 0.381760, 0.555571, 0.876292, 1.517732",\
+ "0.286525, 0.446144, 0.619684, 0.940203, 1.581241",\
+ "0.597080, 0.796044, 0.970048, 1.288931, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011");
+ values ( "0.033550, 0.309737, 0.640567, 1.253311, 2.473548",\
+ "0.037083, 0.310781, 0.642475, 1.253311, 2.473548",\
+ "0.048991, 0.312947, 0.642512, 1.253386, 2.473548",\
+ "0.061025, 0.316093, 0.642622, 1.254135, 2.473548",\
+ "0.138571, 0.353164, 0.648838, 1.257074, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011");
+ values ( "0.073991, 0.176164, 0.286756, 0.490040, 0.896607",\
+ "0.161383, 0.263480, 0.374037, 0.577345, 0.983960",\
+ "0.241839, 0.343803, 0.454064, 0.657373, 1.063992",\
+ "0.298782, 0.401353, 0.511604, 0.714616, 1.120639",\
+ "0.595184, 0.704706, 0.815229, 1.017625, 1.422416");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011");
+ values ( "0.030929, 0.192373, 0.390610, 0.760567, 1.500480",\
+ "0.030929, 0.192373, 0.390610, 0.760567, 1.500480",\
+ "0.031735, 0.192373, 0.390610, 0.760567, 1.500480",\
+ "0.033533, 0.192976, 0.391072, 0.761472, 1.502271",\
+ "0.050926, 0.197109, 0.391153, 0.762247, 1.504437");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.033550, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.220362, 0.174433, 0.144233, 0.132890, 0.146575",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.030929, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.253498, 0.178177, 0.110018, 0.087050, 0.149964",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.033550, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.152289, -0.109872, -0.075385, -0.035962, 0.270085",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.030929, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.166653, -0.100738, -0.043079, -0.001118, 0.219490",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_hldr*/
+
+} /* end of pin sprom_rm_o[2] */
+
+pin("sprom_rm_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002475 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprom_rm_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\
+ "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\
+ "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\
+ "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\
+ "0.579442, 0.791721, 0.966837, 1.286790, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025782, 0.301558, 0.634384, 1.250443, 2.482564",\
+ "0.030125, 0.302556, 0.636324, 1.250443, 2.482564",\
+ "0.042888, 0.304795, 0.636360, 1.250443, 2.482564",\
+ "0.054816, 0.308050, 0.636463, 1.250443, 2.482564",\
+ "0.130787, 0.346172, 0.642713, 1.252991, 2.482564");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\
+ "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\
+ "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\
+ "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\
+ "0.587713, 0.702042, 0.813273, 1.016348, 1.422499");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025687, 0.188435, 0.388543, 0.760465, 1.504307",\
+ "0.025687, 0.188583, 0.389046, 0.760465, 1.504307",\
+ "0.026721, 0.188583, 0.389046, 0.760465, 1.504307",\
+ "0.028743, 0.188583, 0.389046, 0.760465, 1.504307",\
+ "0.047139, 0.192514, 0.389046, 0.760465, 1.504587");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\
+ "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\
+ "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\
+ "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\
+ "0.579442, 0.791721, 0.966837, 1.286790, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025782, 0.301558, 0.634384, 1.249210, 2.473548",\
+ "0.030125, 0.302556, 0.636324, 1.249210, 2.473548",\
+ "0.042888, 0.304795, 0.636360, 1.249285, 2.473548",\
+ "0.054816, 0.308050, 0.636463, 1.250030, 2.473548",\
+ "0.130787, 0.346172, 0.642713, 1.252991, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\
+ "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\
+ "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\
+ "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\
+ "0.587713, 0.702042, 0.813273, 1.016348, 1.422499");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011");
+ values ( "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\
+ "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\
+ "0.026721, 0.187631, 0.387035, 0.758233, 1.500630",\
+ "0.028743, 0.188240, 0.387493, 0.759136, 1.502422",\
+ "0.047139, 0.192514, 0.387566, 0.759907, 1.504587");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216765, 0.170836, 0.140637, 0.129293, 0.142978",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.251111, 0.175790, 0.107631, 0.084664, 0.147578",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.148693, -0.106276, -0.071789, -0.032365, 0.273682",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.164267, -0.098352, -0.040693, 0.001268, 0.221876",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_hldr*/
+
+} /* end of pin sprom_rm_o[1] */
+
+pin("sprom_rm_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.642011 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002026 ;
+
+ /* Other user defined attributes. */
+ original_pin : sprom_rm_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\
+ "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\
+ "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\
+ "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\
+ "0.575742, 0.790814, 0.966163, 1.286341, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\
+ "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\
+ "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\
+ "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\
+ "0.129154, 0.344706, 0.641428, 1.252134, 2.482563");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\
+ "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\
+ "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\
+ "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\
+ "0.586152, 0.701486, 0.812865, 1.016083, 1.422518");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\
+ "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\
+ "0.046348, 0.191554, 0.388300, 0.759979, 1.504623");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\
+ "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\
+ "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\
+ "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\
+ "0.575742, 0.790814, 0.966163, 1.286341, 1.926697");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\
+ "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\
+ "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\
+ "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\
+ "0.129154, 0.344706, 0.641428, 1.252134, 2.473548");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\
+ "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\
+ "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\
+ "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\
+ "0.586152, 0.701486, 0.812865, 1.016083, 1.422518");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011");
+ values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\
+ "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\
+ "0.046348, 0.191554, 0.386818, 0.759420, 1.504623");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\
+ "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\
+ "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\
+ "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\
+ "0.827149, 0.779820, 0.749512, 0.738085, 0.751291");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\
+ "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\
+ "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\
+ "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\
+ "0.935354, 0.860120, 0.792428, 0.770222, 0.840039");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\
+ "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\
+ "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\
+ "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\
+ "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\
+ "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\
+ "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\
+ "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\
+ "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092");
+ }
+
+ } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_hldr*/
+
+} /* end of pin sprom_rm_o[0] */
+} /* end of bus sprom_rm_o */
+bus ( dft_scan_md_o ) {
+
+ bus_type : BUS4_type6 ;
+ direction : output ;
+
+pin("dft_scan_md_o[3]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003517 ;
+
+ /* Other user defined attributes. */
+ original_pin : dft_scan_md_o[3];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713");
+ values ( "0.133436, 0.291149, 0.448015, 0.761558, 1.388635",\
+ "0.217239, 0.374877, 0.531734, 0.845677, 1.473578",\
+ "0.292722, 0.450435, 0.607370, 0.921610, 1.550114",\
+ "0.345414, 0.503270, 0.660387, 0.974530, 1.602811",\
+ "0.613422, 0.771515, 0.928749, 1.242027, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713");
+ values ( "0.066308, 0.363809, 0.664826, 1.265395, 2.466601",\
+ "0.066379, 0.363809, 0.664826, 1.265395, 2.466601",\
+ "0.066379, 0.364085, 0.666054, 1.266438, 2.466601",\
+ "0.066379, 0.364085, 0.666054, 1.266438, 2.466601",\
+ "0.066665, 0.364152, 0.666054, 1.266438, 2.466601");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713");
+ values ( "0.114669, 0.217180, 0.316410, 0.514247, 0.909878",\
+ "0.195349, 0.297552, 0.396278, 0.593860, 0.989031",\
+ "0.275060, 0.377342, 0.475886, 0.672942, 1.067052",\
+ "0.331983, 0.434648, 0.533289, 0.730356, 1.124476",\
+ "0.627120, 0.733734, 0.832492, 1.029975, 1.424937");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713");
+ values ( "0.047862, 0.221071, 0.402991, 0.762572, 1.481727",\
+ "0.048050, 0.221071, 0.402991, 0.762572, 1.484038",\
+ "0.048841, 0.221071, 0.402991, 0.762572, 1.484038",\
+ "0.050174, 0.221071, 0.402991, 0.762572, 1.484038",\
+ "0.063454, 0.223134, 0.402991, 0.763435, 1.490666");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713");
+ values ( "0.133312, 0.291022, 0.447820, 0.761354, 1.388420",\
+ "0.217237, 0.374875, 0.531731, 0.845675, 1.473578",\
+ "0.292688, 0.450412, 0.607364, 0.921580, 1.550030",\
+ "0.345261, 0.502988, 0.659849, 0.973849, 1.601865",\
+ "0.613232, 0.771275, 0.928568, 1.241507, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713");
+ values ( "0.066239, 0.363467, 0.663180, 1.263144, 2.462725",\
+ "0.066251, 0.363467, 0.663180, 1.263144, 2.462725",\
+ "0.066251, 0.363585, 0.663361, 1.263144, 2.462725",\
+ "0.066330, 0.363585, 0.663361, 1.263144, 2.462725",\
+ "0.066585, 0.363585, 0.663361, 1.263144, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713");
+ values ( "0.114669, 0.217179, 0.316406, 0.514185, 0.909696",\
+ "0.195349, 0.297552, 0.396278, 0.593860, 0.989031",\
+ "0.275060, 0.377342, 0.475886, 0.672905, 1.066937",\
+ "0.331983, 0.434648, 0.533289, 0.730334, 1.124409",\
+ "0.627120, 0.733671, 0.832318, 1.029654, 1.424330");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713");
+ values ( "0.047860, 0.219783, 0.399450, 0.759952, 1.480082",\
+ "0.047983, 0.219783, 0.399450, 0.759952, 1.480442",\
+ "0.048841, 0.219783, 0.399450, 0.759952, 1.480924",\
+ "0.050169, 0.219999, 0.399514, 0.759952, 1.480924",\
+ "0.063451, 0.222984, 0.400129, 0.761188, 1.483772");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.066308, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.460686, 0.485165, 0.562988, 0.630573, 1.061400",\
+ "0.481673, 0.506153, 0.583976, 0.651561, 1.082387",\
+ "0.534849, 0.559328, 0.637151, 0.704736, 1.135562",\
+ "0.617824, 0.642303, 0.720126, 0.787711, 1.218538",\
+ "0.947556, 0.972173, 1.049996, 1.117581, 1.548407");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.047862, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.457000, 0.374371, 0.299229, 0.265511, 0.232819",\
+ "0.477245, 0.394617, 0.319474, 0.285756, 0.253064",\
+ "0.547749, 0.465121, 0.389978, 0.356260, 0.323568",\
+ "0.640993, 0.558364, 0.483222, 0.449504, 0.416811",\
+ "1.063337, 0.980709, 0.905566, 0.871848, 0.839156");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.066239, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.335865, -0.312869, -0.277184, -0.251910, -0.123825",\
+ "-0.356827, -0.333831, -0.298147, -0.272873, -0.144787",\
+ "-0.410399, -0.387403, -0.351719, -0.326444, -0.198359",\
+ "-0.492968, -0.469972, -0.434287, -0.409013, -0.280927",\
+ "-0.820618, -0.797635, -0.761950, -0.736676, -0.608590");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.047860, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.242066, -0.200653, -0.167936, -0.130741, 0.097416",\
+ "-0.262424, -0.221011, -0.188294, -0.151099, 0.077058",\
+ "-0.336018, -0.294606, -0.261888, -0.224693, 0.003464",\
+ "-0.427308, -0.385895, -0.353178, -0.315983, -0.087826",\
+ "-0.831346, -0.789933, -0.757216, -0.720060, -0.491903");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_hldr*/
+
+} /* end of pin dft_scan_md_o[3] */
+
+pin("dft_scan_md_o[2]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002946 ;
+
+ /* Other user defined attributes. */
+ original_pin : dft_scan_md_o[2];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177");
+ values ( "0.089185, 0.209900, 0.411017, 0.726230, 1.356390",\
+ "0.176530, 0.297275, 0.498423, 0.814441, 1.446276",\
+ "0.269642, 0.392143, 0.593017, 0.908861, 1.540369",\
+ "0.337617, 0.463374, 0.664040, 0.979619, 1.610599",\
+ "0.699386, 0.858557, 1.060886, 1.375366, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177");
+ values ( "0.068736, 0.284281, 0.666318, 1.270003, 2.477274",\
+ "0.069806, 0.284281, 0.666318, 1.270003, 2.477274",\
+ "0.079825, 0.285836, 0.666318, 1.270003, 2.477473",\
+ "0.092727, 0.288939, 0.666318, 1.270003, 2.478527",\
+ "0.183999, 0.330916, 0.673768, 1.274123, 2.479640");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177");
+ values ( "0.114548, 0.198291, 0.327841, 0.529548, 0.932669",\
+ "0.202420, 0.286233, 0.415819, 0.617532, 1.020660",\
+ "0.283719, 0.367201, 0.496624, 0.698334, 1.101477",\
+ "0.341605, 0.425242, 0.554619, 0.756211, 1.159115",\
+ "0.647553, 0.733958, 0.863532, 1.064748, 1.466840");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177");
+ values ( "0.059272, 0.178664, 0.407996, 0.776762, 1.514808",\
+ "0.059349, 0.178981, 0.409509, 0.776762, 1.514808",\
+ "0.059349, 0.178981, 0.409796, 0.777827, 1.514808",\
+ "0.059903, 0.178981, 0.409796, 0.777827, 1.514808",\
+ "0.069603, 0.181400, 0.409796, 0.777827, 1.514808");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[2]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177");
+ values ( "0.089178, 0.209899, 0.411017, 0.726223, 1.356368",\
+ "0.176530, 0.297223, 0.498130, 0.813320, 1.443459",\
+ "0.269641, 0.392139, 0.592998, 0.908848, 1.540369",\
+ "0.337615, 0.463370, 0.664029, 0.979611, 1.610599",\
+ "0.699305, 0.858522, 1.060836, 1.375332, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177");
+ values ( "0.068736, 0.284090, 0.664476, 1.268786, 2.477107",\
+ "0.069799, 0.284090, 0.664476, 1.268786, 2.477170",\
+ "0.079823, 0.285806, 0.664476, 1.268786, 2.477473",\
+ "0.092726, 0.288922, 0.664476, 1.268786, 2.478218",\
+ "0.183999, 0.330234, 0.669979, 1.271116, 2.478674");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177");
+ values ( "0.114547, 0.198291, 0.327841, 0.529547, 0.932665",\
+ "0.202385, 0.286186, 0.415735, 0.617437, 1.020546",\
+ "0.283468, 0.366941, 0.496348, 0.698061, 1.101213",\
+ "0.341452, 0.425085, 0.554450, 0.756012, 1.158853",\
+ "0.647498, 0.733909, 0.863481, 1.064711, 1.466833");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177");
+ values ( "0.059268, 0.178282, 0.407986, 0.775351, 1.510125",\
+ "0.059268, 0.178282, 0.408103, 0.775351, 1.510125",\
+ "0.059268, 0.178282, 0.408103, 0.775351, 1.510553",\
+ "0.059897, 0.178402, 0.408103, 0.775351, 1.510553",\
+ "0.069562, 0.181271, 0.408103, 0.775351, 1.510553");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[2]_redg_min*/
+
+} /* end of pin dft_scan_md_o[2] */
+
+pin("dft_scan_md_o[1]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.158177 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.002940 ;
+
+ /* Other user defined attributes. */
+ original_pin : dft_scan_md_o[1];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177");
+ values ( "0.089114, 0.209844, 0.410975, 0.726203, 1.356391",\
+ "0.176459, 0.297219, 0.498381, 0.814414, 1.446276",\
+ "0.269560, 0.392087, 0.592975, 0.908833, 1.540369",\
+ "0.337521, 0.463318, 0.663998, 0.979591, 1.610599",\
+ "0.699205, 0.858501, 1.060843, 1.375339, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177");
+ values ( "0.068629, 0.284175, 0.666239, 1.269949, 2.477274",\
+ "0.069702, 0.284175, 0.666239, 1.269949, 2.477274",\
+ "0.079734, 0.285730, 0.666239, 1.269949, 2.477474",\
+ "0.092637, 0.288835, 0.666239, 1.269949, 2.478527",\
+ "0.183880, 0.330821, 0.673696, 1.274070, 2.479641");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177");
+ values ( "0.114532, 0.198282, 0.327841, 0.529557, 0.932695",\
+ "0.202404, 0.286224, 0.415819, 0.617541, 1.020687",\
+ "0.283703, 0.367192, 0.496624, 0.698343, 1.101503",\
+ "0.341588, 0.425233, 0.554619, 0.756220, 1.159141",\
+ "0.647534, 0.733949, 0.863532, 1.064757, 1.466866");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177");
+ values ( "0.059254, 0.178648, 0.407996, 0.776778, 1.514857",\
+ "0.059330, 0.178965, 0.409508, 0.776778, 1.514857",\
+ "0.059330, 0.178965, 0.409796, 0.777843, 1.514857",\
+ "0.059885, 0.178965, 0.409796, 0.777843, 1.514857",\
+ "0.069589, 0.181384, 0.409796, 0.777843, 1.514857");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[1]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177");
+ values ( "0.089108, 0.209843, 0.410975, 0.726196, 1.356369",\
+ "0.176459, 0.297167, 0.498088, 0.813292, 1.443459",\
+ "0.269559, 0.392083, 0.592956, 0.908820, 1.540369",\
+ "0.337519, 0.463314, 0.663987, 0.979583, 1.610599",\
+ "0.699124, 0.858466, 1.060793, 1.375304, 2.003839");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177");
+ values ( "0.068628, 0.283984, 0.664398, 1.268733, 2.477107",\
+ "0.069695, 0.283984, 0.664398, 1.268733, 2.477171",\
+ "0.079731, 0.285701, 0.664398, 1.268733, 2.477474",\
+ "0.092635, 0.288817, 0.664398, 1.268733, 2.478218",\
+ "0.183880, 0.330139, 0.669908, 1.271063, 2.478675");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177");
+ values ( "0.114530, 0.198282, 0.327841, 0.529556, 0.932692",\
+ "0.202368, 0.286177, 0.415735, 0.617446, 1.020573",\
+ "0.283452, 0.366932, 0.496348, 0.698070, 1.101240",\
+ "0.341435, 0.425076, 0.554450, 0.756020, 1.158880",\
+ "0.647479, 0.733900, 0.863481, 1.064720, 1.466859");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177");
+ values ( "0.059249, 0.178266, 0.407986, 0.775367, 1.510173",\
+ "0.059249, 0.178266, 0.408103, 0.775367, 1.510173",\
+ "0.059249, 0.178266, 0.408103, 0.775367, 1.510602",\
+ "0.059879, 0.178385, 0.408103, 0.775367, 1.510602",\
+ "0.069548, 0.181255, 0.408103, 0.775367, 1.510602");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[1]_redg_min*/
+
+} /* end of pin dft_scan_md_o[1] */
+
+pin("dft_scan_md_o[0]") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.161713 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.003291 ;
+
+ /* Other user defined attributes. */
+ original_pin : dft_scan_md_o[0];
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713");
+ values ( "0.131615, 0.289575, 0.446666, 0.760660, 1.388635",\
+ "0.215420, 0.373304, 0.530386, 0.844778, 1.473578",\
+ "0.290903, 0.448861, 0.606021, 0.920710, 1.550114",\
+ "0.343593, 0.501694, 0.659036, 0.973630, 1.602811",\
+ "0.611596, 0.769938, 0.927397, 1.241129, 1.868510");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713");
+ values ( "0.062950, 0.360790, 0.662238, 1.263674, 2.466600",\
+ "0.063013, 0.360790, 0.662238, 1.263674, 2.466600",\
+ "0.063013, 0.361056, 0.663457, 1.264718, 2.466600",\
+ "0.063013, 0.361056, 0.663457, 1.264718, 2.466600",\
+ "0.063304, 0.361135, 0.663457, 1.264718, 2.466600");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713");
+ values ( "0.113407, 0.216311, 0.315683, 0.513806, 0.910003",\
+ "0.194085, 0.296687, 0.395555, 0.593419, 0.989157",\
+ "0.273778, 0.376478, 0.475164, 0.672502, 1.067177",\
+ "0.330670, 0.433783, 0.532566, 0.729916, 1.124601",\
+ "0.625514, 0.732868, 0.831768, 1.029534, 1.425062");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713");
+ values ( "0.046113, 0.219478, 0.401657, 0.761769, 1.481954",\
+ "0.046300, 0.219478, 0.401657, 0.761769, 1.484267",\
+ "0.047120, 0.219478, 0.401657, 0.761769, 1.484267",\
+ "0.048485, 0.219478, 0.401657, 0.761769, 1.484267",\
+ "0.061963, 0.221582, 0.401657, 0.762623, 1.490896");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713");
+ values ( "0.131490, 0.289449, 0.446472, 0.760456, 1.388420",\
+ "0.215418, 0.373302, 0.530383, 0.844776, 1.473578",\
+ "0.290869, 0.448838, 0.606015, 0.920679, 1.550029",\
+ "0.343439, 0.501415, 0.658500, 0.972949, 1.601865",\
+ "0.611409, 0.769697, 0.927216, 1.240610, 1.867283");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713");
+ values ( "0.062879, 0.360460, 0.660603, 1.261425, 2.462725",\
+ "0.062899, 0.360460, 0.660603, 1.261425, 2.462725",\
+ "0.062899, 0.360578, 0.660783, 1.261425, 2.462725",\
+ "0.062968, 0.360578, 0.660783, 1.261425, 2.462725",\
+ "0.063222, 0.360578, 0.660783, 1.261425, 2.462725");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713");
+ values ( "0.113407, 0.216309, 0.315678, 0.513743, 0.909821",\
+ "0.194085, 0.296687, 0.395555, 0.593419, 0.989157",\
+ "0.273778, 0.376478, 0.475164, 0.672465, 1.067062",\
+ "0.330670, 0.433783, 0.532566, 0.729894, 1.124533",\
+ "0.625514, 0.732807, 0.831595, 1.029214, 1.424455");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713");
+ values ( "0.046112, 0.218208, 0.398133, 0.759147, 1.480310",\
+ "0.046235, 0.218208, 0.398133, 0.759147, 1.480670",\
+ "0.047116, 0.218208, 0.398133, 0.759147, 1.481152",\
+ "0.048480, 0.218425, 0.398198, 0.759147, 1.481152",\
+ "0.061948, 0.221432, 0.398830, 0.760382, 1.484000");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.062950, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.468253, 0.492732, 0.570555, 0.638140, 1.068967",\
+ "0.490044, 0.514523, 0.592346, 0.659931, 1.090757",\
+ "0.545368, 0.569847, 0.647670, 0.715255, 1.146082",\
+ "0.634688, 0.659168, 0.736991, 0.804576, 1.235402",\
+ "1.017271, 1.041743, 1.119566, 1.187151, 1.617977");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.046113, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.459602, 0.376973, 0.301830, 0.268113, 0.235420",\
+ "0.477883, 0.395254, 0.320112, 0.286394, 0.253701",\
+ "0.549719, 0.467091, 0.391948, 0.358230, 0.325538",\
+ "0.644311, 0.561683, 0.486540, 0.452822, 0.420130",\
+ "1.067339, 0.984711, 0.909568, 0.875850, 0.843158");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_stupr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.062879, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.343432, -0.320436, -0.284752, -0.259478, -0.131392",\
+ "-0.365195, -0.342199, -0.306515, -0.281240, -0.153155",\
+ "-0.420715, -0.397719, -0.362035, -0.336760, -0.208675",\
+ "-0.509827, -0.486831, -0.451147, -0.425873, -0.297787",\
+ "-0.891088, -0.868095, -0.832410, -0.807136, -0.679050");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.046112, 0.195118, 0.455354, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.244757, -0.203344, -0.170627, -0.133432, 0.094725",\
+ "-0.263038, -0.221625, -0.188908, -0.151713, 0.076444",\
+ "-0.337776, -0.296363, -0.263646, -0.226451, 0.001706",\
+ "-0.430900, -0.389488, -0.356770, -0.319575, -0.091418",\
+ "-0.836348, -0.794936, -0.762218, -0.725057, -0.496900");
+ }
+
+ } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_hldr*/
+
+} /* end of pin dft_scan_md_o[0] */
+} /* end of bus dft_scan_md_o */
+
+pin("scan_shift_en_o") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.095084 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.028179 ;
+
+ /* Other user defined attributes. */
+ original_pin : scan_shift_en_o;
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.532219, 0.489613, 0.431727, 0.435127, 0.476450",\
+ "0.639994, 0.597388, 0.539502, 0.542902, 0.584225",\
+ "0.783455, 0.740849, 0.682963, 0.686363, 0.727686",\
+ "0.930263, 0.887658, 0.829771, 0.833171, 0.874494",\
+ "1.623874, 1.581268, 1.523381, 1.526781, 1.568104");
+ }
+
+ } /* end of arc clk_ast_alert_i_scan_shift_en_o_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "0.043626, 0.100485, 0.237779, 0.265545, 0.602978",\
+ "-0.038691, 0.018168, 0.155463, 0.183228, 0.520661",\
+ "-0.121016, -0.064151, 0.072977, 0.100718, 0.437847",\
+ "-0.190085, -0.133213, 0.003667, 0.031370, 0.368047",\
+ "-0.499886, -0.442913, -0.307440, -0.279961, 0.053979");
+ }
+
+ } /* end of arc clk_ast_alert_i_scan_shift_en_o_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : setup_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.063826, 0.062652, 0.129143, 0.282266, 0.638582",\
+ "0.144516, 0.122873, 0.153635, 0.250761, 0.490135",\
+ "0.243845, 0.203218, 0.197002, 0.225868, 0.314993",\
+ "0.333420, 0.283466, 0.260028, 0.260578, 0.289579",\
+ "0.742571, 0.680072, 0.640181, 0.639634, 0.684785");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.484230, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.069804, -0.018648, -0.111764, -0.244874, -0.513274",\
+ "0.147065, 0.058673, -0.032069, -0.165383, -0.437145",\
+ "0.257633, 0.169188, 0.076752, -0.058192, -0.332590",\
+ "0.419789, 0.332087, 0.238963, 0.102061, -0.177084",\
+ "0.794358, 0.708802, 0.615035, 0.473837, 0.183265");
+ }
+
+ } /* end of arc clk_ast_ext_i_scan_shift_en_o_cgsr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : hold_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.041482, 0.004889, 0.044867, 0.102673, 0.219769",\
+ "-0.121636, -0.074743, -0.032444, 0.026924, 0.145736",\
+ "-0.213199, -0.163583, -0.120926, -0.060090, 0.062464",\
+ "-0.289736, -0.238766, -0.195667, -0.134080, -0.009915",\
+ "-0.654569, -0.601430, -0.555559, -0.492609, -0.367822");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.476372, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.044121, 0.037282, 0.129537, 0.261976, 0.529485",\
+ "-0.122275, -0.038844, 0.049184, 0.181641, 0.454147",\
+ "-0.228703, -0.144549, -0.055160, 0.079110, 0.355165",\
+ "-0.387423, -0.304473, -0.214026, -0.077712, 0.202895",\
+ "-0.744719, -0.665813, -0.573547, -0.433021, -0.142598");
+ }
+
+ } /* end of arc clk_ast_ext_i_scan_shift_en_o_cghr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "380000.437500, 380000.468750, 380000.531250, 380000.812500, 380001.312500",\
+ "380000.531250, 380000.562500, 380000.625000, 380000.906250, 380001.406250",\
+ "380000.593750, 380000.625000, 380000.687500, 380000.968750, 380001.468750",\
+ "380000.656250, 380000.687500, 380000.750000, 380001.031250, 380001.531250",\
+ "380000.968750, 380001.000000, 380001.062500, 380001.343750, 380001.843750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "380001.750000, 380001.781250, 380001.843750, 380002.031250, 380002.375000",\
+ "380001.843750, 380001.875000, 380001.937500, 380002.125000, 380002.468750",\
+ "380001.937500, 380001.968750, 380002.031250, 380002.218750, 380002.562500",\
+ "380002.000000, 380002.031250, 380002.093750, 380002.281250, 380002.625000",\
+ "380002.343750, 380002.375000, 380002.437500, 380002.625000, 380002.968750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.476972, 0.520642, 0.623430, 0.968675, 1.632439",\
+ "0.476972, 0.520642, 0.623430, 0.968675, 1.632439",\
+ "0.476984, 0.520655, 0.623442, 0.968683, 1.632439",\
+ "0.477092, 0.520773, 0.623551, 0.968760, 1.632439",\
+ "0.477240, 0.520936, 0.623729, 0.968990, 1.632439");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_shift_en_o_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.567867, 0.601968, 0.682377, 0.952454, 1.470934",\
+ "0.656009, 0.690105, 0.770491, 1.040492, 1.558825",\
+ "0.750333, 0.784422, 0.864790, 1.134732, 1.652952",\
+ "0.817746, 0.851834, 0.932210, 1.202178, 1.720448",\
+ "1.177034, 1.211190, 1.291747, 1.562319, 2.081752");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.742023, 0.806942, 0.960129, 1.473159, 2.454133",\
+ "0.742023, 0.806942, 0.960129, 1.473159, 2.454133",\
+ "0.742023, 0.806942, 0.960129, 1.473554, 2.458020",\
+ "0.742023, 0.806942, 0.960129, 1.474655, 2.462414",\
+ "0.742023, 0.806942, 0.960129, 1.474655, 2.462414");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.436555, 0.460383, 0.516602, 0.705431, 1.067936",\
+ "0.524364, 0.548192, 0.604409, 0.793229, 1.155716",\
+ "0.605651, 0.629479, 0.685698, 0.874530, 1.237040",\
+ "0.663776, 0.687602, 0.743831, 0.932696, 1.295270",\
+ "0.971918, 0.995743, 1.051944, 1.240713, 1.603103");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.476372, 0.519944, 0.622887, 0.968653, 1.631455",\
+ "0.476372, 0.519944, 0.622887, 0.968653, 1.631455",\
+ "0.476372, 0.519944, 0.622887, 0.968653, 1.631461",\
+ "0.476372, 0.519944, 0.622887, 0.968653, 1.631478",\
+ "0.476373, 0.519944, 0.622887, 0.968653, 1.631806");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_shift_en_o_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "1.025280, 0.973708, 0.938980, 0.927998, 0.968803",\
+ "1.133724, 1.082152, 1.047424, 1.036442, 1.077247",\
+ "1.276742, 1.225171, 1.190443, 1.179460, 1.220266",\
+ "1.421700, 1.370129, 1.335400, 1.324418, 1.365223",\
+ "2.112985, 2.061414, 2.026685, 2.015703, 2.056509");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_shift_en_o_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.484807, -0.401976, -0.317025, -0.255738, 0.062771",\
+ "-0.593251, -0.510420, -0.425469, -0.364182, -0.045673",\
+ "-0.735922, -0.653091, -0.568140, -0.506853, -0.188344",\
+ "-0.871661, -0.788831, -0.703879, -0.642593, -0.324084",\
+ "-1.567978, -1.485147, -1.400195, -1.338909, -1.020400");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_shift_en_o_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : setup_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.500052, 0.464257, 0.467454, 0.481872, 0.641062",\
+ "0.608496, 0.572702, 0.575898, 0.590317, 0.749506",\
+ "0.751349, 0.715408, 0.718319, 0.732500, 0.890238",\
+ "0.895828, 0.859887, 0.862797, 0.876979, 1.034717",\
+ "1.584854, 1.547746, 1.548384, 1.560677, 1.706875");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.484230, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "0.472376, 0.383961, 0.292457, 0.226602, -0.114540",\
+ "0.571622, 0.483207, 0.391702, 0.325848, -0.015294",\
+ "0.718823, 0.630408, 0.538891, 0.473029, 0.131864",\
+ "0.967954, 0.879538, 0.787986, 0.722105, 0.380872",\
+ "1.461814, 1.373393, 1.281717, 1.215763, 0.874287");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_shift_en_o_cgsr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : hold_rising ;
+ clock_gating_flag : true ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.471383, -0.422460, -0.379894, -0.349813, -0.197830",\
+ "-0.579827, -0.530904, -0.488339, -0.458257, -0.306274",\
+ "-0.722620, -0.673676, -0.631108, -0.601022, -0.449003",\
+ "-0.858078, -0.809134, -0.766565, -0.736479, -0.584461",\
+ "-1.555647, -1.506536, -1.463946, -1.433827, -1.281521");
+ }
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.476372, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.447062, -0.363296, -0.274639, -0.209836, 0.132805",\
+ "-0.546307, -0.462542, -0.373884, -0.309082, 0.033560",\
+ "-0.689363, -0.605598, -0.516940, -0.452138, -0.109496",\
+ "-0.942607, -0.858821, -0.770125, -0.705296, -0.362529",\
+ "-1.436381, -1.352539, -1.263740, -1.198841, -0.855737");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_shift_en_o_cghr*/
+
+ timing () {
+ related_pin : "padmux2ast_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.489833, 0.523915, 0.604311, 0.874343, 1.392737",\
+ "0.566174, 0.600431, 0.681298, 0.952915, 1.474352",\
+ "0.660833, 0.694982, 0.775530, 1.046072, 1.565447",\
+ "0.820966, 0.855139, 0.935773, 1.206609, 1.726547",\
+ "1.095138, 1.129115, 1.209400, 1.479059, 1.996736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.766211, 0.830301, 0.980244, 1.483872, 2.450712",\
+ "0.766211, 0.830301, 0.980244, 1.483872, 2.456399",\
+ "0.766211, 0.830301, 0.980244, 1.483872, 2.457642",\
+ "0.766211, 0.830301, 0.980244, 1.483872, 2.465531",\
+ "0.766211, 0.830301, 0.980244, 1.483872, 2.465531");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.331095, 0.354971, 0.411113, 0.599682, 0.961689",\
+ "0.422338, 0.446186, 0.502618, 0.692160, 1.056035",\
+ "0.529474, 0.553262, 0.609349, 0.797734, 1.159388",\
+ "0.719234, 0.743081, 0.799295, 0.988106, 1.350577",\
+ "1.047647, 1.071864, 1.127881, 1.316028, 1.677225");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\
+ "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\
+ "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\
+ "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\
+ "0.491280, 0.530601, 0.632503, 0.976140, 1.638195");
+ }
+
+ } /* end of arc padmux2ast_i[2]_scan_shift_en_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[2]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.489833, 0.523915, 0.604311, 0.874343, 1.392737",\
+ "0.566174, 0.600431, 0.681298, 0.952915, 1.474352",\
+ "0.660833, 0.694982, 0.775530, 1.046072, 1.565447",\
+ "0.820966, 0.855139, 0.935773, 1.206609, 1.726547",\
+ "1.095138, 1.129115, 1.209400, 1.479059, 1.996736");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.748897, 0.805011, 0.957821, 1.471076, 2.450712",\
+ "0.748897, 0.805011, 0.957821, 1.471076, 2.456399",\
+ "0.748897, 0.811237, 0.965448, 1.477816, 2.457642",\
+ "0.748897, 0.811237, 0.965448, 1.479720, 2.465531",\
+ "0.748897, 0.813325, 0.966210, 1.479720, 2.465531");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.331095, 0.354971, 0.411113, 0.599682, 0.961689",\
+ "0.422338, 0.446186, 0.502618, 0.692160, 1.056035",\
+ "0.529474, 0.553262, 0.609349, 0.797734, 1.159388",\
+ "0.719234, 0.743081, 0.799295, 0.988106, 1.350577",\
+ "1.047647, 1.071864, 1.127881, 1.316028, 1.677225");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.484230, 0.518873, 0.622079, 0.966408, 1.621243",\
+ "0.484230, 0.518873, 0.622079, 0.966408, 1.621243",\
+ "0.484230, 0.518873, 0.622079, 0.968730, 1.631847",\
+ "0.484230, 0.522164, 0.625240, 0.971450, 1.631847",\
+ "0.491280, 0.530601, 0.632503, 0.974773, 1.631847");
+ }
+
+ } /* end of arc padmux2ast_i[2]_scan_shift_en_o_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "380000.312500, 380000.343750, 380000.406250, 380000.687500, 380001.187500",\
+ "380000.406250, 380000.437500, 380000.500000, 380000.781250, 380001.281250",\
+ "380000.500000, 380000.531250, 380000.593750, 380000.875000, 380001.375000",\
+ "380000.656250, 380000.687500, 380000.750000, 380001.031250, 380001.531250",\
+ "380000.906250, 380000.937500, 380001.000000, 380001.281250, 380001.781250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "380001.656250, 380001.687500, 380001.750000, 380001.937500, 380002.281250",\
+ "380001.750000, 380001.781250, 380001.843750, 380002.031250, 380002.375000",\
+ "380001.875000, 380001.906250, 380001.968750, 380002.156250, 380002.500000",\
+ "380002.062500, 380002.093750, 380002.156250, 380002.343750, 380002.687500",\
+ "380002.375000, 380002.406250, 380002.468750, 380002.656250, 380003.000000");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\
+ "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\
+ "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\
+ "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\
+ "0.476385, 0.519957, 0.622899, 0.968661, 1.632439");
+ }
+
+ } /* end of arc padmux2ast_i[4]_scan_shift_en_o_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "380000.312500, 380000.343750, 380000.406250, 380000.687500, 380001.187500",\
+ "380000.406250, 380000.437500, 380000.500000, 380000.781250, 380001.281250",\
+ "380000.468750, 380000.500000, 380000.562500, 380000.843750, 380001.343750",\
+ "380000.625000, 380000.656250, 380000.718750, 380001.000000, 380001.500000",\
+ "380000.843750, 380000.875000, 380000.937500, 380001.218750, 380001.718750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\
+ "0.750971, 0.815816, 0.968419, 1.480978, 2.464965");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "380001.656250, 380001.687500, 380001.750000, 380001.937500, 380002.281250",\
+ "380001.750000, 380001.781250, 380001.843750, 380002.031250, 380002.375000",\
+ "380001.843750, 380001.875000, 380001.937500, 380002.125000, 380002.468750",\
+ "380002.031250, 380002.062500, 380002.125000, 380002.312500, 380002.656250",\
+ "380002.281250, 380002.312500, 380002.375000, 380002.562500, 380002.906250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084");
+ values ( "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\
+ "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\
+ "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\
+ "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\
+ "0.476385, 0.519957, 0.622899, 0.968661, 1.632439");
+ }
+
+ } /* end of arc padmux2ast_i[4]_scan_shift_en_o_una_min*/
+
+} /* end of pin scan_shift_en_o */
+
+pin("scan_reset_no") {
+ direction : output ;
+ max_transition : 2.480000 ;
+ min_transition : 0.000000 ;
+ max_capacitance : 0.044252 ;
+ min_capacitance : 0.000067 ;
+ max_fanout : 50.000000 ;
+ capacitance : 0.021601 ;
+
+ /* Other user defined attributes. */
+ original_pin : scan_reset_no;
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : recovery_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 1.099537, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "1.964051, 1.921426, 1.863863, 1.867343, 1.909642",\
+ "2.060242, 2.017617, 1.960053, 1.963533, 2.005833",\
+ "2.173090, 2.130465, 2.072901, 2.076381, 2.118681",\
+ "2.375021, 2.332396, 2.274832, 2.278312, 2.320612",\
+ "2.686105, 2.643480, 2.585916, 2.589396, 2.631696");
+ }
+
+ } /* end of arc clk_ast_alert_i_scan_reset_no_recfr*/
+
+ timing () {
+ related_pin : "clk_ast_alert_i" ;
+ timing_type : removal_rising ;
+ fall_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 0.898734, 2.480000");
+ index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000");
+ values ( "-1.851924, -1.814471, -1.754913, -1.744727, -1.620931",\
+ "-1.948175, -1.910723, -1.851165, -1.840978, -1.717183",\
+ "-2.061304, -2.023851, -1.964293, -1.954107, -1.830311",\
+ "-2.203395, -2.165943, -2.106384, -2.096198, -1.972402",\
+ "-2.574453, -2.537001, -2.477442, -2.467256, -2.343460");
+ }
+
+ } /* end of arc clk_ast_alert_i_scan_reset_no_remfr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.802143, 0.819742, 0.854125, 0.955681, 1.487746",\
+ "0.890534, 0.908134, 0.942517, 1.044073, 1.576140",\
+ "0.986100, 1.003701, 1.038085, 1.139644, 1.671728",\
+ "1.152159, 1.169761, 1.204148, 1.305714, 1.837840",\
+ "1.418048, 1.435651, 1.470039, 1.571612, 2.103765");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.229517, 1.260918, 1.322264, 1.503458, 2.452761",\
+ "1.229525, 1.260928, 1.322278, 1.503483, 2.452843",\
+ "1.229623, 1.261050, 1.322445, 1.503785, 2.453854",\
+ "1.229849, 1.261330, 1.322831, 1.504483, 2.456189",\
+ "1.230249, 1.261792, 1.323416, 1.505431, 2.459036");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.798583, 0.815273, 0.847880, 0.944189, 1.448769",\
+ "0.886419, 0.903109, 0.935716, 1.032025, 1.536605",\
+ "0.967929, 0.984620, 1.017227, 1.113536, 1.618116",\
+ "1.107256, 1.123946, 1.156553, 1.252862, 1.757442",\
+ "1.334271, 1.350961, 1.383568, 1.479877, 1.984456");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.070623, 1.099479, 1.155855, 1.322366, 2.194748",\
+ "1.070624, 1.099480, 1.155855, 1.322366, 2.194748",\
+ "1.070624, 1.099480, 1.155855, 1.322366, 2.194748",\
+ "1.070624, 1.099480, 1.155855, 1.322366, 2.194752",\
+ "1.070624, 1.099480, 1.155855, 1.322366, 2.194762");
+ }
+
+ } /* end of arc clk_ast_ext_i_scan_reset_no_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.802125, 0.819724, 0.854108, 0.955663, 1.487728",\
+ "0.890342, 0.907941, 0.942325, 1.043880, 1.575947",\
+ "0.986099, 1.003699, 1.038084, 1.139642, 1.671727",\
+ "1.152155, 1.169757, 1.204144, 1.305710, 1.837835",\
+ "1.417944, 1.435547, 1.469935, 1.571508, 2.103662");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.229517, 1.260918, 1.322264, 1.503458, 2.452760",\
+ "1.229525, 1.260928, 1.322278, 1.503482, 2.452842",\
+ "1.229623, 1.261050, 1.322445, 1.503785, 2.453854",\
+ "1.229849, 1.261330, 1.322831, 1.504483, 2.456189",\
+ "1.230248, 1.261792, 1.323416, 1.505430, 2.459036");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.798579, 0.815269, 0.847876, 0.944185, 1.448765",\
+ "0.886379, 0.903069, 0.935677, 1.031986, 1.536566",\
+ "0.967658, 0.984348, 1.016956, 1.113265, 1.617844",\
+ "1.107229, 1.123919, 1.156526, 1.252835, 1.757415",\
+ "1.334205, 1.350896, 1.383503, 1.479811, 1.984390");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.070600, 1.099457, 1.155835, 1.322351, 2.194748",\
+ "1.070600, 1.099457, 1.155835, 1.322351, 2.194748",\
+ "1.070600, 1.099457, 1.155835, 1.322351, 2.194748",\
+ "1.070600, 1.099457, 1.155835, 1.322351, 2.194752",\
+ "1.070600, 1.099457, 1.155835, 1.322351, 2.194762");
+ }
+
+ } /* end of arc clk_ast_ext_i_scan_reset_no_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 1.230133, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "3.588611, 3.540715, 3.506416, 3.500099, 3.522348",\
+ "3.671103, 3.623207, 3.588908, 3.582592, 3.604841",\
+ "3.766086, 3.718189, 3.683890, 3.677574, 3.699822",\
+ "3.975284, 3.927388, 3.893089, 3.886772, 3.909021",\
+ "4.236159, 4.188263, 4.153964, 4.147648, 4.169896");
+ }
+
+ } /* end of arc clk_ast_ext_i_scan_reset_no_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : recovery_falling ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 1.230133, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "0.254411, 0.254411, 0.254411, 0.254411, 0.254411",\
+ "0.332233, 0.332233, 0.332233, 0.332233, 0.332233",\
+ "0.412826, 0.412826, 0.412826, 0.412826, 0.412826",\
+ "0.584722, 0.584722, 0.584722, 0.584722, 0.584722",\
+ "0.796290, 0.796290, 0.796290, 0.796290, 0.796290");
+ }
+
+ } /* end of arc clk_ast_ext_i_scan_reset_no_recrf*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.591561, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.156602, -0.106021, -0.062437, -0.009182, 0.090788",\
+ "-0.234424, -0.183844, -0.140259, -0.087005, 0.012965",\
+ "-0.347653, -0.297234, -0.253546, -0.200284, -0.100415",\
+ "-0.457700, -0.407414, -0.363694, -0.310440, -0.210630",\
+ "-0.693682, -0.643595, -0.600273, -0.547145, -0.447229");
+ }
+
+ } /* end of arc clk_ast_ext_i_scan_reset_no_remrr*/
+
+ timing () {
+ related_pin : "clk_ast_ext_i" ;
+ timing_type : removal_falling ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.591561, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ values ( "-0.072639, -0.072639, -0.072639, -0.072639, -0.072639",\
+ "-0.150732, -0.150732, -0.150732, -0.150732, -0.150732",\
+ "-0.261960, -0.261960, -0.261960, -0.261960, -0.261960",\
+ "-0.368573, -0.368573, -0.368573, -0.368573, -0.368573",\
+ "-0.585347, -0.585347, -0.585347, -0.585347, -0.585347");
+ }
+
+ } /* end of arc clk_ast_ext_i_scan_reset_no_remrf*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "380001.750000, 380001.750000, 380001.750000, 380001.812500, 380002.062500",\
+ "380001.843750, 380001.843750, 380001.843750, 380001.906250, 380002.156250",\
+ "380001.937500, 380001.937500, 380001.937500, 380002.000000, 380002.250000",\
+ "380002.000000, 380002.000000, 380002.000000, 380002.062500, 380002.312500",\
+ "380002.343750, 380002.343750, 380002.343750, 380002.406250, 380002.656250");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.229646, 1.261078, 1.322484, 1.503854, 2.454086",\
+ "1.229646, 1.261078, 1.322484, 1.503854, 2.454086",\
+ "1.229646, 1.261078, 1.322484, 1.503854, 2.454086",\
+ "1.229646, 1.261078, 1.322484, 1.503855, 2.454087",\
+ "1.229648, 1.261080, 1.322487, 1.503860, 2.454105");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "380000.593750, 380000.593750, 380000.625000, 380000.718750, 380001.250000",\
+ "380000.687500, 380000.687500, 380000.718750, 380000.812500, 380001.343750",\
+ "380000.750000, 380000.750000, 380000.781250, 380000.875000, 380001.406250",\
+ "380000.812500, 380000.812500, 380000.843750, 380000.937500, 380001.468750",\
+ "380001.125000, 380001.125000, 380001.156250, 380001.250000, 380001.781250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\
+ "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\
+ "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\
+ "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\
+ "1.099064, 1.128619, 1.186359, 1.356900, 2.250939");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_reset_no_redg*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : rising_edge ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.422873, 0.430902, 0.446588, 0.492920, 0.735645",\
+ "0.510672, 0.518701, 0.534387, 0.580719, 0.823446",\
+ "0.591965, 0.599994, 0.615680, 0.662012, 0.904736",\
+ "0.650145, 0.658174, 0.673861, 0.720193, 0.962908",\
+ "0.958388, 0.966413, 0.982090, 1.028394, 1.270988");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.591561, 0.606759, 0.636466, 0.724197, 1.183709",\
+ "0.591561, 0.606759, 0.636466, 0.724197, 1.183709",\
+ "0.591563, 0.606768, 0.636472, 0.724197, 1.183709",\
+ "0.591595, 0.606795, 0.636489, 0.724197, 1.183709",\
+ "0.591849, 0.607055, 0.636761, 0.724504, 1.184204");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.601971, 0.615882, 0.643058, 0.723326, 1.143863",\
+ "0.689980, 0.703892, 0.731069, 0.811342, 1.231904",\
+ "0.785109, 0.799012, 0.826172, 0.906394, 1.326690",\
+ "0.853674, 0.867567, 0.894707, 0.974869, 1.394853",\
+ "1.216942, 1.230863, 1.258059, 1.338388, 1.759243");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.898014, 0.922343, 0.969635, 1.108981, 1.838479",\
+ "0.898014, 0.922343, 0.969635, 1.108981, 1.838479",\
+ "0.898014, 0.922343, 0.969635, 1.108981, 1.839038",\
+ "0.898014, 0.922343, 0.969800, 1.109378, 1.840651",\
+ "0.898014, 0.922343, 0.969873, 1.110259, 1.842156");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_reset_no_redg_min*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : recovery_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.455354, 1.230133, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "1.415613, 1.363816, 1.325401, 1.311644, 1.337231",\
+ "1.501586, 1.449789, 1.411374, 1.397617, 1.423205",\
+ "1.612727, 1.560930, 1.522515, 1.508758, 1.534346",\
+ "1.834322, 1.782526, 1.744110, 1.730354, 1.755941",\
+ "2.101753, 2.049956, 2.011540, 1.997784, 2.023371");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_reset_no_recrr*/
+
+ timing () {
+ related_pin : "clk_ast_tlul_i" ;
+ timing_type : removal_rising ;
+ rise_constraint( f_dtrans_ctrans ){
+ index_1 ( "0.006578, 0.195118, 0.591561, 1.062676, 2.480000");
+ index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000");
+ values ( "-0.697532, -0.650599, -0.616529, -0.592387, -0.469972",\
+ "-0.783374, -0.736441, -0.702370, -0.678229, -0.555814",\
+ "-0.939179, -0.892246, -0.858175, -0.834034, -0.711619",\
+ "-1.080269, -1.033336, -0.999265, -0.975124, -0.852709",\
+ "-1.378594, -1.331661, -1.297591, -1.273450, -1.151034");
+ }
+
+ } /* end of arc clk_ast_tlul_i_scan_reset_no_remrr*/
+
+ timing () {
+ related_pin : "padmux2ast_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.726887, 0.744473, 0.778830, 0.880309, 1.411971",\
+ "0.813994, 0.831587, 0.865957, 0.967473, 1.499333",\
+ "0.895839, 0.913433, 0.947805, 1.049329, 1.581226",\
+ "1.037802, 1.055400, 1.089781, 1.191329, 1.723358",\
+ "1.277047, 1.294652, 1.329045, 1.430630, 1.962853");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.230133, 1.261577, 1.323007, 1.504448, 2.455048",\
+ "1.230133, 1.261577, 1.323007, 1.504448, 2.455048",\
+ "1.230191, 1.261616, 1.323008, 1.504448, 2.455048",\
+ "1.230748, 1.262222, 1.323711, 1.505326, 2.455673",\
+ "1.230748, 1.262222, 1.323711, 1.505326, 2.455673");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.683808, 0.700926, 0.734366, 0.833138, 1.350622",\
+ "0.774648, 0.791774, 0.825231, 0.924052, 1.441793",\
+ "0.860296, 0.877424, 0.910885, 1.009716, 1.527510",\
+ "1.010613, 1.027735, 1.061184, 1.159981, 1.677597",\
+ "1.262256, 1.279377, 1.312826, 1.411619, 1.929216");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\
+ "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\
+ "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\
+ "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\
+ "1.099652, 1.129190, 1.186897, 1.357342, 2.250541");
+ }
+
+ } /* end of arc padmux2ast_i[3]_scan_reset_no_una*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[3]" ;
+ timing_type : combinational ;
+ timing_sense : positive_unate ;
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.726887, 0.744473, 0.778830, 0.880309, 1.411971",\
+ "0.813994, 0.831587, 0.865957, 0.967473, 1.499333",\
+ "0.895839, 0.913433, 0.947805, 1.049329, 1.581226",\
+ "1.037802, 1.055400, 1.089781, 1.191329, 1.723358",\
+ "1.277047, 1.294652, 1.329045, 1.430630, 1.962853");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.230133, 1.260882, 1.322288, 1.503659, 2.453893",\
+ "1.230133, 1.260882, 1.322288, 1.503659, 2.453893",\
+ "1.230191, 1.261616, 1.323008, 1.504337, 2.454350",\
+ "1.230581, 1.262030, 1.323468, 1.504936, 2.455673",\
+ "1.230581, 1.262030, 1.323468, 1.504936, 2.455673");
+ }
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.683808, 0.700926, 0.734366, 0.833138, 1.350622",\
+ "0.774648, 0.791774, 0.825231, 0.924052, 1.441793",\
+ "0.860296, 0.877424, 0.910885, 1.009716, 1.527510",\
+ "1.010613, 1.027735, 1.061184, 1.159981, 1.677597",\
+ "1.262256, 1.279377, 1.312826, 1.411619, 1.929216");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.099537, 1.128236, 1.185986, 1.356560, 2.250221",\
+ "1.099537, 1.128236, 1.185986, 1.356560, 2.250221",\
+ "1.099537, 1.128268, 1.186038, 1.356667, 2.250334",\
+ "1.099537, 1.128795, 1.186566, 1.357201, 2.250334",\
+ "1.099652, 1.129190, 1.186897, 1.357342, 2.250334");
+ }
+
+ } /* end of arc padmux2ast_i[3]_scan_reset_no_una_min*/
+
+ timing () {
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "380000.468750, 380000.468750, 380000.500000, 380000.593750, 380001.125000",\
+ "380000.562500, 380000.562500, 380000.593750, 380000.687500, 380001.218750",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.781250, 380001.312500",\
+ "380000.812500, 380000.812500, 380000.843750, 380000.937500, 380001.468750",\
+ "380001.062500, 380001.062500, 380001.093750, 380001.187500, 380001.718750");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\
+ "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\
+ "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\
+ "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\
+ "1.098794, 1.128370, 1.186150, 1.356812, 2.250939");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "380001.656250, 380001.656250, 380001.656250, 380001.718750, 380001.968750",\
+ "380001.750000, 380001.750000, 380001.750000, 380001.812500, 380002.062500",\
+ "380001.875000, 380001.875000, 380001.875000, 380001.937500, 380002.187500",\
+ "380002.062500, 380002.062500, 380002.062500, 380002.125000, 380002.375000",\
+ "380002.375000, 380002.375000, 380002.375000, 380002.437500, 380002.687500");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\
+ "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\
+ "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\
+ "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\
+ "0.602094, 0.617527, 0.647677, 0.736728, 1.205538");
+ }
+
+ } /* end of arc padmux2ast_i[4]_scan_reset_no_inv*/
+
+ timing () {
+ min_delay_flag : true ;
+ related_pin : "padmux2ast_i[4]" ;
+ timing_type : combinational ;
+ timing_sense : negative_unate ;
+ cell_fall( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "380000.343750, 380000.343750, 380000.375000, 380000.468750, 380000.875000",\
+ "380000.437500, 380000.437500, 380000.468750, 380000.562500, 380000.968750",\
+ "380000.500000, 380000.500000, 380000.531250, 380000.625000, 380001.031250",\
+ "380000.656250, 380000.656250, 380000.687500, 380000.781250, 380001.187500",\
+ "380000.875000, 380000.875000, 380000.906250, 380001.000000, 380001.406250");
+ }
+ fall_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\
+ "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\
+ "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\
+ "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\
+ "0.899963, 0.924149, 0.971400, 1.110963, 1.842156");
+ }
+ cell_rise( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "380001.656250, 380001.656250, 380001.656250, 380001.718750, 380001.968750",\
+ "380001.750000, 380001.750000, 380001.750000, 380001.812500, 380002.062500",\
+ "380001.843750, 380001.843750, 380001.843750, 380001.906250, 380002.156250",\
+ "380002.031250, 380002.031250, 380002.031250, 380002.093750, 380002.343750",\
+ "380002.281250, 380002.281250, 380002.281250, 380002.343750, 380002.593750");
+ }
+ rise_transition( f_itrans_ocap ){
+ index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000");
+ index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252");
+ values ( "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\
+ "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\
+ "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\
+ "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\
+ "0.599658, 0.615162, 0.645450, 0.734911, 1.203284");
+ }
+
+ } /* end of arc padmux2ast_i[4]_scan_reset_no_inv_min*/
+
+} /* end of pin scan_reset_no */
+
+
+
+
+
+
+} /* end of cell */
+
+} /* end of library */
diff --git a/hw/top_sencha/ip/ast/lint/ast.vlt b/hw/top_sencha/ip/ast/lint/ast.vlt
new file mode 100644
index 0000000..1a6e37b
--- /dev/null
+++ b/hw/top_sencha/ip/ast/lint/ast.vlt
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// waiver file for ast
+
+`verilator_config
+
+// ast_clks_byp.sv has an always_latch block which doesn't actually do anything
+// because the enable signal (!scan_mode_i) is always true. Verilator notices
+// and complains, but we're doing this on purpose.
+lint_off -rule NOLATCH -file "*/rtl/ast_clks_byp.sv"
+
+// Manually mark a clock enable: if we don't tell Verilator we're doing it on
+// purpose, it will warn us that there's a path from "normal" logic through to
+// a clock signal.
+clock_enable -module "ast_clks_byp" -var "clk_ext_en"
diff --git a/hw/top_sencha/ip/ast/lint/ast.waiver b/hw/top_sencha/ip/ast/lint/ast.waiver
new file mode 100644
index 0000000..d261f11
--- /dev/null
+++ b/hw/top_sencha/ip/ast/lint/ast.waiver
@@ -0,0 +1,337 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for ast
+
+waive -rules CONST_FF -location {ast_clks_byp.sv} \
+ -msg {Flip-flop 'sw_clk_byp_en' is driven by constant one} \
+ -comment {This flip flop is supposed to change to 1 on the first clock cycle and remain there afterwards.}
+
+waive -rules IFDEF_CODE -location {ast.sv} \
+ -msg {Assignment to 'ast2pad_t0_ao' contained within `else block at ast.sv} \
+ -comment {This ifdef statement is used for analog simulations and is OK.}
+
+waive -rules IFDEF_CODE -location {ast.sv} \
+ -msg {Assignment to 'unused_analog_sigs' contained within `ifndef 'ANALOGSIM' block at} \
+ -comment {This ifdef statement is used for assigning "unused" signals and is OK.}
+
+waive -rules IFDEF_CODE -location {ast.sv} \
+ -regexp {Assignment to 'clk_(sys|usb|aon|io)_ext' contained within `ifdef 'AST_BYPASS_CLK' block at} \
+ -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.}
+
+waive -rules IFDEF_CODE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \
+ -regexp {Assignment to '(sys|usb|aon|io)_clk_dly' contained within `else block at} \
+ -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.}
+
+waive -rules IFDEF_CODE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \
+ -regexp {Assignment to 'en_osc_re' contained within} \
+ -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.}
+
+waive -rules IFDEF_CODE -location {aon_osc.sv} \
+ -regexp {Assignment to 'clk' contained within} \
+ -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.}
+
+waive -rules CLOCK_EDGE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \
+ -msg {Falling edge of clock 'clk' used here, should use rising edge} \
+ -comment {This negedge trigger is done on purpose.}
+
+waive -rules CLOCK_EDGE -location {ast_clks_byp.sv} \
+ -msg {Falling edge of clock 'clk_ast_ext_scn' used here, should use rising edge} \
+ -comment {This negedge trigger is done on purpose.}
+
+waive -rules CLOCK_DRIVER -location {ast.sv} \
+ -regexp {'clk_src_(aon|io|sys)' is driven by instance 'u_ast_clks_byp' of module 'ast_clks_byp', and used as a clock 'clk_i' at} \
+ -comment {This is clock generation logic, hence it needs to drive this clock signal.}
+
+waive -rules CLOCK_DRIVER -location {ast.sv} \
+ -regexp {'clk_src_(aon|io|sys)' in module 'ast_clks_byp' by port} \
+ -comment {This is clock generation logic, hence it needs to drive this clock signal.}
+
+waive -rules CLOCK_DRIVER -location {ast.sv} \
+ -msg {'clk_o' driven in module 'gfr_clk_mux2' at} \
+ -comment {This is clock generation logic, hence it needs to drive this clock signal.}
+
+waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \
+ -regexp {'clk_src_(aon|io)_o' is driven by instance 'u_clk_src_(aon|io)_sel' of module 'gfr_clk_mux2', and used as a clock 'clk_i' at} \
+ -comment {This is clock generation logic, hence it needs to drive this clock signal.}
+
+waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \
+ -regexp {'clk_ext_scn' is driven here, and used as a clock 'clk_i' at} \
+ -comment {This is clock generation logic, hence it needs to drive this clock signal.}
+
+waive -rules CLOCK_MUX -location {ast_clks_byp.sv} \
+ -regexp {Clock '(clk_ast_ext_scn|clk_ext_scn|clk_src_ext_usb|clk_ext_aon)' is driven by a multiplexer here, used as a clock} \
+ -comment {This is clock generation logic, hence it needs to drive this clock signal.}
+
+waive -rules CLOCK_MUX -location {ast.sv} \
+ -regexp {Clock 'clk_aon_n' is driven by a multiplexer here, used as a clock} \
+ -comment {This clock inverter has a DFT mux.}
+
+waive -rules CLOCK_MUX -location {rglts_pdm_3p3v.sv} \
+ -regexp {Clock 'clk_src_aon_h_n' is driven by a multiplexer here, used as a clock at } \
+ -comment {This signal has a DFT mux.}
+
+waive -rules CLOCK_USE -location {gfr_clk_mux2.sv} \
+ -regexp {('clk_ext'|'clk_osc') is used for some other purpose, and as clock ('clk_ext_i'|'clk_osc_i') at gfr_clk_mux2.sv} \
+ -comment {This message pops up due to a clock OR operation.}
+
+waive -rules CLOCK_USE -location {ast.sv} \
+ -regexp {'clk_ast_tlul_i' is connected to 'ast_dft' port 'clk_i', and used as a clock 'clk_i' at prim_lfsr} \
+ -comment {This is a valid clock signal and the LFSR runs on the bus clock here.}
+
+waive -rules CLOCK_USE -location {ast.sv} \
+ -regexp {'clk_aon' is connected to 'rglts_pdm_3p3v' port 'clk_src_aon_h_i', and used as a clock} \
+ -comment {This is a valid clock signal and the connection is ok here.}
+
+waive -rules CLOCK_USE -location {ast.sv} \
+ -regexp {'clk_ast_usb_i' is used for some other purpose, and as clock 'clk_i' at prim_generic_flop.sv} \
+ -comment {This is a valid clock signal and the connection is ok here.}
+
+waive -rules INV_CLOCK -location {ast.sv rglts_pdm_3p3v.sv} \
+ -regexp {'(clk_aon|clk_src_aon_h_i)' is inverted, used as clock} \
+ -comment {These clocks are inverted.}
+
+waive -rules RESET_DRIVER -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \
+ -msg {'rst_val_n' is driven here, and used as an asynchronous reset} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \
+ -regexp {'(aon|io|sys|usb)_clk_en' is driven here, and used as an asynchronous reset} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {rng.sv} \
+ -msg {'rst_n' is driven here, and used as an asynchronous reset at rng.sv} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -regexp {'(vcaon_pok_h|por_rst_n|vcmain_pok_por|vcmain_pok_por_src)' is driven here, and used as an asynchronous reset} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -msg {'clk_io_osc_val' is driven by instance 'u_io_clk' of module 'io_clk', and used as an asynchronous reset 'rst_clk_osc_n' at ast_dft.sv} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -msg {'clk_src_io_val_o' driven in module 'io_clk' by port 'u_val_sync.q_o[0]' at io_clk.sv} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast.sv dev_entropy.sv ast_clks_byp.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port .* at prim_flop_2sync.sv} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -msg {'vcmain_pok_por_sys' is driven by instance 'u_rst_sys_dasrt' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_dev_ni' at dev_entropy.sv} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {dev_entropy.sv} \
+ -msg {'rst_es_dev_nd' is driven by instance 'u_rst_es_n_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_es_dev_n'} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {dev_entropy.sv} \
+ -msg {'rst_es_dev_nd' is driven by instance 'u_rst_es_n_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_es_dev_n'} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {dev_entropy.sv} \
+ -msg {'rst_es_dev_da_n' is driven by instance 'u_rst_es_n_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_es_dev_n' at} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {dev_entropy.sv} \
+ -msg {'rst_es_dev_in_n' is driven here, and used as an asynchronous reset 'rst_ni' at} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast_pulse_sync.sv} \
+ -regexp {'(rst_src_n|rst_dst_n)' is driven here, and used as an asynchronous reset at} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \
+ -regexp {'rst_aon_n_(ioda|exda)' is driven by instance 'u_rst_aon_n_(ioda|exda)_sync' of module} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \
+ -regexp {'rst_sw_clk_byp_en' is driven here, and used as an asynchronous reset 'rst_sw_ckbpe_n'} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -regexp {'(vcc_pok|rst_poks_n|rst_poks_por_n|vcaon_pok_por_lat)' is driven here, and used as an asynchronous reset} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -msg {'vcmain_pok_por_sys' is driven by instance 'u_rst_sys_dasrt' of module} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -msg {'rst_aon_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
+waive -rules RESET_DRIVER -location {rglts_pdm_3p3v.sv} \
+ -regexp {'(vcc_pok_rst_h_n|vcc_pok_set_h|vcc_pok_str_.*|)' is driven here, and used as an asynchronous reset} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -regexp {'(vcaon_pok|vcaon_pok_h)' is driven by instance 'u_rglts_pdm_3p3v'} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -regexp {'(vcaon_pok_1p1_h_o|vcaon_pok_h_o)' driven in module 'rglts_pdm_3p3v'} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -regexp {'rst_sys_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -regexp {'rst_usb_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {ast.sv} \
+ -regexp {'rst_io_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'rst_da_n' is driven by instance 'u_rst_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port 'u_sync_2.q_o[0]' at prim_flop_2sync.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_flop' by port 'gen_generic.u_impl_generic.q_o[0]' at prim_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_generic_flop' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'rst_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'rst_n' driven in module 'usb_clk' by 'rst_da_n' at usb_clk.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port 'u_sync_2.q_o[0]' at prim_flop_2sync.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_flop' by port 'gen_generic.u_impl_generic.q_o[0]' at prim_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_generic_flop' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'rst_usb_n' is driven by instance 'u_rst_ast_usb_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port 'u_sync_2.q_o[0]' at prim_flop_2sync.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_flop' by port 'gen_generic.u_impl_generic.q_o[0]' at prim_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_DRIVER -location {usb_clk.sv} \
+ -regexp {'q_o[0]' driven in module 'prim_generic_flop' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_MUX -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \
+ -msg {Asynchronous reset 'rst_val_n' is driven by a multiplexer here, used as a reset} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_MUX -location {ast.sv} \
+ -regexp {Asynchronous reset '(rst_poks_n|rst_poks_por_n|vcmain_pok_por|rst_src_sys_n|vcaon_pok_por)' is driven by a multiplexer here, used as a reset} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_MUX -location {rng.sv} \
+ -msg {Asynchronous reset 'rst_n' is driven by a multiplexer here, used as a reset at rng.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_MUX -location {ast_clks_byp.sv} \
+ -regexp {Asynchronous reset '(rst_aon_n|rst_aon_exda_n|rst_aon_ioda_n|rst_sw_ckbpe_n)' is driven by a multiplexer here, used as a reset} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_MUX -location {ast_pulse_sync.sv} \
+ -regexp {Asynchronous reset '(rst_src_n|rst_dst_n)' is driven by a multiplexer here, used as a reset} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_MUX -location {rglts_pdm_3p3v.sv} \
+ -msg {Asynchronous reset 'vcc_pok_rst_h_n' is driven by a multiplexer here, used as a reset} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_MUX -location {usb_clk.sv} \
+ -regexp {Asynchronous reset 'rst_n' is driven by a multiplexer here, used as a reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_USE -location {ast.sv} \
+ -regexp {('vcore_pok_h_i'|'vcaon_pok') is used for some other purpose, and as asynchronous reset} \
+ -comment {This is reset / clock generation logic, hence special reset usage is allowed.}
+
+waive -rules RESET_USE -location {ast.sv} \
+ -regexp {'(vcmain_pok_por|vcmain_pok_por_src)' is connected to 'rglts_pdm_3p3v' port 'vcmain_pok_por_h_i', and used as an asynchronous reset or set} \
+ -comment {This is reset / clock generation logic, hence special reset usage is allowed.}
+
+waive -rules RESET_USE -location {ast.sv} \
+ -msg {'vcaon_pok_por' is connected to 'rglts_pdm_3p3v' port 'vcaon_pok_por_h_i', and used as an asynchronous reset or set} \
+ -comment {This is reset / clock generation logic, hence special reset usage is allowed.}
+
+waive -rules RESET_USE -location {ast.sv} \
+ -regexp {'(vcc_pok|vcmain_pok_por)' is used for some other purpose, and as asynchronous reset} \
+ -comment {This is reset / clock generation logic, hence special reset usage is allowed.}
+
+waive -rules RESET_USE -location {ast.sv} \
+ -regexp {'rst_(usb|aon|io|sys)_clk_n' is connected to '(usb|aon|io|sys)_clk' port 'rst_(usb|aon|io|sys)_clk_ni', and used as an asynchronous reset or set ('rst_ni'|'vcore_pok_h_i'|'rst_clk_byp_n')} \
+ -comment {This is reset / clock generation logic, hence special reset usage is allowed.}
+
+waive -rules RESET_USE -location {io_osc.sv sys_osc.sv usb_osc.sv aon_osc.sv} \
+ -msg {'vcore_pok_h_i' is used for some other purpose, and as asynchronous reset at} \
+ -comment {This is reset / clock generation logic, hence special reset usage is allowed.}
+
+waive -rules RESET_USE -location {ast_dft.sv} \
+ -msg {'clk_io_osc_val_i' is used for some other purpose, and as asynchronous reset 'rst_clk_osc_n' at ast_dft.sv} \
+ -comment {This is reset / clock generation logic, hence special reset usage is allowed.}
+
+waive -rules RESET_USE -location {ast.sv} \
+ -msg {'rst_ast_tlul_ni' is connected to 'ast_dft' port 'rst_ni', and used as an asynchronous reset or set 'rst_n' at rng} \
+ -comment {This is a valid reset connection.}
+
+waive -rules RESET_USE -location {ast.sv} \
+ -regexp {('rst_sys_clk_n'|'rst_usb_clk_n') is connected to ('sys_clk'|'usb_clk') port ('rst_sys_clk_ni'|'rst_usb_clk_ni'), and used as an asynchronous reset or set} \
+ -comment {This is a valid reset connection.}
+
+waive -rules RESET_USE -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \
+ -regexp {'(aon|io|sys|usb)_clk_en' is connected to '(aon|io|sys|usb)_osc' port '(aon|io|sys|usb)_en_i', and used as an asynchronous reset or set} \
+ -comment {This is reset / clock generation logic, hence special reset usage is allowed.}
+
+waive -rules RESET_USE -location {ast.sv} \
+ -regexp {'rst_ast_usb_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules RESET_USE -location {usb_clk.sv} \
+ -regexp {'rst_usb_clk_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment {This is reset generation logic, hence reset muxes are allowed.}
+
+waive -rules TRI_DRIVER -location {ast.sv} \
+ -regexp {'ast2pad_(t0|t1)_ao' is driven by a tristate driver} \
+ -comment {This part models a tristate driver.}
+
+waive -rules TERMINAL_STATE -location {rglts_pdm_3p3v.sv} \
+ -msg {Terminal state 'RGLS_BROUT' is detected. State register 'rgls_sm' is not assigned to another state.} \
+ -comment {The brownout state is terminal.}
+
+waive -rules Z_USE -location {ast.sv} \
+ -msg {Constant with 'Z literal value '1'bz' encountered} \
+ -comment {This part models a tristate driver.}
+
+waive -rules MULTI_RESET -location {rglts_pdm_3p3v.sv} \
+ -msg {Found 2 asynchronous resets for this block: 'vcc_pok_rst_h_n', 'vcc_pok_set_h'} \
+ -comment {This code is only a model and hence this is allowed.}
+
+waive -rules NOT_READ -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \
+ -msg {Signal 'en_osc' is not read from in module} \
+ -comment {Signal 'en_osc' is not read when SYNTHESIS is defined, and AST_BYPASS_CLK is not defined.}
diff --git a/hw/top_sencha/ip/ast/rtl/adc.sv b/hw/top_sencha/ip/ast/rtl/adc.sv
new file mode 100644
index 0000000..31726bf
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/adc.sv
@@ -0,0 +1,123 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: adc
+// *Module Description: Analog/Digital Converter
+//############################################################################
+
+module adc #(
+ parameter int unsigned AdcCnvtClks = 22, // TODO: Update to actual convertion clock
+ parameter int AdcChannels = 2, // ADC number of Channels
+ parameter int AdcDataWidth = 10
+) (
+ input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input
+ input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input
+ input [AdcChannels-1:0] adc_chnsel_i, // Onehot value only for selrction
+ input adc_pd_i, // ADC Power Down
+ input clk_adc_i, // ADC Clock (aon_clk - 200KHz)
+ input rst_adc_ni, // ADC Reset active low
+ output logic [AdcDataWidth-1:0] adc_d_o, // ADC 10-bit Data Output
+ output logic adc_d_val_o // ADC Data Valid Output
+);
+
+///////////////////////////////////////
+// ADC Enable
+///////////////////////////////////////
+logic adc_en;
+
+always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin
+ if ( !rst_adc_ni ) begin
+ adc_en <= 1'b0;
+ end else begin
+ adc_en <= !adc_pd_i;
+ end
+end
+
+
+///////////////////////////////////////
+// ADC Channel Select
+///////////////////////////////////////
+logic chn_selected, chn_selected_d, new_convert, adc_busy;
+
+assign chn_selected = |(adc_chnsel_i);
+
+// TODO: Reset?
+always_ff @( posedge clk_adc_i ) begin
+ chn_selected_d <= chn_selected;
+end
+
+// New Convertion
+// TODO: Add assertion that channel change always happen on ADC_IDLE!
+assign new_convert = chn_selected && !chn_selected_d && !adc_busy;
+
+////////////////////////////////////////
+// ADC Analog Model
+////////////////////////////////////////
+logic [10-1:0] adc_d_ch0, adc_d_ch1;
+
+adc_ana u_adc_ana (
+ .adc_a0_ai ( adc_a0_ai ),
+ .adc_a1_ai ( adc_a1_ai ),
+ .adc_d_ch0_o ( adc_d_ch0[10-1:0] ),
+ .adc_d_ch1_o ( adc_d_ch1[10-1:0] )
+);
+
+
+////////////////////////////////////////
+// ADC Digital Model
+////////////////////////////////////////
+logic [8-1:0] cnv_cyc;
+logic [8-1:0] ConvertCount;
+
+assign ConvertCount = AdcCnvtClks[8-1:0];
+
+always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin
+ if (!rst_adc_ni ) begin
+ cnv_cyc <= 8'h00;
+ adc_busy <= 1'b0;
+ adc_d_val_o <= 1'b0;
+ adc_d_o <= {AdcDataWidth{1'b0}};
+ end else if ( !(adc_en && chn_selected) ) begin
+ cnv_cyc <= 8'h00;
+ adc_busy <= 1'b0;
+ adc_d_val_o <= 1'b0;
+ end else if ( new_convert ) begin
+ cnv_cyc <= ConvertCount;
+ adc_busy <= 1'b1;
+ adc_d_val_o <= 1'b0;
+ end else if ( adc_busy && (cnv_cyc > 8'h00) ) begin
+ cnv_cyc <= cnv_cyc - 1'b1;
+ adc_busy <= 1'b1;
+ adc_d_val_o <= 1'b0;
+ end else if ( adc_busy ) begin
+ adc_busy <= 1'b0;
+ adc_d_val_o <= 1'b1;
+ adc_d_o <= (adc_chnsel_i == 2'b00) ? adc_d_o :
+ (adc_chnsel_i == 2'b01) ? adc_d_ch0[10-1:0] :
+ (adc_chnsel_i == 2'b10) ? adc_d_ch1[10-1:0] :
+ {AdcDataWidth{1'b1}};
+ end
+end
+
+
+/////////////////////////
+// ASSERTIONS
+/////////////////////////
+// TODO: Add assertiom adc_en=0 chnsel is 0.
+// TODO: Add assertiom RE of adc_en on 30us chnsel is 0.
+// TODO: Add Assertion for (adc_chnsel_i == 2'b11) @clk_adc_i
+
+endmodule : adc
diff --git a/hw/top_sencha/ip/ast/rtl/adc_ana.sv b/hw/top_sencha/ip/ast/rtl/adc_ana.sv
new file mode 100644
index 0000000..d1c71c0
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/adc_ana.sv
@@ -0,0 +1,57 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: sdc_ana
+// *Module Description: ADC Analog
+//############################################################################
+
+module adc_ana (
+ input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input
+ input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input
+ output logic [10-1:0] adc_d_ch0_o, // ADC A0 Digital Output
+ output logic [10-1:0] adc_d_ch1_o // ADC A1 Digital Output
+);
+
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+real vref = 2.3;
+real adc_vi0_hook = 1.0;
+real adc_vi1_hook = 1.0;
+real adc_vi0, adc_vi1;
+
+`ifdef ANALOGSIM
+assign adc_vi0 = adc_a0_ai;
+assign adc_vi1 = adc_a1_ai;
+`else
+assign adc_vi0 = adc_a0_ai ? adc_vi0_hook : 0.0;
+assign adc_vi1 = adc_a1_ai ? adc_vi1_hook : 0.0;
+`endif
+assign adc_d_ch0_o = $rtoi((adc_vi0/vref) * $itor(10'h3ff));
+assign adc_d_ch1_o = $rtoi((adc_vi1/vref) * $itor(10'h3ff));
+`else // of SYNTHESIS
+// FPGA/VERILATOR
+////////////////////////////////////////
+logic [10-1:0] adc_d_vi0_hook, adc_d_vi1_hook;
+
+assign adc_d_vi0_hook = 10'h155;
+assign adc_d_vi1_hook = 10'h2AA;
+
+assign adc_d_ch0_o = adc_a0_ai ? adc_d_vi0_hook : 10'h000;
+assign adc_d_ch1_o = adc_a1_ai ? adc_d_vi1_hook : 10'h000;
+`endif
+
+endmodule : adc_ana
diff --git a/hw/top_sencha/ip/ast/rtl/aon_clk.sv b/hw/top_sencha/ip/ast/rtl/aon_clk.sv
new file mode 100644
index 0000000..3a294aa
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/aon_clk.sv
@@ -0,0 +1,75 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: aon_clk
+// *Module Description: Always ON Clock
+//############################################################################
+
+module aon_clk (
+ input vcore_pok_h_i, // VCORE POK @3.3V (for OSC)
+ input clk_aon_pd_ni, // AON Clock Power-down
+ input rst_aon_clk_ni, // AON Clock Logic reset
+ input clk_src_aon_en_i, // AON Source Clock Enable
+ input scan_mode_i, // Scan Mode
+ input aon_osc_cal_i, // AON Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_aon_ext_i, // FPGA/VERILATOR Clock input
+`endif
+ output logic clk_src_aon_o, // AON Source Clock
+ output logic clk_src_aon_val_o // AON Source Clock Valid
+);
+
+logic clk, osc_en, aon_clk_en;
+
+assign osc_en = (clk_src_aon_en_i && clk_aon_pd_ni && rst_aon_clk_ni);
+assign aon_clk_en = scan_mode_i || osc_en;
+
+// Clock Oscillator
+///////////////////////////////////////
+aon_osc u_aon_osc (
+ .vcore_pok_h_i ( vcore_pok_h_i ),
+ .aon_en_i ( aon_clk_en ),
+ .aon_osc_cal_i ( aon_osc_cal_i ),
+`ifdef AST_BYPASS_CLK
+ .clk_aon_ext_i ( clk_aon_ext_i ),
+`endif
+ .aon_clk_o ( clk )
+); // of u_aon_osc
+
+// Clock & Valid
+///////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_aon_buf(
+ .clk_i ( clk ),
+ .clk_o ( clk_src_aon_o )
+);
+
+// 2-stage de-assertion
+logic rst_val_n;
+assign rst_val_n = aon_clk_en;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_val_sync (
+ .clk_i ( clk_src_aon_o ),
+ .rst_ni ( rst_val_n ),
+ .d_i ( 1'b1 ),
+ .q_o ( clk_src_aon_val_o )
+);
+
+endmodule : aon_clk
diff --git a/hw/top_sencha/ip/ast/rtl/aon_osc.sv b/hw/top_sencha/ip/ast/rtl/aon_osc.sv
new file mode 100644
index 0000000..8950ce5
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/aon_osc.sv
@@ -0,0 +1,144 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: aon_osc
+// *Module Description: AON Clock Oscilator
+//############################################################################
+
+module aon_osc (
+ input vcore_pok_h_i, // VCORE POK @3.3V
+ input aon_en_i, // AON Source Clock Enable
+ input aon_osc_cal_i, // AON Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_aon_ext_i, // FPGA/VERILATOR Clock input\
+`endif
+ output logic aon_clk_o // AON Clock Output
+);
+
+`ifndef AST_BYPASS_CLK
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+timeunit 1ns / 10ps;
+
+real CLK_PERIOD, ckmul;
+
+reg init_start;
+initial init_start = 1'b0;
+
+initial begin
+ if ( !$value$plusargs("osc200k_freq_multiplier=%f", ckmul) ) ckmul = 1.0;
+ #1;
+ init_start = 1'b1;
+ #1;
+ $display("\n%m: AON Base Clock Power-up Frequency: %0d Hz", $rtoi(10**9/(CLK_PERIOD*ckmul)));
+ $display("%m: AON %0.1fxBase Clock Power-up Frequency: %0d Hz", ckmul, $rtoi(10**9/CLK_PERIOD));
+end
+
+// Enable 5us RC Delay on rise
+wire en_osc_re_buf, en_osc_re;
+buf #(ast_bhv_pkg::AON_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && aon_en_i));
+assign en_osc_re = en_osc_re_buf && init_start;
+
+// Clock Oscillator
+////////////////////////////////////////
+real CalAonClkPeriod, UncAonClkPeriod, AonClkPeriod;
+
+initial CalAonClkPeriod = $itor( 5000 ); // 5000ns (200KHz)
+initial UncAonClkPeriod = $itor( $urandom_range(10000, 5555) ); // 10000-5555ps (100-180KHz)
+
+assign AonClkPeriod = (aon_osc_cal_i && init_start) ? CalAonClkPeriod : UncAonClkPeriod;
+assign CLK_PERIOD = AonClkPeriod/ckmul;
+
+// Free running oscillator
+reg clk_osc;
+initial clk_osc = 1'b1;
+
+always begin
+ #(CLK_PERIOD/2) clk_osc = ~clk_osc;
+end
+
+logic en_osc;
+
+// HDL Clock Gate
+logic en_clk, clk;
+
+always_latch begin
+ if ( !clk_osc ) en_clk = en_osc;
+end
+
+assign clk = clk_osc && en_clk;
+`else // of SYNTHESIS
+// SYNTHESIS/LINTER
+///////////////////////////////////////
+logic clk, en_osc;
+assign clk = 1'b0;
+
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && aon_en_i;
+`endif // of SYNTHESIS
+`else // of AST_BYPASS_CLK
+// VERILATOR/FPGA
+///////////////////////////////////////
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && aon_en_i;
+
+// Clock Oscillator
+////////////////////////////////////////
+logic clk, en_osc;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1 )
+) u_clk_ckgt (
+ .clk_i ( clk_aon_ext_i ),
+ .en_i ( en_osc ),
+ .test_en_i ( 1'b0 ),
+ .clk_o ( clk )
+);
+`endif
+
+logic en_osc_fe;
+
+// Syncronize en_osc to clk FE for glitch free disable
+always_ff @( negedge clk, negedge vcore_pok_h_i ) begin
+ if ( !vcore_pok_h_i ) begin
+ en_osc_fe <= 1'b0;
+ end else begin
+ en_osc_fe <= en_osc_re;
+ end
+end
+
+assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0
+
+// Clock Output Buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_buf (
+ .clk_i ( clk ),
+ .clk_o ( aon_clk_o )
+);
+
+
+`ifdef SYNTHESIS
+///////////////////////
+// Unused Signals
+///////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ aon_osc_cal_i };
+`endif
+
+endmodule : aon_osc
diff --git a/hw/top_sencha/ip/ast/rtl/ast.sv b/hw/top_sencha/ip/ast/rtl/ast.sv
new file mode 100644
index 0000000..cd74367
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast.sv
@@ -0,0 +1,1169 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- //
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED.
+//
+//############################################################################
+// *Name: ast
+// *Module Description: Analog Sensors Top
+//############################################################################
+
+`include "prim_assert.sv"
+
+module ast #(
+ parameter int unsigned AdcChannels = 2,
+ parameter int unsigned AdcDataWidth = 10,
+ parameter int unsigned EntropyStreams = 4,
+ parameter int unsigned UsbCalibWidth = 20,
+ parameter int unsigned Ast2PadOutWidth = 9,
+ parameter int unsigned Pad2AstInWidth = 9
+) (
+ // tlul if
+ input tlul_pkg::tl_h2d_t tl_i, // TLUL H2D
+ output tlul_pkg::tl_d2h_t tl_o, // TLUL D2H
+ output prim_mubi_pkg::mubi4_t ast_init_done_o, // AST (registers) Init Done
+
+ // clocks / resets
+ input clk_ast_adc_i, // Buffered AST ADC Clock
+ input rst_ast_adc_ni, // Buffered AST ADC Reset
+ input clk_ast_alert_i, // Buffered AST Alert Clock
+ input rst_ast_alert_ni, // Buffered AST Alert Reset
+ input clk_ast_es_i, // Buffered AST Entropy Source Clock
+ input rst_ast_es_ni, // Buffered AST Entropy Source Reset
+ input clk_ast_rng_i, // Buffered AST RNG Clock
+ input rst_ast_rng_ni, // Buffered AST RNG Reset
+ input clk_ast_tlul_i, // Buffered AST TLUL Clock
+ input rst_ast_tlul_ni, // Buffered AST TLUL Reset
+ input clk_ast_usb_i, // Buffered AST USB Clock
+ input rst_ast_usb_ni, // Buffered AST USB Reset
+ input clk_ast_ext_i, // Buffered AST External Clock
+ input por_ni, // Power ON Reset
+
+ // sensed clocks / resets
+ input clkmgr_pkg::clkmgr_out_t sns_clks_i, // Sensed Clocks
+ input rstmgr_pkg::rstmgr_out_t sns_rsts_i, // Sensed Resets
+ input sns_spi_ext_clk_i, // Sensed SPI External Clock
+
+`ifdef AST_BYPASS_CLK
+ // Clocks' Oschillator bypass for OS FPGA
+ input ast_pkg::clks_osc_byp_t clk_osc_byp_i, // Clocks' Oschillator bypass for OS FPGA/VERILATOR
+`endif
+
+ // power OK control
+ // In non-power aware DV environment, the <>_supp_i is for debug only!
+ // POK signal follow this input.
+ // In a power aware environment this signal should be connected to constant '1'
+ input vcc_supp_i, // VCC Supply Test for OS FPGA
+ input vcaon_supp_i, // VCAON Supply Test for OS FPGA
+ input vcmain_supp_i, // VCMAIN Supply Test for OS FPGA
+ input vioa_supp_i, // VIOA Rail Supply Test for OS FPGA
+ input viob_supp_i, // VIOB Rail Supply Test for OS FPGA
+ output ast_pkg::ast_pwst_t ast_pwst_o, // AON, MAIN, IO-0 Rail, IO-1 Rail Power OK @1.1V
+ output ast_pkg::ast_pwst_t ast_pwst_h_o, // AON, MAIN, IO-9 Rail, IO-1 Rail Power OK @3.3V
+
+ // Power and IO pin connections
+ input main_pd_ni, // MAIN Regulator Power Down
+ input main_env_iso_en_i, // Enveloped ISOlation ENable for MAIN
+
+ // power down monitor logic - flash/otp related
+ output logic flash_power_down_h_o, // Flash Power Down
+ output logic flash_power_ready_h_o, // Flash Power Ready
+ input [1:0] otp_power_seq_i, // MMR0,24 in (VDD)
+ output logic [1:0] otp_power_seq_h_o, // MMR0,24 masked by PDM, out (VCC)
+
+ // system source clock
+ input clk_src_sys_en_i, // SYS Source Clock Enable
+ input prim_mubi_pkg::mubi4_t clk_src_sys_jen_i, // SYS Source Clock Jitter Enable
+ output logic clk_src_sys_o, // SYS Source Clock
+ output logic clk_src_sys_val_o, // SYS Source Clock Valid
+
+ // aon source clock
+ output logic clk_src_aon_o, // AON Source Clock
+ output logic clk_src_aon_val_o, // AON Source Clock Valid
+
+ // io source clock
+ input clk_src_io_en_i, // IO Source Clock Enable
+ output logic clk_src_io_o, // IO Source Clock
+ output logic clk_src_io_val_o, // IO Source Clock Valid
+ output prim_mubi_pkg::mubi4_t clk_src_io_48m_o, // IO Source Clock is 48MHz
+
+ // usb source clock
+ input usb_ref_pulse_i, // USB Reference Pulse
+ input usb_ref_val_i, // USB Reference Valid
+ input clk_src_usb_en_i, // USB Source Clock Enable
+ output logic clk_src_usb_o, // USB Source Clock
+ output logic clk_src_usb_val_o, // USB Source Clock Valid
+ output logic [UsbCalibWidth-1:0] usb_io_pu_cal_o, // USB IO Pull-up Calibration Setting
+
+ // smc source clock
+ input clk_src_smc_en_i, // SMC Source Clock Enable
+ output logic clk_src_smc_o, // SMC Source Clock
+ output logic clk_src_smc_val_o, // SMC Source Clock Valid
+
+ // ml source clock
+ input clk_src_ml_en_i, // ML Source Clock Enable
+ output logic clk_src_ml_o, // ML Source Clock
+ output logic clk_src_ml_val_o, // ML Source Clock Valid
+
+ // video source clock
+ input clk_src_video_en_i, // VideO Source Clock Enable
+ output logic clk_src_video_o, // Video Source Clock
+ output logic clk_src_video_val_o, // Video Source Clock Valid
+
+ // audio source clock
+ input clk_src_audio_en_i, // AUDIO Source Clock Enable
+ output logic clk_src_audio_o, // audio Source Clock
+ output logic clk_src_audio_val_o, // audio Source Clock Valid
+
+ // adc interface
+ input adc_pd_i, // ADC Power Down
+ input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input
+ input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input
+ input [AdcChannels-1:0] adc_chnsel_i, // ADC Channel Select
+ output [AdcDataWidth-1:0] adc_d_o, // ADC Digital (per channel)
+ output adc_d_val_o, // ADC Digital Valid
+
+ // rng (entropy source) interface
+ input rng_en_i, // RNG Enable
+ input rng_fips_i, // RNG FIPS
+ output logic rng_val_o, // RNG Valid
+ output logic [EntropyStreams-1:0] rng_b_o, // RNG Bit(s)
+
+ // entropy distribution interface
+ input edn_pkg::edn_rsp_t entropy_rsp_i, // Entropy Response
+ output edn_pkg::edn_req_t entropy_req_o, // Entropy Request
+
+ // alerts
+ input ast_pkg::ast_alert_rsp_t alert_rsp_i, // Alerts Trigger & Acknowledge Inputs
+ output ast_pkg::ast_alert_req_t alert_req_o, // Alerts Output
+
+ // dft interface
+ input pinmux_pkg::dft_strap_test_req_t dft_strap_test_i, // DFT Straps
+ input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, // DFT enable (secure bus)
+ input [8-1:0] fla_obs_i, // FLASH Observe Bus
+ input [8-1:0] otp_obs_i, // OTP Observe Bus
+ input [8-1:0] otm_obs_i, // OT Modules Observe Bus
+ input usb_obs_i, // USB DIFF RX Observe
+ output ast_pkg::ast_obs_ctrl_t obs_ctrl_o, // Observe Control
+
+ // pad mux/pad related
+ input [Pad2AstInWidth-1:0] padmux2ast_i, // IO_2_DFT Input Signals
+ output logic [Ast2PadOutWidth-1:0] ast2padmux_o, // DFT_2_IO Output Signals
+
+`ifdef ANALOGSIM
+ output real ast2pad_t0_ao, // AST_2_PAD Analog T0 Output Signal
+ output real ast2pad_t1_ao, // AST_2_PAD Analog T1 Output Signal
+`else
+ output wire ast2pad_t0_ao, // AST_2_PAD Analog T0 Output Signal
+ output wire ast2pad_t1_ao, // AST_2_PAD Analog T1 Output Signal
+`endif
+
+ // flash and external clocks
+ input prim_mubi_pkg::mubi4_t ext_freq_is_96m_i, // External clock frequecy is 96MHz
+ input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // All clocks bypass request
+ output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o, // Switch all clocks to External clocks
+ input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // IO clock bypass request (for OTP bootstrap)
+ output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o, // Switch IO clock to External clockn
+ output prim_mubi_pkg::mubi4_t flash_bist_en_o, // Flush BIST (TAP) Enable
+
+ // memories read-write margins
+ output ast_pkg::dpm_rm_t dpram_rmf_o, // Dual Port RAM Read-write Margin Fast
+ output ast_pkg::dpm_rm_t dpram_rml_o, // Dual Port RAM Read-write Margin sLow
+ output ast_pkg::spm_rm_t spram_rm_o, // Single Port RAM Read-write Margin
+ output ast_pkg::spm_rm_t sprgf_rm_o, // Single Port Reg-File Read-write Margin
+ output ast_pkg::spm_rm_t sprom_rm_o, // Single Port ROM Read-write Margin
+
+ // Scan interface
+ output prim_mubi_pkg::mubi4_t dft_scan_md_o, // Scan Mode output
+ output scan_shift_en_o, // Scan Shift Enable output
+ output scan_reset_no // Scan Reset output
+);
+
+import ast_pkg::* ;
+import ast_reg_pkg::* ;
+import ast_bhv_pkg::* ;
+
+logic scan_mode, shift_en, scan_reset_n;
+logic vcc_pok, vcc_pok_h, vcc_pok_str;
+logic vcaon_pok, vcaon_pok_h, vcmain_pok;
+logic vcaon_pok_por, vcmain_pok_por;
+
+// Local (AST) System clock buffer
+////////////////////////////////////////
+logic clk_sys;
+
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_sys_buf (
+ .clk_i ( clk_src_sys_o ),
+ .clk_o ( clk_sys )
+);
+
+// Local (AST) AON clock buffer
+////////////////////////////////////////
+logic clk_aon;
+
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_aon_buf (
+ .clk_i ( clk_src_aon_o ),
+ .clk_o ( clk_aon )
+);
+
+
+assign flash_bist_en_o = prim_mubi_pkg::MuBi4False;
+//
+assign dft_scan_md_o = prim_mubi_pkg::MuBi4False;
+assign scan_shift_en_o = 1'b0;
+assign scan_reset_no = 1'b1;
+assign scan_mode = 1'b0;
+assign shift_en = 1'b0;
+assign scan_reset_n = 1'b1;
+
+
+///////////////////////////////////////
+// VCC POK (Always ON)
+///////////////////////////////////////
+logic vcc_pok_int;
+
+vcc_pgd u_vcc_pok (
+ .vcc_pok_o ( vcc_pok_int )
+);
+
+assign vcc_pok = vcc_pok_int && vcc_supp_i;
+assign vcc_pok_h = vcc_pok; // "Level Shifter"
+
+
+////////////////////////////////////////
+// VCAON POK POR (Always ON)
+///////////////////////////////////////
+logic rst_poks_n, rst_poks_por_n, por_sync_n;
+logic vcaon_pok_por_src, vcaon_pok_por_lat, poks_por_ack, rglssm_vcmon, rglssm_brout;
+
+assign rst_poks_n = vcc_pok_str && vcaon_pok;
+assign rst_poks_por_n = vcc_pok_str && vcaon_pok && por_ni;
+assign poks_por_ack = vcaon_pok_por_src || rglssm_vcmon;
+
+// Reset De-Assert Sync
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_poks_por_dasrt (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_poks_por_n ),
+ .d_i ( poks_por_ack ),
+ .q_o ( vcaon_pok_por_src )
+);
+
+logic clk_aon_n;
+
+prim_clock_inv #(
+ .HasScanMode ( 1 )
+) u_clk_aon_inv (
+ .clk_i ( clk_aon ),
+ .scanmode_i ( scan_mode ),
+ .clk_no ( clk_aon_n )
+);
+
+prim_flop #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_por_sync_n (
+ .clk_i ( clk_aon_n ),
+ .rst_ni ( rst_poks_n ),
+ .d_i ( vcaon_pok_por_src ),
+ .q_o ( por_sync_n )
+);
+
+// Replace Latch for the OS code
+assign vcaon_pok_por_lat = rglssm_brout || vcaon_pok_por_src;
+assign ast_pwst_o.aon_pok = vcaon_pok_por_lat;
+assign vcaon_pok_por = scan_mode ? scan_reset_n : vcaon_pok_por_lat;
+
+
+////////////////////////////////////////
+// VCMAIN POK POR (Always ON)
+///////////////////////////////////////
+logic rglssm_vmppr, vcmain_pok_por_src;
+
+assign vcmain_pok_por_src = vcaon_pok_por_lat && vcmain_pok && !rglssm_vmppr;
+assign ast_pwst_o.main_pok = vcmain_pok_por_src;
+assign vcmain_pok_por = scan_mode ? scan_reset_n : vcmain_pok_por_src;
+
+
+///////////////////////////////////////
+// VIOA POK (Always ON)
+///////////////////////////////////////
+logic vioa_pok;
+logic vioa_pok_int;
+
+vio_pgd u_vioa_pok (
+ .vio_pok_o ( vioa_pok_int )
+);
+
+assign vioa_pok = vioa_pok_int && vioa_supp_i;
+assign ast_pwst_o.io_pok[0] = vcaon_pok && vioa_pok;
+
+
+///////////////////////////////////////
+// VIOB POK (Always ON)
+///////////////////////////////////////
+logic viob_pok;
+logic viob_pok_int;
+
+vio_pgd u_viob_pok (
+ .vio_pok_o ( viob_pok_int )
+);
+
+assign viob_pok = viob_pok_int && viob_supp_i;
+assign ast_pwst_o.io_pok[1] = vcaon_pok && viob_pok;
+
+
+///////////////////////////////////////
+// Regulators & PDM Logic (VCC)
+///////////////////////////////////////
+logic deep_sleep;
+logic main_pd, por_sync;
+
+assign main_pd = !main_pd_ni;
+assign por_sync = !por_sync_n;
+
+rglts_pdm_3p3v u_rglts_pdm_3p3v (
+ .vcc_pok_h_i ( vcc_pok_h ),
+ .vcaon_pok_por_h_i ( vcaon_pok_por_src ),
+ .vcmain_pok_por_h_i ( vcmain_pok_por_src ),
+ .vio_pok_h_i ( ast_pwst_o.io_pok[1:0] ),
+ .clk_src_aon_h_i ( clk_aon ),
+ .main_pd_h_i ( main_pd ),
+ .por_sync_h_i ( por_sync ),
+ .scan_mode_h_i ( scan_mode ),
+ .otp_power_seq_h_i ( otp_power_seq_i[2-1:0] ),
+ .vcaon_supp_i ( vcaon_supp_i ),
+ .vcmain_supp_i ( vcmain_supp_i ),
+ .rglssm_vmppr_h_o ( rglssm_vmppr ),
+ .rglssm_vcmon_h_o ( rglssm_vcmon ),
+ .rglssm_brout_h_o ( rglssm_brout ),
+ .vcmain_pok_h_o ( vcmain_pok ),
+ .vcmain_pok_por_h_o ( ast_pwst_h_o.main_pok ),
+ .vcaon_pok_h_o ( vcaon_pok_h ),
+ .vcaon_pok_1p1_h_o ( vcaon_pok ),
+ .vcaon_pok_por_h_o ( ast_pwst_h_o.aon_pok ),
+ .vio_pok_h_o ( ast_pwst_h_o.io_pok[2-1:0] ),
+ .vcc_pok_str_h_o ( ast_pwst_h_o.vcc_pok ),
+ .vcc_pok_str_1p1_h_o ( vcc_pok_str ),
+ .deep_sleep_h_o ( deep_sleep ),
+ .flash_power_down_h_o ( flash_power_down_h_o ),
+ .flash_power_ready_h_o ( flash_power_ready_h_o ),
+ .otp_power_seq_h_o ( otp_power_seq_h_o[2-1:0] )
+);
+
+assign ast_pwst_o.vcc_pok = vcc_pok_str;
+
+
+///////////////////////////////////////
+///////////////////////////////////////
+// Clocks Oscillattors
+///////////////////////////////////////
+///////////////////////////////////////
+
+
+
+///////////////////////////////////////
+// System Clock (Always ON)
+///////////////////////////////////////
+logic rst_sys_clk_n, clk_sys_pd_n;
+logic clk_sys_en, clk_osc_sys, clk_osc_sys_val;
+prim_mubi_pkg::mubi4_t clk_src_sys_jen;
+
+assign rst_sys_clk_n = vcmain_pok_por && vcc_pok;
+assign clk_sys_pd_n = scan_mode || !deep_sleep;
+
+logic sys_io_osc_cal;
+
+assign clk_sys_en = clk_src_sys_en_i;
+
+`ifdef AST_BYPASS_CLK
+logic clk_sys_ext;
+assign clk_sys_ext = clk_osc_byp_i.sys;
+`endif
+
+sys_clk u_sys_clk (
+ .clk_src_sys_jen_i ( prim_mubi_pkg::mubi4_test_true_loose(clk_src_sys_jen) ),
+ .clk_src_sys_en_i ( clk_sys_en ),
+ .clk_sys_pd_ni ( clk_sys_pd_n ),
+ .rst_sys_clk_ni ( rst_sys_clk_n ),
+ .vcore_pok_h_i ( vcaon_pok_h ),
+ .scan_mode_i ( scan_mode ),
+ .sys_osc_cal_i ( sys_io_osc_cal ),
+`ifdef AST_BYPASS_CLK
+ .clk_sys_ext_i ( clk_sys_ext ),
+`endif
+ .clk_src_sys_o ( clk_osc_sys ),
+ .clk_src_sys_val_o ( clk_osc_sys_val )
+);
+
+
+///////////////////////////////////////
+// USB Clock (Always ON)
+///////////////////////////////////////
+logic rst_usb_clk_n, clk_usb_pd_n;
+logic clk_usb_en, clk_osc_usb, clk_osc_usb_val;
+logic usb_ref_val, usb_ref_pulse;
+
+assign rst_usb_clk_n = vcmain_pok_por && vcc_pok;
+assign clk_usb_pd_n = scan_mode || !deep_sleep;
+
+logic usb_osc_cal;
+
+`ifdef AST_BYPASS_CLK
+logic clk_usb_ext;
+assign clk_usb_ext = clk_osc_byp_i.usb;
+`endif
+
+assign clk_usb_en = clk_src_usb_en_i;
+assign usb_ref_val = usb_ref_val_i;
+assign usb_ref_pulse = usb_ref_pulse_i;
+
+usb_clk u_usb_clk (
+ .vcore_pok_h_i ( vcaon_pok_h ),
+ .clk_usb_pd_ni ( clk_usb_pd_n ),
+ .rst_usb_clk_ni ( rst_usb_clk_n ),
+ .clk_src_usb_en_i ( clk_usb_en ),
+ .usb_ref_val_i ( usb_ref_val ),
+ .usb_ref_pulse_i ( usb_ref_pulse ),
+ .clk_ast_usb_i ( clk_ast_usb_i ),
+ .rst_ast_usb_ni ( rst_ast_usb_ni ),
+ .scan_mode_i ( scan_mode ),
+ .usb_osc_cal_i ( usb_osc_cal ),
+`ifdef AST_BYPASS_CLK
+ .clk_usb_ext_i ( clk_usb_ext ),
+`endif
+ .clk_src_usb_o ( clk_osc_usb ),
+ .clk_src_usb_val_o ( clk_osc_usb_val )
+);
+
+
+///////////////////////////////////////
+// AON Clock (Always ON)
+///////////////////////////////////////
+logic rst_aon_clk_n;
+logic clk_src_aon_en, clk_osc_aon, clk_osc_aon_val;
+logic aon_osc_cal;
+
+`ifdef AST_BYPASS_CLK
+logic clk_aon_ext;
+assign clk_aon_ext = clk_osc_byp_i.aon;
+`endif
+
+assign rst_aon_clk_n = vcc_pok_str && vcaon_pok;
+assign clk_src_aon_en = 1'b1; // Always Enabled
+
+aon_clk u_aon_clk (
+ .vcore_pok_h_i ( vcaon_pok_h ),
+ .clk_aon_pd_ni ( 1'b1 ), // Always Enabled
+ .rst_aon_clk_ni ( rst_aon_clk_n ),
+ .clk_src_aon_en_i ( clk_src_aon_en ),
+ .scan_mode_i ( scan_mode ),
+ .aon_osc_cal_i ( aon_osc_cal ),
+`ifdef AST_BYPASS_CLK
+ .clk_aon_ext_i ( clk_aon_ext ),
+`endif
+ .clk_src_aon_o ( clk_osc_aon ),
+ .clk_src_aon_val_o ( clk_osc_aon_val )
+);
+
+logic vcmpp_aon_sync_n, rst_vcmpp_aon_n;
+
+// Reset De-Assert Sync
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_rst_vcmpp_aon_dasrt (
+ .clk_i ( clk_aon ),
+ .rst_ni ( vcmain_pok_por ),
+ .d_i ( 1'b1 ),
+ .q_o ( vcmpp_aon_sync_n )
+);
+
+assign rst_vcmpp_aon_n = scan_mode ? scan_reset_n : vcmpp_aon_sync_n;
+
+
+///////////////////////////////////////
+// IO Clock (Always ON)
+///////////////////////////////////////
+logic rst_io_clk_n, clk_io_pd_n;
+logic clk_src_io_en, clk_osc_io, clk_osc_io_val;
+
+assign rst_io_clk_n = vcmain_pok_por && vcc_pok;
+assign clk_io_pd_n = scan_mode || !deep_sleep;
+
+`ifdef AST_BYPASS_CLK
+logic clk_io_ext;
+assign clk_io_ext = clk_osc_byp_i.io;
+`endif
+
+assign clk_src_io_en = clk_src_io_en_i;
+
+io_clk u_io_clk (
+ .vcore_pok_h_i ( vcaon_pok_h ),
+ .clk_io_pd_ni ( clk_io_pd_n ),
+ .rst_io_clk_ni ( rst_io_clk_n ),
+ .clk_src_io_en_i ( clk_src_io_en ),
+ .scan_mode_i ( scan_mode ),
+ .io_osc_cal_i ( sys_io_osc_cal ),
+`ifdef AST_BYPASS_CLK
+ .clk_io_ext_i ( clk_io_ext ),
+`endif
+ .clk_src_io_o ( clk_osc_io ),
+ .clk_src_io_val_o ( clk_osc_io_val )
+);
+
+
+///////////////////////////////////////
+// AUDIO Clock (Always ON)
+///////////////////////////////////////
+logic rst_audio_clk_n, clk_audio_pd_n;
+logic clk_src_audio_en, clk_osc_audio, clk_osc_audio_val;
+
+assign rst_audio_clk_n = vcmain_pok_por && vcc_pok;
+assign clk_audio_pd_n = scan_mode || !deep_sleep;
+
+`ifdef AST_BYPASS_CLK
+logic clk_audio_ext;
+assign clk_audio_ext = clk_osc_byp_i.audio;
+`endif
+
+assign clk_src_audio_en = clk_src_audio_en_i;
+
+audio_clk u_audio_clk (
+ .vcore_pok_h_i ( vcaon_pok_h ),
+ .clk_audio_pd_ni ( clk_audio_pd_n ),
+ .rst_audio_clk_ni ( rst_audio_clk_n ),
+ .clk_src_audio_en_i ( clk_src_audio_en ),
+ .scan_mode_i ( scan_mode ),
+ .audio_osc_cal_i ( sys_io_osc_cal ),
+`ifdef AST_BYPASS_CLK
+ .clk_audio_ext_i ( clk_audio_ext ),
+`endif
+ .clk_src_audio_o ( clk_osc_audio ),
+ .clk_src_audio_val_o ( clk_osc_audio_val )
+);
+
+///////////////////////////////////////
+// AST Clocks Bypass
+///////////////////////////////////////
+logic clk_src_sys, clk_src_io, clk_src_usb, clk_src_aon;
+
+ast_clks_byp u_ast_clks_byp (
+ .vcaon_pok_i ( vcaon_pok ),
+ .deep_sleep_i ( deep_sleep ),
+ .clk_src_sys_en_i ( clk_src_sys_en_i ),
+ .clk_osc_sys_i ( clk_osc_sys ),
+ .clk_osc_sys_val_i ( clk_osc_sys_val ),
+ .clk_src_io_en_i ( clk_src_io_en_i ),
+ .clk_osc_io_i ( clk_osc_io ),
+ .clk_osc_io_val_i ( clk_osc_io_val ),
+ .clk_src_usb_en_i ( clk_src_usb_en_i ),
+ .clk_osc_usb_i ( clk_osc_usb ),
+ .clk_osc_usb_val_i ( clk_osc_usb_val ),
+ .clk_osc_aon_i ( clk_osc_aon ),
+ .clk_osc_aon_val_i ( clk_osc_aon_val ),
+ .clk_src_audio_en_i ( clk_src_audio_en_i ),
+ .clk_osc_audio_i ( clk_osc_audio ),
+ .clk_osc_audio_val_i ( clk_osc_audio_val ),
+ .clk_ast_ext_i ( clk_ast_ext_i ),
+ .io_clk_byp_req_i ( io_clk_byp_req_i ),
+ .all_clk_byp_req_i ( all_clk_byp_req_i ),
+ .ext_freq_is_96m_i ( ext_freq_is_96m_i ),
+ .io_clk_byp_ack_o ( io_clk_byp_ack_o ),
+ .all_clk_byp_ack_o ( all_clk_byp_ack_o ),
+ .clk_src_sys_o ( clk_src_sys ),
+ .clk_src_sys_val_o ( clk_src_sys_val_o ),
+ .clk_src_io_o ( clk_src_io ),
+ .clk_src_io_val_o ( clk_src_io_val_o ),
+ .clk_src_io_48m_o ( clk_src_io_48m_o ),
+ .clk_src_usb_o ( clk_src_usb ),
+ .clk_src_usb_val_o ( clk_src_usb_val_o ),
+ .clk_src_aon_o ( clk_src_aon ),
+ .clk_src_aon_val_o ( clk_src_aon_val_o ),
+ .clk_src_audio_o ( clk_src_audio ),
+ .clk_src_audio_val_o ( clk_src_audio_val_o )
+);
+
+// System source clock buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_src_sys_buf (
+ .clk_i ( clk_src_sys ),
+ .clk_o ( clk_src_sys_o )
+);
+
+// IO source clock buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_src_io_buf (
+ .clk_i ( clk_src_io ),
+ .clk_o ( clk_src_io_o )
+);
+
+// USB source clock buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_src_usb_buf (
+ .clk_i ( clk_src_usb ),
+ .clk_o ( clk_src_usb_o )
+);
+
+// AON source clock buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_src_aon_buf (
+ .clk_i ( clk_src_aon ),
+ .clk_o ( clk_src_aon_o )
+);
+
+
+// TO-DO(VSI): Add PLL output for new clocks: smc, ml, video
+// For DV test purpose as of now, smc/ml/video clock will just use the same clock as clk_src_syc.
+
+// SMC source clock buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_src_smc_buf (
+ .clk_i ( clk_src_sys ), // TO-DO(VSI): use the sys_clk for now. Change to SMC clock late.
+ .clk_o ( clk_src_smc_o )
+);
+
+assign clk_src_smc_val_o = clk_src_sys_val_o;
+
+// ML source clock buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_src_ml_buf (
+ .clk_i ( clk_src_sys ), // TO-DO(VSI):use the sys_clk for now. Change to ML clock late.
+ .clk_o ( clk_src_ml_o )
+);
+
+assign clk_src_ml_val_o = clk_src_sys_val_o;
+
+// video source clock buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_src_video_buf (
+ .clk_i ( clk_src_sys ), // TO-DO(VSI):use the sys_clk for now. Change to video clock late.
+ .clk_o ( clk_src_video_o )
+);
+
+assign clk_src_video_val_o = clk_src_sys_val_o;
+
+// audio source clock buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_src_audio_buf (
+ .clk_i ( clk_src_audio ),
+ .clk_o ( clk_src_audio_o )
+);
+
+///////////////////////////////////////
+// ADC (Always ON)
+///////////////////////////////////////
+adc #(
+ .AdcCnvtClks ( AdcCnvtClks ),
+ .AdcChannels ( AdcChannels ),
+ .AdcDataWidth ( AdcDataWidth )
+) u_adc (
+ .adc_a0_ai ( adc_a0_ai ),
+ .adc_a1_ai ( adc_a1_ai ),
+ .adc_chnsel_i ( adc_chnsel_i[AdcChannels-1:0] ),
+ .adc_pd_i ( adc_pd_i ),
+ .clk_adc_i ( clk_ast_adc_i ),
+ .rst_adc_ni ( rst_ast_adc_ni ),
+ .adc_d_o ( adc_d_o[AdcDataWidth-1:0] ),
+ .adc_d_val_o ( adc_d_val_o )
+);
+
+
+///////////////////////////////////////
+// Entropy (Always ON)
+///////////////////////////////////////
+localparam int EntropyRateWidth = 4;
+logic [EntropyRateWidth-1:0] entropy_rate;
+logic vcmain_pok_por_sys, rst_src_sys_n;
+
+// Sync clk_src_sys_jen_i to clk_sys
+prim_mubi4_sync #(
+ .NumCopies ( 1 ),
+ .AsyncOn ( 1 ),
+ .StabilityCheck ( 1 ),
+ .ResetValue (prim_mubi_pkg::MuBi4False )
+) u_jitter_en_sync (
+ .clk_i ( clk_sys ),
+ .rst_ni ( rst_src_sys_n ),
+ .mubi_i ( clk_src_sys_jen_i ),
+ .mubi_o ( {clk_src_sys_jen} )
+);
+
+// Reset De-Assert Sync
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_rst_sys_dasrt (
+ .clk_i ( clk_sys ),
+ .rst_ni ( vcmain_pok_por ),
+ .d_i ( 1'b1 ),
+ .q_o ( vcmain_pok_por_sys )
+);
+
+assign rst_src_sys_n = scan_mode ? scan_reset_n : vcmain_pok_por_sys;
+
+`ifndef SYNTHESIS
+logic [EntropyRateWidth-1:0] dv_entropy_rate_value;
+
+initial begin : erate_plusargs
+ dv_entropy_rate_value = EntropyRateWidth'($urandom_range(0, (2**EntropyRateWidth -1)));
+ void'($value$plusargs("entropy_rate_value=%0d", dv_entropy_rate_value));
+ `ASSERT_I(DvErateValueCheck, dv_entropy_rate_value inside {[0:(2**EntropyRateWidth -1)]})
+end
+
+assign entropy_rate = dv_entropy_rate_value;
+`else
+assign entropy_rate = EntropyRateWidth'(5);
+`endif
+
+ast_entropy #(
+ .EntropyRateWidth ( EntropyRateWidth )
+) u_entropy (
+ .entropy_rsp_i ( entropy_rsp_i ),
+ .entropy_rate_i ( entropy_rate[EntropyRateWidth-1:0] ),
+ .clk_ast_es_i ( clk_ast_es_i ),
+ .rst_ast_es_ni ( rst_ast_es_ni ),
+ .clk_src_sys_i ( clk_sys ),
+ .rst_src_sys_ni ( rst_src_sys_n ),
+ .clk_src_sys_val_i ( clk_src_sys_val_o ),
+ .clk_src_sys_jen_i ( prim_mubi_pkg::mubi4_test_true_loose(clk_src_sys_jen) ),
+ .entropy_req_o ( entropy_req_o )
+);
+
+
+///////////////////////////////////////
+// RNG (Always ON)
+///////////////////////////////////////
+ast_pkg::ast_dif_t ot1_alert_src;
+
+rng #(
+ .EntropyStreams ( EntropyStreams )
+) u_rng (
+ .clk_i ( clk_ast_tlul_i ),
+ .rst_ni ( rst_ast_tlul_ni ),
+ .clk_ast_rng_i ( clk_ast_rng_i ),
+ .rst_ast_rng_ni ( rst_ast_rng_ni ),
+ .rng_en_i ( rng_en_i ),
+ .rng_fips_i ( rng_fips_i ),
+ .scan_mode_i ( scan_mode ),
+ .rng_b_o ( rng_b_o[EntropyStreams-1:0] ),
+ .rng_val_o ( rng_val_o )
+);
+
+
+///////////////////////////////////////
+// Alerts (Always ON)
+///////////////////////////////////////
+ast_pkg::ast_dif_t as_alert_src;
+ast_pkg::ast_dif_t cg_alert_src;
+ast_pkg::ast_dif_t gd_alert_src;
+ast_pkg::ast_dif_t ts_alert_hi_src;
+ast_pkg::ast_dif_t ts_alert_lo_src;
+ast_pkg::ast_dif_t ot0_alert_src;
+ast_pkg::ast_dif_t ot2_alert_src;
+ast_pkg::ast_dif_t ot3_alert_src;
+ast_pkg::ast_dif_t ot4_alert_src;
+ast_pkg::ast_dif_t ot5_alert_src;
+
+
+// Active Shield (AS)
+///////////////////////////////////////
+ast_alert u_alert_as (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( as_alert_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::AsSel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::AsSel] ),
+ .alert_req_o ( alert_req_o.alerts[ast_pkg::AsSel] )
+);
+
+// Clock Glitch (CG)
+///////////////////////////////////////
+ast_alert u_alert_cg (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( cg_alert_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::CgSel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::CgSel] ),
+ .alert_req_o ( alert_req_o.alerts[ast_pkg::CgSel] )
+);
+
+// Glitch Detector (GD)
+///////////////////////////////////////
+ast_alert u_alert_gd (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( gd_alert_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::GdSel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::GdSel] ),
+ .alert_req_o ( alert_req_o.alerts[ast_pkg::GdSel] )
+);
+
+// Temprature Sensor High (TS Hi)
+///////////////////////////////////////
+ast_alert u_alert_ts_hi (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( ts_alert_hi_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::TsHiSel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::TsHiSel] ),
+ .alert_req_o ( alert_req_o.alerts[ast_pkg::TsHiSel] )
+);
+
+// Temprature Sensor Low (TS Lo)
+///////////////////////////////////////
+ast_alert u_alert_ts_lo (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( ts_alert_lo_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::TsLoSel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::TsLoSel] ),
+ .alert_req_o ( alert_req_o.alerts[ast_pkg::TsLoSel] )
+);
+
+// Other-0 Alert (OT0)
+///////////////////////////////////////
+ast_alert u_alert_ot0 (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( ot0_alert_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot0Sel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot0Sel] ),
+ .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot0Sel] )
+); // of u_alert_ot0
+
+// Other-1 Alert (OT1)
+///////////////////////////////////////
+ast_alert u_alert_ot1 (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( ot1_alert_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot1Sel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot1Sel] ),
+ .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot1Sel] )
+); // of u_alert_ot1
+
+// Other-2 Alert (OT2)
+///////////////////////////////////////
+ast_alert u_alert_ot2 (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( ot2_alert_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[Ot2Sel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[Ot2Sel] ),
+ .alert_req_o ( alert_req_o.alerts[Ot2Sel] )
+); // of u_alert_ot2
+
+// Other-3 Alert (OT3)
+///////////////////////////////////////
+ast_alert u_alert_ot3 (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( ot3_alert_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[Ot3Sel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[Ot3Sel] ),
+ .alert_req_o ( alert_req_o.alerts[Ot3Sel] )
+); // of u_alert_ot3
+
+// Other-4 Alert (OT4)
+///////////////////////////////////////
+ast_alert u_alert_ot4 (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( ot4_alert_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot4Sel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot4Sel] ),
+ .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot4Sel] )
+); // of u_alert_ot4
+
+// Other-5 Alert (OT5)
+///////////////////////////////////////
+ast_alert u_alert_ot5 (
+ .clk_i ( clk_ast_alert_i ),
+ .rst_ni ( rst_ast_alert_ni ),
+ .alert_src_i ( ot5_alert_src ),
+ .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot5Sel] ),
+ .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot5Sel] ),
+ .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot5Sel] )
+); // of u_alert_ot5
+
+// Alerts Open-Source Selection
+////////////////////////////////////////
+assign as_alert_src = '{p: 1'b0, n: 1'b1};
+assign cg_alert_src = '{p: 1'b0, n: 1'b1};
+assign gd_alert_src = '{p: 1'b0, n: 1'b1};
+assign ts_alert_hi_src = '{p: 1'b0, n: 1'b1};
+assign ts_alert_lo_src = '{p: 1'b0, n: 1'b1};
+assign ot1_alert_src = '{p: 1'b0, n: 1'b1};
+assign ot2_alert_src = '{p: 1'b0, n: 1'b1};
+assign ot3_alert_src = '{p: 1'b0, n: 1'b1};
+assign ot4_alert_src = '{p: 1'b0, n: 1'b1};
+assign ot5_alert_src = '{p: 1'b0, n: 1'b1};
+
+
+///////////////////////////////////////
+// AST Registers (Always ON)
+///////////////////////////////////////
+ast_reg_pkg::ast_reg2hw_t reg2hw; // Write (To HW)
+ast_reg_pkg::ast_hw2reg_t hw2reg; // Read (From HW)
+logic intg_err;
+
+ast_reg_top u_reg (
+ .clk_i ( clk_ast_tlul_i ),
+ .rst_ni ( rst_ast_tlul_ni ),
+ .tl_i ( tl_i ),
+ .tl_o ( tl_o ),
+ .reg2hw ( reg2hw ),
+ .hw2reg ( hw2reg ),
+ .intg_err_o ( intg_err ),
+ .devmode_i ( 1'b1 )
+);
+
+
+///////////////////////////////////////
+// REGAL Register
+///////////////////////////////////////
+logic regal_rst_n;
+assign regal_rst_n = rst_ast_tlul_ni;
+
+logic regal_we;
+logic [32-1:0] regal, regal_di;
+
+assign regal_we = reg2hw.regal.qe;
+assign regal_di = reg2hw.regal.q;
+assign hw2reg.regal.d = regal;
+
+// REGAL & AST init done indication
+always_ff @( posedge clk_ast_tlul_i, negedge regal_rst_n ) begin
+ if ( !regal_rst_n ) begin
+ regal <= ast_reg_pkg::AST_REGAL_RESVAL;
+ ast_init_done_o <= prim_mubi_pkg::MuBi4False;
+ end else if ( regal_we ) begin
+ regal <= regal_di;
+ ast_init_done_o <= prim_mubi_pkg::MuBi4True;
+ end
+end
+
+always_ff @( posedge clk_ast_tlul_i, negedge rst_ast_tlul_ni ) begin
+ if ( !rst_ast_tlul_ni ) begin
+ sys_io_osc_cal <= 1'b0;
+ end else if ( regal_we ) begin
+ sys_io_osc_cal <= 1'b1;
+ end
+end
+
+always_ff @( posedge clk_ast_tlul_i, negedge vcaon_pok_por ) begin
+ if ( !vcaon_pok_por ) begin
+ usb_osc_cal <= 1'b0;
+ end else if ( regal_we ) begin
+ usb_osc_cal <= 1'b1;
+ end
+end
+
+always_ff @( posedge clk_ast_tlul_i, negedge vcaon_pok ) begin
+ if ( !vcaon_pok ) begin
+ aon_osc_cal <= 1'b0;
+ end else if ( regal_we ) begin
+ aon_osc_cal <= 1'b1;
+ end
+end
+
+// TLUL Integrity Error
+assign ot0_alert_src = '{p: intg_err, n: !intg_err};
+
+// USB PU-P and PU-N value selection
+assign usb_io_pu_cal_o = UsbCalibWidth'(1 << (UsbCalibWidth[5-1:0]/2));
+
+
+///////////////////////////////////////
+// DFT (Main | Always ON)
+///////////////////////////////////////
+ast_dft u_ast_dft (
+ .obs_ctrl_o ( obs_ctrl_o ),
+ .ast2padmux_o ( ast2padmux_o[Ast2PadOutWidth-1:0] ),
+ .dpram_rmf_o ( dpram_rmf_o ),
+ .dpram_rml_o ( dpram_rml_o ),
+ .spram_rm_o ( spram_rm_o ),
+ .sprgf_rm_o ( sprgf_rm_o ),
+ .sprom_rm_o ( sprom_rm_o )
+);
+
+
+////////////////////////////////////////
+// DFT Misc Logic
+////////////////////////////////////////
+`ifdef ANALOGSIM
+assign ast2pad_t0_ao = 0.0;
+assign ast2pad_t1_ao = 0.1;
+`else
+assign ast2pad_t0_ao = 1'bz;
+assign ast2pad_t1_ao = 1'bz;
+`endif
+
+
+////////////////
+// Assertions //
+////////////////
+
+// Clocks
+`ASSERT_KNOWN(ClkSrcAonKnownO_A, clk_src_aon_o, 1, ast_pwst_o.aon_pok)
+`ASSERT_KNOWN(ClkSrcAonValKnownO_A, clk_src_aon_val_o, clk_src_aon_o, rst_aon_clk_n)
+`ASSERT_KNOWN(ClkSrcIoKnownO_A, clk_src_io_o, 1, ast_pwst_o.main_pok)
+`ASSERT_KNOWN(ClkSrcIoValKnownO_A, clk_src_io_val_o, clk_src_io_o, rst_io_clk_n)
+`ASSERT_KNOWN(ClkSrcIo48mKnownO_A, clk_src_io_48m_o, clk_src_io_o, rst_io_clk_n)
+`ASSERT_KNOWN(ClkSrcSysKnownO_A, clk_src_sys_o, 1, ast_pwst_o.main_pok)
+`ASSERT_KNOWN(ClkSrcSysValKnownO_A, clk_src_sys_val_o, clk_src_sys_o, rst_sys_clk_n)
+`ASSERT_KNOWN(ClkSrcUsbKnownO_A, clk_src_usb_o, 1, ast_pwst_o.main_pok)
+`ASSERT_KNOWN(ClkSrcUsbValKnownO_A, clk_src_usb_val_o, clk_src_usb_o, rst_usb_clk_n)
+//
+`ASSERT_KNOWN(UsbIoPuCalKnownO_A, usb_io_pu_cal_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+`ASSERT_KNOWN(LcClkBypAckEnKnownO_A, io_clk_byp_ack_o, clk_ast_tlul_i, rst_ast_tlul_ni)
+`ASSERT_KNOWN(AllClkBypAckEnKnownO_A, all_clk_byp_ack_o, clk_ast_tlul_i, rst_ast_tlul_ni)
+// ADC
+`ASSERT_KNOWN(AdcDKnownO_A, adc_d_o, clk_ast_adc_i, rst_ast_adc_ni)
+`ASSERT_KNOWN(AdcDValKnownO_A, adc_d_val_o, clk_ast_adc_i, rst_ast_adc_ni)
+// RNG
+`ASSERT_KNOWN(RngBKnownO_A, rng_b_o, clk_ast_rng_i, rst_ast_rng_ni)
+`ASSERT_KNOWN(RngValKnownO_A, rng_val_o, clk_ast_rng_i, rst_ast_rng_ni)
+// TLUL
+`ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid, clk_ast_tlul_i, rst_ast_tlul_ni)
+`ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready, clk_ast_tlul_i, rst_ast_tlul_ni)
+//
+`ASSERT_KNOWN(InitDoneKnownO_A, ast_init_done_o, clk_ast_tlul_i, rst_ast_tlul_ni)
+// POs
+`ASSERT_KNOWN(VcaonPokKnownO_A, ast_pwst_o.aon_pok, clk_src_aon_o, por_ni)
+`ASSERT_KNOWN(VcmainPokKnownO_A, ast_pwst_o.main_pok, clk_src_aon_o, por_ni)
+`ASSERT_KNOWN(VioaPokKnownO_A, ast_pwst_o.io_pok[0], clk_src_aon_o, por_ni)
+`ASSERT_KNOWN(ViobPokKnownO_A, ast_pwst_o.io_pok[1], clk_src_aon_o, por_ni)
+`ASSERT_KNOWN(VcaonPokHKnownO_A, ast_pwst_h_o.aon_pok, clk_src_aon_o, por_ni)
+`ASSERT_KNOWN(VcmainPokHKnownO_A, ast_pwst_h_o.main_pok, clk_src_aon_o, por_ni)
+`ASSERT_KNOWN(VioaPokHKnownO_A, ast_pwst_h_o.io_pok[0], clk_src_aon_o, por_ni)
+`ASSERT_KNOWN(ViobPokHKnownO_A, ast_pwst_h_o.io_pok[1], clk_src_aon_o, por_ni)
+// FLASH/OTP
+`ASSERT_KNOWN(FlashPowerDownKnownO_A, flash_power_down_h_o, 1, ast_pwst_o.main_pok)
+`ASSERT_KNOWN(FlashPowerReadyKnownO_A, flash_power_ready_h_o, 1, ast_pwst_o.main_pok)
+`ASSERT_KNOWN(OtpPowerSeqKnownO_A, otp_power_seq_h_o, 1, ast_pwst_o.main_pok)
+//
+// ES
+`ASSERT_KNOWN(EntropyReeqKnownO_A, entropy_req_o, clk_ast_es_i,rst_ast_es_ni)
+// Alerts
+`ASSERT_KNOWN(AlertReqKnownO_A, alert_req_o, clk_ast_alert_i, rst_ast_alert_ni)
+// DPRAM/SPRAM
+`ASSERT_KNOWN(DpramRmfKnownO_A, dpram_rmf_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+`ASSERT_KNOWN(DpramRmlKnownO_A, dpram_rml_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+`ASSERT_KNOWN(SpramRmKnownO_A, spram_rm_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+`ASSERT_KNOWN(SprgfRmKnownO_A, sprgf_rm_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+`ASSERT_KNOWN(SpromRmKnownO_A, sprom_rm_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+// DFT
+`ASSERT_KNOWN(Ast2PadmuxKnownO_A, ast2padmux_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+// SCAN
+`ASSERT_KNOWN(DftScanMdKnownO_A, dft_scan_md_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+`ASSERT_KNOWN(ScanShiftEnKnownO_A, scan_shift_en_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+`ASSERT_KNOWN(ScanResetKnownO_A, scan_reset_no, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+`ASSERT_KNOWN(FlashBistEnKnownO_A, flash_bist_en_o, clk_ast_tlul_i, ast_pwst_o.aon_pok)
+
+// Alert assertions for reg_we onehot check
+`ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(RegWeOnehot_A,
+ u_reg, alert_req_o.alerts[ast_pkg::Ot0Sel].p, , , clk_ast_alert_i, rst_ast_alert_ni)
+
+
+/////////////////////
+// Unused Signals //
+/////////////////////
+logic unused_sigs;
+
+assign unused_sigs = ^{ clk_ast_usb_i,
+ rst_ast_usb_ni,
+ sns_spi_ext_clk_i,
+ sns_clks_i,
+ sns_rsts_i,
+ intg_err,
+ shift_en,
+ main_env_iso_en_i,
+ rst_vcmpp_aon_n,
+ padmux2ast_i[Pad2AstInWidth-1:0],
+ dft_strap_test_i.valid,
+ dft_strap_test_i.straps[1:0],
+ lc_dft_en_i[3:0],
+ fla_obs_i[8-1:0],
+ otp_obs_i[8-1:0],
+ otm_obs_i[8-1:0],
+ usb_obs_i,
+ reg2hw.rega0,
+ reg2hw.rega1,
+ reg2hw.rega2,
+ reg2hw.rega3,
+ reg2hw.rega4,
+ reg2hw.rega5,
+ reg2hw.rega6,
+ reg2hw.rega7,
+ reg2hw.rega8,
+ reg2hw.rega9,
+ reg2hw.rega10,
+ reg2hw.rega11,
+ reg2hw.rega12,
+ reg2hw.rega13,
+ reg2hw.rega14,
+ reg2hw.rega15,
+ reg2hw.rega16,
+ reg2hw.rega17,
+ reg2hw.rega18,
+ reg2hw.rega19,
+ reg2hw.rega20,
+ reg2hw.rega21,
+ reg2hw.rega22,
+ reg2hw.rega23,
+ reg2hw.rega24,
+ reg2hw.rega25,
+ reg2hw.rega26,
+ reg2hw.rega27,
+ reg2hw.rega28,
+ reg2hw.rega29,
+ reg2hw.rega30,
+ reg2hw.rega31,
+ reg2hw.rega32,
+ reg2hw.rega33,
+ reg2hw.rega34,
+ reg2hw.rega35,
+ reg2hw.rega36,
+ reg2hw.rega37,
+ reg2hw.regb // [0:3]
+ };
+
+endmodule : ast
diff --git a/hw/top_sencha/ip/ast/rtl/ast_alert.sv b/hw/top_sencha/ip/ast/rtl/ast_alert.sv
new file mode 100644
index 0000000..39da8c9
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast_alert.sv
@@ -0,0 +1,85 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: ast_alert
+// *Module Description: AST Alert
+//############################################################################
+
+module ast_alert (
+ input clk_i,
+ input rst_ni,
+ input ast_pkg::ast_dif_t alert_src_i,
+ input ast_pkg::ast_dif_t alert_ack_i,
+ input ast_pkg::ast_dif_t alert_trig_i,
+ output ast_pkg::ast_dif_t alert_req_o
+);
+
+// Unpack inputs
+logic p_alert_src, n_alert_src;
+assign p_alert_src = alert_src_i.p;
+assign n_alert_src = alert_src_i.n;
+
+logic p_alert_ack, n_alert_ack;
+assign p_alert_ack = alert_ack_i.p;
+assign n_alert_ack = alert_ack_i.n;
+
+logic p_alert_trig, n_alert_trig;
+assign p_alert_trig = alert_trig_i.p;
+assign n_alert_trig = alert_trig_i.n;
+
+// Pack outputs
+logic p_alert_req, n_alert_req;
+
+assign alert_req_o.p = p_alert_req;
+assign alert_req_o.n = n_alert_req;
+
+// P Alert
+logic p_alert, set_p_alert, clr_p_alert;
+
+assign set_p_alert = p_alert_src || p_alert_trig;
+assign clr_p_alert = !set_p_alert && p_alert_ack;
+
+always_ff @( posedge clk_i, negedge rst_ni ) begin
+ if ( !rst_ni ) begin
+ p_alert <= 1'b0;
+ end else if ( set_p_alert ) begin
+ p_alert <= 1'b1;
+ end else if ( clr_p_alert ) begin
+ p_alert <= 1'b0;
+ end
+end
+
+assign p_alert_req = p_alert;
+
+// N Alert
+logic n_alert, set_n_alert, clr_n_alert;
+
+assign set_n_alert = !(n_alert_src && n_alert_trig);
+assign clr_n_alert = !(set_n_alert || n_alert_ack);
+
+always_ff @( posedge clk_i, negedge rst_ni ) begin
+ if ( !rst_ni ) begin
+ n_alert <= 1'b1;
+ end else if ( set_n_alert ) begin
+ n_alert <= 1'b0;
+ end else if ( clr_n_alert ) begin
+ n_alert <= 1'b1;
+ end
+end
+
+assign n_alert_req = n_alert;
+
+endmodule : ast_alert
diff --git a/hw/top_sencha/ip/ast/rtl/ast_bhv_pkg.sv b/hw/top_sencha/ip/ast/rtl/ast_bhv_pkg.sv
new file mode 100644
index 0000000..e9508ac
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast_bhv_pkg.sv
@@ -0,0 +1,58 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: ast_bhv_pkg
+// *Module Description: AST Behavioral Package
+//############################################################################
+`ifdef __AST_BHV_PKG_SV
+`else
+`define __AST_BHV_PKG_SV
+
+package ast_bhv_pkg;
+
+ /////////////////////////////////
+ // Delay Parameters from Spec
+ /////////////////////////////////
+`ifndef SYNTHESIS
+ // POKs
+ parameter time VCC_POK_RDLY = 3us;
+ parameter time VCC_POK_FDLY = 500ns;
+ parameter time VCAON_POK_RDLY = 3us;
+ parameter time VCAON_POK_FDLY = 500ns;
+ parameter time VCMAIN_POK_RDLY = 3us;
+ parameter time VCMAIN_POK_FDLY = 500ns;
+ parameter time VIO_POK_RDLY = 3us;
+ parameter time VIO_POK_FDLY = 500ns;
+ // Main Regulator
+ parameter time MPVCC_RDLY = 5us;
+ parameter time MPVCC_FDLY = 100ns;
+ parameter time MPPD_RDLY = 50us;
+ parameter time MPPD_FDLY = 1us;
+ // Clocks
+ parameter time SYS_EN_RDLY = 5us;
+ parameter time USB_EN_RDLY = 5us;
+ // Reduced for simulation from 50ms
+ parameter time USB_VAL_RDLY = 80ns; // 50ms
+ parameter time USB_VAL_FDLY = 80ns;
+ parameter time IO_EN_RDLY = 5us;
+ parameter time AON_EN_RDLY = 5us;
+ parameter time RNG_EN_RDLY = 5us;
+`endif // of SYNTHESIS
+ // ADC
+ parameter int unsigned AdcCnvtClks = 22;
+
+endpackage // of ast_bhv_pkg
+`endif // of __AST_BHV_PKG_SV
diff --git a/hw/top_sencha/ip/ast/rtl/ast_clks_byp.sv b/hw/top_sencha/ip/ast/rtl/ast_clks_byp.sv
new file mode 100644
index 0000000..bf8f032
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast_clks_byp.sv
@@ -0,0 +1,775 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- //
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED.
+//
+//############################################################################
+// *Name: ast_clks_byp
+// *Module Description: AST Clocks Bypass
+//############################################################################
+
+`include "prim_assert.sv"
+
+module ast_clks_byp (
+ input vcaon_pok_i, // VCAON POK
+ input deep_sleep_i, // Deep Sleep (main regulator & switch are off)
+ input clk_src_sys_en_i, // SYS Source Clock Enable
+ input clk_osc_sys_i, // SYS Oscillator Clock
+ input clk_osc_sys_val_i, // SYS Oscillator Clock Valid
+ input clk_src_io_en_i, // IO Source Clock Enable
+ input clk_osc_io_i, // IO Oscillator Clock
+ input clk_osc_io_val_i, // IO Oscillator Clock Valid
+ input clk_src_usb_en_i, // USB Source Clock Enable
+ input clk_osc_usb_i, // USB Oscillator Clock
+ input clk_osc_usb_val_i, // USB Oscillator Clock Valid
+ input clk_osc_aon_i, // AON Oscillator Clock
+ input clk_osc_aon_val_i, // AON Oscillator Clock Valid
+ input clk_src_audio_en_i, // IO Source Clock Enable
+ input clk_osc_audio_i, // AUDIO Oscillator Clock
+ input clk_osc_audio_val_i, // AUDIO Oscillator Clock Valid
+ input clk_ast_ext_i, // External Clock
+ input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // External IO clock mux for OTP bootstrap
+ input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // External all clock mux override
+ input prim_mubi_pkg::mubi4_t ext_freq_is_96m_i, // External Clock Frequecy is 96MHz (else 48MHz)
+ output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o, // Switch IO clock to External clock
+ output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o, // Switch all clocks to External clock
+ output logic clk_src_sys_o, // SYS Source Clock
+ output logic clk_src_sys_val_o, // SYS Source Clock Valid
+ output logic clk_src_io_o, // IO Source Clock
+ output logic clk_src_io_val_o, // IO Source Clock Valid
+ output prim_mubi_pkg::mubi4_t clk_src_io_48m_o, // IO Source Clock is 48Mhz
+ output logic clk_src_usb_o, // USB Source Clock
+ output logic clk_src_usb_val_o, // USB Source Clock Valid
+ output logic clk_src_aon_o, // AON Source Clock
+ output logic clk_src_aon_val_o, // AON Source Clock Valid
+ output logic clk_src_audio_o, // AON Source Clock
+ output logic clk_src_audio_val_o // AON Source Clock Valid
+);
+
+logic scan_mode_i, scan_reset_ni;
+
+assign scan_mode_i = 1'b0;
+assign scan_reset_ni = 1'b1;
+
+////////////////////////////////////////
+// Local AON clock buffer
+////////////////////////////////////////
+logic clk_aon, rst_aon_n;
+
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_aon_buf (
+ .clk_i ( clk_src_aon_o ),
+ .clk_o ( clk_aon )
+);
+
+logic vcaon_pok; // For Spyglass waiver!!!
+
+assign vcaon_pok = vcaon_pok_i;
+assign rst_aon_n = scan_mode_i ? scan_reset_ni : vcaon_pok;
+
+
+////////////////////////////////////////
+// External Clocks Generation
+////////////////////////////////////////
+// Enable External Clock for SW Bypass
+logic rst_sw_clk_byp_en, sw_all_clk_byp, sw_io_clk_byp;
+
+always_ff @( posedge clk_aon, negedge rst_aon_n ) begin
+ if ( !rst_aon_n ) begin
+ rst_sw_clk_byp_en <= 1'b0;
+ end else if ( sw_all_clk_byp || sw_io_clk_byp ) begin
+ rst_sw_clk_byp_en <= 1'b1;
+ end
+end
+
+logic rst_sw_ckbpe_n, clk_ast_ext_scn, sw_clk_byp_en;
+
+assign rst_sw_ckbpe_n = scan_mode_i ? scan_reset_ni : rst_sw_clk_byp_en;
+assign clk_ast_ext_scn = scan_mode_i ? clk_osc_sys_i : clk_ast_ext_i;
+
+// De-assert with external clock input
+always_ff @( negedge clk_ast_ext_scn, negedge rst_sw_ckbpe_n ) begin
+ if ( !rst_sw_ckbpe_n ) begin
+ sw_clk_byp_en <= 1'b0;
+ end else begin
+ sw_clk_byp_en <= 1'b1;
+ end
+end
+
+logic clk_ext_en, clk_ext_scn;
+
+assign clk_ext_en = sw_clk_byp_en;
+assign clk_ext_scn = scan_mode_i ? clk_osc_sys_i : clk_ast_ext_i && clk_ext_en;
+
+// Local EXT clock buffer
+////////////////////////////////////////
+logic clk_ext;
+
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_ext_buf (
+ .clk_i ( clk_ext_scn ),
+ .clk_o ( clk_ext )
+);
+
+logic rst_aon_n_exda, rst_aon_exda_n;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_rst_aon_n_exda_sync (
+ .clk_i ( clk_ext ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( 1'b1 ),
+ .q_o ( rst_aon_n_exda )
+);
+
+assign rst_aon_exda_n = scan_mode_i ? scan_reset_ni : rst_aon_n_exda;
+
+// External USB & AON clocks genaration
+////////////////////////////////////////
+logic clk_src_ext_usb, ext_freq_is_96m, ext_freq_is_96m_sync;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ // Assume external clock is 96Hhz on reset
+ .ResetValue ( 1'b1 )
+) u_no_scan_ext_freq_is_96m_sync (
+ .clk_i ( clk_ext ),
+ .rst_ni ( rst_aon_exda_n ),
+ .d_i ( ext_freq_is_96m ),
+ .q_o ( ext_freq_is_96m_sync )
+);
+
+prim_clock_div #(
+ .Divisor( 2 )
+) u_no_scan_clk_ext_d1ord2 (
+ .clk_i ( clk_ext ),
+ .rst_ni ( rst_aon_exda_n ),
+ .step_down_req_i( !ext_freq_is_96m_sync ),
+ .step_down_ack_o ( ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( clk_src_ext_usb )
+);
+
+logic clk_ext_aon, clk_ext_aon_val;
+
+assign clk_ext_aon_val = 1'b1; // Always ON clock
+
+prim_clock_div #(
+ .Divisor( 240 )
+) u_no_scan_clk_usb_div240_div (
+ .clk_i ( clk_src_ext_usb ),
+ .rst_ni ( rst_aon_exda_n ),
+ .step_down_req_i( 1'b0 ),
+ .step_down_ack_o ( ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( clk_ext_aon )
+);
+
+
+////////////////////////////////////////
+// Deep-Sleep/Enables Gators
+////////////////////////////////////////
+
+// Deep-Sleep Sync to External clcok
+////////////////////////////////////////
+logic deep_sleep, deep_sleep_n;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_deep_sleep_sync (
+ .clk_i ( clk_ext ),
+ .rst_ni ( rst_aon_exda_n ),
+ .d_i ( deep_sleep_i ),
+ .q_o ( deep_sleep )
+);
+
+assign deep_sleep_n = !deep_sleep;
+
+// SYS External Clock Enable
+////////////////////////////////////////
+logic clk_ext_sys, clk_ext_sys_en, clk_ext_sys_val;
+logic clk_src_sys_en;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_clk_src_sys_en_sync (
+ .clk_i ( clk_ext ),
+ .rst_ni ( rst_aon_exda_n ),
+ .d_i ( clk_src_sys_en_i ),
+ .q_o ( clk_src_sys_en )
+);
+
+assign clk_ext_sys_en = deep_sleep_n && clk_src_sys_en;
+assign clk_ext_sys_val = clk_ext_sys_en;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1)
+) u_clk_ext_sys_ckgt (
+ .clk_i ( clk_ext ),
+ .en_i ( clk_ext_sys_en ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( clk_ext_sys )
+);
+
+// IO External Clock Enable
+////////////////////////////////////////
+logic clk_ext_io, clk_ext_io_en, clk_ext_io_val;
+logic clk_src_io_en;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_clk_src_io_en_sync (
+ .clk_i ( clk_ext ),
+ .rst_ni ( rst_aon_exda_n ),
+ .d_i ( clk_src_io_en_i ),
+ .q_o ( clk_src_io_en )
+);
+
+assign clk_ext_io_en = deep_sleep_n && clk_src_io_en;
+assign clk_ext_io_val = clk_ext_io_en;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1)
+) u_clk_ext_io_ckgt (
+ .clk_i ( clk_ext ),
+ .en_i ( clk_ext_io_en ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( clk_ext_io )
+);
+
+// USB External Clock Enable
+////////////////////////////////////////
+logic clk_ext_usb, clk_ext_usb_en, clk_ext_usb_val;
+logic clk_src_usb_en;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_clk_src_usb_en_sync (
+ .clk_i ( clk_ext ),
+ .rst_ni ( rst_aon_exda_n ),
+ .d_i ( clk_src_usb_en_i ),
+ .q_o ( clk_src_usb_en )
+);
+
+assign clk_ext_usb_en = deep_sleep_n && clk_src_usb_en;
+assign clk_ext_usb_val = clk_ext_usb_en;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1)
+) u_clk_ext_usb_ckgt (
+ .clk_i ( clk_src_ext_usb ),
+ .en_i ( clk_ext_usb_en ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( clk_ext_usb )
+);
+
+// AUDIO External Clock Enable
+////////////////////////////////////////
+logic clk_ext_audio, clk_ext_audio_en, clk_ext_audio_val;
+logic clk_src_audio_en;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_clk_src_audio_en_sync (
+ .clk_i ( clk_ext ),
+ .rst_ni ( rst_aon_exda_n ),
+ .d_i ( clk_src_audio_en_i ),
+ .q_o ( clk_src_audio_en )
+);
+
+assign clk_ext_audio_en = deep_sleep_n && clk_src_audio_en;
+assign clk_ext_audio_val = clk_ext_audio_en;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1)
+) u_clk_ext_audio_ckgt (
+ .clk_i ( clk_ext ),
+ .en_i ( clk_ext_audio_en ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( clk_ext_audio )
+);
+////////////////////////////////////////
+// SW Bypass select logic
+////////////////////////////////////////
+// Sync to local AON clock
+prim_mubi_pkg::mubi4_t ot_io_clk_byp_req, ot_all_clk_byp_req, ot_ext_freq_is_96m;
+
+prim_mubi4_sync #(
+ .StabilityCheck ( 1 ),
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_io_clk_byp_req (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .mubi_i ( io_clk_byp_req_i ),
+ .mubi_o ( {ot_io_clk_byp_req} )
+);
+
+prim_mubi4_sync #(
+ .StabilityCheck ( 1 ),
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_all_clk_byp_req (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .mubi_i ( all_clk_byp_req_i ),
+ .mubi_o ( {ot_all_clk_byp_req} )
+);
+
+prim_mubi4_sync #(
+ .StabilityCheck ( 1 ),
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_ext_freq_is_96m (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .mubi_i ( ext_freq_is_96m_i ),
+ .mubi_o ( {ot_ext_freq_is_96m} )
+);
+
+// Decode logic
+logic ot_all_clk_byp, ot_sys_clk_byp, ot_io_clk_byp, ot_usb_clk_byp, ot_aon_clk_byp, ot_audio_clk_byp;
+
+prim_mubi4_dec u_all_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_all_clk_byp ) );
+prim_mubi4_dec u_sys_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_sys_clk_byp ) );
+prim_mubi4_dec u_io_byp_sel ( .mubi_i ( ot_io_clk_byp_req ), .mubi_dec_o ( ot_io_clk_byp ) );
+prim_mubi4_dec u_usb_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_usb_clk_byp ) );
+prim_mubi4_dec u_aon_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_aon_clk_byp ) );
+prim_mubi4_dec u_audio_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_audio_clk_byp ) );
+
+// De-Glitch selects (decode "noise")
+logic sw_sys_clk_byp, sw_usb_clk_byp, sw_aon_clk_byp, sw_exfr_is_96m, sw_audio_clk_byp;
+
+prim_flop #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_sw_all_clk_byp_dgl (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( ot_all_clk_byp ),
+ .q_o ( sw_all_clk_byp )
+);
+
+prim_flop #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_sw_sys_clk_byp_dgl (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( ot_sys_clk_byp ),
+ .q_o ( sw_sys_clk_byp )
+);
+
+prim_flop #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_sw_io_clk_byp_dgl (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( ot_io_clk_byp ),
+ .q_o ( sw_io_clk_byp )
+);
+
+prim_flop #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_sw_usb_clk_byp_dgl (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( ot_usb_clk_byp ),
+ .q_o ( sw_usb_clk_byp )
+);
+
+prim_flop #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_sw_aon_clk_byp_dgl (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( ot_aon_clk_byp ),
+ .q_o ( sw_aon_clk_byp )
+);
+
+prim_flop #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_sw_exfr_is_96m_dgl (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( prim_mubi_pkg::mubi4_test_true_strict(ot_ext_freq_is_96m) ),
+ .q_o ( sw_exfr_is_96m )
+);
+
+prim_flop #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_sw_audio_clk_byp_dgl (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( ot_audio_clk_byp ),
+ .q_o ( sw_audio_clk_byp )
+);
+
+logic sys_clk_byp;
+
+assign sys_clk_byp = sw_sys_clk_byp;
+
+logic sel_io_clk_byp, io_clk_byp;
+
+assign sel_io_clk_byp = sw_io_clk_byp || sw_all_clk_byp;
+
+// De-Glitch IO Clock Bypass Select
+////////////////////////////////////////
+prim_flop #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_io_clk_byp_dgl (
+ .clk_i ( clk_aon ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( sel_io_clk_byp ),
+ .q_o ( io_clk_byp )
+);
+
+logic usb_clk_byp;
+
+assign usb_clk_byp = sw_usb_clk_byp;
+
+logic aon_clk_byp;
+
+assign aon_clk_byp = sw_aon_clk_byp;
+
+logic extfreq_is_96m;
+
+assign extfreq_is_96m = sw_exfr_is_96m;
+
+logic audio_clk_byp;
+
+assign audio_clk_byp = sw_audio_clk_byp;
+
+// Block changes during scan mode
+////////////////////////////////////////
+logic sys_clk_byp_sel, io_clk_byp_sel, usb_clk_byp_sel, aon_clk_byp_sel, audio_clk_byp_sel;
+
+always_latch begin
+ if ( !scan_mode_i ) begin
+ sys_clk_byp_sel = sys_clk_byp;
+ io_clk_byp_sel = io_clk_byp;
+ usb_clk_byp_sel = usb_clk_byp;
+ aon_clk_byp_sel = aon_clk_byp;
+ ext_freq_is_96m = extfreq_is_96m;
+ audio_clk_byp_sel = audio_clk_byp;
+ end
+end
+
+
+////////////////////////////////////////
+// Clocks Bypass Muxes
+////////////////////////////////////////
+logic sys_clk_osc_en, io_clk_osc_en, usb_clk_osc_en, aon_clk_osc_en, audio_clk_osc_en;
+logic sys_clk_byp_en, io_clk_byp_en, usb_clk_byp_en, aon_clk_byp_en, audio_clk_byp_en;
+logic rst_clk_osc_n, rst_clk_ext_n;
+
+assign rst_clk_osc_n = vcaon_pok;
+assign rst_clk_ext_n = vcaon_pok;
+
+// DV Hooks for IO clocks
+logic io_clk_byp_select, io_clk_byp_sel_buf, io_clk_osc_en_buf, io_clk_byp_en_buf;
+
+assign io_clk_byp_select = io_clk_byp_sel;
+
+prim_buf u_io_clk_byp_sel (
+ .in_i ( io_clk_byp_select ),
+ .out_o ( io_clk_byp_sel_buf )
+);
+
+prim_buf u_io_clk_osc_en (
+ .in_i ( io_clk_osc_en ),
+ .out_o ( io_clk_osc_en_buf )
+);
+
+prim_buf u_io_clk_byp_en (
+ .in_i ( io_clk_byp_en ),
+ .out_o ( io_clk_byp_en_buf )
+);
+
+logic rst_clk_osc_sys_n, rst_clk_ext_sys_n, rst_clk_osc_io_n, rst_clk_ext_io_n;
+logic rst_clk_osc_usb_n, rst_clk_ext_usb_n, rst_clk_osc_aon_n, rst_clk_ext_aon_n;
+logic rst_clk_osc_audio_n, rst_clk_ext_audio_n;
+
+prim_buf u_rst_clk_osc_sys (
+ .in_i ( rst_clk_osc_n ),
+ .out_o ( rst_clk_osc_sys_n )
+);
+
+prim_buf u_rst_clk_ext_sys (
+ .in_i ( rst_clk_ext_n ),
+ .out_o ( rst_clk_ext_sys_n )
+);
+
+prim_buf u_rst_clk_osc_io (
+ .in_i ( rst_clk_osc_n ),
+ .out_o ( rst_clk_osc_io_n )
+);
+
+prim_buf u_rst_clk_ext_io (
+ .in_i ( rst_clk_ext_n ),
+ .out_o ( rst_clk_ext_io_n )
+);
+
+prim_buf u_rst_clk_osc_usb (
+ .in_i ( rst_clk_osc_n ),
+ .out_o ( rst_clk_osc_usb_n )
+);
+
+prim_buf u_rst_clk_ext_usb (
+ .in_i ( rst_clk_ext_n ),
+ .out_o ( rst_clk_ext_usb_n )
+);
+
+prim_buf u_rst_clk_osc_aon (
+ .in_i ( rst_clk_osc_n ),
+ .out_o ( rst_clk_osc_aon_n )
+);
+
+prim_buf u_rst_clk_ext_aon (
+ .in_i ( rst_clk_ext_n ),
+ .out_o ( rst_clk_ext_aon_n )
+);
+
+prim_buf u_rst_clk_osc_audio (
+ .in_i ( rst_clk_osc_n ),
+ .out_o ( rst_clk_osc_audio_n )
+);
+
+prim_buf u_rst_clk_ext_audio (
+ .in_i ( rst_clk_ext_n ),
+ .out_o ( rst_clk_ext_audio_n )
+);
+
+// SYS Clock Bypass Mux
+////////////////////////////////////////
+gfr_clk_mux2 u_clk_src_sys_sel (
+ .clk_osc_i ( clk_osc_sys_i ),
+ .clk_osc_val_i ( clk_osc_sys_val_i ),
+ .rst_clk_osc_ni ( rst_clk_osc_sys_n ),
+ .clk_ext_i ( clk_ext_sys ),
+ .clk_ext_val_i ( clk_ext_sys_val ),
+ .rst_clk_ext_ni ( rst_clk_ext_sys_n ),
+ .ext_sel_i ( sys_clk_byp_sel ),
+ .clk_osc_en_o ( sys_clk_osc_en ),
+ .clk_ext_en_o ( sys_clk_byp_en ),
+ .clk_val_o ( clk_src_sys_val_o ),
+ .clk_o ( clk_src_sys_o )
+);
+
+// IO Clock Bypass Mux
+////////////////////////////////////////
+gfr_clk_mux2 u_clk_src_io_sel (
+ .clk_osc_i ( clk_osc_io_i ),
+ .clk_osc_val_i ( clk_osc_io_val_i ),
+ .rst_clk_osc_ni ( rst_clk_osc_io_n ),
+ .clk_ext_i ( clk_ext_io ),
+ .clk_ext_val_i ( clk_ext_io_val ),
+ .rst_clk_ext_ni ( rst_clk_ext_io_n ),
+ .ext_sel_i ( io_clk_byp_sel ),
+ .clk_osc_en_o ( io_clk_osc_en ),
+ .clk_ext_en_o ( io_clk_byp_en ),
+ .clk_val_o ( clk_src_io_val_o ),
+ .clk_o ( clk_src_io_o )
+);
+
+// USB Clock Bypass Mux
+////////////////////////////////////////
+gfr_clk_mux2 u_clk_src_usb_sel (
+ .clk_osc_i ( clk_osc_usb_i ),
+ .clk_osc_val_i ( clk_osc_usb_val_i ),
+ .rst_clk_osc_ni ( rst_clk_osc_usb_n ),
+ .clk_ext_i ( clk_ext_usb ),
+ .clk_ext_val_i ( clk_ext_usb_val ),
+ .rst_clk_ext_ni ( rst_clk_ext_usb_n ),
+ .ext_sel_i ( usb_clk_byp_sel ),
+ .clk_osc_en_o ( usb_clk_osc_en ),
+ .clk_ext_en_o ( usb_clk_byp_en ),
+ .clk_val_o ( clk_src_usb_val_o ),
+ .clk_o ( clk_src_usb_o )
+);
+
+// AON Clock Bypass Mux
+////////////////////////////////////////
+gfr_clk_mux2 u_clk_src_aon_sel (
+ .clk_osc_i ( clk_osc_aon_i ),
+ .clk_osc_val_i ( clk_osc_aon_val_i ),
+ .rst_clk_osc_ni ( rst_clk_osc_aon_n ),
+ .clk_ext_i ( clk_ext_aon ),
+ .clk_ext_val_i ( clk_ext_aon_val ),
+ .rst_clk_ext_ni ( rst_clk_ext_aon_n ),
+ .ext_sel_i ( aon_clk_byp_sel ),
+ .clk_osc_en_o ( aon_clk_osc_en ),
+ .clk_ext_en_o ( aon_clk_byp_en ),
+ .clk_val_o ( clk_src_aon_val_o ),
+ .clk_o ( clk_src_aon_o )
+);
+
+// AUDIO Clock Bypass Mux
+////////////////////////////////////////
+gfr_clk_mux2 u_clk_src_audio_sel (
+ .clk_osc_i ( clk_osc_audio_i ),
+ .clk_osc_val_i ( clk_osc_audio_val_i ),
+ .rst_clk_osc_ni ( rst_clk_osc_audio_n ),
+ .clk_ext_i ( clk_ext_audio ),
+ .clk_ext_val_i ( clk_ext_audio_val ),
+ .rst_clk_ext_ni ( rst_clk_ext_audio_n ),
+ .ext_sel_i ( audio_clk_byp_sel ),
+ .clk_osc_en_o ( audio_clk_osc_en ),
+ .clk_ext_en_o ( audio_clk_byp_en ),
+ .clk_val_o ( clk_src_audio_val_o ),
+ .clk_o ( clk_src_audio_o )
+);
+
+// rst_aon_n deasset to io clock
+////////////////////////////////////////
+logic rst_aon_n_ioda, rst_aon_ioda_n;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_rst_aon_n_ioda_sync (
+ .clk_i ( clk_src_io_o ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( 1'b1 ),
+ .q_o ( rst_aon_n_ioda )
+);
+
+assign rst_aon_ioda_n = scan_mode_i ? scan_reset_ni : rst_aon_n_ioda;
+
+// All Clocks Bypass Acknowledge
+////////////////////////////////////////
+logic all_clks_byp_en_src, all_clks_byp_en;
+
+always_ff @( posedge clk_aon, negedge rst_aon_n ) begin
+ if ( !rst_aon_n ) begin
+ all_clks_byp_en_src <= 1'b0;
+ end else begin
+ all_clks_byp_en_src <= sw_all_clk_byp && sys_clk_byp_en && io_clk_byp_en &&
+ usb_clk_byp_en && aon_clk_byp_en && audio_clk_byp_en;
+ end
+end
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_all_clks_byp_en_sync (
+ .clk_i ( clk_src_io_o ),
+ .rst_ni ( rst_aon_ioda_n ),
+ .d_i ( all_clks_byp_en_src ),
+ .q_o ( all_clks_byp_en )
+);
+
+prim_mubi4_sender #(
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_all_clk_byp_ack (
+ .clk_i ( clk_src_io_o ),
+ .rst_ni ( rst_aon_ioda_n ),
+ .mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(all_clks_byp_en) ),
+ .mubi_o ( {all_clk_byp_ack_o} )
+);
+
+// IO Clock Bypass Acknowledge
+////////////////////////////////////////
+logic only_io_clk_byp_en_src, only_io_clk_byp_en;
+
+always_ff @( posedge clk_aon, negedge rst_aon_n ) begin
+ if ( !rst_aon_n ) begin
+ only_io_clk_byp_en_src <= 1'b0;
+ end else begin
+ only_io_clk_byp_en_src <= sw_io_clk_byp && io_clk_byp_en;
+ end
+end
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_only_io_clk_byp_en_sync (
+ .clk_i ( clk_src_io_o ),
+ .rst_ni ( rst_aon_ioda_n ),
+ .d_i ( only_io_clk_byp_en_src ),
+ .q_o ( only_io_clk_byp_en )
+);
+
+prim_mubi4_sender #(
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_io_clk_byp_ack (
+ .clk_i ( clk_src_io_o ),
+ .rst_ni ( rst_aon_ioda_n ),
+ .mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(only_io_clk_byp_en) ),
+ .mubi_o ( {io_clk_byp_ack_o} )
+);
+
+// IO Clock Source is 48MHz
+////////////////////////////////////////
+logic io_clk_byp_is_48m_src, io_clk_byp_is_48m;
+
+// Oscillator source is always 96MHz.
+// External Bypass source is assume to be 96MHz until it is ebabled as 48MHz
+always_ff @( posedge clk_aon, negedge rst_aon_n ) begin
+ if ( !rst_aon_n ) begin
+ io_clk_byp_is_48m_src <= 1'b0;
+ end else begin
+ io_clk_byp_is_48m_src <= io_clk_byp_en && !ext_freq_is_96m;
+ end
+end
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_io_clk_byp_is_48m_sync (
+ .clk_i ( clk_src_io_o ),
+ .rst_ni ( rst_aon_ioda_n ),
+ .d_i ( io_clk_byp_is_48m_src ),
+ .q_o ( io_clk_byp_is_48m )
+);
+
+prim_mubi4_sender #(
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_clk_src_io_48m_sync (
+ .clk_i ( clk_src_io_o ),
+ .rst_ni ( rst_aon_ioda_n ),
+ .mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(io_clk_byp_is_48m) ),
+ .mubi_o ( {clk_src_io_48m_o} )
+);
+
+
+/////////////////////
+// Unused Signals //
+/////////////////////
+logic unused_sigs;
+
+assign unused_sigs = ^{ io_clk_byp_sel_buf,
+ io_clk_byp_en_buf,
+ io_clk_osc_en_buf,
+ sys_clk_osc_en,
+ io_clk_osc_en,
+ usb_clk_osc_en,
+ aon_clk_osc_en
+ };
+
+endmodule : ast_clks_byp
diff --git a/hw/top_sencha/ip/ast/rtl/ast_dft.sv b/hw/top_sencha/ip/ast/rtl/ast_dft.sv
new file mode 100644
index 0000000..4ef0078
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast_dft.sv
@@ -0,0 +1,53 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: ast_dft
+// *Module Description: AST DFT
+//############################################################################
+
+`include "prim_assert.sv"
+
+module ast_dft (
+ output ast_pkg::ast_obs_ctrl_t obs_ctrl_o, // Observe Control
+ output logic [ast_pkg::Ast2PadOutWidth-1:0] ast2padmux_o, // DFT observed outputs
+ // memories read-write margins
+ output ast_pkg::dpm_rm_t dpram_rmf_o, // Dual Port RAM Read-write Margin Fast
+ output ast_pkg::dpm_rm_t dpram_rml_o, // Dual Port RAM Read-write Margin sLow
+ output ast_pkg::spm_rm_t spram_rm_o, // Single Port RAM Read-write Margin
+ output ast_pkg::spm_rm_t sprgf_rm_o, // Single Port Reg-File Read-write Margin
+ output ast_pkg::spm_rm_t sprom_rm_o // Single Port ROM Read-write Margin
+);
+
+// DFT to AST Digital PADs
+assign ast2padmux_o = {ast_pkg::Ast2PadOutWidth{1'b0}};
+
+assign obs_ctrl_o = '{
+ obgsl: 4'h0,
+ obmsl: ast_pkg::ObsNon,
+ obmen: prim_mubi_pkg::MuBi4False
+ };
+
+
+////////////////////////////////////////
+// Memories Read-write Margins
+////////////////////////////////////////
+assign dpram_rmf_o = 10'h000;
+assign dpram_rml_o = 10'h000;
+assign spram_rm_o = 5'h00;
+assign sprgf_rm_o = 5'h00;
+assign sprom_rm_o = 5'h00;
+
+endmodule : ast_dft
diff --git a/hw/top_sencha/ip/ast/rtl/ast_entropy.sv b/hw/top_sencha/ip/ast/rtl/ast_entropy.sv
new file mode 100644
index 0000000..5656b9a
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast_entropy.sv
@@ -0,0 +1,137 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- //
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED.
+//
+//############################################################################
+// *Name: ast_entropy
+// *Module Description: AST Entropy
+//############################################################################
+
+module ast_entropy #(
+ parameter int EntropyRateWidth = 4
+) (
+ input edn_pkg::edn_rsp_t entropy_rsp_i, // Entropy Response
+ input [EntropyRateWidth-1:0] entropy_rate_i, // Entropy Rate
+ input clk_ast_es_i, // Entropy Clock
+ input rst_ast_es_ni, // Entropy Reset
+ input clk_src_sys_i, // System Source Clock
+ input rst_src_sys_ni, // System Source Reset
+ input clk_src_sys_val_i, // System Source Clock Valid
+ input clk_src_sys_jen_i, // System Source Clock Jitter Enable
+ output edn_pkg::edn_req_t entropy_req_o // Entropy Request
+);
+
+////////////////////////////////////////
+// Entropy Request FSM
+////////////////////////////////////////
+typedef enum logic [2-1:0] {
+ ERQ_REQ0 = 2'd1, // Device-0 Request (source)
+ ERQ_ACK0 = 2'd3, // Device-0 Acknowledge
+ ERQ_IDLE = 2'd0 // IDLE/RESET
+} erq_sm_e;
+
+erq_sm_e erq_sm;
+logic dev0_wready, dev0_ack;
+logic edn_ack, edn_req;
+logic [32-1:0] edn_bus;
+
+// Pack/Un-pack
+assign entropy_req_o.edn_req = edn_req;
+assign edn_ack = entropy_rsp_i.edn_ack;
+assign edn_bus = entropy_rsp_i.edn_bus;
+
+always_ff @( posedge clk_ast_es_i, negedge rst_ast_es_ni ) begin
+ if ( !rst_ast_es_ni ) begin
+ edn_req <= 1'b0;
+ erq_sm <= ERQ_IDLE;
+ end else begin
+ unique case ( erq_sm )
+ ERQ_IDLE: begin
+ if ( dev0_wready ) begin
+ edn_req <= 1'b1;
+ erq_sm <= ERQ_REQ0;
+ end else begin
+ edn_req <= 1'b0;
+ erq_sm <= ERQ_IDLE;
+ end
+ end
+
+ ERQ_REQ0: begin
+ if ( edn_ack ) begin
+ edn_req <= 1'b0;
+ erq_sm <= ERQ_ACK0;
+ end else begin
+ edn_req <= 1'b1;
+ erq_sm <= ERQ_REQ0;
+ end
+ end
+
+ ERQ_ACK0: begin
+ if ( dev0_wready ) begin
+ edn_req <= 1'b1;
+ erq_sm <= ERQ_REQ0;
+ end else begin
+ edn_req <= 1'b0;
+ erq_sm <= ERQ_ACK0;
+ end
+ end
+
+ default: begin
+ edn_req <= 1'b0;
+ erq_sm <= ERQ_IDLE;
+ end
+ endcase
+ end
+end
+
+assign dev0_ack = edn_ack && ((erq_sm == ERQ_REQ0) || (erq_sm == ERQ_ACK0));
+
+
+////////////////////////////////////////
+// Device 0
+////////////////////////////////////////
+logic dev0_en, dev0_entropy;
+
+assign dev0_en = clk_src_sys_val_i && clk_src_sys_jen_i;
+
+dev_entropy #(
+ .EntropyRateWidth ( EntropyRateWidth )
+) u_dev0_entropy (
+ .clk_i ( clk_ast_es_i ),
+ .rst_ni ( rst_ast_es_ni ),
+ .clk_dev_i ( clk_src_sys_i ),
+ .rst_dev_ni ( rst_src_sys_ni ),
+ .dev_en_i ( dev0_en ),
+ .dev_rate_i ( entropy_rate_i[EntropyRateWidth-1:0] ),
+ .dev_ack_i ( dev0_ack ),
+ .dev_data_i ( edn_bus[32-1:0] ),
+ .dev_wready_o ( dev0_wready ),
+ .dev_data_o ( dev0_entropy )
+);
+
+
+
+/////////////////////
+// Unused Signals
+/////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ entropy_rsp_i.edn_fips,
+ dev0_entropy // Used in ASIC implementation
+ };
+
+endmodule : ast_entropy
diff --git a/hw/top_sencha/ip/ast/rtl/ast_pkg.sv b/hw/top_sencha/ip/ast/rtl/ast_pkg.sv
new file mode 100644
index 0000000..4134f78
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast_pkg.sv
@@ -0,0 +1,189 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: ast_pkg
+// *Module Description: AST Package
+//############################################################################
+`ifdef __AST_PKG_SV
+`else
+`define __AST_PKG_SV
+
+`define PAD2AST_WIRES \
+{ manual_in_ast_misc, \
+ mio_in_raw[MioPadIoc3], \
+ mio_in_raw[MioPadIoc2], \
+ mio_in_raw[MioPadIoc1], \
+ mio_in_raw[MioPadIob2], \
+ mio_in_raw[MioPadIob1], \
+ mio_in_raw[MioPadIob0], \
+ mio_in_raw[MioPadIoa5], \
+ mio_in_raw[MioPadIoa4] }
+
+package ast_pkg;
+
+parameter int unsigned NumIoRails = 2;
+// Alerts
+parameter int unsigned NumAlerts = 11;
+parameter int unsigned AsSel = 0;
+parameter int unsigned CgSel = 1;
+parameter int unsigned GdSel = 2;
+parameter int unsigned TsHiSel = 3;
+parameter int unsigned TsLoSel = 4;
+parameter int unsigned Ot0Sel = 5;
+parameter int unsigned Ot1Sel = 6;
+parameter int unsigned Ot2Sel = 7;
+parameter int unsigned Ot3Sel = 8;
+parameter int unsigned Ot4Sel = 9;
+parameter int unsigned Ot5Sel = 10;
+//
+parameter int unsigned Lc2HcTrCyc = 102; // ((99+1)+(3+1))x5 = 520 us
+parameter int unsigned Hc2LcTrCyc = 38; // ((35+1)+(3+1))x5 = 200 us
+//
+parameter int unsigned EntropyStreams = 4;
+parameter int unsigned AdcChannels = 2;
+parameter int unsigned AdcDataWidth = 10;
+parameter int unsigned UsbCalibWidth = 20;
+parameter int unsigned Ast2PadOutWidth = 9;
+parameter int unsigned Pad2AstInWidth = 9;
+//
+// AstRegsNum is the number of AST registers programmed during initialization. It includes
+// the register that marks the finalization of init, which asserts the ast_init_done_o.
+// The offset of this register is represented with the AstLastRegOffset parameter.
+parameter int unsigned AstRegsNum = 39;
+parameter int unsigned AstLastRegOffset = (AstRegsNum-1)*4;
+
+// Memories Read-Write Margin Interface
+typedef struct packed {
+ logic marg_en_a;
+ logic [4-1:0] marg_a;
+ logic marg_en_b;
+ logic [4-1:0] marg_b;
+} dpm_rm_t;
+
+typedef struct packed {
+ logic marg_en;
+ logic [4-1:0] marg;
+} spm_rm_t;
+
+// ADC Interface
+typedef struct packed {
+ logic [AdcChannels-1:0] channel_sel;
+ logic pd;
+} adc_ast_req_t;
+
+typedef struct packed {
+ logic [AdcDataWidth-1:0] data;
+ logic data_valid;
+} adc_ast_rsp_t;
+
+// Analog Signal
+ `ifdef ANALOGSIM
+typedef real awire_t;
+ `else
+typedef logic awire_t;
+ `endif
+
+// Clock & Resets Interface
+typedef struct packed {
+ logic clk_sys;
+ logic clk_io;
+ logic clk_usb;
+ logic clk_aon;
+ logic clk_smc;
+ logic clk_ml;
+ logic clk_video;
+ logic clk_audio;
+} ast_clks_t;
+
+typedef struct packed {
+ logic aon_pok;
+} ast_rst_t;
+
+parameter ast_rst_t AST_RST_DEFAULT = '{
+ aon_pok: 1'b1
+};
+
+typedef struct packed {
+ logic [NumIoRails-1:0] io_pok;
+} ast_status_t;
+
+typedef struct packed {
+ logic aon_pok;
+ logic vcc_pok;
+ logic main_pok;
+ logic [NumIoRails-1:0] io_pok;
+} ast_pwst_t;
+
+// Alerts Interface
+typedef struct packed {
+ logic p;
+ logic n;
+} ast_dif_t;
+
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts;
+} ast_alert_req_t;
+
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts_ack;
+ ast_dif_t [NumAlerts-1:0] alerts_trig;
+} ast_alert_rsp_t;
+
+// Ack mode enumerations
+typedef enum logic {
+ ImmAck = 0,
+ SwAck = 1
+} ast_ack_mode_e;
+
+// Clocks Oschillator Bypass
+typedef struct packed {
+ logic usb;
+ logic sys;
+ logic io;
+ logic aon;
+ logic smc;
+ logic ml;
+ logic video;
+ logic audio;
+} clks_osc_byp_t;
+
+typedef enum logic [4-1:0] {
+ ObsNon = 4'h0, // No module observed (disable)
+ ObsAst = 4'h1, // Observe AST
+ ObsFla = 4'h2, // Observe FLASH
+ ObsOtp = 4'h3, // Observe OTP
+ ObsOt0 = 4'h4, // Observe OT0
+ ObsOt1 = 4'h5, // Observe OT1
+ ObsOt2 = 4'h6, // Observe OT2
+ ObsOt3 = 4'h7, // Observe OT3
+ ObsRs0 = 4'h8, // RESERVED
+ ObsRs1 = 4'h9, // RESERVED
+ ObsRs2 = 4'hA, // RESERVED
+ ObsRs3 = 4'hB, // RESERVED
+ ObsRs4 = 4'hC, // RESERVED
+ ObsRs5 = 4'hD, // RESERVED
+ ObsRs6 = 4'hE, // RESERVED
+ ObsRs7 = 4'hF // RESERVED
+} ast_omdl_e;
+
+typedef struct packed {
+ logic [4-1:0] obgsl;
+ ast_omdl_e obmsl;
+ prim_mubi_pkg::mubi4_t obmen;
+} ast_obs_ctrl_t;
+
+endpackage // of ast_pkg
+`endif // of __AST_PKG_SV
diff --git a/hw/top_sencha/ip/ast/rtl/ast_pulse_sync.sv b/hw/top_sencha/ip/ast/rtl/ast_pulse_sync.sv
new file mode 100644
index 0000000..30e27b2
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast_pulse_sync.sv
@@ -0,0 +1,159 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: ast_pulse_symc
+// *Module Description: AST Pulse Synchronizer
+//
+// Synchronizes a pulse from source clock domain (clk_src) to destination
+// clock domain (clk_dst). The source pulse can have any length of the
+// source clock cycle.
+// The destination pulse has the length of one destination clock cycle.
+// Consecutive pulses need to be spaced appropriately apart from each other
+// depending on the clock frequency ratio of the two clock domains.
+//############################################################################
+
+`include "prim_assert.sv"
+
+module ast_pulse_sync (
+ input scan_mode_i,
+ // source clock domain
+ input clk_src_i,
+ input rst_src_ni,
+ input src_pulse_i,
+ output logic src_pulse_en_o,
+ output logic src_busy_o,
+ // destination clock domain
+ input clk_dst_i,
+ input rst_dst_ni,
+ output logic dst_pulse_o
+);
+
+// Reset all flops by both resets
+////////////////////////////////////////
+logic rst_src_n, rst_dst_da_n;
+logic rst_dst_n, rst_src_da_n;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_rst_dst_da (
+ .clk_i ( clk_src_i),
+ .rst_ni ( rst_dst_ni ),
+ .d_i ( 1'b1 ),
+ .q_o ( rst_dst_da_n )
+);
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_rst_src_da (
+ .clk_i ( clk_dst_i),
+ .rst_ni ( rst_src_ni ),
+ .d_i ( 1'b1 ),
+ .q_o ( rst_src_da_n )
+);
+
+assign rst_src_n = scan_mode_i ? rst_src_ni : rst_src_ni && rst_dst_da_n;
+assign rst_dst_n = scan_mode_i ? rst_dst_ni : rst_dst_ni && rst_src_da_n;
+
+
+// Pulse Rising Edge Detect & Block
+///////////////////////////////////////
+logic src_pulse_d;
+
+always_ff @( posedge clk_src_i, negedge rst_src_n ) begin
+ if ( !rst_src_n ) begin
+ src_pulse_d <= 1'b0;
+ end else begin
+ src_pulse_d <= src_pulse_i;
+ end
+end
+
+assign src_pulse_en_o = src_pulse_i & !src_pulse_d & !src_busy_o;
+
+
+// Pulse Transformation
+///////////////////////////////////////
+logic src_req;
+
+// Convert src_pulse_en to a level signal
+always_ff @( posedge clk_src_i, negedge rst_src_n ) begin
+ if ( !rst_src_n ) begin
+ src_req <= 1'b0;
+ end else begin
+ src_req <= (src_pulse_en_o ^ src_req);
+ end
+end
+
+
+// SRC_REQ Synchronizer to DST
+///////////////////////////////////////
+logic dst_req;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_dst_req (
+ .clk_i ( clk_dst_i ),
+ .rst_ni ( rst_dst_n ),
+ .d_i ( src_req ),
+ .q_o ( dst_req )
+);
+
+
+// DST_REQ Synchronizer to SRC for ACK
+///////////////////////////////////////
+logic src_ack;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_sync2_ack (
+ .clk_i ( clk_src_i ),
+ .rst_ni ( rst_src_n ),
+ .d_i ( dst_req ),
+ .q_o ( src_ack )
+);
+
+// Source is BUSY when REQ not equel to ACK
+assign src_busy_o = (src_req ^ src_ack);
+
+
+// Pulse Reconstruction
+///////////////////////////////////////
+logic dst_req_d;
+
+always_ff @( posedge clk_dst_i, negedge rst_dst_n ) begin
+ if ( !rst_dst_n ) begin
+ dst_req_d <= 1'b0;
+ end else begin
+ dst_req_d <= dst_req;
+ end
+end
+
+assign dst_pulse_o = (dst_req ^ dst_req_d);
+
+
+////////////////////
+// Assertions
+////////////////////
+
+// A new PULSE can only be introduced when source is not BUSY.
+`ASSERT(NewPulseWhenSrcBusy, $rose(src_pulse_i) |-> !src_busy_o, clk_src_i, !rst_src_n)
+
+`ASSERT(DstPulseCheck_A, dst_pulse_o |=> !dst_pulse_o, clk_dst_i, !rst_dst_n)
+
+endmodule : ast_pulse_sync
diff --git a/hw/top_sencha/ip/ast/rtl/audio_clk.sv b/hw/top_sencha/ip/ast/rtl/audio_clk.sv
new file mode 100644
index 0000000..ceb17a7
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/audio_clk.sv
@@ -0,0 +1,75 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: audio_clk
+// *Module Description: AUDIO Clock
+//############################################################################
+
+module audio_clk (
+ input vcore_pok_h_i, // VCORE POK @3.3V (for OSC)
+ input clk_audio_pd_ni, // IO Clock Power-down
+ input rst_audio_clk_ni, // IO Clock Logic reset
+ input clk_src_audio_en_i, // IO Source Clock Enable
+ input scan_mode_i, // Scan Mode
+ input audio_osc_cal_i, // IO Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_audio_ext_i, // FPGA/VERILATOR Clock input
+`endif
+ output logic clk_src_audio_o, // IO Source Clock
+ output logic clk_src_audio_val_o // IO Source Clock Valid
+);
+
+logic clk, osc_en, audio_clk_en;
+
+assign osc_en = (clk_src_audio_en_i && clk_audio_pd_ni && rst_audio_clk_ni);
+assign audio_clk_en = scan_mode_i || osc_en;
+
+// Clock Oscilator
+///////////////////////////////////////
+audio_osc u_audio_osc (
+ .vcore_pok_h_i ( vcore_pok_h_i ),
+ .audio_en_i ( audio_clk_en ),
+ .audio_osc_cal_i ( audio_osc_cal_i ),
+`ifdef AST_BYPASS_CLK
+ .clk_audio_ext_i ( clk_audio_ext_i ),
+`endif
+ .audio_clk_o ( clk )
+); // of u_audio_osc
+
+// Clock & Valid
+///////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_audio_buf(
+ .clk_i ( clk ),
+ .clk_o ( clk_src_audio_o )
+);
+
+// 2-stage de-assertion
+logic rst_val_n;
+assign rst_val_n = audio_clk_en;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_val_sync (
+ .clk_i ( clk_src_audio_o ),
+ .rst_ni ( rst_val_n ),
+ .d_i ( 1'b1 ),
+ .q_o ( clk_src_audio_val_o )
+);
+
+endmodule : audio_clk
diff --git a/hw/top_sencha/ip/ast/rtl/audio_osc.sv b/hw/top_sencha/ip/ast/rtl/audio_osc.sv
new file mode 100644
index 0000000..321f09c
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/audio_osc.sv
@@ -0,0 +1,143 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: audio_osc
+// *Module Description: AUDIO Clock Oscilator
+//############################################################################
+
+module audio_osc (
+ input vcore_pok_h_i, // VCORE POK @3.3V
+ input audio_en_i, // IO Source Clock Enable
+ input audio_osc_cal_i, // IO Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_audio_ext_i, // FPGA/VERILATOR Clock input
+`endif
+ output logic audio_clk_o // IO Clock Output
+);
+
+`ifndef AST_BYPASS_CLK
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+timeunit 1ns / 1ps;
+
+real CLK_PERIOD;
+
+reg init_start;
+initial init_start = 1'b0;
+
+initial begin
+ #1;
+ init_start = 1'b1;
+ #1;
+ $display("\n%m: IO Clock Power-up Frequency: %0d Hz", $rtoi(10**9/CLK_PERIOD));
+end
+
+// Enable 5us RC Delay on rise
+wire en_osc_re_buf, en_osc_re;
+buf #(ast_bhv_pkg::IO_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && audio_en_i));
+assign en_osc_re = en_osc_re_buf && init_start;
+
+
+// Clock Oscillator
+////////////////////////////////////////
+real CalIoClkPeriod, UncIoClkPeriod, IoClkPeriod;
+
+initial CalIoClkPeriod = $itor( 1000000/48 ); // ~20833.333333ps (48MHz)
+initial UncIoClkPeriod = $itor( $urandom_range(55555, 25000) ); // 55555-25000ps (18-40MHz)
+
+assign IoClkPeriod = (audio_osc_cal_i && init_start) ? CalIoClkPeriod : UncIoClkPeriod;
+assign CLK_PERIOD = IoClkPeriod/1000;
+
+// Free running oscillator
+reg clk_osc;
+initial clk_osc = 1'b1;
+
+always begin
+ #(CLK_PERIOD/2) clk_osc = ~clk_osc;
+end
+
+logic en_osc;
+
+// HDL Clock Gate
+logic en_clk, clk;
+
+always_latch begin
+ if ( !clk_osc ) en_clk = en_osc;
+end
+
+assign clk = clk_osc && en_clk;
+`else // of SYNTHESIS
+// SYNTHESIS/LINTER
+///////////////////////////////////////
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && audio_en_i;
+
+logic clk, en_osc;
+assign clk = 1'b0;
+`endif // of SYNTHESIS
+`else // of AST_BYPASS_CLK
+// VERILATOR/FPGA
+///////////////////////////////////////
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && audio_en_i;
+
+// Clock Oscillator
+////////////////////////////////////////
+logic clk, en_osc;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1 )
+) u_clk_ckgt (
+ .clk_i ( clk_audio_ext_i ),
+ .en_i ( en_osc ),
+ .test_en_i ( 1'b0 ),
+ .clk_o ( clk )
+);
+`endif
+
+logic en_osc_fe;
+
+// Syncronize en_osc to clk FE for glitch free disable
+always_ff @( negedge clk, negedge vcore_pok_h_i ) begin
+ if ( !vcore_pok_h_i ) begin
+ en_osc_fe <= 1'b0;
+ end else begin
+ en_osc_fe <= en_osc_re;
+ end
+end
+
+assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0
+
+// Clock Output Buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_buf (
+ .clk_i ( clk ),
+ .clk_o ( audio_clk_o )
+);
+
+
+`ifdef SYNTHESIS
+/////////////////////////
+// Unused Signals
+/////////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ audio_osc_cal_i };
+`endif
+
+endmodule : audio_osc
diff --git a/hw/top_sencha/ip/ast/rtl/dev_entropy.sv b/hw/top_sencha/ip/ast/rtl/dev_entropy.sv
new file mode 100644
index 0000000..4d80521
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/dev_entropy.sv
@@ -0,0 +1,275 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- //
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED.
+//
+//############################################################################
+// *Name: dev_entropy
+// *Module Description: Device Entropy
+//############################################################################
+
+module dev_entropy #(
+ parameter int EntropyRateWidth = 4
+) (
+ input clk_i, // Entropy Clock
+ input rst_ni, // Entropy Reset
+ input clk_dev_i, // Device Clock
+ input rst_dev_ni, // Device Reset
+ input dev_en_i, // Device Enable
+ input [EntropyRateWidth-1:0] dev_rate_i, // Entropy Rate
+ input dev_ack_i, // Write Valid (EDN_ACK)
+ input [32-1:0] dev_data_i, // Write Data (EDN_BUS)
+ output logic dev_wready_o, // Write Ready (EDN_REQ)
+ output logic dev_data_o // Entropy Data
+);
+
+
+////////////////////////////////////
+// Device Enable Sync
+////////////////////////////////////
+logic dev_en_dev;
+
+// Sync dev_en to Dev clock
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_dev_en_dev_sync (
+ .clk_i ( clk_dev_i ),
+ .rst_ni ( rst_dev_ni ),
+ .d_i ( dev_en_i ),
+ .q_o ( dev_en_dev )
+);
+
+
+////////////////////////////////////
+// Entropy Rate
+///////////////////////////////////////
+logic fast_start, rate_pulse, rready;
+logic [7-1:0] fast_cnt;
+logic [(1<<EntropyRateWidth)-1:0] erate_cnt, dev_rate;
+
+// Sync dev_rate_i to Device clock
+// A simplified synchrnization is used instead of a pulse synchronize.
+// The rate might go through a different value for one clk_dev_i cycle.
+// In most cases the rate will be set ahead of the dev_en_i
+logic [EntropyRateWidth-1:0] dev_rate_sync;
+
+prim_flop_2sync #(
+ .Width ( EntropyRateWidth ),
+ .ResetValue ( {EntropyRateWidth{1'b0}} )
+) u_erate_sync (
+ .clk_i ( clk_dev_i ) ,
+ .rst_ni ( rst_dev_ni ),
+ .d_i ( dev_rate_i[EntropyRateWidth-1:0] ),
+ .q_o ( dev_rate_sync[EntropyRateWidth-1:0] )
+);
+
+// Fastest rate to init the LFSR
+always_ff @( posedge clk_dev_i, negedge rst_dev_ni ) begin
+ if ( !rst_dev_ni ) begin
+ fast_start <= 1'b1;
+ fast_cnt <= 7'h00;
+ end else if ( fast_cnt == 7'h40 ) begin
+ fast_start <= 1'b0;
+ end else if ( fast_start && rready ) begin
+ fast_cnt <= fast_cnt + 1'b1;
+ end
+end
+
+assign dev_rate = fast_start ? '0 : ((1<<EntropyRateWidth)'(1'b1) << dev_rate_sync) - 1;
+
+always_ff @( posedge clk_dev_i, negedge rst_dev_ni ) begin
+ if ( !rst_dev_ni ) begin
+ erate_cnt <= '0;
+ end else if ( rate_pulse ) begin
+ erate_cnt <= dev_rate;
+ end else if ( erate_cnt != '0 ) begin
+ erate_cnt <= erate_cnt - 1'b1;
+ end
+end
+
+assign rate_pulse = (erate_cnt == '0) && dev_en_dev;
+
+
+////////////////////////////////////////
+// Entropy Data Buffer at ES Clock
+////////////////////////////////////////
+
+// Entropy Clock
+///////////////////////////////////////
+logic [32-1:0] wdata;
+
+always_ff @( posedge clk_i, negedge rst_ni ) begin
+ if ( !rst_ni ) begin
+ wdata <= 32'h0000_0000;
+ end else if ( dev_ack_i ) begin
+ wdata <= dev_data_i;
+ end
+end
+
+// Sync wvalid to ES clock
+logic wready_dev, wready_es;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_wvalid_es_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i ( wready_dev ),
+ .q_o ( wready_es )
+);
+
+logic wready_es_d;
+
+always_ff @( posedge clk_i, negedge rst_ni ) begin
+ if ( !rst_ni ) begin
+ wready_es_d <= 1'b0;
+ end else begin
+ wready_es_d <= wready_es;
+ end
+end
+
+logic wdata_val, set_wdata_val, clr_wdata_val, wready_es_fe;
+
+assign wready_es_fe = !wready_es && wready_es_d;
+assign set_wdata_val = !wdata_val && dev_ack_i;
+assign clr_wdata_val = wdata_val && wready_es_fe;
+
+always_ff @( posedge clk_i, negedge rst_ni ) begin
+ if ( !rst_ni ) begin
+ wdata_val <= 1'b0;
+ end else if ( set_wdata_val ) begin
+ wdata_val <= 1'b1;
+ end else if ( clr_wdata_val ) begin
+ wdata_val <= 1'b0;
+ end
+end
+
+assign dev_wready_o = !wdata_val;
+
+
+// Device Clock
+///////////////////////////////////////
+// Reset de-assert of rst_ni to Device clock
+logic rst_es_dev_in_n, rst_es_dev_da_n, rst_es_dev_n;
+
+assign rst_es_dev_in_n = rst_ni && rst_dev_ni;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_rst_es_n_da (
+ .clk_i ( clk_dev_i ),
+ .rst_ni ( rst_es_dev_in_n ),
+ .d_i ( 1'b1 ),
+ .q_o ( rst_es_dev_da_n )
+);
+
+assign rst_es_dev_n = rst_es_dev_da_n;
+
+// Sync wready_es to Device clock
+logic wready, wready_es_dev;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_wready_es_dev_sync (
+ .clk_i ( clk_dev_i ),
+ .rst_ni ( rst_es_dev_n ),
+ .d_i ( wready_es ),
+ .q_o ( wready_es_dev )
+);
+
+logic set_wready_dev, clr_wready_dev;
+
+assign set_wready_dev = !wready_dev && wready;
+assign clr_wready_dev = wready_dev && !wready && wready_es_dev;
+
+always_ff @( posedge clk_dev_i, negedge rst_es_dev_n ) begin
+ if ( !rst_es_dev_n ) begin
+ wready_dev <= 1'b0;
+ end else if ( set_wready_dev ) begin
+ wready_dev <= 1'b1;
+ end else if ( clr_wready_dev ) begin
+ wready_dev <= 1'b0;
+ end
+end
+
+// Sync wdata_val to Device clock
+logic wdata_val_dev;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_wvalid_dev_sync (
+ .clk_i ( clk_dev_i ),
+ .rst_ni ( rst_es_dev_n ),
+ .d_i ( wdata_val ),
+ .q_o ( wdata_val_dev )
+);
+
+logic wvalid, set_wvalid, clr_wvalid;
+
+assign set_wvalid = !wvalid && wready && wdata_val_dev;
+assign clr_wvalid = wvalid;
+
+always_ff @( posedge clk_dev_i, negedge rst_es_dev_n ) begin
+ if ( !rst_es_dev_n ) begin
+ wvalid <= 1'b0;
+ end else if ( set_wvalid ) begin
+ wvalid <= 1'b1;
+ end else if ( clr_wvalid ) begin
+ wvalid <= 1'b0;
+ end
+end
+
+
+////////////////////////////////////////
+// Packer FIFO (32to1 bit)
+////////////////////////////////////////
+logic rdata, rvalid;
+logic [6-1:0] depth;
+
+prim_packer_fifo #(
+ .InW ( 32 ),
+ .OutW ( 1 )
+) u_dev_fifo (
+ .clk_i ( clk_dev_i ),
+ .rst_ni ( rst_dev_ni ),
+ .clr_i ( 1'b0 ), // !dev_en_dev ), // Clear (sync)
+ .wvalid_i ( wvalid ), // Write Valid
+ .wdata_i ( wdata ), // Write Data (32-bit)
+ .wready_o ( wready ), // Write Ready
+ //
+ .rvalid_o ( rvalid ), // Read Valid
+ .rdata_o ( rdata ), // Read Data
+ .rready_i ( rready ), // Read Ready (done)
+ .depth_o ( depth[6-1:0] ) // empty when (depth_o == `0)
+);
+
+assign rready = rvalid && rate_pulse;
+assign dev_data_o = rdata && rate_pulse;
+
+
+///////////////////////
+// Unused Signals
+///////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ depth[6-1:0] };
+
+endmodule : dev_entropy
diff --git a/hw/top_sencha/ip/ast/rtl/gfr_clk_mux2.sv b/hw/top_sencha/ip/ast/rtl/gfr_clk_mux2.sv
new file mode 100644
index 0000000..952a5a3
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/gfr_clk_mux2.sv
@@ -0,0 +1,130 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+//############################################################################
+// *Name: gfr_clk_mux2
+// *Module Description: Glitch Free Asyncronus 2-Clocks Multiplexer
+//############################################################################
+
+module gfr_clk_mux2 (
+ input clk_osc_i,
+ input clk_osc_val_i,
+ input rst_clk_osc_ni,
+ input clk_ext_i,
+ input clk_ext_val_i,
+ input rst_clk_ext_ni,
+ input ext_sel_i,
+ output logic clk_osc_en_o,
+ output logic clk_ext_en_o,
+ output logic clk_val_o,
+ output logic clk_o
+);
+
+////////////////////////////////////////
+// All Clocks OFF
+////////////////////////////////////////
+logic clks_aoff, clk_osc_en_q, clk_ext_en_q;
+
+assign clks_aoff = !(clk_osc_en_q || clk_ext_en_q);
+
+
+////////////////////////////////////////
+// CLK_OSC
+////////////////////////////////////////
+logic clk_osc_sel, clk_osc_aoff;
+
+always_ff @( posedge clk_osc_i, negedge rst_clk_osc_ni ) begin
+ if ( !rst_clk_osc_ni ) begin
+ clk_osc_sel <= 1'b0;
+ clk_osc_aoff <= 1'b0;
+ end else begin
+ clk_osc_sel <= !ext_sel_i;
+ clk_osc_aoff <= clks_aoff;
+ end
+end
+
+always_ff @( posedge clk_osc_i, negedge rst_clk_osc_ni ) begin
+ if ( !rst_clk_osc_ni ) begin
+ clk_osc_en_q <= 1'b0;
+ end else if ( !clk_osc_sel ) begin
+ clk_osc_en_q <= 1'b0;
+ end else if ( clk_osc_sel && clk_osc_aoff ) begin
+ clk_osc_en_q <= 1'b1;
+ end
+end
+
+assign clk_osc_en_o = clk_osc_sel && (clk_osc_en_q || clk_osc_aoff);
+
+
+////////////////////////////////////////
+// CLK_EXT
+////////////////////////////////////////
+logic clk_ext_sel, clk_ext_aoff;
+
+always_ff @( posedge clk_ext_i, negedge rst_clk_ext_ni ) begin
+ if ( !rst_clk_ext_ni ) begin
+ clk_ext_sel <= 1'b0;
+ clk_ext_aoff <= 1'b0;
+ end else begin
+ clk_ext_sel <= ext_sel_i;
+ clk_ext_aoff <= clks_aoff;
+ end
+end
+
+always_ff @( posedge clk_ext_i, negedge rst_clk_ext_ni ) begin
+ if ( !rst_clk_ext_ni ) begin
+ clk_ext_en_q <= 1'b0;
+ end else if ( !clk_ext_sel ) begin
+ clk_ext_en_q <= 1'b0;
+ end else if ( clk_ext_sel && clk_ext_aoff ) begin
+ clk_ext_en_q <= 1'b1;
+ end
+end
+
+assign clk_ext_en_o = clk_ext_sel && (clk_ext_en_q || clk_ext_aoff);
+
+
+////////////////////////////////////////
+// CLK Output
+////////////////////////////////////////
+logic clk_osc, clk_ext;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1)
+) u_clk_osc_ckgt (
+ .clk_i ( clk_osc_i ),
+ .en_i ( clk_osc_en_o ),
+ .test_en_i ( 1'b0 ),
+ .clk_o ( clk_osc )
+);
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1)
+) u_clk_byp_ckgt (
+ .clk_i ( clk_ext_i ),
+ .en_i ( clk_ext_en_o ),
+ .test_en_i ( 1'b0 ),
+ .clk_o ( clk_ext )
+);
+
+assign clk_o = clk_osc || clk_ext;
+
+// Clock Valid Output
+assign clk_val_o = clk_osc_en_o ? clk_osc_val_i :
+ clk_ext_en_o ? clk_ext_val_i :
+ 1'b0;
+
+endmodule : gfr_clk_mux2
diff --git a/hw/top_sencha/ip/ast/rtl/io_clk.sv b/hw/top_sencha/ip/ast/rtl/io_clk.sv
new file mode 100644
index 0000000..d5554d9
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/io_clk.sv
@@ -0,0 +1,75 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: io_clk
+// *Module Description: IO Clock
+//############################################################################
+
+module io_clk (
+ input vcore_pok_h_i, // VCORE POK @3.3V (for OSC)
+ input clk_io_pd_ni, // IO Clock Power-down
+ input rst_io_clk_ni, // IO Clock Logic reset
+ input clk_src_io_en_i, // IO Source Clock Enable
+ input scan_mode_i, // Scan Mode
+ input io_osc_cal_i, // IO Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_io_ext_i, // FPGA/VERILATOR Clock input
+`endif
+ output logic clk_src_io_o, // IO Source Clock
+ output logic clk_src_io_val_o // IO Source Clock Valid
+);
+
+logic clk, osc_en, io_clk_en;
+
+assign osc_en = (clk_src_io_en_i && clk_io_pd_ni && rst_io_clk_ni);
+assign io_clk_en = scan_mode_i || osc_en;
+
+// Clock Oscilator
+///////////////////////////////////////
+io_osc u_io_osc (
+ .vcore_pok_h_i ( vcore_pok_h_i ),
+ .io_en_i ( io_clk_en ),
+ .io_osc_cal_i ( io_osc_cal_i ),
+`ifdef AST_BYPASS_CLK
+ .clk_io_ext_i ( clk_io_ext_i ),
+`endif
+ .io_clk_o ( clk )
+); // of u_io_osc
+
+// Clock & Valid
+///////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_io_buf(
+ .clk_i ( clk ),
+ .clk_o ( clk_src_io_o )
+);
+
+// 2-stage de-assertion
+logic rst_val_n;
+assign rst_val_n = io_clk_en;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_val_sync (
+ .clk_i ( clk_src_io_o ),
+ .rst_ni ( rst_val_n ),
+ .d_i ( 1'b1 ),
+ .q_o ( clk_src_io_val_o )
+);
+
+endmodule : io_clk
diff --git a/hw/top_sencha/ip/ast/rtl/io_osc.sv b/hw/top_sencha/ip/ast/rtl/io_osc.sv
new file mode 100644
index 0000000..bf30722
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/io_osc.sv
@@ -0,0 +1,143 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: io_osc
+// *Module Description: IO Clock Oscilator
+//############################################################################
+
+module io_osc (
+ input vcore_pok_h_i, // VCORE POK @3.3V
+ input io_en_i, // IO Source Clock Enable
+ input io_osc_cal_i, // IO Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_io_ext_i, // FPGA/VERILATOR Clock input
+`endif
+ output logic io_clk_o // IO Clock Output
+);
+
+`ifndef AST_BYPASS_CLK
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+timeunit 1ns / 1ps;
+
+real CLK_PERIOD;
+
+reg init_start;
+initial init_start = 1'b0;
+
+initial begin
+ #1;
+ init_start = 1'b1;
+ #1;
+ $display("\n%m: IO Clock Power-up Frequency: %0d Hz", $rtoi(10**9/CLK_PERIOD));
+end
+
+// Enable 5us RC Delay on rise
+wire en_osc_re_buf, en_osc_re;
+buf #(ast_bhv_pkg::IO_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && io_en_i));
+assign en_osc_re = en_osc_re_buf && init_start;
+
+
+// Clock Oscillator
+////////////////////////////////////////
+real CalIoClkPeriod, UncIoClkPeriod, IoClkPeriod;
+
+initial CalIoClkPeriod = $itor( 1000000/96 ); // ~10416.666667ps (96MHz)
+initial UncIoClkPeriod = $itor( $urandom_range(40000, 16667) ); // 40000-16667ps (25-60MHz)
+
+assign IoClkPeriod = (io_osc_cal_i && init_start) ? CalIoClkPeriod : UncIoClkPeriod;
+assign CLK_PERIOD = IoClkPeriod/1000;
+
+// Free running oscillator
+reg clk_osc;
+initial clk_osc = 1'b1;
+
+always begin
+ #(CLK_PERIOD/2) clk_osc = ~clk_osc;
+end
+
+logic en_osc;
+
+// HDL Clock Gate
+logic en_clk, clk;
+
+always_latch begin
+ if ( !clk_osc ) en_clk = en_osc;
+end
+
+assign clk = clk_osc && en_clk;
+`else // of SYNTHESIS
+// SYNTHESIS/LINTER
+///////////////////////////////////////
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && io_en_i;
+
+logic clk, en_osc;
+assign clk = 1'b0;
+`endif // of SYNTHESIS
+`else // of AST_BYPASS_CLK
+// VERILATOR/FPGA
+///////////////////////////////////////
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && io_en_i;
+
+// Clock Oscillator
+////////////////////////////////////////
+logic clk, en_osc;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1 )
+) u_clk_ckgt (
+ .clk_i ( clk_io_ext_i ),
+ .en_i ( en_osc ),
+ .test_en_i ( 1'b0 ),
+ .clk_o ( clk )
+);
+`endif
+
+logic en_osc_fe;
+
+// Syncronize en_osc to clk FE for glitch free disable
+always_ff @( negedge clk, negedge vcore_pok_h_i ) begin
+ if ( !vcore_pok_h_i ) begin
+ en_osc_fe <= 1'b0;
+ end else begin
+ en_osc_fe <= en_osc_re;
+ end
+end
+
+assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0
+
+// Clock Output Buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_buf (
+ .clk_i ( clk ),
+ .clk_o ( io_clk_o )
+);
+
+
+`ifdef SYNTHESIS
+/////////////////////////
+// Unused Signals
+/////////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ io_osc_cal_i };
+`endif
+
+endmodule : io_osc
diff --git a/hw/top_sencha/ip/ast/rtl/rglts_pdm_3p3v.sv b/hw/top_sencha/ip/ast/rtl/rglts_pdm_3p3v.sv
new file mode 100644
index 0000000..7084600
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/rglts_pdm_3p3v.sv
@@ -0,0 +1,428 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- //
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED.
+//
+//############################################################################
+// *Name: rglts_pdm_3p3v
+// *Module Description: Regulators (MAIN & AON) & PDM Logic @3.3V
+//############################################################################
+
+`include "prim_assert.sv"
+
+module rglts_pdm_3p3v (
+ input vcc_pok_h_i, // VCC Exist @3.3v
+ input vcaon_pok_por_h_i, // VCAON_POK_POR @1.1v
+ input vcmain_pok_por_h_i, // VCMAIN_POK_POR @1.1v
+ input [2-1:0] vio_pok_h_i, // vioa/b_pok signals @1.1v
+ input clk_src_aon_h_i, // AON Clock @1.1v
+ input main_pd_h_i, // MAIN Regulator Power Down @1.1v
+ input por_sync_h_i, // POR (Sync to AON clock) @1.1v
+ input scan_mode_h_i, // Scan Mode @1.1v
+ input [2-1:0] otp_power_seq_h_i, // MMR0,24 in @1.1v
+ input vcaon_supp_i, //
+ input vcmain_supp_i, //
+ output logic rglssm_vmppr_h_o, // Regulators SM at VMPPR (vcmaim_pok_por_reset) @3.3v
+ output logic rglssm_vcmon_h_o, // Regulators state machine at VCMON @3.3v
+ output logic rglssm_brout_h_o, // Regulators state machine at BROUT @3.3v
+ output logic vcmain_pok_h_o, // VCMAIN POK @3.3v
+ output logic vcmain_pok_por_h_o, // VCMAIN_POK_POR @3.3v
+ output logic vcaon_pok_h_o, // VCAON Exist @3.3v
+ output logic vcaon_pok_1p1_h_o, // VCAON Exist @3.3v for BE 1.1v (UPF issue)
+ output logic vcaon_pok_por_h_o, // VCAON_POK_POR @3.3v
+ output logic [2-1:0] vio_pok_h_o, // vioa/b_pok_h signals @3.3v
+ output logic vcc_pok_str_h_o, // VCC Exist Stretched @3.3V
+ output logic vcc_pok_str_1p1_h_o, // VCC Exist Stretched @3.3V for BE 1.1v (UPF issue)
+ output logic deep_sleep_h_o, // Deep Sleep (main regulator & switch are off) @3.3v
+ output logic flash_power_down_h_o, //
+ output logic flash_power_ready_h_o, //
+ output logic [2-1:0] otp_power_seq_h_o // MMR0,24 masked by PDM, out (VCC)
+);
+
+// Turn 1.1v into 3.3v signals
+////////////////////////////////////////
+assign vcaon_pok_por_h_o = vcaon_pok_por_h_i; // Level Up Shifter
+assign vcmain_pok_por_h_o = vcmain_pok_por_h_i; // Level Up Shifter
+assign vio_pok_h_o[1:0] = vio_pok_h_i[1:0]; // Level Up Shifter
+
+
+///////////////////////////////////////
+// Regulators Enable State Machine
+///////////////////////////////////////
+logic fla_pdm_h, otp_pdm_h;
+logic [9-1:0] dly_cnt, hc2lc_val, lc2hc_val; // upto 255 aon clock (1275us)
+
+// DV Hook
+logic [1:0] dv_hook, dft_sel;
+
+`ifndef SYNTHESIS
+initial begin
+ // Regulator Power-up time (non cold power-up) selected according to 'dv_hook' value:
+ //
+ // 0: hc2lc_val=HC2LCOC; lc2hc_val=LC2HCOC;
+ // 1: hc2lc_val=HC2LCOC*2; lc2hc_val=LC2HCOC*2;
+ // 2: hc2lc_val=9'd2; lc2hc_val=9'd6;
+ // 3: hc2lc_val=9'd4; lc2hc_val=9'd12;
+ //
+ if ( !$value$plusargs("accelerate_regulators_power_up_time=%d", dv_hook) ) begin
+ dv_hook = 2'd0;
+ end
+ `ASSERT_I(accelerate_regulators_power_up_time, dv_hook inside {[0:3]})
+end
+`else
+assign dv_hook = 2'd0;
+`endif
+
+localparam int unsigned HC2LCOC = ast_pkg::Hc2LcTrCyc;
+localparam int unsigned LC2HCOC = ast_pkg::Lc2HcTrCyc;
+logic [9-1:0] cld_pu_val;
+
+`ifndef SYNTHESIS
+initial begin
+ // Cold Power-up time can be selected between 2 and LC2HCOC (default: ast_pkg::Lc2HcTrCyc)
+ if ( !$value$plusargs("accelerate_cold_power_up_time=%d", cld_pu_val) ) begin
+ cld_pu_val = LC2HCOC[9-1:0];
+ end
+ `ASSERT_I(accelerate_cold_power_up_time, cld_pu_val inside {[2:LC2HCOC[9-1:0]]})
+end
+`else
+assign cld_pu_val = LC2HCOC[9-1:0];
+`endif
+
+// Force 2'b11 to reduce LDOs time & double LDOs start-up time
+assign dft_sel = dv_hook;
+
+assign hc2lc_val = (dft_sel == 2'b10) ? 9'd2 :
+ (dft_sel == 2'b11) ? 9'd4 :
+ (dft_sel == 2'b00) ? HC2LCOC[9-1:0] :
+ HC2LCOC[8-1:0]*2;
+
+assign lc2hc_val = (dft_sel == 2'b10) ? 9'd6 :
+ (dft_sel == 2'b11) ? 9'd12 :
+ (dft_sel == 2'b00) ? LC2HCOC[9-1:0] :
+ LC2HCOC[8-1:0]*2;
+
+
+
+///////////////////////////////////////
+// Regulators State Machine
+///////////////////////////////////////
+typedef enum logic [3-1:0] {
+ RGLS_CLDPU = 3'd0, // Cold power-up (MAIN Regulator ON, AON Regulator OFF, Power Switch Enabled)
+ RGLS_VCMON = 3'd1, // MAIN Regulator ON (AON Regulator OFF, Power Switch Enabled)
+ RGLS_VCM2A = 3'd3, // MAIN Regulator ON (AON Regulator rN, Power Switch Enabled->Disabled)
+ RGLS_VCAON = 3'd7, // AON Regulator ON (MAIN Regulator OFF, Power Switch Diabled)
+ RGLS_VCA2M = 3'd5, // AON Regulator ON (MAIN Regulator ON, Power Switch Diabled->Enabled)
+ RGLS_BROUT = 3'd6 // Brownout (MAIN Regulator ON, AON Regulator OFF, Power Switch Enabled)
+} rgls_sm_e;
+
+rgls_sm_e rgls_sm;
+logic vcmain_pok_h, vcaon_pok_h, main_pd_str_h;
+
+// Hold state machin reset on brownout for minimum 13us.
+logic rgls_rst_h_n;
+assign rgls_rst_h_n = vcc_pok_str_h_o;
+
+// Syncronizers
+// First stage clk FE & second clk RE
+///////////////////////////////////////
+logic vcc_pok_fe_h, vcc_pok_s_h;
+
+
+logic clk_src_aon_h_n;
+assign clk_src_aon_h_n = scan_mode_h_i ? clk_src_aon_h_i :
+ !clk_src_aon_h_i;
+
+always_ff @( posedge clk_src_aon_h_n, negedge rgls_rst_h_n ) begin
+ if ( !rgls_rst_h_n ) begin
+ vcc_pok_fe_h <= 1'b0;
+ end else begin
+ vcc_pok_fe_h <= vcc_pok_h_i;
+ end
+end
+
+always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
+ if ( !rgls_rst_h_n ) begin
+ vcc_pok_s_h <= 1'b0;
+ end else begin
+ vcc_pok_s_h <= vcc_pok_fe_h;
+ end
+end
+
+// Regulators State Mashine
+////////////////////////////////////////
+always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
+ if ( !rgls_rst_h_n ) begin
+ vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled
+ vcaon_pok_h <= 1'b0; // VCAON Rail Disabled
+ main_pd_str_h <= 1'b0; // Power Down Stratch off
+ //
+ rglssm_vcmon_h_o <= 1'b0; //
+ rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rglssm_brout_h_o <= 1'b0; //
+ fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
+ //
+ dly_cnt <= cld_pu_val; // VCMAIN Regulator power-up time
+ //
+ rgls_sm <= RGLS_CLDPU; // Power VCMAIN (Cold)
+ end else begin
+ unique case ( rgls_sm )
+ RGLS_CLDPU: begin
+ vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled
+ vcaon_pok_h <= 1'b0; // VCAON Rail Disabled
+ main_pd_str_h <= 1'b0; // Power Down Stratch off
+ //
+ rglssm_vcmon_h_o <= 1'b0; //
+ rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rglssm_brout_h_o <= 1'b0; //
+ fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON)||(rgls_sm == RGLS_BROUT))
+ //
+ dly_cnt <= dly_cnt - 1'b1;
+ //
+ if (dly_cnt == '0) begin
+ vcmain_pok_h <= 1'b1; // VCMAIN Rail Enable
+ vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
+ rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON)
+ rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ fla_pdm_h <= 1'b0; //
+ rgls_sm <= RGLS_VCMON; // VCMAIN Regultor is ON!
+ end else begin
+ rgls_sm <= RGLS_CLDPU; // Power VCMAIN!
+ end
+ end
+
+ RGLS_VCMON: begin
+ vcmain_pok_h <= 1'b1; // VCMAIN Rail Enabled
+ vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
+ main_pd_str_h <= 1'b0; // Power Down Stratch
+ //
+ rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON)
+ rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rglssm_brout_h_o <= 1'b0; //
+ fla_pdm_h <= 1'b0; //
+ //
+ dly_cnt <= hc2lc_val; // VCAON Regulator power-up time
+ //
+ if ( !vcc_pok_s_h ) begin
+ rglssm_vcmon_h_o <= 1'b0; //
+ rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rglssm_brout_h_o <= 1'b1; // (rgls_sm == RGLS_BROUT)
+ fla_pdm_h <= 1'b0; //
+ rgls_sm <= RGLS_BROUT; // Brownout
+ end else if ( main_pd_h_i && !por_sync_h_i ) begin
+ main_pd_str_h <= 1'b1; // Power Down Stratch on
+ rglssm_vcmon_h_o <= 1'b0; //
+ rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
+ rgls_sm <= RGLS_VCM2A; // VCMAIN to VCAON Transition
+ end else begin
+ rgls_sm <= RGLS_VCMON; // VCMAIN Regulator is ON!
+ end
+ end
+
+ RGLS_VCM2A: begin
+ vcmain_pok_h <= 1'b1; // VCMAIN Rail Enabled
+ vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
+ main_pd_str_h <= 1'b1; // Power Down Stratch
+ //
+ rglssm_vcmon_h_o <= 1'b0; //
+ rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rglssm_brout_h_o <= 1'b0; //
+ fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
+ //
+ dly_cnt <= dly_cnt - 1'b1;
+ //
+ if ( por_sync_h_i ) begin
+ vcmain_pok_h <= 1'b1; // VCMAIN Rail Enable
+ vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
+ rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON)
+ rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ fla_pdm_h <= 1'b0; //
+ rgls_sm <= RGLS_VCMON; // VCMAIN Regultor is ON!
+ end else if ( dly_cnt == '0 ) begin
+ rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rgls_sm <= RGLS_VCAON; // VCAON Regulator is ON!
+ end else begin
+ rgls_sm <= RGLS_VCM2A; // VCMAIN to VCAON Transition
+ end
+ end
+
+ RGLS_VCAON: begin
+ vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled
+ vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
+ main_pd_str_h <= 1'b1; // Power Down Stratch
+ //
+ rglssm_vcmon_h_o <= 1'b0; //
+ rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rglssm_brout_h_o <= 1'b0; //
+ fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
+ //
+ dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time
+ //
+ if ( !main_pd_h_i || por_sync_h_i ) begin
+ rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rgls_sm <= RGLS_VCA2M; // VCAON->VCMAIN Transition
+ end else begin
+ rgls_sm <= RGLS_VCAON; // VCAON Regulator is ON!
+ end
+ end
+
+ RGLS_VCA2M: begin
+ vcmain_pok_h <= 1'b0; // VCMAIN Rail Disable
+ vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
+ main_pd_str_h <= 1'b0; // Power Down Stratch off
+ //
+ rglssm_vcmon_h_o <= 1'b0; //
+ rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rglssm_brout_h_o <= 1'b0; //
+ fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
+ //
+ dly_cnt <= dly_cnt - 1'b1;
+ //
+ if ( dly_cnt == '0 ) begin
+ vcmain_pok_h <= 1'b1; // VCMAIN Rail Enable
+ vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
+ rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON)
+ rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ fla_pdm_h <= 1'b0; //
+ rgls_sm <= RGLS_VCMON; // VCMAIN Regulator is ON!
+ end else begin
+ rgls_sm <= RGLS_VCA2M; // VCAON->VCMAIN Transition
+ end
+ end
+
+ RGLS_BROUT: begin
+ vcmain_pok_h <= 1'b1; // VCMAIN Rail Enabled
+ vcaon_pok_h <= 1'b1; // VCAON Rail Enabled
+ main_pd_str_h <= 1'b0; // Powe Down Stratch off
+ //
+ rglssm_vcmon_h_o <= 1'b0; //
+ rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rglssm_brout_h_o <= 1'b1; // (rgls_sm == RGLS_BROUT)
+ fla_pdm_h <= 1'b0; //
+ //
+ dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time
+ //
+ rgls_sm <= RGLS_BROUT; // Brownout
+ end
+
+ default: begin
+ vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled
+ vcaon_pok_h <= 1'b0; // VCAON Rail Disabled
+ main_pd_str_h <= 1'b0; // Powe Down Stratch off
+ //
+ rglssm_vcmon_h_o <= 1'b0; //
+ rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M])
+ rglssm_brout_h_o <= 1'b0; //
+ fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT))
+ //
+ dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time
+ //
+ rgls_sm <= RGLS_CLDPU; // Power VCMAIN (Cold)
+ end
+ endcase
+ end
+end
+
+
+///////////////////////////////////////
+// VCMAIN_POK & VCAON POK
+///////////////////////////////////////
+assign vcmain_pok_h_o = vcmain_pok_h && vcmain_supp_i;
+// VCAON POK is needed for cold power-up to enable the AON clock
+// Therefore, it is connected directly to VCC POK.
+assign vcaon_pok_h_o = vcc_pok_h_i && vcaon_supp_i;
+assign vcaon_pok_1p1_h_o = vcaon_pok_h_o; // For layout separation
+
+
+///////////////////////////////////////
+// Streched VCC_POK During Brownout
+///////////////////////////////////////
+localparam int VccPokStrNum = 4; // (Min-Max) (3-4)x5us=(15-20)us
+
+logic vcc_pok_set_h, vcc_pok_rst_h_n;
+logic [VccPokStrNum-1:0] vcc_pok_str_no_scan_h;
+
+assign vcc_pok_rst_h_n = vcc_pok_h_i || vcaon_pok_h_o; // Non-Scan
+
+// Enable proper order of reset/set execution
+always_comb begin
+ vcc_pok_set_h = vcc_pok_rst_h_n && vcc_pok_h_i;
+end
+
+always_ff @( posedge clk_src_aon_h_i, negedge vcc_pok_rst_h_n, posedge vcc_pok_set_h ) begin
+ if ( !vcc_pok_rst_h_n ) begin
+ vcc_pok_str_no_scan_h[0] <= 1'b0;
+ end else if ( vcc_pok_set_h ) begin
+ vcc_pok_str_no_scan_h[0] <= 1'b1;
+ end else begin
+ vcc_pok_str_no_scan_h[0] <= 1'b0;
+ end
+end
+
+for (genvar i = 1; i < VccPokStrNum; i++ ) begin : gen_vcc_pok_str
+ always_ff @( posedge clk_src_aon_h_i, negedge vcc_pok_rst_h_n, posedge vcc_pok_set_h ) begin
+ if ( !vcc_pok_rst_h_n ) begin
+ vcc_pok_str_no_scan_h[i] <= 1'b0;
+ end else if ( vcc_pok_set_h ) begin
+ vcc_pok_str_no_scan_h[i] <= 1'b1;
+ end else begin
+ vcc_pok_str_no_scan_h[i] <= vcc_pok_str_no_scan_h[i-1];
+ end
+ end
+end
+
+assign vcc_pok_str_h_o = vcc_pok_str_no_scan_h[VccPokStrNum-1];
+assign vcc_pok_str_1p1_h_o = vcc_pok_str_no_scan_h[VccPokStrNum-1];
+
+
+///////////////////////////////////////
+// Deep Sleep Indication
+///////////////////////////////////////
+always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin
+ if ( !rgls_rst_h_n ) begin
+ deep_sleep_h_o <= 1'b0;
+ end else begin
+ deep_sleep_h_o <= main_pd_h_i || main_pd_str_h;
+ end
+end
+
+
+///////////////////////////////////////
+// Flash
+///////////////////////////////////////
+// fla_pdm_h = !(rglssm_vcmon || rglssm_brout);
+assign flash_power_down_h_o = scan_mode_h_i || fla_pdm_h;
+assign flash_power_ready_h_o = vcc_pok_h_i;
+
+
+///////////////////////////////////////
+// OTP
+///////////////////////////////////////
+assign otp_pdm_h = !rglssm_vcmon_h_o;
+assign otp_power_seq_h_o[0] = !scan_mode_h_i && !otp_pdm_h && otp_power_seq_h_i[0];
+assign otp_power_seq_h_o[1] = scan_mode_h_i || otp_pdm_h || otp_power_seq_h_i[1];
+
+
+/////////////////////
+// Unused Signals //
+/////////////////////
+logic unused_sigs;
+
+assign unused_sigs = ^{ vcaon_pok_h };
+
+endmodule : rglts_pdm_3p3v
diff --git a/hw/top_sencha/ip/ast/rtl/rng.sv b/hw/top_sencha/ip/ast/rtl/rng.sv
new file mode 100644
index 0000000..1272d23
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/rng.sv
@@ -0,0 +1,173 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- //
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED.
+//
+//############################################################################
+// *Name: rng
+// *Module Description: Random (bit/s) Generator (Pseudo Model)
+//############################################################################
+
+`include "prim_assert.sv"
+
+module rng #(
+ parameter int EntropyStreams = 4
+) (
+ input clk_i, // Non-Jittery Clock (TLUL)
+ input rst_ni, // Non-Jittery Reset (TLUL)
+ input clk_ast_rng_i, // Jittery Clock (RNG)
+ input rst_ast_rng_ni, // Jittery Reset (RNG)
+ input rng_en_i, // RNG Enable
+ input rng_fips_i, // RNG FIPS Enable
+ input scan_mode_i, // Scan Mode
+ output logic [EntropyStreams-1:0] rng_b_o, // RNG Bus/Bits Output
+ output logic rng_val_o // RNG Bus/Bits Valid
+);
+
+///////////////////////////////////////
+// RNG Bus using LFSR
+///////////////////////////////////////
+logic rst_n;
+logic[EntropyStreams-1:0] lfsr_val;
+
+assign rst_n = scan_mode_i ? rst_ni : rst_ni && rng_en_i;
+
+// These LFSR parameters have been generated with
+// $ ./util/design/gen-lfsr-seed.py --width 64 --seed 15513 --prefix "Rng"
+localparam int RngLfsrWidth = 64;
+typedef logic [RngLfsrWidth-1:0] rng_lfsr_seed_t;
+typedef logic [RngLfsrWidth-1:0][$clog2(RngLfsrWidth)-1:0] rng_lfsr_perm_t;
+localparam rng_lfsr_seed_t RndCnstRngLfsrSeedDefault = 64'h1d033d20eed3b14;
+localparam rng_lfsr_perm_t RndCnstRngLfsrPermDefault = {
+ 128'h98c2c94ab5e40420ed73f6c7396cd9e1,
+ 256'h58c6d7435ddb2ed1f22400c53a5aaa796ef7785e120628fbabc87f0b3928550f
+};
+
+prim_lfsr #(
+ .LfsrDw ( RngLfsrWidth ),
+ .EntropyDw ( 1 ),
+ .StateOutDw ( EntropyStreams ),
+ .DefaultSeed ( RndCnstRngLfsrSeedDefault ),
+ .StatePermEn ( 1'b1 ),
+ .StatePerm ( RndCnstRngLfsrPermDefault ),
+ .ExtSeedSVA ( 1'b0 ) // ext seed is unused
+) u_rng_lfsr (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_n ),
+ .lfsr_en_i ( rng_en_i ),
+ .seed_en_i ( 1'b0 ),
+ .seed_i ( '0 ),
+ .entropy_i ( 1'b0 ),
+ .state_o ( lfsr_val )
+);
+
+logic srate_rng_val;
+logic [12-1:0] srate_cnt, srate_value;
+logic [EntropyStreams-1:0] rng_b;
+
+`ifndef SYNTHESIS
+logic [12-1:0] dv_srate_value;
+// 4-bit rng_b needs at least 5 clocks. While the limit for these min and max values is 5:500, the
+// default is set to a shorter window of 32:128 to avoid large runtimes.
+logic [12-1:0] rng_srate_value_min = 12'd32;
+logic [12-1:0] rng_srate_value_max = 12'd128;
+
+initial begin : rng_plusargs
+ void'($value$plusargs("rng_srate_value_min=%0d", rng_srate_value_min));
+ void'($value$plusargs("rng_srate_value_max=%0d", rng_srate_value_max));
+ `ASSERT_I(DvRngSrateMinCheck, rng_srate_value_min inside {[5:500]})
+ `ASSERT_I(DvRngSrateMaxCheck, rng_srate_value_max inside {[5:500]})
+ `ASSERT_I(DvRngSrateBoundsCheck, rng_srate_value_max >= rng_srate_value_min)
+ dv_srate_value = 12'($urandom_range(int'(rng_srate_value_min), int'(rng_srate_value_max)));
+ void'($value$plusargs("rng_srate_value=%0d", dv_srate_value));
+ `ASSERT_I(DvSrateValueCheck, dv_srate_value inside {[5:500]})
+end
+
+assign srate_value = dv_srate_value;
+`else
+assign srate_value = 12'd120;
+`endif
+
+logic src_busy;
+
+always_ff @( posedge clk_i, negedge rst_n ) begin
+ if ( !rst_n ) begin
+ srate_cnt <= 12'h000;
+ srate_rng_val <= 1'b0;
+ end else if ( (srate_cnt == srate_value) && src_busy ) begin
+ srate_rng_val <= 1'b0;
+ end else if ( srate_cnt == srate_value ) begin
+ srate_cnt <= 12'h000;
+ srate_rng_val <= 1'b1;
+ end else begin
+ srate_cnt <= srate_cnt + 1'b1;
+ srate_rng_val <= 1'b0;
+ end
+end
+
+
+////////////////////////////////////////
+// Sychronize Bus & Valid to RNG Clock
+////////////////////////////////////////
+logic sync_rng_val, srate_rng_val_en;
+
+ast_pulse_sync u_rng_val_pulse_sync (
+ .scan_mode_i ( scan_mode_i ),
+ // source clock domain
+ .clk_src_i ( clk_i ),
+ .rst_src_ni ( rst_n ),
+ .src_pulse_i ( srate_rng_val ),
+ .src_pulse_en_o ( srate_rng_val_en ),
+ .src_busy_o ( src_busy ),
+ // destination clock domain
+ .clk_dst_i ( clk_ast_rng_i ),
+ .rst_dst_ni ( rst_ast_rng_ni ),
+ .dst_pulse_o ( sync_rng_val )
+);
+
+// Sanple & Hold the rng_b value until the sync completes
+always_ff @( posedge clk_i, negedge rst_n ) begin
+ if ( !rst_n ) begin
+ rng_b <= {EntropyStreams{1'b0}};
+ end else if ( srate_rng_val_en ) begin
+ rng_b <= lfsr_val[EntropyStreams-1:0];
+ end
+end
+
+//Sync to RNG clock domain
+always_ff @( posedge clk_ast_rng_i, negedge rst_ast_rng_ni ) begin
+ if (!rst_ast_rng_ni ) begin
+ rng_b_o <= {EntropyStreams{1'b0}};
+ rng_val_o <= 1'b0;
+ end else if ( sync_rng_val ) begin
+ rng_b_o <= rng_b[EntropyStreams-1:0];
+ rng_val_o <= 1'b1;
+ end else begin
+ rng_val_o <= 1'b0;
+ end
+end
+
+
+///////////////////////
+// Unused Signals
+///////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{
+ rng_fips_i // Used in ASIC implementation
+ };
+
+endmodule : rng
diff --git a/hw/top_sencha/ip/ast/rtl/sys_clk.sv b/hw/top_sencha/ip/ast/rtl/sys_clk.sv
new file mode 100644
index 0000000..df3efa0
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/sys_clk.sv
@@ -0,0 +1,77 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: sys_clk
+// *Module Description: System Clock
+//############################################################################
+
+module sys_clk (
+ input clk_src_sys_jen_i, // System Source Clock Jitter Enable
+ input clk_src_sys_en_i, // System Source Clock Enable
+ input clk_sys_pd_ni, // System Clock Power-down
+ input rst_sys_clk_ni, // System Clock Logic reset
+ input vcore_pok_h_i, // VCORE POK @3.3V (for OSC)
+ input scan_mode_i, // Scan Mode
+ input sys_osc_cal_i, // System Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_sys_ext_i, // FPGA/VERILATOR Clock input
+`endif
+ output logic clk_src_sys_o, // System Source Clock
+ output logic clk_src_sys_val_o // System Source Clock Valid
+);
+
+logic clk, osc_en, sys_clk_en;
+
+assign osc_en = (clk_src_sys_en_i && clk_sys_pd_ni && rst_sys_clk_ni);
+assign sys_clk_en = scan_mode_i || osc_en;
+
+// Clock Oscilator
+///////////////////////////////////////
+sys_osc u_sys_osc (
+ .vcore_pok_h_i ( vcore_pok_h_i ),
+ .sys_en_i ( sys_clk_en ),
+ .sys_jen_i ( clk_src_sys_jen_i ),
+ .sys_osc_cal_i ( sys_osc_cal_i ),
+`ifdef AST_BYPASS_CLK
+ .clk_sys_ext_i ( clk_sys_ext_i ),
+`endif
+ .sys_clk_o ( clk )
+); // of u_sys_osc
+
+// Clock & Valid
+///////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_sys_buf(
+ .clk_i ( clk ),
+ .clk_o ( clk_src_sys_o )
+);
+
+// 2-stage de-assertion
+logic rst_val_n;
+assign rst_val_n = sys_clk_en;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_val_sync (
+ .clk_i ( clk_src_sys_o ),
+ .rst_ni ( rst_val_n ),
+ .d_i ( 1'b1 ),
+ .q_o ( clk_src_sys_val_o )
+);
+
+endmodule : sys_clk
diff --git a/hw/top_sencha/ip/ast/rtl/sys_osc.sv b/hw/top_sencha/ip/ast/rtl/sys_osc.sv
new file mode 100644
index 0000000..a46a664
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/sys_osc.sv
@@ -0,0 +1,170 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: sys_osc
+// *Module Description: System Clock Oscilator
+//############################################################################
+
+module sys_osc (
+ input vcore_pok_h_i, // VCORE POK @3.3V
+ input sys_en_i, // System Source Clock Enable
+ input sys_jen_i, // System Source Clock Jitter Enable
+ input sys_osc_cal_i, // System Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_sys_ext_i, // FPGA/VERILATOR Clock input
+`endif
+ output logic sys_clk_o // System Clock Output
+);
+
+`ifndef AST_BYPASS_CLK
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+timeunit 1ns / 1ps;
+
+real CLK_PERIOD;
+
+reg init_start;
+initial init_start = 1'b0;
+logic cal_sys_clk_70mhz = 1'b0;
+logic [16-1:0] jrate, jrate_cnt;
+
+initial begin
+ jrate = 16'(1 << $urandom_range(7, 0)) - 1'b1;
+ void'($value$plusargs("cal_sys_clk_70mhz=%0b", cal_sys_clk_70mhz));
+ #1;
+ init_start = 1'b1;
+ #1;
+ $display("\n%m: System Clock Power-up Frequency: %0d Hz", $rtoi(10**9/CLK_PERIOD));
+end
+
+// Enable 5us RC Delay on rise
+wire en_osc_re_buf, en_osc_re, sys_jen;
+buf #(ast_bhv_pkg::SYS_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && sys_en_i));
+assign en_osc_re = en_osc_re_buf && init_start;
+assign sys_jen = sys_jen_i && en_osc_re_buf && init_start;
+
+// Clock Oscillator
+////////////////////////////////////////
+real CalSysClkPeriod, UncSysClkPeriod, SysClkPeriod, jitter;
+
+initial CalSysClkPeriod = cal_sys_clk_70mhz ? $itor( 14286 ) : // 14286ps (70MHz)
+ $itor( 10416 ); // 10416ps (96MHz)
+
+initial UncSysClkPeriod = $itor( $urandom_range(40000, 16667) ); // 40000-16667ps (25-60MHz)
+
+assign SysClkPeriod = (sys_osc_cal_i && init_start) ? CalSysClkPeriod : UncSysClkPeriod;
+
+logic clk;
+
+// -20% Jitter on calibrated frequency
+always_ff (* xprop_off *) @( posedge clk, negedge vcore_pok_h_i ) begin
+ if ( !vcore_pok_h_i ) begin
+ jitter <= 0.0;
+ jrate_cnt <= '0;
+ end else if ( !sys_jen ) begin
+ jrate_cnt <= '0;
+ jitter <= 0.0;
+ end else if ( jrate_cnt == '0 ) begin
+ jrate_cnt <= jrate;
+ jitter <= cal_sys_clk_70mhz ? $itor($urandom_range(3571, 0)) : // 56MHz - 70MHz
+ $itor($urandom_range(2500, 0)); // 80MHz - 100MHz
+ end else if ( jrate_cnt > '0 ) begin
+ jrate_cnt <= jrate_cnt - 1'b1;
+ end
+end
+
+assign CLK_PERIOD = (SysClkPeriod + jitter)/1000;
+
+// Free running oscillator
+reg clk_osc;
+initial clk_osc = 1'b1;
+
+always begin
+ #(CLK_PERIOD/2) clk_osc = ~clk_osc;
+end
+
+logic en_osc;
+
+// HDL Clock Gate
+logic en_clk;
+
+always_latch begin
+ if ( !clk_osc ) en_clk = en_osc;
+end
+
+assign clk = clk_osc && en_clk;
+`else // of SYNTHESIS
+// SYNTHESIS/LINTER
+///////////////////////////////////////
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && sys_en_i;
+
+logic clk, en_osc;
+assign clk = 1'b0;
+`endif // of SYNTHESIS
+`else // of AST_BYPASS_CLK
+// VERILATOR/FPGA
+///////////////////////////////////////
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && sys_en_i;
+
+// Clock Oscillator
+////////////////////////////////////////
+logic clk, en_osc;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1 )
+) u_clk_ckgt (
+ .clk_i ( clk_sys_ext_i ),
+ .en_i ( en_osc ),
+ .test_en_i ( 1'b0 ),
+ .clk_o ( clk )
+);
+`endif
+
+logic en_osc_fe;
+
+// Syncronize en_osc to clk FE for glitch free disable
+always_ff @( negedge clk, negedge vcore_pok_h_i ) begin
+ if ( !vcore_pok_h_i ) begin
+ en_osc_fe <= 1'b0;
+ end else begin
+ en_osc_fe <= en_osc_re;
+ end
+end
+
+assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0
+
+// Clock Output Buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_buf (
+ .clk_i ( clk ),
+ .clk_o ( sys_clk_o )
+);
+
+
+`ifdef SYNTHESIS
+/////////////////////////
+// Unused Signals
+/////////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ sys_osc_cal_i, sys_jen_i };
+`endif
+
+endmodule : sys_osc
diff --git a/hw/top_sencha/ip/ast/rtl/usb_clk.sv b/hw/top_sencha/ip/ast/rtl/usb_clk.sv
new file mode 100644
index 0000000..a67fc6d
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/usb_clk.sv
@@ -0,0 +1,159 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// -------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------- //
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED.
+//
+//############################################################################
+// *Name: usb_clk
+// *Module Description: USB Clock
+//############################################################################
+
+module usb_clk (
+ input vcore_pok_h_i, // VCORE POK @3.3V (for OSC)
+ input clk_usb_pd_ni, // USB Clock Power-down
+ input rst_usb_clk_ni, // USB Clock Logic reset
+ input clk_src_usb_en_i, // USB Source Clock Enable
+ input usb_ref_val_i, // USB Reference (Pulse) Valid
+ input usb_ref_pulse_i, // USB Reference Pulse
+ input clk_ast_usb_i, // USB Bufferd Clock
+ input rst_ast_usb_ni, // USB Bufferd Reset
+ input scan_mode_i, // Scan Mode
+ input usb_osc_cal_i, // USB Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_usb_ext_i, // FPGA/VERILATOR Clock input
+`endif
+ //
+ output logic clk_src_usb_o, // USB Source Clock
+ output logic clk_src_usb_val_o // USB Source Clock Valid
+);
+
+logic clk, osc_en, usb_clk_en;
+
+assign osc_en = (clk_src_usb_en_i && clk_usb_pd_ni && rst_usb_clk_ni);
+assign usb_clk_en = scan_mode_i || osc_en;
+
+logic rst_da_n, rst_n;
+
+// 2-stage de-assertion
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_rst_da (
+ .clk_i ( clk_src_usb_o ),
+ .rst_ni ( rst_usb_clk_ni ),
+ .d_i ( 1'b1 ),
+ .q_o ( rst_da_n )
+);
+
+assign rst_n = scan_mode_i ? rst_ast_usb_ni : rst_da_n;
+
+
+///////////////////////////////////////
+// Clock Calibrate & Drift Adjusment
+///////////////////////////////////////
+
+// Reference Pulse Detect
+///////////////////////////////////////
+logic ref_pulse_in, ref_pulse_re, src_pulse_en, src_busy;
+
+assign ref_pulse_in = usb_ref_pulse_i && usb_ref_val_i;
+
+ast_pulse_sync u_ref_pulse_sync (
+ .scan_mode_i ( scan_mode_i ),
+ // source clock domain
+ .clk_src_i ( clk_ast_usb_i ),
+ .rst_src_ni ( rst_ast_usb_ni ),
+ .src_pulse_i ( ref_pulse_in ),
+ .src_pulse_en_o ( src_pulse_en ),
+ .src_busy_o ( src_busy ),
+ // destination clock domain
+ .clk_dst_i ( clk ),
+ .rst_dst_ni ( rst_n ),
+ .dst_pulse_o ( ref_pulse_re )
+);
+
+// Clock Oscilator
+///////////////////////////////////////
+// 2-stage de-assertion
+logic rst_usb_n;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_rst_ast_usb_da (
+ .clk_i ( clk ),
+ .rst_ni ( rst_ast_usb_ni ),
+ .d_i ( 1'b1 ),
+ .q_o ( rst_usb_n )
+);
+
+// Sync usb_ref_val_i to clk
+logic usb_ref_val;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_ref_val_sync (
+ .clk_i ( clk ),
+ .rst_ni ( rst_usb_n ),
+ .d_i ( usb_ref_val_i ),
+ .q_o ( usb_ref_val )
+);
+
+usb_osc u_usb_osc (
+ .vcore_pok_h_i ( vcore_pok_h_i ),
+ .usb_en_i (usb_clk_en ),
+ .usb_ref_pulse_i ( ref_pulse_re ),
+ .usb_ref_val_i ( usb_ref_val ),
+ .usb_osc_cal_i ( usb_osc_cal_i ),
+`ifdef AST_BYPASS_CLK
+ .clk_usb_ext_i ( clk_usb_ext_i ),
+`endif
+ .usb_clk_o ( clk )
+); // u_usb_osc
+
+// Clock & Valid
+///////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_clk_usb_buf(
+ .clk_i ( clk ),
+ .clk_o ( clk_src_usb_o )
+);
+
+// 2-stage de-assertion
+logic rst_val_n;
+assign rst_val_n = usb_clk_en;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_no_scan_val_sync (
+ .clk_i ( clk_src_usb_o ),
+ .rst_ni ( rst_val_n ),
+ .d_i ( 1'b1 ),
+ .q_o ( clk_src_usb_val_o )
+);
+
+
+/////////////////////////
+// Unused Signals
+/////////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ src_pulse_en, src_busy };
+
+endmodule : usb_clk
diff --git a/hw/top_sencha/ip/ast/rtl/usb_osc.sv b/hw/top_sencha/ip/ast/rtl/usb_osc.sv
new file mode 100644
index 0000000..028061e
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/usb_osc.sv
@@ -0,0 +1,195 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: usb_osc
+// *Module Description: USB Clock Oscilator
+//############################################################################
+
+module usb_osc (
+ input vcore_pok_h_i, // VCORE POK @3.3V
+ input usb_en_i, // USB Source Clock Enable
+ input usb_ref_pulse_i, // USB Reference Pulse
+ input usb_ref_val_i, // USB Reference Valid
+ input usb_osc_cal_i, // USB Oscillator Calibrated
+`ifdef AST_BYPASS_CLK
+ input clk_usb_ext_i, // FPGA/VERILATOR Clock input
+`endif
+ output logic usb_clk_o // USB Clock Output
+);
+
+`ifndef AST_BYPASS_CLK
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+timeunit 1ns / 1ps;
+
+real CLK_PERIOD;
+integer beacon_rdly;
+bit calibrate_usb_clk, max_drift;
+localparam int MAXUSBDRIFT = 416; // 416 is +/-2% of 48MHz; 694 is +/-3% of 48MHz
+integer usb_clk_drift;
+
+reg init_start;
+initial init_start = 1'b0;
+
+initial begin
+ // With this flag activated, +calibrate_usb_clk=0. the USB clock will be calibrated
+ // as-soon-as the 'ast_init_done_o' gets active (using '=1' will delay by 1 ns).
+ //
+ // | <- BEACON_RDLY in ns -> |
+ // < un-calibrated clock >< calibrated+drift >< calibrated >
+ // _______________________/``````````````````````````````````````````````````` ast_init_done_o
+ //
+ if ( !$value$plusargs("calibrate_usb_clk=%0d", beacon_rdly) ) begin
+ beacon_rdly = 0;
+ calibrate_usb_clk = 1'b0;
+ end else begin
+ calibrate_usb_clk = 1'b1;
+ end
+ // Max USB drift is: +/-2%
+ if ( !$value$plusargs("usb_max_drift=%0b", max_drift) ) begin
+ max_drift = 1'b0;
+ end
+ //
+ #1;
+ init_start = 1'b1;
+ #1;
+ $display("\n%m: USB Clock Power-up Frequency: %0d Hz", $rtoi(10**9/CLK_PERIOD));
+ usb_clk_drift = max_drift ? ($urandom_range(0, 1) ? MAXUSBDRIFT : -MAXUSBDRIFT) : // +2% or -2%
+ ($urandom_range(0, 2*MAXUSBDRIFT) - MAXUSBDRIFT); // Up to +/-2%
+ $display("%m: USB Clock Drift: %0d ps", usb_clk_drift);
+end
+
+// Enable 5us RC Delay on rise
+wire en_osc_re_buf, en_osc_re;
+buf #(ast_bhv_pkg::USB_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && usb_en_i));
+assign en_osc_re = en_osc_re_buf && init_start;
+
+logic usb_ref_val_buf, zero_drift;
+
+buf #(ast_bhv_pkg::USB_VAL_RDLY, ast_bhv_pkg::USB_VAL_FDLY) b1
+ (usb_ref_val_buf, (vcore_pok_h_i && usb_ref_val_i));
+
+buf #(beacon_rdly, 0) b2 (usb_beacon_on_buf, (usb_osc_cal_i && calibrate_usb_clk));
+
+assign zero_drift = (usb_ref_val_buf && calibrate_usb_clk || usb_beacon_on_buf) && init_start;
+
+logic [4-1:0] ref_pulse_cnt_down;
+
+always_ff @( posedge usb_clk_o, negedge usb_ref_val_i ) begin
+ if ( !usb_ref_val_i ) begin
+ ref_pulse_cnt_down <= ast_reg_pkg::NumUsbBeaconPulses[4-1:0];
+ end else if ( (ref_pulse_cnt_down > 4'h0) && usb_ref_pulse_i ) begin
+ ref_pulse_cnt_down <= ref_pulse_cnt_down - 1'b1;
+ end
+end
+
+// Clock Oscillator
+////////////////////////////////////////
+real CalUsbClkPeriod, UncUsbClkPeriod, UsbClkPeriod, drift;
+
+initial CalUsbClkPeriod = $itor( 1000000/48 ); // ~20833.33333ps (48MHz)
+initial UncUsbClkPeriod = $itor( $urandom_range(55555, 25000) ); // 55555-25000ps (18-40MHz)
+
+real adj_drift;
+assign adj_drift = $itor(usb_clk_drift) * $itor(ref_pulse_cnt_down) /
+ $itor(ast_reg_pkg::NumUsbBeaconPulses[4-1:0]);
+
+assign drift = zero_drift ? 0.0 : adj_drift;
+
+assign UsbClkPeriod = (usb_osc_cal_i && init_start) ? CalUsbClkPeriod :
+ UncUsbClkPeriod;
+assign CLK_PERIOD = (UsbClkPeriod + drift)/1000;
+
+// Free running oscillator
+reg clk_osc;
+initial clk_osc = 1'b1;
+
+always begin
+ #(CLK_PERIOD/2) clk_osc = ~clk_osc;
+end
+
+logic en_osc;
+
+// HDL Clock Gate
+logic en_clk, clk;
+
+always_latch begin
+ if ( !clk_osc ) en_clk = en_osc;
+end
+
+assign clk = clk_osc && en_clk;
+`else // of SYNTHESIS
+// SYNTHESIS/LINTER
+///////////////////////////////////////
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && usb_en_i;
+
+logic clk, en_osc;
+assign clk = 1'b0;
+`endif // of SYNTHESIS
+`else // of AST_BYPASS_CLK
+// VERILATOR/FPGA
+///////////////////////////////////////
+logic en_osc_re;
+assign en_osc_re = vcore_pok_h_i && usb_en_i;
+
+// Clock Oscillator
+////////////////////////////////////////
+logic clk, en_osc;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1 )
+) u_clk_ckgt (
+ .clk_i ( clk_usb_ext_i ),
+ .en_i ( en_osc ),
+ .test_en_i ( 1'b0 ),
+ .clk_o ( clk )
+);
+`endif
+
+logic en_osc_fe;
+
+// Syncronize en_osc to clk FE for glitch free disable
+always_ff @( negedge clk, negedge vcore_pok_h_i ) begin
+ if ( !vcore_pok_h_i ) begin
+ en_osc_fe <= 1'b0;
+ end else begin
+ en_osc_fe <= en_osc_re;
+ end
+end
+
+assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0
+
+// Clock Output Buffer
+////////////////////////////////////////
+prim_clock_buf #(
+ .NoFpgaBuf ( 1'b1 )
+) u_buf (
+ .clk_i ( clk ),
+ .clk_o ( usb_clk_o )
+);
+
+
+`ifdef SYNTHESIS
+///////////////////////
+// Unused Signals
+///////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ usb_osc_cal_i, usb_ref_pulse_i, usb_ref_val_i };
+`endif
+
+endmodule : usb_osc
diff --git a/hw/top_sencha/ip/ast/rtl/vcaon_pgd.sv b/hw/top_sencha/ip/ast/rtl/vcaon_pgd.sv
new file mode 100644
index 0000000..823eb28
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/vcaon_pgd.sv
@@ -0,0 +1,69 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: vcaon_pgd
+// *Module Description: VCAON Power Good
+//############################################################################
+`ifdef SYNTHESIS
+`ifndef PRIM_DEFAULT_IMPL
+`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+`endif
+`endif
+
+module vcaon_pgd (
+ output logic vcaon_pok_o
+);
+
+// Local signal for testing hook
+logic gen_supp_a;
+assign gen_supp_a = 1'b1;
+
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+// The initial is needed to clear the X of the delays at the start
+// Also to force a power-up effect at the bgining.
+logic init_start;
+
+initial begin
+ init_start = 1'b1; #1;
+ init_start = 1'b0;
+end
+
+always @( * ) begin
+ if ( init_start ) begin
+ vcaon_pok_o <= 1'b0;
+ end else if ( !init_start && gen_supp_a ) begin
+ vcaon_pok_o <= #(ast_bhv_pkg::VCAON_POK_RDLY) gen_supp_a;
+ end else if ( !init_start && !gen_supp_a ) begin
+ vcaon_pok_o <= #(ast_bhv_pkg::VCAON_POK_FDLY) gen_supp_a;
+ end
+end
+`else
+// SYNTHESIS/VERILATOR/LINTER/FPGA
+///////////////////////////////////////
+localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+
+if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
+ // FPGA Specific (place holder)
+ ///////////////////////////////////////
+ assign vcaon_pok_o = gen_supp_a;
+end else begin : gen_generic
+ assign vcaon_pok_o = gen_supp_a;
+end
+`endif
+
+endmodule : vcaon_pgd
diff --git a/hw/top_sencha/ip/ast/rtl/vcc_pgd.sv b/hw/top_sencha/ip/ast/rtl/vcc_pgd.sv
new file mode 100644
index 0000000..00c7682
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/vcc_pgd.sv
@@ -0,0 +1,71 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: vcc_pgd
+// *Module Description: VCC Power Good
+//############################################################################
+`ifdef SYNTHESIS
+`ifndef PRIM_DEFAULT_IMPL
+`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+`endif
+`endif
+
+module vcc_pgd (
+ output logic vcc_pok_o
+);
+
+// Local signal for testing hook
+logic gen_supp_a;
+assign gen_supp_a = 1'b1;
+
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+// The initial is needed to clear the X of the delays at the start
+// Also to force a power-up effect at the bgining.
+logic init_start;
+
+initial begin
+ init_start = 1'b1; #1;
+ init_start = 1'b0;
+end
+
+always (* xprop_off *) @( * ) begin
+ if ( init_start ) begin
+ vcc_pok_o <= 1'b0;
+ end
+ if ( !init_start && gen_supp_a ) begin
+ vcc_pok_o <= #(ast_bhv_pkg::VCC_POK_RDLY) gen_supp_a;
+ end
+ if ( !init_start && !gen_supp_a ) begin
+ vcc_pok_o <= #(ast_bhv_pkg::VCC_POK_FDLY) gen_supp_a;
+ end
+end
+`else
+// SYNTHESIS/VERILATOR/LINTER/FPGA
+///////////////////////////////////////
+localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+
+if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
+ // FPGA Specific (place holder)
+ ///////////////////////////////////////
+ assign vcc_pok_o = gen_supp_a;
+end else begin : gen_generic
+ assign vcc_pok_o = gen_supp_a;
+end
+`endif
+
+endmodule : vcc_pgd
diff --git a/hw/top_sencha/ip/ast/rtl/vcmain_pgd.sv b/hw/top_sencha/ip/ast/rtl/vcmain_pgd.sv
new file mode 100644
index 0000000..b8d8d3e
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/vcmain_pgd.sv
@@ -0,0 +1,69 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: vcmain_pgd
+// *Module Description: VCMAIN Power Good
+//############################################################################
+`ifdef SYNTHESIS
+`ifndef PRIM_DEFAULT_IMPL
+`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+`endif
+`endif
+
+module vcmain_pgd (
+ output logic vcmain_pok_o
+);
+
+// Local signal for testing hook
+logic gen_supp_a;
+assign gen_supp_a = 1'b1;
+
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+// The initial is needed to clear the X of the delays at the start
+// Also to force a power-up effect at the bgining.
+logic init_start;
+
+initial begin
+ init_start = 1'b1; #1;
+ init_start = 1'b0;
+end
+
+always @( * ) begin
+ if ( init_start ) begin
+ vcmain_pok_o <= 1'b0;
+ end else if ( !init_start && gen_supp_a ) begin
+ vcmain_pok_o <= #(ast_bhv_pkg::VCMAIN_POK_RDLY) gen_supp_a;
+ end else if ( !init_start && !gen_supp_a ) begin
+ vcmain_pok_o <= #(ast_bhv_pkg::VCMAIN_POK_FDLY) gen_supp_a;
+ end
+end
+`else
+// SYNTHESIS/VERILATOR/LINTER/FPGA
+///////////////////////////////////////
+localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+
+if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
+ // FPGA Specific (place holder)
+ ///////////////////////////////////////
+ assign vcmain_pok_o = gen_supp_a;
+end else begin : gen_generic
+ assign vcmain_pok_o = gen_supp_a;
+end
+`endif
+
+endmodule : vcmain_pgd
diff --git a/hw/top_sencha/ip/ast/rtl/vio_pgd.sv b/hw/top_sencha/ip/ast/rtl/vio_pgd.sv
new file mode 100644
index 0000000..26af1d4
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/vio_pgd.sv
@@ -0,0 +1,71 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//############################################################################
+// *Name: vio_pgd
+// *Module Description: VIO Power Good
+//############################################################################
+`ifdef SYNTHESIS
+`ifndef PRIM_DEFAULT_IMPL
+`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+`endif
+`endif
+
+module vio_pgd (
+ output logic vio_pok_o
+);
+
+// Local signal for testing hook
+logic gen_supp_a;
+assign gen_supp_a = 1'b1;
+
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+// The initial is needed to clear the X of the delays at the start
+// Also to force a power-up effect at the bgining.
+logic init_start;
+
+initial begin
+ init_start = 1'b1; #1;
+ init_start = 1'b0;
+end
+
+always (* xprop_off *) @( * ) begin
+ if ( init_start ) begin
+ vio_pok_o <= 1'b0;
+ end
+ if ( !init_start && gen_supp_a ) begin
+ vio_pok_o <= #(ast_bhv_pkg::VIO_POK_RDLY) gen_supp_a;
+ end
+ if ( !init_start && !gen_supp_a ) begin
+ vio_pok_o <= #(ast_bhv_pkg::VIO_POK_FDLY) gen_supp_a;
+ end
+end
+`else
+// SYNTHESIS/VERILATOR/LINTER/FPGA
+//////////////////////////////////////
+localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+
+if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
+ // FPGA Specific (place holder)
+ ///////////////////////////////////////
+ assign vio_pok_o = gen_supp_a;
+end else begin : gen_generic
+ assign vio_pok_o = gen_supp_a;
+end
+`endif
+
+endmodule : vio_pgd
diff --git a/hw/top_sencha/ip/clkmgr/BUILD b/hw/top_sencha/ip/clkmgr/BUILD
new file mode 100644
index 0000000..7ffa24f
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/clkmgr/data:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/clkmgr/clkmgr.core b/hw/top_sencha/ip/clkmgr/clkmgr.core
new file mode 100644
index 0000000..b146e9c
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/clkmgr.core
@@ -0,0 +1,69 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:clkmgr:0.1"
+description: "Top specific clock manager "
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:lc_ctrl_pkg
+ - lowrisc:ip:pwrmgr_pkg
+ - lowrisc:ip:tlul
+ - lowrisc:prim:all
+ - lowrisc:prim:buf
+ - lowrisc:prim:clock_buf
+ - lowrisc:prim:clock_div
+ - lowrisc:prim:clock_gating
+ - lowrisc:prim:edge_detector
+ - lowrisc:prim:lc_sync
+ - lowrisc:prim:lc_sender
+ - lowrisc:systems:clkmgr_pkg
+ - lowrisc:ip:clkmgr_components
+ files:
+ - rtl/autogen/clkmgr_reg_pkg.sv
+ - rtl/autogen/clkmgr_reg_top.sv
+ - rtl/autogen/clkmgr.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/clkmgr.waiver
+ file_type: waiver
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - files_rtl
+ toplevel: clkmgr
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_sencha/ip/clkmgr/clkmgr_pkg.core b/hw/top_sencha/ip/clkmgr/clkmgr_pkg.core
new file mode 100644
index 0000000..c8c3b25
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/clkmgr_pkg.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:clkmgr_pkg:0.1"
+description: "Top specific clock manager package"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:constants:top_pkg
+ - lowrisc:ip:pwrmgr_pkg
+ files:
+ - rtl/autogen/clkmgr_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/clkmgr/data/BUILD b/hw/top_sencha/ip/clkmgr/data/BUILD
new file mode 100644
index 0000000..8017a77
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/data/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/clkmgr/data/autogen:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/clkmgr/data/autogen/BUILD b/hw/top_sencha/ip/clkmgr/data/autogen/BUILD
new file mode 100644
index 0000000..48f4a30
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/data/autogen/BUILD
@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+load("@lowrisc_opentitan//rules:autogen.bzl", "autogen_hjson_header")
+
+autogen_hjson_header(
+ name = "clkmgr_regs",
+ srcs = [
+ "clkmgr.hjson",
+ ],
+)
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/ip/clkmgr/data/autogen/clkmgr_sec_cm_testplan.hjson b/hw/top_sencha/ip/clkmgr/data/autogen/clkmgr_sec_cm_testplan.hjson
new file mode 100644
index 0000000..62e0302
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/data/autogen/clkmgr_sec_cm_testplan.hjson
@@ -0,0 +1,190 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Security countermeasures testplan extracted from the IP Hjson using reggen.
+//
+// This testplan is auto-generated only the first time it is created. This is
+// because this testplan needs to be hand-editable. It is possible that these
+// testpoints can go out of date if the spec is updated with new
+// countermeasures. When `reggen` is invoked when this testplan already exists,
+// It checks if the list of testpoints is up-to-date and enforces the user to
+// make further manual updates.
+//
+// These countermeasures and their descriptions can be found here:
+// .../clkmgr/data/clkmgr.hjson
+//
+// It is possible that the testing of some of these countermeasures may already
+// be covered as a testpoint in a different testplan. This duplication is ok -
+// the test would have likely already been developed. We simply map those tests
+// to the testpoints below using the `tests` key.
+//
+// Please ensure that this testplan is imported in:
+// .../clkmgr/data/clkmgr_testplan.hjson
+{
+ testpoints: [
+ {
+ name: sec_cm_bus_integrity
+ desc: '''Verify the countermeasure(s) BUS.INTEGRITY.
+ This entry is covered by tl_access_test.
+ '''
+ milestone: V2S
+ tests: ["clkmgr_tl_intg_err"]
+ }
+ {
+ name: sec_cm_meas_clk_bkgn_chk
+ desc: '''Verify the countermeasure(s) MEAS.CLK.BKGN_CHK.
+ - Test measurement feature of clkmgr_meas_chk modules.
+ For all test clocks (clk_main, clk_usb, clk_io, clk_io_div2
+ and clk_io_div4), do measurement with normal configuration.
+ Then change either min or max threshold value to see
+ whether the module can detect measurement error for each test
+ clock.
+ - Measurement error should trigger a recoverable alert
+ '''
+ milestone: V2S
+ tests: ["clkmgr_frequency"]
+ }
+ {
+ name: sec_cm_timeout_clk_bkgn_chk
+ desc: '''Verify the countermeasure(s) TIMEOUT.CLK.BKGN_CHK.
+ - Test timeout feature of clkmgr_meas_chk modules.
+ While frequency measurement, one of
+ clk_main, clk_usb, clk_io, clk_io_div2 and clk_io_div4 are choose
+ and stopped. This will leads to timeout event.
+ - Timeout should cause a recoverable alert
+ '''
+ milestone: V2S
+ tests: ["clkmgr_frequency_timeout"]
+ }
+ {
+ name: sec_cm_meas_config_shadow
+ desc: '''
+ Verify the countermeasure(s) MEAS.CONFIG.SHADOW.
+
+ This is covered by shadow_reg_errors_tests
+ (https://github.com/lowRISC/opentitan/blob/master/
+ hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson)
+ '''
+ milestone: V2S
+ tests: ["clkmgr_shadow_reg_errors"]
+ }
+ {
+ name: sec_cm_idle_intersig_mubi
+ desc: '''Verify the countermeasure(s) IDLE.INTERSIG.MUBI.
+ It uses true_strict and false_loose.
+ **Stimulus**:
+ Use same sequence as trans_enables test.
+ Randomize dut.idle_i ports with illegal values.
+ **Check**:
+ - hins_status check:
+ When clk_hints update from '1' to '0',
+ clk_hints_status has to wait idle becomes 'true'. So check
+ clk_hints_status with random idle value, then check again
+ after set all idle values to 'true'.
+
+ - clock output check:
+ When clk_hints_status go to '0', check clocks_o
+ to see if clock is really off
+ '''
+ milestone: V2S
+ tests: ["clkmgr_idle_intersig_mubi"]
+ }
+ {
+ name: sec_cm_lc_ctrl_intersig_mubi
+ desc: '''Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI.
+ It compares to lc_ctrl_pkg::On only.
+ Use clkmgr_extclk test as in testplan.extclk but randomize
+ dut.lc_hw_debug_en_i s.t. all 16 values can be generated with equal priority.
+
+ **Checks**:
+ When dut sees invalid values of lc_hw_debug_en_i,
+ all_clk_byp_req should not be asserted. Covered by assertion checker.
+ '''
+ milestone: V2S
+ tests: ["clkmgr_lc_ctrl_intersig_mubi"]
+ }
+ {
+ name: sec_cm_lc_ctrl_clk_handshake_intersig_mubi
+ desc: '''Verify the countermeasure(s) LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI.
+ It compared to lc_ctrl_pkg::On only.
+ Use clkmgr_extclk test but randomize lc_clk_byp_req s.t.
+ all 16 values can be generated with equal priority.
+ lc_clk_byp_req drives dut.lc_clk_byp_req_i in the test.
+ **Checks**:
+ When dut sees invalid values of lc_clk_byp_req_i,
+ io_clk_byp_req_o should not be asserted. Covered by assertion checker.
+ '''
+ milestone: V2S
+ tests: ["clkmgr_lc_clk_byp_req_intersig_mubi"]
+ }
+ {
+ name: sec_cm_clk_handshake_intersig_mubi
+ desc: '''Verify the countermeasure(s) CLK_HANDSHAKE.INTERSIG.MUBI.
+ It uses true_strict.
+ Use clkmgr_extclk test. Upon receiving [io|all]_clk_byp_req_o from dut,
+ assert invalid [io|all]_clk_byp_ack values to dut.
+
+ **Check**:
+ all_clk_byp_ack is copied to CLKGMR.EXTCLK_STATUS as is. So read extclk
+ status and compare.
+ io_clk_byp_ack is evaluated with step_down_acks_syn.
+ When both are true, lc_clk_byp_req is assigned to lc_clk_byp_ack.
+ Covered by assertion checker.
+ '''
+ milestone: V2S
+ tests: ["clkmgr_clk_handshake_intersig_mubi"]
+ }
+ {
+ name: sec_cm_div_intersig_mubi
+ desc: '''Verify the countermeasure(s) DIV.INTERSIG.MUBI.
+ use true_strict.
+ Use clkmgr_extclk test. Before, test drive dut.div_step_down_req_i
+ with 'true', sends invalid values.
+ **Check**:
+ dut should ignore invalid req values. Covered by assertion checker.
+ '''
+ milestone: V2S
+ tests: ["clkmgr_div_intersig_mubi"]
+ }
+ {
+ name: sec_cm_jitter_config_mubi
+ desc: '''Verify the countermeasure(s) JITTER.CONFIG.MUBI.
+ use false_strict.
+ This doesn't do any function in the dut but indicating
+ jittery clock is enabled. So it can be covered by default
+ csr test.
+ '''
+ milestone: V2S
+ tests: ["clkmgr_csr_rw"]
+ }
+ {
+ name: sec_cm_idle_ctr_redun
+ desc: '''Verify the countermeasure(s) IDLE.CTR.REDUN.
+ This is triggered by common cm primitives (SecCmPrimCount).
+ **Check**:
+ read check CLKMGR.FATAL_ERR_CODE.IDLE_CNT == 1
+ '''
+ milestone: V2S
+ tests: ["clkmgr_sec_cm"]
+ }
+ {
+ name: sec_cm_meas_config_regwen
+ desc: '''Verify the countermeasure(s) MEAS.CONFIG.REGWEN.
+
+ This is covered by auto csr test.
+ '''
+ milestone: V2S
+ tests: ["clkmgr_csr_rw"]
+ }
+ {
+ name: sec_cm_clk_ctrl_config_regwen
+ desc: '''Verify the countermeasure(s) CLK_CTRL.CONFIG.REGWEN.
+
+ This is covered by auto csr test.
+ '''
+ milestone: V2S
+ tests: ["clkmgr_csr_rw"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/clkmgr/lint/clkmgr.vlt b/hw/top_sencha/ip/clkmgr/lint/clkmgr.vlt
new file mode 100644
index 0000000..5b59fde
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/lint/clkmgr.vlt
@@ -0,0 +1,5 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// waiver file for clkmgr
diff --git a/hw/top_sencha/ip/clkmgr/lint/clkmgr.waiver b/hw/top_sencha/ip/clkmgr/lint/clkmgr.waiver
new file mode 100644
index 0000000..622630f
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/lint/clkmgr.waiver
@@ -0,0 +1,21 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for clkmgr
+
+#
+# fake errors
+
+waive -rules INPUT_NOT_READ -location {prim_clock_gating.sv} -regexp {.*} \
+ -comment "Generated abstraction files use .*'s which create fake errors"
+
+waive -rules EMPTY_PARAM_LIST -location {prim_clock_gating.sv} -regexp {.*} \
+ -comment "Generated abstraction files may have empty params"
+
+waive -rules OUTPUT_NOT_DRIVEN -location {prim_clock_gating.sv} -regexp {.*} \
+ -comment "Generated abstraction files do not detect drivers"
+
+# clock mux errors
+waive -rules CLOCK_MUX -location {clkmgr.sv} -regexp {.*clk_io_div.* is driven by a multiplexer here} \
+ -comment "All divided clocks terminate with a scan mux"
diff --git a/hw/top_sencha/ip/flash_ctrl/BUILD b/hw/top_sencha/ip/flash_ctrl/BUILD
new file mode 100644
index 0000000..3e9bd22
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/flash_ctrl/data:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/flash_ctrl/data/BUILD b/hw/top_sencha/ip/flash_ctrl/data/BUILD
new file mode 100644
index 0000000..20f5e81
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/data/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/flash_ctrl/data/autogen:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/flash_ctrl/data/autogen/BUILD b/hw/top_sencha/ip/flash_ctrl/data/autogen/BUILD
new file mode 100644
index 0000000..fa45ad5
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/data/autogen/BUILD
@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+load("@lowrisc_opentitan//rules:autogen.bzl", "autogen_hjson_header")
+
+autogen_hjson_header(
+ name = "flash_ctrl_regs",
+ srcs = [
+ "flash_ctrl.hjson",
+ ],
+)
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/ip/flash_ctrl/flash_ctrl_system.core b/hw/top_sencha/ip/flash_ctrl/flash_ctrl_system.core
new file mode 100644
index 0000000..15be873
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/flash_ctrl_system.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:flash_ctrl:0.1"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:flash_ctrl_pkg
+ files:
+ - rtl/autogen/flash_ctrl_core_reg_top.sv
+ - rtl/autogen/flash_ctrl_region_cfg.sv
+ - rtl/autogen/flash_ctrl.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/flash_ctrl/flash_ctrl_system_pkg.core b/hw/top_sencha/ip/flash_ctrl/flash_ctrl_system_pkg.core
new file mode 100644
index 0000000..4fafdf0
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/flash_ctrl_system_pkg.core
@@ -0,0 +1,21 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:flash_ctrl_pkg:0.1"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:edn_pkg
+ - lowrisc:constants:top_pkg
+ - lowrisc:prim:util
+ files:
+ - rtl/autogen/flash_ctrl_reg_pkg.sv
+ - rtl/autogen/flash_ctrl_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/pinmux/BUILD b/hw/top_sencha/ip/pinmux/BUILD
new file mode 100644
index 0000000..eec52cf
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/pinmux/data:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/pinmux/data/BUILD b/hw/top_sencha/ip/pinmux/data/BUILD
new file mode 100644
index 0000000..1412e90
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/data/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/pinmux/data/autogen:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/pinmux/data/autogen/BUILD b/hw/top_sencha/ip/pinmux/data/autogen/BUILD
new file mode 100644
index 0000000..5ced915
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/data/autogen/BUILD
@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+load("@lowrisc_opentitan//rules:autogen.bzl", "autogen_hjson_header")
+
+autogen_hjson_header(
+ name = "pinmux_regs",
+ srcs = [
+ "pinmux.hjson",
+ ],
+)
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/ip/pinmux/data/autogen/pinmux_sec_cm_testplan.hjson b/hw/top_sencha/ip/pinmux/data/autogen/pinmux_sec_cm_testplan.hjson
new file mode 100644
index 0000000..7a13b81
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/data/autogen/pinmux_sec_cm_testplan.hjson
@@ -0,0 +1,33 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Security countermeasures testplan extracted from the IP Hjson using reggen.
+//
+// This testplan is auto-generated only the first time it is created. This is
+// because this testplan needs to be hand-editable. It is possible that these
+// testpoints can go out of date if the spec is updated with new
+// countermeasures. When `reggen` is invoked when this testplan already exists,
+// It checks if the list of testpoints is up-to-date and enforces the user to
+// make further manual updates.
+//
+// These countermeasures and their descriptions can be found here:
+// .../pinmux/data/pinmux.hjson
+//
+// It is possible that the testing of some of these countermeasures may already
+// be covered as a testpoint in a different testplan. This duplication is ok -
+// the test would have likely already been developed. We simply map those tests
+// to the testpoints below using the `tests` key.
+//
+// Please ensure that this testplan is imported in:
+// .../pinmux/data/pinmux_testplan.hjson
+{
+ testpoints: [
+ {
+ name: sec_cm_bus_integrity
+ desc: "Verify the countermeasure(s) BUS.INTEGRITY."
+ milestone: V2S
+ tests: []
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/pinmux/fpv/pinmux_chip_fpv.core b/hw/top_sencha/ip/pinmux/fpv/pinmux_chip_fpv.core
new file mode 100644
index 0000000..dfa6894
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/fpv/pinmux_chip_fpv.core
@@ -0,0 +1,39 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:pinmux_chip_fpv:0.1"
+description: "pinmux FPV target with chip_sencha parameters"
+filesets:
+ files_formal:
+ depend:
+ - lowrisc:prim:all
+ - lowrisc:ip:tlul
+ - lowrisc:ip:pinmux
+ - lowrisc:fpv:csr_assert_gen
+ - lowrisc:fpv:pinmux_common_fpv
+ - lowrisc:systems:top_sencha_pkg
+ files:
+ - tb/pinmux_tb.sv
+ file_type: systemVerilogSource
+
+generate:
+ csr_assert_gen:
+ generator: csr_assert_gen
+ parameters:
+ spec: ../data/autogen/pinmux.hjson
+
+targets:
+ default: &default_target
+ default_tool: icarus
+ filesets:
+ - files_formal
+ generate:
+ - csr_assert_gen
+ toplevel: pinmux_tb
+
+ formal:
+ <<: *default_target
+
+ lint:
+ <<: *default_target
diff --git a/hw/top_sencha/ip/pinmux/fpv/tb/pinmux_tb.sv b/hw/top_sencha/ip/pinmux/fpv/tb/pinmux_tb.sv
new file mode 100644
index 0000000..7cd4142
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/fpv/tb/pinmux_tb.sv
@@ -0,0 +1,232 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Testbench module for pinmux.
+// Intended to be used with a formal tool.
+
+module pinmux_tb
+ import pinmux_pkg::*;
+ import pinmux_reg_pkg::*;
+ import prim_pad_wrapper_pkg::*;
+ import top_sencha_pkg::*;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
+ input clk_i,
+ input rst_ni,
+ input prim_mubi_pkg::mubi4_t scanmode_i,
+ input clk_aon_i,
+ input rst_aon_ni,
+ output logic pin_wkup_req_o,
+ output logic usb_wkup_req_o,
+ input sleep_en_i,
+ input strap_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_dft_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i,
+ output dft_strap_test_req_t dft_strap_test_o,
+ input dft_hold_tap_sel_i,
+ output jtag_pkg::jtag_req_t lc_jtag_o,
+ input jtag_pkg::jtag_rsp_t lc_jtag_i,
+ output jtag_pkg::jtag_req_t rv_jtag_o,
+ input jtag_pkg::jtag_rsp_t rv_jtag_i,
+ output jtag_pkg::jtag_req_t dft_jtag_o,
+ input jtag_pkg::jtag_rsp_t dft_jtag_i,
+ input usb_dppullup_en_upwr_i,
+ input usb_dnpullup_en_upwr_i,
+ output usb_dppullup_en_o,
+ output usb_dnpullup_en_o,
+ input usb_out_of_rst_i,
+ input usb_aon_wake_en_i,
+ input usb_aon_wake_ack_i,
+ input usb_suspend_i,
+ output usb_bus_reset_o,
+ output usb_sense_lost_o,
+ output usbdev_pkg::awk_state_t usb_state_debug_o,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ input prim_alert_pkg::alert_rx_t[NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t[NumAlerts-1:0] alert_tx_o,
+ input [NMioPeriphOut-1:0] periph_to_mio_i,
+ input [NMioPeriphOut-1:0] periph_to_mio_oe_i,
+ output logic[NMioPeriphIn-1:0] mio_to_periph_o,
+ input [NDioPads-1:0] periph_to_dio_i,
+ input [NDioPads-1:0] periph_to_dio_oe_i,
+ output logic[NDioPads-1:0] dio_to_periph_o,
+ output prim_pad_wrapper_pkg::pad_attr_t[NMioPads-1:0] mio_attr_o,
+ output logic[NMioPads-1:0] mio_out_o,
+ output logic[NMioPads-1:0] mio_oe_o,
+ input [NMioPads-1:0] mio_in_i,
+ output prim_pad_wrapper_pkg::pad_attr_t[NDioPads-1:0] dio_attr_o,
+ output logic[NDioPads-1:0] dio_out_o,
+ output logic[NDioPads-1:0] dio_oe_o,
+ input [NDioPads-1:0] dio_in_i
+);
+ import top_sencha_pkg::*;
+
+ parameter int Tap0PadIdx = 30;
+ parameter int Tap1PadIdx = 27;
+ parameter int Dft0PadIdx = 25;
+ parameter int Dft1PadIdx = 26;
+ parameter int TckPadIdx = 38;
+ parameter int TmsPadIdx = 35;
+ parameter int TrstNPadIdx = 39;
+ parameter int TdiPadIdx = 37;
+ parameter int TdoPadIdx = 36;
+
+ // Parameters for chip_sencha_asic.
+ localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
+ tck_idx: TckPadIdx,
+ tms_idx: TmsPadIdx,
+ trst_idx: TrstNPadIdx,
+ tdi_idx: TdiPadIdx,
+ tdo_idx: TdoPadIdx,
+ tap_strap0_idx: Tap0PadIdx,
+ tap_strap1_idx: Tap1PadIdx,
+ dft_strap0_idx: Dft0PadIdx,
+ dft_strap1_idx: Dft1PadIdx,
+ usb_dp_idx: DioUsbdevUsbDp,
+ usb_dn_idx: DioUsbdevUsbDn,
+ usb_sense_idx: MioInUsbdevSense,
+ // Pad types for attribute WARL behavior
+ dio_pad_type: {
+ BidirOd, // DIO sysrst_ctrl_aon_flash_wp_l
+ BidirTol, // DIO usbdev_rx_enable
+ BidirTol, // DIO usbdev_suspend
+ BidirTol, // DIO usbdev_tx_mode_se
+ BidirTol, // DIO usbdev_dn_pullup
+ BidirTol, // DIO usbdev_dp_pullup
+ BidirTol, // DIO usbdev_se0
+ BidirStd, // DIO spi_host0_csb
+ BidirStd, // DIO spi_host0_sck
+ BidirTol, // DIO usbdev_sense
+ InputStd, // DIO spi_device_csb
+ InputStd, // DIO spi_device_sck
+ BidirOd, // DIO sysrst_ctrl_aon_ec_rst_l
+ BidirTol, // DIO usbdev_dn
+ BidirTol, // DIO usbdev_dp
+ BidirTol, // DIO usbdev_d
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd // DIO spi_host0_sd
+ },
+ mio_pad_type: {
+ BidirOd, // MIO Pad 46
+ BidirOd, // MIO Pad 45
+ BidirOd, // MIO Pad 44
+ BidirOd, // MIO Pad 43
+ BidirStd, // MIO Pad 42
+ BidirStd, // MIO Pad 41
+ BidirStd, // MIO Pad 40
+ BidirStd, // MIO Pad 39
+ BidirStd, // MIO Pad 38
+ BidirStd, // MIO Pad 37
+ BidirStd, // MIO Pad 36
+ BidirStd, // MIO Pad 35
+ BidirOd, // MIO Pad 34
+ BidirOd, // MIO Pad 33
+ BidirOd, // MIO Pad 32
+ BidirStd, // MIO Pad 31
+ BidirStd, // MIO Pad 30
+ BidirStd, // MIO Pad 29
+ BidirStd, // MIO Pad 28
+ BidirStd, // MIO Pad 27
+ BidirStd, // MIO Pad 26
+ BidirStd, // MIO Pad 25
+ BidirStd, // MIO Pad 24
+ BidirStd, // MIO Pad 23
+ BidirStd, // MIO Pad 22
+ BidirOd, // MIO Pad 21
+ BidirOd, // MIO Pad 20
+ BidirOd, // MIO Pad 19
+ BidirOd, // MIO Pad 18
+ BidirStd, // MIO Pad 17
+ BidirStd, // MIO Pad 16
+ BidirStd, // MIO Pad 15
+ BidirStd, // MIO Pad 14
+ BidirStd, // MIO Pad 13
+ BidirStd, // MIO Pad 12
+ BidirStd, // MIO Pad 11
+ BidirStd, // MIO Pad 10
+ BidirStd, // MIO Pad 9
+ BidirOd, // MIO Pad 8
+ BidirOd, // MIO Pad 7
+ BidirOd, // MIO Pad 6
+ BidirStd, // MIO Pad 5
+ BidirStd, // MIO Pad 4
+ BidirStd, // MIO Pad 3
+ BidirStd, // MIO Pad 2
+ BidirStd, // MIO Pad 1
+ BidirStd // MIO Pad 0
+ }
+ };
+
+ pinmux #(
+ .TargetCfg(PinmuxTargetCfg),
+ .AlertAsyncOn(AlertAsyncOn)
+ ) dut_asic (
+ .clk_i,
+ .rst_ni,
+ .scanmode_i,
+ .clk_aon_i,
+ .rst_aon_ni,
+ .pin_wkup_req_o,
+ .usb_wkup_req_o,
+ .sleep_en_i,
+ .strap_en_i,
+ .lc_dft_en_i,
+ .lc_hw_debug_en_i,
+ .dft_strap_test_o,
+ .dft_hold_tap_sel_i,
+ .lc_jtag_o,
+ .lc_jtag_i,
+ .rv_jtag_o,
+ .rv_jtag_i,
+ .dft_jtag_o,
+ .dft_jtag_i,
+ .usb_dppullup_en_upwr_i,
+ .usb_dnpullup_en_upwr_i,
+ .usb_dppullup_en_o,
+ .usb_dnpullup_en_o,
+ .usb_out_of_rst_i,
+ .usb_aon_wake_en_i,
+ .usb_aon_wake_ack_i,
+ .usb_suspend_i,
+ .usb_state_debug_o,
+ .tl_i,
+ .tl_o,
+ .alert_rx_i,
+ .alert_tx_o,
+ .periph_to_mio_i,
+ .periph_to_mio_oe_i,
+ .mio_to_periph_o,
+ .periph_to_dio_i,
+ .periph_to_dio_oe_i,
+ .dio_to_periph_o,
+ .mio_attr_o,
+ .mio_out_o,
+ .mio_oe_o,
+ .mio_in_i,
+ .dio_attr_o,
+ .dio_out_o,
+ .dio_oe_o,
+ .dio_in_i
+ );
+endmodule : pinmux_tb
diff --git a/hw/top_sencha/ip/pinmux/pinmux_reg.core b/hw/top_sencha/ip/pinmux/pinmux_reg.core
new file mode 100644
index 0000000..bae7bf3
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/pinmux_reg.core
@@ -0,0 +1,21 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:pinmux_reg:0.1"
+description: "Auto-generated pinmux register sources for top_sencha chip."
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:tlul:headers
+
+ files:
+ - rtl/autogen/pinmux_reg_pkg.sv
+ - rtl/autogen/pinmux_reg_top.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/pwrmgr/BUILD b/hw/top_sencha/ip/pwrmgr/BUILD
new file mode 100644
index 0000000..dc75bb1
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/pwrmgr/data:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/pwrmgr/README.md b/hw/top_sencha/ip/pwrmgr/README.md
new file mode 100644
index 0000000..348924e
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/README.md
@@ -0,0 +1,412 @@
+# Power Manager HWIP Technical Specification
+
+# Overview
+
+This document specifies the functionality of the Sencha (based on OpenTitan) power manager.
+
+## Features
+
+- Cold boot, low power entry / exit and reset support.
+- 2 different low power modes.
+- Software initiated low power entry and hardware requested low power exit.
+- Peripheral reset requests
+- Low power abort and low power fall-through support.
+- ROM integrity check at power-up.
+- Local checks for escalator and power stability.
+
+## Description
+
+The power manager sequences power, clocks, and reset resources of the design through cold boot, low power entry/exit and reset scenarios.
+
+Cold boot, also known as POR (power on reset) is the first reset state of the design.
+The power manager sequences the design from a freshly reset state to an active state where software can be initialized.
+
+- Low power entry is the process in which the device enters one of two low power modes (sleep or deep sleep).
+- Low power exit is the process in which the device exits low power mode and returns to active state.
+- Low power entry is always initiated by software, while low power exit is always initiated by a previously setup hardware event such as pins or internal timers.
+- The power manager processes the software and hardware requests to perform the appropriate actions.
+
+Reset scenarios refer to non-POR events that cause the device to reboot.
+There are various stimuli that can cause such a reset, ranging from external user input to watchdog timeout.
+The power manager processes the reset request and brings the device to an appropriate state.
+
+
+# Theory Of Operation
+
+The power manager performs the following functions:
+- Turn on/off power domain(s).
+- Control root resets with the reset manager.
+- Control root clock enables with AST and clock manager.
+- Sequence various power up activities such as OTP sensing, life cycle initiation and releasing software to execute.
+
+
+## Block Diagram
+
+See the below high level block diagram that illustrates the connections between the power manager and various system components.
+Blocks outlined with a solid magenta line are always on; while blocks outlined with a dashed magenta line are a mix of components that are and those that are not.
+
+
+
+## Hardware Interfaces
+
+* [Interface Tables](../../top_sencha/ip/pwrmgr/data/autogen/pwrmgr.hjson#interfaces)
+
+## Overall Sequencing
+
+The power manager contains two state machines.
+One operates on the always-on slow clock (this clock is always running and usually measured in KHz) and is responsible for turning faster clocks on and off and managing the power domains.
+The other operates on a normal fixed clock (usually measured in MHz) and is responsible for everything else in the power sequence.
+
+The following diagram breaks down the general functionality of both.
+The state machines are colored based on their clock domains.
+The green state machine is clocked by the normal fixed domain, while the orange state machine is clocked by the slow domain.
+Specific request / acknowledge signals are also highlighted in this color scheme to show where the two state machines communicate.
+
+
+
+
+Note, most of the states are transitional states, and only the following state combinations are resting states.
+
+
+* Slow FSM `Idle` and fast FSM `Active`
+* Slow FSM `Low Power` and fast FSM `Low Power`
+
+The slow FSM `Low Power` and fast FSM `Active` states specifically are concepts useful when examining [reset handling](#reset-request-handling).
+
+
+## Slow Clock Domain FSM
+
+The slow clock domain FSM (referred to as the slow FSM from here on) resets to the Reset state.
+This state is released by `por_rst_n`, which is supplied from the reset controller.
+The `por_rst_n` signal is released when the reset controller detects the root power domains (`vcaon_pok` from AST) of the system are ready.
+Please see the [ast](../../top_sencha/ip/ast/README.md) for more details.
+
+The slow FSM requests the AST to power up the main domain and high speed clocks.
+Once those steps are done, it requests the [fast FSM](#fast-clock-domain-fsm) to begin operation.
+The slow FSM also handles power isolation controls as part of this process.
+
+Once the fast FSM acknowledges the power-up completion, the slow FSM transitions to `Idle` and waits for a power down request.
+When a power down request is received, the slow FSM turns off AST clocks and power as directed by software configuration.
+This means the clocks and power are not always turned off, but are rather controlled by software configurations in [`CONTROL`](../pwm/data/pwm.hjson#control) prior to low power entry .
+Once these steps are complete, the slow FSM transitions to a low power state and awaits a wake request, which can come either as an actual wakeup, or a reset event (for example always on watchdog expiration).
+
+#### Sparse FSM
+
+Since the slow FSM is sparsely encoded, it is possible for the FSM to end up in an undefined state if attacked.
+When this occurs, the slow FSM sends an `invalid` indication to the fast FSM and forcibly powers off and clamps everything.
+
+The clocks are kept on however to allow the fast FSM to operate if it is able to receive the `invalid` indication.
+The slow FSM does not recover from this state until the system is reset by POR.
+
+Unlike [escalation resets](#escalation-reset-request), the system does not self reset.
+Instead the system goes into a terminal non-responsive state where a user or host must directly intervene by toggling the power or asserting an external reset input.
+
+## Fast Clock Domain FSM
+
+The fast clock domain FSM (referred to as fast FSM from here on) resets to `Low Power` state and waits for a power-up request from the slow FSM.
+
+Once received, the fast FSM releases the life cycle reset stage (see [reset controller]({{< relref "hw/ip/rstmgr/doc" >}}) for more details).
+This allows the [OTP](../otp_ctrl/README.md) to begin sensing.
+Once OTP sensing completes , the life cycle controller is initialized.
+The initialization of the life cycle controller puts the device into its allowed operating state (see [life cycle controller](../lc_ctrl/README.md) for more details).
+
+Once life cycle initialization is done, the fast FSM enables all second level clock gating (see [clock controller](../clkmgr/README.md) for more details) and initiates strap sampling.
+For more details on what exactly the strap samples, please see [here](https://docs.google.com/spreadsheets/d/1pH8T1MhQ7TXtP_bFNT85T9jSVIHlxHAfbMnPbsMdjc0/edit?usp=sharing).
+
+Once strap sampling is complete, the system is ready to begin normal operations (note `flash_ctrl` initialization is explicitly not done here, please see [sections below](#flash-handling) for more details).
+The fast FSM acknowledges the slow FSM (which made the original power up request) and releases the system reset stage - this enables the processor to begin operation.
+Afterwards, the fast FSM transitions to `Active` state and waits for a software low power entry request.
+
+A low power request is initiated by software through a combination of WFI and software low power hint in [`CONTROL`](../pwm/data/pwm.hjson#control).
+Specifically, this means if software issues only WFI, the power manager does not treat it as a power down request.
+The notion of WFI is exported from the processor.
+For Ibex, this is currently in the form of `core_sleeping_o`.
+
+In response to the low power entry request, the fast FSM disables all second level clock gating.
+Before proceeding, the fast FSM explicitly separates the handling between a normal low power entry and a [reset request](#reset-request-handlig).
+
+For low power entry, there are two cases, [fall through handling](#fall-through-handling) and [abort handling](#abort-handling).
+If none of these exception cases are matched for low power entry, the fast FSM then asserts appropriate resets as necessary and requests the slow FSM to take over.
+
+For reset requests, fall through and aborts are not checked and the system simply resets directly.
+Note in this scenario the slow FSM is not requested to take over.
+
+#### Sparse FSM
+
+Since the fast FSM is sparsely encoded, it is possible for the FSM to end up in an undefined state if attacked.
+When this occurs, the fast FSM forcibly disables all clocks and holds the system in reset.
+
+The fast FSM does not recover from this state until the system is reset by POR.
+
+
+### ROM Integrity Checks
+
+The power manager coordinates the [start up ROM check](../rom_ctrl/README.md#the-startup-rom-check) with `rom_ctrl`.
+
+After every reset, the power manager sends an indication to the `rom_ctrl` to begin performing integrity checks.
+When the `rom_ctrl` checks are finished, a `done` and `good` indication are sent back to the power manager.
+
+If the device is in life cycle test states (`TEST_UNLOCKED` or `RMA`), the `good` signal is ignored and the ROM contents are always allowed to execute.
+
+If the device is not in one of the test states, the `good` signal is used to determine ROM execution.
+If `good` is true, ROM execution is allowed.
+If `good` is false, ROM execution is disallowed.
+
+### Fall Through Handling
+
+A low power entry fall through occurs when some condition occurs that immediately de-assert the entry conditions right after the software requests it.
+
+This can happen if right after software asserts WFI, an interrupt is shown to the processor, thus breaking it out of its currently stopped state.
+Whether this type of fall through happens is highly dependent on how the system handles interrupts during low power entry - some systems may choose to completely silence any interrupt not related to wakeup, others may choose to leave them all enabled.
+The fall through handle is specifically catered to the latter category.
+
+For a normal low power entry, the fast FSM first checks that the low power entry conditions are still true.
+If the entry conditions are no longer true, the fast FSM "falls through" the entry handling and returns the system to active state, thus terminating the entry process.
+
+### Abort Handling
+
+If the entry conditions are still true, the fast FSM then checks there are no ongoing non-volatile activities from `otp_ctrl`, `lc_ctrl` and `flash_ctrl`.
+If any module is active, the fast FSM "aborts" entry handling and returns the system to active state, thus terminating the entry process.
+
+## Reset Request Handling
+
+There are 4 reset requests in the system
+- peripheral requested reset such as watchdog.
+- reset manager's software requested reset, which is functionally very similar to a peripheral requested reset.
+- power manager's internal reset request.
+- Non-debug module reset.
+
+Flash brownout is handled separately and described in [flash handling section](#flash-handling) below.
+
+Peripheral requested resets such as watchdog are handled directly by the power manager, while the non-debug module reset is handled by the reset controller.
+This separation is because the non-debug reset does not affect the life cycle controller, non-volatile storage controllers and alert states.
+There is thus no need to sequence its operation like the others.
+
+The power controller only observes reset requests in two states - the slow FSM `Low Power` state and the fast FSM `Active` state.
+When a reset request is received during slow FSM `Low Power` state, the system begins its usual power up sequence even if a wakeup has not been received.
+
+When a reset request is received during fast FSM `Active` state, the fast FSM asserts resets and transitions back to its `Low Power` state.
+The normal power-up process described [above](#fast-clock-domain-fsm) is then followed to release the resets.
+Note in this case, the slow FSM is "not activated" and remains in its `Idle` state.
+
+### Power Manager Internal Reset Requests
+
+In additional to external requests, the power manager maintains 2 internal reset requests:
+* Escalation reset request
+* Main power domain unstable reset request
+
+#### Escalation Reset Request
+
+Alert escalation resets in general behave similarly to peripheral requested resets.
+However, peripheral resets are always handled gracefully and follow the normal FSM transition.
+
+Alert escalations can happen at any time and do not always obey normal rules.
+As a result, upon alert escalation, the power manager makes a best case effort to transition directly into reset handling.
+
+This may not always be possible if the escalation happens while the FSM is in an invalid state.
+In this scenario, the pwrmgr keeps everything powered off and silenced and requests escalation handling if the system ever wakes up.
+
+#### Escalation Clock Timeout
+
+Under normal behavior, the power manager can receive escalation requests from the system and handle them [appropriately](#escalation-reset-request).
+However, if the escalation clock or reset are non-functional for any reason, the escalation request would not be serviced.
+
+To mitigate this, the power manager actively checks for escalation interface clock/reset timeout.
+This is done by a continuous request / acknowledge interface between the power manager's local clock/reset and the escalate network's clock/reset.
+
+If the request / acknowledge interface does not respond within 128 power manager clock cycles, the escalate domain is assumed to be off.
+When this happens, the power manager creates a local escalation request that behaves identically to the global escalation request.
+
+
+#### Main Power Unstable Reset Requests
+If the main power ever becomes unstable (the power okay indication is low even though it is powered on), the power manager requests an internal reset.
+This reset behaves similarly to the escalation reset and transitions directly into reset handling.
+
+Note that under normal low power conditions, the main power may be be turned off.
+As a result of this, the main power unstable checks are valid only during states that power should be on and stable.
+This includes any state where power manager has requested the power to be turned on.
+
+
+### Reset Requests Received During Other States
+
+All other states in the slow / fast FSM are considered transitional states.
+Resets are not observed in other states because the system will always be transitioning towards one of the steady states (the system is in the process of powering down or powering up).
+Once a steady state is reached, reset requests are then observed and processed.
+
+### Reset Recording
+
+There are three ways in which the device is reset:
+- Non-debug-module reset request
+- Low power entry (`sleep_req` in the state diagram)
+- Direct reset requests by peripherals or alert escalation
+
+The power manager does not handle the non-debug-module request (please see reset controller).
+For the remaining two reset causes, the power manager handles only 1 pathway at a time (see state diagrams).
+This means if reset request and low power entry collide, the power manager will handle them on a first come first served basis.
+When the handling of the first is completed, the power manager handles the second pending request if it is still present.
+
+This is done because low power resets and peripheral requested resets lead to different behaviors.
+When the power manager commits to handling a specific request, it informs the reset manager why it has reset the processor.
+
+For example, assume a low power entry request arrives slightly ahead of reset requests.
+The power manager will:
+- Transition the system into low power state.
+- Inform the reset manager to record "low power exit" as the reset reason.
+- Once in low state, transition the system to `Active` state by using the reset request as a wakeup indicator.
+- Inform the reset manager to also record the peripheral that requested reset.
+- Once in `Active` state, reset the system and begin normal power-up routines again.
+
+If reset requests arrive slightly ahead of a low power entry request, then power manager will:
+- Reset the system and begin normal power-up routines.
+- Inform the reset manager to record the peripheral that requested reset.
+- Once in `Active` state, if the low power entry request is still present, transition to low power state.
+ - Inform the reset manager to also record "low power exit" as the reset reason.
+- If the low power entry request was wiped out by reset, the system then stays in `Active` state and awaits software instructions.
+
+Ultimately when control is returned to software, it may see two reset reasons and must handle them accordingly.
+
+
+## Wakeup Recording
+
+Similar to [reset handling](#reset-request-handling), wakeup signals are only observed during slow FSM `Low Power`; however their recording is continuous until explicitly disabled by software.
+
+Wakeup recording begins when the fast FSM transitions out of `Active` state and continues until explicitly disabled by software.
+This ensures wakeup events are not missed until software has set up the appropriate peripherals.
+
+The software is also able to enable recording during `Active` state if it chooses to do so. The recording enables are OR’d together for hardware purposes.
+
+
+## Flash Handling
+For the section below, flash macro refers to the proprietary flash storage supplied by a vendor.
+`flash_ctrl`, on the other hand, refers to the open source controller that manages access to the flash macro.
+
+### Power-Up Handling
+
+The [AST](../../top_sencha/ip/ast/README.md) automatically takes the flash macro out of power down state as part of the power manager's power up request.
+
+Once flash macro is powered up and ready, an indication is sent to the `flash_ctrl`.
+
+Once the boot ROM is allowed to execute, it is expected to further initialize the `flash_ctrl` and flash macro prior to using it.
+This involves the following steps:
+
+* Poll `flash_ctrl` register to ensure flash macro has powered up and completed internal initialization.
+* Initialize `flash_ctrl` seed reading and scrambling.
+
+### Power-Down Handling
+
+Before the device enters low power, the pwrmgr first checks to ensure there are no ongoing transactions to the flash macro.
+When the device enters deep sleep, the flash macro is automatically put into power down mode by the AST.
+The AST places the flash macro into power down through direct signaling between AST and flash macro, the pwrmgr is not directly involved.
+
+When the device exits low power state, it is the responsibility of the boot ROM to poll for flash macro and `flash_ctrl` power-up complete similar to the above section.
+
+### Flash Brownout Handling
+
+When the external supply of the device dips below a certain threshold during a non-volatile flash macro operation (program or erase), the flash macro requires the operation to terminate in a pre-defined manner.
+This sequence will be exclusively handled by the AST.
+
+The power manager is unaware of the difference between POR and flash brownout.
+Because of this, the software also cannot distinguish between these two reset causes.
+
+
+## Supported Low Power Modes
+
+This section details the various low power modes supported by OpenTitan.
+
+
+### Deep Sleep or Standby
+
+This is the lowest power mode of the device (outside of full power down or device held in reset).
+During this state:
+
+* All clocks other than the always-on slow clock are turned off at the source.
+* All non-always-on digital domains are powered off.
+* I/O power domains may or may not be off.
+ * The state of the IO power domain has no impact on the digital core’s power budget, e.g. the IO power being off does not cause the accompanying digital logic in pads or elsewhere to leak more.
+
+
+### Normal Sleep
+
+This is a fast low power mode of the device that trades-off power consumption for resume latency.
+During this state:
+
+* All clocks other than the KHz slow clock are turned off at the source.
+* All power domains are kept on for fast resume.
+* Sensor countermeasures can be opportunistically on.
+* I/O power domains may or may not be off.
+ * The state of the IO power domain has no impact on the digital core’s power budget, e.g. the IO power being off does not cause the accompanying digital logic in pads or elsewhere to leak more.
+
+## Debug
+
+When performing TAP debug, it is important for the debugging software to prevent the system from going to low power.
+If the system enters low power during live debug, the debug session will be broken.
+There is currently no standardized way to do this, so it is up to the debugging agent to perform the correct steps.
+
+
+# Programmers Guide
+
+The process in which the power manager is used is highly dependent on the system's topology.
+The following proposes one method for how this can be done.
+
+Assume first the system has the power states described [above](#supported-low-power-modes).
+
+## Programmer Sequence for Entering Low Power
+
+1. Disable interrupts
+2. Enable desired wakeup and reset sources in [`WAKEUP_EN`](../pwm/data/pwm.hjson#wakeup_en) and [`RESET_EN`](../pwm/data/pwm.hjson#reset_en).
+3. Perform any system-specific low power entry steps, e.g.
+ - Interrupt checks (if something became pending prior to disable)
+4. Configure low power mode in [`CONTROL`](../pwm/data/pwm.hjson#control).
+5. Set low power hint in [`LOW_POWER_HINT`](../pwm/data/pwm.hjson#low_power_hint).
+6. Set and poll [`CFG_CDC_SYNC`](../pwm/data/pwm.hjson#cfg_cdc_sync) to ensure above settings propagate across clock domains.
+7. Execute wait-for-interrupt instruction on the processing host.
+
+### Possible Exits
+
+Once low power is initiated, the system may exit due to several reasons.
+1. Graceful low power exit - This exit occurs when some source in the system gracefully wakes up the power manager.
+2. System reset request - This exit occurs when either software or a peripheral requests the pwrmgr to reset the system.
+3. [Fall through exit](#fall-through-handling) - This exit occurs when an interrupt manages to break the wait-for-interrupt loop.
+4. [Aborted entry](#abort-handling) - This exit occurs when low power entry is attempted with an ongoing non-volatile transaction.
+
+In both fall through exit and aborted entry, the power manager does not actually enter low power.
+Instead the low power entry is interrupted and the system restored to active state.
+
+## Programmer Sequence for Exiting Low Power
+
+There are two separate cases for low power exit.
+One is exiting from deep sleep, and the other is exiting from normal sleep.
+
+### Exiting from Deep Sleep
+
+When exiting from deep sleep, the system begins execution in ROM.
+
+1. Complete normal preparation steps.
+2. Check reset cause in [rstmgr](../rstmgr/README.md)
+3. Re-enable modules that have powered down.
+4. Disable wakeup recording through [`WAKE_INFO_CAPTURE_DIS`](../pwm/data/pwm.hjson#wake_info_capture_dis).
+5. Check which source woke up the system through [`WAKE_INFO`](../pwm/data/pwm.hjson#wake_info).
+6. Take appropriate steps to handle the wake and resume normal operation.
+7. Once wake is handled, clear the wake indication in [`WAKE_INFO`](../pwm/data/pwm.hjson#wake_info).
+
+### Exiting from Normal Sleep
+
+The handling for fall-through and abort are similar to normal sleep exit.
+Since in these scenarios the system was not reset, software continues executing the instruction after the wait-for-interrupt invocation.
+
+1. Check exit condition to determine appropriate steps.
+2. Clear low power hints and configuration in [`CONTROL`](../pwm/data/pwm.hjson#control).
+3. Set and poll [`CFG_CDC_SYNC`](../pwm/data/pwm.hjson#cfg_cdc_sync) to ensure setting changes have propagated across clock boundaries.
+4. Disable wakeup sources and stop recording.
+5. Re-enable interrupts for normal operation and wakeup handling.
+6. Once wake is handled, clear the wake indication in [`WAKE_INFO`](../pwm/data/pwm.hjson#wake_info).
+
+For an in-depth discussion, please see [power management programmers model](https://docs.google.com/document/d/1w86rmvylJgZVmmQ6Q1YBcCp2VFctkQT3zJ408SJMLPE/edit?usp=sharing) for additional details.
+
+## Device Interface Functions (DIFs)
+
+- [Device Interface Functions](../../../sw/device/lib/dif/dif_pwrmgr.h)
+
+## Register Table
+
+* [Register Table](../../top_sencha/ip/pwrmgr/data/autogen/pwrmgr.hjson#registers)
diff --git a/hw/top_sencha/ip/pwrmgr/data/BUILD b/hw/top_sencha/ip/pwrmgr/data/BUILD
new file mode 100644
index 0000000..e920389
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/data/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/pwrmgr/data/autogen:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/pwrmgr/data/autogen/BUILD b/hw/top_sencha/ip/pwrmgr/data/autogen/BUILD
new file mode 100644
index 0000000..8c59276
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/data/autogen/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+load("@lowrisc_opentitan//rules:autogen.bzl", "autogen_hjson_header")
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/ip/pwrmgr/data/pwrmgr.hjson.tpl b/hw/top_sencha/ip/pwrmgr/data/pwrmgr.hjson.tpl
new file mode 100644
index 0000000..864a09a
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/data/pwrmgr.hjson.tpl
@@ -0,0 +1,724 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+<%
+ # Additional reset
+ int_reset_reqs = rst_reqs["int"]
+ debug_reset_reqs = rst_reqs["debug"]
+%>\
+{
+ name: "pwrmgr",
+ human_name: "Power Manager",
+ one_line_desc: "Sequences on-chip power, clocks, and resets through different reset and power states",
+ one_paragraph_desc: '''
+ Power Manager sequences on-chip power, clocks, and reset signals on power-on reset (aka cold boot), low power entry and exit, and non-power-on resets.
+ To this end, it can turn power domains on and off, control root resets with Reset Manager, and control root clock enables with AST and Clock Manager.
+ During power up, Power Manager is responsible for triggering OTP sensing, initiating Life Cycle Controller, coordinating with ROM Controller for the startup ROM check, and eventually releasing software to execute.
+ It features several countermeasures to deter fault injection (FI) attacks.
+ '''
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_pwrmgr",
+ revisions: [
+ {
+ version: "0.1",
+ life_stage: "L1",
+ design_stage: "D1",
+ verification_stage: "V0", // this module is not verified at the block level
+ dif_stage: "S0",
+ commit_id: "b2abc989498f072d9a5530f8aab9b58c1f92c9fb"
+ }
+ {
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D2S",
+ verification_stage: "V2S",
+ dif_stage: "S2",
+ }
+ ]
+ clocking: [
+ {clock: "clk_i", reset: "rst_ni", primary: true},
+ {reset: "rst_main_ni"},
+ {clock: "clk_slow_i", reset: "rst_slow_ni"},
+ {clock: "clk_lc_i", reset: "rst_lc_ni"},
+ {clock: "clk_esc_i", reset: "rst_esc_ni"}
+ ]
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device" }
+ ],
+ interrupt_list: [
+ { name: "wakeup", desc: "Wake from low power state. See wake info for more details" },
+ ],
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+ '''
+ }
+ ],
+
+ inter_signal_list: [
+ { struct: "pwr_ast",
+ type: "req_rsp",
+ name: "pwr_ast",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_rst",
+ type: "req_rsp",
+ name: "pwr_rst",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_clk",
+ type: "req_rsp",
+ name: "pwr_clk",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_otp",
+ type: "req_rsp",
+ name: "pwr_otp",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_lc",
+ type: "req_rsp",
+ name: "pwr_lc",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_flash",
+ type: "uni",
+ name: "pwr_flash",
+ act: "rcv",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "esc_tx",
+ type: "uni",
+ name: "esc_rst_tx",
+ act: "rcv",
+ package: "prim_esc_pkg",
+ },
+
+ { struct: "esc_rx",
+ type: "uni",
+ name: "esc_rst_rx",
+ act: "req",
+ package: "prim_esc_pkg",
+ },
+
+ { struct: "pwr_cpu",
+ type: "uni",
+ name: "pwr_cpu",
+ act: "rcv",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "logic",
+ width: ${NumWkups},
+ type: "uni",
+ name: "wakeups",
+ act: "rcv",
+ package: "",
+ },
+
+ { struct: "logic",
+ width: ${NumRstReqs},
+ type: "uni",
+ name: "rstreqs",
+ act: "rcv",
+ package: "",
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "ndmreset_req",
+ act: "rcv",
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "strap",
+ act: "req",
+ package: "",
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "low_power",
+ act: "req",
+ package: "",
+ },
+
+ { struct: "pwrmgr_data",
+ type: "uni",
+ name: "rom_ctrl",
+ act: "rcv",
+ package: "rom_ctrl_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "fetch_en",
+ act: "req",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_dft_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_hw_debug_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "sw_rst_req",
+ act: "rcv",
+ package: "prim_mubi_pkg",
+ },
+ ],
+
+ param_list: [
+ { name: "NumWkups",
+ desc: "Number of wakeups",
+ type: "int",
+ default: "${NumWkups}",
+ local: "true"
+ },
+
+ % for wkup in Wkups:
+ { name: "${wkup['module'].upper()}_${wkup['name'].upper()}_IDX",
+ desc: "Vector index for ${wkup['module']} ${wkup['name']}, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO",
+ type: "int",
+ default: "${loop.index}",
+ local: "true"
+ },
+
+ % endfor
+
+ { name: "NumRstReqs",
+ desc: "Number of peripheral reset requets",
+ type: "int",
+ default: "${NumRstReqs}",
+ local: "true"
+ },
+
+ { name: "NumIntRstReqs",
+ desc: "Number of pwrmgr internal reset requets",
+ type: "int",
+ default: "${len(int_reset_reqs)}",
+ local: "true"
+ },
+
+ { name: "NumDebugRstReqs",
+ desc: "Number of debug reset requets",
+ type: "int",
+ default: "${len(debug_reset_reqs)}",
+ local: "true"
+ },
+
+ % for req in int_reset_reqs + debug_reset_reqs:
+ { name: "${f"Reset{req['name']}Idx"}",
+ desc: "Reset req idx for ${req['name']}",
+ type: "int",
+ default: "${loop.index + NumRstReqs}",
+ local: "true"
+ },
+ % endfor
+
+ ],
+ countermeasures: [
+ { name: "BUS.INTEGRITY",
+ desc: "End-to-end bus integrity scheme."
+ }
+ { name: "LC_CTRL.INTERSIG.MUBI",
+ desc: "life cycle control / debug signals are multibit."
+ }
+ { name: "ROM_CTRL.INTERSIG.MUBI",
+ desc: "rom control done/good signals are multibit."
+ }
+ { name: "RSTMGR.INTERSIG.MUBI",
+ desc: "reset manager software request is multibit."
+ }
+ { name: "ESC_RX.CLK.BKGN_CHK",
+ desc: "Escalation receiver has a background timeout check"
+ }
+ { name: "ESC_RX.CLK.LOCAL_ESC",
+ desc: "Escalation receiver clock timeout has a local reset escalation"
+ }
+ { name: "FSM.SPARSE",
+ desc: "Sparse encoding for slow and fast state machines."
+ }
+ { name: "FSM.TERMINAL",
+ desc: '''
+ When FSMs reach a bad state, go into a terminate state that does not
+ recover without user or external host intervention.
+ '''
+ }
+ { name: "CTRL_FLOW.GLOBAL_ESC",
+ desc: "When global escalation is received, proceed directly to reset."
+ }
+ { name: "MAIN_PD.RST.LOCAL_ESC",
+ desc: "When main power domain reset glitches, proceed directly to reset."
+ }
+ { name: "CTRL.CONFIG.REGWEN",
+ desc: "Main control protected by regwen."
+ }
+ { name: "WAKEUP.CONFIG.REGWEN",
+ desc: "Wakeup configuration protected by regwen."
+ }
+ { name: "RESET.CONFIG.REGWEN",
+ desc: "Reset configuration protected by regwen."
+ }
+
+ ]
+
+ regwidth: "32",
+ registers: [
+
+ { name: "CTRL_CFG_REGWEN",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ desc: '''
+ Controls the configurability of the !!CONTROL register.
+
+ This register ensures the contents do not change once a low power hint and
+ WFI has occurred.
+
+ It unlocks whenever a low power transition has completed (transition back to the
+ ACTIVE state) for any reason.
+ ''',
+
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Configuration enable.
+
+ This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated.
+ When the device transitions back from low power state to active state, this bit is set
+ back to 1 to allow software configuration of !!CONTROL
+ ''',
+ resval: "1",
+ },
+ ]
+ tags: [// This regwen is completely under HW management and thus cannot be manipulated
+ // by software.
+ "excl:CsrNonInitTests:CsrExclCheck"]
+ },
+
+
+ { name: "CONTROL",
+ desc: "Control register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "CTRL_CFG_REGWEN",
+ tags: [// Turning off USB clock in active state impacts other CSRs
+ // at the chip level (in other blocks, such as clkmgr),
+ // so we exclude writing from this register.
+ "excl:CsrAllTests:CsrExclWrite"]
+ fields: [
+ { bits: "0",
+ hwaccess: "hrw",
+ name: "LOW_POWER_HINT",
+ desc: '''
+ The low power hint to power manager.
+ The hint is an indication for how the manager should treat the next WFI.
+ Once the power manager begins a low power transition, or if a valid reset request is registered,
+ this bit is automatically cleared by HW.
+ '''
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "None",
+ desc: '''
+ No low power intent
+ '''
+ },
+ { value: "1",
+ name: "Low Power",
+ desc: '''
+ Next WFI should trigger low power entry
+ '''
+ },
+ ]
+ tags: [// The regwen for this reg is RO. CSR seq can't support to check this reg
+ "excl:CsrAllTests:CsrExclAll"]
+ },
+
+ { bits: "4",
+ name: "CORE_CLK_EN",
+ desc: "core clock enable during low power state",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Disabled",
+ desc: '''
+ Core clock disabled during low power state
+ '''
+ },
+ { value: "1",
+ name: "Enabled",
+ desc: '''
+ Core clock enabled during low power state
+ '''
+ },
+ ]
+ },
+
+ { bits: "5",
+ name: "IO_CLK_EN",
+ desc: "IO clock enable during low power state",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Disabled",
+ desc: '''
+ IO clock disabled during low power state
+ '''
+ },
+ { value: "1",
+ name: "Enabled",
+ desc: '''
+ IO clock enabled during low power state
+ '''
+ },
+ ]
+ },
+
+ { bits: "6",
+ name: "USB_CLK_EN_LP",
+ desc: "USB clock enable during low power state",
+ resval: "0",
+ enum: [
+ { value: "0",
+ name: "Disabled",
+ desc: '''
+ USB clock disabled during low power state
+ '''
+ },
+ { value: "1",
+ name: "Enabled",
+ desc: '''
+ USB clock enabled during low power state.
+
+ However, if !!CONTROL.MAIN_PD_N is 0, USB clock is disabled
+ during low power state.
+ '''
+ },
+ ]
+ },
+
+ { bits: "7",
+ name: "USB_CLK_EN_ACTIVE",
+ desc: "USB clock enable during active power state",
+ resval: "1"
+ enum: [
+ { value: "0",
+ name: "Disabled",
+ desc: '''
+ USB clock disabled during active power state
+ '''
+ },
+ { value: "1",
+ name: "Enabled",
+ desc: '''
+ USB clock enabled during active power state
+ '''
+ },
+ ]
+ },
+
+ { bits: "8",
+ name: "MAIN_PD_N",
+ desc: "Active low, main power domain power down",
+ resval: "1"
+ enum: [
+ { value: "0",
+ name: "Power down",
+ desc: '''
+ Main power domain is powered down during low power state.
+ '''
+ },
+ { value: "1",
+ name: "Power up",
+ desc: '''
+ Main power domain is kept powered during low power state
+ '''
+ },
+ ]
+ },
+
+
+ ],
+ },
+
+ { name: "CFG_CDC_SYNC",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ hwqe: "true",
+ desc: '''
+ The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the
+ fast clock domain but used in the slow clock domain.
+
+ The configuration are not propagated across the clock boundary until this
+ register is triggered and read. See fields below for more details
+ ''',
+
+ fields: [
+ { bits: "0",
+ name: "SYNC",
+ desc: '''
+ Configuration sync. When this bit is written to 1, a sync pulse is generated. When
+ the sync completes, this bit then self clears.
+
+ Software should write this bit to 1, wait for it to clear, before assuming the slow clock
+ domain has accepted the programmed values.
+ ''',
+ resval: "0",
+ },
+ ]
+ tags: [// This bit triggers a payload synchronization and self clears when complete.
+ // Do not write this bit as there will be side effects and the value will not persist
+ "excl:CsrNonInitTests:CsrExclWrite"]
+ },
+
+ { name: "WAKEUP_EN_REGWEN",
+ desc: "Configuration enable for wakeup_en register",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ resval: "1"
+ name: "EN",
+ desc: '''
+ When 1, WAKEUP_EN register can be configured.
+ When 0, WAKEUP_EN register cannot be configured.
+ ''',
+ },
+ ]
+ },
+
+ { multireg:
+ { name: "WAKEUP_EN",
+ desc: "Bit mask for enabled wakeups",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WAKEUP_EN_REGWEN",
+ resval: "0"
+ cname: "wakeup_en",
+ count: "NumWkups"
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Whenever a particular bit is set to 1, that wakeup is also enabled.
+ Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.
+ ''',
+ },
+ ]
+ },
+ },
+
+ { multireg:
+ { name: "WAKE_STATUS",
+ desc: "A read only register of all current wake requests post enable mask",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ resval: "0"
+ cname: "wake_status",
+ count: "NumWkups",
+ tags: [// Cannot auto-predict current wake request status
+ "excl:CsrNonInitTests:CsrExclWriteCheck"],
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ Current value of wake requests
+ ''',
+ },
+ ]
+ },
+ },
+
+ { name: "RESET_EN_REGWEN",
+ desc: "Configuration enable for reset_en register",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ resval: "1"
+ name: "EN",
+ desc: '''
+ When 1, RESET_EN register can be configured.
+ When 0, RESET_EN register cannot be configured.
+ ''',
+ },
+ ]
+ },
+
+ { multireg:
+ { name: "RESET_EN",
+ desc: "Bit mask for enabled reset requests",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "RESET_EN_REGWEN",
+ resval: "0"
+ cname: "rstreq_en",
+ count: "NumRstReqs"
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Whenever a particular bit is set to 1, that reset request is enabled.
+ Whenever a particular bit is set to 0, that reset request cannot reset the device.
+ ''',
+ },
+ ]
+ tags: [// Self resets should never be triggered by automated tests
+ "excl:CsrAllTests:CsrExclWrite"]
+ },
+ },
+
+ { multireg:
+ { name: "RESET_STATUS",
+ desc: "A read only register of all current reset requests post enable mask",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ resval: "0"
+ cname: "reset_status",
+ count: "NumRstReqs",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ Current value of reset request
+ ''',
+ },
+ ]
+ },
+ },
+
+ { name: "ESCALATE_RESET_STATUS",
+ desc: "A read only register of escalation reset request",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ resval: "0"
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ When 1, an escalation reset has been seen.
+ When 0, there is no escalation reset.
+ ''',
+ },
+ ]
+ },
+
+ { name: "WAKE_INFO_CAPTURE_DIS",
+ desc: "Indicates which functions caused the chip to wakeup",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0"
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ When written to 1, this actively suppresses the wakeup info capture.
+ When written to 0, wakeup info capture timing is controlled by HW.
+ ''',
+ },
+ ]
+ },
+
+ { name: "WAKE_INFO",
+ desc: '''
+ Indicates which functions caused the chip to wakeup.
+ The wake info recording begins whenever the device begins a valid low power entry.
+
+ This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS.
+ This means it is possible to capture multiple wakeup reasons.
+ ''',
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ hwext: "true",
+ hwqe: "true",
+ resval: "0"
+ fields: [
+ { bits: "${NumWkups-1}:0",
+ name: "REASONS",
+ desc: "Various peripheral wake reasons"
+ },
+ { bits: "${NumWkups}",
+ name: "FALL_THROUGH",
+ desc: '''
+ The fall through wakeup reason indicates that despite setting a WFI and providing a low power
+ hint, an interrupt arrived at just the right time to break the executing core out of WFI.
+
+ The power manager detects this condition, halts low power entry and reports as a wakeup reason
+ ''',
+ },
+ { bits: "${NumWkups+1}",
+ name: "ABORT",
+ desc: '''
+ The abort wakeup reason indicates that despite setting a WFI and providing a low power
+ hint, an active flash / lifecycle / otp transaction was ongoing when the power controller
+ attempted to initiate low power entry.
+
+ The power manager detects this condition, halts low power entry and reports as a wakeup reason
+ ''',
+ },
+ ]
+ tags: [// This regwen is completely under HW management and thus cannot be manipulated
+ // by software.
+ "excl:CsrNonInitTests:CsrExclCheck"]
+ },
+
+ { name: "FAULT_STATUS",
+ desc: "A read only register that shows the existing faults",
+ swaccess: "ro",
+ hwaccess: "hrw",
+ sync: "clk_lc_i",
+ resval: "0"
+ fields: [
+ { bits: "0",
+ name: "REG_INTG_ERR",
+ desc: '''
+ When 1, an integrity error has occurred.
+ ''',
+ },
+
+ { bits: "1",
+ name: "ESC_TIMEOUT",
+ desc: '''
+ When 1, an escalation clock / reset timeout has occurred.
+ ''',
+ },
+
+ { bits: "2",
+ name: "MAIN_PD_GLITCH",
+ desc: '''
+ When 1, unexpected power glitch was observed on main PD.
+ ''',
+ },
+ ]
+ },
+ ]
+}
diff --git a/hw/top_sencha/ip/pwrmgr/data/pwrmgr_testplan.hjson b/hw/top_sencha/ip/pwrmgr/data/pwrmgr_testplan.hjson
new file mode 100644
index 0000000..95058d4
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/data/pwrmgr_testplan.hjson
@@ -0,0 +1,353 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "pwrmgr"
+ // TODO: remove the common testplans if not applicable
+ import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
+ // TODO: Top-level specific Hjson imported here. This will likely be resolved
+ // once we move to IPgen flow.
+ "hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr_sec_cm_testplan.hjson"]
+ testpoints: [
+ {
+ name: smoke
+ desc: '''
+ Smoke test exercising the pwrmgr state transitions.
+
+ - Brings pwrmgr out of POR.
+ - Enables wakeup.
+ - Triggers SW initiated low power transition with reset settings
+ in `control` CSR.
+ - Triggers wakeup.
+ - Enables and triggers a reset.
+ - Waits for pwrmgr to be out of reset.
+
+ **Stimulus**:
+ - CSR writes to `wakeup_en`, `reset_en`, and `low_power_hint`.
+ - Needs many input pins to line up correctly in order to prevent the
+ pwrmgr from waiting forever. Most of these are set in response
+ to outputs, and are checked by SVA.
+
+ **Checks**:
+ - The fast fsm becomes active when `fetch_en_o` output rises.
+ - The wakeup and reset causes are as expected reading CSRs
+ `wake_status` and `reset_status`.
+ - The output `pwr_rst_req.reset_cause` matches a low power or
+ reset cause.
+ - The output `pwr_rst_req.rstreqs` matches the enabled resets.
+ '''
+ stage: V1
+ tests: ["pwrmgr_smoke"]
+ }
+ {
+ name: wakeup
+ desc: '''
+ Test random wakeup, wakeup_en, wake_info_capture_dis, and
+ interrupt.
+
+ The different wakeup inputs can be disabled via bits in the
+ `wakeup_en` CSR. Update of `wakeup_info` can be disabled
+ via the `wake_info_capture_dis` CSR. Any wakeup causes an
+ interrupt unless interrupts are disabled.
+
+ **Stimulus**:
+ - Sets `wakeup_en` randomly but don't set it to zero, or the
+ test will timeout.
+ - Set `wake_info_capture_dis` randomly on and off.
+ - Bring pwrmgr to low power.
+ - Set `wakeups_i` inputs randomly.
+ - Set `intr_enable` randomly.
+
+ **Checks**:
+ - The fast fsm becomes active when `fetch_en_o` output rises.
+ - Depending on `wakeups_i`:
+ - If all wakeups are disabled, wait some time checking the
+ state remains inactive.
+ - Set `wakeups_i` so at least one is enabled.
+ - Checks `wakeup_status` CSR during transition to active state
+ since the reset involved will clear the wakeups_i input.
+ - Checks the `wake_info` CSR.
+ - Checks the output `pwr_rst_req.reset_cause` is `LowPwrEntry`.
+ - Check that `intr_wakeup_o` is set according to `intr_enable` CSR.
+ - Coverage collected by `wakeup_cg` and `wakeup_intr_cg`.
+ '''
+ stage: V2
+ tests: ["pwrmgr_wakeup"]
+ }
+ {
+ name: control_clks
+ desc: '''
+ Test CSR control of peripheral clocks during low power.
+
+ The peripheral clocks can be configured to remain on or be turned
+ off during low power with bits in the `control` CSR register. The
+ usb clock can also be configured off in active mode.
+
+ **Stimulus**:
+ - Sets these control bits at random.
+ - Cause a low power transition and wakeup.
+
+ **Checks**:
+ - The clock enable outputs to the AST clocks during a low
+ power transition match the control bits.
+ - The usb clock enable is also checked during active mode against
+ the control register.
+ '''
+ stage: V2
+ tests: ["pwrmgr_wakeup"]
+ }
+ {
+ name: aborted_low_power
+ desc: '''
+ Test aborted low power transitions.
+
+ Low power transitions can be aborted in two cases:
+ - The processor gets an interrupt soon after a low power entry is
+ triggered.
+ - OTP, LC, or FLASH are not idle.
+ This test aborts low power transitions, and disables any wakeups,
+ so the test would timeout if low power was entered.
+
+ **Stimulus**:
+ - Bring pwrmgr to low power.
+ - Either disable `pwr_cpu.core_sleeping` or keep some of `lc_idle`,
+ `otp_idle`, or `flash_idle` inputs off.
+ - Disable all wakeup enables.
+ - Randomly set `wakeup_info_capture_dis` CSR.
+
+ **Checks**:
+ - The `ctrl_cfg_regwen` CSR reads as 1 on the first attempt.
+ - Checks the output `pwr_rst_req.reset_cause` doesn't change for
+ a bounded amount of time.
+ - Check that the `wakeup_info` CSR flags either `fall_through` or
+ `abort` events when capture is enabled.
+ '''
+ stage: V2
+ tests: ["pwrmgr_aborted_low_power", "pwrmgr_lowpower_invalid"]
+ }
+ {
+ name: reset
+ desc: '''
+ Test random reset and reset_en.
+
+ Conditional reset inputs can be disabled via bits in the `reset_en`
+ CSR, while escalation and main power are unconditional. Resets can
+ be triggered either in active or low power state.
+
+ **Stimulus**:
+ - Sets `reset_en` randomly.
+ - Randomly choose whether to put the unit in low power mode.
+ - Generate resets randomly in value and time:
+ - Conditionals via rstreqs_i,
+ - Main power glitch via rst_main_ni.
+ - Escalation via `esc_rst_tx_i`.
+ - Sw reset from rstmgr via `sw_rst_req_i`.
+
+ **Checks**:
+ - The fast fsm becomes active when `fetch_en_o` output rises.
+ - Checks the `reset_status` CSRs.
+ - Checks `ip_clk_en` output has a low transition.
+ - SVA that when `pwr_rst_req.reset_cause` is HwReq, and the output
+ `pwr_rst_req.rstreqs` matches the unconditional and enabled
+ conditional resets inputs.
+ '''
+ stage: V2
+ tests: ["pwrmgr_reset", "pwrmgr_reset_invalid"]
+ }
+ {
+ name: main_power_glitch_reset
+ desc: '''
+ Test reset due to a glitch in main power.
+
+ A power glitch causes an unconditional reset.
+
+ **Stimulus**:
+ - Set the rst_main_ni input low indicating a main power glitch.
+
+ **Checks**:
+ - The fast fsm becomes active when `fetch_en_o` output rises.
+ - Checks the `reset_status` CSRs.
+ - Checks `ip_clk_en` output has a low transition.
+ - Checks the output `pwr_rst_req.reset_cause` matches HwReq.
+ - Checks the output `pwr_rst_req.rstreqs` matches power glitch.
+ '''
+ stage: V2
+ tests: ["pwrmgr_reset"]
+ }
+ {
+ name: reset_wakeup_race
+ desc: '''
+ Test wakeup from low power and reset request almost coinciding.
+
+ If a wakeup from low power and a reset occur at nearly the same time
+ the system handles them one at a time.
+
+ **Stimulus**:
+ - Trigger reset and wakeup from low power as described for other
+ testpoints.
+ - Issue reset and wakeup a random number of cycles after the slow
+ state machine is in LowPower state.
+ - This also checks them coinciding.
+
+ **Check**:
+ - Similar tests as for the wakeup and reset testpoints, except
+ making sure they happen per the triggering order.
+ '''
+ stage: V2
+ tests: ["pwrmgr_wakeup_reset"]
+ }
+ {
+ name: lowpower_wakeup_race
+ desc: '''
+ Test wakeups coming close to lowpower entry.
+
+ If low power entry and a wakeup are closely aligned the hardware
+ could get confused. Notice this is very unlikely, since wakeup is
+ only sensed when the slow fsm is in LowPower state.
+
+ **Stimulus**:
+ - Trigger low power entry as described for other testpoints.
+ - Have all wakeups enabled.
+ - Assert wakeups_i in the temporal neighborhood of low power
+ entry.
+
+ **Check**:
+ - No timeout occurs.
+ - Either pwrmgr remains active or a full low power cycle occurs.
+ '''
+ stage: V2
+ tests: ["pwrmgr_lowpower_wakeup_race"]
+ }
+ {
+ name: disable_rom_integrity_check
+ desc: '''
+ Test rom integrity check is disabled under life cycle test states.
+
+ While running a series of reset event, at FastPwrStateRomCheck
+ state,
+ - Drive lc_hw_debug_en_i and lc_dft_en_i to random value
+ excluding {lc_ctrl_pkg::On, lc_ctrl_pkg::On} for both ports.
+ - Set rom_ctrl_i.good = Mubi4False.
+ - Wait for a while to make sure fsm state check is not FastPwrStateActive.
+
+ Then,
+ - Drive lc_hw_debug_en_i and lc_dft_en_i to {lc_ctrl_pkg::On, lc_ctrl_pkg::On}
+ - Check test finish gracefully.
+
+ Try these steps with different lc_ctrl inputs.
+ '''
+ stage: V2
+ tests: ["pwrmgr_disable_rom_integrity_check"]
+ }
+ {
+ name: stress_all
+ desc: '''This runs random sequences in succession.
+
+ Randomly chooses from the following sequences:
+ - pwrmgr_aborted_low_power_vseq
+ - pwrmgr_lowpower_wakeup_race_vseq
+ - pwrmgr_reset_vseq
+ - pwrmgr_smoke_vseq
+ - pwrmgr_wakeup_reset_vseq
+ - pwrmgr_wakeup_vseq
+ '''
+ stage: V2
+ tests: ["pwrmgr_stress_all"]
+ }
+ ]
+
+ covergroups: [
+ {
+ name: wakeup_ctrl_cg
+ desc: '''
+ Collects coverage on wakeup enable and capture functionality.
+
+ This is collected per individual wakeup bit. Covergroup contains
+ coverpoints for the `wakeup_en` CSR bit, `wakeup_info_capture_dis`
+ CSR, `wakeups_i` input bit, and `wakeup_status` CSR bit, and their
+ cross.
+ '''
+ }
+ {
+ name: wakeup_intr_cg
+ desc: '''
+ Collects coverage on interrupts for wakeup functionality.
+
+ This is collected per individual wakeup bit. Covergroup contains
+ coverpoints for the `intr_en` CSR, the `wakeup_status` CSR bit,
+ the `intr_status` CSR, the output `intr_wakeup` port, and their
+ cross.
+ '''
+ }
+ {
+ name: control_cg
+ desc: '''
+ Collects coverage on clock and power bits from `control` CSR during
+ a lowpower transition and active state.
+ '''
+ }
+ {
+ name: hw_reset_0_cg
+ desc: '''
+ Collects coverage related to external reset `0`.
+
+ Covergroup contains coverpoints for the `rstreqs_i[0]` external
+ reset input, its corresponding bit in `reset_en` CSR, and whether
+ this reset is asserted during low power state, and suitable crosses.
+ '''
+ }
+ {
+ name: hw_reset_1_cg
+ desc: '''
+ Collects coverage related to external reset `1`.
+
+ Covergroup contains coverpoints for the `rstreqs_i[1]` external
+ reset input, its corresponding bit in `reset_en` CSR, and whether
+ this reset is asserted during low power state, and suitable crosses.
+ '''
+ }
+ {
+ name: rstmgr_sw_reset_cg
+ desc: '''
+ Collects coverage on the software reset from rstmgr.
+
+ Covergroup contains a coverpoint for the input `sw_rst_req_i` from
+ rstmgr.
+ '''
+ }
+ {
+ name: main_power_reset_cg
+ desc: '''
+ Collects coverage on resets due to a main power glitch.
+
+ Covergroup contains a coverpoint for the input `rst_main_i` that
+ triggers a power glitch reset, and whether this reset is asserted
+ during low power state.
+ '''
+ }
+ {
+ name: esc_reset_cg
+ desc: '''
+ Collects coverage on resets due to escalation.
+
+ Covergroup contains a coverpoint for the input `esc_rst_tx_i` that
+ triggers an escalation reset, and whether this reset is asserted
+ during low power state.
+ '''
+ }
+ {
+ name: reset_wakeup_distance_cg
+ desc: '''
+ Covergroup contains a coverpoint for the difference between the
+ cycles when the reset and the wakeup were received in the inputs.
+ The difference is positive when reset happened after wakeup, and
+ zero when the two happened at the same clock cycle.
+ '''
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/pwrmgr/doc/checklist.md b/hw/top_sencha/ip/pwrmgr/doc/checklist.md
new file mode 100644
index 0000000..d62e270
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/doc/checklist.md
@@ -0,0 +1,266 @@
+# PWRMGR Checklist
+
+This checklist is for [Hardware Stage](../../../../doc/project_governance/development_stages.md) transitions for the [PWRMGR peripheral.](../README.md)
+All checklist items refer to the content in the [Checklist.](../../../../doc/project_governance/checklist/README.md)
+
+## Design Checklist
+
+### D1
+
+Type | Item | Resolution | Note/Collaterals
+--------------|--------------------------------|-------------|------------------
+Documentation | [SPEC_COMPLETE][] | Done |[PWRMGR Design Spec](../README.md)
+Documentation | [CSR_DEFINED][] | Done |
+RTL | [CLKRST_CONNECTED][] | Done |
+RTL | [IP_TOP][] | Done |
+RTL | [IP_INSTANTIABLE][] | Done |
+RTL | [PHYSICAL_MACROS_DEFINED_80][] | N/A |
+RTL | [FUNC_IMPLEMENTED][] | Done |
+RTL | [ASSERT_KNOWN_ADDED][] | Done |
+Code Quality | [LINT_SETUP][] | Done |
+
+[SPEC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#spec_complete
+[CSR_DEFINED]: ../../../../doc/project_governance/checklist/README.md#csr_defined
+[CLKRST_CONNECTED]: ../../../../doc/project_governance/checklist/README.md#clkrst_connected
+[IP_TOP]: ../../../../doc/project_governance/checklist/README.md#ip_top
+[IP_INSTANTIABLE]: ../../../../doc/project_governance/checklist/README.md#ip_instantiable
+[PHYSICAL_MACROS_DEFINED_80]: ../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80
+[FUNC_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#func_implemented
+[ASSERT_KNOWN_ADDED]: ../../../../doc/project_governance/checklist/README.md#assert_known_added
+[LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#lint_setup
+
+### D2
+
+Type | Item | Resolution | Note/Collaterals
+--------------|---------------------------|-------------|------------------
+Documentation | [NEW_FEATURES][] | Done |
+Documentation | [BLOCK_DIAGRAM][] | Done |
+Documentation | [DOC_INTERFACE][] | Done |
+Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively.
+Documentation | [MISSING_FUNC][] | Done |
+Documentation | [FEATURE_FROZEN][] | Done |
+RTL | [FEATURE_COMPLETE][] | Done |
+RTL | [PORT_FROZEN][] | Done |
+RTL | [ARCHITECTURE_FROZEN][] | Done |
+RTL | [REVIEW_TODO][] | Done |
+RTL | [STYLE_X][] | Done |
+RTL | [CDC_SYNCMACRO][] | N/A |
+Code Quality | [LINT_PASS][] | Done |
+Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff.
+Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff.
+Code Quality | [AREA_CHECK][] | Done |
+Code Quality | [TIMING_CHECK][] | Done |
+Security | [SEC_CM_DOCUMENTED][] | Done |
+
+[NEW_FEATURES]: ../../../../doc/project_governance/checklist/README.md#new_features
+[BLOCK_DIAGRAM]: ../../../../doc/project_governance/checklist/README.md#block_diagram
+[DOC_INTERFACE]: ../../../../doc/project_governance/checklist/README.md#doc_interface
+[DOC_INTEGRATION_GUIDE]: ../../../../doc/project_governance/checklist/README.md#doc_integration_guide
+[MISSING_FUNC]: ../../../../doc/project_governance/checklist/README.md#missing_func
+[FEATURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#feature_frozen
+[FEATURE_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#feature_complete
+[PORT_FROZEN]: ../../../../doc/project_governance/checklist/README.md#port_frozen
+[ARCHITECTURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#architecture_frozen
+[REVIEW_TODO]: ../../../../doc/project_governance/checklist/README.md#review_todo
+[STYLE_X]: ../../../../doc/project_governance/checklist/README.md#style_x
+[CDC_SYNCMACRO]: ../../../../doc/project_governance/checklist/README.md#cdc_syncmacro
+[LINT_PASS]: ../../../../doc/project_governance/checklist/README.md#lint_pass
+[CDC_SETUP]: ../../../../doc/project_governance/checklist/README.md#cdc_setup
+[RDC_SETUP]: ../../../../doc/project_governance/checklist/README.md#rdc_setup
+[AREA_CHECK]: ../../../../doc/project_governance/checklist/README.md#area_check
+[TIMING_CHECK]: ../../../../doc/project_governance/checklist/README.md#timing_check
+[SEC_CM_DOCUMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_documented
+
+### D2S
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|------------------------------|-------------|------------------
+Security | [SEC_CM_ASSETS_LISTED][] | Done |
+Security | [SEC_CM_IMPLEMENTED][] | Done |
+Security | [SEC_CM_RND_CNST][] | N/A |
+Security | [SEC_CM_NON_RESET_FLOPS][] | Done |
+Security | [SEC_CM_SHADOW_REGS][] | Done |
+Security | [SEC_CM_RTL_REVIEWED][] | Done |
+Security | [SEC_CM_COUNCIL_REVIEWED][] | Done |
+
+[SEC_CM_ASSETS_LISTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed
+[SEC_CM_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_implemented
+[SEC_CM_RND_CNST]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst
+[SEC_CM_NON_RESET_FLOPS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops
+[SEC_CM_SHADOW_REGS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs
+[SEC_CM_RTL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed
+[SEC_CM_COUNCIL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed
+
+### D3
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES_D3][] | Not Started |
+RTL | [TODO_COMPLETE][] | Not Started |
+Code Quality | [LINT_COMPLETE][] | Not Started |
+Code Quality | [CDC_COMPLETE][] | Not Started |
+Code Quality | [RDC_COMPLETE][] | Not Started |
+Review | [REVIEW_RTL][] | Not Started |
+Review | [REVIEW_DELETED_FF][] | Not Started |
+Review | [REVIEW_SW_CHANGE][] | Not Started |
+Review | [REVIEW_SW_ERRATA][] | Not Started |
+Review | Reviewer(s) | Not Started |
+Review | Signoff date | Not Started |
+
+[NEW_FEATURES_D3]: ../../../../doc/project_governance/checklist/README.md#new_features_d3
+[TODO_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#todo_complete
+[LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#lint_complete
+[CDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#cdc_complete
+[RDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#rdc_complete
+[REVIEW_RTL]: ../../../../doc/project_governance/checklist/README.md#review_rtl
+[REVIEW_DELETED_FF]: ../../../../doc/project_governance/checklist/README.md#review_deleted_ff
+[REVIEW_SW_CHANGE]: ../../../../doc/project_governance/checklist/README.md#review_sw_change
+[REVIEW_SW_ERRATA]: ../../../../doc/project_governance/checklist/README.md#review_sw_errata
+
+## Verification Checklist
+
+### V1
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|---------------------------------------|-------------|------------------
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [PWRMGR DV document](../dv/README.md)
+Documentation | [TESTPLAN_COMPLETED][] | Done | [PWRMGR testplan](../dv/README.md#testplan)
+Testbench | [TB_TOP_CREATED][] | Done |
+Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
+Testbench | [SIM_TB_ENV_CREATED][] | Done |
+Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done |
+Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done |
+Testbench | [TB_GEN_AUTOMATED][] | Done |
+Tests | [SIM_SMOKE_TEST_PASSING][] | Done |
+Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | Block has no mem
+Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A |
+Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium
+Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done |
+Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done |
+Regression | [FPV_REGRESSION_SETUP][] | N/A |
+Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done |
+Code Quality | [TB_LINT_SETUP][] | Done |
+Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done |
+Review | [DESIGN_SPEC_REVIEWED][] | Done |
+Review | [TESTPLAN_REVIEWED][] | Done |
+Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exceptions: debug, power, performance
+Review | [V2_CHECKLIST_SCOPED][] | Done |
+
+[DV_DOC_DRAFT_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed
+[TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#testplan_completed
+[TB_TOP_CREATED]: ../../../../doc/project_governance/checklist/README.md#tb_top_created
+[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added
+[SIM_TB_ENV_CREATED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_created
+[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated
+[CSR_CHECK_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated
+[TB_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#tb_gen_automated
+[SIM_SMOKE_TEST_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing
+[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing
+[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven
+[SIM_ALT_TOOL_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup
+[SIM_SMOKE_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup
+[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup
+[FPV_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#fpv_regression_setup
+[SIM_COVERAGE_MODEL_ADDED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added
+[TB_LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#tb_lint_setup
+[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1
+[DESIGN_SPEC_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#design_spec_reviewed
+[TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#testplan_reviewed
+[STD_TEST_CATEGORIES_PLANNED]: ../../../../doc/project_governance/checklist/README.md#std_test_categories_planned
+[V2_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped
+
+### V2
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done |
+Documentation | [DV_DOC_COMPLETED][] | Done |
+Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done |
+Testbench | [ALL_INTERFACES_EXERCISED][] | Done |
+Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done |
+Testbench | [SIM_TB_ENV_COMPLETED][] | Done |
+Tests | [SIM_ALL_TESTS_PASSING][] | Done |
+Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | NA |
+Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | NA |
+Tests | [SIM_FW_SIMULATED][] | Done |
+Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done |
+Coverage | [SIM_CODE_COVERAGE_V2][] | Done |
+Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done |
+Coverage | [FPV_CODE_COVERAGE_V2][] | NA |
+Coverage | [FPV_COI_COVERAGE_V2][] | NA |
+Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Done |
+Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done |
+Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done |
+Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done |
+Review | [V3_CHECKLIST_SCOPED][] | Done |
+
+[DESIGN_DELTAS_CAPTURED_V2]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2
+[DV_DOC_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_completed
+[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented
+[ALL_INTERFACES_EXERCISED]: ../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised
+[ALL_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added
+[SIM_TB_ENV_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed
+[SIM_ALL_TESTS_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing
+[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written
+[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed
+[SIM_FW_SIMULATED]: ../../../../doc/project_governance/checklist/README.md#sim_fw_simulated
+[SIM_NIGHTLY_REGRESSION_V2]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2
+[SIM_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2
+[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2
+[FPV_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2
+[FPV_COI_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2
+[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2
+[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending
+[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused
+[DV_DOC_TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed
+[V3_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped
+
+### V2S
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------------|-------------|------------------
+Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done |
+Tests | [FPV_SEC_CM_VERIFIED][] | Done |
+Tests | [SIM_SEC_CM_VERIFIED][] | Done |
+Coverage | [SIM_COVERAGE_REVIEWED][] | Done | UNR will be added after intra structure issue is resolved.
+Review | [SEC_CM_DV_REVIEWED][] | Done |
+
+[SEC_CM_TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed
+[FPV_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified
+[SIM_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified
+[SIM_COVERAGE_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed
+[SEC_CM_DV_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed
+
+### V3
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started |
+Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started |
+Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started |
+Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started |
+Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started |
+Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started |
+Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started |
+Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started |
+Code Quality | [ALL_TODOS_RESOLVED][] | Not Started |
+Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started |
+Code Quality | [TB_LINT_COMPLETE][] | Not Started |
+Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started |
+Issues | [NO_ISSUES_PENDING][] | Not Started |
+Review | Reviewer(s) | Not Started |
+Review | Signoff date | Not Started |
+
+[DESIGN_DELTAS_CAPTURED_V3]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3
+[X_PROP_ANALYSIS_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed
+[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3
+[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3
+[SIM_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100
+[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100
+[FPV_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100
+[FPV_COI_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100
+[ALL_TODOS_RESOLVED]: ../../../../doc/project_governance/checklist/README.md#all_todos_resolved
+[NO_TOOL_WARNINGS_THROWN]: ../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown
+[TB_LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#tb_lint_complete
+[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3
+[NO_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_issues_pending
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\ No newline at end of file
diff --git a/hw/top_sencha/ip/pwrmgr/dv/README.md b/hw/top_sencha/ip/pwrmgr/dv/README.md
new file mode 100644
index 0000000..04490f5
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/README.md
@@ -0,0 +1,256 @@
+# PWRMGR DV document
+
+## Goals
+* **DV**
+ * Verify all PWRMGR IP features by running dynamic simulations with a SV/UVM based testbench.
+ * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules.
+* **FPV**
+ * Verify TileLink device protocol compliance with an SVA based testbench.
+
+## Current status
+* [Design & verification stage](../doc/checklist.md)
+ * [HW development stages](../../../../doc/project_governance/development_stages.md)
+* [Simulation results](https://reports.opentitan.org/hw/ip/pwrmgr/dv/latest/report.html)
+
+## Design features
+For detailed information on PWRMGR design features, please see the [PWRMGR HWIP technical specification](../README.md).
+
+## Testbench architecture
+PWRMGR testbench has been constructed based on the [CIP testbench architecture](../../../dv/sv/cip_lib/README.md).
+
+### Block diagram
+
+
+### Top level testbench
+Top level testbench is located at [`hw/ip/pwrmgr/dv/tb.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/dv/tb.sv).
+It instantiates the PWRMGR DUT module [`hw/ip/pwrmgr/rtl/pwrmgr.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/rtl/pwrmgr.sv).
+In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
+* [Clock and reset interface](../../../dv/sv/common_ifs/README.md)
+* [TileLink host interface](../../../dv/sv/tl_agent/README.md)
+* PWRMGR interface [`hw/ip/pwrmgr/dv/env/pwrmgr_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/dv/env/pwrmgr_if.sv).
+* Interrupts ([`pins_if`](../../../dv/sv/common_ifs/README.md))
+* Alerts ([`alert_esc_if`](../../../dv/sv/alert_esc_agent/README.md))
+* Devmode ([`pins_if`](../../../dv/sv/common_ifs/README.md))
+
+### Common DV utility components
+The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
+* [dv_utils_pkg](../../../dv/sv/dv_utils/README.md)
+* [csr_utils_pkg](../../../dv/sv/csr_utils/README.md)
+
+### Global types & methods
+All common types and methods defined at the package level can be found in
+[`pwrmgr_env_pkg`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/dv/env/pwrmgr_env_pkg.sv).
+Some of them in use are:
+```systemverilog
+ typedef enum int {
+ WakeupSysrst,
+ WakeupDbgCable,
+ WakeupPin,
+ WakeupUsb,
+ WakeupAonTimer,
+ WakeupSensorCtrl
+ } wakeup_e;
+
+ typedef struct packed {
+ logic main_pd_n;
+ logic usb_clk_en_active;
+ logic usb_clk_en_lp;
+ logic io_clk_en;
+ logic core_clk_en;
+ } control_enables_t;
+
+ typedef bit [pwrmgr_reg_pkg::NumWkups-1:0] wakeups_t;
+ typedef bit [pwrmgr_reg_pkg::NumRstReqs-1:0] resets_t;
+
+ // This is used to send all resets to rstmgr.
+ typedef bit [pwrmgr_pkg::HwResetWidth-1:0] resets_out_t;
+```
+### TL_agent
+PWRMGR testbench instantiates (already handled in CIP base env) [tl_agent](../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into PWRMGR device.
+
+### UVM RAL Model
+The PWRMGR RAL model is created with the [`ralgen`](../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage.
+
+It can be created manually by invoking [`regtool`](../../../../util/reggen/doc/setup_and_use.md).
+
+### Stimulus strategy
+The sequences are closely related to the testplan's testpoints.
+Testpoints and coverage are described in more detail in the [testplan](#testplan).
+All test sequences reside in [`hw/ip/pwrmgr/dv/env/seq_lib`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/dv/env/seq_lib), and extend `pwrmgr_base_vseq`.
+The `pwrmgr_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point.
+It provides commonly used handles, variables, functions and tasks used by the test sequences.
+Some of the most commonly used tasks and functions are as follows:
+* task `wait_for_fast_fsm_active`:
+ Waits for the `fetch_en_o` output to become 1, indicating the fast fsm is active and the CPU can fetch instructions.
+ We wait for this before the tests can start, since any CSR accesses require the CPU to be running.
+ Due to complexities in the UVM sequences this task is called in the virtual post_apply_reset task of dv_base_vseq.
+* task `wait_for_csr_to_propagate_to_slow_domain`:
+ Waits for `cfg_cdc_sync` CSR to be clear, indicating the CDC to the slow clock has completed.
+* task `wait_for_reset_cause`:
+ Waits for the `pwr_rst_req.reset_cause` output to match an expected cause.
+* task `check_wait_info`:
+ Checks the wake_info CSR matches expectations.
+* task `check_reset_status`:
+ Checks the reset_status CSR matches expectations.
+* task `check_and_clear_interrupt`:
+ Checks the interrupt enable, status, and output pin.
+
+In addition, the base sequence provides two tasks that provide expected inputs based on the pwrmgr outputs.
+In the absence of these inputs the pwrmgr will be stuck waiting forever.
+Being based on outputs means the inputs are in accordance to the implicit protocol.
+The tasks in question are:
+* task `slow_responder`:
+ Handles required input changes from AST for the slow state machine.
+ For the various `<clk>_en` outputs it changes the `<clk>_val` as required, for `core`, `io`, `main`, and `usb` clocks.
+* task `fast_responder`:
+ Handles input changes for the fast state machine.
+ * Completes the handshake with rstmgr for lc and sys resets: some random cycles after an output reset is requested the corresponding reset src input must go low.
+ * Completes the handshake with clkmgr: the various `<clk>_status` inputs need to match the corresponding `<clk>_ip_clk_en` output after some cycles, for `io`, `main`, and `usb` clocks.
+ * Completes the handshake with lc and otp: both *_done inputs must match the corresponding *_init outputs after some cycles.
+
+These tasks are started by the parent sequence's `pre_start` task, and terminated gracefully in the parent sequence's `post_start` task.
+### Test sequences
+The test sequences besides the base are as follows:
+* `pwrmgr_smoke_vseq` tests the pwrmgr through POR, entry and exit from software initiated low power and reset.
+* `pwrmgr_wakeup_vseq` checks the transitions to low power and the wakeup settings.
+ It randomizes wakeup inputs, wakeup enables, the wakeup info capture enable, and the interrupt enable.
+* `pwrmgr_aborted_low_power_vseq` creates scenarios that lead to aborting a low power transition.
+ The abort can be due to the processor waking up very soon, or otp, lc, or flash being busy.
+* `pwrmgr_reset_vseq` checks the pwrmgr response to conditional resets and reset enables, and unconditional escalation and main power glitch resets.
+* `pwrmgr_wakeup_reset_vseq` aligns reset and wakeup from low power.
+* `pwrmgr_lowpower_wakeup_race_vseq` aligns a wakeup event coming in proximity to low power entry.
+ Notice the wakeup is not expected to impact low power entry, since it is not sampled at this time.
+
+### Functional coverage
+To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model.
+The following covergroups have been developed to prove that the test intent has been adequately met:
+* `wakeup_ctrl_cg` covers wakeup and capture control.
+* `wakeup_intr_cg` covers control of the interrupt due to a wakeup.
+* `control_cg` covers clock controls.
+* `hw_reset_0_cg` covers external reset via `rstreqs_i[0]`.
+* `hw_reset_1_cg` covers external reset via `rstreqs_i[1]`.
+* `rstmgr_sw_reset_cg` covers software initiated resets via rstmgr CSR.
+* `main_power_reset_cg` covers resets due to a main power glitch.
+* `esc_reset_cg` covers resets due to an incoming escalation.
+* `reset_wakeup_distance_cg` covers the distance in clock cycles between a wakeup and a reset request.
+
+More details about these sequences and covergroups can be found at [testplan](#testplan).
+
+### Self-checking strategy
+Many of the checks are performed via SVA, and are enabled for all test sequences.
+Refer to the [assertions](#assertions) section below for details.
+
+#### Scoreboard
+The `pwrmgr_scoreboard` is primarily used for end to end checking.
+
+Many inputs must have specific transitions to prevent the pwrmgr fsms from wait forever.
+When possible the transitions are triggered by pwrmgr output changes.
+These are described according to the unit that originates or is the recipient of the ports.
+See also the test plan for specific ways these are driven to trigger different testpoints.
+
+##### AST
+- Output `slow_clk_en` is always on.
+- Input `slow_clk_val` is unused.
+- Outputs `core_clk_en`, `io_clk_en`, and `usb_clk_en` reset low, and go high prior to the slow fsm requesting the fast fsm to wakeup.
+ Notice the usb clock can be programmed to stay low on wakeup via the `control` CSR.
+ These clock enables are cleared on reset, and should match their corresponding enables in the `control` CSR on low power transitions.
+ These clock enables are checked via SVAs in [`hw/ip/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv).
+ When slow fsm transitions to `SlowPwrStateReqPwrUp` the clock enables should be on (except usb should match `control.usb_clk_en_active`).
+ When slow fsm transitions to `SlowPwrStatePwrClampOn` the clock enables should match their bits in the `control` CSR.
+- Inputs `core_clk_val`, `io_clk_val`, and `usb_clk_val` track the corresponding enables.
+ They are driven by `slow_responder`, which turn them off when their enables go off, and turn them back on a few random slow clock cycles after their enables go on.
+ Slow fsm waits for them to go high prior to requesting fast fsm wakeup.
+ Lack of a high transition when needed is detected via timeout.
+ Such timeout would be due to the corresponding enables being set incorrectly.
+ These inputs are checked via SVAs in [`hw/ip/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv).
+- Output `main_pd_n` should go high when slow fsm transitions to `SlowPwrStateMainPowerOn`, and should match `control.main_pd_n` CSR when slow fsm transitions to `SlowPwrStateMainPowerOff`.
+- Input `main_pok` should turn on for the slow fsm to start power up sequence.
+ This is also driven by `slow_responder`, which turn this off in response to `main_pd_n` going low, and turn it back on after a few random slow clock cycles from `main_pd_n` going high.
+ Lack of a high transition causes a timeout, and would point to `main_pd_n` being set incorrectly.
+- Output transitions of `pwr_clamp_env` must always precede transitions of
+ `pwr_clamp` output.
+ Output transitions of `pwr_clamp` to active must always precede transitions
+ of `main_pd_n` output to active.
+ Output transitions of `pwr_clamp` to inactive must always follow transitions
+ of `main_pd_n` output to inactive.
+
+##### RSTMGR
+- Output `rst_lc_req` resets to 1, also set on reset transition, and on low power transitions that turn off main clock.
+ Cleared early on during the steps to fast fsm active.
+- Input `rst_lc_src_n` go low in response to `rst_lc_req` high, go high when `rst_lc_req` clears (and lc is reset).
+ Driven by `fast_responder` in response to `rst_lc_req`, waiting a few random cycles prior to transitions.
+ Fast fsm waits for it to go low before deactivating, and for it to go high before activating.
+ Checked implicitly by lack of timeout: a timeout would be due to `rst_lc_req` being set incorrectly, and by SVA as described below.
+- Output `rst_sys_req` resets to 1, also set to on reset, and on low power transitions that turn off main clock.
+ Cleared right before the fast fsm goes active.
+- Input `rst_sys_src_n` go low in response to `rst_sys_req` high.
+ Transitions go high when `rst_sysd_req` clears (and lc is reset).
+ Fast fsm waits for it to go low before deactivating.
+ Also driver by `fast_responder`.
+ Checked implicitly by lack of timeout, and by SVA.
+- Output `rstreqs` correspond to the enabled pwrmgr rstreqs inputs plus main power glitch, escalation reset, and software reset request from RSTMGR.
+ Checked in scoreboard and SVA.
+- Output `reset_cause` indicates a reset is due to low power entry or a reset request.
+ Checked in scoreboard.
+
+##### CLKMGR
+- Outputs `pwr_clk_o.<clk>_ip_clk_en` reset low, are driven high by fast fsm when going active, and driven low when going inactive.
+ The `<clk>` correspond to `io`, `main`, and `usb`.
+- Inputs `pwr_clk_i.<clk>_status` are expected to track `pwr_clk_o.<clk>_ip_clk_en`.
+ Fast fsm waits for them going high prior to going active, and going low prior to deactivating.
+ These are controlled by the `control` CSR.
+ Driven by `fast_responder`, which turns them off when `<clk>_ip_clk_en` goes low, and turns them back on a few random cycles after `<clk>_ip_clk_en` goes high.
+ Checked by lack of a timeout: such timeout would be due to `ip_clk_en` being set incorrectly.
+ Also checked by SVA.
+
+##### OTP
+- Output `otp_init` resets low, goes high when the fast fsm is going active, and low after the `otp_done` input goes high.
+- Input `otp_done` is driven by `fast_responder`.
+ It is initialized low, and goes high some random cycles after `otp_init` goes high.
+ The sequencer will timeout if `otp_init` is not driven high.
+- Input `otp_idle` normally set high, but is set low by the `pwrmgr_aborted_low_power_vseq` sequence.
+
+###### LC
+The pins connecting to LC behave pretty much the same way as those to OTP.
+
+##### FLASH
+- Input `flash_idle` is handled much like `lc_idle` and `otp_idle`.
+
+##### CPU
+- Input `core_sleeping` is driven by sequences.
+ It is driven low to enable a transition to low power.
+ After the transition is under way it is a don't care.
+ The `pwrmgr_aborted_low_power_vseq` sequence sets it carefully to abort a low power entry soon after the attempt because the processor wakes up.
+
+##### Wakeups and Resets
+There are a number of wakeup and reset requests.
+They are driven by sequences as they need to.
+
+#### Assertions
+The [`hw/ip/pwrmgr/dv/sva/pwrmgr_bind.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/dv/sva/pwrmgr_bind.sv) module binds a few modules containing assertions to the IP as follows:
+* TLUL assertions: the `tlul_assert` [assertions](../../tlul/doc/TlulProtocolChecker.md) ensures TileLink interface protocol compliance.
+* Clock enables assertions:
+ The `pwrmgr_clock_enables_sva_if` module contains assertions checking that the various clk_en outputs correspond to the settings in the `control` CSR.
+* CLKMGR clk_en to status handshake assertions:
+ The `clkmgr_pwrmgr_sva_if` contains assertions checking the various `<clk>_status` inputs track the corresponding `<clk>_ip_clk_en` outputs.
+* AST input/output handshake assertions:
+ The `pwrmgr_ast_sva_if` module contains assertions checking that the inputs from the AST respond to the pwrmgr outputs.
+* RSTMGR input/output handshake assertions:
+ The `pwrmgr_rstmgr_sva_if` module contains assertions checking the following:
+ * The `rst_lc_src_n` input from RSTMGR respond to the `rst_lc_req` pwrmgr output.
+ * The `rst_sys_src_n` input from RSTMGR respond to the `rst_sys_req` pwrmgr output.
+ * The different `pwr_rst_o.rstreqs` output bits track the corresponding reset causes.
+ These include hardware, power glitch, escalation, and software resets.
+
+In addition, the RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
+
+## Building and running tests
+We are using our in-house developed [regression tool](../../../../util/dvsim/README.md) for building and running our tests and regressions.
+Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
+Here's how to run a smoke test:
+```console
+$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_smoke
+```
+
+## Testplan
+[Testplan](../data/pwrmgr_testplan.hjson)
diff --git a/hw/top_sencha/ip/pwrmgr/dv/cov/pwrmgr_cov_bind.sv b/hw/top_sencha/ip/pwrmgr/dv/cov/pwrmgr_cov_bind.sv
new file mode 100644
index 0000000..eba0a23
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/cov/pwrmgr_cov_bind.sv
@@ -0,0 +1,45 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Description:
+// Power manager coverage bindings for multi bus input
+module pwrmgr_cov_bind;
+
+ bind pwrmgr cip_lc_tx_cov_if u_lc_dft_en_mubi_cov_if (
+ .rst_ni (rst_ni),
+ .val (lc_dft_en_i)
+ );
+
+ bind pwrmgr cip_lc_tx_cov_if u_lc_hw_debug_en_mubi_cov_if (
+ .rst_ni (rst_ni),
+ .val (lc_hw_debug_en_i)
+ );
+
+ bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl_good_mubi_cov_if (
+ .rst_ni (rst_ni),
+ .mubi (rom_ctrl_i.done)
+ );
+
+ bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl_done_mubi_cov_if (
+ .rst_ni (rst_ni),
+ .mubi (rom_ctrl_i.good)
+ );
+
+ bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_sw_rst_req_mubi_cov_if (
+ .rst_ni (rst_ni),
+ .mubi (sw_rst_req_i)
+ );
+endmodule // pwrmgr_cov_bind
diff --git a/hw/top_sencha/ip/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el b/hw/top_sencha/ip/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el
new file mode 100644
index 0000000..dc74622
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el
@@ -0,0 +1,44 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//==================================================
+// This file contains the Excluded objects
+// Generated By User: jdonjdon
+// Format Version: 2
+// Date: Sun Sep 25 22:09:48 2022
+// ExclMode: default
+//==================================================
+CHECKSUM: "2301929872 963630968"
+INSTANCE: tb.dut.u_esc_rx.u_prim_count
+ANNOTATION: "[UNSUPPORTED] Ports are assigned constant by RTL."
+Toggle step_i "net step_i[21:0]"
+Toggle set_cnt_i "net set_cnt_i[21:0]"
+CHECKSUM: "3681358461"
+INSTANCE: tb.dut.u_esc_timeout.u_ref_timeout
+ANNOTATION: "[UNR] Input req_chk_i is tied to constant 0 and src_req_i to constant 1"
+Assert SyncReqAckHoldReq "assertion"
+CHECKSUM: "2699797328"
+INSTANCE: tb.dut.pwrmgr_ast_sva_if
+ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1"
+Assert CoreClkGlitchToEnOff_A "assertion"
+ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1"
+Assert UsbClkGlitchToValOff_A "assertion"
+ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1"
+Assert UsbClkGlitchToEnOff_A "assertion"
+ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1"
+Assert IoClkGlitchToValOff_A "assertion"
+ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1"
+Assert IoClkGlitchToEnOff_A "assertion"
+ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1"
+Assert CoreClkGlitchToValOff_A "assertion"
diff --git a/hw/top_sencha/ip/pwrmgr/dv/doc/tb.svg b/hw/top_sencha/ip/pwrmgr/dv/doc/tb.svg
new file mode 100644
index 0000000..285ef69
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/doc/tb.svg
@@ -0,0 +1 @@
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diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env.core
new file mode 100644
index 0000000..a1ae37d
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env.core
@@ -0,0 +1,53 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:dv:pwrmgr_env:0.1"
+description: "PWRMGR DV UVM environment"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:ralgen
+ - lowrisc:dv:cip_lib
+ files:
+ - pwrmgr_env_pkg.sv
+ - pwrmgr_env_cfg.sv: {is_include_file: true}
+ - pwrmgr_env_cov.sv: {is_include_file: true}
+ - pwrmgr_if.sv
+ - pwrmgr_virtual_sequencer.sv: {is_include_file: true}
+ - pwrmgr_scoreboard.sv: {is_include_file: true}
+ - pwrmgr_env.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_vseq_list.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_base_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_aborted_low_power_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_common_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_reset_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_smoke_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_stress_all_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_wakeup_reset_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_wakeup_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_sw_reset_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_global_esc_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_glitch_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_reset_invalid_vseq.sv: {is_include_file: true}
+ - seq_lib/pwrmgr_lowpower_invalid_vseq.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+generate:
+ ral:
+ generator: ralgen
+ parameters:
+ name: pwrmgr
+ ip_hjson: ../../../../../top_sencha/ip/pwrmgr/data/autogen/pwrmgr.hjson
+
+targets:
+ default:
+ filesets:
+ - files_dv
+ generate:
+ - ral
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env.sv b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env.sv
new file mode 100644
index 0000000..8135846
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env.sv
@@ -0,0 +1,74 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+class pwrmgr_env extends cip_base_env #(
+ .CFG_T (pwrmgr_env_cfg),
+ .COV_T (pwrmgr_env_cov),
+ .VIRTUAL_SEQUENCER_T(pwrmgr_virtual_sequencer),
+ .SCOREBOARD_T (pwrmgr_scoreboard)
+);
+ `uvm_component_utils(pwrmgr_env)
+
+ alert_esc_agent m_esc_agent;
+ `uvm_component_new
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ if (!uvm_config_db#(virtual clk_rst_if)::get(
+ this, "", "slow_clk_rst_vif", cfg.slow_clk_rst_vif
+ )) begin
+ `uvm_fatal(`gfn, "failed to get slow_clk_rst_vif from uvm_config_db")
+ end
+ if (!uvm_config_db#(virtual clk_rst_if)::get(
+ this, "", "esc_clk_rst_vif", cfg.esc_clk_rst_vif
+ )) begin
+ `uvm_fatal(`gfn, "failed to get esc_clk_rst_vif from uvm_config_db")
+ end
+ if (!uvm_config_db#(virtual clk_rst_if)::get(
+ this, "", "lc_clk_rst_vif", cfg.lc_clk_rst_vif
+ )) begin
+ `uvm_fatal(`gfn, "failed to get lc_clk_rst_vif from uvm_config_db")
+ end
+ if (!uvm_config_db#(virtual clk_rst_if)::get(
+ this, "", "aon_clk_rst_vif", cfg.aon_clk_rst_vif
+ )) begin
+ `uvm_fatal(`gfn, "failed to get aon_clk_rst_vif from uvm_config_db")
+ end
+ if (!uvm_config_db#(virtual pwrmgr_if)::get(this, "", "pwrmgr_vif", cfg.pwrmgr_vif)) begin
+ `uvm_fatal(`gfn, "failed to get pwrmgr_vif from uvm_config_db")
+ end
+ if (!uvm_config_db#(virtual pwrmgr_clock_enables_sva_if)::get(
+ this, "", "pwrmgr_clock_enables_sva_vif", cfg.pwrmgr_clock_enables_sva_vif
+ )) begin
+ `uvm_fatal(`gfn, "failed to get pwrmgr_clock_enables_sva_vif from uvm_config_db")
+ end
+ if (!uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::get(
+ this, "", "pwrmgr_rstmgr_sva_vif", cfg.pwrmgr_rstmgr_sva_vif
+ )) begin
+ `uvm_fatal(`gfn, "failed to get pwrmgr_rstmgr_sva_vif from uvm_config_db")
+ end
+
+ m_esc_agent = alert_esc_agent::type_id::create("m_esc_agent", this);
+ uvm_config_db#(alert_esc_agent_cfg)::set(this, "m_esc_agent", "cfg", cfg.m_esc_agent_cfg);
+ cfg.m_esc_agent_cfg.en_cov = cfg.en_cov;
+
+ endfunction
+
+ function void connect_phase(uvm_phase phase);
+ super.connect_phase(phase);
+ endfunction
+
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env_cfg.sv b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env_cfg.sv
new file mode 100644
index 0000000..4a11dfb
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env_cfg.sv
@@ -0,0 +1,66 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+class pwrmgr_env_cfg extends cip_base_env_cfg #(
+ .RAL_T(pwrmgr_reg_block)
+);
+
+ // disable fault csr read check from scoreboard
+ bit disable_csr_rd_chk = 0;
+
+ // Invalid state test. Used to disable interrupt check.
+ bit invalid_st_test = 0;
+
+ // ext component cfgs
+ alert_esc_agent_cfg m_esc_agent_cfg;
+
+ `uvm_object_utils_begin(pwrmgr_env_cfg)
+ `uvm_object_utils_end
+
+ `uvm_object_new
+
+ // ext interfaces
+ virtual clk_rst_if esc_clk_rst_vif;
+ virtual clk_rst_if lc_clk_rst_vif;
+ // same as main_clk but don't have a clk_gate
+ virtual clk_rst_if aon_clk_rst_vif;
+ virtual clk_rst_if slow_clk_rst_vif;
+ virtual pwrmgr_if pwrmgr_vif;
+ virtual pwrmgr_clock_enables_sva_if pwrmgr_clock_enables_sva_vif;
+ virtual pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_vif;
+
+ // The run_phase object, to deal with objections.
+ uvm_phase run_phase;
+
+ virtual function void initialize(bit [31:0] csr_base_addr = '1);
+ list_of_alerts = pwrmgr_env_pkg::LIST_OF_ALERTS;
+ super.initialize(csr_base_addr);
+ num_interrupts = ral.intr_state.get_n_used_bits();
+ `ASSERT_I(NumInstrMatch_A, num_interrupts == NUM_INTERRUPTS)
+ `uvm_info(`gfn, $sformatf("num_interrupts = %0d", num_interrupts), UVM_MEDIUM)
+
+ // pwrmgr_tl_intg_err test uses default alert name "fata_fault"
+ // and it requires following field to be '1'
+ tl_intg_alert_fields[ral.fault_status.reg_intg_err] = 1;
+ m_tl_agent_cfg.max_outstanding_req = 1;
+ m_esc_agent_cfg = alert_esc_agent_cfg::type_id::create("m_esc_agent_cfg");
+ `DV_CHECK_RANDOMIZE_FATAL(m_esc_agent_cfg)
+ m_esc_agent_cfg.is_alert = 0;
+ // Disable escalation ping coverage.
+ m_esc_agent_cfg.en_ping_cov = 0;
+ endfunction
+
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env_cov.sv b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env_cov.sv
new file mode 100644
index 0000000..6c6ea9d
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env_cov.sv
@@ -0,0 +1,205 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+/**
+ * Covergoups that are dependent on run-time parameters that may be available
+ * only in build_phase can be defined here.
+ * Covergroups may also be wrapped inside helper classes if needed.
+ */
+
+`include "cip_macros.svh"
+
+// Wrapper class for wakeup control covergroup.
+class pwrmgr_wakeup_ctrl_cg_wrap;
+ // This covers enable, capture, and status of wakeups.
+ covergroup wakeup_ctrl_cg(string name) with function sample (bit enable, bit capture, bit wakeup);
+ option.name = name;
+ option.per_instance = 1;
+
+ enable_cp: coverpoint enable;
+ capture_cp: coverpoint capture;
+ wakeup_cp: coverpoint wakeup;
+
+ wakeup_cross: cross enable_cp, capture_cp, wakeup_cp;
+ endgroup
+
+ function new(string name);
+ wakeup_ctrl_cg = new(name);
+ endfunction
+
+ function void sample (bit enable, bit capture, bit wakeup);
+ wakeup_ctrl_cg.sample(enable, capture, wakeup);
+ endfunction
+endclass
+
+// Wrapper class for wakeup interrupt covergroup.
+class pwrmgr_wakeup_intr_cg_wrap;
+ // This covers interrupts generated by wakeups.
+ covergroup wakeup_intr_cg(
+ string name
+ ) with function sample (
+ bit wakeup, bit enable, bit status, bit interrupt
+ );
+ option.name = name;
+ option.per_instance = 1;
+
+ enable_cp: coverpoint enable;
+ status_cp: coverpoint status;
+ wakeup_cp: coverpoint wakeup;
+ interrupt_cp: coverpoint interrupt;
+
+ interrupt_cross: cross enable_cp, status_cp, wakeup_cp, interrupt_cp{
+ // An interrupt cannot happen unless wake_status is on.
+ ignore_bins no_wakeup = interrupt_cross with (!wakeup_cp && interrupt_cp);
+ // An interrupt cannot happen unless it is enabled.
+ ignore_bins disable_pin = interrupt_cross with (!enable_cp && interrupt_cp);
+ // An interrupt cannot happen if intr_status is off.
+ ignore_bins no_status_pin = interrupt_cross with (!status_cp && interrupt_cp);
+ // If all preconditions are satisfied there must be an interrupt.
+ ignore_bins missing_int = interrupt_cross with (enable_cp && status_cp && wakeup_cp &&
+ !interrupt_cp);
+ }
+ endgroup
+
+ function new(string name);
+ wakeup_intr_cg = new(name);
+ endfunction
+
+ function void sample (bit enable, bit status, bit wakeup, bit interrupt);
+ wakeup_intr_cg.sample(wakeup, enable, status, interrupt);
+ endfunction
+endclass
+
+class pwrmgr_env_cov extends cip_base_env_cov #(
+ .CFG_T(pwrmgr_env_cfg)
+);
+ `uvm_component_utils(pwrmgr_env_cov)
+
+ // the base class provides the following handles for use:
+ // pwrmgr_env_cfg: cfg
+
+ // covergroups
+ pwrmgr_wakeup_ctrl_cg_wrap wakeup_ctrl_cg_wrap[pwrmgr_reg_pkg::NumWkups];
+ pwrmgr_wakeup_intr_cg_wrap wakeup_intr_cg_wrap[pwrmgr_reg_pkg::NumWkups];
+
+ // This collects coverage on the clock and power control functionality.
+ covergroup control_cg with function sample (control_enables_t control_enables, bit sleep);
+ core_cp: coverpoint control_enables.core_clk_en;
+ io_cp: coverpoint control_enables.io_clk_en;
+ usb_lp_cp: coverpoint control_enables.usb_clk_en_lp;
+ usb_active_cp: coverpoint control_enables.usb_clk_en_active;
+ main_pd_n_cp: coverpoint control_enables.main_pd_n;
+ sleep_cp: coverpoint sleep;
+
+ control_cross: cross core_cp, io_cp, usb_lp_cp, usb_active_cp, main_pd_n_cp, sleep_cp;
+ endgroup
+
+ covergroup hw_reset_0_cg with function sample (logic reset, logic enable, bit sleep);
+ reset_cp: coverpoint reset;
+ enable_cp: coverpoint enable;
+ sleep_cp: coverpoint sleep;
+ reset_cross: cross reset_cp, enable_cp, sleep_cp {
+ // Reset and sleep are mutually exclusive.
+ illegal_bins illegal = reset_cross with (reset_cp && sleep_cp);
+ }
+ endgroup
+
+ covergroup hw_reset_1_cg with function sample (logic reset, logic enable, bit sleep);
+ reset_cp: coverpoint reset;
+ enable_cp: coverpoint enable;
+ sleep_cp: coverpoint sleep;
+ reset_cross: cross reset_cp, enable_cp, sleep_cp {
+ // Reset and sleep are mutually exclusive.
+ illegal_bins illegal = reset_cross with (reset_cp && sleep_cp);
+ }
+ endgroup
+
+ // This reset cannot be generated in low power state since it is triggered by software.
+ covergroup rstmgr_sw_reset_cg with function sample (logic sw_reset);
+ sw_reset_cp: coverpoint sw_reset;
+ endgroup
+
+ covergroup main_power_reset_cg with function sample (logic main_power_reset, bit sleep);
+ main_power_reset_cp: coverpoint main_power_reset;
+ sleep_cp: coverpoint sleep;
+ reset_cross: cross main_power_reset_cp, sleep_cp {
+ // Any reset and sleep are mutually exclusive.
+ illegal_bins illegal = reset_cross with (main_power_reset_cp && sleep_cp);
+ }
+ endgroup
+
+ covergroup esc_reset_cg with function sample (logic esc_reset, bit sleep);
+ esc_reset_cp: coverpoint esc_reset;
+ sleep_cp: coverpoint sleep;
+ reset_cross: cross esc_reset_cp, sleep_cp {
+ // Any reset and sleep are mutually exclusive.
+ illegal_bins illegal = reset_cross with (esc_reset_cp && sleep_cp);
+ }
+ endgroup
+
+ // This measures the number of cycles between the reset and wakeup.
+ // It is positive when reset happened after wakeup, and zero when they coincided in time.
+ covergroup reset_wakeup_distance_cg with function sample (int cycles);
+ cycles_cp: coverpoint cycles {
+ bins close[] = {[-4 : 4]};
+ bins far = default;
+ }
+ endgroup
+
+ // This covers the rom inputs that should prevent entering the active state.
+ covergroup rom_active_blockers_cg with function sample (
+ logic [3:0] done, logic [3:0] good, logic [3:0] dft, logic [3:0] debug
+ );
+ done_cp: coverpoint done {
+ `DV_MUBI4_CP_BINS
+ }
+ good_cp: coverpoint good {
+ `DV_MUBI4_CP_BINS
+ }
+ dft_cp: coverpoint dft {
+ `DV_LC_TX_T_CP_BINS
+ }
+ debug_cp: coverpoint debug {
+ `DV_LC_TX_T_CP_BINS
+ }
+ blockers_cross: cross done_cp, good_cp, dft_cp, debug_cp;
+ endgroup
+
+ function new(string name, uvm_component parent);
+ super.new(name, parent);
+ foreach (wakeup_ctrl_cg_wrap[i]) begin
+ pwrmgr_env_pkg::wakeup_e wakeup = pwrmgr_env_pkg::wakeup_e'(i);
+ wakeup_ctrl_cg_wrap[i] = new({wakeup.name, "_ctrl_cg"});
+ wakeup_intr_cg_wrap[i] = new({wakeup.name, "_intr_cg"});
+ end
+ control_cg = new();
+ hw_reset_0_cg = new();
+ hw_reset_1_cg = new();
+ rstmgr_sw_reset_cg = new();
+ main_power_reset_cg = new();
+ esc_reset_cg = new();
+ reset_wakeup_distance_cg = new();
+ rom_active_blockers_cg = new();
+ endfunction : new
+
+ virtual function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ // [or instantiate covergroups here]
+ // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky
+ // See cip_base_env_cov for details
+ endfunction
+
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env_pkg.sv b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env_pkg.sv
new file mode 100644
index 0000000..9bedc45
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_env_pkg.sv
@@ -0,0 +1,101 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+package pwrmgr_env_pkg;
+ // dep packages
+ import uvm_pkg::*;
+ import top_pkg::*;
+ import dv_utils_pkg::*;
+ import dv_lib_pkg::*;
+ import tl_agent_pkg::*;
+ import cip_base_pkg::*;
+ import dv_base_reg_pkg::*;
+ import csr_utils_pkg::*;
+ import pwrmgr_ral_pkg::*;
+ import alert_esc_agent_pkg::*;
+ import pwrmgr_pkg::PowerDomains;
+ import prim_mubi_pkg::mubi4_t;
+ import prim_mubi_pkg::MuBi4False;
+ import prim_mubi_pkg::MuBi4True;
+ import prim_mubi_pkg::MuBi4Width;
+ import sec_cm_pkg::*;
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ // parameters
+ parameter int NUM_INTERRUPTS = 1;
+
+ // clk enable disable delay
+ parameter uint MAIN_CLK_DELAY_MIN = 15;
+ parameter uint MAIN_CLK_DELAY_MAX = 258;
+ parameter uint ESC_CLK_DELAY_MIN = 1;
+ parameter uint ESC_CLK_DELAY_MAX = 10;
+
+ // alerts
+ parameter uint NUM_ALERTS = 1;
+ parameter string LIST_OF_ALERTS[] = {"fatal_fault"};
+
+ // types
+ typedef enum int {
+ WakeupSysrst,
+ WakeupDbgCable,
+ WakeupPin,
+ WakeupUsb,
+ WakeupAonTimer,
+ WakeupSensorCtrl
+ } wakeup_e;
+
+ typedef enum int {
+ PwrmgrMubiNone = 0,
+ PwrmgrMubiLcCtrl = 1,
+ PwrmgrMubiRomCtrl = 2
+ } pwrmgr_mubi_e;
+
+ typedef struct packed {
+ logic main_pd_n;
+ logic usb_clk_en_active;
+ logic usb_clk_en_lp;
+ logic io_clk_en;
+ logic core_clk_en;
+ } control_enables_t;
+
+ typedef bit [pwrmgr_reg_pkg::NumWkups-1:0] wakeups_t;
+ typedef bit [pwrmgr_reg_pkg::NumRstReqs-1:0] resets_t;
+
+ // This is used to send all resets to rstmgr.
+ typedef bit [pwrmgr_pkg::HwResetWidth-1:0] resets_out_t;
+
+ // need a short name to avoid 100 line cut off
+ parameter int MUBI4W = prim_mubi_pkg::MuBi4Width;
+
+ // functions
+
+ // variables
+ bit [NUM_INTERRUPTS-1:0] exp_intr;
+ wakeups_t exp_wakeup_reasons;
+ control_enables_t control_enables;
+ logic low_power_hint;
+
+ // package sources
+ `include "pwrmgr_env_cfg.sv"
+ `include "pwrmgr_env_cov.sv"
+ `include "pwrmgr_virtual_sequencer.sv"
+ `include "pwrmgr_scoreboard.sv"
+ `include "pwrmgr_env.sv"
+ `include "pwrmgr_vseq_list.sv"
+
+endpackage
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_if.sv b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_if.sv
new file mode 100644
index 0000000..80e91dc
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_if.sv
@@ -0,0 +1,231 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// pwrmgr interface.
+//
+// Samples some internal signals to help coverage collection:
+interface pwrmgr_if (
+ input logic clk,
+ input logic rst_n,
+ input logic clk_slow,
+ input logic rst_slow_n
+);
+ import uvm_pkg::*;
+ import pwrmgr_env_pkg::*;
+
+ // Ports to the dut side.
+
+ logic rst_main_n;
+
+ pwrmgr_pkg::pwr_ast_req_t pwr_ast_req;
+ pwrmgr_pkg::pwr_ast_rsp_t pwr_ast_rsp;
+
+ pwrmgr_pkg::pwr_rst_req_t pwr_rst_req;
+ pwrmgr_pkg::pwr_rst_rsp_t pwr_rst_rsp;
+
+ pwrmgr_pkg::pwr_clk_req_t pwr_clk_req;
+ pwrmgr_pkg::pwr_clk_rsp_t pwr_clk_rsp;
+
+ pwrmgr_pkg::pwr_otp_req_t pwr_otp_req;
+ pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_rsp;
+
+ pwrmgr_pkg::pwr_lc_req_t pwr_lc_req;
+ pwrmgr_pkg::pwr_lc_rsp_t pwr_lc_rsp;
+
+ pwrmgr_pkg::pwr_flash_t pwr_flash;
+
+ pwrmgr_pkg::pwrmgr_cpu_t cpu_i;
+ pwrmgr_pkg::pwr_cpu_t pwr_cpu;
+
+ lc_ctrl_pkg::lc_tx_t fetch_en;
+ lc_ctrl_pkg::lc_tx_t lc_hw_debug_en;
+ lc_ctrl_pkg::lc_tx_t lc_dft_en;
+
+ logic [ pwrmgr_reg_pkg::NumWkups-1:0] wakeups_i;
+ logic [pwrmgr_reg_pkg::NumRstReqs-1:0] rstreqs_i;
+
+ logic strap;
+ logic low_power;
+ rom_ctrl_pkg::pwrmgr_data_t rom_ctrl;
+
+ prim_mubi_pkg::mubi4_t sw_rst_req_i;
+
+ logic intr_wakeup;
+
+ // Relevant CSR values.
+ logic wakeup_en_regwen;
+ logic [ pwrmgr_reg_pkg::NumWkups-1:0] wakeup_en;
+ logic [ pwrmgr_reg_pkg::NumWkups-1:0] wakeup_status;
+ logic wakeup_capture_en;
+
+ logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_en;
+ logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_en_q;
+ logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_status;
+
+ logic lowpwr_cfg_wen;
+ pwrmgr_reg_pkg::pwrmgr_hw2reg_wake_info_reg_t wake_info;
+
+ // Internal DUT signals.
+`ifndef PATH_TO_DUT
+ `define PATH_TO_DUT tb.dut
+`endif
+
+ // Slow fsm state.
+ pwrmgr_pkg::slow_pwr_state_e slow_state;
+ always_comb slow_state = `PATH_TO_DUT.u_slow_fsm.state_q;
+
+ // Fast fsm state.
+ pwrmgr_pkg::fast_pwr_state_e fast_state;
+ always_comb fast_state = `PATH_TO_DUT.u_fsm.state_q;
+
+ // cfg regwen
+ always_comb lowpwr_cfg_wen = `PATH_TO_DUT.lowpwr_cfg_wen;
+
+ // reset status
+ always_comb reset_status = {`PATH_TO_DUT.u_reg.reset_status_val_1_qs,
+ `PATH_TO_DUT.u_reg.reset_status_val_0_qs};
+ always_comb reset_en_q = {`PATH_TO_DUT.u_reg.reset_en_en_1_qs,
+ `PATH_TO_DUT.u_reg.reset_en_en_0_qs};
+ always_comb
+ wakeup_en = {
+ `PATH_TO_DUT.reg2hw.wakeup_en[5].q,
+ `PATH_TO_DUT.reg2hw.wakeup_en[4].q,
+ `PATH_TO_DUT.reg2hw.wakeup_en[3].q,
+ `PATH_TO_DUT.reg2hw.wakeup_en[2].q,
+ `PATH_TO_DUT.reg2hw.wakeup_en[1].q,
+ `PATH_TO_DUT.reg2hw.wakeup_en[0].q
+ };
+
+ // Wakeup_status ro CSR.
+ always_comb
+ wakeup_status = {
+ `PATH_TO_DUT.hw2reg.wake_status[5].d,
+ `PATH_TO_DUT.hw2reg.wake_status[4].d,
+ `PATH_TO_DUT.hw2reg.wake_status[3].d,
+ `PATH_TO_DUT.hw2reg.wake_status[2].d,
+ `PATH_TO_DUT.hw2reg.wake_status[1].d,
+ `PATH_TO_DUT.hw2reg.wake_status[0].d
+ };
+
+ always_comb wakeup_capture_en = !`PATH_TO_DUT.u_reg.wake_info_capture_dis_qs;
+ always_comb wake_info = `PATH_TO_DUT.i_wake_info.info_o;
+
+ logic intr_enable;
+ always_comb intr_enable = `PATH_TO_DUT.reg2hw.intr_enable.q;
+
+ logic intr_status;
+ always_comb intr_status = `PATH_TO_DUT.reg2hw.intr_state.q;
+
+ // This is only used to determine if an interrupt will be set in case of a reset while in
+ // low power. tryIt is very hard to perdict if the reset or a wakeup happen first, so this
+ // signal is used to help instead.
+ pwrmgr_pkg::pwrup_cause_e pwrup_cause;
+ always_comb pwrup_cause = `PATH_TO_DUT.slow_pwrup_cause;
+
+ // Used to disable assertions once with the first power glitch.
+ bit internal_assertion_disabled;
+
+ function automatic void update_ast_main_pok(logic value);
+ pwr_ast_rsp.main_pok = value;
+ endfunction
+
+ function automatic void update_otp_done(logic value);
+ pwr_otp_rsp.otp_done = value;
+ endfunction
+
+ function automatic void update_otp_idle(logic value);
+ pwr_otp_rsp.otp_idle = value;
+ endfunction
+
+ function automatic void update_lc_done(logic value);
+ pwr_lc_rsp.lc_done = value;
+ endfunction
+
+ function automatic void update_lc_idle(logic value);
+ pwr_lc_rsp.lc_idle = value;
+ endfunction
+
+ function automatic void update_flash_idle(logic value);
+ pwr_flash.flash_idle = value;
+ endfunction
+
+ function automatic void update_cpu_sleeping(logic value);
+ pwr_cpu.core_sleeping = value;
+ endfunction
+
+ function automatic void update_wakeups(logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups);
+ wakeups_i = wakeups;
+ endfunction
+
+ function automatic void update_resets(logic [pwrmgr_reg_pkg::NumRstReqs-1:0] resets);
+ rstreqs_i = resets;
+ endfunction
+
+ function automatic void update_reset_en(
+ logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_en_value);
+ reset_en = reset_en_value;
+ endfunction
+
+ function automatic void update_sw_rst_req(prim_mubi_pkg::mubi4_t value);
+ sw_rst_req_i = value;
+ endfunction
+
+ // Sends a main power glitch and disables a design assertion that trips for power glitches.
+ task automatic glitch_power_reset();
+ rst_main_n = 1'b0;
+ if (!internal_assertion_disabled) begin
+ internal_assertion_disabled = 1'b1;
+ `uvm_info("pwrmgr_if", "disabling power glitch related SVA", UVM_MEDIUM)
+ $assertoff(1, dut.u_slow_fsm.IntRstReq_A);
+ end
+ repeat (2) @(posedge clk_slow);
+ rst_main_n = 1'b1;
+ endtask
+
+ // FIXME Move all these initializations to sequences.
+ initial begin
+ // From AST.
+ pwr_ast_rsp = '{default: '0};
+ pwr_rst_rsp = '{default: '0};
+ pwr_clk_rsp = '{default: '0};
+ pwr_otp_rsp = '{default: '0};
+ pwr_lc_rsp = '{default: '0};
+ pwr_flash = '{default: '0};
+ pwr_cpu = pwrmgr_pkg::PWR_CPU_DEFAULT;
+ wakeups_i = pwrmgr_pkg::WAKEUPS_DEFAULT;
+ rstreqs_i = pwrmgr_pkg::RSTREQS_DEFAULT;
+ sw_rst_req_i = prim_mubi_pkg::MuBi4False;
+ rom_ctrl = rom_ctrl_pkg::PWRMGR_DATA_DEFAULT;
+ end
+
+ clocking slow_cb @(posedge clk_slow);
+ input slow_state;
+ input pwr_ast_req;
+ output pwr_ast_rsp;
+ endclocking
+
+ clocking fast_cb @(posedge clk);
+ input fast_state;
+ input pwr_rst_req;
+ output pwr_rst_rsp;
+ input pwr_clk_req;
+ output pwr_clk_rsp;
+ input pwr_lc_req;
+ output pwr_lc_rsp;
+ input pwr_otp_req;
+ output pwr_otp_rsp;
+ endclocking
+endinterface
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_scoreboard.sv b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_scoreboard.sv
new file mode 100644
index 0000000..5d58a40
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_scoreboard.sv
@@ -0,0 +1,352 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+class pwrmgr_scoreboard extends cip_base_scoreboard #(
+ .CFG_T(pwrmgr_env_cfg),
+ .RAL_T(pwrmgr_reg_block),
+ .COV_T(pwrmgr_env_cov)
+);
+ `uvm_component_utils(pwrmgr_scoreboard)
+
+ // local variables
+
+ // TLM agent fifos
+
+ // local queues to hold incoming packets pending comparison
+
+ `uvm_component_new
+
+ function void build_phase(uvm_phase phase);
+ string common_seq_type;
+ super.build_phase(phase);
+
+ void'($value$plusargs("run_%0s", common_seq_type));
+ if (common_seq_type == "stress_all_with_rand_reset") do_alert_check = 0;
+ endfunction
+
+ task run_phase(uvm_phase phase);
+ super.run_phase(phase);
+ cfg.run_phase = phase;
+ fork
+ monitor_power_glitch();
+ monitor_escalation_timeout();
+ reset_cip_helper();
+ wakeup_ctrl_coverage_collector();
+ wakeup_intr_coverage_collector();
+ low_power_coverage_collector();
+ reset_coverage_collector();
+ rom_coverage_collector();
+ join_none
+ endtask
+
+ task monitor_power_glitch();
+ fork
+ forever
+ @cfg.pwrmgr_vif.rst_main_n begin
+ if (cfg.pwrmgr_vif.rst_main_n == 1'b0 && `gmv(ral.control.main_pd_n)) begin
+ set_exp_alert("fatal_fault", 1, 500);
+ end
+ end
+ join
+ endtask
+
+ // An escalation timeout is triggered in test sequences by stopping clk_esc_i or by driving
+ // rst_esc_ni active when the dut state is not expecting it.
+ task monitor_escalation_timeout();
+ fork
+ forever
+ @(posedge cfg.esc_clk_rst_vif.clk_gate) begin
+ if (cfg.pwrmgr_vif.pwr_ast_req.io_clk_en && cfg.pwrmgr_vif.pwr_clk_req.io_ip_clk_en) begin
+ `uvm_info(`gfn, "Detected unexpected clk_esc_i stop", UVM_MEDIUM)
+ set_exp_alert("fatal_fault", 1, 500);
+ end
+ end
+ forever
+ @(negedge cfg.esc_clk_rst_vif.o_rst_n) begin
+ if (cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On) begin
+ `uvm_info(`gfn, "Detected unexpected rst_esc_ni active", UVM_MEDIUM)
+ set_exp_alert("fatal_fault", 1, 500);
+ end
+ end
+ join
+ endtask
+
+ // We need to reset the cip scoreboard, since the alert handler responds
+ // to lc domain0 resets, yet the pwrmgr's clk_rst_vif is aon. So when a
+ // reset happens the cip scoreboard needs to be informed, both when reset
+ // starts and when it ends.
+ task reset_cip_helper();
+ fork
+ forever
+ @cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req begin
+ if (|cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req) begin
+ // Start of d0 reset request.
+ `uvm_info(`gfn, "pwrmgr start reset in reset_cip_helper", UVM_MEDIUM)
+ cfg.under_reset = 1;
+ end
+ end
+ forever
+ @cfg.pwrmgr_vif.fetch_en begin
+ if (cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On) begin
+ // End of d0 reset request.
+ `uvm_info(`gfn, "pwrmgr end reset in reset_cip_helper", UVM_MEDIUM)
+ reset_alert_state();
+ end
+ end
+ join
+ endtask
+
+ task wakeup_ctrl_coverage_collector();
+ forever
+ @(posedge (|cfg.pwrmgr_vif.wakeups_i)) begin
+ if (cfg.en_cov) begin
+ // Allow for synchronization delay.
+ cfg.slow_clk_rst_vif.wait_clks(2);
+ foreach (cov.wakeup_ctrl_cg_wrap[i]) begin
+ cov.wakeup_ctrl_cg_wrap[i].sample(cfg.pwrmgr_vif.wakeup_en[i],
+ cfg.pwrmgr_vif.wakeup_capture_en,
+ cfg.pwrmgr_vif.wakeups_i[i]);
+ end
+ end
+ end
+ endtask
+
+ task wakeup_intr_coverage_collector();
+ forever
+ @(posedge (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone)) begin
+ if (cfg.en_cov) begin
+ foreach (cov.wakeup_intr_cg_wrap[i]) begin
+ cov.wakeup_intr_cg_wrap[i].sample(
+ cfg.pwrmgr_vif.wakeup_status[i], cfg.pwrmgr_vif.intr_enable,
+ cfg.pwrmgr_vif.intr_status, cfg.pwrmgr_vif.intr_wakeup);
+ end
+ end
+ end
+ endtask
+
+ task low_power_coverage_collector();
+ forever
+ @(posedge cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::LowPwrEntry) begin
+ if (cfg.en_cov) begin
+ // At this point pwrmgr is asleep.
+ cov.control_cg.sample(control_enables, 1'b1);
+ end
+ end
+ endtask
+
+ local task sample_reset_coverage(bit sleep);
+ cov.hw_reset_0_cg.sample(cfg.pwrmgr_vif.rstreqs_i[0], cfg.pwrmgr_vif.reset_en[0], sleep);
+ cov.hw_reset_1_cg.sample(cfg.pwrmgr_vif.rstreqs_i[1], cfg.pwrmgr_vif.reset_en[1], sleep);
+ cov.rstmgr_sw_reset_cg.sample(cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True);
+ cov.main_power_reset_cg.sample(
+ cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx], sleep);
+ cov.esc_reset_cg.sample(cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx], sleep);
+ `uvm_info(`gfn, $sformatf(
+ {
+ "reset_cg sample with hw_resets=%b, hw_resets_en=%b, ",
+ "esc_rst=%b, main_pwr_rst=%b, sw_rst=%b, sleep=%b"
+ },
+ cfg.pwrmgr_vif.rstreqs_i,
+ cfg.pwrmgr_vif.reset_en,
+ cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx],
+ cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx],
+ cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True,
+ sleep
+ ), UVM_MEDIUM)
+ endtask
+
+ task reset_coverage_collector();
+ fork
+ forever
+ @(posedge cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::HwReq) begin
+ if (cfg.en_cov) begin
+ sample_reset_coverage(.sleep(1'b0));
+ end
+ end
+ forever
+ @(posedge cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateLowPower) begin
+ if (cfg.en_cov) begin
+ sample_reset_coverage(.sleep(1'b1));
+ end
+ end
+ join_none
+ endtask
+
+ task rom_coverage_collector();
+ forever
+ @(cfg.pwrmgr_vif.rom_ctrl or cfg.pwrmgr_vif.lc_hw_debug_en or cfg.pwrmgr_vif.lc_dft_en) begin
+ if (cfg.en_cov) begin
+ cov.rom_active_blockers_cg.sample(cfg.pwrmgr_vif.rom_ctrl.done,
+ cfg.pwrmgr_vif.rom_ctrl.good, cfg.pwrmgr_vif.lc_dft_en,
+ cfg.pwrmgr_vif.lc_hw_debug_en);
+ end
+ end
+ endtask
+
+ virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name);
+ uvm_reg csr;
+ bit do_read_check = ~(cfg.disable_csr_rd_chk);
+ bit skip_intr_chk = cfg.invalid_st_test;
+ bit write = item.is_write();
+ uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr);
+
+ bit addr_phase_read = (!write && channel == AddrChannel);
+ bit addr_phase_write = (write && channel == AddrChannel);
+ bit data_phase_read = (!write && channel == DataChannel);
+ bit data_phase_write = (write && channel == DataChannel);
+
+ // if access was to a valid csr, get the csr handle
+ if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin
+ csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr);
+ `DV_CHECK_NE_FATAL(csr, null)
+ end else begin
+ `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr))
+ end
+
+ // if incoming access is a write to a valid csr, then make updates right away
+ if (addr_phase_write) begin
+ `uvm_info(`gfn, $sformatf("Writing 0x%x to %s", item.a_data, csr.get_full_name()), UVM_MEDIUM)
+ void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask)));
+ end
+
+ // process the csr req
+ // for write, update local variable and fifo at address phase
+ // for read, update predication at address phase and compare at data phase
+ // TODO handle more read checks.
+ case (csr.get_name())
+ // add individual case item for each csr
+ "intr_state": begin
+ if (skip_intr_chk) return;
+ if (data_phase_write) begin
+ exp_intr &= ~item.a_data;
+ end else if (data_phase_read) begin
+ bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value();
+ foreach (exp_intr[i]) begin
+ if (cfg.en_cov) begin
+ cov.intr_cg.sample(i, intr_en[i], exp_intr[i]);
+ cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]);
+ end
+ `DV_CHECK_EQ(item.d_data[i], exp_intr[i], $sformatf("Interrupt bit %0d", i));
+ `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[i], (intr_en[i] & exp_intr[i]), $sformatf(
+ "Interrupt_pin bit %0d", i));
+ end
+ end
+ // rw1c: write 1 clears, write 0 is no-op.
+ do_read_check = 1'b0;
+ end
+ "intr_enable", "alert_test": begin
+ // Do nothing
+ end
+ "intr_test": begin
+ if (data_phase_write) begin
+ bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value();
+ exp_intr |= item.a_data;
+ if (cfg.en_cov) begin
+ foreach (exp_intr[i]) begin
+ cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], exp_intr[i]);
+ end
+ end
+ end
+ // Write-only, so it can't be read.
+ do_read_check = 1'b0;
+ end
+ "ctrl_cfg_regwen": begin
+ // Read-only. Hardware clears this bit when going to low power mode,
+ // and sets it in active mode.
+ do_read_check = 1'b0;
+ end
+ "control": begin
+ // Only some bits can be checked on reads. Bit 0 is cleared by hardware
+ // on low power transition or when registering a valid reset.
+ if (data_phase_write) begin
+ low_power_hint = get_field_val(ral.control.low_power_hint, item.a_data);
+ control_enables = '{
+ core_clk_en: get_field_val(ral.control.core_clk_en, item.a_data),
+ io_clk_en: get_field_val(ral.control.io_clk_en, item.a_data),
+ usb_clk_en_lp: get_field_val(ral.control.usb_clk_en_lp, item.a_data),
+ usb_clk_en_active: get_field_val(ral.control.usb_clk_en_active, item.a_data),
+ main_pd_n: get_field_val(ral.control.main_pd_n, item.a_data)
+ };
+ `uvm_info(`gfn, $sformatf("Writing low power hint=%b", low_power_hint), UVM_MEDIUM)
+ `uvm_info(`gfn, $sformatf("Writing control_enables=%p", control_enables), UVM_MEDIUM)
+ if (cfg.en_cov) begin
+ // At this point the processor is not asleep.
+ cov.control_cg.sample(control_enables, 1'b0);
+ end
+ end
+ end
+ "cfg_cdc_sync": begin
+ // rw1c: When written to 1 this bit self-clears when the slow clock domain
+ // syncs.
+ do_read_check = 1'b0;
+ end
+ "wakeup_en_regwen": begin
+ end
+ "wakeup_en": begin
+ end
+ "wake_status": begin
+ // Read-only.
+ do_read_check = 1'b0;
+ end
+ "reset_en_regwen": begin
+ // rw0c, so writing a 1 is a no-op.
+ end
+ "reset_en": begin
+ if (data_phase_write) begin
+ cfg.pwrmgr_vif.update_reset_en(item.a_data);
+ end
+ end
+ "reset_status": begin
+ // Read-only.
+ do_read_check = 1'b0;
+ end
+ "escalate_reset_status": begin
+ // Read-only.
+ do_read_check = 1'b0;
+ end
+ "wake_info_capture_dis": begin
+ end
+ "wake_info": begin
+ // rw1c: write 1 clears, write 0 is no-op.
+ do_read_check = 1'b0;
+ end
+ default: begin
+ `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name()))
+ end
+ endcase
+
+ // On reads, if do_read_check, is set, then check mirrored_value against item.d_data
+ if (data_phase_read) begin
+ `uvm_info(`gfn, $sformatf("Reading 0x%x from %s", item.d_data, csr.get_full_name()), UVM_LOW)
+ if (do_read_check) begin
+ `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, $sformatf(
+ "reg name: %0s", csr.get_full_name()))
+ end
+ void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ)));
+ end
+ endtask
+
+ virtual function void reset(string kind = "HARD");
+ super.reset(kind);
+ // reset local fifos queues and variables
+ endfunction
+
+ function void check_phase(uvm_phase phase);
+ super.check_phase(phase);
+ // post test checks - ensure that all local fifos and queues are empty
+ endfunction
+
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv
new file mode 100644
index 0000000..5e8d77a
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv
@@ -0,0 +1,26 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+class pwrmgr_virtual_sequencer extends cip_base_virtual_sequencer #(
+ .CFG_T(pwrmgr_env_cfg),
+ .COV_T(pwrmgr_env_cov)
+);
+ `uvm_component_utils(pwrmgr_virtual_sequencer)
+
+
+ `uvm_component_new
+
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv
new file mode 100644
index 0000000..7edc685
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv
@@ -0,0 +1,136 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// The aborted low power test causes low power transitions to abort for CPU interrupts and nvms not
+// idle. It randomly enables wakeups, info capture, and interrupts, and sends wakeups at random
+// times, and causes a test failure if they are not aborted.
+class pwrmgr_aborted_low_power_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_aborted_low_power_vseq)
+
+ `uvm_object_new
+
+ // If set causes an abort because the CPU gets an interrupt, which shows up as
+ // pwr_cpu.core_sleeping being low when the fast FSM is in FastPwrStateFallThrough.
+ rand bit cpu_interrupt;
+
+ constraint cpu_interrupt_c {
+ cpu_interrupt dist {
+ 1 := 2,
+ 0 := 6
+ };
+ }
+
+ rand bit flash_idle;
+ rand bit lc_idle;
+ rand bit otp_idle;
+
+ constraint idle_c {
+ solve cpu_interrupt before flash_idle, lc_idle, otp_idle;
+ if (!cpu_interrupt) {(flash_idle && lc_idle && otp_idle) == 1'b0;}
+ }
+
+ constraint wakeups_c {wakeups != 0;}
+
+ constraint wakeup_en_c {
+ solve wakeups before wakeups_en;
+ |(wakeups_en & wakeups) == 1'b1;
+ }
+
+ // Make sure wakeup capture is enabled to check the abort happened.
+ constraint enable_wakeup_capture_c {disable_wakeup_capture == 1'b0;}
+
+ task body();
+ logic [TL_DW-1:0] value;
+ wakeups_t enabled_wakeups;
+ wait_for_fast_fsm_active();
+
+ check_wake_status('0);
+ set_nvms_idle();
+ for (int i = 0; i < num_trans; ++i) begin
+ `uvm_info(`gfn, "Starting new round", UVM_MEDIUM)
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ setup_interrupt(.enable(en_intr));
+ // Enable wakeups.
+ enabled_wakeups = wakeups_en & wakeups;
+ `DV_CHECK(enabled_wakeups, $sformatf(
+ "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en))
+ `uvm_info(`gfn, $sformatf(
+ "Enabled wakeups=0x%x (wkups=%x wkup_en=%x)", enabled_wakeups, wakeups, wakeups_en
+ ), UVM_MEDIUM)
+ csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en));
+ `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"),
+ UVM_MEDIUM)
+ csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture));
+ low_power_hint = 1'b1;
+
+ // Put CPU to sleep even before the control registers are fully written to avoid
+ // unexpected failures to abort due to delicate timing.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b1);
+
+ fork
+ begin
+ update_control_csr();
+ `uvm_info(`gfn, $sformatf("After update_control_csr exp_intr=%b", exp_intr), UVM_MEDIUM)
+ end
+ begin
+ // Prepare for an abort ahead of time.
+ `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive)
+ // Wait one more cycle for update_control_csr called above to predict the interrupt
+ // based on the value of cpu_sleeping right after the transition out of active state.
+ // There is enough time for this since it takes time to disable the clocks.
+ cfg.clk_rst_vif.wait_clks(1);
+ if (cpu_interrupt) begin
+ `uvm_info(`gfn, "Expecting a fall through (0x40)", UVM_MEDIUM)
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b0);
+ end else begin
+ `uvm_info(`gfn, $sformatf(
+ "Expecting an abort (0x80): fi=%b, li=%b, oi=%b",
+ flash_idle,
+ lc_idle,
+ otp_idle
+ ), UVM_MEDIUM)
+ set_nvms_idle(flash_idle, lc_idle, otp_idle);
+ end
+ end
+ join
+ wait_for_fast_fsm_active();
+
+ `uvm_info(`gfn, "Back from sleep attempt", UVM_MEDIUM)
+ @cfg.clk_rst_vif.cb;
+
+ // No wakeups, but check abort and fall_through.
+ fork
+ begin
+ fast_check_reset_status(0);
+ end
+ begin
+ fast_check_wake_info(.reasons('0), .fall_through(cpu_interrupt), .abort(~cpu_interrupt));
+ end
+ join
+
+ clear_wake_info();
+
+ // And check interrupt is set.
+ check_and_clear_interrupt(.expected(1'b1));
+
+ // Get ready for another round.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b0);
+ set_nvms_idle();
+ end
+ `uvm_info(`gfn, "Test done", UVM_MEDIUM)
+ endtask
+
+endclass : pwrmgr_aborted_low_power_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv
new file mode 100644
index 0000000..b35ee58
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv
@@ -0,0 +1,826 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+class pwrmgr_base_vseq extends cip_base_vseq #(
+ .RAL_T (pwrmgr_reg_block),
+ .CFG_T (pwrmgr_env_cfg),
+ .COV_T (pwrmgr_env_cov),
+ .VIRTUAL_SEQUENCER_T(pwrmgr_virtual_sequencer)
+);
+ `uvm_object_utils(pwrmgr_base_vseq)
+
+ `uvm_object_new
+
+ localparam int ActiveTimeoutInNanoSeconds = 10_000;
+ localparam int PropagationToSlowTimeoutInNanoSeconds = 15_000;
+ localparam int FetchEnTimeoutNs = 40_000;
+
+ localparam int MaxCyclesBeforeEnable = 12;
+
+ // Random wakeups and resets.
+ rand wakeups_t wakeups;
+ rand wakeups_t wakeups_en;
+ rand resets_t resets;
+ rand resets_t resets_en;
+ rand bit power_glitch_reset;
+ rand bit escalation_reset;
+ rand bit ndm_reset;
+
+ rand bit en_intr;
+
+ constraint resets_en_c {
+ solve resets, power_glitch_reset, escalation_reset, ndm_reset before resets_en;
+ |{resets_en & resets, power_glitch_reset, escalation_reset, ndm_reset} == 1'b1;
+ }
+
+ rand bit disable_wakeup_capture;
+
+ // Random control enables.
+ rand control_enables_t control_enables;
+
+ // Random delays.
+ rand int cycles_before_clks_ok;
+ rand int cycles_between_clks_ok;
+ rand int cycles_before_io_status;
+ rand int cycles_before_main_status;
+ rand int cycles_before_usb_status;
+ rand int cycles_before_rst_lc_src;
+ rand int cycles_before_rst_sys_src;
+ rand int cycles_before_otp_done;
+ rand int cycles_before_lc_done;
+ rand int cycles_before_wakeup;
+ rand int cycles_before_reset;
+
+ // Slow responder delays.
+ rand int cycles_before_core_clk_en;
+ rand int cycles_before_io_clk_en;
+ rand int cycles_before_usb_clk_en;
+ rand int cycles_before_main_pok;
+
+ // This tracks the local objection count from these responders. We do not use UVM
+ // objections because uvm_objection::wait_for(UVM_ALL_DROPPED, this) seems to wait
+ // for all objections to be dropped, not just those raised by this.
+ local int fast_objection_count = 0;
+ local int slow_objection_count = 0;
+
+ constraint cycles_before_clks_ok_c {cycles_before_clks_ok inside {[3 : 10]};}
+ constraint cycles_between_clks_ok_c {cycles_between_clks_ok inside {[3 : 10]};}
+ constraint cycles_before_io_status_c {cycles_before_io_status inside {[0 : 4]};}
+ constraint cycles_before_main_status_c {cycles_before_main_status inside {[0 : 4]};}
+ constraint cycles_before_usb_status_c {cycles_before_usb_status inside {[0 : 4]};}
+ constraint cycles_before_rst_lc_src_base_c {cycles_before_rst_lc_src inside {[0 : 4]};}
+ constraint cycles_before_rst_sys_src_base_c {cycles_before_rst_sys_src inside {[0 : 4]};}
+ constraint cycles_before_otp_done_base_c {cycles_before_otp_done inside {[0 : 4]};}
+ constraint cycles_before_lc_done_base_c {cycles_before_lc_done inside {[0 : 4]};}
+ constraint cycles_before_wakeup_c {cycles_before_wakeup inside {[2 : 6]};}
+ constraint cycles_before_reset_c {cycles_before_reset inside {[2 : 6]};}
+ constraint cycles_before_core_clk_en_c {
+ cycles_before_core_clk_en inside {[1 : MaxCyclesBeforeEnable]};
+ }
+ constraint cycles_before_io_clk_en_c {
+ cycles_before_io_clk_en inside {[1 : MaxCyclesBeforeEnable - 2]};
+ }
+ constraint cycles_before_usb_clk_en_c {
+ cycles_before_usb_clk_en inside {[1 : MaxCyclesBeforeEnable]};
+ }
+ constraint cycles_before_main_pok_c {cycles_before_main_pok inside {[2 : MaxCyclesBeforeEnable]};}
+
+ // This is used to trigger a software reset, as per rstmgr's `reset_req` CSR.
+ prim_mubi_pkg::mubi4_t sw_rst_from_rstmgr = prim_mubi_pkg::MuBi4False;
+
+ bit do_pwrmgr_init = 1'b1;
+ // This static variable is incremented in each pre_start and decremented in each post_start.
+ // It is used to start and stop the responders when the parent sequence starts and ends.
+ local static int sequence_depth = 0;
+ pwrmgr_mubi_e mubi_mode;
+
+ // This stops randomizing cycles counts that select from a pipeline, since
+ // changes can lead to missing or unexpected transitions.
+ task stop_randomizing_cycles();
+ cycles_before_core_clk_en.rand_mode(0);
+ cycles_before_io_clk_en.rand_mode(0);
+ cycles_before_usb_clk_en.rand_mode(0);
+ cycles_before_main_pok.rand_mode(0);
+ endtask
+
+ // Disable exclusions for CONTROL.USB_CLK_EN_ACTIVE and RESET_EN: they are meant for full-chip only.
+ function void disable_unnecessary_exclusions();
+ csr_excl_item csr_excl = ral.get_excl_item();
+ `uvm_info(`gfn, "Dealing with exclusions", UVM_MEDIUM)
+ csr_excl.enable_excl(.obj("pwrmgr_reg_block.control"), .enable(1'b0));
+ csr_excl.enable_excl(.obj("pwrmgr_reg_block.reset_en"), .enable(1'b0));
+ csr_excl.print_exclusions(UVM_MEDIUM);
+ endfunction
+
+ virtual task pre_start();
+ cfg.pwrmgr_vif.lc_hw_debug_en = lc_ctrl_pkg::Off;
+ cfg.pwrmgr_vif.lc_dft_en = lc_ctrl_pkg::Off;
+ mubi_mode = PwrmgrMubiNone;
+ `DV_GET_ENUM_PLUSARG(pwrmgr_mubi_e, mubi_mode, pwrmgr_mubi_mode)
+ `uvm_info(`gfn, $sformatf("pwrmgr mubi mode : %s", mubi_mode.name()), UVM_MEDIUM)
+
+ if (do_pwrmgr_init) pwrmgr_init();
+ disable_unnecessary_exclusions();
+ cfg.slow_clk_rst_vif.wait_for_reset(.wait_negedge(0));
+ stop_randomizing_cycles();
+ fork
+ // Deactivate rst_main_n to make sure the slow fsm won't be confused into thinking
+ // a power glitch occurred, and wait some cycles so testing doesn't start until any
+ // side-effects are cleared. This confusion can arise if a sequence with random resets
+ // gets reset while sending a power glitch.
+ begin
+ cfg.pwrmgr_vif.rst_main_n = 1'b1;
+ cfg.slow_clk_rst_vif.wait_clks(7);
+ end
+ begin
+ if (sequence_depth == 0) begin
+ `uvm_info(`gfn, "Starting responders", UVM_MEDIUM)
+ slow_responder();
+ fast_responder();
+ end
+ ++sequence_depth;
+ super.pre_start();
+ end
+ join
+ endtask : pre_start
+
+ task post_apply_reset(string reset_kind = "HARD");
+ super.post_apply_reset(reset_kind);
+ if (reset_kind == "HARD") begin
+ // Undo any pending resets.
+ cfg.pwrmgr_vif.rst_main_n = 1'b1;
+ cfg.pwrmgr_vif.update_resets(0);
+ end
+
+ `uvm_info(`gfn, "waiting for fast active after applying reset", UVM_MEDIUM)
+
+ // There is tb lock up case
+ // when reset come while rom_ctrl = {false, false}.
+ // So we need rom_ctrl driver runs in parallel with
+ // wait_for_fast_fsm_active
+ fork
+ wait_for_fast_fsm_active();
+ init_rom_response();
+ join
+ // And drive the cpu not sleeping.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b0);
+ endtask
+
+ task post_start();
+ super.post_start();
+ --sequence_depth;
+ if (sequence_depth == 0) begin
+ `uvm_info(`gfn, $sformatf(
+ "Waiting for all objections done with fast=%0d, slow=%0d",
+ fast_objection_count,
+ slow_objection_count
+ ), UVM_MEDIUM)
+ `DV_WAIT(fast_objection_count == 0 && slow_objection_count == 0)
+ `uvm_info(`gfn, "all local objections are done", UVM_LOW)
+ control_assertions(0);
+ `uvm_info(`gfn, "Stopping responders", UVM_MEDIUM)
+ disable slow_responder;
+ disable fast_responder;
+ end
+ endtask
+
+ virtual task dut_init(string reset_kind = "HARD");
+ super.dut_init();
+ endtask
+
+ virtual task dut_shutdown();
+ // check for pending pwrmgr operations and wait for them to complete
+ // TODO
+ endtask
+
+ virtual task apply_reset(string kind = "HARD");
+ `uvm_info(`gfn, $sformatf("At apply_reset kind='%0s'", kind), UVM_MEDIUM)
+ fork
+ super.apply_reset(kind);
+ if (kind == "HARD") begin
+ // A short slow clock reset should suffice.
+ cfg.slow_clk_rst_vif.apply_reset(.pre_reset_dly_clks(0), .reset_width_clks(5));
+ end
+ cfg.esc_clk_rst_vif.apply_reset();
+ cfg.lc_clk_rst_vif.apply_reset();
+ // Escalation resets are cleared when reset goes active.
+ clear_escalation_reset();
+ clear_ndm_reset();
+ cfg.aon_clk_rst_vif.apply_reset();
+ join
+ // And wait until the responders settle with all okay from the AST.
+ `DV_WAIT(
+ cfg.pwrmgr_vif.pwr_ast_rsp.main_pok &&
+ cfg.pwrmgr_vif.pwr_ast_rsp.core_clk_val &&
+ cfg.pwrmgr_vif.pwr_ast_rsp.io_clk_val)
+ `uvm_info(`gfn, $sformatf("Out of apply_reset kind='%0s'", kind), UVM_MEDIUM)
+ endtask
+
+ virtual task apply_resets_concurrently(int reset_duration_ps = 0);
+ cfg.slow_clk_rst_vif.drive_rst_pin(0);
+ cfg.esc_clk_rst_vif.drive_rst_pin(0);
+ cfg.lc_clk_rst_vif.drive_rst_pin(0);
+ cfg.aon_clk_rst_vif.drive_rst_pin(0);
+ super.apply_resets_concurrently(cfg.slow_clk_rst_vif.clk_period_ps);
+ cfg.aon_clk_rst_vif.drive_rst_pin(1);
+ cfg.esc_clk_rst_vif.drive_rst_pin(1);
+ cfg.lc_clk_rst_vif.drive_rst_pin(1);
+ cfg.slow_clk_rst_vif.drive_rst_pin(1);
+ endtask
+
+ // setup basic pwrmgr features
+ virtual task pwrmgr_init();
+ // The fast clock frequency is set by ral.
+ // The real slow clock rate is 200kHz, but that slows testing down.
+ // Increasing its frequency improves DV efficiency without compromising quality.
+ cfg.slow_clk_rst_vif.set_freq_mhz(7);
+ `uvm_info(`gfn, $sformatf(
+ "slow clock freq=%fMHz, period=%0dns",
+ cfg.slow_clk_rst_vif.clk_freq_mhz,
+ cfg.slow_clk_rst_vif.clk_period_ps
+ ), UVM_MEDIUM)
+ cfg.esc_clk_rst_vif.set_freq_mhz(cfg.clk_rst_vif.clk_freq_mhz);
+ cfg.lc_clk_rst_vif.set_freq_mhz(cfg.clk_rst_vif.clk_freq_mhz);
+ cfg.aon_clk_rst_vif.set_freq_mhz(cfg.clk_rst_vif.clk_freq_mhz);
+ set_ndmreset_req('0);
+ control_assertions(0);
+ endtask
+
+ virtual task setup_interrupt(bit enable);
+ csr_wr(.ptr(ral.intr_enable.wakeup), .value(enable));
+ `uvm_info(`gfn, $sformatf("Wakeup interrupt is %0sabled", enable ? "en" : "dis"), UVM_MEDIUM)
+ endtask
+
+ // May check intr_state.wakeup CSR against expected, and regardless, it checks that the
+ // interrupt output matches intr_state && intr_enable. The first check is disabled if
+ // check_expected is off, which is used when a reset and an interrupt come in close
+ // temporal proximity.
+ virtual task check_and_clear_interrupt(bit expected, bit check_expected = 1'b1);
+ bit enable;
+ `uvm_info(`gfn, "Checking and clearing interrupt", UVM_MEDIUM)
+ if (check_expected) begin
+ csr_rd_check(.ptr(ral.intr_state.wakeup), .compare_value(expected),
+ .err_msg("interrupt mismatch"));
+ end else begin
+ csr_rd(.ptr(ral.intr_state.wakeup), .value(expected));
+ end
+ csr_rd(.ptr(ral.intr_enable.wakeup), .value(enable));
+ `DV_CHECK_EQ(cfg.pwrmgr_vif.intr_wakeup, expected && enable)
+ csr_wr(.ptr(ral.intr_state.wakeup), .value(1'b1));
+ endtask
+
+ local function void raise_fast_objection(string label);
+ ++fast_objection_count;
+ `uvm_info(`gfn, $sformatf("Raising fast objection to %0d for %0s", fast_objection_count, label),
+ UVM_HIGH)
+ endfunction
+
+ local function void drop_fast_objection(string label);
+ --fast_objection_count;
+ `uvm_info(`gfn, $sformatf("Dropping fast objection to %0d for %0s", fast_objection_count, label
+ ), UVM_HIGH)
+ endfunction
+
+ local function void raise_slow_objection(string label);
+ ++slow_objection_count;
+ `uvm_info(`gfn, $sformatf("Raising slow objection to %0d for %0s", slow_objection_count, label),
+ UVM_MEDIUM)
+ endfunction
+
+ local function void drop_slow_objection(string label);
+ --slow_objection_count;
+ `uvm_info(`gfn, $sformatf("Dropping slow objection to %0d for %0s", slow_objection_count, label
+ ), UVM_MEDIUM)
+ endfunction
+
+ virtual function void set_ndmreset_req(logic value);
+ cfg.pwrmgr_vif.cpu_i.ndmreset_req = value;
+ endfunction
+
+ // Generates expected responses for the slow fsm.
+ // - Completes the clock handshake with the ast: when a clk_en output changes, after a few
+ // cycles the ast is expected to set the corresponding clk_val input to the same value.
+ // - It is possible changes occur in fast succession, so the side-effect is pipelined.
+ // Uses macros because VCS flags an error for assignments to automatic variables,
+ // even if the variable is a ref to an interface variable.
+
+ `define SLOW_DETECT(rsp_name_, req_) \
+ forever \
+ @req_ begin \
+ raise_slow_objection(rsp_name_); \
+ `uvm_info(`gfn, $sformatf( \
+ "slow_responder: Will drive %0s to %b", rsp_name_, req_), UVM_MEDIUM) \
+ end
+
+ `define SLOW_SHIFT_SR(req_, rsp_sr_) \
+ forever \
+ @cfg.slow_clk_rst_vif.cb begin \
+ rsp_sr_ = {rsp_sr_[MaxCyclesBeforeEnable-1:0], req_}; \
+ end
+
+ `define SLOW_ASSIGN(rsp_name_, cycles_, rsp_sr_, rsp_) \
+ forever \
+ @(rsp_sr_[cycles_]) begin \
+ `uvm_info(`gfn, $sformatf( \
+ "slow_responder: Driving %0s to %b after %0d AON cycles.", \
+ rsp_name_, \
+ rsp_sr_[cycles_], \
+ cycles_ \
+ ), UVM_MEDIUM) \
+ rsp_ <= rsp_sr_[cycles_]; \
+ drop_slow_objection(rsp_name_); \
+ end
+
+ task slow_responder();
+ logic [MaxCyclesBeforeEnable:0] core_clk_val_sr;
+ logic [MaxCyclesBeforeEnable:0] io_clk_val_sr;
+ logic [MaxCyclesBeforeEnable:0] usb_clk_val_sr;
+ logic [MaxCyclesBeforeEnable:0] main_pd_val_sr;
+ fork
+ `SLOW_DETECT("core_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.core_clk_en)
+ `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.core_clk_en, core_clk_val_sr)
+ `SLOW_ASSIGN("core_clk_val", cycles_before_core_clk_en, core_clk_val_sr,
+ cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.core_clk_val)
+
+ `SLOW_DETECT("io_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.io_clk_en)
+ `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.io_clk_en, io_clk_val_sr)
+ // Notice this splits updates due to io_clk_en in two processes: with a single process
+ // and a wait inside a quick sequence of changes would cause skipping some update, per
+ // SV scheduling semantics.
+ forever
+ @(io_clk_val_sr[cycles_before_io_clk_en]) begin
+ logic new_value = io_clk_val_sr[cycles_before_io_clk_en];
+ `uvm_info(`gfn, $sformatf(
+ "slow_responder: Driving %0s to %b after %0d AON cycles.",
+ "io_clk_val",
+ new_value,
+ cycles_before_io_clk_en
+ ), UVM_MEDIUM)
+ if (new_value == 1) begin
+ cfg.clk_rst_vif.start_clk();
+ cfg.lc_clk_rst_vif.start_clk();
+ cfg.esc_clk_rst_vif.start_clk();
+ end else begin
+ cfg.clk_rst_vif.stop_clk();
+ cfg.lc_clk_rst_vif.stop_clk();
+ cfg.esc_clk_rst_vif.stop_clk();
+ end
+ end
+ forever
+ @(io_clk_val_sr[cycles_before_io_clk_en+2]) begin
+ logic new_value = io_clk_val_sr[cycles_before_io_clk_en+2];
+ cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.io_clk_val <= new_value;
+ drop_slow_objection("io_clk_val");
+ end
+
+ `SLOW_DETECT("usb_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.usb_clk_en)
+ `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.usb_clk_en, usb_clk_val_sr)
+ `SLOW_ASSIGN("usb_clk_val", cycles_before_usb_clk_en, usb_clk_val_sr,
+ cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.usb_clk_val)
+
+ `SLOW_DETECT("main_pok", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.main_pd_n)
+ `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.main_pd_n, main_pd_val_sr)
+ `SLOW_ASSIGN("main_pok", cycles_before_main_pok, main_pd_val_sr,
+ cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.main_pok)
+ join_none
+ endtask : slow_responder
+ `undef SLOW_DETECT
+ `undef SLOW_SHIFT_SR
+ `undef SLOW_ASSIGN
+
+ // Generates expected responses for the fast fsm.
+ // - Completes the reset handshake with the rstmgr for lc and sys resets: soon after a
+ // reset is requested the corresponding active low reset src must go low.
+ // - Completes the handshake with the clkmgr for io, main, and usb clocks:
+ // each status input needs to track the corresponding ip_clk_en output.
+ // - Completes handshake with lc and otp: *_done needs to track *_init.
+ // Macros for the same reason as the slow responder.
+
+ `define FAST_RESPONSE_ACTION(rsp_name, rsp, req, cycles) \
+ `uvm_info(`gfn, $sformatf( \
+ "fast_responder %s: Will drive %0s to %b in %0d fast clock cycles", \
+ rsp_name, rsp_name, req, cycles), UVM_HIGH) \
+ cfg.clk_rst_vif.wait_clks(cycles); \
+ rsp <= req; \
+ `uvm_info(`gfn, $sformatf("fast_responder %s: Driving %0s to %b", rsp_name, rsp_name, req), UVM_HIGH) \
+
+
+ task fast_responder();
+ fork
+ forever
+ @cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req begin
+ `uvm_info(`gfn, $sformatf(
+ "fast responder got rst_lc_req change to 0x%x",
+ cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req
+ ), UVM_HIGH)
+ raise_fast_objection("rst_lc_src_n");
+ `FAST_RESPONSE_ACTION("rst_lc_src_n", cfg.pwrmgr_vif.fast_cb.pwr_rst_rsp.rst_lc_src_n,
+ ~cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req,
+ cycles_before_rst_lc_src)
+ if (cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req[1] == 1'b0) begin
+ cfg.esc_clk_rst_vif.drive_rst_pin(1);
+ cfg.lc_clk_rst_vif.drive_rst_pin(1);
+ end else begin
+ // And clear all reset requests when rst_lc_req[1] goes high, because when
+ // peripherals are reset they should drop their reset requests.
+ cfg.esc_clk_rst_vif.drive_rst_pin(0);
+ cfg.lc_clk_rst_vif.drive_rst_pin(0);
+ clear_escalation_reset();
+ clear_ndm_reset();
+ cfg.pwrmgr_vif.update_resets('0);
+ cfg.pwrmgr_vif.update_sw_rst_req(prim_mubi_pkg::MuBi4False);
+ `uvm_info(`gfn, "Clearing resets", UVM_MEDIUM)
+ end
+ drop_fast_objection("rst_lc_src_n");
+ `uvm_info(`gfn, "fast responder done with rst_lc_req change", UVM_HIGH)
+ end
+ forever
+ @cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_sys_req begin
+ raise_fast_objection("rst_sys_src_n");
+ `FAST_RESPONSE_ACTION("rst_sys_src_n", cfg.pwrmgr_vif.fast_cb.pwr_rst_rsp.rst_sys_src_n,
+ ~cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_sys_req,
+ cycles_before_rst_sys_src)
+ drop_fast_objection("rst_sys_src_n");
+ end
+
+ forever
+ @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en begin
+ logic new_value = cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en;
+ raise_fast_objection("io_status");
+ `uvm_info(`gfn, $sformatf(
+ "fast_responder: Will drive %0s to %b in %0d fast clock cycles",
+ "io_status",
+ new_value,
+ cycles_before_io_status
+ ), UVM_HIGH)
+ cfg.clk_rst_vif.wait_clks(cycles_before_io_status);
+ if (new_value) cfg.esc_clk_rst_vif.start_clk();
+ else cfg.esc_clk_rst_vif.stop_clk();
+ cfg.clk_rst_vif.wait_clks(2);
+ cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.io_status <= new_value;
+ `uvm_info(`gfn, $sformatf(
+ "fast_responder: Driving %0s to %b",
+ "io_status",
+ cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en
+ ), UVM_HIGH)
+ drop_fast_objection("io_status");
+ end
+
+ forever
+ @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.main_ip_clk_en begin
+ raise_fast_objection("main_status");
+ `FAST_RESPONSE_ACTION("main_status", cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.main_status,
+ cfg.pwrmgr_vif.fast_cb.pwr_clk_req.main_ip_clk_en,
+ cycles_before_main_status)
+ drop_fast_objection("main_status");
+ end
+ forever
+ @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.usb_ip_clk_en begin
+ raise_fast_objection("usb_status");
+ `FAST_RESPONSE_ACTION("usb_status", cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.usb_status,
+ cfg.pwrmgr_vif.fast_cb.pwr_clk_req.usb_ip_clk_en,
+ cycles_before_usb_status)
+ drop_fast_objection("usb_status");
+ end
+ forever
+ @cfg.pwrmgr_vif.fast_cb.pwr_lc_req.lc_init begin
+ raise_fast_objection("lc_done");
+ `FAST_RESPONSE_ACTION("lc_done", cfg.pwrmgr_vif.fast_cb.pwr_lc_rsp.lc_done,
+ cfg.pwrmgr_vif.fast_cb.pwr_lc_req.lc_init, cycles_before_lc_done)
+ drop_fast_objection("lc_done");
+ end
+ forever
+ @cfg.pwrmgr_vif.fast_cb.pwr_otp_req.otp_init begin
+ raise_fast_objection("otp_done");
+ `FAST_RESPONSE_ACTION("otp_done", cfg.pwrmgr_vif.fast_cb.pwr_otp_rsp.otp_done,
+ cfg.pwrmgr_vif.fast_cb.pwr_otp_req.otp_init, cycles_before_otp_done)
+ drop_fast_objection("otp_done");
+ end
+ join_none
+ endtask : fast_responder
+ `undef FAST_RESPONSE_ACTION
+
+ function void control_assertions(bit enable);
+ `uvm_info(`gfn, $sformatf("%0sabling assertions", enable ? "En" : "Dis"), UVM_MEDIUM)
+ cfg.pwrmgr_clock_enables_sva_vif.disable_sva = !enable;
+ cfg.pwrmgr_rstmgr_sva_vif.disable_sva = !enable;
+ endfunction
+
+ local task wait_for_fall_through();
+ `DV_WAIT(!cfg.pwrmgr_vif.pwr_cpu.core_sleeping)
+ exp_intr = 1'b1;
+ `uvm_info(`gfn, "wait_for_fall_through succeeds", UVM_MEDIUM)
+ endtask
+
+ local task wait_for_abort();
+ `DV_WAIT(
+ !cfg.pwrmgr_vif.pwr_flash.flash_idle || !cfg.pwrmgr_vif.pwr_otp_rsp.otp_idle ||
+ !cfg.pwrmgr_vif.pwr_lc_rsp.lc_idle)
+ exp_intr = 1'b1;
+ `uvm_info(`gfn, "wait_for_abort succeeds", UVM_MEDIUM)
+ endtask
+
+ local task wait_for_low_power_transition();
+ wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry);
+ exp_wakeup_reasons = wakeups & wakeups_en;
+ exp_intr = 1'b1;
+ `uvm_info(`gfn, "Setting expected interrupt", UVM_MEDIUM)
+ endtask
+
+ task process_low_power_hint();
+ `uvm_info(`gfn, "Entering process_low_power_hint", UVM_MEDIUM)
+ // Timeout if the low power transition waits too long for WFI.
+ `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive)
+ `uvm_info(`gfn, "In process_low_power_hint pre forks", UVM_MEDIUM)
+ // Clear expectations.
+ exp_wakeup_reasons = 1'b0;
+ fork
+ begin : isolation_fork
+ fork
+ wait_for_fall_through();
+ wait_for_abort();
+ wait_for_low_power_transition();
+ join_any
+ disable fork;
+ end
+ join
+ // At this point we know the low power transition went through or was aborted.
+ // If it went through, determine if the transition to active state is for a reset, and
+ // cancel the expected interrupt.
+ if (exp_wakeup_reasons) begin
+ `DV_WAIT(cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateMainPowerOn)
+ if (cfg.pwrmgr_vif.pwrup_cause == pwrmgr_pkg::Reset) begin
+ `uvm_info(`gfn, "Cancelling expected interrupt", UVM_MEDIUM)
+ exp_intr = 1'b0;
+ end
+ end
+ endtask
+
+ // Updates control CSR.
+ task update_control_csr();
+ fork
+ begin
+ ral.control.core_clk_en.set(control_enables.core_clk_en);
+ ral.control.io_clk_en.set(control_enables.io_clk_en);
+ ral.control.usb_clk_en_lp.set(control_enables.usb_clk_en_lp);
+ ral.control.usb_clk_en_active.set(control_enables.usb_clk_en_active);
+ ral.control.main_pd_n.set(control_enables.main_pd_n);
+ ral.control.low_power_hint.set(low_power_hint);
+ // Disable assertions when main power is down.
+ control_assertions(control_enables.main_pd_n);
+ `uvm_info(`gfn, $sformatf(
+ "Setting control CSR to 0x%x, enables=%p, low_power_hint=%b",
+ ral.control.get(),
+ control_enables,
+ low_power_hint
+ ), UVM_MEDIUM)
+ csr_update(.csr(ral.control));
+ end
+ // Predict the effect of the potential low power transition.
+ if (low_power_hint) process_low_power_hint();
+ join_any
+ endtask : update_control_csr
+
+ // This enables the fast fsm to transition to low power when all nvms are idle after the
+ // transition is enabled by software and cpu WFI. When not all are idle the transition is
+ // aborted.
+ virtual task set_nvms_idle(logic flash_idle = 1'b1, logic lc_idle = 1'b1, logic otp_idle = 1'b1);
+ `uvm_info(`gfn, $sformatf(
+ "Setting nvms idle: flash=%b, lc=%b, otp=%b", flash_idle, lc_idle, otp_idle),
+ UVM_MEDIUM)
+ cfg.pwrmgr_vif.update_flash_idle(flash_idle);
+ cfg.pwrmgr_vif.update_lc_idle(lc_idle);
+ cfg.pwrmgr_vif.update_otp_idle(otp_idle);
+ endtask
+
+ // Waits for the fast fsm becoming active after SW initiated low power, indicated by the
+ // fetch_en output going high.
+ task wait_for_fast_fsm_active();
+ `uvm_info(`gfn, "starting wait for pwrmgr fast fsm active", UVM_MEDIUM)
+ `DV_SPINWAIT(wait (cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On);,
+ "timeout waiting for the CPU to be active", FetchEnTimeoutNs)
+ `uvm_info(`gfn, "pwrmgr fast fsm is active", UVM_MEDIUM)
+ endtask
+
+ task wait_for_reset_cause(pwrmgr_pkg::reset_cause_e cause);
+ `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.reset_cause == cause)
+ `uvm_info(`gfn, $sformatf("Observed reset cause_match 0x%x", cause), UVM_MEDIUM)
+ endtask
+
+ virtual task wait_for_csr_to_propagate_to_slow_domain();
+ csr_wr(.ptr(ral.cfg_cdc_sync), .value(1'b1));
+ csr_spinwait(.ptr(ral.cfg_cdc_sync), .exp_data(1'b0),
+ .timeout_ns(PropagationToSlowTimeoutInNanoSeconds));
+ `uvm_info(`gfn, "CSR updates made it to the slow domain", UVM_MEDIUM)
+ endtask
+
+ // Checks the reset_status CSR matches expectations.
+ task check_reset_status(resets_t expected_resets);
+ csr_rd_check(.ptr(ral.reset_status[0]), .compare_value(expected_resets),
+ .err_msg("reset_status"));
+ endtask
+
+ task fast_check_reset_status(resets_t expected_resets);
+ logic [pwrmgr_reg_pkg::NumRstReqs-1:0] init_reset_status;
+ `uvm_info(`gfn, "init reset status", UVM_MEDIUM);
+ // Wait to get out of low power state, since all reset status should have settled.
+ if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateLowPower) begin
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateLowPower);,
+ "fast state out of low power for reset timeout", 15_000)
+ end
+
+ init_reset_status = cfg.pwrmgr_vif.reset_status;
+ if (expected_resets == init_reset_status) begin
+ // This is a success, so nothing more to do.
+ return;
+ end else begin
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.reset_status != init_reset_status);, $sformatf(
+ "reset_status wait timeout exp:%x init:%x", expected_resets, init_reset_status),
+ 15_000)
+ // The various bits of reset_status could have different sync delays, wait some more.
+ cfg.clk_rst_vif.wait_clks(2);
+ `DV_CHECK_EQ(cfg.pwrmgr_vif.reset_status, expected_resets)
+ end
+ endtask
+
+ // Checks the wake_status CSR matches expectations.
+ task check_wake_status(wakeups_t expected_wakeups);
+ csr_rd_check(.ptr(ral.wake_status[0]), .compare_value(expected_wakeups),
+ .err_msg("wake_status"));
+ endtask
+
+ task fast_check_wake_status(wakeups_t expected_wakeups);
+ logic [pwrmgr_reg_pkg::NumWkups-1:0] init_wakeup_status;
+ `uvm_info(`gfn, "init wakeup", UVM_MEDIUM);
+ init_wakeup_status = cfg.pwrmgr_vif.wakeup_status;
+
+ // Wait to get out of low power state, since all wake status should have settled
+ if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateLowPower) begin
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateLowPower);,
+ "fast state out of low power for wakeup timeout", 15_000)
+ end
+
+ if (expected_wakeups == init_wakeup_status) begin
+ // This is a success, so nothing more to do.
+ return;
+ end else begin
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.wakeup_status != init_wakeup_status);, $sformatf(
+ "wakeup_status wait timeout exp:%x init:%x", expected_wakeups, init_wakeup_status
+ ), 15_000)
+ // The various bits of wakeup_status could have different sync delays, so wait some more.
+ cfg.clk_rst_vif.wait_clks(2);
+ `DV_CHECK_EQ(cfg.pwrmgr_vif.wakeup_status, expected_wakeups)
+ end
+ endtask
+
+ task fast_check_wake_info(wakeups_t reasons, wakeups_t prior_reasons = '0, bit fall_through,
+ bit prior_fall_through = '0, bit abort, bit prior_abort = '0);
+ pwrmgr_reg_pkg::pwrmgr_hw2reg_wake_info_reg_t initial_value, exp_value;
+ initial_value = cfg.pwrmgr_vif.wake_info;
+
+ if (disable_wakeup_capture) begin
+ exp_value.reasons = prior_reasons;
+ exp_value.fall_through = prior_fall_through;
+ exp_value.abort = prior_abort;
+ end else begin
+ exp_value.reasons = (reasons | prior_reasons);
+ exp_value.fall_through = (fall_through | prior_fall_through);
+ exp_value.abort = (abort | prior_abort);
+ end
+ if (exp_value != initial_value) begin
+ // The various bits of wake_info could have different sync delays, so wait some more.
+ cfg.clk_rst_vif.wait_clks(1);
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.wake_info != initial_value);, $sformatf(
+ "wake info wait timeout exp:%p init:%p", exp_value, initial_value), 15_000)
+ end
+ endtask : fast_check_wake_info
+
+ // Checks the wake_info CSR matches expectations depending on capture disable.
+ // The per-field "prior_" arguments support cases where the wake_info register was not
+ // cleared and may contain residual values.
+ task check_wake_info(wakeups_t reasons, wakeups_t prior_reasons = '0, bit fall_through,
+ bit prior_fall_through = '0, bit abort, bit prior_abort = '0);
+ if (disable_wakeup_capture) begin
+ csr_rd_check(.ptr(ral.wake_info.reasons), .compare_value(prior_reasons),
+ .err_msg("With capture disabled"));
+ csr_rd_check(.ptr(ral.wake_info.fall_through), .compare_value(prior_fall_through),
+ .err_msg("With capture disabled"));
+ csr_rd_check(.ptr(ral.wake_info.abort), .compare_value(prior_abort),
+ .err_msg("With capture disabled"));
+ end else begin
+ csr_rd_check(.ptr(ral.wake_info.reasons), .compare_value(reasons | prior_reasons),
+ .err_msg("With capture enabled"));
+ csr_rd_check(.ptr(ral.wake_info.fall_through),
+ .compare_value(fall_through | prior_fall_through),
+ .err_msg("With capture enabled"));
+ csr_rd_check(.ptr(ral.wake_info.abort), .compare_value(abort | prior_abort),
+ .err_msg("With capture enabled"));
+ end
+ endtask : check_wake_info
+
+ task clear_wake_info();
+ // To clear wake_info, capture must be disabled.
+ csr_wr(.ptr(ral.wake_info_capture_dis), .value(1'b1));
+ csr_wr(.ptr(ral.wake_info), .value('1));
+ endtask
+
+ function void send_escalation_reset();
+ `uvm_info(`gfn, "Sending escalation reset", UVM_MEDIUM)
+ cfg.m_esc_agent_cfg.vif.sender_cb.esc_tx_int <= 2'b10;
+ endfunction
+
+ function void clear_escalation_reset();
+ `uvm_info(`gfn, "Clearing escalation reset", UVM_MEDIUM)
+ cfg.m_esc_agent_cfg.vif.sender_cb.esc_tx_int <= 2'b01;
+ endfunction
+
+ function void send_ndm_reset();
+ `uvm_info(`gfn, "Sending ndm reset", UVM_MEDIUM)
+ cfg.pwrmgr_vif.cpu_i.ndmreset_req = 1'b1;
+ endfunction
+
+ function void clear_ndm_reset();
+ `uvm_info(`gfn, "Clearing ndm reset", UVM_MEDIUM)
+ cfg.pwrmgr_vif.cpu_i.ndmreset_req = 1'b0;
+ endfunction
+
+ task send_power_glitch();
+ // Create glitch by 'glitch_power_reset'. An outgoing alert is only possible
+ // when main power is up.
+ if (control_enables.main_pd_n) expect_fatal_alerts = 1;
+ else expect_fatal_alerts = 0;
+ `uvm_info(`gfn, $sformatf(
+ "Sending power glitch, expecting %0s alert", expect_fatal_alerts ? "an" : "no"),
+ UVM_MEDIUM)
+ cfg.pwrmgr_vif.glitch_power_reset();
+ endtask
+
+ // bad_bits = {done, good}
+ task add_rom_rsp_noise();
+ bit [MUBI4W*2-1:0] bad_bits;
+ int delay;
+
+ repeat (10) begin
+ delay = $urandom_range(5, 10);
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bad_bits,
+ bad_bits[MUBI4W*2-1:MUBI4W] != prim_mubi_pkg::MuBi4True;
+ bad_bits[MUBI4W*2-1:MUBI4W] != prim_mubi_pkg::MuBi4False;
+ bad_bits[MUBI4W-1:0] != prim_mubi_pkg::MuBi4False;
+ bad_bits[MUBI4W-1:0] != prim_mubi_pkg::MuBi4True;)
+ `uvm_info(`gfn, $sformatf("add_rom_rsp_noise to 0x%x", bad_bits), UVM_HIGH)
+ cfg.pwrmgr_vif.rom_ctrl = bad_bits;
+ #(delay * 10ns);
+ end
+ endtask : add_rom_rsp_noise
+
+ // Drive rom_ctrl at post reset stage
+ virtual task init_rom_response();
+ if (cfg.pwrmgr_vif.rom_ctrl.done != prim_mubi_pkg::MuBi4True) begin
+ cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val(
+ .t_weight(1), .f_weight(1), .other_weight(1)
+ );
+ cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val(
+ .t_weight(0), .f_weight(1), .other_weight(1)
+ );
+ `DV_WAIT(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone)
+ cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val(
+ .t_weight(1), .f_weight(1), .other_weight(1)
+ );
+ cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val(
+ .t_weight(0), .f_weight(1), .other_weight(1)
+ );
+ cfg.aon_clk_rst_vif.wait_clks(10);
+ cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val(
+ .t_weight(1), .f_weight(1), .other_weight(1)
+ );
+ cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val(
+ .t_weight(0), .f_weight(1), .other_weight(1)
+ );
+ cfg.aon_clk_rst_vif.wait_clks(5);
+ cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val(
+ .t_weight(1), .f_weight(1), .other_weight(1)
+ );
+ cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val(
+ .t_weight(0), .f_weight(1), .other_weight(1)
+ );
+ cfg.aon_clk_rst_vif.wait_clks(5);
+ cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True;
+ cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True;
+ end
+ `uvm_info(`gfn, "Set rom response to MuBi4True", UVM_MEDIUM)
+ endtask
+
+endclass : pwrmgr_base_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv
new file mode 100644
index 0000000..efee661
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv
@@ -0,0 +1,125 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+class pwrmgr_common_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_common_vseq)
+
+ constraint num_trans_c {num_trans inside {[1 : 2]};}
+ `uvm_object_new
+
+ parameter int STATE_TRANSITION_NS = 50000;
+
+ virtual task pre_start();
+ csr_excl_item csr_excl = ral.get_excl_item();
+ super.pre_start();
+ // In pwrmgr, random reset event can be regarded as power glitch in tb.
+ // Since glitch is marked as fatal and creates alert after PR#12072,
+ // exclude pwrmgr_reg_block.fault_status from the random reset tests
+ // to avoid spurious test failure.
+ if (common_seq_type inside {"csr_mem_rw_with_rand_reset", "stress_all_with_rand_reset"}) begin
+ csr_excl.add_excl("pwrmgr_reg_block.fault_status", CsrExclCheck);
+ expect_fatal_alerts = 1;
+ end
+ endtask
+
+ virtual task body();
+ run_common_vseq_wrapper(num_trans);
+ `uvm_info(`gfn, "Done with body", UVM_HIGH)
+ endtask : body
+
+ task rand_reset_eor_clean_up();
+ // clear wakeup at the beginning
+ cfg.pwrmgr_vif.update_wakeups('0);
+ cfg.clk_rst_vif.wait_clks(2);
+
+ // clear interrupt
+ csr_wr(.ptr(ral.intr_state), .value(1));
+ endtask : rand_reset_eor_clean_up
+
+ // pwrmgr has three alert events
+ // REG_INTG_ERR, ESC_TIMEOUT and MAIN_PD_GLITCH
+ // all others will trigger only reset.
+ // So disable wait_alert by skipping super.check_sec_cm_fi_resp()
+ virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy);
+ string slow_st_to, fast_st_to, msg;
+ // to avoid 100 column cut off
+ slow_st_to = {
+ "slow state local esc chk timeout:",
+ "fast_state %s, pwr_ast_req.pwr_clamp %0d, pwr_ast_req.main_pd_n %0d"
+ };
+ fast_st_to = {
+ "fast state local esc chk timeout:",
+ "pwr_rst_req.rst_lc_req %0d, pwr_rst_req.rst_sys_req %0d, pwr_clk_req %0d"
+ };
+
+ `uvm_info(`gfn, $sformatf("sec_cm_type %s", if_proxy.sec_cm_type.name), UVM_MEDIUM)
+
+ case (if_proxy.sec_cm_type)
+ SecCmPrimSparseFsmFlop: begin
+ // if slow state is unknown,
+ // wait for
+ // fast_state == FastPwrStateInvalid
+ // tb.dut.pwr_ast_o.pwr_clamp == 1
+ // tb.dut.pwr_ast_o.main_pd_n == 0
+ //
+ // if fast state is unknown,
+ // wait for
+ // tb.dut.pwr_rst_o.rst_lc_req == 2'b11
+ // tb.dut.pwr_rst_o.rst_sys_req == 2'b11
+ // tb.dut.pwr_clk_o == 3'b0
+ if (!uvm_re_match("*.u_slow_fsm.*", if_proxy.path)) begin
+ `uvm_info(`gfn, "detect unknown slow state", UVM_MEDIUM)
+ msg = $sformatf(
+ slow_st_to,
+ cfg.pwrmgr_vif.fast_state.name,
+ cfg.pwrmgr_vif.pwr_ast_req.pwr_clamp,
+ cfg.pwrmgr_vif.pwr_ast_req.main_pd_n
+ );
+
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateInvalid &&
+ cfg.pwrmgr_vif.pwr_ast_req.pwr_clamp == 1 &&
+ cfg.pwrmgr_vif.pwr_ast_rsp.main_pok == 0);, msg, STATE_TRANSITION_NS)
+ end
+ if (!uvm_re_match("*.u_fsm.*", if_proxy.path)) begin
+ `uvm_info(`gfn, "detect unknown fast state", UVM_MEDIUM)
+ msg = $sformatf(
+ fast_st_to,
+ cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req,
+ cfg.pwrmgr_vif.pwr_rst_req.rst_sys_req,
+ cfg.pwrmgr_vif.pwr_clk_req
+ );
+
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req == 2'b11 &&
+ cfg.pwrmgr_vif.pwr_rst_req.rst_sys_req == 2'b11 &&
+ cfg.pwrmgr_vif.pwr_clk_req == 3'h0);, msg, 5000)
+ end
+ end
+ SecCmPrimCount: begin
+ // wait for fast state to be FastPwrStateResetPrep
+ // before assert reset
+ `uvm_info(`gfn, "check rx_clk local esc", UVM_MEDIUM)
+ msg = $sformatf(
+ "rx clk loc esc chk timeout : fast_state %s", cfg.pwrmgr_vif.fast_state.name
+ );
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep);, msg,
+ STATE_TRANSITION_NS)
+ end
+ default: `uvm_fatal(`gfn, $sformatf("unexpected sec_cm_type %s", if_proxy.sec_cm_type.name))
+ endcase // case (if_proxy.sec_cm_type)
+ // This makes sure errors are not injected too close together to avoid confusion.
+ cfg.aon_clk_rst_vif.wait_clks(10);
+ endtask : check_sec_cm_fi_resp
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv
new file mode 100644
index 0000000..14aebc1
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv
@@ -0,0 +1,104 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Test multiple resets with setting lc_* inputs with random value.
+class pwrmgr_disable_rom_integrity_check_vseq extends pwrmgr_base_vseq;
+
+ `uvm_object_utils(pwrmgr_disable_rom_integrity_check_vseq)
+ `uvm_object_new
+
+ constraint wakeups_c {wakeups == 0;}
+ constraint wakeups_en_c {wakeups_en == 0;}
+
+ function void post_randomize();
+ sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4));
+ super.post_randomize();
+ endfunction
+
+ task body();
+ resets_t enabled_resets;
+ wait_for_fast_fsm_active();
+ check_reset_status('0);
+
+ for (int i = 0; i < 5; ++i) begin
+ `uvm_info(`gfn, $sformatf("Starting new round%0d", i), UVM_MEDIUM)
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ setup_interrupt(.enable(en_intr));
+
+ // set lc ctrl input to random value
+ cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val(
+ .t_weight(0), .f_weight(1), .other_weight(4)
+ );
+ cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(0), .f_weight(1), .other_weight(4));
+ cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True;
+ cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False;
+ `uvm_info(`gfn, "Set done True, good False", UVM_MEDIUM)
+ enabled_resets = resets_en & resets;
+ `uvm_info(`gfn, $sformatf(
+ "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b",
+ enabled_resets,
+ power_glitch_reset,
+ escalation_reset,
+ sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True,
+ ndm_reset
+ ), UVM_MEDIUM)
+
+ csr_wr(.ptr(ral.reset_en[0]), .value(resets_en));
+ // This is necessary to propagate reset_en.
+ wait_for_csr_to_propagate_to_slow_domain();
+
+ // Trigger resets. The glitch is sent prior to the externals since if it is delayed
+ // it will cause a separate reset after the externals, which complicates the checks.
+ if (power_glitch_reset) send_power_glitch();
+ cfg.clk_rst_vif.wait_clks(cycles_before_reset);
+
+ `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM)
+ cfg.pwrmgr_vif.update_resets(resets);
+ `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM)
+ if (escalation_reset) send_escalation_reset();
+ cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr);
+ if (ndm_reset) send_ndm_reset();
+
+ `uvm_info(`gfn, "Wait for Fast State NE FastPwrStateActive", UVM_MEDIUM)
+ `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive)
+
+ // Check fast state is not FastPwrStateActive for a while
+ repeat (20) begin
+ @cfg.slow_clk_rst_vif.cb;
+ `DV_CHECK_NE(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateActive)
+ end
+
+ `uvm_info(`gfn, "Set lc ctrl input On", UVM_MEDIUM)
+ cfg.pwrmgr_vif.lc_hw_debug_en = lc_ctrl_pkg::On;
+ cfg.pwrmgr_vif.lc_dft_en = lc_ctrl_pkg::On;
+
+ wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1);
+
+ wait_for_fast_fsm_active();
+ `uvm_info(`gfn, "Back from reset", UVM_MEDIUM)
+
+ check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0));
+
+ cfg.slow_clk_rst_vif.wait_clks(4);
+ check_reset_status('0);
+
+ // And check interrupt is not set.
+ check_and_clear_interrupt(.expected(1'b0));
+ end
+ clear_wake_info();
+ endtask
+
+endclass : pwrmgr_disable_rom_integrity_check_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv
new file mode 100644
index 0000000..de2a227
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv
@@ -0,0 +1,54 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// Description:
+// This sequence creates escalation clock and reset malfunction at FastPwrStateActive state.
+// This event will trigger timeout counter and assert timeout signal
+// when timeout counter reaches EscTimeOutCnt value.
+// Once the timeout occurs, it will create fatal alert and alert agent(tb) will set esc rst.
+// The pass or failure status is determined in the cip scoreboard.
+class pwrmgr_esc_clk_rst_malfunc_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_esc_clk_rst_malfunc_vseq)
+
+ `uvm_object_new
+ constraint num_trans_c {num_trans inside {[1 : 3]};}
+
+ virtual task body();
+ wait_for_fast_fsm_active();
+ // Wait some time so the stimulus is sent after the fast fsm becoming active.
+ cfg.clk_rst_vif.wait_clks(4);
+ expect_fatal_alerts = 1;
+ trigger_escalation_timeout();
+ wait_for_fast_fsm_active();
+ endtask : body
+
+ // Trigers an escalation timeout fault, either stopping clk_esc_i or driving rst_esc_ni.
+ //
+ // Randomly set a bit to 0 or 1: if 0 stop clk_esc_i, if 1 make rst_esc_ni active.
+ task trigger_escalation_timeout();
+ int which = $urandom_range(0, 1);
+ `uvm_info(`gfn, $sformatf("Triggering escalation via %0s", which ? "rst" : "clk"), UVM_MEDIUM)
+ if (which == 0) cfg.esc_clk_rst_vif.stop_clk();
+ else cfg.esc_clk_rst_vif.drive_rst_pin(1'b0);
+
+ // Wait for cpu fetch to be disabled, as an indication a reset is triggered.
+ `DV_SPINWAIT(wait (cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On);,
+ "timeout waiting for the CPU to be inactive", FetchEnTimeoutNs)
+ `uvm_info(`gfn, "Releasing trigger", UVM_MEDIUM)
+ if (which == 0) cfg.esc_clk_rst_vif.start_clk();
+ else cfg.esc_clk_rst_vif.drive_rst_pin(1'b1);
+ endtask : trigger_escalation_timeout
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv
new file mode 100644
index 0000000..eaec398
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv
@@ -0,0 +1,54 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Description:
+// This test asserts glitch to power_reset and see
+// dut can recover gracefully.
+class pwrmgr_glitch_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_glitch_vseq)
+
+ `uvm_object_new
+
+ int trans_cnt = 0;
+ constraint num_trans_c {num_trans inside {[1 : 5]};}
+
+ virtual task body();
+ expect_fatal_alerts = 1;
+ for (int i = 0; i < num_trans; ++i) begin
+ wait_for_fast_fsm_active();
+ cfg.clk_rst_vif.wait_clks(4);
+
+ fork
+ send_power_glitch();
+ begin
+ cfg.pwrmgr_vif.update_ast_main_pok(0);
+ cfg.slow_clk_rst_vif.wait_clks(2);
+ cfg.pwrmgr_vif.update_ast_main_pok(1);
+ end
+ join
+
+ cfg.clk_rst_vif.wait_clks(cycles_before_reset);
+
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep &&
+ cfg.pwrmgr_vif.pwr_rst_req.rstreqs[2] == 1);, $sformatf(
+ "checker timeout : fast_state %s, pwr_rst_req 0x%x",
+ cfg.pwrmgr_vif.fast_state.name,
+ cfg.pwrmgr_vif.pwr_rst_req.rstreqs
+ ), 10000)
+
+ dut_init();
+ end
+ endtask : body
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv
new file mode 100644
index 0000000..ab265ca
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv
@@ -0,0 +1,75 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Description:
+// This test asserts global escalation reset to dut
+// and check glocal escalation request is handled by
+// dut properly.
+class pwrmgr_global_esc_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_global_esc_vseq)
+
+ `uvm_object_new
+
+ int trans_cnt = 0;
+ constraint num_trans_c {num_trans inside {[1 : 5]};}
+
+ virtual task body();
+ fork
+ send_esc();
+ check_rst_req();
+ join
+ endtask : body
+
+ task send_esc();
+ int cycle;
+ for (int i = 0; i < num_trans; ++i) begin
+ wait_for_fast_fsm_active();
+ cycle = $urandom_range(50, 300);
+ send_escalation_reset();
+ repeat (cycle) @(cfg.clk_rst_vif.cb);
+ clear_escalation_reset();
+ end
+ endtask : send_esc
+
+ task check_rst_req();
+ bit dut_init_done = -1;
+
+ while (trans_cnt < num_trans) begin
+ @(cfg.clk_rst_vif.cb);
+ wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive &&
+ cfg.pwrmgr_vif.pwr_rst_req.rstreqs[3] == 1'b1);
+ trans_cnt++;
+
+ // Make sure previous dut_init is done
+ if (dut_init_done > -1) begin
+ wait(dut_init_done == 1);
+ end
+ // Spawning dut_init thread then go to
+ // wait reset state
+ fork
+ begin
+ dut_init_done = 0;
+ dut_init();
+ dut_init_done = 1;
+ end
+ begin
+ cfg.clk_rst_vif.wait_clks(10);
+ end
+ join_any
+ end
+ wait(dut_init_done == 1);
+ endtask : check_rst_req
+
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv
new file mode 100644
index 0000000..ba35728
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv
@@ -0,0 +1,152 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// The test to create transition to invalid state from any lowpower transitions.
+class pwrmgr_lowpower_invalid_vseq extends pwrmgr_base_vseq;
+
+ `uvm_object_utils(pwrmgr_lowpower_invalid_vseq)
+ `uvm_object_new
+
+ // Create enum to map rtl local sparse state
+ // to continuous dv state.
+ typedef enum bit [3:0] {
+ DVWaitDisClks = 0,
+ DVWaitFallThrough = 1,
+ DVWaitNvmIdleChk = 2,
+ DVWaitLowPowerPrep = 3,
+ DVWaitReqPwrDn = 4,
+ DVWaitLowPower = 5,
+ DVWaitEnableClocks = 6,
+ DVWaitReleaseLcRst = 7,
+ DVWaitOtpInit = 8,
+ DVWaitLcInit = 9,
+ DVWaitAckPwrUp = 10,
+ DVWaitRomCheck = 11,
+ DVWaitStrap = 12,
+ DVWaitActive = 13,
+ DVWaitInvalid = 14
+ } reset_index_e;
+
+ constraint wakeups_c {wakeups != 0;}
+ constraint wakeup_en_c {
+ solve wakeups before wakeups_en;
+ |(wakeups_en & wakeups) == 1'b1;
+ }
+
+ task body();
+ reset_index_e reset_index;
+ resets_t enabled_resets;
+ string path = "tb.dut.u_fsm.fsm_invalid_i";
+ int num_of_target_states = 4;
+
+ // Spurious interrupt check can be executed by
+ // residue of lowpower task. Since we cannot kill csr op
+ // by disable fork, we have to disable spurious interrup check.
+ cfg.invalid_st_test = 1;
+
+ wait_for_fast_fsm_active();
+ `uvm_info(`gfn, "At body start", UVM_MEDIUM)
+ check_wake_status('0);
+ reset_index = DVWaitFallThrough;
+
+ for (int i = 0; i < num_of_target_states; ++i) begin
+ `uvm_info(`gfn, $sformatf("Starting new round%0d %s", i, reset_index.name), UVM_MEDIUM)
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ setup_interrupt(.enable(en_intr));
+ fork
+ start_lowpower_transition();
+ begin
+ int wait_time_ns = 10000;
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == dv2rtl_st(reset_index));, $sformatf(
+ "Timed out waiting for state %s", reset_index.name), wait_time_ns)
+
+ @cfg.clk_rst_vif.cbn;
+ `DV_CHECK(uvm_hdl_force(path, 1))
+ `uvm_info(`gfn, "Injected invalid slow state", UVM_MEDIUM)
+ @cfg.clk_rst_vif.cb;
+ end
+ join_any
+ @cfg.clk_rst_vif.cb;
+ `DV_CHECK(uvm_hdl_release(path))
+ `DV_CHECK(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateInvalid)
+
+ repeat (10) @cfg.clk_rst_vif.cb;
+
+ apply_reset();
+ reset_index++;
+ wait_for_fast_fsm_active();
+ end // for (int i = 0; i < 4; ++i)
+ endtask
+
+ task start_lowpower_transition();
+ wakeups_t enabled_wakeups = wakeups_en & wakeups;
+ `DV_CHECK(enabled_wakeups, $sformatf(
+ "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en))
+ `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM)
+ csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en));
+ low_power_hint = 1;
+ update_control_csr();
+
+ wait_for_csr_to_propagate_to_slow_domain();
+ `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM)
+
+ // Initiate low power transition.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b1);
+ set_nvms_idle();
+
+ `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive)
+
+ if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin
+ wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry);
+ end
+
+ // Now bring it back.
+ cfg.clk_rst_vif.wait_clks(cycles_before_wakeup);
+ cfg.pwrmgr_vif.update_wakeups(wakeups);
+
+ wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1);
+
+ // wakeups should be registered.
+ cfg.pwrmgr_vif.update_wakeups('1);
+
+ wait_for_fast_fsm_active();
+ `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM)
+ endtask : start_lowpower_transition
+
+ function pwrmgr_pkg::fast_pwr_state_e dv2rtl_st(reset_index_e idx);
+ case (idx)
+ DVWaitDisClks: return pwrmgr_pkg::FastPwrStateDisClks;
+ DVWaitFallThrough: return pwrmgr_pkg::FastPwrStateFallThrough;
+ DVWaitNvmIdleChk: return pwrmgr_pkg::FastPwrStateNvmIdleChk;
+ DVWaitLowPowerPrep: return pwrmgr_pkg::FastPwrStateLowPowerPrep;
+ DVWaitReqPwrDn: return pwrmgr_pkg::FastPwrStateReqPwrDn;
+ DVWaitLowPower: return pwrmgr_pkg::FastPwrStateLowPower;
+ DVWaitEnableClocks: return pwrmgr_pkg::FastPwrStateEnableClocks;
+ DVWaitReleaseLcRst: return pwrmgr_pkg::FastPwrStateReleaseLcRst;
+ DVWaitOtpInit: return pwrmgr_pkg::FastPwrStateOtpInit;
+ DVWaitLcInit: return pwrmgr_pkg::FastPwrStateLcInit;
+ DVWaitAckPwrUp: return pwrmgr_pkg::FastPwrStateAckPwrUp;
+ DVWaitRomCheck: return pwrmgr_pkg::FastPwrStateRomCheckDone;
+ DVWaitStrap: return pwrmgr_pkg::FastPwrStateStrap;
+ DVWaitActive: return pwrmgr_pkg::FastPwrStateActive;
+ DVWaitInvalid: return pwrmgr_pkg::FastPwrStateInvalid;
+ default: begin
+ `uvm_error("dv2rma_st", $sformatf("unknown index:%0d", idx))
+ end
+ endcase
+ endfunction : dv2rtl_st
+
+endclass : pwrmgr_lowpower_invalid_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv
new file mode 100644
index 0000000..8ae022f
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv
@@ -0,0 +1,153 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// The lowpower_wakeup race test randomly enables wakeups, info capture, and interrupts,
+// and sends wakeups in the temporal vecinity of low power entry. It also sends wakeups
+// after wakeup processing starts.
+class pwrmgr_lowpower_wakeup_race_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_lowpower_wakeup_race_vseq)
+
+ `uvm_object_new
+
+ constraint wakeups_c {wakeups != 0;}
+
+ rand bit keep_prior_wake_info;
+
+ constraint wakeup_en_c {
+ solve wakeups before wakeups_en;
+ |(wakeups_en & wakeups) == 1'b1;
+ }
+
+ rand int cycles_before_early_wakeup;
+ rand int cycles_before_transition;
+ constraint cycles_racing_c {
+ cycles_before_early_wakeup inside {[2 : 8]};
+ cycles_before_transition inside {[2 : 8]};
+ }
+
+ task body();
+ logic [TL_DW-1:0] value;
+ wakeups_t prior_reasons = '0;
+ bit prior_fall_through = '0;
+ bit prior_abort = '0;
+ wait_for_fast_fsm_active();
+
+ check_wake_status('0);
+ for (int i = 0; i < num_trans; ++i) begin
+ `uvm_info(`gfn, "Starting new round", UVM_MEDIUM)
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ setup_interrupt(.enable(en_intr));
+
+ csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en));
+ `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", wakeups_en & wakeups), UVM_MEDIUM)
+
+ if (keep_prior_wake_info) begin
+ csr_rd(.ptr(ral.wake_info.reasons), .value(prior_reasons));
+ csr_rd(.ptr(ral.wake_info.fall_through), .value(prior_fall_through));
+ csr_rd(.ptr(ral.wake_info.abort), .value(prior_abort));
+ end else begin
+ clear_wake_info();
+ prior_reasons = '0;
+ prior_fall_through = '0;
+ prior_abort = '0;
+ end
+ `uvm_info(`gfn, $sformatf(
+ "Prior wake_info: reasons=0x%x, fall_through=%b, abort=%b",
+ prior_reasons,
+ prior_fall_through,
+ prior_abort
+ ), UVM_MEDIUM)
+
+ `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"),
+ UVM_MEDIUM)
+ csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture));
+
+ low_power_hint = 1'b1;
+ update_control_csr();
+
+ wait_for_csr_to_propagate_to_slow_domain();
+ set_nvms_idle();
+
+ // This will send the wakeup and trigger low power entry so they almost coincide.
+ fork
+ begin
+ cfg.clk_rst_vif.wait_clks(cycles_before_transition);
+ // Initiate low power transition.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b1);
+ end
+ begin
+ cfg.clk_rst_vif.wait_clks(cycles_before_early_wakeup);
+ // Send the wakeups.
+ cfg.pwrmgr_vif.update_wakeups(wakeups);
+ end
+ join
+
+ if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin
+ wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry);
+ end
+
+ // Now bring it back.
+ cfg.clk_rst_vif.wait_clks(cycles_before_wakeup);
+
+ // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset.
+ // This read will not work in the chip, since the processor will be asleep.
+ cfg.slow_clk_rst_vif.wait_clks(4);
+ check_wake_status(wakeups & wakeups_en);
+ `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", wakeups & wakeups_en), UVM_MEDIUM)
+ wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1);
+
+ // Send more wakeups to make sure they are reported in CSRs. With this all enabled
+ // wakeups should be registered.
+ cfg.pwrmgr_vif.update_wakeups('1);
+
+ wait_for_fast_fsm_active();
+ `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM)
+
+ // make this check parallel.
+ // to avoid csr rd blocking later status read request and
+ // miss status update window.
+ @cfg.clk_rst_vif.cb;
+ fork
+ begin
+ fast_check_reset_status(0);
+ end
+ begin
+ fast_check_wake_info(.reasons(wakeups_en), .prior_reasons(prior_reasons),
+ .fall_through(1'b0), .abort(1'b0),
+ .prior_fall_through(prior_fall_through), .prior_abort(prior_abort));
+ end
+ join
+ // This is the expected side-effect of the low power entry reset, since the source of the
+ // non-aon wakeup sources will deassert it as a consequence of their reset.
+ // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups
+ // will remain active, preventing the device from going to sleep.
+ cfg.pwrmgr_vif.update_wakeups('0);
+ cfg.slow_clk_rst_vif.wait_clks(10);
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b0);
+
+ // wait for clock is on
+ cfg.clk_rst_vif.wait_clks(10);
+
+ check_wake_status('0);
+
+ // Wait for interrupt to be generated whether or not it is enabled.
+ cfg.slow_clk_rst_vif.wait_clks(10);
+ check_and_clear_interrupt(.expected(1'b1));
+ end
+ clear_wake_info();
+ endtask
+
+endclass : pwrmgr_lowpower_wakeup_race_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv
new file mode 100644
index 0000000..175862d
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv
@@ -0,0 +1,91 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Description:
+// The wakeup_reset test randomly enables wakeups and resets, info capture, and interrupts,
+// and sends wakeups and resets in close temporal proximity at random times.
+class pwrmgr_repeat_wakeup_reset_vseq extends pwrmgr_wakeup_reset_vseq;
+ `uvm_object_utils(pwrmgr_repeat_wakeup_reset_vseq)
+
+ `uvm_object_new
+
+ bit [lc_ctrl_pkg::TxWidth-1:0] bad_lc_tx;
+
+ int cycles_from_reset;
+ int micros_to_release;
+
+ bit super_sequence_done;
+
+ // add invalid value to rom_ctrl
+ virtual task twirl_rom_response();
+ add_rom_rsp_noise();
+ cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4False;
+ cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False;
+ cfg.clk_rst_vif.wait_clks(5);
+ add_rom_rsp_noise();
+ wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone);
+ add_rom_rsp_noise();
+ cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True;
+ cfg.clk_rst_vif.wait_clks(5);
+ cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True;
+ endtask
+
+ task body();
+ num_trans_c.constraint_mode(0);
+ num_trans = 50;
+ super_sequence_done = 0;
+
+ disable_assert();
+ fork
+ begin
+ super.body();
+ super_sequence_done = 1;
+ end
+ drv_stim(mubi_mode);
+ join
+ endtask : body
+
+ function void disable_assert();
+ $assertoff(0, "tb.dut.u_cdc.u_sync_rom_ctrl");
+ endfunction : disable_assert
+
+ task drv_stim(pwrmgr_mubi_e mubi_mode);
+ if (mubi_mode == PwrmgrMubiLcCtrl) drv_lc_ctrl();
+ endtask : drv_stim
+
+ task drv_lc_ctrl();
+ int delay;
+
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(cycles_from_reset, {cycles_from_reset inside {[2 : 8]};})
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(micros_to_release, {micros_to_release inside {[2 : 4]};})
+
+ repeat (50) begin
+ wait(cfg.esc_clk_rst_vif.rst_n);
+ cfg.clk_rst_vif.wait_clks(cycles_from_reset);
+ if (super_sequence_done) break;
+ `uvm_info(`gfn, "Injection to lc_hw_debug_en", UVM_MEDIUM)
+ cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val(
+ .t_weight(1), .f_weight(1), .other_weight(2)
+ );
+ #(micros_to_release * 1us);
+ `uvm_info(`gfn, "Injection to lc_dft_en", UVM_MEDIUM)
+ if (super_sequence_done) break;
+ cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(2));
+ #(micros_to_release * 1us);
+ end // repeat (50)
+ `uvm_info(`gfn, "ended drv_lc_ctrl", UVM_MEDIUM)
+ endtask : drv_lc_ctrl
+
+endclass : pwrmgr_repeat_wakeup_reset_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv
new file mode 100644
index 0000000..737d45e
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv
@@ -0,0 +1,141 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// The test to create transition to invalid state from any reset transitions.
+class pwrmgr_reset_invalid_vseq extends pwrmgr_base_vseq;
+
+ `uvm_object_utils(pwrmgr_reset_invalid_vseq)
+ `uvm_object_new
+
+ // Create enum to map rtl local sparse state
+ // to continuous dv state.
+ typedef enum bit [3:0] {
+ DVWaitDisClks = 0,
+ DVWaitNvmShutDown = 1,
+ DVWaitResetPrep = 2,
+ DVWaitLowPower = 3,
+ DVWaitEnableClocks = 4,
+ DVWaitReleaseLcRst = 5,
+ DVWaitOtpInit = 6,
+ DVWaitLcInit = 7,
+ DVWaitAckPwrUp = 8,
+ DVWaitRomCheck = 9,
+ DVWaitStrap = 10,
+ DVWaitActive = 11,
+ DVWaitInvalid = 12
+ } reset_index_e;
+
+ constraint wakeups_c {wakeups == 0;}
+ constraint wakeups_en_c {wakeups_en == 0;}
+
+ function void post_randomize();
+ sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4));
+ super.post_randomize();
+ endfunction
+
+ task body();
+ reset_index_e reset_index;
+ resets_t enabled_resets;
+ string path = "tb.dut.u_fsm.fsm_invalid_i";
+ int num_of_target_states = 11;
+
+ wait_for_fast_fsm_active();
+ check_reset_status('0);
+ $assertoff(0, "tb.dut.u_cdc.u_clr_reqack.SyncReqAckHoldReq");
+
+ for (int i = 0; i < num_of_target_states; ++i) begin
+ `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM)
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ setup_interrupt(.enable(en_intr));
+
+ fork
+ create_any_reset_event();
+ begin
+ int wait_time_ns = 10000;
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == dv2rtl_st(reset_index));, $sformatf(
+ "Timed out waiting for state %s", reset_index.name), wait_time_ns)
+
+ @cfg.clk_rst_vif.cbn;
+ `uvm_info(`gfn, $sformatf("Will cause invalid state forcing %s = 1", path), UVM_MEDIUM)
+ `DV_CHECK(uvm_hdl_force(path, 1))
+ @cfg.clk_rst_vif.cb;
+ end
+ join
+ @cfg.clk_rst_vif.cb;
+ `DV_CHECK(uvm_hdl_release(path))
+ `DV_CHECK(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateInvalid)
+ `uvm_info(`gfn, "All good, resetting for next round", UVM_MEDIUM)
+ repeat (10) @cfg.clk_rst_vif.cb;
+ apply_reset();
+ reset_index++;
+ wait_for_fast_fsm_active();
+ end
+ endtask
+
+ task create_any_reset_event();
+ resets_t enabled_resets = resets_en & resets;
+ `uvm_info(`gfn, $sformatf(
+ "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b",
+ enabled_resets,
+ power_glitch_reset,
+ escalation_reset,
+ sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True,
+ ndm_reset
+ ), UVM_MEDIUM)
+
+ `uvm_info(`gfn, "Trying to write to reset_en CSR", UVM_MEDIUM)
+ csr_wr(.ptr(ral.reset_en[0]), .value(resets_en));
+ // This is necessary to propagate reset_en.
+ wait_for_csr_to_propagate_to_slow_domain();
+
+ // Trigger resets. The glitch is sent prior to the externals since if it is delayed
+ // it will cause a separate reset after the externals, which complicates the checks.
+ if (power_glitch_reset) send_power_glitch();
+ cfg.clk_rst_vif.wait_clks(cycles_before_reset);
+
+ if (cycles_before_reset == 0) enabled_resets = 0;
+
+ `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM)
+ cfg.pwrmgr_vif.update_resets(resets);
+ `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM)
+ if (escalation_reset) send_escalation_reset();
+ if (ndm_reset) send_ndm_reset();
+ cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr);
+
+ endtask : create_any_reset_event
+
+ function pwrmgr_pkg::fast_pwr_state_e dv2rtl_st(reset_index_e idx);
+ case (idx)
+ DVWaitDisClks: return pwrmgr_pkg::FastPwrStateDisClks;
+ DVWaitNvmShutDown: return pwrmgr_pkg::FastPwrStateNvmShutDown;
+ DVWaitResetPrep: return pwrmgr_pkg::FastPwrStateResetPrep;
+ DVWaitLowPower: return pwrmgr_pkg::FastPwrStateLowPower;
+ DVWaitEnableClocks: return pwrmgr_pkg::FastPwrStateEnableClocks;
+ DVWaitReleaseLcRst: return pwrmgr_pkg::FastPwrStateReleaseLcRst;
+ DVWaitOtpInit: return pwrmgr_pkg::FastPwrStateOtpInit;
+ DVWaitLcInit: return pwrmgr_pkg::FastPwrStateLcInit;
+ DVWaitAckPwrUp: return pwrmgr_pkg::FastPwrStateAckPwrUp;
+ DVWaitRomCheck: return pwrmgr_pkg::FastPwrStateRomCheckDone;
+ DVWaitStrap: return pwrmgr_pkg::FastPwrStateStrap;
+ DVWaitActive: return pwrmgr_pkg::FastPwrStateActive;
+ DVWaitInvalid: return pwrmgr_pkg::FastPwrStateInvalid;
+ default: begin
+ `uvm_error("dv2rma_st", $sformatf("unknown index:%0d", idx))
+ end
+ endcase
+ endfunction : dv2rtl_st
+
+endclass : pwrmgr_reset_invalid_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv
new file mode 100644
index 0000000..2c4320a
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv
@@ -0,0 +1,89 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// The reset test randomly introduces external resets, ndm resets, power glitches, and escalation
+// resets.
+class pwrmgr_reset_vseq extends pwrmgr_base_vseq;
+
+ `uvm_object_utils(pwrmgr_reset_vseq)
+ `uvm_object_new
+
+ constraint wakeups_c {wakeups == 0;}
+ constraint wakeups_en_c {wakeups_en == 0;}
+
+ function void post_randomize();
+ sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4));
+ super.post_randomize();
+ endfunction
+
+ task body();
+ logic [TL_DW-1:0] value;
+ resets_t enabled_resets;
+ wait_for_fast_fsm_active();
+
+ check_reset_status('0);
+ for (int i = 0; i < num_trans; ++i) begin
+ `uvm_info(`gfn, "Starting new round", UVM_MEDIUM)
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ setup_interrupt(.enable(en_intr));
+ enabled_resets = resets_en & resets;
+ `uvm_info(`gfn, $sformatf(
+ "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b",
+ enabled_resets,
+ power_glitch_reset,
+ escalation_reset,
+ sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True,
+ ndm_reset
+ ), UVM_MEDIUM)
+
+ csr_wr(.ptr(ral.reset_en[0]), .value(resets_en));
+ // This is necessary to propagate reset_en.
+ wait_for_csr_to_propagate_to_slow_domain();
+
+ // Trigger resets. The glitch is sent prior to the externals since if it is delayed
+ // it will cause a separate reset after the externals, which complicates the checks.
+ if (power_glitch_reset) send_power_glitch();
+ cfg.clk_rst_vif.wait_clks(cycles_before_reset);
+
+ `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM)
+ cfg.pwrmgr_vif.update_resets(resets);
+ `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM)
+ if (escalation_reset) begin
+ send_escalation_reset();
+ // Wait for the alert to propagate to fault_status?
+ end
+ cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr);
+ if (ndm_reset) send_ndm_reset();
+
+ // Expect to start reset.
+ `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive)
+ `uvm_info(`gfn, "Started to process reset", UVM_MEDIUM)
+
+ wait_for_fast_fsm_active();
+ `uvm_info(`gfn, "Back from reset", UVM_MEDIUM)
+
+ check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0));
+
+ cfg.slow_clk_rst_vif.wait_clks(4);
+ check_reset_status('0);
+
+ // And check interrupt is not set.
+ check_and_clear_interrupt(.expected(1'b0));
+ end
+ clear_wake_info();
+ endtask
+
+endclass : pwrmgr_reset_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv
new file mode 100644
index 0000000..2f77235
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv
@@ -0,0 +1,50 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Decription:
+// Create low power transition and wakeup a few times.
+// When PWRMGR.CONTROL.LOW_POWER_HINT is set,
+// issue random write to PWRMGR.CONTROL and check
+// PWRMGR.CONTROL value is not changed.
+class pwrmgr_sec_cm_ctrl_config_regwen_vseq extends pwrmgr_wakeup_vseq;
+ `uvm_object_utils(pwrmgr_sec_cm_ctrl_config_regwen_vseq)
+
+ `uvm_object_new
+
+ virtual task pre_start();
+ super.pre_start();
+ cfg.disable_csr_rd_chk = 1;
+ endtask : pre_start
+
+ task proc_illegal_ctrl_access();
+ uvm_reg_data_t wdata, expdata;
+ cfg.clk_rst_vif.wait_clks(1);
+ wait(cfg.pwrmgr_vif.lowpwr_cfg_wen == 0);
+
+ repeat ($urandom_range(1, 5)) begin
+ `DV_CHECK_STD_RANDOMIZE_FATAL(wdata)
+ expdata = ral.control.get();
+ `uvm_info(`gfn, $sformatf("csr start %x", ral.control.get()), UVM_HIGH)
+ csr_wr(.ptr(ral.control), .value(wdata));
+ csr_rd_check(.ptr(ral.control), .compare_value(expdata));
+ `uvm_info(`gfn, "csr done", UVM_HIGH)
+ end
+ endtask : proc_illegal_ctrl_access
+
+ virtual task wait_for_csr_to_propagate_to_slow_domain();
+ proc_illegal_ctrl_access();
+ super.wait_for_csr_to_propagate_to_slow_domain();
+ endtask
+endclass : pwrmgr_sec_cm_ctrl_config_regwen_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv
new file mode 100644
index 0000000..441b117
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv
@@ -0,0 +1,102 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// The smoke test brings the pwrmgr through a POR reset, followed by a low
+// power sequence, followed by reset.
+
+// smoke test vseq
+class pwrmgr_smoke_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_smoke_vseq)
+
+ `uvm_object_new
+ constraint cycles_before_rst_lc_src_c {cycles_before_rst_lc_src inside {[1 : 2]};}
+ constraint cycles_before_otp_done_c {cycles_before_otp_done inside {[1 : 2]};}
+ constraint cycles_before_lc_done_c {cycles_before_lc_done inside {[1 : 2]};}
+
+ constraint wakeups_c {wakeups != 0;}
+ constraint resets_c {resets != 0;}
+
+ constraint control_enables_c {
+ control_enables.core_clk_en == ral.control.core_clk_en.get_reset();
+ control_enables.io_clk_en == ral.control.io_clk_en.get_reset();
+ control_enables.usb_clk_en_lp == ral.control.usb_clk_en_lp.get_reset();
+ control_enables.usb_clk_en_active == ral.control.usb_clk_en_active.get_reset();
+ control_enables.main_pd_n == ral.control.main_pd_n.get_reset();
+ }
+
+ task body();
+ logic [TL_DW-1:0] value;
+ wakeups_t wakeup_en;
+ resets_t reset_en;
+ wait_for_fast_fsm_active();
+ set_nvms_idle();
+ setup_interrupt(.enable(1'b1));
+
+ check_wake_status('0);
+ check_reset_status('0);
+
+ // Enable all wakeups so any peripheral can cause a wakeup.
+ wakeup_en = '1;
+ csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeup_en));
+ low_power_hint = 1'b1;
+ update_control_csr();
+ wait_for_csr_to_propagate_to_slow_domain();
+
+ // Initiate low power transition.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b1);
+ wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry);
+
+ // Now bring it back.
+ cfg.clk_rst_vif.wait_clks(cycles_before_wakeup);
+ cfg.pwrmgr_vif.update_wakeups(wakeups);
+
+ wait_for_fast_fsm_active();
+ `uvm_info(`gfn, "smoke back from wakeup", UVM_MEDIUM)
+
+ check_wake_status(wakeups & wakeup_en);
+ check_reset_status('0);
+ // And make the cpu active.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b0);
+
+ cfg.pwrmgr_vif.update_wakeups('0);
+ check_and_clear_interrupt(.expected(1'b1));
+
+ // Enable resets.
+ reset_en = '1;
+ csr_wr(.ptr(ral.reset_en[0]), .value(reset_en));
+ wait_for_csr_to_propagate_to_slow_domain();
+
+ // Trigger a reset.
+ cfg.pwrmgr_vif.update_resets(resets);
+ cfg.slow_clk_rst_vif.wait_clks(2);
+ wait_for_reset_cause(pwrmgr_pkg::HwReq);
+
+ // Now bring it back: the slow fsm doesn't participate on this, so we cannot
+ // rely on the ctrl_cfg_regwen CSR. Wait for the reset status to clear.
+ wait_for_fast_fsm_active();
+
+ // The reset_status CSR should be clear since the unit requesting reset
+ // should have been reset, so the incoming reset should have cleared.
+ check_reset_status('0);
+ check_wake_status('0);
+ clear_wake_info();
+
+ // Wait for interrupt to be generated whether or not it is enabled.
+ cfg.slow_clk_rst_vif.wait_clks(10);
+ check_and_clear_interrupt(.expected(1'b0));
+ endtask
+
+endclass : pwrmgr_smoke_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv
new file mode 100644
index 0000000..cdd9394
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv
@@ -0,0 +1,54 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// combine all pwrmgr seqs (except below seqs) in one seq to run sequentially
+// 1. csr seq, which requires scb to be disabled
+class pwrmgr_stress_all_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_stress_all_vseq)
+
+ `uvm_object_new
+
+ task body();
+ string seq_names[] = {
+ "pwrmgr_aborted_low_power_vseq",
+ "pwrmgr_lowpower_wakeup_race_vseq",
+ "pwrmgr_reset_vseq",
+ "pwrmgr_smoke_vseq",
+ "pwrmgr_wakeup_reset_vseq",
+ "pwrmgr_wakeup_vseq"
+ };
+
+ for (int i = 1; i <= num_trans; i++) begin
+ uvm_sequence seq;
+ pwrmgr_base_vseq pwrmgr_vseq;
+ uint seq_idx = $urandom_range(0, seq_names.size - 1);
+
+ seq = create_seq_by_name(seq_names[seq_idx]);
+ `downcast(pwrmgr_vseq, seq)
+
+ pwrmgr_vseq.do_apply_reset = 1;
+ pwrmgr_vseq.set_sequencer(p_sequencer);
+ `DV_CHECK_RANDOMIZE_FATAL(pwrmgr_vseq)
+ `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, pwrmgr_vseq.get_name()),
+ UVM_MEDIUM)
+
+ pwrmgr_vseq.start(p_sequencer);
+ `uvm_info(`gfn, $sformatf(
+ "End of sequence %0s with seq_idx = %0d", pwrmgr_vseq.get_name(), seq_idx),
+ UVM_MEDIUM)
+ end
+ endtask : body
+endclass
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv
new file mode 100644
index 0000000..dfe8e2f
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv
@@ -0,0 +1,66 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Description:
+// The reset test randomly introduces external resets.
+class pwrmgr_sw_reset_vseq extends pwrmgr_base_vseq;
+
+ `uvm_object_utils(pwrmgr_sw_reset_vseq)
+ `uvm_object_new
+
+ constraint wakeups_c {wakeups == 0;}
+ constraint wakeups_en_c {wakeups_en == 0;}
+
+ task body();
+ int exp_rst;
+ wait_for_fast_fsm_active();
+
+ check_reset_status('0);
+ num_trans_c.constraint_mode(0);
+ num_trans = 30;
+ for (int i = 0; i < num_trans; ++i) begin
+ `uvm_info(`gfn, "Starting new round", UVM_MEDIUM)
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ setup_interrupt(.enable(en_intr));
+
+ cfg.pwrmgr_vif.sw_rst_req_i = $urandom_range(0, 15);
+ exp_rst = (cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True);
+ cfg.slow_clk_rst_vif.wait_clks(4);
+
+ // sw reset causes fast state machine transition to lowpower state
+ if (exp_rst == 1) begin
+ `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive);,
+ "timeout waiting for non fast-active state", 1000)
+ end
+
+ // This read is not always possible since the CPU may be off.
+
+ wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1);
+
+ wait_for_fast_fsm_active();
+ `uvm_info(`gfn, "Back from reset", UVM_MEDIUM)
+
+ check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0));
+
+ cfg.slow_clk_rst_vif.wait_clks(4);
+ check_reset_status('0);
+
+ // And check interrupt is not set.
+ check_and_clear_interrupt(.expected(1'b0));
+ end
+ clear_wake_info();
+ endtask
+
+endclass : pwrmgr_sw_reset_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv
new file mode 100644
index 0000000..b24ced5
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv
@@ -0,0 +1,34 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+`include "pwrmgr_base_vseq.sv"
+`include "pwrmgr_aborted_low_power_vseq.sv"
+`include "pwrmgr_lowpower_wakeup_race_vseq.sv"
+`include "pwrmgr_reset_vseq.sv"
+`include "pwrmgr_smoke_vseq.sv"
+`include "pwrmgr_stress_all_vseq.sv"
+`include "pwrmgr_wakeup_reset_vseq.sv"
+`include "pwrmgr_wakeup_vseq.sv"
+`include "pwrmgr_common_vseq.sv"
+`include "pwrmgr_repeat_wakeup_reset_vseq.sv"
+`include "pwrmgr_sw_reset_vseq.sv"
+`include "pwrmgr_esc_clk_rst_malfunc_vseq.sv"
+`include "pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv"
+`include "pwrmgr_global_esc_vseq.sv"
+`include "pwrmgr_glitch_vseq.sv"
+`include "pwrmgr_disable_rom_integrity_check_vseq.sv"
+`include "pwrmgr_reset_invalid_vseq.sv"
+`include "pwrmgr_lowpower_invalid_vseq.sv"
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv
new file mode 100644
index 0000000..4a446e3
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv
@@ -0,0 +1,183 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// The wakeup_reset test randomly enables wakeups and resets, info capture, and interrupts,
+// and sends wakeups and resets in close temporal proximity at random times.
+// Notice it makes no sense to send escalation reset requests while in low
+// power, when the clocks are stopped, or while the system is already in reset
+// since escalation should not be triggered with reset active.
+class pwrmgr_wakeup_reset_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_wakeup_reset_vseq)
+
+ `uvm_object_new
+
+ constraint wakeups_c {wakeups != 0;}
+
+ constraint wakeup_en_c {
+ solve wakeups before wakeups_en;
+ (wakeups_en & wakeups) != 0;
+ }
+ constraint disable_wakeup_capture_c {disable_wakeup_capture == 1'b0;}
+
+ // Disabling escalation resets per comment above.
+ constraint escalation_reset_c {escalation_reset == 0;}
+
+ // Cause some delays for the rom_ctrl done and good inputs. Simple, enough to hold the
+ // transition to active state.
+ // Consider adding SVA to monitor fast state transitions are compliant
+ // with "ROM Integrity Checks" at
+ // https://docs.opentitan.org/hw/ip/pwrmgr/doc/#fast-clock-domain-fsm
+ // TODO(maturana) https://github.com/lowRISC/opentitan/issues/10241
+ virtual task twirl_rom_response();
+ cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4False;
+ cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False;
+ @(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateAckPwrUp);
+ cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True;
+ @(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone);
+ cfg.clk_rst_vif.wait_clks(10);
+ cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False;
+ cfg.clk_rst_vif.wait_clks(5);
+ cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True;
+ cfg.clk_rst_vif.wait_clks(5);
+ cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True;
+ endtask
+
+ task body();
+ logic [TL_DW-1:0] value;
+ resets_t enabled_resets;
+ wakeups_t enabled_wakeups;
+
+ wait_for_fast_fsm_active();
+
+ check_reset_status('0);
+ check_wake_status('0);
+ for (int i = 0; i < num_trans; ++i) begin
+ `uvm_info(`gfn, "Starting new round", UVM_MEDIUM)
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ setup_interrupt(.enable(en_intr));
+
+ // Enable resets.
+ enabled_resets = resets_en & resets;
+ `uvm_info(`gfn, $sformatf(
+ "Enabled resets=0x%x, power_reset=%b, sw_reset=%b",
+ enabled_resets,
+ power_glitch_reset,
+ sw_rst_from_rstmgr
+ ), UVM_MEDIUM)
+ csr_wr(.ptr(ral.reset_en[0]), .value(resets_en));
+
+ // Enable wakeups.
+ enabled_wakeups = wakeups_en & wakeups;
+ `DV_CHECK(enabled_wakeups, $sformatf(
+ "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en))
+ `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM)
+ csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en));
+
+ clear_wake_info();
+
+ `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"),
+ UVM_MEDIUM)
+ csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture));
+
+ low_power_hint = 1'b1;
+ update_control_csr();
+ wait_for_csr_to_propagate_to_slow_domain();
+
+ // Initiate low power transition.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b1);
+ set_nvms_idle();
+ // Wait for the slow state machine to be in low power.
+ wait(cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateLowPower);
+ // This will send the wakeup and reset so they almost coincide.
+ // at low power state, do not use clk_rst_vif, cause it is off.
+ fork
+ begin
+ cfg.aon_clk_rst_vif.wait_clks(cycles_before_reset);
+ cfg.pwrmgr_vif.update_resets(resets);
+
+ if (power_glitch_reset) begin
+ send_power_glitch();
+ enabled_resets = 0;
+ end
+ `uvm_info(`gfn, $sformatf("Sending reset=%b, power_glitch=%b", resets, power_glitch_reset
+ ), UVM_MEDIUM)
+ end
+
+ begin
+ cfg.aon_clk_rst_vif.wait_clks(cycles_before_wakeup);
+ cfg.pwrmgr_vif.update_wakeups(wakeups);
+ `uvm_info(`gfn, $sformatf("Sending wakeup=%b", wakeups), UVM_MEDIUM)
+ end
+ join
+
+ if (cfg.en_cov) begin
+ cov.reset_wakeup_distance_cg.sample(cycles_before_reset - cycles_before_wakeup);
+ end
+ // twirl_rom_response has some waits, and so does the code to check wake_status,
+ // so we fork them to avoid conflicts.
+
+ fork
+ begin
+ // At lowpower state, wait for clock comes back before check any csr
+ @cfg.clk_rst_vif.cb;
+ // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset.
+ // This read will not work in the chip, since the processor will be asleep.
+ // Reset status cannot be reliably checked here since it is cleared when reset goes active.
+ fast_check_wake_status(enabled_wakeups);
+ `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", enabled_wakeups), UVM_MEDIUM)
+ end
+ twirl_rom_response();
+ join
+
+ wait_for_fast_fsm_active();
+
+ check_reset_status('0);
+
+ check_wake_info(.reasons(enabled_wakeups), .prior_reasons(1'b0), .fall_through(1'b0),
+ .prior_fall_through(1'b0), .abort(1'b0), .prior_abort(1'b0));
+
+ if (mubi_mode == PwrmgrMubiRomCtrl) begin
+ add_rom_rsp_noise();
+ cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True;
+ cfg.clk_rst_vif.wait_clks(5);
+ cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True;
+ end
+
+ // This is the expected side-effect of the low power entry reset, since the source of the
+ // non-aon wakeup sources will deassert it as a consequence of their reset.
+ // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups
+ // will remain active, preventing the device from going to sleep.
+ cfg.pwrmgr_vif.update_wakeups('0);
+ cfg.slow_clk_rst_vif.wait_clks(10);
+ check_reset_status('0);
+ check_wake_status('0);
+
+ cfg.slow_clk_rst_vif.wait_clks(10);
+ // An interrupt will be generated depending on the exact timing of the slow fsm getting
+ // the reset and wakeup. We choose not to predict it here (it is checked on other tests).
+ // Instead, we just check if the interrupt status is asserted and it is enabled the
+ // output interrupt is active.
+ check_and_clear_interrupt(.expected(1'b1), .check_expected('0));
+ // Clear hardware resets: if they are enabled they are cleared when rst_lc_req[1] goes active,
+ // but this makes sure they are cleared even if none is enabled for the next round.
+ cfg.pwrmgr_vif.update_resets('0);
+ // And make the cpu active.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b0);
+ end
+ clear_wake_info();
+ endtask
+
+endclass : pwrmgr_wakeup_reset_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv
new file mode 100644
index 0000000..6f0d57c
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv
@@ -0,0 +1,138 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// The wakeup test randomly enables wakeups, info capture, and interrupts,
+// and sends wakeups at random times.
+class pwrmgr_wakeup_vseq extends pwrmgr_base_vseq;
+ `uvm_object_utils(pwrmgr_wakeup_vseq)
+
+ `uvm_object_new
+
+ constraint wakeups_c {wakeups != 0;}
+
+ rand bit keep_prior_wake_info;
+
+ constraint wakeup_en_c {
+ solve wakeups before wakeups_en;
+ |(wakeups_en & wakeups) == 1'b1;
+ }
+
+ task body();
+ logic [TL_DW-1:0] value;
+ wakeups_t enabled_wakeups;
+ wakeups_t prior_reasons = '0;
+ bit prior_fall_through = '0;
+ bit prior_abort = '0;
+
+ wait_for_fast_fsm_active();
+ check_wake_status('0);
+ for (int i = 0; i < num_trans; ++i) begin
+ `uvm_info(`gfn, "Starting new round", UVM_MEDIUM)
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+
+ // Instrument interrupts.
+ setup_interrupt(en_intr);
+
+ // Enable wakeups.
+ enabled_wakeups = wakeups_en & wakeups;
+ `DV_CHECK(enabled_wakeups, $sformatf(
+ "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en))
+ `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM)
+ csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en));
+
+ if (keep_prior_wake_info) begin
+ csr_rd(.ptr(ral.wake_info.reasons), .value(prior_reasons));
+ csr_rd(.ptr(ral.wake_info.fall_through), .value(prior_fall_through));
+ csr_rd(.ptr(ral.wake_info.abort), .value(prior_abort));
+ end else begin
+ clear_wake_info();
+ prior_reasons = '0;
+ prior_fall_through = '0;
+ prior_abort = '0;
+ end
+ `uvm_info(`gfn, $sformatf(
+ "Prior wake_info: reasons=0x%x, fall_through=%b, abort=%b",
+ prior_reasons,
+ prior_fall_through,
+ prior_abort
+ ), UVM_MEDIUM)
+
+ `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"),
+ UVM_MEDIUM)
+ csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture));
+
+ low_power_hint = 1'b1;
+ update_control_csr();
+
+ wait_for_csr_to_propagate_to_slow_domain();
+
+ // Initiate low power transition.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b1);
+ set_nvms_idle();
+
+ if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin
+ wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry);
+ end
+
+ // Now bring it back.
+ cfg.clk_rst_vif.wait_clks(cycles_before_wakeup);
+ cfg.pwrmgr_vif.update_wakeups(wakeups);
+ // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset.
+ // This read will not work in the chip, since the processor will be asleep.
+ cfg.slow_clk_rst_vif.wait_clks(4);
+ // wait for clock is on
+ cfg.clk_rst_vif.wait_clks(10);
+
+ check_wake_status(enabled_wakeups);
+ `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", enabled_wakeups), UVM_MEDIUM)
+ wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1);
+
+ wait_for_fast_fsm_active();
+ `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM)
+
+ @cfg.clk_rst_vif.cb;
+ fork
+ begin
+ fast_check_reset_status(0);
+ end
+ begin
+ fast_check_wake_info(.reasons(enabled_wakeups), .prior_reasons(prior_reasons),
+ .fall_through(1'b0), .abort(1'b0),
+ .prior_fall_through(prior_fall_through), .prior_abort(prior_abort));
+ end
+ join
+ // This is the expected side-effect of the low power entry reset, since the source of the
+ // non-aon wakeup sources will deassert it as a consequence of their reset.
+ // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups
+ // will remain active, preventing the device from going to sleep.
+ cfg.pwrmgr_vif.update_wakeups('0);
+ cfg.slow_clk_rst_vif.wait_clks(10);
+
+ // if clock is off, we need to wait until it is resumed.
+ cfg.clk_rst_vif.wait_clks(5);
+ check_wake_status('0);
+
+ // And make the cpu active.
+ cfg.pwrmgr_vif.update_cpu_sleeping(1'b0);
+
+ // Wait for interrupt to be generated whether or not it is enabled.
+ cfg.slow_clk_rst_vif.wait_clks(10);
+ check_and_clear_interrupt(.expected(1'b1));
+ end
+ clear_wake_info();
+ endtask
+
+endclass : pwrmgr_wakeup_vseq
diff --git a/hw/top_sencha/ip/pwrmgr/dv/pwrmgr_sim.core b/hw/top_sencha/ip/pwrmgr/dv/pwrmgr_sim.core
new file mode 100644
index 0000000..8e0cf49
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/pwrmgr_sim.core
@@ -0,0 +1,30 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:dv:pwrmgr_sim:0.1"
+description: "PWRMGR DV sim target"
+filesets:
+ files_rtl:
+ depend:
+ - google:systems:pwrmgr
+ files_dv:
+ depend:
+ - google:dv:pwrmgr_test
+ - google:dv:pwrmgr_sva
+ files:
+ - tb.sv
+ - cov/pwrmgr_cov_bind.sv
+ file_type: systemVerilogSource
+
+targets:
+ sim: &sim_target
+ toplevel: tb
+ filesets:
+ - files_rtl
+ - files_dv
+ default_tool: vcs
+
+ # TODO: add a lint check cfg in `hw/top_sencha/lint/top_sencha_dv_lint_cfgs.hjson`
+ lint:
+ <<: *sim_target
diff --git a/hw/top_sencha/ip/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_sencha/ip/pwrmgr/dv/pwrmgr_sim_cfg.hjson
new file mode 100644
index 0000000..aef72a3
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/pwrmgr_sim_cfg.hjson
@@ -0,0 +1,156 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Name of the sim cfg - typically same as the name of the DUT.
+ name: pwrmgr
+
+ // Top level dut name (sv module).
+ dut: pwrmgr
+
+ // Top level testbench name (sv module).
+ tb: tb
+
+ // Simulator used to sign off this block
+ tool: vcs
+
+ // Fusesoc core file used for building the file list.
+ fusesoc_core: google:dv:pwrmgr_sim:0.1
+
+ // Testplan hjson file.
+ testplan: "{proj_root}/hw/top_sencha/ip/pwrmgr/data/pwrmgr_testplan.hjson"
+
+ // RAL spec - used to generate the RAL model.
+ ral_spec: "{proj_root}/hw/top_sencha/ip/pwrmgr/data/autogen/pwrmgr.hjson"
+
+ // Import additional common sim cfg files.
+ // TODO: remove imported cfgs that do not apply.
+ import_cfgs: [// Project wide common sim cfg file
+ "{titan_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
+ // Common CIP test lists
+ "{titan_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
+ "{titan_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
+ "{titan_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
+ "{titan_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
+ "{titan_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]
+
+ // Overrides
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+
+ // Exclusion files
+ vcs_cov_excl_files: ["{proj_root}/hw/top_sencha/ip/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el"]
+
+ // Add additional tops for simulation.
+ sim_tops: ["pwrmgr_bind",
+ "pwrmgr_cov_bind",
+ "sec_cm_prim_count_bind",
+ "sec_cm_prim_sparse_fsm_flop_bind",
+ "sec_cm_prim_onehot_check_bind"]
+
+ // Default iterations for all tests - each test entry can override this.
+ reseed: 50
+
+ // Default UVM test and seq class name.
+ uvm_test: pwrmgr_base_test
+ uvm_test_seq: pwrmgr_base_vseq
+
+ // Enable cdc instrumentation.
+ run_opts: ["+cdc_instrumentation_enabled=1"]
+
+ // List of test specifications.
+ tests: [
+ {
+ name: pwrmgr_smoke
+ uvm_test_seq: pwrmgr_smoke_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_reset
+ uvm_test_seq: pwrmgr_reset_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_lowpower_wakeup_race
+ uvm_test_seq: pwrmgr_lowpower_wakeup_race_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_wakeup
+ uvm_test_seq: pwrmgr_wakeup_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_wakeup_reset
+ uvm_test_seq: pwrmgr_wakeup_reset_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_aborted_low_power
+ uvm_test_seq: pwrmgr_aborted_low_power_vseq
+ }
+ {
+ name: pwrmgr_sec_cm_lc_ctrl_intersig_mubi
+ uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq
+ run_opts: ["+test_timeout_ns=2000000", "+pwrmgr_mubi_mode=PwrmgrMubiLcCtrl"]
+ }
+ {
+ name: pwrmgr_sec_cm_rom_ctrl_intersig_mubi
+ uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq
+ run_opts: ["+test_timeout_ns=2000000", "+pwrmgr_mubi_mode=PwrmgrMubiRomCtrl"]
+ }
+ {
+ name: pwrmgr_sec_cm_rstmgr_intersig_mubi
+ uvm_test_seq: pwrmgr_sw_reset_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_esc_clk_rst_malfunc
+ uvm_test_seq: pwrmgr_esc_clk_rst_malfunc_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_sec_cm_ctrl_config_regwen
+ uvm_test_seq: pwrmgr_sec_cm_ctrl_config_regwen_vseq
+ run_opts: ["+test_timeout_ns=50000000"]
+ }
+ {
+ name: pwrmgr_global_esc
+ uvm_test_seq: pwrmgr_global_esc_vseq
+ run_opts: ["+test_timeout_ns=1000000000"]
+ }
+ {
+ name: pwrmgr_glitch
+ uvm_test_seq: pwrmgr_glitch_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_disable_rom_integrity_check
+ uvm_test_seq: pwrmgr_disable_rom_integrity_check_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_reset_invalid
+ uvm_test_seq: pwrmgr_reset_invalid_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ {
+ name: pwrmgr_lowpower_invalid
+ uvm_test_seq: pwrmgr_lowpower_invalid_vseq
+ run_opts: ["+test_timeout_ns=1000000"]
+ }
+ // TODO: add more tests here
+ ]
+
+ // List of regressions.
+ regressions: [
+ {
+ name: smoke
+ tests: ["pwrmgr_smoke"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv
new file mode 100644
index 0000000..29ab343
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv
@@ -0,0 +1,157 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// This has some assertions that check the inputs from ast react according to
+// the pwrmgr outputs. The ast inputs are generated by the base sequences, but
+// these assertions will also be useful at full chip level.
+interface pwrmgr_ast_sva_if #(
+ parameter bit CheckClocks = 1'b0
+) (
+ input logic clk_slow_i,
+ input logic rst_slow_ni,
+ input logic clk_main_i,
+ input logic clk_io_i,
+ input logic clk_usb_i,
+ input logic por_d0_ni,
+ // The pwrmgr outputs.
+ input pwrmgr_pkg::pwr_ast_req_t pwr_ast_o,
+ // The pwrmgr inputs.
+ input pwrmgr_pkg::pwr_ast_rsp_t pwr_ast_i
+);
+
+ // These numbers of cycles are meant to match both the randomization in
+ // pwrmgr_base_vseq, and the actual cycle counts from full chip.
+ // Notice the expectation for full chip is that deassertion of *clk_val
+ // takes 0 cycles, and assertion takes a 2 cycle synchronizer delay on
+ // the slow clock; deassertion of main_pok takes one cycle, and assertion
+ // not more than 2 cycles.
+ localparam int MIN_CLK_WAIT_CYCLES = 0;
+ localparam int MIN_PDN_WAIT_CYCLES = 0;
+ localparam int MAX_CLK_WAIT_CYCLES = 60;
+ localparam int MAX_PDN_WAIT_CYCLES = 110;
+
+ bit disable_sva;
+ bit reset_or_disable;
+
+ always_comb reset_or_disable = !rst_slow_ni || disable_sva;
+
+ `define CLK_WAIT_BOUNDS ##[MIN_CLK_WAIT_CYCLES:MAX_CLK_WAIT_CYCLES]
+ `define PDN_WAIT_BOUNDS ##[MIN_PDN_WAIT_CYCLES:MAX_PDN_WAIT_CYCLES]
+
+ // Clock enable-valid.
+
+ // Changes triggered by por_d0_ni only affect clk_val.
+ `ASSERT(CoreClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:1] !pwr_ast_i.core_clk_val, clk_slow_i,
+ reset_or_disable)
+ `ASSERT(CoreClkGlitchToValOn_A,
+ $rose(por_d0_ni) && pwr_ast_o.core_clk_en |-> ##[0:2] pwr_ast_i.core_clk_val, clk_slow_i,
+ reset_or_disable)
+ `ASSERT(IoClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:1] !pwr_ast_i.io_clk_val, clk_slow_i,
+ reset_or_disable)
+ `ASSERT(IoClkGlitchToValOn_A,
+ $rose(por_d0_ni) && pwr_ast_o.io_clk_en |-> ##[0:2] pwr_ast_i.io_clk_val, clk_slow_i,
+ reset_or_disable)
+ `ASSERT(UsbClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:5] !pwr_ast_i.usb_clk_val, clk_slow_i,
+ reset_or_disable)
+ `ASSERT(UsbClkGlitchToValOn_A,
+ $rose(por_d0_ni) && pwr_ast_o.usb_clk_en |-> ##[0:5] pwr_ast_i.usb_clk_val, clk_slow_i,
+ reset_or_disable)
+
+ // Changes not triggered by por_d0_ni
+ `ASSERT(CoreClkHandshakeOn_A,
+ $rose(pwr_ast_o.core_clk_en) && por_d0_ni |-> `CLK_WAIT_BOUNDS
+ pwr_ast_i.core_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable)
+ `ASSERT(CoreClkHandshakeOff_A,
+ $fell(pwr_ast_o.core_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.core_clk_val, clk_slow_i,
+ reset_or_disable)
+
+ `ASSERT(IoClkHandshakeOn_A,
+ $rose(pwr_ast_o.io_clk_en) && por_d0_ni |-> `CLK_WAIT_BOUNDS
+ pwr_ast_i.io_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable)
+ `ASSERT(IoClkHandshakeOff_A,
+ $fell(pwr_ast_o.io_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.io_clk_val, clk_slow_i,
+ reset_or_disable)
+
+ // Usb is a bit different: apparently usb_clk_val can stay low after a power glitch, so it may
+ // already be low when usb_clk_en drops.
+ `ASSERT(UsbClkHandshakeOn_A,
+ $rose(pwr_ast_o.usb_clk_en) && por_d0_ni && $past(por_d0_ni, 1) |-> `CLK_WAIT_BOUNDS
+ pwr_ast_i.usb_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable)
+ `ASSERT(UsbClkHandshakeOff_A,
+ $fell(pwr_ast_o.usb_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.usb_clk_val, clk_slow_i,
+ reset_or_disable)
+
+ if (CheckClocks) begin : gen_check_clock
+ int main_clk_cycles, io_clk_cycles, usb_clk_cycles;
+ always_ff @(posedge clk_main_i) main_clk_cycles++;
+ always_ff @(posedge clk_io_i) io_clk_cycles++;
+ always_ff @(posedge clk_usb_i) usb_clk_cycles++;
+
+ `ASSERT(MainClkStopped_A,
+ $fell(
+ pwr_ast_i.core_clk_val
+ ) |=> ($stable(
+ main_clk_cycles
+ ) || pwr_ast_i.core_clk_val) [* 1 : $],
+ clk_slow_i, reset_or_disable)
+ `ASSERT(MainClkRun_A,
+ $rose(
+ pwr_ast_i.core_clk_val
+ ) |=> (!$stable(
+ main_clk_cycles
+ ) || !pwr_ast_i.core_clk_val) [* 1 : $],
+ clk_slow_i, reset_or_disable)
+
+ `ASSERT(IOClkStopped_A,
+ $fell(
+ pwr_ast_i.io_clk_val
+ ) |=> ($stable(
+ io_clk_cycles
+ ) || pwr_ast_i.io_clk_val) [* 1 : $],
+ clk_slow_i, reset_or_disable)
+ `ASSERT(IOClkRun_A,
+ $rose(
+ pwr_ast_i.io_clk_val
+ ) |=> (!$stable(
+ io_clk_cycles
+ ) || !pwr_ast_i.io_clk_val) [* 1 : $],
+ clk_slow_i, reset_or_disable)
+
+ `ASSERT(USBClkStopped_A,
+ $fell(
+ pwr_ast_i.usb_clk_val
+ ) |=> ($stable(
+ usb_clk_cycles
+ ) || pwr_ast_i.usb_clk_val) [* 1 : $],
+ clk_slow_i, reset_or_disable)
+ `ASSERT(USBClkRun_A,
+ $rose(
+ pwr_ast_i.usb_clk_val
+ ) |=> (!$stable(
+ usb_clk_cycles
+ ) || !pwr_ast_i.usb_clk_val) [* 1 : $],
+ clk_slow_i, reset_or_disable)
+ end
+
+ // Main pd-pok
+ `ASSERT(MainPdHandshakeOn_A, pwr_ast_o.main_pd_n |-> `PDN_WAIT_BOUNDS pwr_ast_i.main_pok,
+ clk_slow_i, reset_or_disable)
+ `ASSERT(MainPdHandshakeOff_A, !pwr_ast_o.main_pd_n |-> `PDN_WAIT_BOUNDS !pwr_ast_i.main_pok,
+ clk_slow_i, reset_or_disable)
+
+ `undef CLK_WAIT_BOUNDS
+ `undef PDN_WAIT_BOUNDS
+endinterface
diff --git a/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_bind.sv b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_bind.sv
new file mode 100644
index 0000000..b98be86
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_bind.sv
@@ -0,0 +1,96 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module pwrmgr_bind;
+
+ bind pwrmgr tlul_assert #(
+ .EndpointType("Device")
+ ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o));
+
+ // In top-level testbench, do not bind the csr_assert_fpv to reduce simulation time.
+`ifndef TOP_LEVEL_DV
+ bind pwrmgr pwrmgr_csr_assert_fpv pwrmgr_csr_assert (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o));
+`endif
+
+ // Clock control assertions.
+ bind pwrmgr pwrmgr_clock_enables_sva_if pwrmgr_clock_enables_sva_if (
+ .clk_i(clk_slow_i),
+ .rst_ni(rst_slow_ni),
+ .fast_state(u_fsm.state_q),
+ .slow_state(u_slow_fsm.state_q),
+ // The synchronized control CSR bits.
+ .main_pd_ni(slow_main_pd_n),
+ .core_clk_en_i(slow_core_clk_en),
+ .io_clk_en_i(slow_io_clk_en),
+ .usb_clk_en_lp_i(slow_usb_clk_en_lp),
+ .usb_clk_en_active_i(slow_usb_clk_en_active),
+ .usb_ip_clk_status_i(usb_ip_clk_status),
+ // The main power control.
+ .main_pd_n(pwr_ast_o.main_pd_n),
+ // The output enables.
+ .core_clk_en(pwr_ast_o.core_clk_en),
+ .io_clk_en(pwr_ast_o.io_clk_en),
+ .usb_clk_en(pwr_ast_o.usb_clk_en)
+ );
+
+ bind pwrmgr pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_if (
+ .clk_i,
+ .rst_ni,
+ .clk_slow_i,
+ .rst_slow_ni,
+ // The outputs from pwrmgr.
+ .rst_lc_req(pwr_rst_o.rst_lc_req),
+ .rst_sys_req(pwr_rst_o.rst_sys_req),
+ // The inputs from rstmgr.
+ .rst_lc_src_n(pwr_rst_i.rst_lc_src_n),
+ .rst_sys_src_n(pwr_rst_i.rst_sys_src_n)
+ );
+
+ bind pwrmgr clkmgr_pwrmgr_sva_if clkmgr_pwrmgr_sva_if (
+ .clk_i,
+ .rst_ni,
+ .io_clk_en(pwr_clk_o.io_ip_clk_en),
+ .io_status(pwr_clk_i.io_status),
+ .main_clk_en(pwr_clk_o.main_ip_clk_en),
+ .main_status(pwr_clk_i.main_status),
+ .usb_clk_en(pwr_clk_o.usb_ip_clk_en),
+ .usb_status(pwr_clk_i.usb_status)
+ );
+
+ bind pwrmgr pwrmgr_sec_cm_checker_assert pwrmgr_sec_cm_checker_assert (
+ .clk_i,
+ .rst_ni,
+ .clk_lc_i,
+ .rst_lc_ni,
+ .clk_esc_i,
+ .rst_esc_ni,
+ .clk_slow_i,
+ .rst_slow_ni,
+ .rst_main_ni,
+ .pwr_rst_o,
+ .slow_esc_rst_req(slow_peri_reqs.rstreqs[3]),
+ .slow_mp_rst_req(slow_peri_reqs.rstreqs[2]),
+ .slow_fsm_invalid,
+ .fast_fsm_invalid(u_fsm.u_state_regs.unused_err_o),
+ .rom_intg_chk_dis(u_fsm.rom_intg_chk_dis),
+ .rom_intg_chk_ok(prim_mubi_pkg::mubi4_and_hi(u_fsm.rom_intg_chk_done, u_fsm.rom_intg_chk_good)),
+ .lc_dft_en_i,
+ .lc_hw_debug_en_i,
+ .main_pd_ni(u_slow_fsm.main_pd_ni),
+ .rom_ctrl_done_i(u_fsm.rom_ctrl_done_i),
+ .rom_ctrl_good_i(u_fsm.rom_ctrl_good_i)
+ );
+endmodule
diff --git a/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv
new file mode 100644
index 0000000..9e95513
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv
@@ -0,0 +1,71 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// This has some assertions that check that the output clock enables correspond
+// to the control CSR when transitioning into or out of the active state. In
+// addition, the usb clock can change anytime when in the active state.
+interface pwrmgr_clock_enables_sva_if (
+ input logic clk_i,
+ input logic rst_ni,
+ input pwrmgr_pkg::fast_pwr_state_e fast_state,
+ input pwrmgr_pkg::slow_pwr_state_e slow_state,
+ // The synchronized control CSR bits.
+ input logic main_pd_ni,
+ input logic io_clk_en_i,
+ input logic core_clk_en_i,
+ input logic usb_clk_en_lp_i,
+ input logic usb_clk_en_active_i,
+ input logic usb_ip_clk_status_i,
+ // The output enables.
+ input logic main_pd_n,
+ input logic io_clk_en,
+ input logic core_clk_en,
+ input logic usb_clk_en
+);
+
+ bit disable_sva;
+ bit reset_or_disable;
+
+ always_comb reset_or_disable = !rst_ni || disable_sva;
+
+ sequence transitionUp_S; slow_state == pwrmgr_pkg::SlowPwrStateReqPwrUp; endsequence
+
+ sequence transitionDown_S; slow_state == pwrmgr_pkg::SlowPwrStatePwrClampOn; endsequence
+
+ bit fast_is_active;
+ always_comb fast_is_active = fast_state == pwrmgr_pkg::FastPwrStateActive;
+
+ // This allows the usb enable to be slower since it also depends on usb clk_status.
+ sequence usbActiveTransition_S;
+ ##[0:7] !fast_is_active || usb_clk_en == (usb_clk_en_active_i | usb_ip_clk_status_i);
+ endsequence
+
+ `ASSERT(CoreClkPwrUp_A, transitionUp_S |=> core_clk_en == 1'b1, clk_i, reset_or_disable)
+ `ASSERT(IoClkPwrUp_A, transitionUp_S |=> io_clk_en == 1'b1, clk_i, reset_or_disable)
+ `ASSERT(UsbClkPwrUp_A, transitionUp_S |=> usb_clk_en == usb_clk_en_active_i, clk_i,
+ reset_or_disable)
+
+ // This deals with transitions while the fast fsm is active.
+ `ASSERT(UsbClkActive_A, fast_is_active && $changed(usb_clk_en_active_i) |=> usbActiveTransition_S,
+ clk_i, reset_or_disable)
+
+ `ASSERT(CoreClkPwrDown_A, transitionDown_S |=> core_clk_en == (core_clk_en_i && main_pd_ni),
+ clk_i, reset_or_disable)
+ `ASSERT(IoClkPwrDown_A, transitionDown_S |=> io_clk_en == (io_clk_en_i && main_pd_ni), clk_i,
+ reset_or_disable)
+ `ASSERT(UsbClkPwrDown_A, transitionDown_S |=> usb_clk_en == (usb_clk_en_lp_i && main_pd_ni),
+ clk_i, reset_or_disable)
+endinterface
diff --git a/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core
new file mode 100644
index 0000000..7963195
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:pwrmgr_rstmgr_sva_if:0.1"
+description: "PWRMGR to RSTMGR assertion interface."
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:ip:pwrmgr_pkg
+ - lowrisc:prim:assert
+ files:
+ - pwrmgr_rstmgr_sva_if.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv
new file mode 100644
index 0000000..b51a788
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv
@@ -0,0 +1,61 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// This has some assertions that check the inputs from rstmgr react according to
+// the pwrmgr outputs. The rstmgr inputs are generated by the base sequences, but
+// these assertions will also be useful at full chip level.
+interface pwrmgr_rstmgr_sva_if
+ import pwrmgr_pkg::*, pwrmgr_reg_pkg::*;
+(
+ input logic clk_i,
+ input logic rst_ni,
+ input logic clk_slow_i,
+ input logic rst_slow_ni,
+
+ // The inputs from pwrmgr.
+ input logic [PowerDomains-1:0] rst_lc_req,
+ input logic [PowerDomains-1:0] rst_sys_req,
+
+ // The inputs from rstmgr.
+ input logic [PowerDomains-1:0] rst_lc_src_n,
+ input logic [PowerDomains-1:0] rst_sys_src_n
+);
+
+ // Number of cycles for the LC/SYS reset handshake.
+ localparam int MIN_LC_SYS_CYCLES = 0;
+ localparam int MAX_LC_SYS_CYCLES = 150;
+ `define LC_SYS_CYCLES ##[MIN_LC_SYS_CYCLES:MAX_LC_SYS_CYCLES]
+
+ bit disable_sva;
+ bit reset_or_disable;
+
+ always_comb reset_or_disable = !rst_slow_ni || disable_sva;
+
+ // Lc and Sys handshake: pwrmgr rst_*_req causes rstmgr rst_*_src_n
+ for (genvar pd = 0; pd < PowerDomains; ++pd) begin : gen_assertions_per_power_domains
+ `ASSERT(LcHandshakeOn_A, rst_lc_req[pd] |-> `LC_SYS_CYCLES !rst_lc_req[pd] || !rst_lc_src_n[pd],
+ clk_i, reset_or_disable)
+ `ASSERT(LcHandshakeOff_A, $fell(rst_lc_req[pd])
+ |-> `LC_SYS_CYCLES rst_lc_req[pd] || rst_lc_src_n[pd], clk_i, reset_or_disable)
+ `ASSERT(SysHandshakeOn_A,
+ rst_sys_req[pd] |-> `LC_SYS_CYCLES !rst_sys_req[pd] || !rst_sys_src_n[pd], clk_i,
+ reset_or_disable)
+ `ASSERT(SysHandshakeOff_A,
+ !rst_sys_req[pd] |-> `LC_SYS_CYCLES rst_sys_req[pd] || rst_sys_src_n[pd], clk_i,
+ reset_or_disable)
+ end : gen_assertions_per_power_domains
+ `undef LC_SYS_CYCLES
+endinterface
diff --git a/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv
new file mode 100644
index 0000000..a8c552e
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv
@@ -0,0 +1,110 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// This has some assertions that check the pwrmgr rstreqs and reset_cause output is set per the
+// reset requests the pwrmgr receives or generates.
+interface pwrmgr_rstreqs_sva_if
+ import pwrmgr_pkg::*, pwrmgr_reg_pkg::*;
+(
+ input logic clk_i,
+ input logic rst_ni,
+ input logic clk_slow_i,
+ input logic rst_slow_ni,
+
+ // Input causes resets.
+ input logic [ NumRstReqs-1:0] rstreqs_i,
+ input logic [ NumRstReqs-1:0] reset_en,
+ input logic sw_rst_req_i,
+ input logic main_rst_req_i,
+ input logic esc_rst_req_i,
+ input logic ndm_rst_req_i,
+ // outputs
+ input logic main_pd_n,
+ input reset_cause_e reset_cause,
+ input logic [HwResetWidth-1:0] rstreqs
+);
+
+ // output reset cycle with a clk enable disable
+ localparam int MIN_MAIN_RST_CYCLES = 0;
+ localparam int MAX_MAIN_RST_CYCLES = 400;
+ `define MAIN_RST_CYCLES ##[MIN_MAIN_RST_CYCLES:MAX_MAIN_RST_CYCLES]
+
+ // The timing of the escalation reset is determined by the slow clock, but will not propagate if
+ // the non-slow clock is off. We use the regular clock and multiply the clock cycles times the
+ // clock ratio.
+ localparam int FAST_TO_SLOW_FREQ_RATIO = 120;
+
+ localparam int MIN_ESC_RST_CYCLES = 0;
+ localparam int MAX_ESC_RST_CYCLES = 4 * FAST_TO_SLOW_FREQ_RATIO;
+ `define ESC_RST_CYCLES ##[MIN_ESC_RST_CYCLES:MAX_ESC_RST_CYCLES]
+
+ bit disable_sva;
+ bit reset_or_disable;
+
+ always_comb reset_or_disable = !rst_ni || !rst_slow_ni || disable_sva;
+
+ // Reset ins to outs.
+ // TODO: check reset_cause output is set.
+ for (genvar rst = 0; rst < NumRstReqs; ++rst) begin : gen_hw_resets
+ `ASSERT(HwResetOn_A,
+ $rose(
+ rstreqs_i[rst] && reset_en[rst]
+ ) |-> `MAIN_RST_CYCLES rstreqs[rst], clk_slow_i, reset_or_disable)
+ `ASSERT(HwResetOff_A,
+ $fell(
+ rstreqs_i[rst] && reset_en[rst]
+ ) |-> `MAIN_RST_CYCLES !rstreqs[rst], clk_slow_i, reset_or_disable)
+ end
+
+ // This is used to ignore main_rst_req_i (wired to rst_main_n) if it happens during low power,
+ // since as part of deep sleep rst_main_n will trigger and not because of a power glitch.
+ logic rst_main_n_ignored_for_main_pwr_rst;
+ always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin
+ if (!rst_slow_ni) begin
+ rst_main_n_ignored_for_main_pwr_rst <= 0;
+ end else if (!main_pd_n && reset_cause == LowPwrEntry) begin
+ rst_main_n_ignored_for_main_pwr_rst <= 1;
+ end else if (reset_cause != LowPwrEntry) begin
+ rst_main_n_ignored_for_main_pwr_rst <= 0;
+ end
+ end
+
+ `ASSERT(MainPwrRstOn_A,
+ $rose(
+ main_rst_req_i && !rst_main_n_ignored_for_main_pwr_rst
+ ) |-> `MAIN_RST_CYCLES rstreqs[ResetMainPwrIdx], clk_slow_i,
+ reset_or_disable)
+ `ASSERT(MainPwrRstOff_A,
+ $fell(
+ main_rst_req_i
+ ) |-> `MAIN_RST_CYCLES !rstreqs[ResetMainPwrIdx], clk_slow_i,
+ reset_or_disable)
+
+ // Signals in EscRstOn_A and EscRstOff_A are sampled with slow and fast clock.
+ // Since fast clock can be gated, use fast clock to evaluate cycle delay
+ // to avoid spurious failure.
+ `ASSERT(EscRstOn_A,
+ $rose(
+ esc_rst_req_i
+ ) |-> `ESC_RST_CYCLES rstreqs[ResetEscIdx], clk_i, reset_or_disable)
+ `ASSERT(EscRstOff_A,
+ $fell(
+ esc_rst_req_i
+ ) |-> `ESC_RST_CYCLES !rstreqs[ResetEscIdx], clk_i, reset_or_disable)
+
+ // Software initiated resets do not affect rstreqs since rstmgr generate them.
+ // TODO: Check they set reset_cause == HwReq.
+endinterface
diff --git a/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv
new file mode 100644
index 0000000..bb5591e
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv
@@ -0,0 +1,125 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+// add description here TBD
+module pwrmgr_sec_cm_checker_assert
+ import pwrmgr_reg_pkg::*;
+(
+ input clk_i,
+ input rst_ni,
+ input clk_lc_i,
+ input rst_lc_ni,
+ input clk_esc_i,
+ input rst_esc_ni,
+ input rst_main_ni,
+ input clk_slow_i,
+ input rst_slow_ni,
+ input pwrmgr_pkg::pwr_rst_req_t pwr_rst_o,
+ input slow_fsm_invalid,
+ input fast_fsm_invalid,
+ input prim_mubi_pkg::mubi4_t rom_intg_chk_dis,
+ input prim_mubi_pkg::mubi4_t rom_intg_chk_ok,
+ input lc_ctrl_pkg::lc_tx_t lc_dft_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i,
+ input slow_esc_rst_req,
+ input slow_mp_rst_req,
+ input main_pd_ni,
+ input prim_mubi_pkg::mubi4_t rom_ctrl_done_i,
+ input prim_mubi_pkg::mubi4_t rom_ctrl_good_i
+);
+
+ bit disable_sva;
+ bit reset_or_disable;
+ bit esc_reset_or_disable;
+ bit slow_reset_or_disable;
+
+ always_comb reset_or_disable = !rst_ni || disable_sva;
+ always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
+ always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
+
+ `define ASYNC_ASSERT(_name, _prop, _sigs, _rst) \
+ _name: assert property (@(_sigs) disable iff ((_rst) !== '0) (_prop)) \
+ else begin \
+ `ASSERT_ERROR(_name) \
+ end
+
+ // Assuming lc_dft_en_i and lc_hw_debug_en_i are asynchronous
+ // rom_intg_chk_dis only allows two states.
+ `ASYNC_ASSERT(RomIntgChkDisTrue_A,
+ rom_intg_chk_dis == prim_mubi_pkg::MuBi4True |->
+ (lc_dft_en_i == lc_ctrl_pkg::On && lc_hw_debug_en_i == lc_ctrl_pkg::On),
+ (rom_intg_chk_dis | lc_dft_en_i | lc_hw_debug_en_i), reset_or_disable)
+
+ `ASYNC_ASSERT(RomIntgChkDisFalse_A,
+ rom_intg_chk_dis == prim_mubi_pkg::MuBi4False |->
+ (lc_dft_en_i !== lc_ctrl_pkg::On || lc_hw_debug_en_i !== lc_ctrl_pkg::On),
+ (rom_intg_chk_dis | lc_dft_en_i | lc_hw_debug_en_i), reset_or_disable)
+
+ // check rom_intg_chk_ok
+ // rom_ctrl_i go through cdc. So use synchronous assertion.
+ // rom_intg_chk_ok can be any values.
+ `ASYNC_ASSERT(RomIntgChkOkTrue_A,
+ rom_intg_chk_ok == prim_mubi_pkg::MuBi4True |->
+ (rom_intg_chk_dis == prim_mubi_pkg::MuBi4True &&
+ rom_ctrl_done_i == prim_mubi_pkg::MuBi4True) ||
+ (rom_ctrl_done_i == prim_mubi_pkg::MuBi4True &&
+ rom_ctrl_good_i == prim_mubi_pkg::MuBi4True),
+ (rom_intg_chk_ok | rom_intg_chk_dis | rom_ctrl_done_i | rom_ctrl_good_i),
+ reset_or_disable)
+
+ `ASYNC_ASSERT(RomIntgChkOkFalse_A,
+ rom_intg_chk_ok != prim_mubi_pkg::MuBi4True |->
+ (rom_intg_chk_dis == prim_mubi_pkg::MuBi4False ||
+ rom_ctrl_done_i != prim_mubi_pkg::MuBi4True) &&
+ (rom_ctrl_done_i != prim_mubi_pkg::MuBi4True ||
+ rom_ctrl_good_i != prim_mubi_pkg::MuBi4True),
+ (rom_intg_chk_ok | rom_intg_chk_dis | rom_ctrl_done_i | rom_ctrl_good_i),
+ reset_or_disable)
+
+ `undef ASYNC_ASSERT
+
+ // pwr_rst_o.rstreqs checker
+ // sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc
+ // if esc_timeout, rstreqs[ResetEscIdx] should be asserted
+ `ASSERT(RstreqChkEsctimeout_A,
+ $rose(
+ slow_esc_rst_req
+ ) ##1 slow_esc_rst_req |-> ##[0:2] pwr_rst_o.rstreqs[ResetEscIdx],
+ clk_i, reset_or_disable)
+
+// sec_cm_fsm_terminal
+// if slow_fsm or fast_fsm is invalid,
+// both pwr_rst_o.rst_lc_req and pwr_rst_o.rst_sys_req should be set
+
+ `ASSERT(RstreqChkFsmterm_A,
+ $rose(slow_fsm_invalid) || $rose(fast_fsm_invalid)
+ |=> ##[1:10] $rose(pwr_rst_o.rst_lc_req & pwr_rst_o.rst_sys_req),
+ clk_i, reset_or_disable)
+
+// sec_cm_ctrl_flow_global_esc
+// if esc_rst_req is set, pwr_rst_o.rstreqs[ResetEscIdx] should be asserted.
+ `ASSERT(RstreqChkGlbesc_A,
+ $rose(slow_esc_rst_req) ##1 slow_esc_rst_req |->
+ ##[0:2] (pwr_rst_o.rstreqs[ResetEscIdx] | !rst_esc_ni),
+ clk_i, reset_or_disable)
+
+// sec_cm_main_pd_rst_local_esc
+// if power is up and rst_main_ni goes low, pwr_rst_o.rstreqs[ResetMainPwrIdx] should be asserted
+ `ASSERT(RstreqChkMainpd_A,
+ slow_mp_rst_req |-> ##[0:5] pwr_rst_o.rstreqs[ResetMainPwrIdx], clk_i,
+ reset_or_disable)
+
+endmodule // pwrmgr_sec_cm_checker_assert
diff --git a/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_sva.core
new file mode 100644
index 0000000..242fe4c
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/sva/pwrmgr_sva.core
@@ -0,0 +1,43 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:dv:pwrmgr_sva:0.1"
+description: "PWRMGR assertion modules and bind file."
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:tlul:headers
+ - lowrisc:fpv:csr_assert_gen
+ - google:systems:pwrmgr
+ - lowrisc:dv:clkmgr_pwrmgr_sva_if
+ - lowrisc:dv:pwrmgr_rstmgr_sva_if
+ files:
+ - pwrmgr_bind.sv
+ - pwrmgr_clock_enables_sva_if.sv
+ - pwrmgr_rstreqs_sva_if.sv
+ - pwrmgr_sec_cm_checker_assert.sv
+ file_type: systemVerilogSource
+
+ files_formal:
+ depend:
+ - google:systems:pwrmgr
+
+generate:
+ csr_assert_gen:
+ generator: csr_assert_gen
+ parameters:
+ spec: ../../../../top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson
+
+targets:
+ default: &default_target
+ filesets:
+ - files_dv
+ generate:
+ - csr_assert_gen
+ formal:
+ <<: *default_target
+ filesets:
+ - files_formal
+ - files_dv
+ toplevel: pwrmgr
diff --git a/hw/top_sencha/ip/pwrmgr/dv/tb.sv b/hw/top_sencha/ip/pwrmgr/dv/tb.sv
new file mode 100644
index 0000000..e9b2506
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/tb.sv
@@ -0,0 +1,162 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+module tb;
+ // dep packages
+ import uvm_pkg::*;
+ import dv_utils_pkg::*;
+ import pwrmgr_env_pkg::*;
+ import pwrmgr_test_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ wire clk, rst_n;
+ wire clk_esc, rst_esc_n;
+ wire clk_lc, rst_lc_n;
+ wire clk_slow, rst_slow_n;
+ wire aon_clk, aon_rst_n;
+ wire devmode;
+ wire [NUM_MAX_INTERRUPTS-1:0] interrupts;
+
+ // interfaces
+ clk_rst_if clk_rst_if (
+ .clk (clk),
+ .rst_n(rst_n)
+ );
+ clk_rst_if lc_clk_rst_if (
+ .clk (clk_lc),
+ .rst_n(rst_lc_n)
+ );
+ clk_rst_if esc_clk_rst_if (
+ .clk (clk_esc),
+ .rst_n(rst_esc_n)
+ );
+ clk_rst_if aon_clk_rst_if (
+ .clk (aon_clk),
+ .rst_n(aon_rst_n)
+ );
+ clk_rst_if slow_clk_rst_if (
+ .clk (clk_slow),
+ .rst_n(rst_slow_n)
+ );
+ pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts);
+ alert_esc_if esc_if (
+ .clk (clk),
+ .rst_n(rst_n)
+ );
+ pins_if #(1) devmode_if (devmode);
+ tl_if tl_if (
+ .clk (clk),
+ .rst_n(rst_n)
+ );
+
+ assign interrupts[0] = pwrmgr_if.intr_wakeup;
+
+ pwrmgr_if pwrmgr_if (
+ .clk,
+ .rst_n,
+ .clk_slow,
+ .rst_slow_n
+ );
+
+ `DV_ALERT_IF_CONNECT(clk_lc, rst_lc_n)
+
+ // dut
+ pwrmgr dut (
+ .clk_i (clk),
+ .rst_ni (rst_n),
+ .clk_slow_i (clk_slow),
+ .rst_slow_ni(rst_slow_n),
+ .rst_main_ni(pwrmgr_if.rst_main_n),
+ .clk_lc_i (clk_lc),
+ .rst_lc_ni (rst_lc_n),
+ .clk_esc_i (clk_esc),
+ .rst_esc_ni (rst_esc_n),
+
+ .tl_i(tl_if.h2d),
+ .tl_o(tl_if.d2h),
+
+ .alert_rx_i(alert_rx),
+ .alert_tx_o(alert_tx),
+
+ .pwr_ast_i(pwrmgr_if.pwr_ast_rsp),
+ .pwr_ast_o(pwrmgr_if.pwr_ast_req),
+
+ .pwr_rst_i(pwrmgr_if.pwr_rst_rsp),
+ .pwr_rst_o(pwrmgr_if.pwr_rst_req),
+
+ .pwr_clk_i(pwrmgr_if.pwr_clk_rsp),
+ .pwr_clk_o(pwrmgr_if.pwr_clk_req),
+
+ .pwr_otp_i(pwrmgr_if.pwr_otp_rsp),
+ .pwr_otp_o(pwrmgr_if.pwr_otp_req),
+
+ .pwr_lc_i(pwrmgr_if.pwr_lc_rsp),
+ .pwr_lc_o(pwrmgr_if.pwr_lc_req),
+
+ .pwr_flash_i(pwrmgr_if.pwr_flash),
+ .pwr_cpu_i (pwrmgr_if.pwr_cpu),
+
+ .fetch_en_o(pwrmgr_if.fetch_en),
+ .wakeups_i (pwrmgr_if.wakeups_i),
+ .rstreqs_i (pwrmgr_if.rstreqs_i),
+ .ndmreset_req_i(pwrmgr_if.cpu_i.ndmreset_req),
+
+ .lc_dft_en_i (pwrmgr_if.lc_dft_en),
+ .lc_hw_debug_en_i(pwrmgr_if.lc_hw_debug_en),
+
+ .strap_o (pwrmgr_if.strap),
+ .low_power_o(pwrmgr_if.low_power),
+
+ .rom_ctrl_i(pwrmgr_if.rom_ctrl),
+
+ .sw_rst_req_i(pwrmgr_if.sw_rst_req_i),
+
+ .esc_rst_tx_i(esc_if.esc_tx),
+ .esc_rst_rx_o(esc_if.esc_rx),
+
+ .intr_wakeup_o(pwrmgr_if.intr_wakeup)
+ );
+
+ initial begin
+ // drive clk and rst_n from clk_if
+ clk_rst_if.set_active();
+ esc_clk_rst_if.set_active();
+ lc_clk_rst_if.set_active();
+ slow_clk_rst_if.set_active();
+ aon_clk_rst_if.set_active();
+
+ uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
+ uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "esc_clk_rst_vif", esc_clk_rst_if);
+ uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "lc_clk_rst_vif", lc_clk_rst_if);
+ uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "aon_clk_rst_vif", aon_clk_rst_if);
+ uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "slow_clk_rst_vif", slow_clk_rst_if);
+ uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
+ uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
+ uvm_config_db#(virtual alert_esc_if)::set(null, "*.env.m_esc_agent*", "vif", esc_if);
+ uvm_config_db#(virtual pwrmgr_if)::set(null, "*.env", "pwrmgr_vif", pwrmgr_if);
+ uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
+ uvm_config_db#(virtual pwrmgr_clock_enables_sva_if)::set(
+ null, "*.env", "pwrmgr_clock_enables_sva_vif", dut.pwrmgr_clock_enables_sva_if);
+ uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::set(null, "*.env", "pwrmgr_rstmgr_sva_vif",
+ dut.pwrmgr_rstmgr_sva_if);
+ $timeformat(-12, 0, " ps", 12);
+ run_test();
+ end // initial begin
+
+endmodule
diff --git a/hw/top_sencha/ip/pwrmgr/dv/tests/pwrmgr_base_test.sv b/hw/top_sencha/ip/pwrmgr/dv/tests/pwrmgr_base_test.sv
new file mode 100644
index 0000000..fd27228
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/tests/pwrmgr_base_test.sv
@@ -0,0 +1,32 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+class pwrmgr_base_test extends cip_base_test #(
+ .CFG_T(pwrmgr_env_cfg),
+ .ENV_T(pwrmgr_env)
+);
+
+ `uvm_component_utils(pwrmgr_base_test)
+ `uvm_component_new
+
+ // the base class dv_base_test creates the following instances:
+ // pwrmgr_env_cfg: cfg
+ // pwrmgr_env: env
+
+ // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in
+ // the run_phase; as such, nothing more needs to be done
+
+endclass : pwrmgr_base_test
diff --git a/hw/top_sencha/ip/pwrmgr/dv/tests/pwrmgr_test.core b/hw/top_sencha/ip/pwrmgr/dv/tests/pwrmgr_test.core
new file mode 100644
index 0000000..1011fa1
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/tests/pwrmgr_test.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:dv:pwrmgr_test:0.1"
+description: "PWRMGR DV UVM test"
+filesets:
+ files_dv:
+ depend:
+ - google:dv:pwrmgr_env
+ files:
+ - pwrmgr_test_pkg.sv
+ - pwrmgr_base_test.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip/pwrmgr/dv/tests/pwrmgr_test_pkg.sv b/hw/top_sencha/ip/pwrmgr/dv/tests/pwrmgr_test_pkg.sv
new file mode 100644
index 0000000..f7c31f4
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/dv/tests/pwrmgr_test_pkg.sv
@@ -0,0 +1,34 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+package pwrmgr_test_pkg;
+ // dep packages
+ import uvm_pkg::*;
+ import cip_base_pkg::*;
+ import pwrmgr_env_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ // local types
+
+ // functions
+
+ // package sources
+ `include "pwrmgr_base_test.sv"
+
+endpackage
diff --git a/hw/top_sencha/ip/pwrmgr/lint/pwrmgr.vlt b/hw/top_sencha/ip/pwrmgr/lint/pwrmgr.vlt
new file mode 100644
index 0000000..dc237ec
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/lint/pwrmgr.vlt
@@ -0,0 +1,5 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// waiver file for Power Manager
diff --git a/hw/top_sencha/ip/pwrmgr/lint/pwrmgr.waiver b/hw/top_sencha/ip/pwrmgr/lint/pwrmgr.waiver
new file mode 100644
index 0000000..bb053b8
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/lint/pwrmgr.waiver
@@ -0,0 +1,5 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for Power Manager
diff --git a/hw/top_sencha/ip/pwrmgr/lint/pwrmgr_pkg.vlt b/hw/top_sencha/ip/pwrmgr/lint/pwrmgr_pkg.vlt
new file mode 100644
index 0000000..4e83758
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/lint/pwrmgr_pkg.vlt
@@ -0,0 +1,12 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// waiver file for the pwrmgr_pkg
+
+`verilator_config
+
+// Waive the SYMRSVDWORD warning in pwrmgr_reg_pkg: we have a field in
+// the WAKE_INFO register called "abort", which means pwrmgr_reg_pkg
+// defines a struct with that name, clashing with a C++ reserved word.
+lint_off -rule SYMRSVDWORD -file "*/pwrmgr_reg_pkg.sv" -match "*common word: 'abort'"
diff --git a/hw/top_sencha/ip/pwrmgr/pwrmgr.core b/hw/top_sencha/ip/pwrmgr/pwrmgr.core
new file mode 100644
index 0000000..b8846f4
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/pwrmgr.core
@@ -0,0 +1,79 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:systems:pwrmgr:0.1"
+description: "Power manager component without the generated portions"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:prim:esc
+ - lowrisc:prim:lc_sender
+ - lowrisc:prim:all
+ - lowrisc:ip:rom_ctrl_pkg
+ - lowrisc:ip:lc_ctrl_pkg
+ - lowrisc:ip:pwrmgr_pkg
+ - lowrisc:prim:sparse_fsm
+ - lowrisc:prim:mubi
+ - lowrisc:prim:clock_buf
+ - lowrisc:prim:measure
+ - lowrisc:ip_interfaces:alert_handler_reg
+ files:
+ - rtl/pwrmgr.sv
+ - rtl/pwrmgr_cdc.sv
+ - rtl/pwrmgr_slow_fsm.sv
+ - rtl/pwrmgr_fsm.sv
+ - rtl/pwrmgr_wake_info.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/pwrmgr.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/pwrmgr.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
+ toplevel: pwrmgr
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_sencha/ip/pwrmgr/pwrmgr_pkg.core b/hw/top_sencha/ip/pwrmgr/pwrmgr_pkg.core
new file mode 100644
index 0000000..ded3ed5
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/pwrmgr_pkg.core
@@ -0,0 +1,29 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:pwrmgr_pkg:0.1"
+description: "Power manager package"
+
+filesets:
+ files_rtl:
+ depend:
+ - google:systems:pwrmgr_reg
+ files:
+ - rtl/pwrmgr_pkg.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/pwrmgr_pkg.vlt
+ file_type: vlt
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - files_rtl
diff --git a/hw/top_sencha/ip/pwrmgr/pwrmgr_reg.core b/hw/top_sencha/ip/pwrmgr/pwrmgr_reg.core
new file mode 100644
index 0000000..94555f7
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/pwrmgr_reg.core
@@ -0,0 +1,21 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:systems:pwrmgr_reg:0.1"
+description: "Auto-generated power manager registers for top_sencha"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:tlul:headers
+ - lowrisc:prim:subreg
+ files:
+ - rtl/autogen/pwrmgr_reg_pkg.sv
+ - rtl/autogen/pwrmgr_reg_top.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr.sv b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr.sv
new file mode 100644
index 0000000..43fa76b
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr.sv
@@ -0,0 +1,704 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Power Manager
+//
+
+`include "prim_assert.sv"
+
+module pwrmgr
+ import pwrmgr_pkg::*;
+ import pwrmgr_reg_pkg::*;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
+ // Clocks and resets
+ input clk_slow_i,
+ input clk_i,
+ input rst_slow_ni,
+ input rst_ni,
+ input rst_main_ni,
+ input clk_lc_i,
+ input rst_lc_ni,
+ input clk_esc_i,
+ input rst_esc_ni,
+
+ // Bus Interface
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Alerts
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
+ // AST interface
+ input pwr_ast_rsp_t pwr_ast_i,
+ output pwr_ast_req_t pwr_ast_o,
+
+ // rstmgr interface
+ input pwr_rst_rsp_t pwr_rst_i,
+ output pwr_rst_req_t pwr_rst_o,
+
+ // clkmgr interface
+ output pwr_clk_req_t pwr_clk_o,
+ input pwr_clk_rsp_t pwr_clk_i,
+
+ // otp interface
+ input pwr_otp_rsp_t pwr_otp_i,
+ output pwr_otp_req_t pwr_otp_o,
+
+ // life cycle interface
+ input pwr_lc_rsp_t pwr_lc_i,
+ output pwr_lc_req_t pwr_lc_o,
+
+ // flash interface
+ input pwr_flash_t pwr_flash_i,
+
+ // processor interface
+ input pwr_cpu_t pwr_cpu_i,
+ // SEC_CM: LC_CTRL.INTERSIG.MUBI
+ output lc_ctrl_pkg::lc_tx_t fetch_en_o,
+ input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_dft_en_i,
+
+ // peripherals wakeup and reset requests
+ input [NumWkups-1:0] wakeups_i,
+ input [NumRstReqs-1:0] rstreqs_i,
+
+ // cpu related inputs
+ input ndmreset_req_i,
+
+ // pinmux and other peripherals
+ output logic strap_o,
+ output logic low_power_o,
+
+ // rom_ctrl interface
+ // SEC_CM: ROM_CTRL.INTERSIG.MUBI
+ input rom_ctrl_pkg::pwrmgr_data_t rom_ctrl_i,
+
+ // software issued reset request
+ // SEC_CM: RSTMGR.INTERSIG.MUBI
+ input prim_mubi_pkg::mubi4_t sw_rst_req_i,
+
+ // escalation interface
+ input prim_esc_pkg::esc_tx_t esc_rst_tx_i,
+ output prim_esc_pkg::esc_rx_t esc_rst_rx_o,
+
+ output intr_wakeup_o
+
+);
+ ////////////////////////////////////////////////////
+ // Input handling //
+ ////////////////////////////////////////////////////
+
+ logic ndmreset_req_q;
+ logic ndm_req_valid;
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_ndm_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(ndmreset_req_i),
+ .q_o(ndmreset_req_q)
+ );
+
+ assign ndm_req_valid = ndmreset_req_q;
+
+ ////////////////////////////
+ /// escalation detections
+ ////////////////////////////
+
+ logic clk_lc;
+ logic rst_lc_n;
+ assign clk_lc = clk_lc_i;
+ assign rst_lc_n = rst_lc_ni;
+
+ logic clk_esc;
+ logic rst_esc_n;
+ prim_clock_buf #(
+ .NoFpgaBuf(1'b1)
+ ) u_esc_clk_buf (
+ .clk_i(clk_esc_i),
+ .clk_o(clk_esc)
+ );
+
+ prim_clock_buf #(
+ .NoFpgaBuf(1'b1)
+ ) u_esc_rst_buf (
+ .clk_i(rst_esc_ni),
+ .clk_o(rst_esc_n)
+ );
+
+ logic esc_rst_req_d, esc_rst_req_q;
+ prim_esc_receiver #(
+ .N_ESC_SEV (alert_handler_reg_pkg::N_ESC_SEV),
+ .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW)
+ ) u_esc_rx (
+ .clk_i(clk_esc),
+ .rst_ni(rst_esc_n),
+ .esc_req_o(esc_rst_req_d),
+ .esc_rx_o(esc_rst_rx_o),
+ .esc_tx_i(esc_rst_tx_i)
+ );
+
+ // These assertions use formal to approve that once esc_rst_req is latched, we always expect to
+ // see the pwr_rst_o to latch.
+`ifdef SIMULATION
+ // In simulation mode, the prim_cdc_rand_delay module inserts a random one cycle delay to the
+ // two flop synchronizers.
+ // This assertion also adds a two-cycle buffer to handle the scenario where the escalation request
+ // yields to a pending low power reset request.
+ `ASSERT(PwrmgrSecCmEscToFsmResetReq_A, esc_rst_req_d |-> ##[1:5] (u_fsm.reset_reqs_i > 0),
+ clk_slow_i, !rst_slow_ni)
+`else
+ `ASSERT(PwrmgrSecCmEscToFsmResetReq_A, esc_rst_req_d |-> ##3 u_fsm.reset_reqs_i[ResetEscIdx],
+ clk_slow_i, !rst_slow_ni)
+`endif
+
+ `ASSERT(PwrmgrSecCmEscToLCReset_A, u_fsm.reset_reqs_i[ResetEscIdx] &&
+ u_fsm.state_q == FastPwrStateActive |-> ##[0:2] pwr_rst_o.rst_lc_req == 2'b11,
+ clk_slow_i, !rst_slow_ni)
+
+ always_ff @(posedge clk_lc or negedge rst_lc_n) begin
+ if (!rst_lc_n) begin
+ esc_rst_req_q <= '0;
+ end else if (esc_rst_req_d) begin
+ // once latched, do not clear until reset
+ esc_rst_req_q <= 1'b1;
+ end
+ end
+
+ localparam int EscTimeOutCnt = 128;
+ logic esc_timeout;
+ // SEC_CM: ESC_RX.CLK.BKGN_CHK, ESC_RX.CLK.LOCAL_ESC
+ prim_clock_timeout #(
+ .TimeOutCnt(EscTimeOutCnt)
+ ) u_esc_timeout (
+ .clk_chk_i(clk_esc),
+ .rst_chk_ni(rst_esc_n),
+ .clk_i,
+ .rst_ni,
+ // if any ip clock enable is turned on, then the escalation
+ // clocks are also enabled.
+ .en_i(|pwr_clk_o),
+ .timeout_o(esc_timeout)
+ );
+
+
+ ////////////////////////////
+ /// async declarations
+ ////////////////////////////
+ pwr_peri_t peri_reqs_raw;
+ logic slow_rst_req;
+
+ assign peri_reqs_raw.wakeups = wakeups_i;
+ assign peri_reqs_raw.rstreqs[NumRstReqs-1:0] = rstreqs_i;
+ assign peri_reqs_raw.rstreqs[ResetMainPwrIdx] = slow_rst_req;
+ // SEC_CM: ESC_RX.CLK.LOCAL_ESC, CTRL_FLOW.GLOBAL_ESC
+ assign peri_reqs_raw.rstreqs[ResetEscIdx] = esc_rst_req_q | esc_timeout;
+ assign peri_reqs_raw.rstreqs[ResetNdmIdx] = ndm_req_valid;
+
+ ////////////////////////////
+ /// Software reset request
+ ////////////////////////////
+ logic sw_rst_req;
+ prim_buf #(
+ .Width(1)
+ ) u_sw_req_buf (
+ .in_i(prim_mubi_pkg::mubi4_test_true_strict(sw_rst_req_i)),
+ .out_o(sw_rst_req)
+ );
+
+ assign peri_reqs_raw.rstreqs[ResetSwReqIdx] = sw_rst_req;
+
+ ////////////////////////////
+ /// clk_i domain declarations
+ ////////////////////////////
+
+ pwrmgr_reg2hw_t reg2hw;
+ pwrmgr_hw2reg_t hw2reg;
+ pwr_peri_t peri_reqs_masked;
+
+ logic req_pwrup;
+ logic ack_pwrup;
+ logic req_pwrdn;
+ logic ack_pwrdn;
+ logic fsm_invalid;
+ logic clr_slow_req;
+ logic usb_ip_clk_en;
+ logic usb_ip_clk_status;
+ pwrup_cause_e pwrup_cause;
+
+ logic low_power_fall_through;
+ logic low_power_abort;
+
+ pwr_flash_t flash_rsp;
+ pwr_otp_rsp_t otp_rsp;
+
+ prim_mubi_pkg::mubi4_t rom_ctrl_done;
+ prim_mubi_pkg::mubi4_t rom_ctrl_good;
+
+ logic core_sleeping;
+
+ ////////////////////////////
+ /// clk_slow_i domain declarations
+ ////////////////////////////
+
+ // Captured signals
+ // These signals, though on clk_i domain, are safe for clk_slow_i to use
+ logic [NumWkups-1:0] slow_wakeup_en;
+ logic [NumRstReqs-1:0] slow_reset_en;
+
+ pwr_ast_rsp_t slow_ast;
+ pwr_peri_t slow_peri_reqs, slow_peri_reqs_masked;
+
+ pwrup_cause_e slow_pwrup_cause;
+ logic slow_pwrup_cause_toggle;
+ logic slow_req_pwrup;
+ logic slow_ack_pwrup;
+ logic slow_req_pwrdn;
+ logic slow_ack_pwrdn;
+ logic slow_fsm_invalid;
+ logic slow_main_pd_n;
+ logic slow_io_clk_en;
+ logic slow_core_clk_en;
+ logic slow_usb_clk_en_lp;
+ logic slow_usb_clk_en_active;
+ logic slow_clr_req;
+ logic slow_usb_ip_clk_en;
+ logic slow_usb_ip_clk_status;
+
+
+
+ ////////////////////////////
+ /// Register module
+ ////////////////////////////
+ logic [NumAlerts-1:0] alert_test, alerts;
+ logic low_power_hint;
+ logic lowpwr_cfg_wen;
+ logic clr_hint;
+ logic wkup;
+ logic clr_cfg_lock;
+ logic reg_intg_err;
+
+ // SEC_CM: BUS.INTEGRITY
+ // SEC_CM: CTRL.CONFIG.REGWEN, WAKEUP.CONFIG.REGWEN, RESET.CONFIG.REGWEN
+ pwrmgr_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+ .clk_lc_i (clk_lc ),
+ .rst_lc_ni (rst_lc_n),
+ .tl_i,
+ .tl_o,
+ .reg2hw,
+ .hw2reg,
+ .intg_err_o (reg_intg_err),
+ .devmode_i (1'b1)
+ );
+
+ // whenever low power entry begins, wipe the hint
+ assign hw2reg.control.low_power_hint.d = 1'b0;
+ assign hw2reg.control.low_power_hint.de = clr_hint;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ lowpwr_cfg_wen <= 1'b1;
+ end else if (!lowpwr_cfg_wen && (clr_cfg_lock || wkup)) begin
+ lowpwr_cfg_wen <= 1'b1;
+ end else if (low_power_hint) begin
+ lowpwr_cfg_wen <= 1'b0;
+ end
+ end
+
+ assign hw2reg.ctrl_cfg_regwen.d = lowpwr_cfg_wen;
+
+ assign hw2reg.fault_status.reg_intg_err.de = reg_intg_err;
+ assign hw2reg.fault_status.reg_intg_err.d = 1'b1;
+ assign hw2reg.fault_status.esc_timeout.de = esc_timeout;
+ assign hw2reg.fault_status.esc_timeout.d = 1'b1;
+
+ // The main power domain glitch automatically causes a reset, so regsitering
+ // an alert is functionally pointless. However, if an attacker somehow manages/
+ // to silence the reset, this gives us one potential back-up path through alert_handler.
+ // Allow capture of main_pd fault status whenever the system is live.
+ assign hw2reg.fault_status.main_pd_glitch.de = pwr_clk_o.main_ip_clk_en;
+ assign hw2reg.fault_status.main_pd_glitch.d = peri_reqs_masked.rstreqs[ResetMainPwrIdx] |
+ reg2hw.fault_status.main_pd_glitch.q;
+
+ `ASSERT(GlitchStatusPersist_A, $rose(reg2hw.fault_status.main_pd_glitch.q) |->
+ reg2hw.fault_status.main_pd_glitch.q until !rst_lc_ni)
+
+ ////////////////////////////
+ /// alerts
+ ////////////////////////////
+
+ // the logic below assumes there is only one alert, so make an
+ // explicit assertion check for it.
+ `ASSERT_INIT(AlertNumCheck_A, NumAlerts == 1)
+
+ assign alert_test = {
+ reg2hw.alert_test.q &
+ reg2hw.alert_test.qe
+ };
+
+ assign alerts[0] = reg2hw.fault_status.reg_intg_err.q |
+ reg2hw.fault_status.esc_timeout.q |
+ reg2hw.fault_status.main_pd_glitch.q;
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(1'b1)
+ ) u_prim_alert_sender (
+ .clk_i ( clk_lc ),
+ .rst_ni ( rst_lc_n ),
+ .alert_test_i ( alert_test[i] ),
+ .alert_req_i ( alerts[i] ),
+ .alert_ack_o ( ),
+ .alert_state_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
+ ////////////////////////////
+ /// cdc handling
+ ////////////////////////////
+
+ pwrmgr_cdc u_cdc (
+ .clk_i,
+ .rst_ni,
+ .clk_slow_i,
+ .rst_slow_ni,
+
+ // slow domain signals
+ .slow_req_pwrup_i(slow_req_pwrup),
+ .slow_ack_pwrdn_i(slow_ack_pwrdn),
+ .slow_fsm_invalid_i(slow_fsm_invalid),
+ .slow_pwrup_cause_toggle_i(slow_pwrup_cause_toggle),
+ .slow_pwrup_cause_i(slow_pwrup_cause),
+ .slow_wakeup_en_o(slow_wakeup_en),
+ .slow_reset_en_o(slow_reset_en),
+ .slow_main_pd_no(slow_main_pd_n),
+ .slow_io_clk_en_o(slow_io_clk_en),
+ .slow_core_clk_en_o(slow_core_clk_en),
+ .slow_usb_clk_en_lp_o(slow_usb_clk_en_lp),
+ .slow_usb_clk_en_active_o(slow_usb_clk_en_active),
+ .slow_req_pwrdn_o(slow_req_pwrdn),
+ .slow_ack_pwrup_o(slow_ack_pwrup),
+ .slow_ast_o(slow_ast),
+ .slow_peri_reqs_o(slow_peri_reqs),
+ .slow_peri_reqs_masked_i(slow_peri_reqs_masked),
+ .slow_clr_req_o(slow_clr_req),
+ .slow_usb_ip_clk_en_i(slow_usb_ip_clk_en),
+ .slow_usb_ip_clk_status_o(slow_usb_ip_clk_status),
+
+ // fast domain signals
+ .req_pwrdn_i(req_pwrdn),
+ .ack_pwrup_i(ack_pwrup),
+ .cfg_cdc_sync_i(reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q),
+ .cdc_sync_done_o(hw2reg.cfg_cdc_sync.de),
+ .wakeup_en_i(reg2hw.wakeup_en),
+ .reset_en_i(reg2hw.reset_en),
+ .main_pd_ni(reg2hw.control.main_pd_n.q),
+ .io_clk_en_i(reg2hw.control.io_clk_en.q),
+ .core_clk_en_i(reg2hw.control.core_clk_en.q),
+ .usb_clk_en_lp_i(reg2hw.control.usb_clk_en_lp.q),
+ .usb_clk_en_active_i(reg2hw.control.usb_clk_en_active.q),
+ .ack_pwrdn_o(ack_pwrdn),
+ .fsm_invalid_o(fsm_invalid),
+ .req_pwrup_o(req_pwrup),
+ .pwrup_cause_o(pwrup_cause),
+ .peri_reqs_o(peri_reqs_masked),
+ .clr_slow_req_i(clr_slow_req),
+ .usb_ip_clk_en_o(usb_ip_clk_en),
+ .usb_ip_clk_status_i(usb_ip_clk_status),
+
+ // AST signals
+ .ast_i(pwr_ast_i),
+
+ // peripheral signals
+ .peri_i(peri_reqs_raw),
+
+ // flash handshake
+ .flash_i(pwr_flash_i),
+ .flash_o(flash_rsp),
+
+ // OTP signals
+ .otp_i(pwr_otp_i),
+ .otp_o(otp_rsp),
+
+ // rom_ctrl signals
+ .rom_ctrl_done_i(rom_ctrl_i.done),
+ .rom_ctrl_done_o(rom_ctrl_done),
+
+ // core sleeping
+ .core_sleeping_i(pwr_cpu_i.core_sleeping),
+ .core_sleeping_o(core_sleeping)
+
+ );
+ // rom_ctrl_i.good is not synchronized as it acts as a "payload" signal
+ // to "done". Good is only observed if "done" is high.
+ assign rom_ctrl_good = rom_ctrl_i.good;
+ assign hw2reg.cfg_cdc_sync.d = 1'b0;
+
+ ////////////////////////////
+ /// Wakup and reset capture
+ ////////////////////////////
+
+ // reset and wakeup requests are captured into the slow clock domain and then
+ // fanned out to other domains as necessary. This ensures there is not a huge
+ // time gap between when the slow clk domain sees the signal vs when the fast
+ // clock domains see it. This creates redundant syncing but keeps the time
+ // scale approximately the same across all domains.
+ //
+ // This also implies that these signals must be at least 1 clk_slow pulse long
+ //
+ // Since resets are not latched inside pwrmgr, there exists a corner case where
+ // non-always-on reset requests may get wiped out by a graceful low power entry
+ // It's not clear if this is really an issue at the moment, but something to keep
+ // in mind if future changes are needed.
+ //
+ // Latching the reset requests is not difficult, but the bigger question is who
+ // should clear it and when that should happen. If the clearing does not work
+ // correctly, it is possible for the device to end up in a permanent reset loop,
+ // and that would be very undesirable.
+
+ assign slow_peri_reqs_masked.wakeups = slow_peri_reqs.wakeups & slow_wakeup_en;
+ // msb is software request
+ // the internal requests include escalation and internal requests
+ // the lsbs are the software enabled peripheral requests.
+ assign slow_peri_reqs_masked.rstreqs = slow_peri_reqs.rstreqs &
+ {{NumSwRstReq{1'b1}},
+ {NumDebugRstReqs{1'b1}},
+ {NumIntRstReqs{1'b1}},
+ slow_reset_en};
+
+ for (genvar i = 0; i < NumWkups; i++) begin : gen_wakeup_status
+ assign hw2reg.wake_status[i].de = 1'b1;
+ assign hw2reg.wake_status[i].d = peri_reqs_masked.wakeups[i];
+ end
+
+ for (genvar i = 0; i < NumRstReqs; i++) begin : gen_reset_status
+ assign hw2reg.reset_status[i].de = 1'b1;
+ assign hw2reg.reset_status[i].d = peri_reqs_masked.rstreqs[i];
+ end
+
+ assign hw2reg.escalate_reset_status.de = 1'b1;
+ assign hw2reg.escalate_reset_status.d = peri_reqs_masked.rstreqs[NumRstReqs];
+
+
+ ////////////////////////////
+ /// clk_slow FSM
+ ////////////////////////////
+
+ pwrmgr_slow_fsm u_slow_fsm (
+ .clk_i (clk_slow_i),
+ .rst_ni (rst_slow_ni),
+ .rst_main_ni (rst_main_ni),
+ .wakeup_i (|slow_peri_reqs_masked.wakeups),
+ .reset_req_i (|slow_peri_reqs_masked.rstreqs),
+ .ast_i (slow_ast),
+ .req_pwrup_o (slow_req_pwrup),
+ .pwrup_cause_o (slow_pwrup_cause),
+ .pwrup_cause_toggle_o (slow_pwrup_cause_toggle),
+ .ack_pwrup_i (slow_ack_pwrup),
+ .req_pwrdn_i (slow_req_pwrdn),
+ .ack_pwrdn_o (slow_ack_pwrdn),
+ .rst_req_o (slow_rst_req),
+ .fsm_invalid_o (slow_fsm_invalid),
+ .clr_req_i (slow_clr_req),
+ .usb_ip_clk_en_o (slow_usb_ip_clk_en),
+ .usb_ip_clk_status_i (slow_usb_ip_clk_status),
+
+ .main_pd_ni (slow_main_pd_n),
+ .io_clk_en_i (slow_io_clk_en),
+ .core_clk_en_i (slow_core_clk_en),
+ .usb_clk_en_lp_i (slow_usb_clk_en_lp),
+ .usb_clk_en_active_i (slow_usb_clk_en_active),
+
+ // outputs to AST - These are on the slow clock domain
+ // TBD - need to check this with partners
+ .ast_o (pwr_ast_o)
+ );
+
+
+ ////////////////////////////
+ /// clk FSM
+ ////////////////////////////
+
+ assign low_power_hint = reg2hw.control.low_power_hint.q == LowPower;
+
+ pwrmgr_fsm u_fsm (
+ .clk_i,
+ .rst_ni,
+ .clk_slow_i,
+ .rst_slow_ni,
+
+ // interface with slow_fsm
+ .req_pwrup_i (req_pwrup),
+ .pwrup_cause_i (pwrup_cause), // por, wake or reset request
+ .ack_pwrup_o (ack_pwrup),
+ .req_pwrdn_o (req_pwrdn),
+ .ack_pwrdn_i (ack_pwrdn),
+ .low_power_entry_i (core_sleeping & low_power_hint),
+ .reset_reqs_i (peri_reqs_masked.rstreqs),
+ .fsm_invalid_i (fsm_invalid),
+ .clr_slow_req_o (clr_slow_req),
+ .usb_ip_clk_en_i (usb_ip_clk_en),
+ .usb_ip_clk_status_o (usb_ip_clk_status),
+
+ // cfg
+ .main_pd_ni (reg2hw.control.main_pd_n.q),
+
+ // consumed in pwrmgr
+ .wkup_o (wkup),
+ .clr_cfg_lock_o (clr_cfg_lock),
+ .fall_through_o (low_power_fall_through),
+ .abort_o (low_power_abort),
+ .clr_hint_o (clr_hint),
+
+ // rstmgr
+ .pwr_rst_o (pwr_rst_o),
+ .pwr_rst_i (pwr_rst_i),
+
+ // clkmgr
+ .ips_clk_en_o (pwr_clk_o),
+ .clk_en_status_i (pwr_clk_i),
+
+ // otp
+ .otp_init_o (pwr_otp_o.otp_init),
+ .otp_done_i (otp_rsp.otp_done),
+ .otp_idle_i (otp_rsp.otp_idle),
+
+ // lc
+ .lc_init_o (pwr_lc_o.lc_init),
+ .lc_done_i (pwr_lc_i.lc_done),
+ .lc_idle_i (pwr_lc_i.lc_idle),
+ .lc_dft_en_i,
+ .lc_hw_debug_en_i,
+
+ // flash
+ .flash_idle_i (flash_rsp.flash_idle),
+
+ // rom_ctrl
+ .rom_ctrl_done_i (rom_ctrl_done),
+ .rom_ctrl_good_i (rom_ctrl_good),
+
+ // processing element
+ .fetch_en_o,
+
+ // pinmux and other peripherals
+ .strap_o,
+ .low_power_o
+ );
+
+ ////////////////////////////
+ /// Wakeup Info Capture
+ ////////////////////////////
+
+ logic wake_info_wen;
+ logic [TotalWakeWidth-1:0] wake_info_data;
+
+ assign wake_info_wen = reg2hw.wake_info.abort.qe |
+ reg2hw.wake_info.fall_through.qe |
+ reg2hw.wake_info.reasons.qe;
+
+ assign wake_info_data = {reg2hw.wake_info.abort.q,
+ reg2hw.wake_info.fall_through.q,
+ reg2hw.wake_info.reasons.q};
+
+ pwrmgr_wake_info i_wake_info (
+ .clk_i,
+ .rst_ni,
+ .wr_i (wake_info_wen),
+ .data_i (wake_info_data),
+ .start_capture_i (low_power_o),
+ .record_dis_i (reg2hw.wake_info_capture_dis.q),
+ .wakeups_i (peri_reqs_masked.wakeups),
+ .fall_through_i (low_power_fall_through),
+ .abort_i (low_power_abort),
+ .info_o (hw2reg.wake_info)
+ );
+
+ ////////////////////////////
+ /// Interrupts
+ ////////////////////////////
+
+ // This interrupt is asserted whenever the fast FSM transitions
+ // into active state. However, it does not assert during POR
+ prim_intr_hw #(.Width(1)) intr_wakeup (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (wkup),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.d),
+ .intr_o (intr_wakeup_o)
+ );
+
+
+ ////////////////////////////
+ /// Assertions
+ ////////////////////////////
+
+ `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid )
+ `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready )
+ `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o )
+ `ASSERT_KNOWN(AstKnownO_A, pwr_ast_o )
+ `ASSERT_KNOWN(RstKnownO_A, pwr_rst_o )
+ `ASSERT_KNOWN(ClkKnownO_A, pwr_clk_o )
+ `ASSERT_KNOWN(OtpKnownO_A, pwr_otp_o )
+ `ASSERT_KNOWN(LcKnownO_A, pwr_lc_o )
+ `ASSERT_KNOWN(IntrKnownO_A, intr_wakeup_o )
+
+ // EscTimeOutCnt also sets the required clock ratios between escalator and local clock
+ // Ie, clk_lc cannot be so slow that the timeout count is reached
+ `ifdef INC_ASSERT
+ //VCS coverage off
+ // pragma coverage off
+ logic effective_rst_n;
+ assign effective_rst_n = clk_lc_i && rst_ni;
+
+ logic [31:0] cnt;
+ always_ff @(posedge clk_i or negedge effective_rst_n) begin
+ if (!effective_rst_n) begin
+ cnt <= '0;
+ end else begin
+ cnt <= cnt + 1'b1;
+ end
+ end
+ //VCS coverage on
+ // pragma coverage on
+
+ `ASSERT(ClkRatio_A, cnt < EscTimeOutCnt)
+
+ `endif
+
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(FsmCheck_A, u_fsm.u_state_regs,
+ pwr_rst_o.rst_lc_req && pwr_rst_o.rst_sys_req)
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(SlowFsmCheck_A, u_slow_fsm.u_state_regs,
+ pwr_ast_o.pwr_clamp && !pwr_ast_o.main_pd_n, 0, 2,
+ clk_slow_i, !rst_slow_ni)
+
+ // Alert assertions for reg_we onehot check
+ `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0])
+endmodule // pwrmgr
diff --git a/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_cdc.sv b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_cdc.sv
new file mode 100644
index 0000000..614eaa9
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_cdc.sv
@@ -0,0 +1,345 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Power Manager CDC handling
+//
+
+`include "prim_assert.sv"
+
+module pwrmgr_cdc import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;
+(
+ // Clocks and resets
+ input clk_slow_i,
+ input clk_i,
+ input rst_slow_ni,
+ input rst_ni,
+
+ // slow domain signals,
+ input slow_req_pwrup_i,
+ input slow_ack_pwrdn_i,
+ input slow_fsm_invalid_i,
+ input slow_pwrup_cause_toggle_i,
+ input pwrup_cause_e slow_pwrup_cause_i,
+ output logic [NumWkups-1:0] slow_wakeup_en_o,
+ output logic [NumRstReqs-1:0] slow_reset_en_o,
+ output logic slow_main_pd_no,
+ output logic slow_io_clk_en_o,
+ output logic slow_core_clk_en_o,
+ output logic slow_usb_clk_en_lp_o,
+ output logic slow_usb_clk_en_active_o,
+ output logic slow_req_pwrdn_o,
+ output logic slow_ack_pwrup_o,
+ output pwr_ast_rsp_t slow_ast_o,
+ output pwr_peri_t slow_peri_reqs_o,
+ input pwr_peri_t slow_peri_reqs_masked_i,
+ output logic slow_clr_req_o,
+ input slow_usb_ip_clk_en_i,
+ output slow_usb_ip_clk_status_o,
+
+ // fast domain signals
+ input req_pwrdn_i,
+ input ack_pwrup_i,
+ input cfg_cdc_sync_i,
+ input [NumWkups-1:0] wakeup_en_i,
+ input logic [NumRstReqs-1:0] reset_en_i,
+ input main_pd_ni,
+ input io_clk_en_i,
+ input core_clk_en_i,
+ input usb_clk_en_lp_i,
+ input usb_clk_en_active_i,
+ output logic ack_pwrdn_o,
+ output logic fsm_invalid_o,
+ output logic req_pwrup_o,
+ output pwrup_cause_e pwrup_cause_o,
+ output pwr_peri_t peri_reqs_o,
+ output logic cdc_sync_done_o,
+ input clr_slow_req_i,
+ output logic usb_ip_clk_en_o,
+ input usb_ip_clk_status_i,
+
+ // peripheral inputs, mixed domains
+ input pwr_peri_t peri_i,
+ input pwr_flash_t flash_i,
+ output pwr_flash_t flash_o,
+
+ // otp interface
+ input pwr_otp_rsp_t otp_i,
+ output pwr_otp_rsp_t otp_o,
+
+ // AST inputs, unknown domain
+ input pwr_ast_rsp_t ast_i,
+
+ // rom_ctrl signals
+ input prim_mubi_pkg::mubi4_t rom_ctrl_done_i,
+ output prim_mubi_pkg::mubi4_t rom_ctrl_done_o,
+
+ // core sleeping
+ input core_sleeping_i,
+ output logic core_sleeping_o
+
+);
+
+ ////////////////////////////////
+ // Sync from clk_i to clk_slow_i
+ ////////////////////////////////
+
+ logic slow_cdc_sync;
+ pwr_ast_rsp_t slow_ast_q, slow_ast_q2;
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_req_pwrdn_sync (
+ .clk_i(clk_slow_i),
+ .rst_ni(rst_slow_ni),
+ .d_i(req_pwrdn_i),
+ .q_o(slow_req_pwrdn_o)
+ );
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_ack_pwrup_sync (
+ .clk_i(clk_slow_i),
+ .rst_ni(rst_slow_ni),
+ .d_i(ack_pwrup_i),
+ .q_o(slow_ack_pwrup_o)
+ );
+
+ prim_pulse_sync u_slow_cdc_sync (
+ .clk_src_i(clk_i),
+ .rst_src_ni(rst_ni),
+ .src_pulse_i(cfg_cdc_sync_i),
+ .clk_dst_i(clk_slow_i),
+ .rst_dst_ni(rst_slow_ni),
+ .dst_pulse_o(slow_cdc_sync)
+ );
+
+ // Even though this is multi-bit, the bits are individual request lines.
+ // So there is no general concern about recombining as there is
+ // no intent to use them in a related manner.
+ prim_flop_2sync # (
+ .Width($bits(pwr_peri_t))
+ ) u_slow_ext_req_sync (
+ .clk_i (clk_slow_i),
+ .rst_ni (rst_slow_ni),
+ .d_i (peri_i),
+ .q_o (slow_peri_reqs_o)
+ );
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_ip_clk_status_sync (
+ .clk_i (clk_slow_i),
+ .rst_ni (rst_slow_ni),
+ .d_i (usb_ip_clk_status_i),
+ .q_o (slow_usb_ip_clk_status_o)
+ );
+
+ // Some of the AST signals are multi-bits themselves (such as clk_val)
+ // thus they need to be delayed one more stage to check for stability
+ prim_flop_2sync # (
+ .Width($bits(pwr_ast_rsp_t)),
+ .ResetValue(PWR_AST_RSP_SYNC_DEFAULT)
+ ) u_ast_sync (
+ .clk_i (clk_slow_i),
+ .rst_ni (rst_slow_ni),
+ .d_i (ast_i),
+ .q_o (slow_ast_q)
+ );
+
+ always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin
+ if (!rst_slow_ni) begin
+ slow_ast_q2 <= PWR_AST_RSP_SYNC_DEFAULT;
+ end else begin
+ slow_ast_q2 <= slow_ast_q;
+ end
+ end
+
+ // if possible, we should simulate below with random delays through
+ // flop_2sync
+ always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin
+ if (!rst_slow_ni) begin
+ slow_ast_o <= PWR_AST_RSP_SYNC_DEFAULT;
+ end else if (slow_ast_q2 == slow_ast_q) begin
+ // Output only updates whenever sync and delayed outputs both agree.
+ // If there are delays in sync, this will result in a 1 cycle difference
+ // and the output will hold the previous value
+ slow_ast_o <= slow_ast_q2;
+ end
+ end
+
+ // only register configurations can be sync'd using slow_cdc_sync
+ always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin
+ if (!rst_slow_ni) begin
+ slow_wakeup_en_o <= '0;
+ slow_reset_en_o <= '0;
+ slow_main_pd_no <= '1;
+ slow_io_clk_en_o <= '0;
+ slow_core_clk_en_o <= '0;
+ slow_usb_clk_en_lp_o <= '0;
+ slow_usb_clk_en_active_o <= 1'b1;
+ end else if (slow_cdc_sync) begin
+ slow_wakeup_en_o <= wakeup_en_i;
+ slow_reset_en_o <= reset_en_i;
+ slow_main_pd_no <= main_pd_ni;
+ slow_io_clk_en_o <= io_clk_en_i;
+ slow_core_clk_en_o <= core_clk_en_i;
+ slow_usb_clk_en_lp_o <= usb_clk_en_lp_i;
+ slow_usb_clk_en_active_o <= usb_clk_en_active_i;
+ end
+ end
+
+ ////////////////////////////////
+ // Sync from clk_slow_i to clk_i
+ ////////////////////////////////
+
+ logic pwrup_cause_toggle_q, pwrup_cause_toggle_q2;
+ logic pwrup_cause_chg;
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_req_pwrup_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(slow_req_pwrup_i),
+ .q_o(req_pwrup_o)
+ );
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_ack_pwrdn_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(slow_ack_pwrdn_i),
+ .q_o(ack_pwrdn_o)
+ );
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_int_fsm_invalid_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(slow_fsm_invalid_i),
+ .q_o(fsm_invalid_o)
+ );
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_pwrup_chg_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(slow_pwrup_cause_toggle_i),
+ .q_o(pwrup_cause_toggle_q)
+ );
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_ip_clk_en_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(slow_usb_ip_clk_en_i),
+ .q_o(usb_ip_clk_en_o)
+ );
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_sleeping_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(core_sleeping_i),
+ .q_o(core_sleeping_o)
+ );
+
+ prim_pulse_sync u_scdc_sync (
+ .clk_src_i(clk_slow_i),
+ .rst_src_ni(rst_slow_ni),
+ .src_pulse_i(slow_cdc_sync),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(cdc_sync_done_o)
+ );
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ pwrup_cause_toggle_q2 <= 1'b0;
+ end else begin
+ pwrup_cause_toggle_q2 <= pwrup_cause_toggle_q;
+ end
+ end
+
+ assign pwrup_cause_chg = pwrup_cause_toggle_q2 ^ pwrup_cause_toggle_q;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ pwrup_cause_o <= Por;
+ end else if (pwrup_cause_chg) begin
+ pwrup_cause_o <= slow_pwrup_cause_i;
+ end
+ end
+
+ prim_flop_2sync #(
+ .Width($bits(pwr_peri_t))
+ ) u_ext_req_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(slow_peri_reqs_masked_i),
+ .q_o(peri_reqs_o)
+ );
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue(1'b1)
+ ) u_sync_flash_idle (
+ .clk_i,
+ .rst_ni,
+ .d_i(flash_i.flash_idle),
+ .q_o(flash_o.flash_idle)
+ );
+
+ prim_flop_2sync #(
+ .Width($bits(pwr_otp_rsp_t)),
+ .ResetValue('0)
+ ) u_sync_otp (
+ .clk_i,
+ .rst_ni,
+ .d_i(otp_i),
+ .q_o(otp_o)
+ );
+
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(1),
+ .StabilityCheck(1)
+ ) u_sync_rom_ctrl (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(rom_ctrl_done_i),
+ .mubi_o({rom_ctrl_done_o})
+ );
+
+ ////////////////////////////////
+ // Handshake
+ ////////////////////////////////
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_clr_req_sync (
+ .clk_i(clk_slow_i),
+ .rst_ni(rst_slow_ni),
+ .d_i(clr_slow_req_i),
+ .q_o(slow_clr_req_o)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_cdc_pulse.sv b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_cdc_pulse.sv
new file mode 100644
index 0000000..17c7dd7
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_cdc_pulse.sv
@@ -0,0 +1,103 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Power Manager module to find slow clock edges
+// The clock is not used directly to avoid STA issues, instead a toggle
+// pulse is used.
+
+`include "prim_assert.sv"
+
+module pwrmgr_cdc_pulse (
+ input clk_slow_i,
+ input clk_i,
+ input rst_ni,
+ input rst_slow_ni,
+ input start_i,
+ input stop_i,
+ output logic pulse_o
+);
+
+ logic slow_toggle_pq, slow_toggle_nq;
+ logic clk_slow_pq, clk_slow_nq;
+ logic clk_slow_pq2, clk_slow_nq2;
+ logic toggle;
+ logic valid;
+
+ // toggle pulse generated on positive edge
+ always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin
+ if (!rst_slow_ni) begin
+ slow_toggle_pq <= 1'b0;
+ end else begin
+ slow_toggle_pq <= ~slow_toggle_pq;
+ end
+ end
+
+ // toggle pulse generated on negative edge
+ always_ff @(negedge clk_slow_i or negedge rst_slow_ni) begin
+ if (!rst_slow_ni) begin
+ slow_toggle_nq <= 1'b0;
+ end else begin
+ slow_toggle_nq <= ~slow_toggle_nq;
+ end
+ end
+
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) i_pos_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(slow_toggle_pq),
+ .q_o(clk_slow_pq)
+ );
+
+ prim_flop_2sync # (
+ .Width(1)
+ ) i_neg_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(slow_toggle_nq),
+ .q_o(clk_slow_nq)
+ );
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ clk_slow_pq2 <= 1'b0;
+ clk_slow_nq2 <= 1'b0;
+ end else begin
+ clk_slow_pq2 <= clk_slow_pq;
+ clk_slow_nq2 <= clk_slow_nq;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ valid <= 1'b0;
+ end else if (valid && stop_i) begin
+ valid <= 1'b0;
+ end else if (!valid && toggle && start_i) begin
+ valid <= 1'b1;
+ end
+ end
+
+ // toggle is found on either positive and negative edges of clk_slow_i
+ assign toggle = clk_slow_pq2 ^ clk_slow_pq | clk_slow_nq2 ^ clk_slow_nq;
+ assign pulse_o = valid & toggle;
+
+
+
+
+endmodule // pwrmgr
diff --git a/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_fsm.sv b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_fsm.sv
new file mode 100644
index 0000000..bf4ccdd
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_fsm.sv
@@ -0,0 +1,558 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Power Manager Fast FSM
+//
+
+`include "prim_assert.sv"
+
+module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;(
+ input clk_i,
+ input rst_ni,
+ input clk_slow_i,
+ input rst_slow_ni,
+
+ // interface with slow_fsm
+ input req_pwrup_i,
+ input pwrup_cause_e pwrup_cause_i,
+ output logic ack_pwrup_o,
+ output logic req_pwrdn_o,
+ input ack_pwrdn_i,
+ input low_power_entry_i,
+ input main_pd_ni,
+ input [TotalResetWidth-1:0] reset_reqs_i,
+ input fsm_invalid_i,
+ output logic clr_slow_req_o,
+ input usb_ip_clk_en_i,
+ output logic usb_ip_clk_status_o,
+
+ // consumed in pwrmgr
+ output logic wkup_o, // generate wake interrupt
+ output logic fall_through_o,
+ output logic abort_o,
+ output logic clr_hint_o,
+ output logic clr_cfg_lock_o,
+
+ // rstmgr
+ output pwr_rst_req_t pwr_rst_o,
+ input pwr_rst_rsp_t pwr_rst_i,
+
+ // clkmgr
+ output pwr_clk_req_t ips_clk_en_o,
+ input pwr_clk_rsp_t clk_en_status_i,
+
+ // otp
+ output logic otp_init_o,
+ input otp_done_i,
+ input otp_idle_i,
+
+ // lc
+ output logic lc_init_o,
+ input lc_done_i,
+ input lc_idle_i,
+ input lc_ctrl_pkg::lc_tx_t lc_dft_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i,
+
+ // flash
+ input flash_idle_i,
+
+ // rom_ctrl
+ input prim_mubi_pkg::mubi4_t rom_ctrl_done_i,
+ input prim_mubi_pkg::mubi4_t rom_ctrl_good_i,
+
+ // pinmux
+ output logic strap_o,
+ output logic low_power_o,
+
+ // processing elements
+ output lc_ctrl_pkg::lc_tx_t fetch_en_o
+);
+
+ import prim_mubi_pkg::mubi4_t;
+ import prim_mubi_pkg::mubi4_test_true_strict;
+ import prim_mubi_pkg::mubi4_or_hi;
+ import prim_mubi_pkg::mubi4_and_hi;
+ import lc_ctrl_pkg::lc_tx_and_hi;
+ import lc_ctrl_pkg::lc_tx_test_true_strict;
+
+ // The code below always assumes the always on domain is index 0
+ `ASSERT_INIT(AlwaysOnIndex_A, ALWAYS_ON_DOMAIN == 0)
+
+ // when there are multiple on domains, the latter 1 should become another parameter
+ localparam int OffDomainSelStart = ALWAYS_ON_DOMAIN + 1;
+
+ // all powered down domains have resets asserted
+ logic pd_n_rsts_asserted;
+
+ // all domains have resets asserted
+ logic all_rsts_asserted;
+
+ // resets are valid
+ logic reset_valid;
+
+ // reset hint to rstmgr
+ reset_cause_e reset_cause_q, reset_cause_d;
+
+ // reset request
+ logic reset_req;
+ logic direct_rst_req;
+ logic ndmreset_req;
+ logic hw_rst_req;
+ logic sw_rst_req;
+
+ // strap sample should only happen on cold boot or when the
+ // the system goes through a reset cycle
+ logic strap_sampled;
+
+ // disable processing element fetching
+ lc_ctrl_pkg::lc_tx_t fetch_en_q, fetch_en_d;
+
+ fast_pwr_state_e state_d, state_q;
+ logic reset_ongoing_q, reset_ongoing_d;
+ logic req_pwrdn_q, req_pwrdn_d;
+ logic ack_pwrup_q, ack_pwrup_d;
+ logic ip_clk_en_q, ip_clk_en_d;
+ logic [PowerDomains-1:0] rst_lc_req_q, rst_sys_req_q;
+ logic [PowerDomains-1:0] rst_lc_req_d, rst_sys_req_d;
+ logic otp_init;
+ logic lc_init;
+ logic low_power_q, low_power_d;
+
+ assign pd_n_rsts_asserted = pwr_rst_i.rst_lc_src_n[PowerDomains-1:OffDomainSelStart] == '0 &
+ pwr_rst_i.rst_sys_src_n[PowerDomains-1:OffDomainSelStart] == '0;
+
+ logic lc_rsts_valid;
+ assign lc_rsts_valid = ((rst_lc_req_q & ~pwr_rst_i.rst_lc_src_n) |
+ (~rst_lc_req_q & pwr_rst_i.rst_lc_src_n)) == {PowerDomains{1'b1}};
+ logic sys_rsts_valid;
+ assign sys_rsts_valid = ((rst_sys_req_q & ~pwr_rst_i.rst_sys_src_n) |
+ (~rst_sys_req_q & pwr_rst_i.rst_sys_src_n)) == {PowerDomains{1'b1}};
+
+ assign all_rsts_asserted = lc_rsts_valid & sys_rsts_valid;
+
+ // Any reset request was asserted.
+ assign reset_req = |reset_reqs_i;
+
+ // Any peripheral triggererd hardware reset request.
+ assign hw_rst_req = |reset_reqs_i[NumRstReqs-1:0];
+
+ // Direct reset request that bypass checks.
+ assign direct_rst_req = reset_reqs_i[ResetEscIdx] |
+ reset_reqs_i[ResetMainPwrIdx];
+
+ // Ndm reset request.
+ assign ndmreset_req = reset_reqs_i[ResetNdmIdx];
+
+ // Software triggered reset request.
+ assign sw_rst_req = reset_reqs_i[ResetSwReqIdx];
+
+ // when in low power path, resets are controlled by domain power down
+ // when in reset path, all resets must be asserted
+ // when the reset cause is something else, it is invalid
+ assign reset_valid = reset_cause_q == LowPwrEntry ? main_pd_ni | pd_n_rsts_asserted :
+ reset_cause_q == HwReq ? all_rsts_asserted : 1'b0;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ ack_pwrup_q <= 1'b0;
+ req_pwrdn_q <= 1'b0;
+ reset_ongoing_q <= 1'b0;
+ ip_clk_en_q <= 1'b0;
+ rst_lc_req_q <= {PowerDomains{1'b1}};
+ rst_sys_req_q <= {PowerDomains{1'b1}};
+ reset_cause_q <= ResetUndefined;
+ low_power_q <= 1'b1;
+ end else begin
+ ack_pwrup_q <= ack_pwrup_d;
+ req_pwrdn_q <= req_pwrdn_d;
+ reset_ongoing_q <= reset_ongoing_d;
+ ip_clk_en_q <= ip_clk_en_d;
+ rst_lc_req_q <= rst_lc_req_d;
+ rst_sys_req_q <= rst_sys_req_d;
+ reset_cause_q <= reset_cause_d;
+ low_power_q <= low_power_d;
+ end
+ end
+
+ // SEC_CM: FSM.SPARSE
+ `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, fast_pwr_state_e, FastPwrStateLowPower)
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ strap_sampled <= 1'b0;
+ end else if (&rst_sys_req_q) begin
+ strap_sampled <= 1'b0;
+ end else if (strap_o) begin
+ strap_sampled <= 1'b1;
+ end
+ end
+
+ prim_lc_sender u_fetch_en (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(fetch_en_d),
+ .lc_en_o(fetch_en_q)
+ );
+ assign fetch_en_o = fetch_en_q;
+
+ // Life cycle broadcast may take time to propagate through the system.
+ // The sync below simulates that behavior using the slowest clock in the
+ // system.
+ logic slow_lc_done;
+ logic lc_done;
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_slow_sync_lc_done (
+ .clk_i(clk_slow_i),
+ .rst_ni(rst_slow_ni),
+ .d_i(lc_done_i),
+ .q_o(slow_lc_done)
+ );
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_sync_lc_done (
+ .clk_i,
+ .rst_ni,
+ .d_i(slow_lc_done),
+ .q_o(lc_done)
+ );
+
+
+ logic clks_enabled;
+ logic clks_disabled;
+
+ // clocks all enabled computed as follows:
+ // if enable is high, meaning clock is requested to turn on, the status must
+ // also be 1.
+ // if enable is low, meaning clock is not requested to turn on, the status is
+ // don't care.
+ // the bit-wise OR of both conditions must be all true.
+ assign clks_enabled = ip_clk_en_q &&
+ &((ips_clk_en_o & clk_en_status_i) | ~ips_clk_en_o);
+
+ // clocks all disabled is the opposite:
+ // if enable is low the status must also be low.
+ // if enable is high, the status is don't care.
+ // the bit-wise OR of both conditions must be all true.
+ assign clks_disabled = ~ip_clk_en_q &&
+ &((~ips_clk_en_o & ~clk_en_status_i) | ips_clk_en_o);
+
+
+ // rom integrity checks are disabled during TEST / RMA states
+ // During TEST / RMA states, both dft_en and hw_debug_en are On.
+ // During DEV / PROD states, either both signals are Off, or only
+ // hw_debug_en is On
+
+ mubi4_t rom_intg_chk_dis;
+ assign rom_intg_chk_dis = lc_tx_test_true_strict(lc_tx_and_hi(lc_dft_en_i, lc_hw_debug_en_i)) ?
+ prim_mubi_pkg::MuBi4True :
+ prim_mubi_pkg::MuBi4False;
+
+ mubi4_t rom_intg_chk_done;
+ mubi4_t rom_intg_chk_good;
+ assign rom_intg_chk_done = mubi4_or_hi(mubi4_and_hi(rom_intg_chk_dis, rom_ctrl_done_i),
+ rom_ctrl_done_i);
+ assign rom_intg_chk_good = mubi4_or_hi(rom_intg_chk_dis, rom_ctrl_good_i);
+
+ always_comb begin
+ otp_init = 1'b0;
+ lc_init = 1'b0;
+ wkup_o = 1'b0;
+ fall_through_o = 1'b0;
+ abort_o = 1'b0;
+ clr_hint_o = 1'b0;
+ clr_cfg_lock_o = 1'b0;
+ strap_o = 1'b0;
+ clr_slow_req_o = 1'b0;
+
+ state_d = state_q;
+ ack_pwrup_d = ack_pwrup_q;
+ req_pwrdn_d = req_pwrdn_q;
+ reset_ongoing_d = reset_ongoing_q;
+ ip_clk_en_d = ip_clk_en_q;
+ rst_lc_req_d = rst_lc_req_q;
+ rst_sys_req_d = rst_sys_req_q;
+ reset_cause_d = reset_cause_q;
+ low_power_d = low_power_q;
+ fetch_en_d = fetch_en_q;
+
+ unique case(state_q)
+
+ FastPwrStateLowPower: begin
+ if (req_pwrup_i || reset_ongoing_q) begin
+ state_d = FastPwrStateEnableClocks;
+ end
+ end
+
+ FastPwrStateEnableClocks: begin
+ ip_clk_en_d = 1'b1;
+ if (clks_enabled) begin
+ state_d = FastPwrStateReleaseLcRst;
+ end
+ end
+
+ FastPwrStateReleaseLcRst: begin
+ rst_lc_req_d = '0; // release rst_lc_n for all power domains
+ rst_sys_req_d = '0; // release rst_sys_n for all power domains
+ // once all resets are released continue to otp initilization
+ if (&pwr_rst_i.rst_lc_src_n) begin
+ state_d = FastPwrStateOtpInit;
+ end
+ end
+
+ FastPwrStateOtpInit: begin
+ otp_init = 1'b1;
+
+ if (otp_done_i) begin
+ state_d = FastPwrStateLcInit;
+ end
+ end
+
+ FastPwrStateLcInit: begin
+ lc_init = 1'b1;
+
+ if (lc_done) begin
+ state_d = FastPwrStateAckPwrUp;
+
+ end
+ end
+
+ FastPwrStateAckPwrUp: begin
+ // only ack the slow_fsm if we actually transitioned through it
+ ack_pwrup_d = !reset_ongoing_q;
+
+ // wait for request power up to drop relative to ack
+ if (!req_pwrup_i || reset_ongoing_q) begin
+ ack_pwrup_d = 1'b0;
+ clr_cfg_lock_o = 1'b1;
+ // generate a wakeup interrupt if we intended to go to low power
+ // and we were woken from low power with a wakeup and not reset
+ wkup_o = (pwrup_cause_i == Wake) & (reset_cause_q == LowPwrEntry);
+ // This constitutes the end of a reset cycle
+ reset_ongoing_d = 1'b0;
+ state_d = FastPwrStateStrap;
+ end
+ end
+
+ FastPwrStateStrap: begin
+ strap_o = ~strap_sampled;
+ state_d = FastPwrStateRomCheckDone;
+ end
+
+ FastPwrStateRomCheckDone: begin
+ // zero outgoing low power indication
+ low_power_d = '0;
+ reset_cause_d = ResetNone;
+
+ // When done is observed, advance to good check
+ if (mubi4_test_true_strict(rom_intg_chk_done)) begin
+ state_d = FastPwrStateRomCheckGood;
+ end
+ end
+
+ FastPwrStateRomCheckGood: begin
+ if (mubi4_test_true_strict(rom_intg_chk_good)) begin
+ state_d = FastPwrStateActive;
+ end
+ end
+
+ FastPwrStateActive: begin
+ // only in active state, allow processor to execute
+ fetch_en_d = lc_ctrl_pkg::On;
+
+ // when handling reset request or low power entry of any
+ // kind, stop processor from fetching
+ if (reset_req || low_power_entry_i) begin
+ fetch_en_d = lc_ctrl_pkg::Off;
+ reset_cause_d = ResetUndefined;
+ state_d = FastPwrStateDisClks;
+ end
+ end
+
+ FastPwrStateDisClks: begin
+ ip_clk_en_d = 1'b0;
+
+ if (clks_disabled) begin
+ state_d = reset_req ? FastPwrStateNvmShutDown : FastPwrStateFallThrough;
+ low_power_d = ~reset_req;
+ end else begin
+ // escalation was received, skip all handshaking and directly reset
+ state_d = direct_rst_req ? FastPwrStateNvmShutDown : state_q;
+ low_power_d = ~reset_req;
+ end
+ end
+
+ // Low Power Path
+ FastPwrStateFallThrough: begin
+ clr_hint_o = 1'b1;
+
+ // The processor was interrupted after it asserted WFI and is executing again
+ if (!low_power_entry_i) begin
+ ip_clk_en_d = 1'b1;
+ wkup_o = 1'b1;
+ fall_through_o = 1'b1;
+ state_d = FastPwrStateRomCheckDone;
+ end else begin
+ state_d = FastPwrStateNvmIdleChk;
+ end
+ end
+
+ FastPwrStateNvmIdleChk: begin
+
+ if (otp_idle_i && lc_idle_i && flash_idle_i) begin
+ state_d = FastPwrStateLowPowerPrep;
+ end else begin
+ ip_clk_en_d = 1'b1;
+ wkup_o = 1'b1;
+ abort_o = 1'b1;
+ state_d = FastPwrStateRomCheckDone;
+ end
+ end
+
+ FastPwrStateLowPowerPrep: begin
+ // reset cause is set only if main power domain will be turned off
+ reset_cause_d = LowPwrEntry;
+
+ // reset non-always-on domains if requested
+ // this includes the clock manager, which implies pwr/rst managers must
+ // be fed directly from the source
+ for (int i = OffDomainSelStart; i < PowerDomains; i++) begin
+ rst_lc_req_d[i] = ~main_pd_ni;
+ rst_sys_req_d[i] = ~main_pd_ni;
+ end
+
+ if (reset_valid) begin
+ state_d = FastPwrStateReqPwrDn;
+ end
+ end
+
+ FastPwrStateReqPwrDn: begin
+ req_pwrdn_d = 1'b1;
+
+ if (ack_pwrdn_i) begin
+ req_pwrdn_d = 1'b0;
+ state_d = FastPwrStateLowPower;
+ end
+ end
+
+ // Reset Path
+ FastPwrStateNvmShutDown: begin
+ clr_hint_o = 1'b1;
+ reset_ongoing_d = 1'b1;
+ state_d = FastPwrStateResetPrep;
+ end
+
+ FastPwrStateResetPrep: begin
+ reset_cause_d = HwReq;
+ rst_lc_req_d = {PowerDomains{1'b1}};
+ rst_sys_req_d = {PowerDomains{(hw_rst_req |
+ direct_rst_req |
+ sw_rst_req) |
+ (ndmreset_req &
+ lc_ctrl_pkg::lc_tx_test_false_loose(lc_dft_en_i))}};
+
+
+ state_d = FastPwrStateResetWait;
+ end
+
+ FastPwrStateResetWait: begin
+ rst_lc_req_d = {PowerDomains{1'b1}};
+ clr_slow_req_o = reset_reqs_i[ResetMainPwrIdx];
+ // The main power reset request is checked here specifically because it is
+ // the only reset request in the system that operates on the POR domain.
+ // This has to be the case since it would otherwise not be able to monitor
+ // the non-always-on domains.
+ //
+ // As a result of this, the normal reset process does not automatically
+ // wipe out the reset request, so we specifically clear it and wait for it to be
+ // cleared before proceeding. This also implies if the system is under a persistent
+ // glitch, or if someone just turned off the power before pwrmgr turns it off itself,
+ // we will stay stuck here and perpetually hold the system in reset.
+ if (reset_valid && !reset_reqs_i[ResetMainPwrIdx]) begin
+ state_d = FastPwrStateLowPower;
+ end
+ end
+
+
+ // Terminal state, kill everything
+ // SEC_CM: FSM.TERMINAL
+ default: begin
+ rst_lc_req_d = {PowerDomains{1'b1}};
+ rst_sys_req_d = {PowerDomains{1'b1}};
+ ip_clk_en_d = 1'b0;
+ end
+ endcase // unique case (state_q)
+
+ if (fsm_invalid_i) begin
+ // the slow fsm is completely out of sync, transition to terminal state
+ state_d = FastPwrStateInvalid;
+ end
+
+
+ end // always_comb
+
+ assign ack_pwrup_o = ack_pwrup_q;
+ assign req_pwrdn_o = req_pwrdn_q;
+ assign low_power_o = low_power_q;
+
+ assign pwr_rst_o.rst_lc_req = rst_lc_req_q;
+ assign pwr_rst_o.rst_sys_req = rst_sys_req_q;
+ assign pwr_rst_o.reset_cause = reset_cause_q;
+ assign pwr_rst_o.rstreqs = reset_reqs_i[HwResetWidth-1:0];
+
+ // main and io clocks are only turned on/off as part of normal
+ // power sequence
+ assign ips_clk_en_o.main_ip_clk_en = ip_clk_en_q;
+ assign ips_clk_en_o.io_ip_clk_en = ip_clk_en_q;
+ assign ips_clk_en_o.smc_ip_clk_en = ip_clk_en_q;
+ assign ips_clk_en_o.ml_ip_clk_en = ip_clk_en_q;
+ assign ips_clk_en_o.video_ip_clk_en = ip_clk_en_q;
+ assign ips_clk_en_o.audio_ip_clk_en = ip_clk_en_q;
+ prim_flop #(
+ .Width(1),
+ .ResetValue(1'b0)
+ ) u_usb_ip_clk_en (
+ .clk_i,
+ .rst_ni,
+ .d_i(ip_clk_en_d & usb_ip_clk_en_i),
+ .q_o(ips_clk_en_o.usb_ip_clk_en)
+ );
+ assign usb_ip_clk_status_o = clk_en_status_i.usb_status;
+
+ prim_flop #(
+ .Width(1),
+ .ResetValue(1'b0)
+ ) u_reg_otp_init (
+ .clk_i,
+ .rst_ni,
+ .d_i(otp_init),
+ .q_o(otp_init_o)
+ );
+
+ prim_flop #(
+ .Width(1),
+ .ResetValue(1'b0)
+ ) u_reg_lc_init (
+ .clk_i,
+ .rst_ni,
+ .d_i(lc_init),
+ .q_o(lc_init_o)
+ );
+
+
+endmodule
diff --git a/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_pkg.sv
new file mode 100644
index 0000000..26e704f
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_pkg.sv
@@ -0,0 +1,318 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Power Manager Package
+//
+
+package pwrmgr_pkg;
+
+ // global constant
+ parameter int ALWAYS_ON_DOMAIN = 0;
+
+ // variables referenced by other modules / packages
+ parameter int PowerDomains = 2; // this needs to be a topgen populated number, or from topcfg?
+
+ // variables referenced only by pwrmgr
+ localparam int TotalWakeWidth = pwrmgr_reg_pkg::NumWkups + 2; // Abort and fall through are added
+
+ parameter int NumSwRstReq = 1;
+
+ // position of escalation request
+ parameter int HwResetWidth = pwrmgr_reg_pkg::NumRstReqs +
+ pwrmgr_reg_pkg::NumIntRstReqs +
+ pwrmgr_reg_pkg::NumDebugRstReqs;
+ parameter int TotalResetWidth = HwResetWidth + NumSwRstReq;
+ parameter int ResetSwReqIdx = TotalResetWidth - 1;
+
+ // pwrmgr to ast
+ typedef struct packed {
+ logic main_pd_n;
+ logic pwr_clamp_env;
+ logic pwr_clamp;
+ logic slow_clk_en;
+ logic core_clk_en;
+ logic io_clk_en;
+ logic usb_clk_en;
+ logic smc_clk_en;
+ logic ml_clk_en;
+ logic video_clk_en;
+ logic audio_clk_en;
+ } pwr_ast_req_t;
+
+ typedef struct packed {
+ logic slow_clk_val;
+ logic core_clk_val;
+ logic io_clk_val;
+ logic usb_clk_val;
+ logic main_pok;
+ logic smc_clk_val;
+ logic ml_clk_val;
+ logic video_clk_val;
+ logic audio_clk_val;
+ } pwr_ast_rsp_t;
+
+ // default value of pwr_ast_rsp (for dangling ports)
+ parameter pwr_ast_rsp_t PWR_AST_RSP_DEFAULT = '{
+ slow_clk_val: 1'b1,
+ core_clk_val: 1'b1,
+ io_clk_val: 1'b1,
+ usb_clk_val: 1'b1,
+ main_pok: 1'b1,
+ smc_clk_val: 1'b1,
+ ml_clk_val: 1'b1,
+ video_clk_val: 1'b1,
+ audio_clk_val: 1'b1
+ };
+
+ parameter pwr_ast_rsp_t PWR_AST_RSP_SYNC_DEFAULT = '{
+ slow_clk_val: 1'b0,
+ core_clk_val: 1'b0,
+ io_clk_val: 1'b0,
+ usb_clk_val: 1'b0,
+ main_pok: 1'b0,
+ smc_clk_val: 1'b0,
+ ml_clk_val: 1'b0,
+ video_clk_val: 1'b0,
+ audio_clk_val: 1'b0
+ };
+
+ // reasons for pwrmgr reset
+ typedef enum logic [1:0] {
+ ResetNone = 0, // there is no reset
+ LowPwrEntry = 1, // reset is caused by low power entry
+ HwReq = 2, // reset is caused by peripheral reset requests
+ ResetUndefined = 3 // this should never happen outside of POR
+ } reset_cause_e;
+
+ // pwrmgr to rstmgr
+ typedef struct packed {
+ logic [PowerDomains-1:0] rst_lc_req;
+ logic [PowerDomains-1:0] rst_sys_req;
+ logic [HwResetWidth-1:0] rstreqs;
+ reset_cause_e reset_cause;
+ } pwr_rst_req_t;
+
+ // rstmgr to pwrmgr
+ typedef struct packed {
+ logic [PowerDomains-1:0] rst_lc_src_n;
+ logic [PowerDomains-1:0] rst_sys_src_n;
+ } pwr_rst_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_rst_rsp_t PWR_RST_RSP_DEFAULT = '{
+ rst_lc_src_n: {PowerDomains{1'b1}},
+ rst_sys_src_n: {PowerDomains{1'b1}}
+ };
+
+ // pwrmgr to clkmgr
+ typedef struct packed {
+ logic main_ip_clk_en;
+ logic io_ip_clk_en;
+ logic usb_ip_clk_en;
+ logic smc_ip_clk_en;
+ logic ml_ip_clk_en;
+ logic video_ip_clk_en;
+ logic audio_ip_clk_en;
+ } pwr_clk_req_t;
+
+ // clkmgr to pwrmgr
+ typedef struct packed {
+ logic main_status;
+ logic io_status;
+ logic usb_status;
+ logic smc_status;
+ logic ml_status;
+ logic video_status;
+ logic audio_status;
+ } pwr_clk_rsp_t;
+
+ // pwrmgr to otp
+ typedef struct packed {
+ logic otp_init;
+ } pwr_otp_req_t;
+
+ // otp to pwrmgr
+ typedef struct packed {
+ logic otp_done;
+ logic otp_idle;
+ } pwr_otp_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_otp_rsp_t PWR_OTP_RSP_DEFAULT = '{
+ otp_done: 1'b1,
+ otp_idle: 1'b1
+ };
+
+ // pwrmgr to lifecycle
+ typedef struct packed {
+ logic lc_init;
+ } pwr_lc_req_t;
+
+ // lifecycle to pwrmgr
+ typedef struct packed {
+ logic lc_done;
+ logic lc_idle;
+ } pwr_lc_rsp_t;
+
+ // default value (for dangling ports)
+ parameter pwr_lc_rsp_t PWR_LC_RSP_DEFAULT = '{
+ lc_done: 1'b1,
+ lc_idle: 1'b1
+ };
+
+ typedef struct packed {
+ logic flash_idle;
+ } pwr_flash_t;
+
+ parameter pwr_flash_t PWR_FLASH_DEFAULT = '{
+ flash_idle: 1'b1
+ };
+
+ // processor to pwrmgr
+ typedef struct packed {
+ logic core_sleeping;
+ } pwr_cpu_t;
+
+ // cpu reset requests and status
+ typedef struct packed {
+ logic ndmreset_req;
+ } pwrmgr_cpu_t;
+
+ // exported resets
+
+ // default value for pwrmgr_ast_rsp_t (for dangling ports)
+ parameter pwrmgr_cpu_t PWRMGR_CPU_DEFAULT = '{
+ ndmreset_req: '0
+ };
+
+ // default value (for dangling ports)
+ parameter pwr_cpu_t PWR_CPU_DEFAULT = '{
+ core_sleeping: 1'b0
+ };
+
+ // default value (for dangling ports)
+ parameter int WAKEUPS_DEFAULT = '0;
+ parameter int RSTREQS_DEFAULT = '0;
+
+ // peripherals to pwrmgr
+ typedef struct packed {
+ logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups;
+ // reset requests include external requests + escalation reset
+ logic [TotalResetWidth-1:0] rstreqs;
+ } pwr_peri_t;
+
+ // power-up causes
+ typedef enum logic [1:0] {
+ Por = 2'h0,
+ Wake = 2'h1,
+ Reset = 2'h2
+ } pwrup_cause_e;
+
+ // low power hints
+ typedef enum logic {
+ None = 1'b0,
+ LowPower = 1'b1
+ } low_power_hint_e;
+
+ // fast fsm state enum
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 19 -n 12 \
+ // -s 3096160381 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: ||||||||||||||||| (30.99%)
+ // 6: |||||||||||||||||||| (35.09%)
+ // 7: ||||||||| (15.79%)
+ // 8: |||||| (10.53%)
+ // 9: ||| (5.85%)
+ // 10: | (1.75%)
+ // 11: --
+ // 12: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 10
+ // Minimum Hamming weight: 2
+ // Maximum Hamming weight: 10
+ //
+ localparam int FastPwrStateWidth = 12;
+ typedef enum logic [FastPwrStateWidth-1:0] {
+ FastPwrStateLowPower = 12'b000000110111,
+ FastPwrStateEnableClocks = 12'b101011001110,
+ FastPwrStateReleaseLcRst = 12'b100111000000,
+ FastPwrStateOtpInit = 12'b111110100010,
+ FastPwrStateLcInit = 12'b101001010011,
+ FastPwrStateStrap = 12'b110000111010,
+ FastPwrStateAckPwrUp = 12'b000010101000,
+ FastPwrStateRomCheckDone = 12'b010111110011,
+ FastPwrStateRomCheckGood = 12'b010000000100,
+ FastPwrStateActive = 12'b001101100100,
+ FastPwrStateDisClks = 12'b001110010101,
+ FastPwrStateFallThrough = 12'b011011010000,
+ FastPwrStateNvmIdleChk = 12'b100101111001,
+ FastPwrStateLowPowerPrep = 12'b010110001111,
+ FastPwrStateNvmShutDown = 12'b001100001010,
+ FastPwrStateResetPrep = 12'b011001101111,
+ FastPwrStateResetWait = 12'b111111111100,
+ FastPwrStateReqPwrDn = 12'b111010001001,
+ FastPwrStateInvalid = 12'b110101010110
+ } fast_pwr_state_e;
+
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 12 -n 10 \
+ // -s 1726685338 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (54.55%)
+ // 6: |||||||||||||||| (45.45%)
+ // 7: --
+ // 8: --
+ // 9: --
+ // 10: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 6
+ // Minimum Hamming weight: 2
+ // Maximum Hamming weight: 8
+ //
+ localparam int SlowPwrStateWidth = 10;
+ typedef enum logic [SlowPwrStateWidth-1:0] {
+ SlowPwrStateReset = 10'b0000100010,
+ SlowPwrStateLowPower = 10'b1011000111,
+ SlowPwrStateMainPowerOn = 10'b0110101111,
+ SlowPwrStatePwrClampOff = 10'b0110010001,
+ SlowPwrStateClocksOn = 10'b1010111100,
+ SlowPwrStateReqPwrUp = 10'b0011011010,
+ SlowPwrStateIdle = 10'b1111100000,
+ SlowPwrStateAckPwrDn = 10'b0001110101,
+ SlowPwrStateClocksOff = 10'b1101111011,
+ SlowPwrStatePwrClampOn = 10'b0101001100,
+ SlowPwrStateMainPowerOff = 10'b1000001001,
+ SlowPwrStateInvalid = 10'b1100010110
+ } slow_pwr_state_e;
+
+endpackage // pwrmgr_pkg
diff --git a/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv
new file mode 100644
index 0000000..50c4007
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv
@@ -0,0 +1,384 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Power Manager Slow FSM
+//
+
+`include "prim_assert.sv"
+
+module pwrmgr_slow_fsm import pwrmgr_pkg::*; (
+ input clk_i,
+ input rst_ni,
+ input rst_main_ni,
+
+ // sync'ed requests from peripherals
+ input wakeup_i,
+ input reset_req_i,
+
+ // interface with fast fsm
+ output logic req_pwrup_o,
+ output logic pwrup_cause_toggle_o,
+ output pwrup_cause_e pwrup_cause_o,
+ input ack_pwrup_i,
+ input req_pwrdn_i,
+ output logic ack_pwrdn_o,
+ output logic rst_req_o,
+ output logic fsm_invalid_o,
+ input clr_req_i,
+ output logic usb_ip_clk_en_o,
+ input usb_ip_clk_status_i,
+
+ // low power entry configuration
+ input main_pd_ni,
+ input io_clk_en_i,
+ input core_clk_en_i,
+ input usb_clk_en_lp_i,
+ input usb_clk_en_active_i,
+
+ // AST interface
+ input pwr_ast_rsp_t ast_i,
+ output pwr_ast_req_t ast_o
+);
+
+ slow_pwr_state_e state_q, state_d;
+
+ // All signals crossing over to other domain must be flopped
+ pwrup_cause_e cause_q, cause_d;
+ logic cause_toggle_q, cause_toggle_d;
+ logic req_pwrup_q, req_pwrup_d;
+ logic ack_pwrdn_q, ack_pwrdn_d;
+
+ logic clk_active;
+
+ // All power signals and signals going to analog logic are flopped to avoid transitional glitches
+ logic pd_nq, pd_nd;
+ logic pwr_clamp_q, pwr_clamp_d;
+ logic pwr_clamp_env_q, pwr_clamp_env_d;
+ logic core_clk_en_q, core_clk_en_d;
+ logic io_clk_en_q, io_clk_en_d;
+ logic usb_clk_en_q, usb_clk_en_d;
+ logic fsm_invalid_q, fsm_invalid_d;
+
+ logic all_clks_valid;
+ logic all_clks_invalid;
+
+ // when to monitor pok for instability
+ // These are monitored only in active and low power states
+ logic mon_main_pok;
+ logic set_main_pok;
+ logic async_main_pok_st;
+ logic main_pok_st;
+
+ // all clocks sources are valid
+ // if clocks (usb) not configured to be active, then just bypass check
+ assign all_clks_valid = ast_i.core_clk_val &
+ ast_i.io_clk_val &
+ (~usb_clk_en_active_i | ast_i.usb_clk_val) &
+ ast_i.smc_clk_val &
+ ast_i.ml_clk_val &
+ ast_i.video_clk_val &
+ ast_i.audio_clk_val ;
+
+ // usb clock state during low power is not completely controlled by
+ // input.
+ // if main_pd_ni is 0, (ie power will be turned off), then the low power
+ // state of usb is also off. If main_pd_ni is 1 (power will be kept on),
+ // then the low power state of usb is directly controlled.
+ logic usb_clk_en_lp;
+ assign usb_clk_en_lp = main_pd_ni & usb_clk_en_lp_i;
+
+ // all other clocks are also diasbled when power is turned off.
+ logic core_clk_en;
+ logic io_clk_en;
+ assign core_clk_en = main_pd_ni & core_clk_en_i;
+ assign io_clk_en = main_pd_ni & io_clk_en_i;
+
+ // if clocks were configured to turn off, make sure val is invalid
+ // if clocks were not configured to turn off, just bypass the check
+ assign all_clks_invalid = (core_clk_en | ~ast_i.core_clk_val) &
+ (io_clk_en | ~ast_i.io_clk_val) &
+ (usb_clk_en_lp | ~ast_i.usb_clk_val) &
+ (core_clk_en | ~ast_i.smc_clk_val) &
+ (core_clk_en | ~ast_i.ml_clk_val) &
+ (core_clk_en | ~ast_i.video_clk_val) &
+ (core_clk_en | ~ast_i.audio_clk_val);
+
+ // ensure that clock controls are constantly re-evaluated and not just
+ // in one specific state
+ // When fsm is invalid, force the clocks to be on such that the fast fsm
+ // can forcibly reset the system.
+ // In the event the clocks cannot be turned on even when forced, the fsm
+ // invalid signal forces power to turn off.
+ assign core_clk_en_d = fsm_invalid_q | (clk_active | core_clk_en);
+ assign io_clk_en_d = fsm_invalid_q | (clk_active | io_clk_en);
+ assign usb_clk_en_d = fsm_invalid_q | (clk_active ? usb_clk_en_active_i : usb_clk_en_lp);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ cause_q <= Por;
+ cause_toggle_q <= 1'b0;
+ pd_nq <= 1'b1;
+ pwr_clamp_q <= 1'b1;
+ pwr_clamp_env_q <= 1'b1;
+ core_clk_en_q <= 1'b0;
+ io_clk_en_q <= 1'b0;
+ usb_clk_en_q <= 1'b0;
+ req_pwrup_q <= 1'b0;
+ ack_pwrdn_q <= 1'b0;
+ fsm_invalid_q <= 1'b0;
+ end else begin
+ cause_q <= cause_d;
+ cause_toggle_q <= cause_toggle_d;
+ pd_nq <= pd_nd;
+ pwr_clamp_q <= pwr_clamp_d;
+ pwr_clamp_env_q <= pwr_clamp_env_d;
+ core_clk_en_q <= core_clk_en_d;
+ io_clk_en_q <= io_clk_en_d;
+ usb_clk_en_q <= usb_clk_en_d;
+ req_pwrup_q <= req_pwrup_d;
+ ack_pwrdn_q <= ack_pwrdn_d;
+ fsm_invalid_q <= fsm_invalid_d;
+ end
+ end
+
+ // SEC_CM: FSM.SPARSE
+ `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, slow_pwr_state_e, SlowPwrStateReset)
+
+ always_comb begin
+ state_d = state_q;
+ cause_d = cause_q;
+ pd_nd = pd_nq;
+ cause_toggle_d = cause_toggle_q;
+ pwr_clamp_d = pwr_clamp_q;
+ pwr_clamp_env_d = pwr_clamp_env_q;
+
+ req_pwrup_d = req_pwrup_q;
+ ack_pwrdn_d = ack_pwrdn_q;
+ fsm_invalid_d = fsm_invalid_q;
+
+ set_main_pok = '0;
+
+ clk_active = '0;
+
+ unique case(state_q)
+
+ SlowPwrStateReset: begin
+ state_d = SlowPwrStateMainPowerOn;
+ cause_d = Por;
+ end
+
+ SlowPwrStateLowPower: begin
+ // reset request behaves identically to a wakeup, other than the power-up cause being
+ // different
+ if (wakeup_i || reset_req_i) begin
+ state_d = SlowPwrStateMainPowerOn;
+ cause_toggle_d = ~cause_toggle_q;
+ cause_d = reset_req_i ? Reset : Wake;
+ end
+ end
+
+ SlowPwrStateMainPowerOn: begin
+ pd_nd = 1'b1;
+
+ if (main_pok_st) begin
+ set_main_pok = 1'b1;
+ pwr_clamp_env_d = 1'b0;
+ state_d = SlowPwrStatePwrClampOff;
+ end
+ end
+
+ SlowPwrStatePwrClampOff: begin
+ pwr_clamp_d = 1'b0;
+ state_d = SlowPwrStateClocksOn;
+ end
+
+ SlowPwrStateClocksOn: begin
+ clk_active = 1'b1;
+
+ if (all_clks_valid) begin
+ state_d = SlowPwrStateReqPwrUp;
+ end
+ end
+
+ SlowPwrStateReqPwrUp: begin
+ clk_active = 1'b1;
+ req_pwrup_d = 1'b1;
+
+ // req_pwrdn_i should be 0 here to indicate
+ // the request from the previous round has definitely completed
+ if (ack_pwrup_i && !req_pwrdn_i) begin
+ req_pwrup_d = 1'b0;
+ state_d = SlowPwrStateIdle;
+ end
+ end
+
+ SlowPwrStateIdle: begin
+ // ack_pwrup_i should be 0 here to indicate
+ // the ack from the previous round has definitively completed
+ clk_active = 1'b1;
+
+ if (req_pwrdn_i && !ack_pwrup_i) begin
+ state_d = SlowPwrStateAckPwrDn;
+ end
+ end
+
+ SlowPwrStateAckPwrDn: begin
+ clk_active = 1'b1;
+ ack_pwrdn_d = 1'b1;
+
+ if (!req_pwrdn_i) begin
+ ack_pwrdn_d = 1'b0;
+ state_d = SlowPwrStateClocksOff;
+ end
+ end
+
+ SlowPwrStateClocksOff: begin
+ if (all_clks_invalid) begin
+ // if main power is turned off, assert early clamp ahead
+ pwr_clamp_env_d = ~main_pd_ni;
+ state_d = SlowPwrStatePwrClampOn;
+ end
+ end
+
+ SlowPwrStatePwrClampOn: begin
+ // if main power is turned off, assert clamp ahead
+ pwr_clamp_d = pwr_clamp_env_q;
+ state_d = SlowPwrStateMainPowerOff;
+ end
+
+ SlowPwrStateMainPowerOff: begin
+ pd_nd = main_pd_ni;
+
+ // Proceed if power is already off, or if there was no intent to
+ // turn off the power.
+ if (!main_pok_st | main_pd_ni) begin
+ state_d = SlowPwrStateLowPower;
+ end
+ end
+
+ // Very terminal state, kill everything
+ // Signal the fast FSM if it somehow is still running.
+ // Both FSMs are now permanently out of sync and the device
+ // must be rebooted.
+ // SEC_CM: FSM.TERMINAL
+ default: begin
+ fsm_invalid_d = 1'b1;
+ pd_nd = 1'b0;
+ pwr_clamp_d = 1'b1;
+ end
+ endcase // unique case (state_q)
+ end // always_comb
+
+ // If the main_pok ever drops, capture that glitch
+ // and hold onto it for reset escalation
+ always_ff @(posedge clk_i or negedge rst_main_ni) begin
+ if (!rst_main_ni) begin
+ async_main_pok_st <= '0;
+ end else begin
+ async_main_pok_st <= ast_i.main_pok;
+ end
+ end
+
+ // We need to synchronize the above because the reset
+ // may cause the signal to change at any time.
+ prim_flop_2sync # (
+ .Width(1)
+ ) u_main_pok_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_main_pok_st),
+ .q_o(main_pok_st)
+ );
+
+ // Determine when pok should be monitored
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ mon_main_pok <= '0;
+ end else if (!pd_nd && mon_main_pok) begin
+ mon_main_pok <= 1'b0;
+ end else if (set_main_pok) begin
+ mon_main_pok <= 1'b1;
+ end
+ end
+
+ // power stability reset request
+ // If the main power becomes unstable for whatever reason,
+ // request reset
+ // SEC_CM: MAIN_PD.RST.LOCAL_ESC
+ logic pwr_rst_req;
+ assign pwr_rst_req = mon_main_pok & ~main_pok_st;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ rst_req_o <= '0;
+ end else if (clr_req_i) begin
+ rst_req_o <= '0;
+ end else begin
+ rst_req_o <= rst_req_o | pwr_rst_req;
+ end
+ end
+
+ assign pwrup_cause_o = cause_q;
+ assign pwrup_cause_toggle_o = cause_toggle_q;
+ assign req_pwrup_o = req_pwrup_q;
+ assign ack_pwrdn_o = ack_pwrdn_q;
+ assign fsm_invalid_o = fsm_invalid_q;
+
+ assign ast_o.core_clk_en = core_clk_en_q;
+ assign ast_o.io_clk_en = io_clk_en_q;
+ // TO-DO(pbf): check to see if need separate enable other than core_clk_en_q
+ // for following for new clocks.
+ assign ast_o.smc_clk_en = core_clk_en_q;
+ assign ast_o.ml_clk_en = core_clk_en_q;
+ assign ast_o.video_clk_en = core_clk_en_q;
+ assign ast_o.audio_clk_en = core_clk_en_q;
+ // usb's enable is handshake with pwr_fsm, as it can be turned on/off
+ // outside of the normal low power sequence
+ prim_flop #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_usb_clk_en (
+ .clk_i,
+ .rst_ni,
+ // immediate enable
+ // graceful disable when status is 0
+ .d_i(usb_clk_en_q | usb_ip_clk_status_i),
+ .q_o(ast_o.usb_clk_en)
+ );
+ assign usb_ip_clk_en_o = usb_clk_en_q;
+
+ assign ast_o.main_pd_n = pd_nq;
+ assign ast_o.pwr_clamp_env = pwr_clamp_env_q;
+ assign ast_o.pwr_clamp = pwr_clamp_q;
+ // This is hardwired to 1 all the time
+ assign ast_o.slow_clk_en = 1'b1;
+
+
+ ////////////////////////////
+ /// Unused
+ ////////////////////////////
+
+ logic unused_slow_clk_val;
+ assign unused_slow_clk_val = ast_i.slow_clk_val;
+
+ ////////////////////////////
+ /// Assertion
+ ////////////////////////////
+ // Under normal circumstances, this should NEVER fire
+ // May need to add a signal to disable this check for simulation
+ `ASSERT(IntRstReq_A, pwr_rst_req == '0)
+
+endmodule
diff --git a/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_wake_info.sv b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_wake_info.sv
new file mode 100644
index 0000000..d583dc3
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/rtl/pwrmgr_wake_info.sv
@@ -0,0 +1,86 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Power Manager Wake Information
+//
+
+`include "prim_assert.sv"
+
+module pwrmgr_wake_info import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;
+(
+ input clk_i,
+ input rst_ni,
+ input wr_i,
+ input [TotalWakeWidth-1:0] data_i,
+ input start_capture_i,
+ input record_dis_i,
+ input [NumWkups-1:0] wakeups_i,
+ input fall_through_i,
+ input abort_i,
+ output pwrmgr_hw2reg_wake_info_reg_t info_o
+);
+
+ logic record_en;
+
+ // detect rising edge of start_capture_i
+ logic start_capture_q1, start_capture;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ start_capture_q1 <= 1'b1;
+ end else begin
+ start_capture_q1 <= start_capture_i;
+ end
+ end
+
+ assign start_capture = start_capture_i & ~start_capture_q1;
+
+ // generate the record enbale signal
+ // HW enables the recording
+ // Software can suppress the recording or disable it
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ record_en <= 1'b0;
+ end else if (start_capture && !record_dis_i) begin
+ // if not disabled by software
+ // a recording enable puls by HW starts recording
+ record_en <= 1'b1;
+ end else if (record_dis_i && record_en) begin
+ // if recording is already ongoing
+ // a disable command by software shuts things down
+ record_en <= 1'b0;
+ end
+ end
+
+ logic [TotalWakeWidth-1:0] info;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ info <= '0;
+ end else if (wr_i) begin
+ info <= info & ~data_i; // W1C
+ end else if (record_en) begin // If set once, hold until clear
+ info[0 +: NumWkups] <= info[0 +: NumWkups] | wakeups_i;
+ info[NumWkups +: 2] <= info[NumWkups +: 2] | {abort_i, fall_through_i};
+ end
+ end
+
+ // assign outputs
+ assign info_o.abort.d = info[NumWkups + 1];
+ assign info_o.fall_through.d = info[NumWkups];
+ assign info_o.reasons = info[NumWkups-1:0];
+
+
+
+endmodule
diff --git a/hw/top_sencha/ip/pwrmgr/util/reg_pwrmgr.py b/hw/top_sencha/ip/pwrmgr/util/reg_pwrmgr.py
new file mode 100755
index 0000000..911b65d
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/util/reg_pwrmgr.py
@@ -0,0 +1,55 @@
+#!/usr/bin/env python3
+# Copyright 2024 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+r"""Convert mako template to Hjson register description
+"""
+import argparse
+import sys
+from io import StringIO
+
+from mako.template import Template
+
+
+def main():
+ parser = argparse.ArgumentParser(prog="reg_pwrmgr")
+ parser.add_argument('input',
+ nargs='?',
+ metavar='file',
+ type=argparse.FileType('r'),
+ default=sys.stdin,
+ help='input template file')
+ parser.add_argument('--n_wkups',
+ type=int,
+ default=16,
+ help='Number of Wakeup sources')
+
+ args = parser.parse_args()
+
+ # Determine output: if stdin then stdout if not then ??
+ out = StringIO()
+
+ reg_tpl = Template(args.input.read())
+ out.write(
+ reg_tpl.render(NumWkups=args.n_wkups))
+
+ print(out.getvalue())
+
+ out.close()
+
+
+if __name__ == "__main__":
+ main()
diff --git a/hw/top_sencha/ip/rstmgr/BUILD b/hw/top_sencha/ip/rstmgr/BUILD
new file mode 100644
index 0000000..500fb17
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/rstmgr/data:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/rstmgr/data/BUILD b/hw/top_sencha/ip/rstmgr/data/BUILD
new file mode 100644
index 0000000..b444b5d
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/data/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/rstmgr/data/autogen:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/rstmgr/data/autogen/BUILD b/hw/top_sencha/ip/rstmgr/data/autogen/BUILD
new file mode 100644
index 0000000..abe5846
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/data/autogen/BUILD
@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+load("@lowrisc_opentitan//rules:autogen.bzl", "autogen_hjson_header")
+
+autogen_hjson_header(
+ name = "rstmgr_regs",
+ srcs = [
+ "rstmgr.hjson",
+ ],
+)
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/ip/rstmgr/data/autogen/rstmgr.hjson b/hw/top_sencha/ip/rstmgr/data/autogen/rstmgr.hjson
new file mode 100644
index 0000000..46349fe
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/data/autogen/rstmgr.hjson
@@ -0,0 +1,581 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+
+# RSTMGR register template
+#
+{
+ name: "rstmgr",
+ human_name: "Reset Manager",
+ one_line_desc: "Controls the on-chip reset signals, records reset cause and CPU crash dump for software",
+ one_paragraph_desc: '''
+ Reset Manager controls the on-chip reset.
+ It receives one root power-on reset signal for each power domain from AST and feeds one reset signal for each on-chip reset domain to the OpenTitan hardware blocks.
+ Resets can be requested by Power Manager, which internally arbitrates peripheral resets, e.g., from AON Timer and Alert Handler, RISC-V Debug Module, and to a limited extent by software.
+ Through always-on registers, software can get information on the reset cause, as well as alert and CPU status prior to a triggered reset (crash dump).
+ To deter fault injection (FI) attacks, several countermeasures are implemented, including consistency checks of leaf resets and support for shadow resets.
+ '''
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_rstmgr",
+ revisions: [
+ {
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D2S",
+ verification_stage: "V2S",
+ dif_stage: "S2",
+ }
+ ]
+ clocking: [
+ {clock: "clk_i", reset: "rst_ni", primary: true},
+ {clock: "clk_aon_i"},
+ {clock: "clk_io_div4_i"},
+ {clock: "clk_main_i"},
+ {clock: "clk_io_i"},
+ {clock: "clk_io_div2_i"},
+ {clock: "clk_usb_i"},
+ {clock: "clk_smc_i"},
+ {clock: "clk_ml_i"},
+ {clock: "clk_video_i"},
+ {clock: "clk_audio_i"},
+ {clock: "clk_por_i", reset: "rst_por_ni"},
+ ]
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device" }
+ ],
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal structural fault is detected.
+ Structural faults include errors such as sparse fsm errors and tlul integrity errors.
+ '''
+ }
+ { name: "fatal_cnsty_fault",
+ desc: '''
+ This fatal alert is triggered when a reset consistency fault is detected.
+ It is separated from the category above for clearer error collection and debug.
+ '''
+ }
+ ],
+ countermeasures: [
+ { name: "BUS.INTEGRITY",
+ desc: "End-to-end bus integrity scheme."
+ }
+ { name: "SCAN.INTERSIG.MUBI",
+ desc: "scan control signals are multibit"
+ }
+ { name: "LEAF.RST.BKGN_CHK",
+ desc: "Background consistency checks for each leaf reset."
+ }
+ { name: "LEAF.RST.SHADOW",
+ desc: "Leaf resets to blocks containing shadow registers are shadowed"
+ }
+ { name: "LEAF.FSM.SPARSE",
+ desc: "Sparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets"
+ }
+ { name: "SW_RST.CONFIG.REGWEN",
+ desc: "Software reset controls are protected by regwen"
+ }
+ { name: "DUMP_CTRL.CONFIG.REGWEN",
+ desc: "Crash dump controls are protected by regwen"
+ }
+ ]
+ regwidth: "32",
+ scan: "true",
+ scan_reset: "true",
+ param_list: [
+ { name: "RdWidth",
+ desc: "Read width for crash info",
+ type: "int",
+ default: "32",
+ local: "true"
+ },
+
+ { name: "IdxWidth",
+ desc: "Index width for crash info",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+
+ { name: "NumHwResets",
+ desc: "Number of hardware reset requests, inclusive of debug resets and pwrmgr's internal resets ",
+ type: "int",
+ default: "5",
+ local: "true"
+ },
+
+ { name: "NumSwResets",
+ desc: "Number of software resets",
+ type: "int",
+ default: "14",
+ local: "true"
+ },
+
+ { name: "NumTotalResets",
+ desc: "Number of total reset requests, inclusive of hw/sw, por and low power exit",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+
+ { name: "SecCheck",
+ type: "bit",
+ default: "1'b1",
+ desc: '''
+ When 1, enable rstmgr reset consistency checks.
+ When 0, there are no consistency checks.
+ '''
+ local: "false",
+ expose: "true"
+ },
+
+ { name: "SecMaxSyncDelay",
+ type: "int",
+ default: "2",
+ desc: '''
+ The maximum synchronization delay for parent / child reset checks.
+ '''
+ local: "false",
+ expose: "true"
+ },
+ ],
+
+ // Define rstmgr struct package
+ inter_signal_list: [
+ { struct: "logic",
+ type: "uni",
+ name: "por_n",
+ act: "rcv",
+ width: "2"
+ desc: '''
+ Root power on reset signals from ast.
+ There is one root reset signal for each core power domain.
+ '''
+ },
+
+ { struct: "pwr_rst", // pwr_rst_req_t, pwr_rst_rsp_t
+ type: "req_rsp",
+ name: "pwr", // resets_o (req), resets_i (rsp)
+ act: "rsp",
+ desc: '''
+ Reset request signals from power manager.
+ Power manager can request for specific domains of the lc/sys reset tree to assert.
+ '''
+ },
+
+ { struct: "rstmgr_out",
+ type: "uni",
+ name: "resets",
+ act: "req",
+ package: "rstmgr_pkg", // Origin package (only needs for the req)
+ desc: '''
+ Leaf resets fed to the system.
+ '''
+ },
+
+ { struct: "rstmgr_rst_en",
+ type: "uni",
+ name: "rst_en",
+ act: "req",
+ package: "rstmgr_pkg", // Origin package (only needs for the req)
+ desc: '''
+ Low-power-group outputs used by alert handler.
+ '''
+ },
+
+ { struct: "alert_crashdump",
+ type: "uni",
+ name: "alert_dump",
+ act: "rcv",
+ package: "alert_pkg",
+ desc: '''
+ Alert handler crash dump information.
+ '''
+ },
+
+ { struct: "cpu_crash_dump",
+ type: "uni",
+ name: "cpu_dump",
+ act: "rcv",
+ package: "rv_core_ibex_pkg",
+ desc: '''
+ Main processing element crash dump information.
+ '''
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "sw_rst_req",
+ act: "req",
+ package: "prim_mubi_pkg",
+ desc: '''
+ Software requested system reset to pwrmgr.
+ '''
+ },
+
+ // Exported resets
+ ],
+
+ registers: [
+
+ { name: "RESET_REQ",
+ desc: '''
+ Software requested system reset.
+ ''',
+ swaccess: "rw",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "3:0",
+ mubi: true
+ name: "VAL",
+ desc: '''
+ When set to kMultiBitBool4True, a reset to power manager is requested.
+ Upon completion of reset, this bit is automatically cleared by hardware.
+ '''
+ resval: false
+ },
+ ],
+ tags: [// This register will cause a system reset, directed test only
+ "excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "RESET_INFO",
+ desc: '''
+ Device reset reason.
+ ''',
+ swaccess: "rw1c",
+ hwaccess: "hwo",
+ sync: "clk_por_i",
+ fields: [
+ { bits: "0",
+ hwaccess: "none",
+ name: "POR",
+ desc: '''
+ Indicates when a device has reset due to power up.
+ '''
+ resval: "1"
+ },
+
+ { bits: "1",
+ name: "LOW_POWER_EXIT",
+ desc: '''
+ Indicates when a device has reset due low power exit.
+ '''
+ resval: "0"
+ },
+
+ { bits: "2",
+ hwaccess: "hrw",
+ name: "SW_RESET",
+ desc: '''
+ Indicates when a device has reset due to !!RESET_REQ.
+ '''
+ resval: "0"
+ },
+
+ // reset requests include escalation reset, main power glitch,
+ // ndm reset request + other peripheral requests
+ { bits: "7:3",
+ hwaccess: "hrw",
+ name: "HW_REQ",
+ desc: '''
+ Indicates when a device has reset due to a hardware requested reset.
+ The bit mapping is as follows:
+ b3: sysrst_ctrl_aon: OpenTitan reset request to `rstmgr` (running on AON clock).
+ b4: aon_timer_aon: watchdog reset requestt
+ b5: pwrmgr_aon: main power glitch reset request
+ b6: alert_handler: escalation reset request
+ b7: rv_dm: non-debug-module reset request
+ '''
+ resval: "0"
+ },
+ ]
+ },
+
+ { name: "ALERT_REGWEN",
+ desc: "Alert write enable",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ resval: "1"
+ desc: '''
+ When 1, !!ALERT_INFO_CTRL can be modified.
+ '''
+ },
+ ]
+ }
+
+ { name: "ALERT_INFO_CTRL",
+ desc: '''
+ Alert info dump controls.
+ ''',
+ swaccess: "rw",
+ hwaccess: "hro",
+ sync: "clk_por_i",
+ regwen: "ALERT_REGWEN",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ hwaccess: "hrw",
+ desc: '''
+ Enable alert dump to capture new information.
+ This field is automatically set to 0 upon system reset (even if rstmgr is not reset).
+ '''
+ resval: "0"
+ },
+
+ { bits: "4+IdxWidth-1:4",
+ name: "INDEX",
+ desc: '''
+ Controls which 32-bit value to read.
+ '''
+ resval: "0"
+ },
+ ]
+ },
+
+ { name: "ALERT_INFO_ATTR",
+ desc: '''
+ Alert info dump attributes.
+ ''',
+ swaccess: "ro",
+ hwaccess: "hwo",
+ sync: "clk_por_i",
+ hwext: "true",
+ fields: [
+ { bits: "IdxWidth-1:0",
+ name: "CNT_AVAIL",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ desc: '''
+ The number of 32-bit values contained in the alert info dump.
+ '''
+ resval: "0",
+ tags: [// This field is tied to a design constant, thus the
+ // default value is never 0. Since there is not a way
+ // to express this behavior at the moment, exclude from automated checks.
+ "excl:CsrAllTests:CsrExclCheck"]
+ },
+ ]
+ },
+
+ { name: "ALERT_INFO",
+ desc: '''
+ Alert dump information prior to last reset.
+ Which value read is controlled by the !!ALERT_INFO_CTRL register.
+ ''',
+ swaccess: "ro",
+ hwaccess: "hwo",
+ sync: "clk_por_i",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ name: "VALUE",
+ desc: '''
+ The current 32-bit value of crash dump.
+ '''
+ resval: "0",
+ },
+ ]
+ },
+ { name: "CPU_REGWEN",
+ desc: "Cpu write enable",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ resval: "1"
+ desc: '''
+ When 1, !!CPU_INFO_CTRL can be modified.
+ '''
+ },
+ ]
+ }
+
+ { name: "CPU_INFO_CTRL",
+ desc: '''
+ Cpu info dump controls.
+ ''',
+ swaccess: "rw",
+ hwaccess: "hro",
+ sync: "clk_por_i",
+ regwen: "CPU_REGWEN",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ hwaccess: "hrw",
+ desc: '''
+ Enable cpu dump to capture new information.
+ This field is automatically set to 0 upon system reset (even if rstmgr is not reset).
+ '''
+ resval: "0"
+ },
+
+ { bits: "4+IdxWidth-1:4",
+ name: "INDEX",
+ desc: '''
+ Controls which 32-bit value to read.
+ '''
+ resval: "0"
+ },
+ ]
+ },
+
+ { name: "CPU_INFO_ATTR",
+ desc: '''
+ Cpu info dump attributes.
+ ''',
+ swaccess: "ro",
+ hwaccess: "hwo",
+ sync: "clk_por_i",
+ hwext: "true",
+ fields: [
+ { bits: "IdxWidth-1:0",
+ name: "CNT_AVAIL",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ desc: '''
+ The number of 32-bit values contained in the cpu info dump.
+ '''
+ resval: "0",
+ tags: [// This field is tied to a design constant, thus the
+ // default value is never 0. Since there is not a way
+ // to express this behavior at the moment, exclude from automated checks.
+ "excl:CsrAllTests:CsrExclCheck"]
+ },
+ ]
+ },
+
+ { name: "CPU_INFO",
+ desc: '''
+ Cpu dump information prior to last reset.
+ Which value read is controlled by the !!CPU_INFO_CTRL register.
+ ''',
+ swaccess: "ro",
+ hwaccess: "hwo",
+ sync: "clk_por_i",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ name: "VALUE",
+ desc: '''
+ The current 32-bit value of crash dump.
+ '''
+ resval: "0",
+ },
+ ]
+ },
+
+
+ # Templated registers for software control
+
+ { multireg: {
+ cname: "RSTMGR_SW_RST",
+ name: "SW_RST_REGWEN",
+ desc: '''
+ Register write enable for software controllable resets.
+ When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed.
+ When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.
+ ''',
+ count: "NumSwResets",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ {
+ bits: "0",
+ name: "EN",
+ desc: "Register write enable for software controllable resets",
+ resval: "1",
+ },
+ ],
+ }
+ }
+
+ { multireg: {
+ cname: "RSTMGR_SW_RST",
+ name: "SW_RST_CTRL_N",
+ desc: '''
+ Software controllable resets.
+ When a particular bit value is 0, the corresponding module is held in reset.
+ When a particular bit value is 1, the corresponding module is not held in reset.
+ ''',
+ count: "NumSwResets",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "SW_RST_REGWEN",
+ regwen_multi: true,
+ fields: [
+ {
+ bits: "0",
+ name: "VAL",
+ desc: "Software reset value",
+ resval: "1",
+ },
+ ],
+ tags: [// Don't reset other IPs as it will affect CSR access on these IPs.
+ // In addition, rapid flips of these bits can occasionally cause the reset
+ // consistency checkers to trigger alerts, which also update err_code bits.
+ "excl:CsrAllTests:CsrExclWrite"]
+ }
+ }
+
+ { name: "ERR_CODE",
+ desc: '''
+ A bit vector of all the errors that have occurred in reset manager
+ ''',
+ swaccess: "ro",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "REG_INTG_ERR",
+ desc: '''
+ The register file has experienced an integrity error.
+ '''
+ resval: "0"
+ },
+
+ { bits: "1",
+ name: "RESET_CONSISTENCY_ERR",
+ desc: '''
+ A inconsistent parent / child reset was observed.
+ '''
+ resval: "0"
+ },
+
+ { bits: "2",
+ name: "FSM_ERR",
+ desc: '''
+ Sparsely encoded fsm error.
+ '''
+ resval: "0"
+ },
+
+ ]
+ },
+ ]
+}
diff --git a/hw/top_sencha/ip/rstmgr/data/autogen/rstmgr_sec_cm_testplan.hjson b/hw/top_sencha/ip/rstmgr/data/autogen/rstmgr_sec_cm_testplan.hjson
new file mode 100644
index 0000000..05e5b0c
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/data/autogen/rstmgr_sec_cm_testplan.hjson
@@ -0,0 +1,108 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Security countermeasures testplan extracted from the IP Hjson using reggen.
+//
+// This testplan is auto-generated only the first time it is created. This is
+// because this testplan needs to be hand-editable. It is possible that these
+// testpoints can go out of date if the spec is updated with new
+// countermeasures. When `reggen` is invoked when this testplan already exists,
+// It checks if the list of testpoints is up-to-date and enforces the user to
+// make further manual updates.
+//
+// These countermeasures and their descriptions can be found here:
+// .../rstmgr/data/rstmgr.hjson
+//
+// It is possible that the testing of some of these countermeasures may already
+// be covered as a testpoint in a different testplan. This duplication is ok -
+// the test would have likely already been developed. We simply map those tests
+// to the testpoints below using the `tests` key.
+//
+// Please ensure that this testplan is imported in:
+// .../rstmgr/data/rstmgr_testplan.hjson
+{
+ testpoints: [
+ {
+ name: sec_cm_bus_integrity
+ desc: '''Verify the countermeasure(s) BUS.INTEGRITY.
+ This entry is covered by tl_access_test.
+ '''
+ milestone: V2S
+ tests: ["rstmgr_tl_intg_err"]
+ }
+ {
+ name: sec_cm_scan_intersig_mubi
+ desc: '''Verify the countermeasure(s) SCAN.INTERSIG.MUBI.
+
+ **Stimulus**:
+ Same as smoke test but drive scanmode_i with a constant invalid
+ value during the test.
+
+ **Check**:
+ If dut accepts any of invalid values, test will fail by turning dut to scanmode.
+ '''
+ milestone: V2S
+ tests: ["rstmgr_sec_cm_scan_intersig_mubi"]
+ }
+ {
+ name: sec_cm_leaf_rst_bkgn_chk
+ desc: '''Verify the countermeasure(s) LEAF.RST.BKGN_CHK.
+
+ ** Stimulus**:
+ Execute a series of reset event - lowpower, hwreq, ndm, and
+ sw reset -. And at the beginning of these events, create
+ reset consistency error to one of 25 leaf modules.
+ (exclude u_daon_por_io_div4 and u_daon_por_io_div4_shadowed,
+ see #11858, #12729 for details)
+ Do the same test for all 25 modules.
+
+ **Check**:
+ Upon asserting each reset consistency error,
+ check alert_fatal_cnsty_fault is asserted.
+ '''
+ milestone: V2S
+ tests: ["rstmgr_leaf_rst_cnsty"]
+ }
+ {
+ name: sec_cm_leaf_rst_shadow
+ desc: '''Verify the countermeasure(s) LEAF.RST.SHADOW.
+ After power up, create glitch to a shadow leaf reset module.
+ Check if normal leaf reset module is not triggerred.
+ Do over all {shadow, normal} leaf reset module pairs
+ '''
+ milestone: V2S
+ tests: ["rstmgr_leaf_rst_shadow_attack"]
+ }
+ {
+ name: sec_cm_leaf_fsm_sparse
+ desc: '''Verify the countermeasure(s) LEAF.FSM.SPARSE.
+
+ Force leaf rst check state to illegal value.
+ This is triggered by common cm primitives
+ '''
+ milestone: V2S
+ tests: ["rstmgr_sec_cm"]
+ }
+ {
+ name: sec_cm_sw_rst_config_regwen
+ desc: '''Verify the countermeasure(s) SW_RST.CONFIG.REGWEN.
+
+ RSTMGR.SW_RST_CTRL_N.
+ This is covered by auto csr test.
+ '''
+ milestone: V2S
+ tests: ["rstmgr_csr_rw"]
+ }
+ {
+ name: sec_cm_dump_ctrl_config_regwen
+ desc: '''Verify the countermeasure(s) DUMP_CTRL.CONFIG.REGWEN.
+
+ RSTMGR.ALERT_INFO_CTRL and RSTMGR.CPU_INFO_CTRL
+ This is covered by auto csr test.
+ '''
+ milestone: V2S
+ tests: ["rstmgr_csr_rw"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/rstmgr/system_rstmgr.core b/hw/top_sencha/ip/rstmgr/system_rstmgr.core
new file mode 100644
index 0000000..e81339d
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/system_rstmgr.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:rstmgr:0.1"
+description: "Auto-generated reset manager for top_sencha"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:rstmgr_pkg
+ - lowrisc:prim:mubi
+ files:
+ - rtl/autogen/rstmgr.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/rstmgr/system_rstmgr_pkg.core b/hw/top_sencha/ip/rstmgr/system_rstmgr_pkg.core
new file mode 100644
index 0000000..d33872e
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/system_rstmgr_pkg.core
@@ -0,0 +1,22 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:rstmgr_pkg:0.1"
+description: "Auto-generated reset manager package for top_sencha"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:pwrmgr_pkg
+ - lowrisc:ip:rstmgr_reg
+ - lowrisc:ip_interfaces:alert_handler_reg
+ - lowrisc:ip:alert_handler_component
+ files:
+ - rtl/autogen/rstmgr_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/rstmgr/system_rstmgr_reg.core b/hw/top_sencha/ip/rstmgr/system_rstmgr_reg.core
new file mode 100644
index 0000000..a990915
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/system_rstmgr_reg.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:rstmgr_reg:0.1"
+description: "Auto-generated reset manager registers for top_sencha"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:tlul:headers
+ files:
+ - rtl/autogen/rstmgr_reg_pkg.sv
+ - rtl/autogen/rstmgr_reg_top.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/sensor_ctrl/BUILD b/hw/top_sencha/ip/sensor_ctrl/BUILD
new file mode 100644
index 0000000..146de63
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/BUILD
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]) + [
+ "//hw/top_sencha/ip/sensor_ctrl/data:all_files",
+ ],
+)
diff --git a/hw/top_sencha/ip/sensor_ctrl/README.md b/hw/top_sencha/ip/sensor_ctrl/README.md
new file mode 100644
index 0000000..25a219d
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/README.md
@@ -0,0 +1,17 @@
+# Sensor Control Technical Specification
+
+# Overview
+
+This document specifies the functionality of the `sensor control` module.
+The `sensor control` module is a comportable front-end to the [analog sensor top](../ast/README.md).
+
+It provides basic alert functionality, pad debug hook ups, and a small amount of open source visible status readback.
+Long term, this is a module that can be absorbed directly into the `analog sensor top`.
+
+## Features
+
+- Alert hand-shake with `analog sensor top`
+- Alert forwarding to `alert handler`
+- Status readback for `analog sensor top`
+- Pad debug hook up for `analog sensor top`
+- Wakeup based on alert events
diff --git a/hw/top_sencha/ip/sensor_ctrl/data/BUILD b/hw/top_sencha/ip/sensor_ctrl/data/BUILD
new file mode 100644
index 0000000..2136af1
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/data/BUILD
@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+load("@lowrisc_opentitan//rules:autogen.bzl", "autogen_hjson_header")
+
+package(default_visibility = ["//visibility:public"])
+
+autogen_hjson_header(
+ name = "sensor_ctrl_regs",
+ srcs = [
+ "sensor_ctrl.hjson",
+ ],
+)
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/ip/sensor_ctrl/data/sensor_ctrl.hjson b/hw/top_sencha/ip/sensor_ctrl/data/sensor_ctrl.hjson
new file mode 100644
index 0000000..9697902
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/data/sensor_ctrl.hjson
@@ -0,0 +1,268 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+# SENSOR_CTRL register template
+#
+{
+ name: "sensor_ctrl",
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_sensor_ctrl",
+ revisions: [
+ {
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D3",
+ // block level verification not planned
+ verification_stage: "N/A",
+ notes: "Verified at the top-level."
+ }
+ ]
+ clocking: [{clock: "clk_i", reset: "rst_ni", primary: true},
+ {clock: "clk_aon_i", reset: "rst_aon_ni"}],
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device" }
+ ],
+ available_output_list: [
+ { name: "ast_debug_out",
+ desc: "ast debug outputs to pinmux",
+ width: "9"
+ }
+ ],
+ interrupt_list: [
+ { name: "io_status_change",
+ desc: "io power status has changed",
+ }
+ { name: "init_status_change",
+ desc: "ast init status has changed",
+ }
+ ],
+ regwidth: "32",
+ param_list: [
+ { name: "NumAlertEvents",
+ type: "int",
+ default: "11",
+ desc: "Number of alert events from ast",
+ local: "true"
+ },
+ { name: "NumLocalEvents",
+ type: "int",
+ default: "1",
+ desc: "Number of local events",
+ local: "true"
+ },
+ { name: "NumAlerts",
+ type: "int",
+ default: "2",
+ desc: "Number of alerts sent from sensor control",
+ local: "true"
+ },
+ { name: "NumIoRails",
+ type: "int",
+ default: "2",
+ desc: "Number of IO rails",
+ local: "true"
+ },
+ ],
+
+ wakeup_list: [
+ { name: "wkup_req",
+ desc: "Raised if an alert event is seen during low power"
+ },
+ ],
+
+ alert_list: [
+ { name: "recov_alert",
+ desc: "recoverable sensor_ctrl alerts",
+ },
+ { name: "fatal_alert",
+ desc: "fatal sensor_ctrl alerts",
+ }
+ ]
+
+
+ // Define ast_struct package
+ inter_signal_list: [
+ { struct: "ast_alert",
+ type: "req_rsp",
+ name: "ast_alert",
+ act: "rsp",
+ package: "ast_pkg",
+ },
+
+ { struct: "ast_status",
+ type: "uni",
+ name: "ast_status",
+ act: "rcv",
+ package: "ast_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "ast_init_done",
+ act: "rcv",
+ package: "prim_mubi_pkg",
+ default: "prim_mubi_pkg::MuBi4True"
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "ast2pinmux",
+ act: "rcv",
+ width: 9,
+ package: ""
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "wkup_req",
+ act: "req",
+ package: ""
+ },
+ ],
+
+registers: [
+ { name: "CFG_REGWEN",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ desc: '''
+ Controls the configurability of !!FATAL_ALERT_EN register.
+ ''',
+
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Configuration enable.
+ ''',
+ resval: "1",
+ },
+ ]
+ },
+
+ { multireg: {
+ cname: "SENSOR_CTRL",
+ name: "ALERT_TRIG",
+ desc: "Alert trigger test",
+ count: "NumAlertEvents",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ Alert trigger for testing
+ 0 No alerts triggered
+ 1 Continuously trigger alert until disabled
+ For bit mapping, please see !!ALERT_TEST
+ ''',
+ resval: "0"
+ },
+ ],
+ tags: [// This register triggers alerts to fire and should be a directed test
+ "excl:CsrNonInitTests:CsrExclWrite"]
+ },
+ },
+
+ { multireg: {
+ cname: "SENSOR_CTRL",
+ name: "FATAL_ALERT_EN",
+ regwen: "CFG_REGWEN",
+ desc: '''
+ Each bit marks a corresponding alert as fatal or recoverable.
+ ''',
+ count: "NumAlertEvents",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ 1 - An alert event is fatal.
+ 0 - An alert event is recoverable.
+ ''',
+ resval: "0"
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "SENSOR_CTRL",
+ name: "RECOV_ALERT",
+ desc: '''
+ Each bit represents a recoverable alert that has been triggered by AST.
+ Since these are recoverable alerts, they can be cleared by software.
+ ''',
+ count: "NumAlertEvents",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ 1 - An alert event has been set
+ 0 - No alert event has been set
+ ''',
+ resval: "0"
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "SENSOR_CTRL",
+ name: "FATAL_ALERT",
+ desc: '''
+ Each bit represents a fatal alert that has been triggered by AST.
+ Since these registers represent fatal alerts, they cannot be cleared.
+
+ The lower bits are used for ast alert events.
+ The upper bits are used for local events.
+ ''',
+ count: "NumAlertEvents+NumLocalEvents",
+ swaccess: "ro",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ 1 - An alert event has been set
+ 0 - No alert event has been set
+ ''',
+ resval: "0"
+ },
+ ],
+ },
+ },
+
+ { name: "STATUS",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ desc: '''
+ Status readback for ast
+ ''',
+
+ fields: [
+ { bits: "0",
+ name: "ast_init_done",
+ desc: '''
+ AST has finished initializing
+ ''',
+ resval: "0",
+ },
+ { bits: "NumIoRails:1",
+ name: "io_pok",
+ desc: '''
+ IO power is ready
+ ''',
+ resval: "0",
+ },
+ ],
+ tags: [// The status readback depends on state of ast and do not always have a set value
+ "excl:CsrAllTests:CsrExclCheck"]
+ },
+ ]
+}
diff --git a/hw/top_sencha/ip/sensor_ctrl/data/sensor_ctrl.prj.hjson b/hw/top_sencha/ip/sensor_ctrl/data/sensor_ctrl.prj.hjson
new file mode 100644
index 0000000..7a64bf0
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/data/sensor_ctrl.prj.hjson
@@ -0,0 +1,20 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+{
+ name: "sensor_ctrl",
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ revisions: [
+ {
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D2",
+ // block level verification not planned
+ verification_stage: "N/A",
+ notes: "Verified at the top-level."
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/sensor_ctrl/doc/_index.md b/hw/top_sencha/ip/sensor_ctrl/doc/_index.md
new file mode 100644
index 0000000..14face1
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/doc/_index.md
@@ -0,0 +1,79 @@
+---
+title: "Sensor Control Technical Specification"
+---
+
+# Overview
+
+This document specifies the functionality of the sensor control module.
+The sensor control module is a comportable front-end to the [analog sensor top]({{< relref "hw/top_sencha/ip/ast/doc" >}}).
+
+It provides basic alert functionality, pad debug hook ups, and a small amount of open source visible status readback.
+Long term, this is a module that can be absorbed directly into the `analog sensor top`.
+
+## Features
+
+- Alert hand-shake with `analog sensor top`
+- Alert forwarding to `alert handler`
+- Status readback for `analog sensor top`
+- Pad debug hook up for `analog sensor top`
+- Wakeup based on alert events
+
+# Theory of Operations
+
+## Block Diagram
+
+The diagram below shows how `sensor control` helps `analog sensor top` integration into the overall design.
+
+## Recoverable and Fatal Alerts
+
+The `analog sensor top` sends alert requests in independent, differential form to the `sensor control`.
+Each alert request consists of a pair of signals, one active high and one active low.
+The active polarity of each signal is independent, due to the imprecise sensor timing that drives the alert.
+This means that the `sensor control` recognizes an active alert as long as one of the lines is active, and not the pair of signals being in a particular state.
+Each signal in the differential pair is thus a separate dedicated alert indicator.
+
+Once an alert request is detected as active, the `sensor control` formulates a proper alert event through the `prim_alert_sender` and sends a notification to the `alert handler`.
+
+The `sensor control` can optionally generate alert acknowledgements back to the `analog sensor top`.
+
+For each incoming alert, it can be programmed as fatal or recoverable through {{< regref "FATAL_ALERT_EN" >}}.
+If set to recoverable, an alert will be registered in {{< regref "RECOV_ALERT" >}} and the original `analog sensor top` event acknowledged.
+The acknowledgement prevents alerts from constantly being sent.
+
+If set to fatal, an alert will be registered in {{< regref "FATAL_ALERT" >}} but the original `analog sensor top` event will not be acknowledged.
+This causes the alert to constantly send until the system escalates in some form.
+
+## Wakeup Requests
+
+In addition to forwarding events to the `alert handler`, incoming events can also be aggregated into a wakeup request to the system.
+The `sensor_ctrl` does not make assumptions about its power domains and thus it is up to the integrating system to decide which power modes allow alert event wakeups.
+
+As an example, if the `sensor_ctrl` is not placed in an always on domain, then it cannot send alert based wakeups if the system is in a deep low power state.
+It will only be able to send wakeups when the system is powered and the `clk_aon_i` input is available.
+
+## Hardware Interfaces
+
+### Signals
+
+{{< incGenFromIpDesc "../data/sensor_ctrl.hjson" "hwcfg" >}}
+
+The table below lists other signals.
+
+Signal | Direction | Type | Description
+---------------------|------------------|----------------------------------------|---------------
+`ast_alert_i` | `input` | `ast_pkg::ast_alert_req_t` | Incoming alert requests from `analog sensor top`
+`ast_alert_o` | `output` | `ast_pkg::ast_alert_rsp_t` | Outgoing alert acknowledgments to `analog sensor top`
+`status_i` | `input` | `ast_pkg::ast_status_t` | Incoming `analog sensor top` status
+`ast2pinmux_i` | `input` | `logic [ast_pkg::Ast2PadOutWidth-1:0]` | Incoming `analog sensor top` debug output signals
+`cio_ast_debug_out` | `output` | `logic [ast_pkg::Ast2PadOutWidth-1:0]` | Outgoing `analog sensor top` debug output signals to `pinmux`
+
+# Programmer's Guide
+
+Each available alert has a corresponding fatality configuration.
+If an alert event is set to 1 in {{< regref "FATAL_ALERT_EN" >}}, `sensor_ctrl` treats it as a fatal event instead of a recoverable event.
+Fatal events are not acknowledged, and continuously send alert events in the system until some kind of escalation is seen.
+
+
+## Register Table
+
+{{< incGenFromIpDesc "../data/sensor_ctrl.hjson" "registers" >}}
diff --git a/hw/top_sencha/ip/sensor_ctrl/doc/checklist.md b/hw/top_sencha/ip/sensor_ctrl/doc/checklist.md
new file mode 100644
index 0000000..4a0be09
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/doc/checklist.md
@@ -0,0 +1,118 @@
+---
+title: "SENSOR_CTRL Checklist"
+---
+
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [SENSOR_CTRL peripheral.](../)
+All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
+
+## Design Checklist
+
+### D1
+
+Type | Item | Resolution | Note/Collaterals
+--------------|--------------------------------|-------------|------------------
+Documentation | [SPEC_COMPLETE][] | Done | [SENSOR_CTRL Design Spec](../)
+Documentation | [CSR_DEFINED][] | Done |
+RTL | [CLKRST_CONNECTED][] | Done |
+RTL | [IP_TOP][] | Done |
+RTL | [IP_INSTANTIABLE][] | Done |
+RTL | [PHYSICAL_MACROS_DEFINED_80][] | NA |
+RTL | [FUNC_IMPLEMENTED][] | Done |
+RTL | [ASSERT_KNOWN_ADDED][] | Done |
+Code Quality | [LINT_SETUP][] | Done |
+
+[SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec_complete" >}}
+[CSR_DEFINED]: {{<relref "/doc/project/checklist.md#csr_defined" >}}
+[CLKRST_CONNECTED]: {{<relref "/doc/project/checklist.md#clkrst_connected" >}}
+[IP_TOP]: {{<relref "/doc/project/checklist.md#ip_top" >}}
+[IP_INSTANTIABLE]: {{<relref "/doc/project/checklist.md#ip_instantiable" >}}
+[PHYSICAL_MACROS_DEFINED_80]: {{<relref "/doc/project/checklist.md#physical_macros_defined_80" >}}
+[FUNC_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#func_implemented" >}}
+[ASSERT_KNOWN_ADDED]: {{<relref "/doc/project/checklist.md#assert_known_added" >}}
+[LINT_SETUP]: {{<relref "/doc/project/checklist.md#lint_setup" >}}
+
+### D2
+
+Type | Item | Resolution | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES][] | Done |
+Documentation | [BLOCK_DIAGRAM][] | Done |
+Documentation | [DOC_INTERFACE][] | Done |
+Documentation | [MISSING_FUNC][] | Done |
+Documentation | [FEATURE_FROZEN][] | Done |
+RTL | [FEATURE_COMPLETE][] | Done |
+RTL | [AREA_CHECK][] | Done |
+RTL | [PORT_FROZEN][] | Done |
+RTL | [ARCHITECTURE_FROZEN][] | Done |
+RTL | [REVIEW_TODO][] | Done |
+RTL | [STYLE_X][] | Done |
+Code Quality | [LINT_PASS][] | Done |
+Code Quality | [CDC_SETUP][] | N/A | Pending CDC tool availability
+Code Quality | [FPGA_TIMING][] | Done |
+Code Quality | [CDC_SYNCMACRO][] | Done |
+Security | [SEC_CM_DOCUMENTED][] | N/A |
+Security | [SEC_RND_CNST][] | Done |
+
+[NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new_features" >}}
+[BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block_diagram" >}}
+[DOC_INTERFACE]: {{<relref "/doc/project/checklist.md#doc_interface" >}}
+[MISSING_FUNC]: {{<relref "/doc/project/checklist.md#missing_func" >}}
+[FEATURE_FROZEN]: {{<relref "/doc/project/checklist.md#feature_frozen" >}}
+[FEATURE_COMPLETE]: {{<relref "/doc/project/checklist.md#feature_complete" >}}
+[AREA_CHECK]: {{<relref "/doc/project/checklist.md#area_check" >}}
+[PORT_FROZEN]: {{<relref "/doc/project/checklist.md#port_frozen" >}}
+[ARCHITECTURE_FROZEN]: {{<relref "/doc/project/checklist.md#architecture_frozen" >}}
+[REVIEW_TODO]: {{<relref "/doc/project/checklist.md#review_todo" >}}
+[STYLE_X]: {{<relref "/doc/project/checklist.md#style_x" >}}
+[LINT_PASS]: {{<relref "/doc/project/checklist.md#lint_pass" >}}
+[CDC_SETUP]: {{<relref "/doc/project/checklist.md#cdc_setup" >}}
+[FPGA_TIMING]: {{<relref "/doc/project/checklist.md#fpga_timing" >}}
+[CDC_SYNCMACRO]: {{<relref "/doc/project/checklist.md#cdc_syncmacro" >}}
+[SEC_CM_DOCUMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_documented" >}}
+[SEC_RND_CNST]: {{<relref "/doc/project/checklist.md#sec_rnd_cnst" >}}
+
+### D2S
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|------------------------------|-------------|------------------
+Security | [SEC_CM_ASSETS_LISTED][] | N/A |
+Security | [SEC_CM_IMPLEMENTED][] | N/A |
+Security | [SEC_CM_RTL_REVIEWED][] | N/A |
+Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A |
+
+[SEC_CM_ASSETS_LISTED]: {{<relref "/doc/project/checklist.md#sec_cm_assets_listed" >}}
+[SEC_CM_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_implemented" >}}
+[SEC_CM_RTL_REVIEWED]: {{<relref "/doc/project/checklist.md#sec_cm_rtl_reviewed" >}}
+[SEC_CM_COUNCIL_REVIEWED]: {{<relref "/doc/project/checklist.md#sec_cm_council_reviewed" >}}
+
+### D3
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES_D3][] | Not Started |
+RTL | [TODO_COMPLETE][] | Not Started |
+Code Quality | [LINT_COMPLETE][] | Not Started |
+Code Quality | [CDC_COMPLETE][] | Not Started |
+Code Quality | [RDC_COMPLETE][] | Not Started |
+Review | [REVIEW_RTL][] | Not Started |
+Review | [REVIEW_DELETED_FF][] | Not Started |
+Review | [REVIEW_SW_CHANGE][] | Not Started |
+Review | [REVIEW_SW_ERRATA][] | Not Started |
+Review | Reviewer(s) | Not Started |
+Review | Signoff date | Not Started |
+
+[NEW_FEATURES_D3]: {{<relref "/doc/project/checklist.md#new_features_d3" >}}
+[TODO_COMPLETE]: {{<relref "/doc/project/checklist.md#todo_complete" >}}
+[LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#lint_complete" >}}
+[CDC_COMPLETE]: {{<relref "/doc/project/checklist.md#cdc_complete" >}}
+[RDC_COMPLETE]: {{<relref "/doc/project/checklist.md#rdc_complete" >}}
+[REVIEW_RTL]: {{<relref "/doc/project/checklist.md#review_rtl" >}}
+[REVIEW_DELETED_FF]: {{<relref "/doc/project/checklist.md#review_deleted_ff" >}}
+[REVIEW_SW_CHANGE]: {{<relref "/doc/project/checklist.md#review_sw_change" >}}
+[REVIEW_SW_ERRATA]: {{<relref "/doc/project/checklist.md#review_sw_errata" >}}
+
+## Verification Checklist
+
+Since sensor_ctrl is only a front end module for the AST, its verification is done
+at top level only.
+Please reference the top level testplan for more details.
diff --git a/hw/top_sencha/ip/sensor_ctrl/lint/sensor_ctrl.vlt b/hw/top_sencha/ip/sensor_ctrl/lint/sensor_ctrl.vlt
new file mode 100644
index 0000000..4fbffa6
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/lint/sensor_ctrl.vlt
@@ -0,0 +1,5 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// waiver file for sensor_ctrl
diff --git a/hw/top_sencha/ip/sensor_ctrl/lint/sensor_ctrl.waiver b/hw/top_sencha/ip/sensor_ctrl/lint/sensor_ctrl.waiver
new file mode 100644
index 0000000..cc54611
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/lint/sensor_ctrl.waiver
@@ -0,0 +1,14 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for sensor_ctrl
+
+waive -rules HIER_NET_NOT_READ -location {sensor_ctrl_reg_top.sv} -regexp {reg_wdata} \
+ -comment "No registers are 32 bits"
+
+waive -rules HIER_NET_NOT_READ -location {sensor_ctrl_reg_top.sv} -regexp {reg_be} \
+ -comment "No registers are 32 bits"
+
+waive -rules NOT_READ -location {sensor_ctrl_reg_top.sv} -regexp {reg_wdata} \
+ -comment "No registers are 32 bits"
diff --git a/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl.sv b/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl.sv
new file mode 100644
index 0000000..814b81f
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl.sv
@@ -0,0 +1,346 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// This is the integration wrapper layer for AST
+
+`include "prim_assert.sv"
+
+module sensor_ctrl
+ import sensor_ctrl_pkg::*;
+ import sensor_ctrl_reg_pkg::*;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
+ // Primary module clocks
+ input clk_i,
+ input rst_ni,
+ input clk_aon_i,
+ input rst_aon_ni,
+
+ // Bus Interface
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Interface from AST
+ input ast_pkg::ast_alert_req_t ast_alert_i,
+ output ast_pkg::ast_alert_rsp_t ast_alert_o,
+ input ast_pkg::ast_status_t ast_status_i,
+ input [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux_i,
+ input prim_mubi_pkg::mubi4_t ast_init_done_i,
+
+ // Interface to pinmux
+ output logic [ast_pkg::Ast2PadOutWidth-1:0] cio_ast_debug_out_o,
+ output logic [ast_pkg::Ast2PadOutWidth-1:0] cio_ast_debug_out_en_o,
+
+ // Interrutps
+ output logic intr_io_status_change_o,
+ output logic intr_init_status_change_o,
+
+ // Alerts
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
+ // wakeup to power manager
+ output logic wkup_req_o
+);
+
+ // The reg_pkg number of alerts and ast alerts must always match
+ `ASSERT_INIT(NumAlertsMatch_A, ast_pkg::NumAlerts == NumAlertEvents)
+
+ ///////////////////////////
+ // Incoming event synchronization - alerts can assert asynchronously
+ ///////////////////////////
+ logic [NumAlertEvents-1:0] async_alert_event_p, alert_event_p;
+ logic [NumAlertEvents-1:0] async_alert_event_n, alert_event_n;
+
+ for (genvar i = 0; i < NumAlertEvents; i++) begin : gen_alert_sync_assign
+ prim_sec_anchor_buf #(
+ .Width(2)
+ ) u_alert_in_buf (
+ .in_i({ast_alert_i.alerts[i].p,
+ ast_alert_i.alerts[i].n}),
+ .out_o({async_alert_event_p[i],
+ async_alert_event_n[i]})
+ );
+ end
+
+ prim_flop_2sync #(
+ .Width(NumAlertEvents),
+ .ResetValue('0)
+ ) u_alert_p_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_alert_event_p),
+ .q_o(alert_event_p)
+ );
+
+ prim_flop_2sync #(
+ .Width(NumAlertEvents),
+ .ResetValue({NumAlertEvents{1'b1}})
+ ) u_alert_n_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_alert_event_n),
+ .q_o(alert_event_n)
+ );
+
+
+ ///////////////////////////
+ // Register interface
+ ///////////////////////////
+ sensor_ctrl_reg2hw_t reg2hw;
+ sensor_ctrl_hw2reg_t hw2reg;
+ logic intg_err;
+
+ sensor_ctrl_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+ .tl_i,
+ .tl_o,
+ .reg2hw,
+ .hw2reg,
+ .intg_err_o(intg_err),
+ .devmode_i(1'b1)
+ );
+
+ ///////////////////////////
+ // Interrupt handling
+ ///////////////////////////
+
+ // io status change
+ logic [NumIoRails-1:0] io_rise;
+ logic [NumIoRails-1:0] io_fall;
+ prim_edge_detector #(
+ .Width(NumIoRails),
+ .EnSync(1)
+ ) u_io_status_chg (
+ .clk_i,
+ .rst_ni,
+ .d_i(ast_status_i.io_pok),
+ .q_sync_o(hw2reg.status.io_pok.d),
+ .q_posedge_pulse_o(io_rise),
+ .q_negedge_pulse_o(io_fall)
+ );
+
+ assign hw2reg.status.io_pok.de = 1'b1;
+
+ prim_intr_hw #(.Width(1)) u_io_intr (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (|{io_rise, io_fall}),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.io_status_change.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.io_status_change.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.io_status_change.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.io_status_change.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.io_status_change.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.io_status_change.d),
+ .intr_o (intr_io_status_change_o)
+ );
+
+ // init_done change
+ logic init_rise;
+ logic init_fall;
+ prim_edge_detector #(
+ .Width(1),
+ .EnSync(1)
+ ) u_init_chg (
+ .clk_i,
+ .rst_ni,
+ .d_i(prim_mubi_pkg::mubi4_test_true_strict(ast_init_done_i)),
+ .q_sync_o(hw2reg.status.ast_init_done.d),
+ .q_posedge_pulse_o(init_rise),
+ .q_negedge_pulse_o(init_fall)
+ );
+
+ prim_intr_hw #(.Width(1)) u_init_intr (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (|{init_rise, init_fall}),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.init_status_change.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.init_status_change.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.init_status_change.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.init_status_change.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.init_status_change.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.init_status_change.d),
+ .intr_o (intr_init_status_change_o)
+ );
+
+ assign hw2reg.status.ast_init_done.de = 1'b1;
+
+ ///////////////////////////
+ // Alert Event Handling
+ ///////////////////////////
+
+ logic [NumAlertEvents-1:0] event_vld, event_clr;
+
+ // While the alerts are differential, they are not perfectly aligned.
+ // Instead, each alert is treated independently.
+ always_comb begin
+ for (int i = 0; i < NumAlertEvents; i++) begin
+ event_vld[i] = alert_event_p[i] | ~alert_event_n[i];
+ end
+ end
+
+ // Only recoverable alerts are ack'd. Fatal alerts are captured and continuously
+ // triggered, there is thus not a need to ever acknowledge the source.
+ // For recoverable alerts, the ack is only sent once the alert is captured into software readable
+ // registers
+ logic [NumAlertEvents-1:0] recov_event;
+ logic [NumAlertEvents-1:0] fatal_event;
+ for (genvar i = 0; i < NumAlertEvents; i++) begin : gen_ast_alert_events
+
+ // when there is a valid alert, set the alert state
+ assign recov_event[i] = event_vld[i] & ~reg2hw.fatal_alert_en[i];
+ assign fatal_event[i] = event_vld[i] & reg2hw.fatal_alert_en[i];
+
+ assign hw2reg.recov_alert[i].d = 1'b1;
+ assign hw2reg.recov_alert[i].de = recov_event[i];
+
+ assign hw2reg.fatal_alert[i].d = 1'b1;
+ assign hw2reg.fatal_alert[i].de = fatal_event[i];
+
+ // only recoverable alerts ack
+ assign event_clr[i] = recov_event[i] & reg2hw.recov_alert[i].q;
+
+ end
+
+ // handle internal alert events, currently only have fatals
+ for (genvar i = NumAlertEvents; i < TotalEvents; i++) begin : gen_local_alert_events
+ assign hw2reg.fatal_alert[i].d = 1'b1;
+ assign hw2reg.fatal_alert[i].de = intg_err;
+ end
+
+ // Note, even though the incoming alerts are differential, they are NOT expected to be
+ // consistent all the time. It is more appropriate for sensor_ctrl to treat them as
+ // independent lines.
+ // As a result, the alert_ack is only applied if an incoming alert is set to the active polarity.
+ //
+
+ always_comb begin
+ for (int i = 0; i < NumAlertEvents; i++) begin
+ ast_alert_o.alerts_ack[i].p = alert_event_p[i] & event_clr[i];
+ ast_alert_o.alerts_ack[i].n = ~(~alert_event_n[i] & event_clr[i]);
+ end
+ end
+
+ // alert trigger for test
+ always_comb begin
+ for (int i = 0; i < NumAlertEvents; i++) begin
+ ast_alert_o.alerts_trig[i].p = reg2hw.alert_trig[i];
+ ast_alert_o.alerts_trig[i].n = ~reg2hw.alert_trig[i];
+ end
+ end
+
+
+ // alert test connection
+ logic [NumAlerts-1:0] alert_test;
+ assign alert_test[RecovAlert] = reg2hw.alert_test.recov_alert.qe &
+ reg2hw.alert_test.recov_alert.q;
+ assign alert_test[FatalAlert] = reg2hw.alert_test.fatal_alert.qe &
+ reg2hw.alert_test.fatal_alert.q;
+
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[RecovAlert]),
+ .IsFatal(0)
+ ) u_prim_recov_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i(alert_test[RecovAlert]),
+ .alert_req_i(|recov_event),
+ .alert_ack_o(),
+ .alert_state_o(),
+ .alert_rx_i(alert_rx_i[RecovAlert]),
+ .alert_tx_o(alert_tx_o[RecovAlert])
+ );
+
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[FatalAlert]),
+ .IsFatal(1)
+ ) u_prim_fatal_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i(alert_test[FatalAlert]),
+ .alert_req_i(|reg2hw.fatal_alert),
+ .alert_ack_o(),
+ .alert_state_o(),
+ .alert_rx_i(alert_rx_i[FatalAlert]),
+ .alert_tx_o(alert_tx_o[FatalAlert])
+ );
+
+ ///////////////////////////
+ // wakeup generation
+ ///////////////////////////
+
+ // wakeups are synchronized separately from the normal event handling.
+ // The alert handling is not synchronized through these below because
+ // the ack latency would be very long for no apparent gain.
+
+ logic async_wake;
+ logic unstable_wake_req;
+
+ // async wake combines ast inputs as well as recoverable alerts.
+ // This is because it is possible for alert events to arrive "right"
+ // on the boundary of low power. In the event this happens, the
+ // original event is immediately 'acked', making it possible for the
+ // sync flops below to miss the event. By mixing in recov_alert,
+ // we guarantee that if the event is caught by the regfile, it can also
+ // be used to trigger wake from low power.
+ // Fatal alerts are not used here because they do not ever ack, meaning
+ // the originating event can never disappear.
+ assign async_wake = (|async_alert_event_p) |
+ (~&async_alert_event_n) |
+ (|reg2hw.recov_alert);
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_wake_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_wake),
+ .q_o(unstable_wake_req)
+ );
+
+ logic [2:0] wake_req_filter;
+ always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
+ if (!rst_aon_ni) begin
+ wake_req_filter <= '0;
+ end else begin
+ wake_req_filter <= {wake_req_filter[1:0], unstable_wake_req};
+ end
+ end
+
+ // The filter is needed since the input is purely combinational
+ // among async events. The filter is thus used to ensure the
+ // wake indication is real and not a glitch.
+ always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
+ if (!rst_aon_ni) begin
+ wkup_req_o <= '0;
+ end else begin
+ wkup_req_o <= &wake_req_filter;
+ end
+ end
+
+ ///////////////////////////
+ // pinmux feedthrough to ast
+ ///////////////////////////
+
+ assign cio_ast_debug_out_o = ast2pinmux_i;
+ assign cio_ast_debug_out_en_o = '1;
+
+ // Alert assertions for reg_we onehot check
+ `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[FatalAlert])
+endmodule // sensor_ctrl
diff --git a/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl_pkg.sv b/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl_pkg.sv
new file mode 100644
index 0000000..b5b0bed
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl_pkg.sv
@@ -0,0 +1,28 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+
+package sensor_ctrl_pkg;
+
+ // alert position
+ parameter int RecovAlert = 0;
+ parameter int FatalAlert = 1;
+
+ // Total events
+ parameter int TotalEvents = sensor_ctrl_reg_pkg::NumAlertEvents +
+ sensor_ctrl_reg_pkg::NumLocalEvents;
+
+endpackage // sensor_ctrl_pkg
diff --git a/hw/top_sencha/ip/sensor_ctrl/sensor_ctrl.core b/hw/top_sencha/ip/sensor_ctrl/sensor_ctrl.core
new file mode 100644
index 0000000..2e24f7a
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/sensor_ctrl.core
@@ -0,0 +1,59 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:sensor_ctrl:0.1"
+description: "Sensor Control"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:prim:assert
+ - lowrisc:prim:edge_detector
+ - lowrisc:prim:mubi
+ - lowrisc:systems:sensor_ctrl_pkg
+ files:
+ - rtl/sensor_ctrl.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/sensor_ctrl.waiver
+ file_type: waiver
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - files_rtl
+ toplevel: sensor_ctrl
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_sencha/ip/sensor_ctrl/sensor_ctrl_pkg.core b/hw/top_sencha/ip/sensor_ctrl/sensor_ctrl_pkg.core
new file mode 100644
index 0000000..50bc7e5
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/sensor_ctrl_pkg.core
@@ -0,0 +1,22 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:sensor_ctrl_pkg:0.1"
+description: "Sensor Control Package"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:constants:top_pkg
+ - "!fileset_partner ? (lowrisc:systems:ast_pkg)"
+ - "fileset_partner ? (partner:systems:ast_pkg)"
+ - lowrisc:systems:sensor_ctrl_reg
+ files:
+ - rtl/sensor_ctrl_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/sensor_ctrl/sensor_ctrl_reg.core b/hw/top_sencha/ip/sensor_ctrl/sensor_ctrl_reg.core
new file mode 100644
index 0000000..71b57d2
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/sensor_ctrl_reg.core
@@ -0,0 +1,22 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:sensor_ctrl_reg:0.1"
+description: "Sensor Control Package"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:prim:all
+ - lowrisc:constants:top_pkg
+ files:
+ - rtl/sensor_ctrl_reg_pkg.sv
+ - rtl/sensor_ctrl_reg_top.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip/vc_top/data/vc_top.hjson b/hw/top_sencha/ip/vc_top/data/vc_top.hjson
new file mode 100644
index 0000000..f1b1dd2
--- /dev/null
+++ b/hw/top_sencha/ip/vc_top/data/vc_top.hjson
@@ -0,0 +1,178 @@
+// Opensource headers go here
+
+{ name: "vc_top",
+
+ clocking: [
+ {clock: "clk_i", reset: "rst_ni", primary: true},
+ ],
+ bus_interfaces: [
+
+ { protocol: "tlul", direction: "device", name: "core" }, // rename csr to core due to new check.
+ { protocol: "tlul", direction: "device", name: "imem" },
+ { protocol: "tlul", direction: "device", name: "dmem" }
+ ],
+
+ // As current opentitan build script, the registers set (state/enable/test) for each of interrupt
+ // added in below interrupt_list will only be added in the first tlul device defined in
+ // above bus_interface, i.e., "core".
+
+ interrupt_list: [
+ {
+ name: "host_req"
+ desc: "raised if the vc_top need to interrupt host."
+ }
+ {
+ name: "finish"
+ desc: "raised if the vc_top finishes task."
+ }
+ {
+ name: "instruction_fault"
+ desc: "raised if windowMMU instruction fetch faults."
+ }
+ {
+ name: "data_fault"
+ desc: "raised if windowMMU data memory access faults."
+ }
+ ],
+
+ param_list: [
+ { name: "vc_test_param",
+ type: "bit",
+ default: "0",
+ desc: "Test Param for VC_TOP"
+ local: "false",
+ expose: "true"
+ },
+ ],
+
+
+ regwidth: "32",
+
+ registers: {
+
+ core: [
+ { name: "CTRL",
+ desc: "Vector Core Top Control register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "freeze",
+ resval: 0x0
+ desc: "Writing a 1 will freeze the vector core clock"
+ }
+ { bits: "1",
+ name: "vc_reset",
+ resval: 0x0
+ desc: "Writing a 1 will reset the vector core. Writing a 0 will take it out of reset"
+ }
+ { bits: "18:2",
+ name: "pc_start",
+ resval: 0x0
+ desc: "Starting address for the PC when RV32IV is taken out of reset"
+ }
+ ]
+ },
+
+ { name: "MEMORY_BANK_CTRL"
+ desc: "Control register for the memory banks"
+ swaccess: "ro"
+ hwaccess: "hro"
+ fields: [
+ { bits: "3:0"
+ name: "i_mem_enable"
+ resval: 0xf
+ desc: "A value of 1 enables the specified imem bank"
+ }
+ { bits: "11:4"
+ name: "d_mem_enable"
+ resval: 0xff
+ desc: "A value of 1 enables the specified dmem bank"
+ }
+ ]
+ }
+
+ { name: "ERROR_STATUS",
+ desc: "Vector Core Top Error Status register",
+ swaccess: "rc",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "i_mem_out_of_range",
+ resval: 0x0
+ desc: "A value of 1 indicates an out of IMEM range access"
+ }
+ { bits: "1",
+ name: "d_mem_out_of_range",
+ resval: 0x0
+ desc: "A value of 1 indicates an out of DMEM range access"
+ }
+ { bits: "5:2",
+ name: "i_mem_disable_access",
+ resval: 0x0
+ desc: "A value of 1 indicates an access to a disabled IMEM bank"
+ }
+ { bits: "13:6",
+ name: "d_mem_disable_access",
+ resval: 0x0
+ desc: "A value of 1 indicates an access to a disabled DMEM bank"
+ }
+ ]
+ }
+
+ { name: "INIT_START",
+ desc: "Memory Initialization Start Address",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "21:0",
+ name: "address",
+ desc: "Starting Address for initialization."
+ resval: 0x0
+ }
+ { bits: "22",
+ name: "imem_dmem_sel"
+ desc: Specifies if IMem (0) or DMem (1) has to be initialized
+ resval: 0x0
+ }
+ ]
+ }
+
+ { name: "INIT_END",
+ desc: "Memory Initialization End Address",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "21:0",
+ name: "address",
+ desc: "Ending Address for initialization."
+ }
+ { bits: "22",
+ name: "valid"
+ desc: Writing a 1 triggers the initialization to start. HW clears this bit on completion
+ }
+ ]
+ }
+
+ { name: "INIT_STATUS",
+ desc: "Memory Initialization End Address",
+ swaccess: "rc",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "init_pending",
+ desc: "A value of 1 indicates an ongoing initialization operation"
+ }
+ { bits: "1",
+ name: "init_done"
+ //swaccess: rc
+ desc: Indicates init operation has completed
+ }
+ ]
+ }
+ ]
+
+ imem: []
+ dmem: []
+ }
+}
diff --git a/hw/top_sencha/ip/xbar_dbg/xbar_dbg.core b/hw/top_sencha/ip/xbar_dbg/xbar_dbg.core
new file mode 100644
index 0000000..69f5ea4
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/xbar_dbg.core
@@ -0,0 +1,25 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_dbg core file generated by `tlgen.py` tool
+name: "lowrisc:top_sencha:xbar_dbg:0.1"
+description: "Generated RTL xbar_dbg"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:ip:lc_ctrl_pkg
+ files:
+ - rtl/autogen/tl_dbg_pkg.sv
+ - rtl/autogen/xbar_dbg.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: xbar_dbg
diff --git a/hw/top_sencha/ip/xbar_main/xbar_main.core b/hw/top_sencha/ip/xbar_main/xbar_main.core
new file mode 100644
index 0000000..3426e55
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/xbar_main.core
@@ -0,0 +1,25 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_main core file generated by `tlgen.py` tool
+name: "lowrisc:top_sencha:xbar_main:0.1"
+description: "Generated RTL xbar_main"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:ip:lc_ctrl_pkg
+ files:
+ - rtl/autogen/tl_main_pkg.sv
+ - rtl/autogen/xbar_main.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: xbar_main
diff --git a/hw/top_sencha/ip/xbar_peri/xbar_peri.core b/hw/top_sencha/ip/xbar_peri/xbar_peri.core
new file mode 100644
index 0000000..f907f3f
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/xbar_peri.core
@@ -0,0 +1,25 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_peri core file generated by `tlgen.py` tool
+name: "lowrisc:top_sencha:xbar_peri:0.1"
+description: "Generated RTL xbar_peri"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:ip:lc_ctrl_pkg
+ files:
+ - rtl/autogen/tl_peri_pkg.sv
+ - rtl/autogen/xbar_peri.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: xbar_peri
diff --git a/hw/top_sencha/ip/xbar_smc/xbar_smc.core b/hw/top_sencha/ip/xbar_smc/xbar_smc.core
new file mode 100644
index 0000000..ea780b3
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/xbar_smc.core
@@ -0,0 +1,25 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_smc core file generated by `tlgen.py` tool
+name: "lowrisc:top_sencha:xbar_smc:0.1"
+description: "Generated RTL xbar_smc"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:ip:lc_ctrl_pkg
+ files:
+ - rtl/autogen/tl_smc_pkg.sv
+ - rtl/autogen/xbar_smc.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: xbar_smc
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/data/rv_plic_smc.hjson b/hw/top_sencha/ip_autogen/rv_plic_smc/data/rv_plic_smc.hjson
new file mode 100644
index 0000000..ed4b9f8
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/data/rv_plic_smc.hjson
@@ -0,0 +1,521 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# RV_PLIC_SMC register template
+#
+# Parameter (given by Python tool)
+# - src: Number of Interrupt Sources
+# - target: Number of Targets that handle interrupt requests
+# - prio: Max value of interrupt priorities
+# - module_instance_name: Module instance name.
+{
+ name: "rv_plic_smc",
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_rv_plic_smc",
+ revisions: [
+ {
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D3",
+ verification_stage: "V2",
+ dif_stage: "S2",
+ commit_id: "",
+ notes: "Use FPV to perform block level verification.",
+ }
+ ],
+ clocking: [{clock: "clk_i", reset: "rst_ni"}],
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device" }
+ ],
+
+ param_list: [
+ { name: "NumSrc",
+ desc: "Number of interrupt sources",
+ type: "int",
+ default: "43",
+ local: "true"
+ },
+ { name: "NumTarget",
+ desc: "Number of Targets (Harts)",
+ type: "int",
+ default: "1",
+ local: "true",
+ },
+ { name: "PrioWidth",
+ desc: "Width of priority signals",
+ type: "int",
+ default: "2",
+ local: "true",
+ },
+ ],
+
+ // In order to not disturb the PLIC address map, we place the alert test
+ // register manually at a safe offset after the main CSRs.
+ no_auto_alert_regs: "True",
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+ '''
+ }
+ ],
+
+ inter_signal_list: [
+ { struct: "logic",
+ type: "uni",
+ name: "irq",
+ act: "req",
+ package: "",
+ width: "1"
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "irq_id",
+ act: "req",
+ package: "",
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "msip",
+ act: "req",
+ package: "",
+ width: "1"
+ },
+ ]
+
+ countermeasures: [
+ { name: "BUS.INTEGRITY",
+ desc: "End-to-end bus integrity scheme."
+ }
+ ]
+
+ regwidth: "32",
+ registers: [
+ { name: "PRIO0",
+ desc: "Interrupt Source 0 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO1",
+ desc: "Interrupt Source 1 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO2",
+ desc: "Interrupt Source 2 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO3",
+ desc: "Interrupt Source 3 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO4",
+ desc: "Interrupt Source 4 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO5",
+ desc: "Interrupt Source 5 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO6",
+ desc: "Interrupt Source 6 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO7",
+ desc: "Interrupt Source 7 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO8",
+ desc: "Interrupt Source 8 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO9",
+ desc: "Interrupt Source 9 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO10",
+ desc: "Interrupt Source 10 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO11",
+ desc: "Interrupt Source 11 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO12",
+ desc: "Interrupt Source 12 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO13",
+ desc: "Interrupt Source 13 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO14",
+ desc: "Interrupt Source 14 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO15",
+ desc: "Interrupt Source 15 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO16",
+ desc: "Interrupt Source 16 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO17",
+ desc: "Interrupt Source 17 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO18",
+ desc: "Interrupt Source 18 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO19",
+ desc: "Interrupt Source 19 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO20",
+ desc: "Interrupt Source 20 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO21",
+ desc: "Interrupt Source 21 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO22",
+ desc: "Interrupt Source 22 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO23",
+ desc: "Interrupt Source 23 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO24",
+ desc: "Interrupt Source 24 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO25",
+ desc: "Interrupt Source 25 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO26",
+ desc: "Interrupt Source 26 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO27",
+ desc: "Interrupt Source 27 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO28",
+ desc: "Interrupt Source 28 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO29",
+ desc: "Interrupt Source 29 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO30",
+ desc: "Interrupt Source 30 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO31",
+ desc: "Interrupt Source 31 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO32",
+ desc: "Interrupt Source 32 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO33",
+ desc: "Interrupt Source 33 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO34",
+ desc: "Interrupt Source 34 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO35",
+ desc: "Interrupt Source 35 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO36",
+ desc: "Interrupt Source 36 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO37",
+ desc: "Interrupt Source 37 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO38",
+ desc: "Interrupt Source 38 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO39",
+ desc: "Interrupt Source 39 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO40",
+ desc: "Interrupt Source 40 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO41",
+ desc: "Interrupt Source 41 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO42",
+ desc: "Interrupt Source 42 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { skipto: "0x00001000" }
+ { multireg: {
+ name: "IP",
+ desc: "Interrupt Pending",
+ count: "NumSrc",
+ cname: "RV_PLIC_SMC",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0", name: "P", desc: "Interrupt Pending of Source" }
+ ],
+ tags: [// IP is driven by intr_src, cannot auto-predict
+ "excl:CsrNonInitTests:CsrExclCheck"],
+ }
+ },
+ { skipto: "0x2000" }
+ { multireg: {
+ name: "IE0",
+ desc: "Interrupt Enable for Target 0",
+ count: "NumSrc",
+ cname: "RV_PLIC_SMC",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0", name: "E", desc: "Interrupt Enable of Source" }
+ ],
+ }
+ }
+ { skipto: "0x200000" }
+ { name: "THRESHOLD0",
+ desc: "Threshold of priority for Target 0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "CC0",
+ desc: '''Claim interrupt by read, complete interrupt by write for Target 0.
+ Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''',
+ swaccess: "rw",
+ hwaccess: "hrw",
+ hwext: "true",
+ hwqe: "true",
+ hwre: "true",
+ fields: [
+ { bits: "5:0" }
+ ],
+ tags: [// CC register value is related to IP
+ "excl:CsrNonInitTests:CsrExclCheck"],
+ }
+ { skipto: "0x4000000" }
+ { name: "MSIP0",
+ desc: '''msip for Hart 0.
+ Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.''',
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ desc: "Software Interrupt Pending register",
+ }
+ ],
+ }
+ { skipto: "0x4004000" }
+ { name: "ALERT_TEST",
+ desc: '''Alert Test Register.''',
+ swaccess: "wo",
+ hwaccess: "hro",
+ hwqe: "True",
+ hwext: "True",
+ fields: [
+ { bits: "0",
+ name: "fatal_fault",
+ desc: "'Write 1 to trigger one alert event of this kind.'",
+ }
+ ],
+ }
+ ],
+}
diff --git a/hw/top_sencha/jtag_id_pkg.core b/hw/top_sencha/jtag_id_pkg.core
new file mode 100644
index 0000000..0241559
--- /dev/null
+++ b/hw/top_sencha/jtag_id_pkg.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:constants:jtag_id_pkg"
+description: "jtag id for top_sencha"
+filesets:
+ files_rtl:
+ depend:
+ - "fileset_partner ? (partner:constants:jtag_id_pkg)"
+ files:
+ - "!fileset_partner ? (rtl/jtag_id_pkg.sv)"
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/lint/chip_sencha_asic.waiver b/hw/top_sencha/lint/chip_sencha_asic.waiver
new file mode 100644
index 0000000..3c1ce07
--- /dev/null
+++ b/hw/top_sencha/lint/chip_sencha_asic.waiver
@@ -0,0 +1,131 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for chip_sencha_asic
+
+waive -rules {MULTI_DRIVEN} -location {chip_sencha_asic.sv} -regexp {'(IOA2|IOA3)' has 2 drivers, also driven at} \
+ -comment "These two pads are shorted to AST, hence this multiple driver warning is OK."
+
+waive -rules {COMBO_LOOP} -location {chip_sencha_asic.sv} \
+ -regexp {port 'u_passthrough.host_s_i.*' driven in module 'spi_device'} \
+ -comment "In the passthrough mode, SPI 4 lines are connected from pads to pads."
+
+waive -rules {CLOCK_DRIVER} -location {chip_sencha_asic.sv} \
+ -msg {'mio_in_raw[28]' is driven by instance 'u_padring' of module 'padring', and used as a clock 'clk_ast_ext_i' at ast_dft} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_DRIVER} -location {chip_sencha_asic.sv} \
+ -msg {'mio_in_raw_o[28]' driven in module 'padring' by port 'gen_mio_pads[28].u_mio_pad.in_raw_o' at padring} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_DRIVER} -location {chip_sencha_asic.sv} \
+ -msg {'in_raw_o' driven in module 'prim_pad_wrapper' by port 'gen_.*.u_impl_.*.in_raw_o' at prim_pad_wrapper} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_DRIVER} -location {chip_sencha_asic.sv} \
+ -msg {'in_raw_o' driven in module 'prim_.*_pad_wrapper' by port} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_DRIVER} -location {chip_sencha_asic.sv} \
+ -msg {'ast_base_clks.clk_io' is driven by instance 'u_ast' of module 'ast', and used as a clock} \
+ -comment "This is a clock source."
+
+waive -rules {CLOCK_DRIVER} -location {chip_sencha_asic.sv} \
+ -msg {'clk_src_io_o' driven in module 'ast' by port 'u_ast_dft.clk_src_io_o' at ast} \
+ -comment "This is a clock source."
+
+waive -rules {CLOCK_DRIVER} -location {chip_sencha_asic.sv} \
+ -msg {'clk_src_io_o' driven in module 'ast_dft' at ast_dft} \
+ -comment "This is a clock source."
+
+waive -rules {CLOCK_USE} -location {chip_sencha_asic.sv} \
+ -msg {'mio_in_raw[28]' is used for some other purpose, and as clock 'clk_ast_ext_i' at ast_dft} \
+ -comment "This is due to the external clock input pin."
+
+waive -rules {CLOCK_USE} -location {chip_sencha_asic.sv} \
+ -msg {'clks_ast.clk_ast_usbdev_usb_peri' is connected to 'ast' port 'clk_ast_usb_i', and used as a clock} \
+ -comment "This is a valid clock signal."
+
+waive -rules {CLOCK_USE} -location {chip_sencha_asic.sv} \
+ -msg {'clks_ast.clk_ast_usbdev_usb_peri' is connected to 'ast' port 'clk_ast_usb_i', and used as a clock} \
+ -comment "This is a valid clock signal."
+
+waive -rules {CLOCK_USE} -location {ast.sv} \
+ -msg {'clk_ast_usb_i' is used for some other purpose, and as clock 'clk_i' at prim_generic_flop.sv} \
+ -comment "This is a valid clock signal."
+
+waive -rules {RESET_DRIVER} -location {chip_sencha_asic.sv} \
+ -msg {'scan_rst_n' is driven by instance 'u_ast' of module 'ast', and used as an asynchronous reset} \
+ -comment "This is a valid reset signal."
+
+waive -rules {RESET_DRIVER} -location {chip_sencha_asic.sv} \
+ -msg {'scan_reset_no' driven in module 'ast' at ast} \
+ -comment "This is a valid reset signal."
+
+waive -rules {RESET_DRIVER} -location {ast.sv} \
+ -msg {'rst_sys_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment "This is a valid reset signal."
+
+waive -rules {RESET_DRIVER} -location {ast.sv} \
+ -msg {'rst_usb_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment "This is a valid reset signal."
+
+waive -rules {RESET_DRIVER} -location {ast.sv} \
+ -msg {'rst_io_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment "This is a valid reset signal."
+
+# Combo loops through uart loopback can be ignored
+waive -rules {COMBO_LOOP} -location {chip_sencha_asic.sv} -regexp {'tx' driven in module 'uart_core' by 'rx' at uart_core.sv} \
+ -comment "there is technically a loopback path through uart, however RX / TX should never be configured to the same pin"
+
+# Combo loops through sysrst_ctrl inversion can be ignored
+waive -rules {COMBO_LOOP} -location {chip_sencha_asic.sv} -regexp {'outputs\[[0-9]+\]' driven in module 'sysrst_ctrl_pin' by 'inputs\[[0-9]+\]' at sysrst_ctrl_pin} \
+ -comment "sysrst_ctrl creates a feed through path directly for certain muxed pins"
+
+# External clock
+waive -rules {CLOCK_DRIVER} -location {chip_sencha_asic.sv} -regexp {'(attr_padring_o|mio_attr)\[28\].pull_select' driven in module} \
+ -comment "MioPadIoc6 at index 28 may serve as an external clock input, hence the warnings"
+
+waive -rules {CLOCK_USE} -location {chip_sencha_asic.sv} -msg {'mio_in_raw[28]' is used for some other purpose, and as clock 'clk_ast_ext_scn'} \
+ -comment "MioPadIoc6 at index 28 may serve as an external clock input, hence the warnings"
+
+# Unused power OK signals
+waive -rules {HIER_NET_NOT_READ NOT_READ} -location {chip_sencha_asic.sv} -regexp {(Signal|Net) 'ast_pwst(\.vcc_pok|_h\.io_pok|_h\.main_pok|_h\.vcc_pok)' is not read from in module 'chip_sencha_asic'} \
+ -comment "Not all POK signals are used inside top_sencha"
+
+# Clock / reset connections going back into AST
+waive -rules {CLOCK_USE} -location {chip_sencha_asic.sv} -regexp {'clkmgr_aon_clocks..*' is connected to 'ast' port '(sns_clks_i..*|clk_ast_usb_i)', and used as a clock} \
+ -comment "This is a clock struct that is fed back into AST."
+
+waive -rules {CLOCK_MUX} -location {chip_sencha_asic.sv} -regexp {Clock 'ast_base_clks.clk_io' reaches a multiplexer here, used as a clock 'clk_i' at} \
+ -comment "This is a clock signal that is fed back into AST."
+
+waive -rules {CLOCK_MUX} -location {chip_sencha_asic.sv} -regexp {Clock 'clkmgr_aon_clocks.clk_io_div4_secure' is driven by a multiplexer here, used as a clock 'clk_i' at} \
+ -comment "This is a clock signal that is fed back into AST."
+
+waive -rules {CLOCK_MUX} -location {chip_sencha_asic.sv} -regexp {Clock 'clkmgr_aon_clocks.clk_io_div4_infra' is driven by a multiplexer here, used as a clock 'clk_i' at} \
+ -comment "This is a clock signal that is fed back into AST."
+
+waive -rules {RESET_USE} -location {chip_sencha_asic.sv} -regexp {'rstmgr_aon_resets..*' is connected to 'ast' port 'sns_rsts_i..*', and used as an asynchronous reset or set} \
+ -comment "This is a reset struct that is fed back into AST."
+
+waive -rules {RESET_USE} -location {ast.sv} \
+ -regexp {'rst_ast_usb_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment "This is a reset struct that is fed back into AST."
+
+waive -rules {RESET_USE} -location {usb_clk.sv} \
+ -regexp {'rst_usb_clk_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment "This is a reset struct that is fed back into AST."
+
+waive -rules {RESET_MUX} -location {chip_sencha_asic.sv} -regexp {Asynchronous reset 'rstmgr_aon_resets..*' is driven by a multiplexer here, used as a reset} \
+ -comment "This is a reset struct that is fed back into AST."
+
+waive -rules {RESET_MUX} -location {usb_clk.sv} \
+ -regexp {Asynchronous reset 'rst_n' is driven by a multiplexer here, used as a reset 'rst_ni' at prim_generic_flop.sv} \
+ -comment "This is reset generation logic, hence reset muxes are allowed."
+
+# REMOVE FOR PRODUCTION, see https://github.com/lowRISC/opentitan/issues/15674
+waive -rules {LHS_TOO_SHORT} -location {aes_prng_masking.sv} \
+ -regexp {Bitlength mismatch between 'unused_assert_static_lint_error' length 1 and 'AesSecAllowForcingMasksNonDefault'\(1'b1\)' length 2} \
+ -comment "For ES we want to be able to switch off the masking inside AES, see https://github.com/lowRISC/opentitan/issues/14240. REMOVE FOR PRODUCTION!"
diff --git a/hw/top_sencha/lint/padring.waiver b/hw/top_sencha/lint/padring.waiver
new file mode 100644
index 0000000..cd3e77b
--- /dev/null
+++ b/hw/top_sencha/lint/padring.waiver
@@ -0,0 +1,21 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for padring
+
+waive -rules {HIER_BRANCH_NOT_READ HIER_NET_NOT_READ} \
+ -location {padring.sv} \
+ -regexp {Net 'pok_i.*' in module 'padring'.*is not read from} \
+ -comment "SNS and RTO cells are not read from in the converted LIB/DB model, resulting in these warnings."
+
+waive -rules {HIER_BRANCH_NOT_READ HIER_NET_NOT_READ} \
+ -location {padring.sv} \
+ -regexp {Connected net '(SNS|RTO)'.*is not read from in module.*} \
+ -comment "Some ports are not read from in the converted LIB/DB model, resulting in these warnings."
+
+waive -rules {HIER_BRANCH_NOT_READ} \
+ -location {padring.sv} \
+ -regexp {Net 'clk_scan_i' in module 'padring'.*} \
+ -comment "This net is not read from if no scan role is defined for the pads (which is the case in the opensource view)."
+
diff --git a/hw/top_sencha/lint/top_sencha.vbw b/hw/top_sencha/lint/top_sencha.vbw
new file mode 100644
index 0000000..77e35ac
--- /dev/null
+++ b/hw/top_sencha/lint/top_sencha.vbw
@@ -0,0 +1,3 @@
+
+# These lines are too long due to templating
+waive --rule=line-length --location=".*top_sencha.*"
diff --git a/hw/top_sencha/lint/top_sencha.vlt b/hw/top_sencha/lint/top_sencha.vlt
new file mode 100644
index 0000000..fd5bafd
--- /dev/null
+++ b/hw/top_sencha/lint/top_sencha.vlt
@@ -0,0 +1,6 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// waiver file for top_sencha
+
diff --git a/hw/top_sencha/lint/top_sencha.waiver b/hw/top_sencha/lint/top_sencha.waiver
new file mode 100644
index 0000000..763834c
--- /dev/null
+++ b/hw/top_sencha/lint/top_sencha.waiver
@@ -0,0 +1,61 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for top_sencha
+
+# dedicated reset drivers / muxes
+set_reset_drivers prim_clock_mux2 prim_flop_2sync prim_flop
+set_clock_drivers prim_clock_buf prim_clock_mux2
+
+# All leaf resets have a reset multiplex
+waive -rules RESET_MUX -location {top_sencha.sv} -regexp {Asynchronous reset .*rstmgr_aon_resets\.rst.* is driven by a multiplexer} \
+ -comment "This is dedicated reset infrastructure, and hence permissible"
+
+waive -rules RESET_MUX -location {rstmgr.sv rstmgr_por.sv rstmgr_ctrl.sv} -regexp {Asynchronous reset '(resets_o\.)?rst_[A-Za-z_0-9]+_n(\[[0-9:]+\])?' is driven by a multiplexer} \
+ -comment "This is dedicated reset infrastructure, and hence permissible"
+
+waive -rules RESET_MUX -location {rstmgr.sv} -regexp {Asynchronous reset 'scan_rst_ni' reaches a multiplexer} \
+ -comment "This is dedicated reset infrastructure, and hence permissible"
+
+waive -rules RESET_MUX -location {spi_device.sv} -regexp {Asynchronous reset '(rst_ni|rst_spi_n)' reaches a multiplexer} \
+ -comment "This is dedicated reset infrastructure, and hence permissible"
+
+waive -rules CLOCK_USE -location {top_sencha.sv} -regexp {'clkmgr_aon_clocks.clk_io_div2_peri' is connected to 'spi_device' port 'scan_clk_i', and used as a clock} \
+ -comment "This connection is a scan clock connection."
+
+waive -rules CLOCK_MUX -location {clkmgr.sv top_sencha.sv} -regexp {.*clk_io_div.* is driven by a multiplexer here} \
+ -comment "Divided clocks go through prim_clock_div, which use muxes for scan bypass and clock step down"
+
+# scan reset is a legal asynchronous reset
+waive -rules RESET_USE -location {top_sencha.sv} -regexp {'scan_rst_ni' is connected to .* port 'scan_rst_ni', and used as an asynchronous reset or set 'rst_.*ni' at} \
+ -comment "Scan reset is a legal asynchronous reset"
+
+# intentionally unused
+waive -rules {NOT_READ HIER_NET_NOT_READ} -location {top_sencha.sv} -regexp {.*cio_otp_ctrl_test_(en_)?d2p\[7:1\].* is not read} \
+ -comment "otp test bus made deliberately larger on purpose"
+
+## xbar
+#waive -rules HIER_NET_NOT_READ -location {tlul_xbar.sv} -regexp {a_source.* is not read from} \
+# -comment "upper bits of a_source are shifted off when going through M:1 sockets"
+#waive -rules LINE_LENGTH -location {xbar_main.sv} -regexp {Line length of .* exceeds 100 character limit} \
+# -comment "This is a generated file and it is hence permissible to have line lengths that exceed this limit"
+
+# Possible tool shortcomings
+
+waive -rules CLOCK_USE -location {top_sencha.sv} -regexp {'clkmgr_aon_clocks.clk_io_div4_secure' is connected to 'pwrmgr' port 'clk_esc_i', and used as a clock 'clk_i' at tlul_socket_1n.sv} \
+ -comment "The tool for reasons unknown is unable to trace through a prim buf wrap cell to understand the clock is being used as a clock. If a direct assign is used, the error goes away."
+
+waive -rules CLOCK_USE -location {top_sencha.sv} -regexp {'clkmgr_aon_clocks.clk_io_div4_powerup' is connected to 'pwrmgr' port 'clk_lc_i', and used as a clock 'clk_i' at tlul_socket_1n.sv} \
+ -comment "The tool for reasons unknown is unable to trace through a prim buf wrap cell to understand the clock is being used as a clock. If a direct assign is used, the error goes away."
+
+# Most SAME_NAME_TYPE issues have been fixed. There are however some that overlap due to similar terminology.
+# Since these functions / parameters / signals live in different scopes, this is acceptable, and we can waive them.
+waive -rules SAME_NAME_TYPE -location {aes_sbox_canright_pkg.sv} -msg {'theta' is used as a reg here, and as a function at} \
+ -comment {This is acceptable, since these are used in different hierarchies.}
+waive -rules SAME_NAME_TYPE -location {keccak_round.sv} -msg {'L' is used as a parameter here, and as a reg at} \
+ -comment {This is acceptable, since these are used in different hierarchies.}
+waive -rules SAME_NAME_TYPE -location {spi_device.sv} -msg {'spi_device' is used as a module here, and as a reg at } \
+ -comment {This is acceptable, since these are used in different hierarchies.}
+waive -rules SAME_NAME_TYPE -location {tlul_socket_m1.sv} -msg {'M' is used as a parameter here, and as a reg at} \
+ -comment {This is acceptable, since these are used in different hierarchies.}
diff --git a/hw/top_sencha/lint/top_sencha_dv_lint_cfgs.hjson b/hw/top_sencha/lint/top_sencha_dv_lint_cfgs.hjson
new file mode 100644
index 0000000..3d05490
--- /dev/null
+++ b/hw/top_sencha/lint/top_sencha_dv_lint_cfgs.hjson
@@ -0,0 +1,190 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+
+ // This is the primary cfg hjson for DV linting. It imports ALL individual lint
+ // cfgs of the IPs DV environments and the full chip DV environment for top_sencha.
+ // This enables to run them all as a regression in one shot.
+ name: top_sencha_dv_batch
+
+ import_cfgs: [// common server configuration for results upload
+ "{proj_root}/hw/data/common_project_cfg.hjson"
+ // tool-specific configuration
+ "{proj_root}/hw/lint/tools/dvsim/{tool}.hjson"]
+
+ flow: "lint"
+
+ // Different dashboard output path for each tool
+ rel_path: "hw/top_sencha/dv/lint/{tool}/summary"
+
+ use_cfgs: [{ name: aes
+ fusesoc_core: lowrisc:dv:aes_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/aes/dv/lint/{tool}"
+ },
+ { name: alert_handler
+ fusesoc_core: lowrisc:opentitan:top_sencha_alert_handler_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/ip_autogen/alert_handler/dv/lint/{tool}"
+ },
+ { name: aon_timer
+ fusesoc_core: lowrisc:dv:aon_timer_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/ip/aon_timer/dv/lint/{tool}"
+ },
+ { name: clkmgr
+ fusesoc_core: lowrisc:dv:clkmgr_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/clkmgr/dv/lint/{tool}"
+ },
+ { name: csrng
+ fusesoc_core: lowrisc:dv:csrng_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/csrng/dv/lint/{tool}"
+ },
+ { name: adc_ctrl
+ fusesoc_core: lowrisc:dv:adc_ctrl_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/adc_ctrl/dv/lint/{tool}"
+ },
+ { name: entropy_src
+ fusesoc_core: lowrisc:dv:entropy_src_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/entropy_src/dv/lint/{tool}"
+ },
+ { name: edn
+ fusesoc_core: lowrisc:dv:edn_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/edn/dv/lint/{tool}"
+ },
+ { name: flash_ctrl
+ fusesoc_core: lowrisc:dv:flash_ctrl_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/flash_ctrl/dv/lint/{tool}"
+ },
+ { name: gpio
+ fusesoc_core: lowrisc:dv:gpio_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/gpio/dv/lint/{tool}"
+ },
+ { name: hmac
+ fusesoc_core: lowrisc:dv:hmac_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/hmac/dv/lint/{tool}"
+ },
+ { name: i2c
+ fusesoc_core: lowrisc:dv:i2c_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/i2c/dv/lint/{tool}"
+ },
+ { name: keymgr
+ fusesoc_core: lowrisc:dv:keymgr_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/keymgr/dv/lint/{tool}"
+ },
+ {
+ name: kmac
+ fusesoc_core: lowrisc:dv:kmac_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/kmac/dv/lint/{tool}"
+ },
+ {
+ name: lc_ctrl
+ fusesoc_core: lowrisc:dv:lc_ctrl_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/lc_ctrl/dv/lint/{tool}"
+ },
+ { name: otp_ctrl
+ fusesoc_core: lowrisc:dv:otp_ctrl_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/otp_ctrl/dv/lint/{tool}"
+ },
+ { name: pattgen
+ fusesoc_core: lowrisc:,dv:pattgen_sim,
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
+ rel_path: "hw/ip/pattgen/dv/lint/{tool}"
+ },
+ { name: prim_alert
+ fusesoc_core: lowrisc:dv:prim_alert_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/dv/prim_alert/lint/{tool}"
+ },
+ { name: prim_esc
+ fusesoc_core: lowrisc:dv:prim_esc_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/dv/prim_esc/lint/{tool}"
+ },
+ { name: prim_lfsr
+ fusesoc_core: lowrisc:dv:prim_lfsr_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/dv/prim_lfsr/lint/{tool}"
+ },
+ { name: prim_present
+ fusesoc_core: lowrisc:dv:prim_present_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/dv/prim_present/lint/{tool}"
+ },
+ { name: prim_prince
+ fusesoc_core: lowrisc:dv:prim_prince_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/dv/prim_prince/lint/{tool}"
+ },
+ { name: pwrmgr
+ fusesoc_core: lowrisc:dv:pwrmgr_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/pwrmgr/dv/lint/{tool}"
+ },
+ { name: rom_ctrl
+ fusesoc_core: lowrisc:dv:rom_ctrl_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/rom_ctrl/dv/lint/{tool}"
+ },
+ { name: rv_dm
+ fusesoc_core: lowrisc:dv:rv_dm_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/rv_dm/dv/lint/{tool}"
+ },
+ { name: rv_timer
+ fusesoc_core: lowrisc:dv:rv_timer_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/rv_timer/dv/lint/{tool}"
+ },
+ { name: spi_device
+ fusesoc_core: lowrisc:dv:spi_device_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/spi_device/dv/lint/{tool}"
+ },
+ { name: uart
+ fusesoc_core: lowrisc:dv:uart_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/uart/dv/lint/{tool}"
+ },
+ { name: usbdev
+ fusesoc_core: lowrisc:dv:usbdev_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/usbdev/dv/lint/{tool}"
+ },
+ { name: xbar_main
+ fusesoc_core: lowrisc:dv:xbar_main_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/ip/xbar_main/dv/lint/{tool}"
+ },
+ { name: xbar_peri
+ fusesoc_core: lowrisc:dv:xbar_peri_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/ip/xbar_peri/dv/lint/{tool}"
+ },
+ { name: chip
+ fusesoc_core: lowrisc:dv:chip_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/dv/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ ]
+}
diff --git a/hw/top_sencha/lint/top_sencha_fpv_lint_cfgs.hjson b/hw/top_sencha/lint/top_sencha_fpv_lint_cfgs.hjson
new file mode 100644
index 0000000..69eb9bf
--- /dev/null
+++ b/hw/top_sencha/lint/top_sencha_fpv_lint_cfgs.hjson
@@ -0,0 +1,153 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ flow: lint
+
+ // This is the primary cfg hjson for FPV linting. It imports ALL individual lint
+ // cfgs of the IPs FPV environments.
+ // This enables to run them all as a regression in one shot.
+ name: top_sencha_fpv_batch
+
+ import_cfgs: [// common server configuration for results upload
+ "{proj_root}/hw/data/common_project_cfg.hjson"
+ // tool-specific configuration
+ "{proj_root}/hw/lint/tools/dvsim/{tool}.hjson"]
+
+ // Different dashboard output path for each tool
+ rel_path: "hw/top_sencha/fpv/lint/{tool}/summary"
+
+ use_cfgs: [{
+ name: alert_handler_esc_timer_fpv
+ fusesoc_core: lowrisc:opentitan:top_sencha_alert_handler_esc_timer_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/alert_handler/alert_handler_esc_timer_fpv/lint/{tool}"
+ }
+ {
+ name: alert_handler_ping_timer_fpv
+ fusesoc_core: lowrisc:opentitan:top_sencha_alert_handler_ping_timer_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/alert_handler/alert_handler_ping_timer_fpv/lint/{tool}"
+ }
+ {
+ name: prim_arbiter_ppc_fpv
+ fusesoc_core: lowrisc:fpv:prim_arbiter_ppc_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_arbiter_ppc_fpv/lint/{tool}"
+ }
+ {
+ name: prim_arbiter_tree_fpv
+ fusesoc_core: lowrisc:fpv:prim_arbiter_tree_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_arbiter_tree_fpv/lint/{tool}"
+ }
+ {
+ name: prim_arbiter_fixed_fpv
+ fusesoc_core: lowrisc:fpv:prim_arbiter_fixed_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_arbiter_fixed_fpv/lint/{tool}"
+ }
+ {
+ name: prim_lfsr_fpv
+ fusesoc_core: lowrisc:fpv:prim_lfsr_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_lfsr_fpv/lint/{tool}"
+ }
+ {
+ name: prim_fifo_sync_fpv
+ fusesoc_core: lowrisc:fpv:prim_fifo_sync_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_fifo_sync_fpv/lint/{tool}"
+ }
+ {
+ name: prim_alert_rxtx_fpv
+ fusesoc_core: lowrisc:fpv:prim_alert_rxtx_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_alert_rxtx_fpv/lint/{tool}"
+ }
+ {
+ name: prim_alert_rxtx_async_fpv
+ fusesoc_core: lowrisc:fpv:prim_alert_rxtx_async_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_alert_rxtx_async_fpv/lint/{tool}"
+ }
+ {
+ name: prim_esc_rxtx_fpv
+ fusesoc_core: lowrisc:fpv:prim_esc_rxtx_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_esc_rxtx_fpv/lint/{tool}"
+ }
+ {
+ name: prim_secded_22_16_fpv
+ fusesoc_core: lowrisc:fpv:prim_secded_22_16_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_secded_22_16_fpv/lint/{tool}"
+ }
+ {
+ name: prim_secded_28_22_fpv
+ fusesoc_core: lowrisc:fpv:prim_secded_28_22_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_secded_28_22_fpv/lint/{tool}"
+ }
+ {
+ name: prim_secded_39_32_fpv
+ fusesoc_core: lowrisc:fpv:prim_secded_39_32_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_secded_39_32_fpv/lint/{tool}"
+ }
+ {
+ name: prim_secded_64_57_fpv
+ fusesoc_core: lowrisc:fpv:prim_secded_64_57_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_secded_64_57_fpv/lint/{tool}"
+ }
+ {
+ name: prim_secded_72_64_fpv
+ fusesoc_core: lowrisc:fpv:prim_secded_72_64_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_secded_72_64_fpv/lint/{tool}"
+ }
+ {
+ name: prim_secded_hamming_22_16_fpv
+ fusesoc_core: lowrisc:fpv:prim_secded_hamming_22_16_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_hamming_22_16_fpv/lint/{tool}"
+ }
+ {
+ name: prim_secded_hamming_39_32_fpv
+ fusesoc_core: lowrisc:fpv:prim_secded_hamming_39_32_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_hamming_39_32_fpv/lint/{tool}"
+ }
+ {
+ name: prim_secded_hamming_72_64_fpv
+ fusesoc_core: lowrisc:fpv:prim_secded_hamming_72_64_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_hamming_72_64_fpv/lint/{tool}"
+ }
+ {
+ name: prim_packer_fpv
+ fusesoc_core: lowrisc:fpv:prim_packer_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/prim_packer_fpv/lint/{tool}"
+ }
+ {
+ name: pinmux_fpv
+ fusesoc_core: lowrisc:fpv:pinmux_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/pinmux/fpv/lint/{tool}"
+ }
+ {
+ name: top_sencha_rv_plic_fpv
+ fusesoc_core: lowrisc:opentitan:top_sencha_rv_plic_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/ip_autogen/rv_plic/fpv/lint/{tool}"
+ }
+ {
+ name: sha3pad_fpv
+ fusesoc_core: lowrisc:fpv:sha3pad_fpv
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/kmac/fpv/lint/{tool}"
+ }
+ ]
+}
diff --git a/hw/top_sencha/lint/top_sencha_lint_cfgs.hjson b/hw/top_sencha/lint/top_sencha_lint_cfgs.hjson
new file mode 100644
index 0000000..0ad791b
--- /dev/null
+++ b/hw/top_sencha/lint/top_sencha_lint_cfgs.hjson
@@ -0,0 +1,331 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+
+ // This is the primary cfg hjson for RTL linting. It imports ALL individual lint
+ // cfgs of the IPs and the full chip used in top_sencha. This enables to run
+ // them all as a regression in one shot.
+ name: top_sencha_batch
+
+ flow: lint
+
+ import_cfgs: [// common server configuration for results upload
+ "{proj_root}/hw/data/common_project_cfg.hjson"
+ // tool-specific configuration
+ "{proj_root}/hw/lint/tools/dvsim/{tool}.hjson"]
+
+ // Different dashboard output path for each tool
+ rel_path: "hw/top_sencha/lint/{tool}/summary"
+
+ // Severities to be printed in the summary report
+ report_severities: ["warning", "error"]
+
+ use_cfgs: [{ name: aes
+ fusesoc_core: lowrisc:ip:aes
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/aes/lint/{tool}"
+ },
+ { name: alert_handler
+ fusesoc_core: lowrisc:opentitan:top_sencha_alert_handler
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/ip_autogen/alert_handler/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: aon_timer
+ fusesoc_core: lowrisc:ip:aon_timer
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/aon_timer/lint/{tool}"
+ },
+ { name: ast
+ fusesoc_core: google:systems:ast
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/ip/ast/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: entropy_src
+ fusesoc_core: lowrisc:ip:entropy_src
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/entropy_src/lint/{tool}"
+ },
+ { name: clkmgr
+ fusesoc_core: lowrisc:systems:clkmgr
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
+ rel_path: "hw/top_sencha/ip/clkmgr/lint/{tool}",
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: csrng
+ fusesoc_core: lowrisc:ip:csrng
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/csrng/lint/{tool}"
+ },
+ { name: adc_ctrl
+ fusesoc_core: lowrisc:ip:adc_ctrl
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/adc_ctrl/lint/{tool}"
+ },
+ { name: edn
+ fusesoc_core: lowrisc:ip:edn
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/edn/lint/{tool}"
+ },
+ { name: flash_ctrl
+ fusesoc_core: lowrisc:ip:flash_ctrl
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/flash_ctrl/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: gpio
+ fusesoc_core: lowrisc:ip:gpio
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/gpio/lint/{tool}"
+ },
+ { name: hmac
+ fusesoc_core: lowrisc:ip:hmac
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/hmac/lint/{tool}"
+ },
+ { name: kmac
+ fusesoc_core: lowrisc:ip:kmac
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/kmac/lint/{tool}"
+ },
+ { name: i2c
+ fusesoc_core: lowrisc:ip:i2c
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/i2c/lint/{tool}"
+ },
+ { name: lc_ctrl
+ fusesoc_core: lowrisc:ip:lc_ctrl
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/lc_ctrl/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: pattgen
+ fusesoc_core: lowrisc:ip:pattgen
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/pattgen/lint/{tool}"
+ },
+ { name: keymgr
+ fusesoc_core: lowrisc:ip:keymgr
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/keymgr/lint/{tool}"
+ },
+ { name: otbn
+ fusesoc_core: lowrisc:ip:otbn
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/otbn/lint/{tool}"
+ },
+ { name: otp_ctrl
+ fusesoc_core: lowrisc:ip:otp_ctrl
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/otp_ctrl/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: pinmux
+ fusesoc_core: lowrisc:ip:pinmux
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/pinmux/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: pwm
+ fusesoc_core: lowrisc:ip:pwm
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/pwm/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: pwrmgr
+ fusesoc_core: google:systems:pwrmgr
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
+ rel_path: "hw/ip/pwrmgr/lint/{tool}",
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: rom_ctrl
+ fusesoc_core: lowrisc:ip:rom_ctrl
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/rom_ctrl/lint/{tool}"
+ },
+ { name: rstmgr
+ fusesoc_core: lowrisc:ip:rstmgr
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"],
+ rel_path: "hw/top_sencha/ip/rstmgr/lint/{tool}",
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: rv_core_ibex
+ fusesoc_core: lowrisc:ip:rv_core_ibex
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/rv_core_ibex/lint/{tool}"
+ },
+ { name: rv_core_smc
+ fusesoc_core: google:ip:rv_core_smc
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/rv_core_smc/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: rv_dm
+ fusesoc_core: lowrisc:ip:rv_dm
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/rv_dm/lint/{tool}"
+ },
+ { name: top_sencha_rv_plic
+ fusesoc_core: lowrisc:opentitan:top_sencha_rv_plic
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/ip_autogen/rv_plic/lint/{tool}"
+ },
+ { name: rv_timer
+ fusesoc_core: lowrisc:ip:rv_timer
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/rv_timer/lint/{tool}"
+ },
+ { name: spi_device
+ fusesoc_core: lowrisc:ip:spi_device
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/spi_device/lint/{tool}"
+ },
+ { name: spi_host
+ fusesoc_core: lowrisc:ip:spi_host
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/spi_host/lint/{tool}"
+ },
+ { name: sram_ctrl
+ fusesoc_core: lowrisc:ip:sram_ctrl
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/sram_ctrl/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: sysrst_ctrl
+ fusesoc_core: lowrisc:ip:sysrst_ctrl
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/sysrst_ctrl/lint/{tool}"
+ },
+ { name: uart
+ fusesoc_core: lowrisc:ip:uart
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/uart/lint/{tool}"
+ },
+ { name: usbdev
+ fusesoc_core: lowrisc:ip:usbdev
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/usbdev/lint/{tool}"
+ },
+ { name: socket_1n
+ fusesoc_core: lowrisc:tlul:socket_1n
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/tlul/socket_1n/lint/{tool}"
+ },
+ { name: socket_m1
+ fusesoc_core: lowrisc:tlul:socket_m1
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/tlul/socket_m1/lint/{tool}"
+ },
+ { name: adapter_reg
+ fusesoc_core: lowrisc:tlul:adapter_reg
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/tlul/adapter_reg/lint/{tool}"
+ },
+ { name: adapter_sram
+ fusesoc_core: lowrisc:tlul:adapter_sram
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/tlul/adapter_sram/lint/{tool}"
+ },
+ { name: sensor_ctrl
+ fusesoc_core: lowrisc:systems:sensor_ctrl
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/ip/sensor_ctrl/lint/{tool}"
+ },
+ { name: sram2tlul
+ fusesoc_core: lowrisc:tlul:sram2tlul
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/tlul/sram2tlul/lint/{tool}"
+ },
+ { name: top_sencha
+ fusesoc_core: lowrisc:systems:top_sencha
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/top_sencha/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ { name: chip_sencha_asic
+ fusesoc_core: lowrisc:systems:chip_sencha_asic
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/chip_sencha_asic/lint/{tool}"
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ ]
+ },
+ // this currently causes compilation issues in AscentLint
+ //{ name: chip_sencha_verilator
+ // fusesoc_core: lowrisc:systems:chip_sencha_verilator
+ // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ // rel_path: "hw/chip_sencha_verilator/lint/{tool}"
+ //},
+ ]
+
+}
diff --git a/hw/top_sencha/padring.core b/hw/top_sencha/padring.core
new file mode 100644
index 0000000..7dc7e73
--- /dev/null
+++ b/hw/top_sencha/padring.core
@@ -0,0 +1,48 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:padring:0.1"
+description: "Chip-level padring instance"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:pinmux_component
+ - "!fileset_partner ? (lowrisc:systems:physical_pads)"
+ - "fileset_partner ? (partner:systems:physical_pads)"
+ files:
+ - rtl/padring.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ # - lint/padring.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/padring.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/hw/top_sencha/rtl/chip_sencha_verilator.sv b/hw/top_sencha/rtl/chip_sencha_verilator.sv
new file mode 100644
index 0000000..b51cd0b
--- /dev/null
+++ b/hw/top_sencha/rtl/chip_sencha_verilator.sv
@@ -0,0 +1,684 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module chip_sencha_verilator (
+ // Clock and Reset
+ input clk_i,
+ input rst_ni,
+
+ // communication with GPIO
+ input [31:0] cio_gpio_p2d_i,
+ output logic [31:0] cio_gpio_d2p_o,
+ output logic [31:0] cio_gpio_en_d2p_o,
+ output logic [31:0] cio_gpio_pull_en_o,
+ output logic [31:0] cio_gpio_pull_select_o,
+
+ // communication with UART
+ input cio_uart_rx_p2d_i,
+ output logic cio_uart_tx_d2p_o,
+ output logic cio_uart_tx_en_d2p_o,
+
+ input cio_uart_smc_rx_p2d_i,
+ output logic cio_uart_smc_tx_d2p_o,
+ output logic cio_uart_smc_tx_en_d2p_o,
+
+ // communication with SPI
+ input cio_spi_device_sck_p2d_i,
+ input cio_spi_device_csb_p2d_i,
+ input cio_spi_device_sdi_p2d_i,
+ output logic cio_spi_device_sdo_d2p_o,
+ output logic cio_spi_device_sdo_en_d2p_o,
+
+ // communication with USB
+ input cio_usbdev_sense_p2d_i,
+ output logic cio_usbdev_dp_pullup_d2p_o,
+ output logic cio_usbdev_dn_pullup_d2p_o,
+ input cio_usbdev_dp_p2d_i,
+ output logic cio_usbdev_dp_d2p_o,
+ output logic cio_usbdev_dp_en_d2p_o,
+ input cio_usbdev_dn_p2d_i,
+ output logic cio_usbdev_dn_d2p_o,
+ output logic cio_usbdev_dn_en_d2p_o,
+ input cio_usbdev_d_p2d_i,
+ output logic cio_usbdev_d_d2p_o,
+ output logic cio_usbdev_d_en_d2p_o,
+ output logic cio_usbdev_se0_d2p_o,
+ output logic cio_usbdev_rx_enable_d2p_o,
+ output logic cio_usbdev_tx_use_d_se0_d2p_o,
+
+ // communications with I2S
+ input cio_i2s_rx_sd_p2d_i,
+ output logic cio_i2s_rx_sclk_d2p_o,
+ output logic cio_i2s_rx_ws_d2p_o,
+ output logic cio_i2s_tx_sclk_d2p_o,
+ output logic cio_i2s_tx_ws_d2p_o,
+ output logic cio_i2s_tx_sd_d2p_o
+);
+
+ import top_sencha_pkg::*;
+
+
+ logic IO_JTCK, IO_JTMS, IO_JTRST_N, IO_JTDI, IO_JTDO;
+
+ // TODO: instantiate padring and route these signals through that module
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_in;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_out;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe;
+
+ always_comb begin : assign_dio_in
+ dio_in = '0;
+ dio_in[DioSpiDeviceSck] = cio_spi_device_sck_p2d_i;
+ dio_in[DioSpiDeviceCsb] = cio_spi_device_csb_p2d_i;
+ dio_in[DioSpiDeviceSd0] = cio_spi_device_sdi_p2d_i;
+ dio_in[DioUsbdevUsbDp] = cio_usbdev_dp_p2d_i;
+ dio_in[DioUsbdevUsbDn] = cio_usbdev_dn_p2d_i;
+ end
+
+ // USB
+ logic usb_dp_pullup;
+ logic usb_dn_pullup;
+ logic usb_rx_d;
+ logic usb_tx_d;
+ logic usb_tx_se0;
+ logic usb_tx_use_d_se0;
+ logic usb_rx_enable;
+
+ assign usb_rx_d = cio_usbdev_d_p2d_i;
+ assign cio_usbdev_d_d2p_o = usb_tx_d;
+ assign cio_usbdev_d_en_d2p_o = dio_oe[DioUsbdevUsbDp];
+ assign cio_usbdev_dn_pullup_d2p_o = usb_dn_pullup;
+ assign cio_usbdev_dp_pullup_d2p_o = usb_dp_pullup;
+ assign cio_usbdev_se0_d2p_o = usb_tx_se0;
+ assign cio_usbdev_rx_enable_d2p_o = usb_rx_enable;
+ assign cio_usbdev_tx_use_d_se0_d2p_o = usb_tx_use_d_se0;
+
+ assign cio_usbdev_dp_d2p_o = dio_out[DioUsbdevUsbDp];
+ assign cio_usbdev_dp_en_d2p_o = dio_oe[DioUsbdevUsbDp];
+ assign cio_usbdev_dn_d2p_o = dio_out[DioUsbdevUsbDn];
+ assign cio_usbdev_dn_en_d2p_o = dio_oe[DioUsbdevUsbDn];
+
+ assign cio_spi_device_sdo_d2p_o = dio_out[DioSpiDeviceSd1];
+ assign cio_spi_device_sdo_en_d2p_o = dio_oe[DioSpiDeviceSd1];
+
+
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_in;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe;
+ prim_pad_wrapper_pkg::pad_attr_t[pinmux_reg_pkg::NMioPads-1:0] mio_attr;
+
+ always_comb begin : assign_mio_in
+ mio_in[MioPadIob8:MioPadIoa0] = cio_gpio_p2d_i[17:0];
+ mio_in[MioPadIob12:MioPadIob10] = cio_gpio_p2d_i[20:18];
+ mio_in[MioPadIoc6] = cio_gpio_p2d_i[21];
+ mio_in[MioPadIoc7] = cio_gpio_p2d_i[25];
+ mio_in[MioPadIoc9] = cio_gpio_p2d_i[26];
+ mio_in[MioPadIor7:MioPadIor6] = cio_gpio_p2d_i[29:28];
+ mio_in[MioPadIor10] = cio_gpio_p2d_i[31];
+
+ // SW straps
+ mio_in[MioPadIoc2:MioPadIoc0] = cio_gpio_p2d_i[24:22];
+
+ // TAP straps
+ mio_in[MioPadIoc5] = cio_gpio_p2d_i[27];
+ mio_in[MioPadIoc8] = cio_gpio_p2d_i[30];
+
+ // UART RX
+ mio_in[MioPadIoc3] = cio_uart_rx_p2d_i;
+ mio_in[MioPadIoc10] = cio_uart_smc_rx_p2d_i;
+ end
+
+ // Generic GPIOs
+ assign cio_gpio_d2p_o[17:0] = mio_out[MioPadIob8:MioPadIoa0];
+ assign cio_gpio_en_d2p_o[17:0] = mio_oe[MioPadIob8:MioPadIoa0];
+ assign cio_gpio_d2p_o[20:18] = mio_out[MioPadIob12:MioPadIob10];
+ assign cio_gpio_en_d2p_o[20:18] = mio_oe[MioPadIob12:MioPadIob10];
+ assign cio_gpio_d2p_o[21] = mio_out[MioPadIoc6];
+ assign cio_gpio_en_d2p_o[21] = mio_oe[MioPadIoc6];
+ assign cio_gpio_d2p_o[25] = mio_out[MioPadIoc7];
+ assign cio_gpio_en_d2p_o[25] = mio_oe[MioPadIoc7];
+ assign cio_gpio_d2p_o[26] = mio_out[MioPadIoc9];
+ assign cio_gpio_en_d2p_o[26] = mio_oe[MioPadIoc9];
+ assign cio_gpio_d2p_o[29:28] = mio_out[MioPadIor7:MioPadIor6];
+ assign cio_gpio_en_d2p_o[29:28] = mio_oe[MioPadIor7:MioPadIor6];
+ assign cio_gpio_d2p_o[31] = mio_out[MioPadIor10];
+ assign cio_gpio_en_d2p_o[31] = mio_oe[MioPadIor10];
+
+ // SW STRAPs
+ assign cio_gpio_d2p_o[24:22] = mio_out[MioPadIoc2:MioPadIoc0];
+ assign cio_gpio_en_d2p_o[24:22] = mio_oe[MioPadIoc2:MioPadIoc0];
+
+ // TAP straps
+ assign cio_gpio_d2p_o[27] = mio_out[MioPadIoc5];
+ assign cio_gpio_en_d2p_o[27] = mio_oe[MioPadIoc5];
+ assign cio_gpio_d2p_o[30] = mio_out[MioPadIoc8];
+ assign cio_gpio_en_d2p_o[30] = mio_oe[MioPadIoc8];
+
+ assign cio_uart_tx_d2p_o = mio_out[MioPadIoc4];
+ assign cio_uart_tx_en_d2p_o = mio_oe[MioPadIoc4];
+
+ assign cio_uart_smc_tx_d2p_o = mio_out[MioPadIoc11];
+ assign cio_uart_smc_tx_en_d2p_o = mio_oe[MioPadIoc11];
+
+ // I2S
+ assign cio_i2s_rx_sclk_d2p_o = 0;
+ assign cio_i2s_rx_ws_d2p_o = 0;
+ assign cio_i2s_tx_sclk_d2p_o = 0;
+ assign cio_i2s_tx_sd_d2p_o = 0;
+ assign cio_i2s_tx_ws_d2p_o = 0;
+
+ // Note: we're collecting the `pull_en` and `pull_select` signals together
+ // so that the GPIO DPI functions can simulate weak and strong GPIO
+ // inputs. The `cio_gpio_pull_en_o` and `cio_gpio_pull_select_o` bit
+ // vectors should have the same ordering as the `cio_gpio_d2p_o` vector.
+ // See gpiodpi.c to see how weak/strong inputs work.
+ //
+ // Pull enable for generic GPIOs
+ assign cio_gpio_pull_en_o[0] = mio_attr[MioPadIoa0].pull_en;
+ assign cio_gpio_pull_en_o[1] = mio_attr[MioPadIoa1].pull_en;
+ assign cio_gpio_pull_en_o[2] = mio_attr[MioPadIoa2].pull_en;
+ assign cio_gpio_pull_en_o[3] = mio_attr[MioPadIoa3].pull_en;
+ assign cio_gpio_pull_en_o[4] = mio_attr[MioPadIoa4].pull_en;
+ assign cio_gpio_pull_en_o[5] = mio_attr[MioPadIoa5].pull_en;
+ assign cio_gpio_pull_en_o[6] = mio_attr[MioPadIoa6].pull_en;
+ assign cio_gpio_pull_en_o[7] = mio_attr[MioPadIoa7].pull_en;
+ assign cio_gpio_pull_en_o[8] = mio_attr[MioPadIoa8].pull_en;
+ assign cio_gpio_pull_en_o[9] = mio_attr[MioPadIob0].pull_en;
+ assign cio_gpio_pull_en_o[10] = mio_attr[MioPadIob1].pull_en;
+ assign cio_gpio_pull_en_o[11] = mio_attr[MioPadIob2].pull_en;
+ assign cio_gpio_pull_en_o[12] = mio_attr[MioPadIob3].pull_en;
+ assign cio_gpio_pull_en_o[13] = mio_attr[MioPadIob4].pull_en;
+ assign cio_gpio_pull_en_o[14] = mio_attr[MioPadIob5].pull_en;
+ assign cio_gpio_pull_en_o[15] = mio_attr[MioPadIob6].pull_en;
+ assign cio_gpio_pull_en_o[16] = mio_attr[MioPadIob7].pull_en;
+ assign cio_gpio_pull_en_o[17] = mio_attr[MioPadIob8].pull_en;
+ assign cio_gpio_pull_en_o[18] = mio_attr[MioPadIob10].pull_en;
+ assign cio_gpio_pull_en_o[19] = mio_attr[MioPadIob11].pull_en;
+ assign cio_gpio_pull_en_o[20] = mio_attr[MioPadIob12].pull_en;
+ assign cio_gpio_pull_en_o[21] = mio_attr[MioPadIoc6].pull_en;
+ assign cio_gpio_pull_en_o[25] = mio_attr[MioPadIoc7].pull_en;
+ assign cio_gpio_pull_en_o[26] = mio_attr[MioPadIoc9].pull_en;
+ assign cio_gpio_pull_en_o[28] = mio_attr[MioPadIor6].pull_en;
+ assign cio_gpio_pull_en_o[29] = mio_attr[MioPadIor7].pull_en;
+ assign cio_gpio_pull_en_o[31] = mio_attr[MioPadIor10].pull_en;
+
+ // Pull enable for SW STRAPs
+ assign cio_gpio_pull_en_o[22] = mio_attr[MioPadIoc0].pull_en;
+ assign cio_gpio_pull_en_o[23] = mio_attr[MioPadIoc1].pull_en;
+ assign cio_gpio_pull_en_o[24] = mio_attr[MioPadIoc2].pull_en;
+
+ // Pull enable for TAP STRAPs
+ assign cio_gpio_pull_en_o[27] = mio_attr[MioPadIoc5].pull_en;
+ assign cio_gpio_pull_en_o[30] = mio_attr[MioPadIoc8].pull_en;
+
+ // Pull select for 14 generic GPIOs
+ assign cio_gpio_pull_select_o[0] = mio_attr[MioPadIoa0].pull_select;
+ assign cio_gpio_pull_select_o[1] = mio_attr[MioPadIoa1].pull_select;
+ assign cio_gpio_pull_select_o[2] = mio_attr[MioPadIoa2].pull_select;
+ assign cio_gpio_pull_select_o[3] = mio_attr[MioPadIoa3].pull_select;
+ assign cio_gpio_pull_select_o[4] = mio_attr[MioPadIoa4].pull_select;
+ assign cio_gpio_pull_select_o[5] = mio_attr[MioPadIoa5].pull_select;
+ assign cio_gpio_pull_select_o[6] = mio_attr[MioPadIoa6].pull_select;
+ assign cio_gpio_pull_select_o[7] = mio_attr[MioPadIoa7].pull_select;
+ assign cio_gpio_pull_select_o[8] = mio_attr[MioPadIoa8].pull_select;
+ assign cio_gpio_pull_select_o[9] = mio_attr[MioPadIob0].pull_select;
+ assign cio_gpio_pull_select_o[10] = mio_attr[MioPadIob1].pull_select;
+ assign cio_gpio_pull_select_o[11] = mio_attr[MioPadIob2].pull_select;
+ assign cio_gpio_pull_select_o[12] = mio_attr[MioPadIob3].pull_select;
+ assign cio_gpio_pull_select_o[13] = mio_attr[MioPadIob4].pull_select;
+ assign cio_gpio_pull_select_o[14] = mio_attr[MioPadIob5].pull_select;
+ assign cio_gpio_pull_select_o[15] = mio_attr[MioPadIob6].pull_select;
+ assign cio_gpio_pull_select_o[16] = mio_attr[MioPadIob7].pull_select;
+ assign cio_gpio_pull_select_o[17] = mio_attr[MioPadIob8].pull_select;
+ assign cio_gpio_pull_select_o[18] = mio_attr[MioPadIob10].pull_select;
+ assign cio_gpio_pull_select_o[19] = mio_attr[MioPadIob11].pull_select;
+ assign cio_gpio_pull_select_o[20] = mio_attr[MioPadIob12].pull_select;
+ assign cio_gpio_pull_select_o[21] = mio_attr[MioPadIoc6].pull_select;
+ assign cio_gpio_pull_select_o[25] = mio_attr[MioPadIoc7].pull_select;
+ assign cio_gpio_pull_select_o[26] = mio_attr[MioPadIoc9].pull_select;
+ assign cio_gpio_pull_select_o[28] = mio_attr[MioPadIor6].pull_select;
+ assign cio_gpio_pull_select_o[29] = mio_attr[MioPadIor7].pull_select;
+ assign cio_gpio_pull_select_o[31] = mio_attr[MioPadIor10].pull_select;
+
+ // Pull select for SW STRAPs
+ assign cio_gpio_pull_select_o[22] = mio_attr[MioPadIoc0].pull_select;
+ assign cio_gpio_pull_select_o[23] = mio_attr[MioPadIoc1].pull_select;
+ assign cio_gpio_pull_select_o[24] = mio_attr[MioPadIoc2].pull_select;
+
+ // Pull select for TAP STRAPs
+ assign cio_gpio_pull_select_o[27] = mio_attr[MioPadIoc5].pull_select;
+ assign cio_gpio_pull_select_o[30] = mio_attr[MioPadIoc8].pull_select;
+
+ ////////////////////////////////
+ // AST - Custom for Verilator //
+ ////////////////////////////////
+ ast_pkg::ast_pwst_t ast_pwst;
+ ast_pkg::ast_pwst_t ast_pwst_h;
+
+ // pwrmgr interface
+ pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
+ pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
+
+ ast_pkg::ast_clks_t ast_base_clks;
+
+ // external clock comes in at a fixed position
+ logic ext_clk;
+ assign ext_clk = '0;
+
+ logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast;
+ assign pad2ast = '0;
+
+ logic clk_aon;
+ // reset is not used below becuase verilator uses only sync resets
+ // and also does not under 'x'.
+ // if we allow the divider below to reset, clk_aon will be silenced,
+ // and as a result all the clk_aon logic inside top_sencha does not
+ // get reset
+ prim_clock_div #(
+ .Divisor(4)
+ ) u_aon_div (
+ .clk_i,
+ .rst_ni(1'b1),
+ .step_down_req_i('0),
+ .step_down_ack_o(),
+ .test_en_i('0),
+ .clk_o(clk_aon)
+ );
+
+ ast_pkg::clks_osc_byp_t clks_osc_byp;
+ assign clks_osc_byp = '{
+ usb: clk_i,
+ sys: clk_i,
+ io: clk_i,
+ aon: clk_aon,
+ smc: clk_i,
+ ml: clk_i,
+ video: clk_i,
+ audio: clk_i
+ };
+
+ ///////////////////////////////////////
+ // AST - Common with other platforms //
+ ///////////////////////////////////////
+
+ // platform specific supply manipulation to create POR
+ logic [3:0] cnt;
+ logic vcc_supp;
+
+ // keep incrementing until saturation
+ always_ff @(posedge clk_aon) begin
+ if (cnt < 4'hf) begin
+ cnt <= cnt + 1'b1;
+ end
+ end
+
+ // create fake por condition
+ assign vcc_supp = cnt < 4'h4 ? 1'b0 :
+ cnt < 4'h8 ? 1'b1 :
+ cnt < 4'hc ? 1'b0 : 1'b1;
+
+ // TLUL interface
+ tlul_pkg::tl_h2d_t base_ast_bus;
+ tlul_pkg::tl_d2h_t ast_base_bus;
+
+ assign ast_base_pwr.main_pok = ast_pwst.main_pok;
+
+ // synchronization clocks / rests
+ clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks;
+ rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets;
+
+ // monitored clock
+ logic sck_monitor;
+
+ // otp power sequence
+ otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
+ otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
+
+ logic usb_ref_pulse;
+ logic usb_ref_val;
+
+ // adc
+ ast_pkg::adc_ast_req_t adc_req;
+ ast_pkg::adc_ast_rsp_t adc_rsp;
+
+ // entropy source interface
+ // The entropy source pacakge definition should eventually be moved to es
+ entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
+ entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
+ logic es_rng_fips;
+
+ // entropy distribution network
+ edn_pkg::edn_req_t ast_edn_edn_req;
+ edn_pkg::edn_rsp_t ast_edn_edn_rsp;
+
+ // alerts interface
+ ast_pkg::ast_alert_rsp_t ast_alert_rsp;
+ ast_pkg::ast_alert_req_t ast_alert_req;
+
+ // Flash connections
+ prim_mubi_pkg::mubi4_t flash_bist_enable;
+ logic flash_power_down_h;
+ logic flash_power_ready_h;
+
+ // Life cycle clock bypass req/ack
+ prim_mubi_pkg::mubi4_t all_clk_byp_req;
+ prim_mubi_pkg::mubi4_t all_clk_byp_ack;
+ prim_mubi_pkg::mubi4_t io_clk_byp_req;
+ prim_mubi_pkg::mubi4_t io_clk_byp_ack;
+ prim_mubi_pkg::mubi4_t div_step_down_req;
+ logic hi_speed_sel;
+
+ // DFT connections
+ logic scan_en;
+ lc_ctrl_pkg::lc_tx_t dft_en;
+ pinmux_pkg::dft_strap_test_req_t dft_strap_test;
+
+ // Debug connections
+ logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
+
+ // Jitter enable
+ logic jen;
+
+ // reset domain connections
+ import rstmgr_pkg::PowerDomains;
+ import rstmgr_pkg::DomainAonSel;
+ import rstmgr_pkg::Domain0Sel;
+
+ // AST does not use all clocks / resets forwarded to it
+ logic unused_slow_clk_en;
+ assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
+
+ logic unused_pwr_clamp;
+ assign unused_pwr_clamp = base_ast_pwr.pwr_clamp;
+
+ logic unused_cio_usbdev_sense_p2d_i;
+ assign unused_cio_usbdev_sense_p2d_i = cio_usbdev_sense_p2d_i;
+
+ prim_mubi_pkg::mubi4_t ast_init_done;
+ ast #(
+ .EntropyStreams(ast_pkg::EntropyStreams),
+ .AdcChannels(ast_pkg::AdcChannels),
+ .AdcDataWidth(ast_pkg::AdcDataWidth),
+ .UsbCalibWidth(ast_pkg::UsbCalibWidth),
+ .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
+ .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
+ ) u_ast (
+ // different between verilator and other platforms
+ .clk_ast_ext_i ( clk_i ),
+ .por_ni ( rst_ni ),
+ // USB IO Pull-up Calibration Setting
+ .usb_io_pu_cal_o ( ),
+ // adc
+ .adc_a0_ai ( '0 ),
+ .adc_a1_ai ( '0 ),
+ // Direct short to PAD
+ .ast2pad_t0_ao ( ),
+ .ast2pad_t1_ao ( ),
+ // Memory configuration connections
+ .dpram_rmf_o ( ),
+ .dpram_rml_o ( ),
+ .spram_rm_o ( ),
+ .sprgf_rm_o ( ),
+ .sprom_rm_o ( ),
+ // clocks' oschillator bypass for FPGA
+ .clk_osc_byp_i ( clks_osc_byp ),
+
+
+ // clocks and resets supplied for detection
+ .sns_clks_i ( clkmgr_aon_clocks ),
+ .sns_rsts_i ( rstmgr_aon_resets ),
+ .sns_spi_ext_clk_i ( sck_monitor ),
+ // tlul
+ .tl_i ( base_ast_bus ),
+ .tl_o ( ast_base_bus ),
+ // init done indication
+ .ast_init_done_o ( ast_init_done),
+ // buffered clocks & resets
+ .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_secure),
+ .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_ast_es_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_ast_usb_i (clkmgr_aon_clocks.clk_usb_peri),
+ .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_adc_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_es_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_rng_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_usb_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]),
+
+ // pok test for FPGA
+ .vcc_supp_i ( vcc_supp ),
+ .vcaon_supp_i ( 1'b1 ),
+ .vcmain_supp_i ( 1'b1 ),
+ .vioa_supp_i ( 1'b1 ),
+ .viob_supp_i ( 1'b1 ),
+ // pok
+ .ast_pwst_o ( ast_pwst ),
+ .ast_pwst_h_o ( ast_pwst_h ),
+ // main regulator
+ .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ),
+ .main_pd_ni ( base_ast_pwr.main_pd_n ),
+ // pdm control (flash)/otp
+ .flash_power_down_h_o ( flash_power_down_h ),
+ .flash_power_ready_h_o ( flash_power_ready_h ),
+ .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
+ // system source clock
+ .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
+ // need to add function in clkmgr
+ .clk_src_sys_jen_i ( jen ),
+ .clk_src_sys_o ( ast_base_clks.clk_sys ),
+ .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
+ // aon source clock
+ .clk_src_aon_o ( ast_base_clks.clk_aon ),
+ .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
+ // io source clock
+ .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
+ .clk_src_io_o ( ast_base_clks.clk_io ),
+ .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
+ .clk_src_io_48m_o ( div_step_down_req ),
+ // usb source clock
+ .usb_ref_pulse_i ( usb_ref_pulse ),
+ .usb_ref_val_i ( usb_ref_val ),
+ .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
+ .clk_src_usb_o ( ast_base_clks.clk_usb ),
+ .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
+ // smc source clock
+ .clk_src_smc_en_i ( base_ast_pwr.smc_clk_en ),
+ .clk_src_smc_o ( ast_base_clks.clk_smc ),
+ .clk_src_smc_val_o ( ast_base_pwr.smc_clk_val),
+ // ml source clock
+ .clk_src_ml_en_i ( base_ast_pwr.ml_clk_en ),
+ .clk_src_ml_o ( ast_base_clks.clk_ml ),
+ .clk_src_ml_val_o ( ast_base_pwr.ml_clk_val),
+ // video source clock
+ .clk_src_video_en_i ( base_ast_pwr.video_clk_en ),
+ .clk_src_video_o ( ast_base_clks.clk_video ),
+ .clk_src_video_val_o ( ast_base_pwr.video_clk_val),
+ // audio source clock
+ .clk_src_audio_en_i ( base_ast_pwr.audio_clk_en ),
+ .clk_src_audio_o ( ast_base_clks.clk_audio ),
+ .clk_src_audio_val_o ( ast_base_pwr.audio_clk_val),
+ // adc
+ .adc_pd_i ( adc_req.pd ),
+ .adc_chnsel_i ( adc_req.channel_sel ),
+ .adc_d_o ( adc_rsp.data ),
+ .adc_d_val_o ( adc_rsp.data_valid ),
+ // rng
+ .rng_en_i ( es_rng_req.rng_enable ),
+ .rng_fips_i ( es_rng_fips ),
+ .rng_val_o ( es_rng_rsp.rng_valid ),
+ .rng_b_o ( es_rng_rsp.rng_b ),
+ // entropy
+ .entropy_rsp_i ( ast_edn_edn_rsp ),
+ .entropy_req_o ( ast_edn_edn_req ),
+ // alerts
+ .alert_rsp_i ( ast_alert_rsp ),
+ .alert_req_o ( ast_alert_req ),
+ // dft
+ .dft_strap_test_i ( dft_strap_test ),
+ .lc_dft_en_i ( dft_en ),
+ .fla_obs_i ( '0 ),
+ .otp_obs_i ( '0 ),
+ .otm_obs_i ( '0 ),
+ .usb_obs_i ( '0 ),
+ .obs_ctrl_o ( ),
+ // pinmux related
+ .padmux2ast_i ( pad2ast ),
+ .ast2padmux_o ( ast2pinmux ),
+ .ext_freq_is_96m_i ( hi_speed_sel ),
+ .all_clk_byp_req_i ( ast_clk_byp_req ),
+ .all_clk_byp_ack_o ( ast_clk_byp_ack ),
+ .io_clk_byp_req_i ( io_clk_byp_req ),
+ .io_clk_byp_ack_o ( io_clk_byp_ack ),
+ .flash_bist_en_o ( flash_bist_enable ),
+ // scan
+ .dft_scan_md_o ( scanmode ),
+ .scan_shift_en_o ( scan_en ),
+ .scan_reset_no ( scan_rst_n )
+ );
+
+
+ // TODO: generate these indices from the target-specific
+ // pinout configuration. But first, this verilator top needs
+ // to be split into a Verilator TB and a Verilator chiplevel.
+ // DFT and Debug signal positions in the pinout.
+ localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
+ tck_idx: MioPadIor3,
+ tms_idx: MioPadIor0,
+ trst_idx: MioPadIor4,
+ tdi_idx: MioPadIor2,
+ tdo_idx: MioPadIor1,
+ tap_strap0_idx: MioPadIoc8,
+ tap_strap1_idx: MioPadIoc5,
+ dft_strap0_idx: MioPadIoc3,
+ dft_strap1_idx: MioPadIoc4,
+ // TODO: check whether there is a better way to pass these USB-specific params
+ usb_dp_idx: DioUsbdevUsbDp,
+ usb_dn_idx: DioUsbdevUsbDn,
+ usb_sense_idx: MioInUsbdevSense,
+ // TODO: connect these once the verilator chip-level has been merged with the chiplevel.sv.tpl
+ dio_pad_type: {pinmux_reg_pkg::NDioPads{prim_pad_wrapper_pkg::BidirStd}},
+ mio_pad_type: {pinmux_reg_pkg::NMioPads{prim_pad_wrapper_pkg::BidirStd}}
+
+ };
+
+ prim_mubi_pkg::mubi4_t lc_clk_bypass;
+
+
+ // Top-level design
+
+ logic [rstmgr_pkg::PowerDomains-1:0] por_n;
+ assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
+
+ top_sencha #(
+ .PinmuxAonTargetCfg(PinmuxTargetCfg),
+ .SecAesAllowForcingMasks(1'b1),
+ .SramCtrlMainInstrExec(1),
+ .SramCtrlRetAonInstrExec(0)
+ ) top_sencha (
+ // update por / reset connections, this is not quite right here
+ .por_n_i (por_n ),
+ .clk_main_i (clk_i ),
+ .clk_io_i (clk_i ),
+ .clk_usb_i (clk_i ),
+ .clk_aon_i (clk_aon ),
+ .clk_smc_i (clk_i ), // TODO(pbf): assign different frequency for smc
+ .clk_ml_i (clk_i ), // TODO(pbf): assign different frequency for ml
+ .clk_video_i (clk_i ), // TODO(pbf): assign different frequency for video
+ .clk_audio_i (clk_i ), // TODO(pbf): assign different frequency for audio
+ // change the above
+ .clks_ast_o (clkmgr_aon_clocks ),
+ .clk_main_jitter_en_o ( jen ),
+ .rsts_ast_o ( rstmgr_aon_resets),
+ .sck_monitor_o ( sck_monitor ),
+ .pwrmgr_ast_req_o ( base_ast_pwr ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .sensor_ctrl_ast_alert_req_i ( ast_alert_req ),
+ .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ),
+ .sensor_ctrl_ast_status_i ( ast_pwst.io_pok ),
+ .usbdev_usb_ref_val_o ( usb_ref_val ),
+ .usbdev_usb_ref_pulse_o ( usb_ref_pulse ),
+ .ast_tl_req_o ( base_ast_bus ),
+ .ast_tl_rsp_i ( ast_base_bus ),
+ .adc_req_o ( adc_req ),
+ .adc_rsp_i ( adc_rsp ),
+ .ast_edn_req_i ( ast_edn_edn_req ),
+ .ast_edn_rsp_o ( ast_edn_edn_rsp ),
+ .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ),
+ .flash_bist_enable_i ( flash_bist_enable ),
+ .flash_power_down_h_i ( flash_power_down_h ),
+ .flash_power_ready_h_i ( flash_power_ready_h ),
+ .es_rng_req_o ( es_rng_req ),
+ .es_rng_rsp_i ( es_rng_rsp ),
+ .es_rng_fips_o ( es_rng_fips ),
+ .all_clk_byp_req_o ( all_clk_byp_req ),
+ .all_clk_byp_ack_i ( all_clk_byp_ack ),
+ .io_clk_byp_req_o ( io_clk_byp_req ),
+ .io_clk_byp_ack_i ( io_clk_byp_ack ),
+ .hi_speed_sel_o ( hi_speed_sel ),
+ .div_step_down_req_i ( div_step_down_req ),
+ .ast2pinmux_i ( ast2pinmux ),
+ .calib_rdy_i ( ast_init_done ),
+ .ast_init_done_i ( ast_init_done ),
+
+ // USB signals
+ .usb_dp_pullup_en_o (usb_dp_pullup),
+ .usb_dn_pullup_en_o (usb_dn_pullup),
+ .usbdev_usb_rx_d_i (usb_rx_d),
+ .usbdev_usb_tx_d_o (usb_tx_d),
+ .usbdev_usb_tx_se0_o (usb_tx_se0),
+ .usbdev_usb_tx_use_d_se0_o (usb_tx_use_d_se0),
+ .usbdev_usb_rx_enable_o (usb_rx_enable),
+
+ // Flash test mode voltages
+ .flash_test_mode_a_io ( ),
+ .flash_test_voltage_h_io ( ),
+
+ // OTP external voltage
+ .otp_ext_voltage_h_io ( ),
+
+ // Multiplexed I/O
+ .mio_in_i (mio_in),
+ .mio_out_o (mio_out),
+ .mio_oe_o (mio_oe),
+
+ // Dedicated I/O
+ .dio_in_i (dio_in),
+ .dio_out_o (dio_out),
+ .dio_oe_o (dio_oe),
+
+ // Pad attributes
+ .mio_attr_o (mio_attr),
+ .dio_attr_o ( ),
+
+ // Memory attributes
+ // This is different between verilator and the rest of the platforms right now
+ .ram_1p_cfg_i ('0),
+ .ram_2p_cfg_i ('0),
+ .rom_cfg_i ('0),
+
+ // DFT signals
+ .ast_lc_dft_en_o ( dft_en ),
+ .dft_strap_test_o ( dft_strap_test ),
+ .dft_hold_tap_sel_i ( '0 ),
+ .scan_rst_ni ( scan_rst_n ),
+ .scan_en_i ( scan_en ),
+ .scanmode_i ( scanmode )
+ );
+
+endmodule : chip_sencha_verilator
diff --git a/hw/top_sencha/rtl/jtag_id_pkg.sv b/hw/top_sencha/rtl/jtag_id_pkg.sv
new file mode 100644
index 0000000..d99d0e7
--- /dev/null
+++ b/hw/top_sencha/rtl/jtag_id_pkg.sv
@@ -0,0 +1,29 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+
+package jtag_id_pkg;
+
+ // This is the open source facing JTAG value that should be replaced
+ // by manufacturers of each OpenTitan
+ localparam logic [31:0] JTAG_IDCODE = {
+ 4'h0, // Version
+ 16'h4F54, // Part Number: "OT"
+ 11'h426, // TODO: This should be replaced with Lowrisc Identity
+ 1'b1 // (fixed)
+ };
+
+endpackage : jtag_id_pkg
diff --git a/hw/top_sencha/rtl/padring.sv b/hw/top_sencha/rtl/padring.sv
new file mode 100644
index 0000000..a5405eb
--- /dev/null
+++ b/hw/top_sencha/rtl/padring.sv
@@ -0,0 +1,122 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// This is the pinmux portion that has to be instantiated on the chip level.
+// The module instantiates the technology dependent pads, and connects them
+// to the MIOs/DIOs and pad attributes coming from the pinmux block.
+//
+
+`include "prim_assert.sv"
+
+module padring
+ import prim_pad_wrapper_pkg::*;
+#(
+ parameter int NDioPads = 1,
+ parameter int NMioPads = 1,
+ parameter pad_type_e [NDioPads-1:0] DioPadType = {NDioPads{BidirStd}},
+ parameter pad_type_e [NMioPads-1:0] MioPadType = {NMioPads{BidirStd}},
+ // Only used for ASIC target
+ parameter bit PhysicalPads = 0,
+ parameter int NIoBanks = 4,
+ parameter logic [NDioPads-1:0][$clog2(NIoBanks):0] DioPadBank = '0,
+ parameter logic [NMioPads-1:0][$clog2(NIoBanks):0] MioPadBank = '0,
+ parameter scan_role_e [NDioPads-1:0] DioScanRole = {NDioPads{NoScan}},
+ parameter scan_role_e [NMioPads-1:0] MioScanRole = {NMioPads{NoScan}}
+) (
+ // This is only used for scan
+ input clk_scan_i,
+ lc_ctrl_pkg::lc_tx_t scanmode_i,
+ // RAW outputs used for DFT and infrastructure
+ // purposes (e.g. external muxed clock)
+ output logic [NDioPads-1:0] dio_in_raw_o,
+ output logic [NMioPads-1:0] mio_in_raw_o,
+ // Pad wires
+ inout wire [NDioPads-1:0] dio_pad_io,
+ inout wire [NMioPads-1:0] mio_pad_io,
+ // Dedicated IO signals coming from peripherals
+ output logic [NDioPads-1:0] dio_in_o,
+ input [NDioPads-1:0] dio_out_i,
+ input [NDioPads-1:0] dio_oe_i,
+ // Muxed IO signals coming from pinmux
+ output logic [NMioPads-1:0] mio_in_o,
+ input [NMioPads-1:0] mio_out_i,
+ input [NMioPads-1:0] mio_oe_i,
+ // Pad attributes from top level instance
+ input pad_attr_t [NDioPads-1:0] dio_attr_i,
+ input pad_attr_t [NMioPads-1:0] mio_attr_i
+);
+
+ pad_pok_t [NIoBanks-1:0] pad_pok;
+
+ logic scanmode;
+ prim_lc_dec u_prim_lc_dec (
+ .lc_en_i ( scanmode_i ),
+ .lc_en_dec_o ( scanmode )
+ );
+
+ for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_pads
+ prim_pad_wrapper #(
+ .PadType ( DioPadType[k] ),
+ .ScanRole ( DioScanRole[k] )
+ ) u_dio_pad (
+ .clk_scan_i,
+ .scanmode_i ( scanmode ),
+ .pok_i ( pad_pok[DioPadBank[k]] ),
+ .inout_io ( dio_pad_io[k] ),
+ .in_o ( dio_in_o[k] ),
+ .in_raw_o ( dio_in_raw_o[k] ),
+ // This is currently not dynamically controlled.
+ // However, this may change in the future if the
+ // need arises (e.g. as part of to power sequencing).
+ .ie_i ( 1'b1 ),
+ .out_i ( dio_out_i[k] ),
+ .oe_i ( dio_oe_i[k] ),
+ .attr_i ( dio_attr_i[k] )
+ );
+ end
+
+ for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_pads
+ prim_pad_wrapper #(
+ .PadType ( MioPadType[k] ),
+ .ScanRole ( MioScanRole[k] )
+ ) u_mio_pad (
+ .clk_scan_i,
+ .scanmode_i ( scanmode ),
+ .pok_i ( pad_pok[MioPadBank[k]] ),
+ .inout_io ( mio_pad_io[k] ),
+ .in_o ( mio_in_o[k] ),
+ .in_raw_o ( mio_in_raw_o[k] ),
+ // This is currently not dynamically controlled.
+ // However, this may change in the future if the
+ // need arises (e.g. as part of to power sequencing).
+ .ie_i ( 1'b1 ),
+ .out_i ( mio_out_i[k] ),
+ .oe_i ( mio_oe_i[k] ),
+ .attr_i ( mio_attr_i[k] )
+ );
+ end
+
+ if (PhysicalPads) begin : gen_physical_pads
+ physical_pads #(
+ .NIoBanks(NIoBanks)
+ ) u_physical_pads (
+ .pad_pok_o(pad_pok)
+ );
+ end else begin : gen_no_physical_pads
+ assign pad_pok = '0;
+ end
+
+endmodule : padring
diff --git a/hw/top_sencha/rtl/scan_role_pkg.sv b/hw/top_sencha/rtl/scan_role_pkg.sv
new file mode 100644
index 0000000..434d60c
--- /dev/null
+++ b/hw/top_sencha/rtl/scan_role_pkg.sv
@@ -0,0 +1,106 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// Open-source scan role definitions for pads.
+// This is only relevant for the ASIC target.
+
+package scan_role_pkg;
+
+ import prim_pad_wrapper_pkg::*;
+
+ parameter scan_role_e DioPadAstMiscScanRole = NoScan;
+ parameter scan_role_e DioPadPorNScanRole = NoScan;
+ parameter scan_role_e DioPadSpiHostD0ScanRole = NoScan;
+ parameter scan_role_e DioPadSpiHostD1ScanRole = NoScan;
+ parameter scan_role_e DioPadSpiHostD2ScanRole = NoScan;
+ parameter scan_role_e DioPadSpiHostD3ScanRole = NoScan;
+ parameter scan_role_e DioPadSpiHostClkScanRole = NoScan;
+ parameter scan_role_e DioPadSpiHostCsLScanRole = NoScan;
+ parameter scan_role_e DioPadSpiDevD0ScanRole = NoScan;
+ parameter scan_role_e DioPadSpiDevD1ScanRole = NoScan;
+ parameter scan_role_e DioPadSpiDevD2ScanRole = NoScan;
+ parameter scan_role_e DioPadSpiDevD3ScanRole = NoScan;
+ parameter scan_role_e DioPadSpiDevClkScanRole = NoScan;
+ parameter scan_role_e DioPadSpiDevCsLScanRole = NoScan;
+ parameter scan_role_e DioPadUsbPScanRole = NoScan;
+ parameter scan_role_e DioPadUsbNScanRole = NoScan;
+ parameter scan_role_e DioPadCc1ScanRole = NoScan;
+ parameter scan_role_e DioPadCc2ScanRole = NoScan;
+ parameter scan_role_e DioPadFlashTestVoltScanRole = NoScan;
+ parameter scan_role_e DioPadFlashTestMode0ScanRole = NoScan;
+ parameter scan_role_e DioPadFlashTestMode1ScanRole = NoScan;
+ parameter scan_role_e DioPadOtpExtVoltScanRole = NoScan;
+ parameter scan_role_e DioPadIor8ScanRole = NoScan;
+ parameter scan_role_e DioPadIor9ScanRole = NoScan;
+ parameter scan_role_e DioPadClkExtScanRole = NoScan;
+ parameter scan_role_e DioPadClkBypScanRole = NoScan;
+ parameter scan_role_e DioPadClk200kScanRole = NoScan;
+ parameter scan_role_e DioPadXtalInScanRole = NoScan;
+ parameter scan_role_e DioPadXtalOutScanRole = NoScan;
+ parameter scan_role_e MioPadIoa0ScanRole = NoScan;
+ parameter scan_role_e MioPadIoa1ScanRole = NoScan;
+ parameter scan_role_e MioPadIoa2ScanRole = NoScan;
+ parameter scan_role_e MioPadIoa3ScanRole = NoScan;
+ parameter scan_role_e MioPadIoa4ScanRole = NoScan;
+ parameter scan_role_e MioPadIoa5ScanRole = NoScan;
+ parameter scan_role_e MioPadIoa6ScanRole = NoScan;
+ parameter scan_role_e MioPadIoa7ScanRole = NoScan;
+ parameter scan_role_e MioPadIoa8ScanRole = NoScan;
+ parameter scan_role_e MioPadIob0ScanRole = NoScan;
+ parameter scan_role_e MioPadIob1ScanRole = NoScan;
+ parameter scan_role_e MioPadIob2ScanRole = NoScan;
+ parameter scan_role_e MioPadIob3ScanRole = NoScan;
+ parameter scan_role_e MioPadIob4ScanRole = NoScan;
+ parameter scan_role_e MioPadIob5ScanRole = NoScan;
+ parameter scan_role_e MioPadIob6ScanRole = NoScan;
+ parameter scan_role_e MioPadIob7ScanRole = NoScan;
+ parameter scan_role_e MioPadIob8ScanRole = NoScan;
+ parameter scan_role_e MioPadIob9ScanRole = NoScan;
+ parameter scan_role_e MioPadIob10ScanRole = NoScan;
+ parameter scan_role_e MioPadIob11ScanRole = NoScan;
+ parameter scan_role_e MioPadIob12ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc0ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc1ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc2ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc3ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc4ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc5ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc6ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc7ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc8ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc9ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc10ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc11ScanRole = NoScan;
+ parameter scan_role_e MioPadIoc12ScanRole = NoScan;
+ parameter scan_role_e MioPadIor0ScanRole = NoScan;
+ parameter scan_role_e MioPadIor1ScanRole = NoScan;
+ parameter scan_role_e MioPadIor2ScanRole = NoScan;
+ parameter scan_role_e MioPadIor3ScanRole = NoScan;
+ parameter scan_role_e MioPadIor4ScanRole = NoScan;
+ parameter scan_role_e MioPadIor5ScanRole = NoScan;
+ parameter scan_role_e MioPadIor6ScanRole = NoScan;
+ parameter scan_role_e MioPadIor7ScanRole = NoScan;
+ parameter scan_role_e MioPadIor10ScanRole = NoScan;
+ parameter scan_role_e MioPadIor11ScanRole = NoScan;
+ parameter scan_role_e MioPadIor12ScanRole = NoScan;
+ parameter scan_role_e MioPadIor13ScanRole = NoScan;
+ parameter scan_role_e MioPadIod0ScanRole = NoScan;
+ parameter scan_role_e MioPadIod1ScanRole = NoScan;
+ parameter scan_role_e MioPadIod2ScanRole = NoScan;
+ parameter scan_role_e MioPadIod3ScanRole = NoScan;
+ parameter scan_role_e MioPadIod4ScanRole = NoScan;
+ parameter scan_role_e MioPadIod5ScanRole = NoScan;
+endpackage : scan_role_pkg
diff --git a/hw/top_sencha/rtl/top_pkg.sv b/hw/top_sencha/rtl/top_pkg.sv
new file mode 100644
index 0000000..7ea19ee
--- /dev/null
+++ b/hw/top_sencha/rtl/top_pkg.sv
@@ -0,0 +1,28 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+
+package top_pkg;
+
+localparam int TL_AW=32;
+localparam int TL_DW=32; // = TL_DBW * 8; TL_DBW must be a power-of-two
+localparam int TL_AIW=10; // a_source, d_source
+localparam int TL_DIW=1; // d_sink
+localparam int TL_AUW=21; // a_user
+localparam int TL_DUW=14; // d_user
+localparam int TL_DBW=(TL_DW>>3);
+localparam int TL_SZW=$clog2($clog2(TL_DBW)+1);
+endpackage
diff --git a/hw/top_sencha/rtl/usr_access_xil7series.sv b/hw/top_sencha/rtl/usr_access_xil7series.sv
new file mode 100644
index 0000000..93348fe
--- /dev/null
+++ b/hw/top_sencha/rtl/usr_access_xil7series.sv
@@ -0,0 +1,28 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module usr_access_xil7series (
+ output logic [31:0] info_o
+
+);
+
+ USR_ACCESSE2 u_fpga_info (
+ .CFGCLK(),
+ .DATA(info_o),
+ .DATAVALID()
+ );
+
+endmodule // usr_access_xil7series
diff --git a/hw/top_sencha/scan_role_pkg.core b/hw/top_sencha/scan_role_pkg.core
new file mode 100644
index 0000000..57ea2b1
--- /dev/null
+++ b/hw/top_sencha/scan_role_pkg.core
@@ -0,0 +1,42 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:scan_role_pkg:0.1"
+description: "Open-source place-holder for scanrole parameters"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:prim:pad_wrapper_pkg
+ files:
+ - rtl/scan_role_pkg.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/hw/top_sencha/sparrow/BUILD b/hw/top_sencha/sparrow/BUILD
new file mode 100644
index 0000000..d6b2ba6
--- /dev/null
+++ b/hw/top_sencha/sparrow/BUILD
@@ -0,0 +1,22 @@
+# Copyright 2024 Google Inc. All Rights Reserved.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+load("@lowrisc_opentitan//rules:linker.bzl", "ld_library")
+
+package(default_visibility = ["//visibility:public"])
+
+# NOTE: All files in this directory were taken from the Sparrow implemention
+# based off Matcha, as a placeholder. If/when a Sparrow V2 ASIC is fabbed based off
+# Sencha, header files exported for that ASIC will need to replace the ones living here.
+cc_library(
+ name = "top_sencha",
+ srcs = [
+ "//hw/top_sencha/sparrow/hw/top_sencha/sw/autogen:top_sencha.c",
+ ],
+ hdrs = [
+ "//hw/top_sencha/sparrow/hw/top_sencha/sw/autogen:top_sencha.h",
+ "//hw/top_sencha/sparrow/hw/top_sencha/sw/autogen:top_sencha_memory.h",
+ ],
+ includes = ["."],
+)
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/BUILD b/hw/top_sencha/sparrow/hw/top_sencha/BUILD
new file mode 100644
index 0000000..3553a05
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/BUILD
@@ -0,0 +1,5 @@
+# Copyright 2024 Google Inc. All Rights Reserved.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+exports_files(glob(["**/*.h"]))
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/alert_handler_regs.h b/hw/top_sencha/sparrow/hw/top_sencha/alert_handler_regs.h
new file mode 100644
index 0000000..c6bf13c
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/alert_handler_regs.h
@@ -0,0 +1,2504 @@
+// Generated register defines for alert_handler
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _ALERT_HANDLER_REG_DEFS_
+#define _ALERT_HANDLER_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of alert channels.
+#define ALERT_HANDLER_PARAM_N_ALERTS 75
+
+// Number of LPGs.
+#define ALERT_HANDLER_PARAM_N_LPG 33
+
+// Width of LPG ID.
+#define ALERT_HANDLER_PARAM_N_LPG_WIDTH 6
+
+// Width of the escalation timer.
+#define ALERT_HANDLER_PARAM_ESC_CNT_DW 32
+
+// Width of the accumulation counter.
+#define ALERT_HANDLER_PARAM_ACCU_CNT_DW 16
+
+// Number of classes
+#define ALERT_HANDLER_PARAM_N_CLASSES 4
+
+// Number of escalation severities
+#define ALERT_HANDLER_PARAM_N_ESC_SEV 4
+
+// Number of escalation phases
+#define ALERT_HANDLER_PARAM_N_PHASES 4
+
+// Number of local alerts
+#define ALERT_HANDLER_PARAM_N_LOC_ALERT 7
+
+// Width of ping counter
+#define ALERT_HANDLER_PARAM_PING_CNT_DW 16
+
+// Width of phase ID
+#define ALERT_HANDLER_PARAM_PHASE_DW 2
+
+// Width of class ID
+#define ALERT_HANDLER_PARAM_CLASS_DW 2
+
+// Local alert ID for alert ping failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_PINGFAIL 0
+
+// Local alert ID for escalation ping failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_PINGFAIL 1
+
+// Local alert ID for alert integrity failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_INTEGFAIL 2
+
+// Local alert ID for escalation integrity failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_INTEGFAIL 3
+
+// Local alert ID for bus integrity failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_BUS_INTEGFAIL 4
+
+// Local alert ID for shadow register update error.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR 5
+
+// Local alert ID for shadow register storage error.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR 6
+
+// Last local alert ID.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_LAST 6
+
+// Register width
+#define ALERT_HANDLER_PARAM_REG_WIDTH 32
+
+// Common Interrupt Offsets
+#define ALERT_HANDLER_INTR_COMMON_CLASSA_BIT 0
+#define ALERT_HANDLER_INTR_COMMON_CLASSB_BIT 1
+#define ALERT_HANDLER_INTR_COMMON_CLASSC_BIT 2
+#define ALERT_HANDLER_INTR_COMMON_CLASSD_BIT 3
+
+// Interrupt State Register
+#define ALERT_HANDLER_INTR_STATE_REG_OFFSET 0x0
+#define ALERT_HANDLER_INTR_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_INTR_STATE_CLASSA_BIT 0
+#define ALERT_HANDLER_INTR_STATE_CLASSB_BIT 1
+#define ALERT_HANDLER_INTR_STATE_CLASSC_BIT 2
+#define ALERT_HANDLER_INTR_STATE_CLASSD_BIT 3
+
+// Interrupt Enable Register
+#define ALERT_HANDLER_INTR_ENABLE_REG_OFFSET 0x4
+#define ALERT_HANDLER_INTR_ENABLE_REG_RESVAL 0x0
+#define ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT 0
+#define ALERT_HANDLER_INTR_ENABLE_CLASSB_BIT 1
+#define ALERT_HANDLER_INTR_ENABLE_CLASSC_BIT 2
+#define ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT 3
+
+// Interrupt Test Register
+#define ALERT_HANDLER_INTR_TEST_REG_OFFSET 0x8
+#define ALERT_HANDLER_INTR_TEST_REG_RESVAL 0x0
+#define ALERT_HANDLER_INTR_TEST_CLASSA_BIT 0
+#define ALERT_HANDLER_INTR_TEST_CLASSB_BIT 1
+#define ALERT_HANDLER_INTR_TEST_CLASSC_BIT 2
+#define ALERT_HANDLER_INTR_TEST_CLASSD_BIT 3
+
+// Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and
+// !!PING_TIMER_EN_SHADOWED.
+#define ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET 0xc
+#define ALERT_HANDLER_PING_TIMER_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_PING_TIMER_REGWEN_PING_TIMER_REGWEN_BIT 0
+
+// Ping timeout cycle count.
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x10
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x100
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK, .index = ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET })
+
+// Ping timer enable.
+#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET 0x14
+#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT 0
+
+// Register write enable for alert enable bits. (common parameters)
+#define ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH 1
+#define ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT 75
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET 0x18
+#define ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_1_REG_OFFSET 0x1c
+#define ALERT_HANDLER_ALERT_REGWEN_1_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_2_REG_OFFSET 0x20
+#define ALERT_HANDLER_ALERT_REGWEN_2_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET 0x24
+#define ALERT_HANDLER_ALERT_REGWEN_3_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_4_REG_OFFSET 0x28
+#define ALERT_HANDLER_ALERT_REGWEN_4_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_5_REG_OFFSET 0x2c
+#define ALERT_HANDLER_ALERT_REGWEN_5_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_6_REG_OFFSET 0x30
+#define ALERT_HANDLER_ALERT_REGWEN_6_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_7_REG_OFFSET 0x34
+#define ALERT_HANDLER_ALERT_REGWEN_7_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_8_REG_OFFSET 0x38
+#define ALERT_HANDLER_ALERT_REGWEN_8_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_9_REG_OFFSET 0x3c
+#define ALERT_HANDLER_ALERT_REGWEN_9_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_10_REG_OFFSET 0x40
+#define ALERT_HANDLER_ALERT_REGWEN_10_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_11_REG_OFFSET 0x44
+#define ALERT_HANDLER_ALERT_REGWEN_11_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_12_REG_OFFSET 0x48
+#define ALERT_HANDLER_ALERT_REGWEN_12_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_13_REG_OFFSET 0x4c
+#define ALERT_HANDLER_ALERT_REGWEN_13_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_14_REG_OFFSET 0x50
+#define ALERT_HANDLER_ALERT_REGWEN_14_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_15_REG_OFFSET 0x54
+#define ALERT_HANDLER_ALERT_REGWEN_15_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_16_REG_OFFSET 0x58
+#define ALERT_HANDLER_ALERT_REGWEN_16_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_17_REG_OFFSET 0x5c
+#define ALERT_HANDLER_ALERT_REGWEN_17_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_18_REG_OFFSET 0x60
+#define ALERT_HANDLER_ALERT_REGWEN_18_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_19_REG_OFFSET 0x64
+#define ALERT_HANDLER_ALERT_REGWEN_19_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_20_REG_OFFSET 0x68
+#define ALERT_HANDLER_ALERT_REGWEN_20_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_21_REG_OFFSET 0x6c
+#define ALERT_HANDLER_ALERT_REGWEN_21_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_22_REG_OFFSET 0x70
+#define ALERT_HANDLER_ALERT_REGWEN_22_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_23_REG_OFFSET 0x74
+#define ALERT_HANDLER_ALERT_REGWEN_23_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_24_REG_OFFSET 0x78
+#define ALERT_HANDLER_ALERT_REGWEN_24_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_25_REG_OFFSET 0x7c
+#define ALERT_HANDLER_ALERT_REGWEN_25_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_26_REG_OFFSET 0x80
+#define ALERT_HANDLER_ALERT_REGWEN_26_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_27_REG_OFFSET 0x84
+#define ALERT_HANDLER_ALERT_REGWEN_27_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_28_REG_OFFSET 0x88
+#define ALERT_HANDLER_ALERT_REGWEN_28_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_29_REG_OFFSET 0x8c
+#define ALERT_HANDLER_ALERT_REGWEN_29_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_30_REG_OFFSET 0x90
+#define ALERT_HANDLER_ALERT_REGWEN_30_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_31_REG_OFFSET 0x94
+#define ALERT_HANDLER_ALERT_REGWEN_31_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_32_REG_OFFSET 0x98
+#define ALERT_HANDLER_ALERT_REGWEN_32_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_33_REG_OFFSET 0x9c
+#define ALERT_HANDLER_ALERT_REGWEN_33_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_34_REG_OFFSET 0xa0
+#define ALERT_HANDLER_ALERT_REGWEN_34_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_35_REG_OFFSET 0xa4
+#define ALERT_HANDLER_ALERT_REGWEN_35_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_36_REG_OFFSET 0xa8
+#define ALERT_HANDLER_ALERT_REGWEN_36_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_37_REG_OFFSET 0xac
+#define ALERT_HANDLER_ALERT_REGWEN_37_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_38_REG_OFFSET 0xb0
+#define ALERT_HANDLER_ALERT_REGWEN_38_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_39_REG_OFFSET 0xb4
+#define ALERT_HANDLER_ALERT_REGWEN_39_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_40_REG_OFFSET 0xb8
+#define ALERT_HANDLER_ALERT_REGWEN_40_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_41_REG_OFFSET 0xbc
+#define ALERT_HANDLER_ALERT_REGWEN_41_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_42_REG_OFFSET 0xc0
+#define ALERT_HANDLER_ALERT_REGWEN_42_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_43_REG_OFFSET 0xc4
+#define ALERT_HANDLER_ALERT_REGWEN_43_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_44_REG_OFFSET 0xc8
+#define ALERT_HANDLER_ALERT_REGWEN_44_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_45_REG_OFFSET 0xcc
+#define ALERT_HANDLER_ALERT_REGWEN_45_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_46_REG_OFFSET 0xd0
+#define ALERT_HANDLER_ALERT_REGWEN_46_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_47_REG_OFFSET 0xd4
+#define ALERT_HANDLER_ALERT_REGWEN_47_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_48_REG_OFFSET 0xd8
+#define ALERT_HANDLER_ALERT_REGWEN_48_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_49_REG_OFFSET 0xdc
+#define ALERT_HANDLER_ALERT_REGWEN_49_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_50_REG_OFFSET 0xe0
+#define ALERT_HANDLER_ALERT_REGWEN_50_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_51_REG_OFFSET 0xe4
+#define ALERT_HANDLER_ALERT_REGWEN_51_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_52_REG_OFFSET 0xe8
+#define ALERT_HANDLER_ALERT_REGWEN_52_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_52_EN_52_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_53_REG_OFFSET 0xec
+#define ALERT_HANDLER_ALERT_REGWEN_53_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_53_EN_53_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_54_REG_OFFSET 0xf0
+#define ALERT_HANDLER_ALERT_REGWEN_54_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_54_EN_54_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_55_REG_OFFSET 0xf4
+#define ALERT_HANDLER_ALERT_REGWEN_55_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_55_EN_55_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_56_REG_OFFSET 0xf8
+#define ALERT_HANDLER_ALERT_REGWEN_56_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_56_EN_56_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_57_REG_OFFSET 0xfc
+#define ALERT_HANDLER_ALERT_REGWEN_57_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_57_EN_57_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_58_REG_OFFSET 0x100
+#define ALERT_HANDLER_ALERT_REGWEN_58_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_58_EN_58_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_59_REG_OFFSET 0x104
+#define ALERT_HANDLER_ALERT_REGWEN_59_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_59_EN_59_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_60_REG_OFFSET 0x108
+#define ALERT_HANDLER_ALERT_REGWEN_60_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_60_EN_60_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_61_REG_OFFSET 0x10c
+#define ALERT_HANDLER_ALERT_REGWEN_61_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_61_EN_61_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_62_REG_OFFSET 0x110
+#define ALERT_HANDLER_ALERT_REGWEN_62_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET 0x114
+#define ALERT_HANDLER_ALERT_REGWEN_63_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET 0x118
+#define ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_65_REG_OFFSET 0x11c
+#define ALERT_HANDLER_ALERT_REGWEN_65_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_65_EN_65_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_66_REG_OFFSET 0x120
+#define ALERT_HANDLER_ALERT_REGWEN_66_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_66_EN_66_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_67_REG_OFFSET 0x124
+#define ALERT_HANDLER_ALERT_REGWEN_67_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_67_EN_67_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_68_REG_OFFSET 0x128
+#define ALERT_HANDLER_ALERT_REGWEN_68_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_68_EN_68_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_69_REG_OFFSET 0x12c
+#define ALERT_HANDLER_ALERT_REGWEN_69_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_69_EN_69_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_70_REG_OFFSET 0x130
+#define ALERT_HANDLER_ALERT_REGWEN_70_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_70_EN_70_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_71_REG_OFFSET 0x134
+#define ALERT_HANDLER_ALERT_REGWEN_71_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_71_EN_71_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_72_REG_OFFSET 0x138
+#define ALERT_HANDLER_ALERT_REGWEN_72_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_72_EN_72_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_73_REG_OFFSET 0x13c
+#define ALERT_HANDLER_ALERT_REGWEN_73_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_73_EN_73_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_74_REG_OFFSET 0x140
+#define ALERT_HANDLER_ALERT_REGWEN_74_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_74_EN_74_BIT 0
+
+// Enable register for alerts. (common parameters)
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH 1
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT 75
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET 0x144
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET 0x148
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET 0x14c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET 0x150
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET 0x154
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET 0x158
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET 0x15c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET 0x160
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET 0x164
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET 0x168
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET 0x16c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET 0x170
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET 0x174
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET 0x178
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET 0x17c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET 0x180
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET 0x184
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET 0x188
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET 0x18c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET 0x190
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET 0x194
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET 0x198
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET 0x19c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET 0x1a0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET 0x1a4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET 0x1a8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET 0x1ac
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET 0x1b0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET 0x1b4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET 0x1b8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET 0x1bc
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET 0x1c0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET 0x1c4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET 0x1c8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET 0x1cc
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET 0x1d0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET 0x1d4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET 0x1d8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET 0x1dc
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET 0x1e0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET 0x1e4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET 0x1e8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET 0x1ec
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET 0x1f0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET 0x1f4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET 0x1f8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET 0x1fc
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET 0x200
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET 0x204
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET 0x208
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET 0x20c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET 0x210
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET 0x214
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET 0x218
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET 0x21c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET 0x220
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET 0x224
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET 0x228
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET 0x22c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET 0x230
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET 0x234
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET 0x238
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET 0x23c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET 0x240
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET 0x244
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_OFFSET 0x248
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_EN_A_65_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_OFFSET 0x24c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_66_EN_A_66_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_OFFSET 0x250
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_67_EN_A_67_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_OFFSET 0x254
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_68_EN_A_68_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_69_REG_OFFSET 0x258
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_69_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_69_EN_A_69_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_70_REG_OFFSET 0x25c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_70_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_70_EN_A_70_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_71_REG_OFFSET 0x260
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_71_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_71_EN_A_71_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_72_REG_OFFSET 0x264
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_72_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_72_EN_A_72_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_73_REG_OFFSET 0x268
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_73_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_73_EN_A_73_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_74_REG_OFFSET 0x26c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_74_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_74_EN_A_74_BIT 0
+
+// Class assignment of alerts. (common parameters)
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH 2
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT 75
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET 0x270
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET })
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB 0x1
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC 0x2
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD 0x3
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET 0x274
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET 0x278
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET 0x27c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET 0x280
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET 0x284
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET 0x288
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET 0x28c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET 0x290
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET 0x294
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET 0x298
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET 0x29c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET 0x2a0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET 0x2a4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET 0x2a8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET 0x2ac
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET 0x2b0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET 0x2b4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET 0x2b8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET 0x2bc
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET 0x2c0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET 0x2c4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET 0x2c8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET 0x2cc
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET 0x2d0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET 0x2d4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET 0x2d8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET 0x2dc
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET 0x2e0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET 0x2e4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET 0x2e8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET 0x2ec
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET 0x2f0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET 0x2f4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET 0x2f8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET 0x2fc
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET 0x300
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET 0x304
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET 0x308
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET 0x30c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET 0x310
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET 0x314
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET 0x318
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET 0x31c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET 0x320
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET 0x324
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET 0x328
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET 0x32c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET 0x330
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET 0x334
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET 0x338
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET 0x33c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET 0x340
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET 0x344
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET 0x348
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET 0x34c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET 0x350
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET 0x354
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET 0x358
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET 0x35c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET 0x360
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET 0x364
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET 0x368
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET 0x36c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET 0x370
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_OFFSET 0x374
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_OFFSET 0x378
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_OFFSET 0x37c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_OFFSET 0x380
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_REG_OFFSET 0x384
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_REG_OFFSET 0x388
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_REG_OFFSET 0x38c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_REG_OFFSET 0x390
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_REG_OFFSET 0x394
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_REG_OFFSET 0x398
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_OFFSET })
+
+// Alert Cause Register (common parameters)
+#define ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH 1
+#define ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT 75
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET 0x39c
+#define ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET 0x3a0
+#define ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET 0x3a4
+#define ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET 0x3a8
+#define ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET 0x3ac
+#define ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET 0x3b0
+#define ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET 0x3b4
+#define ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET 0x3b8
+#define ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET 0x3bc
+#define ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET 0x3c0
+#define ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET 0x3c4
+#define ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET 0x3c8
+#define ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET 0x3cc
+#define ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET 0x3d0
+#define ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET 0x3d4
+#define ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET 0x3d8
+#define ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET 0x3dc
+#define ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET 0x3e0
+#define ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET 0x3e4
+#define ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET 0x3e8
+#define ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET 0x3ec
+#define ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET 0x3f0
+#define ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET 0x3f4
+#define ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET 0x3f8
+#define ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET 0x3fc
+#define ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET 0x400
+#define ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET 0x404
+#define ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET 0x408
+#define ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET 0x40c
+#define ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET 0x410
+#define ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET 0x414
+#define ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET 0x418
+#define ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET 0x41c
+#define ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET 0x420
+#define ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET 0x424
+#define ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET 0x428
+#define ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET 0x42c
+#define ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET 0x430
+#define ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET 0x434
+#define ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET 0x438
+#define ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET 0x43c
+#define ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET 0x440
+#define ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET 0x444
+#define ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET 0x448
+#define ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET 0x44c
+#define ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET 0x450
+#define ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET 0x454
+#define ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET 0x458
+#define ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET 0x45c
+#define ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET 0x460
+#define ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET 0x464
+#define ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET 0x468
+#define ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET 0x46c
+#define ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET 0x470
+#define ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET 0x474
+#define ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET 0x478
+#define ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET 0x47c
+#define ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET 0x480
+#define ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET 0x484
+#define ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET 0x488
+#define ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET 0x48c
+#define ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET 0x490
+#define ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET 0x494
+#define ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET 0x498
+#define ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET 0x49c
+#define ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_65_REG_OFFSET 0x4a0
+#define ALERT_HANDLER_ALERT_CAUSE_65_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_65_A_65_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_66_REG_OFFSET 0x4a4
+#define ALERT_HANDLER_ALERT_CAUSE_66_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_66_A_66_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_67_REG_OFFSET 0x4a8
+#define ALERT_HANDLER_ALERT_CAUSE_67_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_67_A_67_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_68_REG_OFFSET 0x4ac
+#define ALERT_HANDLER_ALERT_CAUSE_68_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_68_A_68_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_69_REG_OFFSET 0x4b0
+#define ALERT_HANDLER_ALERT_CAUSE_69_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_69_A_69_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_70_REG_OFFSET 0x4b4
+#define ALERT_HANDLER_ALERT_CAUSE_70_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_70_A_70_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_71_REG_OFFSET 0x4b8
+#define ALERT_HANDLER_ALERT_CAUSE_71_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_71_A_71_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_72_REG_OFFSET 0x4bc
+#define ALERT_HANDLER_ALERT_CAUSE_72_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_72_A_72_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_73_REG_OFFSET 0x4c0
+#define ALERT_HANDLER_ALERT_CAUSE_73_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_73_A_73_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_74_REG_OFFSET 0x4c4
+#define ALERT_HANDLER_ALERT_CAUSE_74_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_74_A_74_BIT 0
+
+// Register write enable for alert enable bits. (common parameters)
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH 1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT 7
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET 0x4c8
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET 0x4cc
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET 0x4d0
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET 0x4d4
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET 0x4d8
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET 0x4dc
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET 0x4e0
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH 1
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT 7
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET 0x4e4
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET 0x4e8
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET 0x4ec
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET 0x4f0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET 0x4f4
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET 0x4f8
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET 0x4fc
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT 0
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH 2
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT 7
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET 0x500
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET })
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB 0x1
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC 0x2
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD 0x3
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET 0x504
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET 0x508
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET 0x50c
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET 0x510
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET 0x514
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET 0x518
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET })
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH 1
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT 7
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET 0x51c
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET 0x520
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET 0x524
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET 0x528
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET 0x52c
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET 0x530
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET 0x534
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT 0
+
+// Lock bit for Class A configuration.
+#define ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET 0x538
+#define ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT 0
+
+// Escalation control register for alert Class A. Can not be modified if
+// !!CLASSA_REGWEN is false.
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET 0x53c
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL 0x393c
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT 0
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT 1
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT 2
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT 3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT 4
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT 5
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET })
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET })
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET })
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET 12
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET })
+
+// Clear enable for escalation protocol of Class A alerts.
+#define ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET 0x540
+#define ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT 0
+
+// Clear for escalation protocol of Class A.
+#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET 0x544
+#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT 0
+
+// Current accumulation value for alert Class A. Software can clear this
+// register
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET 0x548
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET 0
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET })
+
+// Accumulation threshold value for alert Class A.
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x54c
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET })
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x550
+#define ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Crashdump trigger configuration for Class A.
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x554
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK \
+ 0x3
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
+
+// Duration of escalation phase 0 for Class A.
+#define ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET 0x558
+#define ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 1 for Class A.
+#define ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET 0x55c
+#define ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 2 for Class A.
+#define ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET 0x560
+#define ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 3 for Class A.
+#define ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET 0x564
+#define ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Escalation counter in cycles for Class A.
+#define ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET 0x568
+#define ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL 0x0
+
+// Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
+#define ALERT_HANDLER_CLASSA_STATE_REG_OFFSET 0x56c
+#define ALERT_HANDLER_CLASSA_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK, .index = ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET })
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_IDLE 0x0
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TIMEOUT 0x1
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_FSMERROR 0x2
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TERMINAL 0x3
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0 0x4
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1 0x5
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2 0x6
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3 0x7
+
+// Lock bit for Class B configuration.
+#define ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET 0x570
+#define ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT 0
+
+// Escalation control register for alert Class B. Can not be modified if
+// !!CLASSB_REGWEN is false.
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET 0x574
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL 0x393c
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT 0
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT 1
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E0_BIT 2
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E1_BIT 3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E2_BIT 4
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E3_BIT 5
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET })
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET })
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET })
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET 12
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET })
+
+// Clear enable for escalation protocol of Class B alerts.
+#define ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET 0x578
+#define ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT 0
+
+// Clear for escalation protocol of Class B.
+#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET 0x57c
+#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT 0
+
+// Current accumulation value for alert Class B. Software can clear this
+// register
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET 0x580
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET 0
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET })
+
+// Accumulation threshold value for alert Class B.
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x584
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET })
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x588
+#define ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Crashdump trigger configuration for Class B.
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x58c
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK \
+ 0x3
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
+
+// Duration of escalation phase 0 for Class B.
+#define ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET 0x590
+#define ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 1 for Class B.
+#define ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET 0x594
+#define ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 2 for Class B.
+#define ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET 0x598
+#define ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 3 for Class B.
+#define ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET 0x59c
+#define ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Escalation counter in cycles for Class B.
+#define ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET 0x5a0
+#define ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL 0x0
+
+// Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
+#define ALERT_HANDLER_CLASSB_STATE_REG_OFFSET 0x5a4
+#define ALERT_HANDLER_CLASSB_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK, .index = ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET })
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_IDLE 0x0
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TIMEOUT 0x1
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_FSMERROR 0x2
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TERMINAL 0x3
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0 0x4
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1 0x5
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2 0x6
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3 0x7
+
+// Lock bit for Class C configuration.
+#define ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET 0x5a8
+#define ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT 0
+
+// Escalation control register for alert Class C. Can not be modified if
+// !!CLASSC_REGWEN is false.
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET 0x5ac
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL 0x393c
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT 0
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT 1
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E0_BIT 2
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E1_BIT 3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E2_BIT 4
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E3_BIT 5
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET })
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET })
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET })
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET 12
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET })
+
+// Clear enable for escalation protocol of Class C alerts.
+#define ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET 0x5b0
+#define ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT 0
+
+// Clear for escalation protocol of Class C.
+#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET 0x5b4
+#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT 0
+
+// Current accumulation value for alert Class C. Software can clear this
+// register
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET 0x5b8
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET 0
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET })
+
+// Accumulation threshold value for alert Class C.
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x5bc
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET })
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x5c0
+#define ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Crashdump trigger configuration for Class C.
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x5c4
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK \
+ 0x3
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
+
+// Duration of escalation phase 0 for Class C.
+#define ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET 0x5c8
+#define ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 1 for Class C.
+#define ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET 0x5cc
+#define ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 2 for Class C.
+#define ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET 0x5d0
+#define ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 3 for Class C.
+#define ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET 0x5d4
+#define ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Escalation counter in cycles for Class C.
+#define ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET 0x5d8
+#define ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL 0x0
+
+// Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
+#define ALERT_HANDLER_CLASSC_STATE_REG_OFFSET 0x5dc
+#define ALERT_HANDLER_CLASSC_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK, .index = ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET })
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_IDLE 0x0
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TIMEOUT 0x1
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_FSMERROR 0x2
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TERMINAL 0x3
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0 0x4
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1 0x5
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2 0x6
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3 0x7
+
+// Lock bit for Class D configuration.
+#define ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET 0x5e0
+#define ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT 0
+
+// Escalation control register for alert Class D. Can not be modified if
+// !!CLASSD_REGWEN is false.
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET 0x5e4
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL 0x393c
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT 0
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT 1
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E0_BIT 2
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E1_BIT 3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E2_BIT 4
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E3_BIT 5
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET })
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET })
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET })
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET 12
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET })
+
+// Clear enable for escalation protocol of Class D alerts.
+#define ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET 0x5e8
+#define ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT 0
+
+// Clear for escalation protocol of Class D.
+#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET 0x5ec
+#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT 0
+
+// Current accumulation value for alert Class D. Software can clear this
+// register
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET 0x5f0
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET 0
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET })
+
+// Accumulation threshold value for alert Class D.
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x5f4
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET })
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x5f8
+#define ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Crashdump trigger configuration for Class D.
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x5fc
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK \
+ 0x3
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
+
+// Duration of escalation phase 0 for Class D.
+#define ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET 0x600
+#define ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 1 for Class D.
+#define ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET 0x604
+#define ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 2 for Class D.
+#define ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET 0x608
+#define ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 3 for Class D.
+#define ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET 0x60c
+#define ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Escalation counter in cycles for Class D.
+#define ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET 0x610
+#define ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL 0x0
+
+// Current escalation state of Class D. See also !!CLASSD_ESC_CNT.
+#define ALERT_HANDLER_CLASSD_STATE_REG_OFFSET 0x614
+#define ALERT_HANDLER_CLASSD_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK, .index = ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET })
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_IDLE 0x0
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TIMEOUT 0x1
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_FSMERROR 0x2
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TERMINAL 0x3
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE0 0x4
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE1 0x5
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE2 0x6
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE3 0x7
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _ALERT_HANDLER_REG_DEFS_
+// End generated register defines for alert_handler
\ No newline at end of file
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/ip/ast/data/ast_regs.h b/hw/top_sencha/sparrow/hw/top_sencha/ip/ast/data/ast_regs.h
new file mode 100644
index 0000000..1428f3b
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/ip/ast/data/ast_regs.h
@@ -0,0 +1,458 @@
+// Generated register defines for ast
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _AST_REG_DEFS_
+#define _AST_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of registers in the Array-B
+#define AST_PARAM_NUM_REGS_B 5
+
+// Number of USB valid beacon pulses for clock to re-calibrate
+#define AST_PARAM_NUM_USB_BEACON_PULSES 8
+
+// Register width
+#define AST_PARAM_REG_WIDTH 32
+
+// AST Register 0 for OTP/ROM Write Testing
+#define AST_REGA0_REG_OFFSET 0x0
+#define AST_REGA0_REG_RESVAL 0x0
+
+// AST 1 Register for OTP/ROM Write Testing
+#define AST_REGA1_REG_OFFSET 0x4
+#define AST_REGA1_REG_RESVAL 0x1
+
+// AST 2 Register for OTP/ROM Write Testing
+#define AST_REGA2_REG_OFFSET 0x8
+#define AST_REGA2_REG_RESVAL 0x2
+
+// AST 3 Register for OTP/ROM Write Testing
+#define AST_REGA3_REG_OFFSET 0xc
+#define AST_REGA3_REG_RESVAL 0x3
+
+// AST 4 Register for OTP/ROM Write Testing
+#define AST_REGA4_REG_OFFSET 0x10
+#define AST_REGA4_REG_RESVAL 0x4
+
+// AST 5 Register for OTP/ROM Write Testing
+#define AST_REGA5_REG_OFFSET 0x14
+#define AST_REGA5_REG_RESVAL 0x5
+
+// AST 6 Register for OTP/ROM Write Testing
+#define AST_REGA6_REG_OFFSET 0x18
+#define AST_REGA6_REG_RESVAL 0x6
+
+// AST 7 Register for OTP/ROM Write Testing
+#define AST_REGA7_REG_OFFSET 0x1c
+#define AST_REGA7_REG_RESVAL 0x7
+
+// AST 8 Register for OTP/ROM Write Testing
+#define AST_REGA8_REG_OFFSET 0x20
+#define AST_REGA8_REG_RESVAL 0x8
+
+// AST 9 Register for OTP/ROM Write Testing
+#define AST_REGA9_REG_OFFSET 0x24
+#define AST_REGA9_REG_RESVAL 0x9
+
+// AST 10 Register for OTP/ROM Write Testing
+#define AST_REGA10_REG_OFFSET 0x28
+#define AST_REGA10_REG_RESVAL 0xa
+
+// AST 11 Register for OTP/ROM Write Testing
+#define AST_REGA11_REG_OFFSET 0x2c
+#define AST_REGA11_REG_RESVAL 0xb
+
+// AST 13 Register for OTP/ROM Write Testing
+#define AST_REGA12_REG_OFFSET 0x30
+#define AST_REGA12_REG_RESVAL 0xc
+
+// AST 13 Register for OTP/ROM Write Testing
+#define AST_REGA13_REG_OFFSET 0x34
+#define AST_REGA13_REG_RESVAL 0xd
+
+// AST 14 Register for OTP/ROM Write Testing
+#define AST_REGA14_REG_OFFSET 0x38
+#define AST_REGA14_REG_RESVAL 0xe
+
+// AST 15 Register for OTP/ROM Write Testing
+#define AST_REGA15_REG_OFFSET 0x3c
+#define AST_REGA15_REG_RESVAL 0xf
+
+// AST 16 Register for OTP/ROM Write Testing
+#define AST_REGA16_REG_OFFSET 0x40
+#define AST_REGA16_REG_RESVAL 0x10
+
+// AST 17 Register for OTP/ROM Write Testing
+#define AST_REGA17_REG_OFFSET 0x44
+#define AST_REGA17_REG_RESVAL 0x11
+
+// AST 18 Register for OTP/ROM Write Testing
+#define AST_REGA18_REG_OFFSET 0x48
+#define AST_REGA18_REG_RESVAL 0x12
+
+// AST 19 Register for OTP/ROM Write Testing
+#define AST_REGA19_REG_OFFSET 0x4c
+#define AST_REGA19_REG_RESVAL 0x13
+
+// AST 20 Register for OTP/ROM Write Testing
+#define AST_REGA20_REG_OFFSET 0x50
+#define AST_REGA20_REG_RESVAL 0x14
+
+// AST 21 Register for OTP/ROM Write Testing
+#define AST_REGA21_REG_OFFSET 0x54
+#define AST_REGA21_REG_RESVAL 0x15
+
+// AST 22 Register for OTP/ROM Write Testing
+#define AST_REGA22_REG_OFFSET 0x58
+#define AST_REGA22_REG_RESVAL 0x16
+
+// AST 23 Register for OTP/ROM Write Testing
+#define AST_REGA23_REG_OFFSET 0x5c
+#define AST_REGA23_REG_RESVAL 0x17
+
+// AST 24 Register for OTP/ROM Write Testing
+#define AST_REGA24_REG_OFFSET 0x60
+#define AST_REGA24_REG_RESVAL 0x18
+
+// AST 25 Register for OTP/ROM Write Testing
+#define AST_REGA25_REG_OFFSET 0x64
+#define AST_REGA25_REG_RESVAL 0x19
+
+// AST 26 Register for OTP/ROM Write Testing
+#define AST_REGA26_REG_OFFSET 0x68
+#define AST_REGA26_REG_RESVAL 0x1a
+
+// AST 27 Register for OTP/ROM Write Testing
+#define AST_REGA27_REG_OFFSET 0x6c
+#define AST_REGA27_REG_RESVAL 0x1b
+
+// AST 28 Register for OTP/ROM Write Testing
+#define AST_REGA28_REG_OFFSET 0x70
+#define AST_REGA28_REG_RESVAL 0x1c
+
+// AST 29 Register for OTP/ROM Write Testing
+#define AST_REGA29_REG_OFFSET 0x74
+#define AST_REGA29_REG_RESVAL 0x1d
+
+// AST 30 Register for OTP/ROM Write Testing
+#define AST_REGA30_REG_OFFSET 0x78
+#define AST_REGA30_REG_RESVAL 0x1e
+
+// AST 31 Register for OTP/ROM Write Testing
+#define AST_REGA31_REG_OFFSET 0x7c
+#define AST_REGA31_REG_RESVAL 0x1f
+
+// AST 32 Register for OTP/ROM Write Testing
+#define AST_REGA32_REG_OFFSET 0x80
+#define AST_REGA32_REG_RESVAL 0x20
+
+// AST 33 Register for OTP/ROM Write Testing
+#define AST_REGA33_REG_OFFSET 0x84
+#define AST_REGA33_REG_RESVAL 0x21
+
+// AST 34 Register for OTP/ROM Write Testing
+#define AST_REGA34_REG_OFFSET 0x88
+#define AST_REGA34_REG_RESVAL 0x22
+
+// AST 35 Register for OTP/ROM Write Testing
+#define AST_REGA35_REG_OFFSET 0x8c
+#define AST_REGA35_REG_RESVAL 0x23
+
+// AST 36 Register for OTP/ROM Write Testing
+#define AST_REGA36_REG_OFFSET 0x90
+#define AST_REGA36_REG_RESVAL 0x24
+
+// AST 37 Register for OTP/ROM Write Testing
+#define AST_REGA37_REG_OFFSET 0x94
+#define AST_REGA37_REG_RESVAL 0x25
+
+// AST Last Register for OTP/ROM Write Testing
+#define AST_REGAL_REG_OFFSET 0x98
+#define AST_REGAL_REG_RESVAL 0x26
+
+// PLL0 register contrrol part0
+#define AST_PLL0_CTRL0_REG_OFFSET 0x9c
+#define AST_PLL0_CTRL0_REG_RESVAL 0xc0c00
+#define AST_PLL0_CTRL0_DM_MASK 0x3f
+#define AST_PLL0_CTRL0_DM_OFFSET 0
+#define AST_PLL0_CTRL0_DM_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_DM_MASK, .index = AST_PLL0_CTRL0_DM_OFFSET })
+#define AST_PLL0_CTRL0_DN_MASK 0x7ff
+#define AST_PLL0_CTRL0_DN_OFFSET 6
+#define AST_PLL0_CTRL0_DN_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_DN_MASK, .index = AST_PLL0_CTRL0_DN_OFFSET })
+#define AST_PLL0_CTRL0_DP_MASK 0x7
+#define AST_PLL0_CTRL0_DP_OFFSET 17
+#define AST_PLL0_CTRL0_DP_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_DP_MASK, .index = AST_PLL0_CTRL0_DP_OFFSET })
+#define AST_PLL0_CTRL0_PD_BIT 20
+#define AST_PLL0_CTRL0_PDP_BIT 21
+#define AST_PLL0_CTRL0_RESETN_BIT 22
+#define AST_PLL0_CTRL0_MODE_MASK 0x3
+#define AST_PLL0_CTRL0_MODE_OFFSET 23
+#define AST_PLL0_CTRL0_MODE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_MODE_MASK, .index = AST_PLL0_CTRL0_MODE_OFFSET })
+#define AST_PLL0_CTRL0_BYPASS_BIT 25
+#define AST_PLL0_CTRL0_TEST_EN_BIT 26
+#define AST_PLL0_CTRL0_RSV_MASK 0x1f
+#define AST_PLL0_CTRL0_RSV_OFFSET 27
+#define AST_PLL0_CTRL0_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_RSV_MASK, .index = AST_PLL0_CTRL0_RSV_OFFSET })
+
+// PLL0 CTRL1 register control part1
+#define AST_PLL0_CTRL1_REG_OFFSET 0xa0
+#define AST_PLL0_CTRL1_REG_RESVAL 0x0
+#define AST_PLL0_CTRL1_SSRATE_MASK 0x7ff
+#define AST_PLL0_CTRL1_SSRATE_OFFSET 0
+#define AST_PLL0_CTRL1_SSRATE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL1_SSRATE_MASK, .index = AST_PLL0_CTRL1_SSRATE_OFFSET })
+#define AST_PLL0_CTRL1_RSV_MASK 0x1fffff
+#define AST_PLL0_CTRL1_RSV_OFFSET 11
+#define AST_PLL0_CTRL1_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL1_RSV_MASK, .index = AST_PLL0_CTRL1_RSV_OFFSET })
+
+// PLL0 register control part2
+#define AST_PLL0_CTRL2_REG_OFFSET 0xa4
+#define AST_PLL0_CTRL2_REG_RESVAL 0x0
+#define AST_PLL0_CTRL2_SLOPE_MASK 0xffffff
+#define AST_PLL0_CTRL2_SLOPE_OFFSET 0
+#define AST_PLL0_CTRL2_SLOPE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL2_SLOPE_MASK, .index = AST_PLL0_CTRL2_SLOPE_OFFSET })
+#define AST_PLL0_CTRL2_RSV_MASK 0xff
+#define AST_PLL0_CTRL2_RSV_OFFSET 24
+#define AST_PLL0_CTRL2_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL2_RSV_MASK, .index = AST_PLL0_CTRL2_RSV_OFFSET })
+
+// PLL0 register control part3
+#define AST_PLL0_CTRL3_REG_OFFSET 0xa8
+#define AST_PLL0_CTRL3_REG_RESVAL 0x0
+#define AST_PLL0_CTRL3_FRAC_MASK 0xffffff
+#define AST_PLL0_CTRL3_FRAC_OFFSET 0
+#define AST_PLL0_CTRL3_FRAC_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL3_FRAC_MASK, .index = AST_PLL0_CTRL3_FRAC_OFFSET })
+#define AST_PLL0_CTRL3_RSV_MASK 0xff
+#define AST_PLL0_CTRL3_RSV_OFFSET 24
+#define AST_PLL0_CTRL3_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL3_RSV_MASK, .index = AST_PLL0_CTRL3_RSV_OFFSET })
+
+// PLL1 register control part0
+#define AST_PLL1_CTRL0_REG_OFFSET 0xac
+#define AST_PLL1_CTRL0_REG_RESVAL 0xc1f42
+#define AST_PLL1_CTRL0_DM_MASK 0x3f
+#define AST_PLL1_CTRL0_DM_OFFSET 0
+#define AST_PLL1_CTRL0_DM_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_DM_MASK, .index = AST_PLL1_CTRL0_DM_OFFSET })
+#define AST_PLL1_CTRL0_DN_MASK 0x7ff
+#define AST_PLL1_CTRL0_DN_OFFSET 6
+#define AST_PLL1_CTRL0_DN_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_DN_MASK, .index = AST_PLL1_CTRL0_DN_OFFSET })
+#define AST_PLL1_CTRL0_DP_MASK 0x7
+#define AST_PLL1_CTRL0_DP_OFFSET 17
+#define AST_PLL1_CTRL0_DP_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_DP_MASK, .index = AST_PLL1_CTRL0_DP_OFFSET })
+#define AST_PLL1_CTRL0_PD_BIT 20
+#define AST_PLL1_CTRL0_PDP_BIT 21
+#define AST_PLL1_CTRL0_RESETN_BIT 22
+#define AST_PLL1_CTRL0_MODE_MASK 0x3
+#define AST_PLL1_CTRL0_MODE_OFFSET 23
+#define AST_PLL1_CTRL0_MODE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_MODE_MASK, .index = AST_PLL1_CTRL0_MODE_OFFSET })
+#define AST_PLL1_CTRL0_BYPASS_BIT 25
+#define AST_PLL1_CTRL0_TEST_EN_BIT 26
+#define AST_PLL1_CTRL0_RSV_MASK 0x1f
+#define AST_PLL1_CTRL0_RSV_OFFSET 27
+#define AST_PLL1_CTRL0_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_RSV_MASK, .index = AST_PLL1_CTRL0_RSV_OFFSET })
+
+// PLL1 register control part1
+#define AST_PLL1_CTRL1_REG_OFFSET 0xb0
+#define AST_PLL1_CTRL1_REG_RESVAL 0x0
+#define AST_PLL1_CTRL1_SSRATE_MASK 0x7ff
+#define AST_PLL1_CTRL1_SSRATE_OFFSET 0
+#define AST_PLL1_CTRL1_SSRATE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL1_SSRATE_MASK, .index = AST_PLL1_CTRL1_SSRATE_OFFSET })
+#define AST_PLL1_CTRL1_RSV_MASK 0x1fffff
+#define AST_PLL1_CTRL1_RSV_OFFSET 11
+#define AST_PLL1_CTRL1_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL1_RSV_MASK, .index = AST_PLL1_CTRL1_RSV_OFFSET })
+
+// PLL1 register control part2
+#define AST_PLL1_CTRL2_REG_OFFSET 0xb4
+#define AST_PLL1_CTRL2_REG_RESVAL 0x0
+#define AST_PLL1_CTRL2_SLOPE_MASK 0xffffff
+#define AST_PLL1_CTRL2_SLOPE_OFFSET 0
+#define AST_PLL1_CTRL2_SLOPE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL2_SLOPE_MASK, .index = AST_PLL1_CTRL2_SLOPE_OFFSET })
+#define AST_PLL1_CTRL2_RSV_MASK 0xff
+#define AST_PLL1_CTRL2_RSV_OFFSET 24
+#define AST_PLL1_CTRL2_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL2_RSV_MASK, .index = AST_PLL1_CTRL2_RSV_OFFSET })
+
+// PLL1 register control part3
+#define AST_PLL1_CTRL3_REG_OFFSET 0xb8
+#define AST_PLL1_CTRL3_REG_RESVAL 0x0
+#define AST_PLL1_CTRL3_FRAC_MASK 0xffffff
+#define AST_PLL1_CTRL3_FRAC_OFFSET 0
+#define AST_PLL1_CTRL3_FRAC_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL3_FRAC_MASK, .index = AST_PLL1_CTRL3_FRAC_OFFSET })
+#define AST_PLL1_CTRL3_RSV_MASK 0xff
+#define AST_PLL1_CTRL3_RSV_OFFSET 24
+#define AST_PLL1_CTRL3_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL3_RSV_MASK, .index = AST_PLL1_CTRL3_RSV_OFFSET })
+
+// PLL2 register control part0
+#define AST_PLL2_CTRL0_REG_OFFSET 0xbc
+#define AST_PLL2_CTRL0_REG_RESVAL 0x8e08c0
+#define AST_PLL2_CTRL0_DM_MASK 0x3f
+#define AST_PLL2_CTRL0_DM_OFFSET 0
+#define AST_PLL2_CTRL0_DM_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_DM_MASK, .index = AST_PLL2_CTRL0_DM_OFFSET })
+#define AST_PLL2_CTRL0_DN_MASK 0x7ff
+#define AST_PLL2_CTRL0_DN_OFFSET 6
+#define AST_PLL2_CTRL0_DN_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_DN_MASK, .index = AST_PLL2_CTRL0_DN_OFFSET })
+#define AST_PLL2_CTRL0_DP_MASK 0x7
+#define AST_PLL2_CTRL0_DP_OFFSET 17
+#define AST_PLL2_CTRL0_DP_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_DP_MASK, .index = AST_PLL2_CTRL0_DP_OFFSET })
+#define AST_PLL2_CTRL0_PD_BIT 20
+#define AST_PLL2_CTRL0_PDP_BIT 21
+#define AST_PLL2_CTRL0_RESETN_BIT 22
+#define AST_PLL2_CTRL0_MODE_MASK 0x3
+#define AST_PLL2_CTRL0_MODE_OFFSET 23
+#define AST_PLL2_CTRL0_MODE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_MODE_MASK, .index = AST_PLL2_CTRL0_MODE_OFFSET })
+#define AST_PLL2_CTRL0_BYPASS_BIT 25
+#define AST_PLL2_CTRL0_TEST_EN_BIT 26
+#define AST_PLL2_CTRL0_RSV_MASK 0x1f
+#define AST_PLL2_CTRL0_RSV_OFFSET 27
+#define AST_PLL2_CTRL0_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_RSV_MASK, .index = AST_PLL2_CTRL0_RSV_OFFSET })
+
+// PLL2 register control part1
+#define AST_PLL2_CTRL1_REG_OFFSET 0xc0
+#define AST_PLL2_CTRL1_REG_RESVAL 0x0
+#define AST_PLL2_CTRL1_SSRATE_MASK 0x7ff
+#define AST_PLL2_CTRL1_SSRATE_OFFSET 0
+#define AST_PLL2_CTRL1_SSRATE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL1_SSRATE_MASK, .index = AST_PLL2_CTRL1_SSRATE_OFFSET })
+#define AST_PLL2_CTRL1_RSV_MASK 0x1fffff
+#define AST_PLL2_CTRL1_RSV_OFFSET 11
+#define AST_PLL2_CTRL1_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL1_RSV_MASK, .index = AST_PLL2_CTRL1_RSV_OFFSET })
+
+// PLL2 register control part2
+#define AST_PLL2_CTRL2_REG_OFFSET 0xc4
+#define AST_PLL2_CTRL2_REG_RESVAL 0x0
+#define AST_PLL2_CTRL2_SLOPE_MASK 0xffffff
+#define AST_PLL2_CTRL2_SLOPE_OFFSET 0
+#define AST_PLL2_CTRL2_SLOPE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL2_SLOPE_MASK, .index = AST_PLL2_CTRL2_SLOPE_OFFSET })
+#define AST_PLL2_CTRL2_RSV_MASK 0xff
+#define AST_PLL2_CTRL2_RSV_OFFSET 24
+#define AST_PLL2_CTRL2_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL2_RSV_MASK, .index = AST_PLL2_CTRL2_RSV_OFFSET })
+
+// PLL2 register control part3
+#define AST_PLL2_CTRL3_REG_OFFSET 0xc8
+#define AST_PLL2_CTRL3_REG_RESVAL 0xd70a3e
+#define AST_PLL2_CTRL3_FRAC_MASK 0xffffff
+#define AST_PLL2_CTRL3_FRAC_OFFSET 0
+#define AST_PLL2_CTRL3_FRAC_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL3_FRAC_MASK, .index = AST_PLL2_CTRL3_FRAC_OFFSET })
+#define AST_PLL2_CTRL3_RSV_MASK 0xff
+#define AST_PLL2_CTRL3_RSV_OFFSET 24
+#define AST_PLL2_CTRL3_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL3_RSV_MASK, .index = AST_PLL2_CTRL3_RSV_OFFSET })
+
+// SARADC register control
+#define AST_SARADC_CTRL_REG_OFFSET 0xcc
+#define AST_SARADC_CTRL_REG_RESVAL 0x1
+#define AST_SARADC_CTRL_SOC_BIT 0
+#define AST_SARADC_CTRL_PD_ADC_BIT 1
+#define AST_SARADC_CTRL_SEL_DIFF_BIT 2
+#define AST_SARADC_CTRL_SEL_SPEED_BIT 3
+#define AST_SARADC_CTRL_SEL_CHA_MASK 0x7
+#define AST_SARADC_CTRL_SEL_CHA_OFFSET 4
+#define AST_SARADC_CTRL_SEL_CHA_FIELD \
+ ((bitfield_field32_t) { .mask = AST_SARADC_CTRL_SEL_CHA_MASK, .index = AST_SARADC_CTRL_SEL_CHA_OFFSET })
+#define AST_SARADC_CTRL_EN_VCM_BIT 7
+#define AST_SARADC_CTRL_EN_CAL_BIT 8
+#define AST_SARADC_CTRL_SEL_CMP_BIT 9
+#define AST_SARADC_CTRL_RSV_MASK 0x3fffff
+#define AST_SARADC_CTRL_RSV_OFFSET 10
+#define AST_SARADC_CTRL_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_SARADC_CTRL_RSV_MASK, .index = AST_SARADC_CTRL_RSV_OFFSET })
+
+// SARADC register control
+#define AST_SARADC_DATA_REG_OFFSET 0xd0
+#define AST_SARADC_DATA_REG_RESVAL 0x0
+#define AST_SARADC_DATA_CAL_DONE_BIT 0
+#define AST_SARADC_DATA_EOC_BIT 1
+#define AST_SARADC_DATA_ADC_OUTPUT_MASK 0xfff
+#define AST_SARADC_DATA_ADC_OUTPUT_OFFSET 2
+#define AST_SARADC_DATA_ADC_OUTPUT_FIELD \
+ ((bitfield_field32_t) { .mask = AST_SARADC_DATA_ADC_OUTPUT_MASK, .index = AST_SARADC_DATA_ADC_OUTPUT_OFFSET })
+
+// VT_SENSOR register control
+#define AST_VT_SENSOR_CTRL_REG_OFFSET 0xd4
+#define AST_VT_SENSOR_CTRL_REG_RESVAL 0xc
+#define AST_VT_SENSOR_CTRL_PD_BIT 0
+#define AST_VT_SENSOR_CTRL_TSTCON_BIT 1
+#define AST_VT_SENSOR_CTRL_TSEL_BIT 2
+#define AST_VT_SENSOR_CTRL_VSEL_BIT 3
+#define AST_VT_SENSOR_CTRL_VTRIM_MASK 0xf
+#define AST_VT_SENSOR_CTRL_VTRIM_OFFSET 4
+#define AST_VT_SENSOR_CTRL_VTRIM_FIELD \
+ ((bitfield_field32_t) { .mask = AST_VT_SENSOR_CTRL_VTRIM_MASK, .index = AST_VT_SENSOR_CTRL_VTRIM_OFFSET })
+#define AST_VT_SENSOR_CTRL_RSV_MASK 0xffffff
+#define AST_VT_SENSOR_CTRL_RSV_OFFSET 8
+#define AST_VT_SENSOR_CTRL_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_VT_SENSOR_CTRL_RSV_MASK, .index = AST_VT_SENSOR_CTRL_RSV_OFFSET })
+
+// VT_SENSOR DATA read register
+#define AST_VT_SENSOR_DATA_REG_OFFSET 0xd8
+#define AST_VT_SENSOR_DATA_REG_RESVAL 0x0
+#define AST_VT_SENSOR_DATA_BN_MASK 0xfff
+#define AST_VT_SENSOR_DATA_BN_OFFSET 0
+#define AST_VT_SENSOR_DATA_BN_FIELD \
+ ((bitfield_field32_t) { .mask = AST_VT_SENSOR_DATA_BN_MASK, .index = AST_VT_SENSOR_DATA_BN_OFFSET })
+#define AST_VT_SENSOR_DATA_EOC_BIT 12
+
+// AST Registers Array-B to set address space size (common parameters)
+#define AST_REGB_REG32_FIELD_WIDTH 32
+#define AST_REGB_MULTIREG_COUNT 5
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_0_REG_OFFSET 0x200
+#define AST_REGB_0_REG_RESVAL 0x0
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_1_REG_OFFSET 0x204
+#define AST_REGB_1_REG_RESVAL 0x0
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_2_REG_OFFSET 0x208
+#define AST_REGB_2_REG_RESVAL 0x0
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_3_REG_OFFSET 0x20c
+#define AST_REGB_3_REG_RESVAL 0x0
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_4_REG_OFFSET 0x210
+#define AST_REGB_4_REG_RESVAL 0x0
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _AST_REG_DEFS_
+// End generated register defines for ast
\ No newline at end of file
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/ip/clkmgr/data/autogen/clkmgr_regs.h b/hw/top_sencha/sparrow/hw/top_sencha/ip/clkmgr/data/autogen/clkmgr_regs.h
new file mode 100644
index 0000000..6d6fdd2
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/ip/clkmgr/data/autogen/clkmgr_regs.h
@@ -0,0 +1,327 @@
+// Generated register defines for clkmgr
+
+// Copyright information found in source file:
+// Copyright 2022 Google Inc.Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _CLKMGR_REG_DEFS_
+#define _CLKMGR_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of clock groups
+#define CLKMGR_PARAM_NUM_GROUPS 7
+
+// Number of SW gateable clocks
+#define CLKMGR_PARAM_NUM_SW_GATEABLE_CLOCKS 7
+
+// Number of hintable clocks
+#define CLKMGR_PARAM_NUM_HINTABLE_CLOCKS 7
+
+// Number of alerts
+#define CLKMGR_PARAM_NUM_ALERTS 2
+
+// Register width
+#define CLKMGR_PARAM_REG_WIDTH 32
+
+// Alert Test Register
+#define CLKMGR_ALERT_TEST_REG_OFFSET 0x0
+#define CLKMGR_ALERT_TEST_REG_RESVAL 0x0
+#define CLKMGR_ALERT_TEST_RECOV_FAULT_BIT 0
+#define CLKMGR_ALERT_TEST_FATAL_FAULT_BIT 1
+
+// External clock control write enable
+#define CLKMGR_EXTCLK_CTRL_REGWEN_REG_OFFSET 0x4
+#define CLKMGR_EXTCLK_CTRL_REGWEN_REG_RESVAL 0x1
+#define CLKMGR_EXTCLK_CTRL_REGWEN_EN_BIT 0
+
+// Select external clock
+#define CLKMGR_EXTCLK_CTRL_REG_OFFSET 0x8
+#define CLKMGR_EXTCLK_CTRL_REG_RESVAL 0x99
+#define CLKMGR_EXTCLK_CTRL_SEL_MASK 0xf
+#define CLKMGR_EXTCLK_CTRL_SEL_OFFSET 0
+#define CLKMGR_EXTCLK_CTRL_SEL_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_EXTCLK_CTRL_SEL_MASK, .index = CLKMGR_EXTCLK_CTRL_SEL_OFFSET })
+#define CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_MASK 0xf
+#define CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_OFFSET 4
+#define CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_MASK, .index = CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_OFFSET })
+
+// Status of requested external clock switch
+#define CLKMGR_EXTCLK_STATUS_REG_OFFSET 0xc
+#define CLKMGR_EXTCLK_STATUS_REG_RESVAL 0x9
+#define CLKMGR_EXTCLK_STATUS_ACK_MASK 0xf
+#define CLKMGR_EXTCLK_STATUS_ACK_OFFSET 0
+#define CLKMGR_EXTCLK_STATUS_ACK_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_EXTCLK_STATUS_ACK_MASK, .index = CLKMGR_EXTCLK_STATUS_ACK_OFFSET })
+
+// Jitter write enable
+#define CLKMGR_JITTER_REGWEN_REG_OFFSET 0x10
+#define CLKMGR_JITTER_REGWEN_REG_RESVAL 0x1
+#define CLKMGR_JITTER_REGWEN_EN_BIT 0
+
+// Enable jittery clock
+#define CLKMGR_JITTER_ENABLE_REG_OFFSET 0x14
+#define CLKMGR_JITTER_ENABLE_REG_RESVAL 0x9
+#define CLKMGR_JITTER_ENABLE_VAL_MASK 0xf
+#define CLKMGR_JITTER_ENABLE_VAL_OFFSET 0
+#define CLKMGR_JITTER_ENABLE_VAL_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_JITTER_ENABLE_VAL_MASK, .index = CLKMGR_JITTER_ENABLE_VAL_OFFSET })
+
+// Clock enable for software gateable clocks.
+#define CLKMGR_CLK_ENABLES_REG_OFFSET 0x18
+#define CLKMGR_CLK_ENABLES_REG_RESVAL 0x7f
+#define CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT 0
+#define CLKMGR_CLK_ENABLES_CLK_IO_DIV2_PERI_EN_BIT 1
+#define CLKMGR_CLK_ENABLES_CLK_IO_PERI_EN_BIT 2
+#define CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT 3
+#define CLKMGR_CLK_ENABLES_CLK_ML_PERI_EN_BIT 4
+#define CLKMGR_CLK_ENABLES_CLK_AUDIO_PERI_EN_BIT 5
+#define CLKMGR_CLK_ENABLES_CLK_SMC_PERI_EN_BIT 6
+
+// Clock hint for software gateable transactional clocks during active mode.
+#define CLKMGR_CLK_HINTS_REG_OFFSET 0x1c
+#define CLKMGR_CLK_HINTS_REG_RESVAL 0x7f
+#define CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT 0
+#define CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT 1
+#define CLKMGR_CLK_HINTS_CLK_MAIN_KMAC_HINT_BIT 2
+#define CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT 3
+#define CLKMGR_CLK_HINTS_CLK_SMC_VIDEO_AUDIO_WRAPPER_HINT_BIT 4
+#define CLKMGR_CLK_HINTS_CLK_AUDIO_VSI_CTL_WRAPPER_HINT_BIT 5
+#define CLKMGR_CLK_HINTS_CLK_VIDEO_VSI_CTL_WRAPPER_HINT_BIT 6
+
+// Since the final state of !!CLK_HINTS is not always determined by software,
+#define CLKMGR_CLK_HINTS_STATUS_REG_OFFSET 0x20
+#define CLKMGR_CLK_HINTS_STATUS_REG_RESVAL 0x7f
+#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT 0
+#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_HMAC_VAL_BIT 1
+#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_KMAC_VAL_BIT 2
+#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT 3
+#define CLKMGR_CLK_HINTS_STATUS_CLK_SMC_VIDEO_AUDIO_WRAPPER_VAL_BIT 4
+#define CLKMGR_CLK_HINTS_STATUS_CLK_AUDIO_VSI_CTL_WRAPPER_VAL_BIT 5
+#define CLKMGR_CLK_HINTS_STATUS_CLK_VIDEO_VSI_CTL_WRAPPER_VAL_BIT 6
+
+// Measurement control write enable
+#define CLKMGR_MEASURE_CTRL_REGWEN_REG_OFFSET 0x24
+#define CLKMGR_MEASURE_CTRL_REGWEN_REG_RESVAL 0x1
+#define CLKMGR_MEASURE_CTRL_REGWEN_EN_BIT 0
+
+// Enable for measurement control
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_REG_OFFSET 0x28
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_AUDIO_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_AUDIO_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for audio measurement.
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_REG_OFFSET 0x2c
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_REG_RESVAL 0x12e270
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_MASK 0x7ff
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_MASK 0x7ff
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_OFFSET 11
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_IO_MEAS_CTRL_EN_REG_OFFSET 0x30
+#define CLKMGR_IO_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_IO_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_IO_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_IO_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_IO_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for io measurement.
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_REG_OFFSET 0x34
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_REG_RESVAL 0x759ea
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_MASK 0x3ff
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_MASK 0x3ff
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_OFFSET 10
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_REG_OFFSET 0x38
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for io_div2 measurement.
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_REG_OFFSET 0x3c
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_REG_RESVAL 0x1ccfa
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_MASK 0x1ff
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_MASK 0x1ff
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_OFFSET 9
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_REG_OFFSET 0x40
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for io_div4 measurement.
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_REG_OFFSET 0x44
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_REG_RESVAL 0x6e82
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_MASK 0xff
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_MASK 0xff
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_OFFSET 8
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_MAIN_MEAS_CTRL_EN_REG_OFFSET 0x48
+#define CLKMGR_MAIN_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_MAIN_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_MAIN_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_MAIN_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_MAIN_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_MAIN_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for main measurement.
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_REG_OFFSET 0x4c
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_REG_RESVAL 0x759ea
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_MASK 0x3ff
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_MASK 0x3ff
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_OFFSET 10
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_ML_MEAS_CTRL_EN_REG_OFFSET 0x50
+#define CLKMGR_ML_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_ML_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_ML_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_ML_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_ML_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_ML_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for ml measurement.
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_REG_OFFSET 0x54
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_REG_RESVAL 0x4d84ec
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_MASK 0xfff
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_MASK 0xfff
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_OFFSET 12
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_SMC_MEAS_CTRL_EN_REG_OFFSET 0x58
+#define CLKMGR_SMC_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_SMC_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_SMC_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_SMC_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_SMC_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_SMC_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for smc measurement.
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_REG_OFFSET 0x5c
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_REG_RESVAL 0x759ea
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_MASK 0x3ff
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_MASK 0x3ff
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_OFFSET 10
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_USB_MEAS_CTRL_EN_REG_OFFSET 0x60
+#define CLKMGR_USB_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_USB_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_USB_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_USB_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_USB_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_USB_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for usb measurement.
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_REG_OFFSET 0x64
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_REG_RESVAL 0x1ccfa
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_MASK 0x1ff
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_MASK 0x1ff
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_OFFSET 9
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_REG_OFFSET 0x68
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_VIDEO_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_VIDEO_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for video measurement.
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_REG_OFFSET 0x6c
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_REG_RESVAL 0x759ea
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_MASK 0x3ff
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_MASK 0x3ff
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_OFFSET 10
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Recoverable Error code
+#define CLKMGR_RECOV_ERR_CODE_REG_OFFSET 0x70
+#define CLKMGR_RECOV_ERR_CODE_REG_RESVAL 0x0
+#define CLKMGR_RECOV_ERR_CODE_SHADOW_UPDATE_ERR_BIT 0
+#define CLKMGR_RECOV_ERR_CODE_AUDIO_MEASURE_ERR_BIT 1
+#define CLKMGR_RECOV_ERR_CODE_IO_MEASURE_ERR_BIT 2
+#define CLKMGR_RECOV_ERR_CODE_IO_DIV2_MEASURE_ERR_BIT 3
+#define CLKMGR_RECOV_ERR_CODE_IO_DIV4_MEASURE_ERR_BIT 4
+#define CLKMGR_RECOV_ERR_CODE_MAIN_MEASURE_ERR_BIT 5
+#define CLKMGR_RECOV_ERR_CODE_ML_MEASURE_ERR_BIT 6
+#define CLKMGR_RECOV_ERR_CODE_SMC_MEASURE_ERR_BIT 7
+#define CLKMGR_RECOV_ERR_CODE_USB_MEASURE_ERR_BIT 8
+#define CLKMGR_RECOV_ERR_CODE_VIDEO_MEASURE_ERR_BIT 9
+#define CLKMGR_RECOV_ERR_CODE_AUDIO_TIMEOUT_ERR_BIT 10
+#define CLKMGR_RECOV_ERR_CODE_IO_TIMEOUT_ERR_BIT 11
+#define CLKMGR_RECOV_ERR_CODE_IO_DIV2_TIMEOUT_ERR_BIT 12
+#define CLKMGR_RECOV_ERR_CODE_IO_DIV4_TIMEOUT_ERR_BIT 13
+#define CLKMGR_RECOV_ERR_CODE_MAIN_TIMEOUT_ERR_BIT 14
+#define CLKMGR_RECOV_ERR_CODE_ML_TIMEOUT_ERR_BIT 15
+#define CLKMGR_RECOV_ERR_CODE_SMC_TIMEOUT_ERR_BIT 16
+#define CLKMGR_RECOV_ERR_CODE_USB_TIMEOUT_ERR_BIT 17
+#define CLKMGR_RECOV_ERR_CODE_VIDEO_TIMEOUT_ERR_BIT 18
+
+// Error code
+#define CLKMGR_FATAL_ERR_CODE_REG_OFFSET 0x74
+#define CLKMGR_FATAL_ERR_CODE_REG_RESVAL 0x0
+#define CLKMGR_FATAL_ERR_CODE_REG_INTG_BIT 0
+#define CLKMGR_FATAL_ERR_CODE_IDLE_CNT_BIT 1
+#define CLKMGR_FATAL_ERR_CODE_SHADOW_STORAGE_ERR_BIT 2
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _CLKMGR_REG_DEFS_
+// End generated register defines for clkmgr
\ No newline at end of file
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/ip/pinmux/data/autogen/pinmux_regs.h b/hw/top_sencha/sparrow/hw/top_sencha/ip/pinmux/data/autogen/pinmux_regs.h
new file mode 100644
index 0000000..6afe955
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/ip/pinmux/data/autogen/pinmux_regs.h
@@ -0,0 +1,5240 @@
+// Generated register defines for pinmux
+
+// Copyright information found in source file:
+// Copyright 2022 Google Inc.Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _PINMUX_REG_DEFS_
+#define _PINMUX_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Pad attribute data width
+#define PINMUX_PARAM_ATTR_DW 13
+
+// Number of muxed peripheral inputs
+#define PINMUX_PARAM_N_MIO_PERIPH_IN 84
+
+// Number of muxed peripheral outputs
+#define PINMUX_PARAM_N_MIO_PERIPH_OUT 97
+
+// Number of muxed IO pads
+#define PINMUX_PARAM_N_MIO_PADS 53
+
+// Number of dedicated IO pads
+#define PINMUX_PARAM_N_DIO_PADS 16
+
+// Number of wakeup detectors
+#define PINMUX_PARAM_N_WKUP_DETECT 8
+
+// Number of wakeup counter bits
+#define PINMUX_PARAM_WKUP_CNT_WIDTH 8
+
+// Number of alerts
+#define PINMUX_PARAM_NUM_ALERTS 1
+
+// Register width
+#define PINMUX_PARAM_REG_WIDTH 32
+
+// Alert Test Register
+#define PINMUX_ALERT_TEST_REG_OFFSET 0x0
+#define PINMUX_ALERT_TEST_REG_RESVAL 0x0
+#define PINMUX_ALERT_TEST_FATAL_FAULT_BIT 0
+
+// Register write enable for MIO peripheral input selects. (common
+// parameters)
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_MULTIREG_COUNT 84
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_OFFSET 0x4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_OFFSET 0x8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_OFFSET 0xc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_OFFSET 0x10
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_4_REG_OFFSET 0x14
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_5_REG_OFFSET 0x18
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_6_REG_OFFSET 0x1c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_7_REG_OFFSET 0x20
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_8_REG_OFFSET 0x24
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_9_REG_OFFSET 0x28
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_10_REG_OFFSET 0x2c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_11_REG_OFFSET 0x30
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_12_REG_OFFSET 0x34
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_13_REG_OFFSET 0x38
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_14_REG_OFFSET 0x3c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_15_REG_OFFSET 0x40
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_16_REG_OFFSET 0x44
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_16_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_17_REG_OFFSET 0x48
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_17_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_18_REG_OFFSET 0x4c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_18_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_19_REG_OFFSET 0x50
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_19_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_20_REG_OFFSET 0x54
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_20_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_21_REG_OFFSET 0x58
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_21_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_22_REG_OFFSET 0x5c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_22_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_23_REG_OFFSET 0x60
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_23_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_24_REG_OFFSET 0x64
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_24_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_25_REG_OFFSET 0x68
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_25_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_26_REG_OFFSET 0x6c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_26_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_27_REG_OFFSET 0x70
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_27_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_28_REG_OFFSET 0x74
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_28_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_29_REG_OFFSET 0x78
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_29_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_30_REG_OFFSET 0x7c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_30_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_31_REG_OFFSET 0x80
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_31_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_32_REG_OFFSET 0x84
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_32_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_33_REG_OFFSET 0x88
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_33_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_34_REG_OFFSET 0x8c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_34_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_35_REG_OFFSET 0x90
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_35_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_36_REG_OFFSET 0x94
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_36_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_37_REG_OFFSET 0x98
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_37_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_38_REG_OFFSET 0x9c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_38_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_39_REG_OFFSET 0xa0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_39_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_40_REG_OFFSET 0xa4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_40_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_41_REG_OFFSET 0xa8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_41_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_42_REG_OFFSET 0xac
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_42_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_43_REG_OFFSET 0xb0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_43_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_44_REG_OFFSET 0xb4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_44_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_45_REG_OFFSET 0xb8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_45_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_46_REG_OFFSET 0xbc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_46_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_47_REG_OFFSET 0xc0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_47_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_48_REG_OFFSET 0xc4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_48_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_49_REG_OFFSET 0xc8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_49_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_50_REG_OFFSET 0xcc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_50_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_51_REG_OFFSET 0xd0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_51_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_52_REG_OFFSET 0xd4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_52_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_52_EN_52_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_53_REG_OFFSET 0xd8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_53_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_53_EN_53_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_54_REG_OFFSET 0xdc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_54_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_54_EN_54_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_55_REG_OFFSET 0xe0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_55_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_55_EN_55_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_56_REG_OFFSET 0xe4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_56_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_56_EN_56_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_57_REG_OFFSET 0xe8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_57_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_57_EN_57_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_58_REG_OFFSET 0xec
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_58_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_58_EN_58_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_59_REG_OFFSET 0xf0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_59_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_59_EN_59_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_60_REG_OFFSET 0xf4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_60_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_60_EN_60_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_61_REG_OFFSET 0xf8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_61_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_61_EN_61_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_62_REG_OFFSET 0xfc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_62_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_62_EN_62_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_63_REG_OFFSET 0x100
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_63_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_63_EN_63_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_64_REG_OFFSET 0x104
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_64_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_64_EN_64_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_65_REG_OFFSET 0x108
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_65_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_65_EN_65_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_66_REG_OFFSET 0x10c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_66_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_66_EN_66_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_67_REG_OFFSET 0x110
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_67_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_67_EN_67_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_68_REG_OFFSET 0x114
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_68_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_68_EN_68_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_69_REG_OFFSET 0x118
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_69_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_69_EN_69_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_70_REG_OFFSET 0x11c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_70_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_70_EN_70_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_71_REG_OFFSET 0x120
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_71_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_71_EN_71_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_72_REG_OFFSET 0x124
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_72_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_72_EN_72_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_73_REG_OFFSET 0x128
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_73_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_73_EN_73_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_74_REG_OFFSET 0x12c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_74_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_74_EN_74_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_75_REG_OFFSET 0x130
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_75_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_75_EN_75_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_76_REG_OFFSET 0x134
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_76_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_76_EN_76_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_77_REG_OFFSET 0x138
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_77_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_77_EN_77_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_78_REG_OFFSET 0x13c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_78_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_78_EN_78_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_79_REG_OFFSET 0x140
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_79_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_79_EN_79_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_80_REG_OFFSET 0x144
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_80_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_80_EN_80_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_81_REG_OFFSET 0x148
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_81_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_81_EN_81_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_82_REG_OFFSET 0x14c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_82_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_82_EN_82_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_83_REG_OFFSET 0x150
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_83_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_83_EN_83_BIT 0
+
+// For each peripheral input, this selects the muxable pad input. (common
+// parameters)
+#define PINMUX_MIO_PERIPH_INSEL_IN_FIELD_WIDTH 6
+#define PINMUX_MIO_PERIPH_INSEL_MULTIREG_COUNT 84
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET 0x154
+#define PINMUX_MIO_PERIPH_INSEL_0_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_0_IN_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK, .index = PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_1_REG_OFFSET 0x158
+#define PINMUX_MIO_PERIPH_INSEL_1_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_1_IN_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK, .index = PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_2_REG_OFFSET 0x15c
+#define PINMUX_MIO_PERIPH_INSEL_2_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_2_IN_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK, .index = PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_3_REG_OFFSET 0x160
+#define PINMUX_MIO_PERIPH_INSEL_3_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_3_IN_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK, .index = PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_4_REG_OFFSET 0x164
+#define PINMUX_MIO_PERIPH_INSEL_4_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_4_IN_4_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_4_IN_4_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_4_IN_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_4_IN_4_MASK, .index = PINMUX_MIO_PERIPH_INSEL_4_IN_4_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_5_REG_OFFSET 0x168
+#define PINMUX_MIO_PERIPH_INSEL_5_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_5_IN_5_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_5_IN_5_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_5_IN_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_5_IN_5_MASK, .index = PINMUX_MIO_PERIPH_INSEL_5_IN_5_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_6_REG_OFFSET 0x16c
+#define PINMUX_MIO_PERIPH_INSEL_6_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_6_IN_6_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_6_IN_6_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_6_IN_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_6_IN_6_MASK, .index = PINMUX_MIO_PERIPH_INSEL_6_IN_6_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_7_REG_OFFSET 0x170
+#define PINMUX_MIO_PERIPH_INSEL_7_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_7_IN_7_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_7_IN_7_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_7_IN_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_7_IN_7_MASK, .index = PINMUX_MIO_PERIPH_INSEL_7_IN_7_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_8_REG_OFFSET 0x174
+#define PINMUX_MIO_PERIPH_INSEL_8_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_8_IN_8_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_8_IN_8_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_8_IN_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_8_IN_8_MASK, .index = PINMUX_MIO_PERIPH_INSEL_8_IN_8_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_9_REG_OFFSET 0x178
+#define PINMUX_MIO_PERIPH_INSEL_9_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_9_IN_9_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_9_IN_9_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_9_IN_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_9_IN_9_MASK, .index = PINMUX_MIO_PERIPH_INSEL_9_IN_9_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_10_REG_OFFSET 0x17c
+#define PINMUX_MIO_PERIPH_INSEL_10_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_10_IN_10_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_10_IN_10_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_10_IN_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_10_IN_10_MASK, .index = PINMUX_MIO_PERIPH_INSEL_10_IN_10_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_11_REG_OFFSET 0x180
+#define PINMUX_MIO_PERIPH_INSEL_11_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_11_IN_11_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_11_IN_11_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_11_IN_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_11_IN_11_MASK, .index = PINMUX_MIO_PERIPH_INSEL_11_IN_11_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_12_REG_OFFSET 0x184
+#define PINMUX_MIO_PERIPH_INSEL_12_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_12_IN_12_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_12_IN_12_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_12_IN_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_12_IN_12_MASK, .index = PINMUX_MIO_PERIPH_INSEL_12_IN_12_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_13_REG_OFFSET 0x188
+#define PINMUX_MIO_PERIPH_INSEL_13_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_13_IN_13_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_13_IN_13_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_13_IN_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_13_IN_13_MASK, .index = PINMUX_MIO_PERIPH_INSEL_13_IN_13_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_14_REG_OFFSET 0x18c
+#define PINMUX_MIO_PERIPH_INSEL_14_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_14_IN_14_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_14_IN_14_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_14_IN_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_14_IN_14_MASK, .index = PINMUX_MIO_PERIPH_INSEL_14_IN_14_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_15_REG_OFFSET 0x190
+#define PINMUX_MIO_PERIPH_INSEL_15_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_15_IN_15_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_15_IN_15_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_15_IN_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_15_IN_15_MASK, .index = PINMUX_MIO_PERIPH_INSEL_15_IN_15_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_16_REG_OFFSET 0x194
+#define PINMUX_MIO_PERIPH_INSEL_16_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_16_IN_16_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_16_IN_16_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_16_IN_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_16_IN_16_MASK, .index = PINMUX_MIO_PERIPH_INSEL_16_IN_16_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_17_REG_OFFSET 0x198
+#define PINMUX_MIO_PERIPH_INSEL_17_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_17_IN_17_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_17_IN_17_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_17_IN_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_17_IN_17_MASK, .index = PINMUX_MIO_PERIPH_INSEL_17_IN_17_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_18_REG_OFFSET 0x19c
+#define PINMUX_MIO_PERIPH_INSEL_18_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_18_IN_18_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_18_IN_18_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_18_IN_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_18_IN_18_MASK, .index = PINMUX_MIO_PERIPH_INSEL_18_IN_18_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_19_REG_OFFSET 0x1a0
+#define PINMUX_MIO_PERIPH_INSEL_19_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_19_IN_19_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_19_IN_19_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_19_IN_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_19_IN_19_MASK, .index = PINMUX_MIO_PERIPH_INSEL_19_IN_19_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_20_REG_OFFSET 0x1a4
+#define PINMUX_MIO_PERIPH_INSEL_20_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_20_IN_20_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_20_IN_20_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_20_IN_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_20_IN_20_MASK, .index = PINMUX_MIO_PERIPH_INSEL_20_IN_20_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_21_REG_OFFSET 0x1a8
+#define PINMUX_MIO_PERIPH_INSEL_21_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_21_IN_21_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_21_IN_21_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_21_IN_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_21_IN_21_MASK, .index = PINMUX_MIO_PERIPH_INSEL_21_IN_21_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_22_REG_OFFSET 0x1ac
+#define PINMUX_MIO_PERIPH_INSEL_22_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_22_IN_22_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_22_IN_22_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_22_IN_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_22_IN_22_MASK, .index = PINMUX_MIO_PERIPH_INSEL_22_IN_22_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_23_REG_OFFSET 0x1b0
+#define PINMUX_MIO_PERIPH_INSEL_23_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_23_IN_23_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_23_IN_23_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_23_IN_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_23_IN_23_MASK, .index = PINMUX_MIO_PERIPH_INSEL_23_IN_23_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_24_REG_OFFSET 0x1b4
+#define PINMUX_MIO_PERIPH_INSEL_24_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_24_IN_24_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_24_IN_24_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_24_IN_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_24_IN_24_MASK, .index = PINMUX_MIO_PERIPH_INSEL_24_IN_24_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_25_REG_OFFSET 0x1b8
+#define PINMUX_MIO_PERIPH_INSEL_25_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_25_IN_25_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_25_IN_25_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_25_IN_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_25_IN_25_MASK, .index = PINMUX_MIO_PERIPH_INSEL_25_IN_25_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_26_REG_OFFSET 0x1bc
+#define PINMUX_MIO_PERIPH_INSEL_26_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_26_IN_26_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_26_IN_26_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_26_IN_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_26_IN_26_MASK, .index = PINMUX_MIO_PERIPH_INSEL_26_IN_26_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_27_REG_OFFSET 0x1c0
+#define PINMUX_MIO_PERIPH_INSEL_27_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_27_IN_27_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_27_IN_27_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_27_IN_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_27_IN_27_MASK, .index = PINMUX_MIO_PERIPH_INSEL_27_IN_27_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_28_REG_OFFSET 0x1c4
+#define PINMUX_MIO_PERIPH_INSEL_28_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_28_IN_28_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_28_IN_28_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_28_IN_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_28_IN_28_MASK, .index = PINMUX_MIO_PERIPH_INSEL_28_IN_28_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_29_REG_OFFSET 0x1c8
+#define PINMUX_MIO_PERIPH_INSEL_29_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_29_IN_29_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_29_IN_29_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_29_IN_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_29_IN_29_MASK, .index = PINMUX_MIO_PERIPH_INSEL_29_IN_29_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_30_REG_OFFSET 0x1cc
+#define PINMUX_MIO_PERIPH_INSEL_30_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_30_IN_30_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_30_IN_30_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_30_IN_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_30_IN_30_MASK, .index = PINMUX_MIO_PERIPH_INSEL_30_IN_30_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_31_REG_OFFSET 0x1d0
+#define PINMUX_MIO_PERIPH_INSEL_31_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_31_IN_31_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_31_IN_31_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_31_IN_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_31_IN_31_MASK, .index = PINMUX_MIO_PERIPH_INSEL_31_IN_31_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_32_REG_OFFSET 0x1d4
+#define PINMUX_MIO_PERIPH_INSEL_32_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_32_IN_32_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_32_IN_32_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_32_IN_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_32_IN_32_MASK, .index = PINMUX_MIO_PERIPH_INSEL_32_IN_32_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_33_REG_OFFSET 0x1d8
+#define PINMUX_MIO_PERIPH_INSEL_33_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_33_IN_33_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_33_IN_33_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_33_IN_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_33_IN_33_MASK, .index = PINMUX_MIO_PERIPH_INSEL_33_IN_33_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_34_REG_OFFSET 0x1dc
+#define PINMUX_MIO_PERIPH_INSEL_34_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_34_IN_34_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_34_IN_34_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_34_IN_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_34_IN_34_MASK, .index = PINMUX_MIO_PERIPH_INSEL_34_IN_34_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_35_REG_OFFSET 0x1e0
+#define PINMUX_MIO_PERIPH_INSEL_35_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_35_IN_35_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_35_IN_35_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_35_IN_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_35_IN_35_MASK, .index = PINMUX_MIO_PERIPH_INSEL_35_IN_35_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_36_REG_OFFSET 0x1e4
+#define PINMUX_MIO_PERIPH_INSEL_36_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_36_IN_36_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_36_IN_36_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_36_IN_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_36_IN_36_MASK, .index = PINMUX_MIO_PERIPH_INSEL_36_IN_36_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_37_REG_OFFSET 0x1e8
+#define PINMUX_MIO_PERIPH_INSEL_37_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_37_IN_37_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_37_IN_37_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_37_IN_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_37_IN_37_MASK, .index = PINMUX_MIO_PERIPH_INSEL_37_IN_37_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_38_REG_OFFSET 0x1ec
+#define PINMUX_MIO_PERIPH_INSEL_38_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_38_IN_38_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_38_IN_38_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_38_IN_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_38_IN_38_MASK, .index = PINMUX_MIO_PERIPH_INSEL_38_IN_38_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_39_REG_OFFSET 0x1f0
+#define PINMUX_MIO_PERIPH_INSEL_39_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_39_IN_39_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_39_IN_39_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_39_IN_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_39_IN_39_MASK, .index = PINMUX_MIO_PERIPH_INSEL_39_IN_39_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_40_REG_OFFSET 0x1f4
+#define PINMUX_MIO_PERIPH_INSEL_40_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_40_IN_40_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_40_IN_40_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_40_IN_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_40_IN_40_MASK, .index = PINMUX_MIO_PERIPH_INSEL_40_IN_40_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_41_REG_OFFSET 0x1f8
+#define PINMUX_MIO_PERIPH_INSEL_41_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_41_IN_41_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_41_IN_41_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_41_IN_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_41_IN_41_MASK, .index = PINMUX_MIO_PERIPH_INSEL_41_IN_41_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_42_REG_OFFSET 0x1fc
+#define PINMUX_MIO_PERIPH_INSEL_42_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_42_IN_42_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_42_IN_42_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_42_IN_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_42_IN_42_MASK, .index = PINMUX_MIO_PERIPH_INSEL_42_IN_42_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_43_REG_OFFSET 0x200
+#define PINMUX_MIO_PERIPH_INSEL_43_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_43_IN_43_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_43_IN_43_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_43_IN_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_43_IN_43_MASK, .index = PINMUX_MIO_PERIPH_INSEL_43_IN_43_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_44_REG_OFFSET 0x204
+#define PINMUX_MIO_PERIPH_INSEL_44_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_44_IN_44_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_44_IN_44_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_44_IN_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_44_IN_44_MASK, .index = PINMUX_MIO_PERIPH_INSEL_44_IN_44_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_45_REG_OFFSET 0x208
+#define PINMUX_MIO_PERIPH_INSEL_45_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_45_IN_45_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_45_IN_45_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_45_IN_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_45_IN_45_MASK, .index = PINMUX_MIO_PERIPH_INSEL_45_IN_45_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_46_REG_OFFSET 0x20c
+#define PINMUX_MIO_PERIPH_INSEL_46_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_46_IN_46_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_46_IN_46_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_46_IN_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_46_IN_46_MASK, .index = PINMUX_MIO_PERIPH_INSEL_46_IN_46_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_47_REG_OFFSET 0x210
+#define PINMUX_MIO_PERIPH_INSEL_47_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_47_IN_47_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_47_IN_47_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_47_IN_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_47_IN_47_MASK, .index = PINMUX_MIO_PERIPH_INSEL_47_IN_47_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_48_REG_OFFSET 0x214
+#define PINMUX_MIO_PERIPH_INSEL_48_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_48_IN_48_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_48_IN_48_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_48_IN_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_48_IN_48_MASK, .index = PINMUX_MIO_PERIPH_INSEL_48_IN_48_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_49_REG_OFFSET 0x218
+#define PINMUX_MIO_PERIPH_INSEL_49_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_49_IN_49_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_49_IN_49_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_49_IN_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_49_IN_49_MASK, .index = PINMUX_MIO_PERIPH_INSEL_49_IN_49_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_50_REG_OFFSET 0x21c
+#define PINMUX_MIO_PERIPH_INSEL_50_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_50_IN_50_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_50_IN_50_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_50_IN_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_50_IN_50_MASK, .index = PINMUX_MIO_PERIPH_INSEL_50_IN_50_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_51_REG_OFFSET 0x220
+#define PINMUX_MIO_PERIPH_INSEL_51_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_51_IN_51_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_51_IN_51_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_51_IN_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_51_IN_51_MASK, .index = PINMUX_MIO_PERIPH_INSEL_51_IN_51_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_52_REG_OFFSET 0x224
+#define PINMUX_MIO_PERIPH_INSEL_52_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_52_IN_52_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_52_IN_52_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_52_IN_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_52_IN_52_MASK, .index = PINMUX_MIO_PERIPH_INSEL_52_IN_52_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_53_REG_OFFSET 0x228
+#define PINMUX_MIO_PERIPH_INSEL_53_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_53_IN_53_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_53_IN_53_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_53_IN_53_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_53_IN_53_MASK, .index = PINMUX_MIO_PERIPH_INSEL_53_IN_53_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_54_REG_OFFSET 0x22c
+#define PINMUX_MIO_PERIPH_INSEL_54_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_54_IN_54_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_54_IN_54_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_54_IN_54_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_54_IN_54_MASK, .index = PINMUX_MIO_PERIPH_INSEL_54_IN_54_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_55_REG_OFFSET 0x230
+#define PINMUX_MIO_PERIPH_INSEL_55_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_55_IN_55_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_55_IN_55_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_55_IN_55_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_55_IN_55_MASK, .index = PINMUX_MIO_PERIPH_INSEL_55_IN_55_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_56_REG_OFFSET 0x234
+#define PINMUX_MIO_PERIPH_INSEL_56_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_56_IN_56_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_56_IN_56_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_56_IN_56_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_56_IN_56_MASK, .index = PINMUX_MIO_PERIPH_INSEL_56_IN_56_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_57_REG_OFFSET 0x238
+#define PINMUX_MIO_PERIPH_INSEL_57_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_57_IN_57_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_57_IN_57_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_57_IN_57_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_57_IN_57_MASK, .index = PINMUX_MIO_PERIPH_INSEL_57_IN_57_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_58_REG_OFFSET 0x23c
+#define PINMUX_MIO_PERIPH_INSEL_58_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_58_IN_58_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_58_IN_58_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_58_IN_58_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_58_IN_58_MASK, .index = PINMUX_MIO_PERIPH_INSEL_58_IN_58_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_59_REG_OFFSET 0x240
+#define PINMUX_MIO_PERIPH_INSEL_59_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_59_IN_59_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_59_IN_59_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_59_IN_59_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_59_IN_59_MASK, .index = PINMUX_MIO_PERIPH_INSEL_59_IN_59_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_60_REG_OFFSET 0x244
+#define PINMUX_MIO_PERIPH_INSEL_60_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_60_IN_60_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_60_IN_60_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_60_IN_60_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_60_IN_60_MASK, .index = PINMUX_MIO_PERIPH_INSEL_60_IN_60_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_61_REG_OFFSET 0x248
+#define PINMUX_MIO_PERIPH_INSEL_61_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_61_IN_61_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_61_IN_61_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_61_IN_61_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_61_IN_61_MASK, .index = PINMUX_MIO_PERIPH_INSEL_61_IN_61_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_62_REG_OFFSET 0x24c
+#define PINMUX_MIO_PERIPH_INSEL_62_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_62_IN_62_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_62_IN_62_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_62_IN_62_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_62_IN_62_MASK, .index = PINMUX_MIO_PERIPH_INSEL_62_IN_62_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_63_REG_OFFSET 0x250
+#define PINMUX_MIO_PERIPH_INSEL_63_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_63_IN_63_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_63_IN_63_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_63_IN_63_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_63_IN_63_MASK, .index = PINMUX_MIO_PERIPH_INSEL_63_IN_63_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_64_REG_OFFSET 0x254
+#define PINMUX_MIO_PERIPH_INSEL_64_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_64_IN_64_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_64_IN_64_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_64_IN_64_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_64_IN_64_MASK, .index = PINMUX_MIO_PERIPH_INSEL_64_IN_64_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_65_REG_OFFSET 0x258
+#define PINMUX_MIO_PERIPH_INSEL_65_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_65_IN_65_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_65_IN_65_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_65_IN_65_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_65_IN_65_MASK, .index = PINMUX_MIO_PERIPH_INSEL_65_IN_65_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_66_REG_OFFSET 0x25c
+#define PINMUX_MIO_PERIPH_INSEL_66_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_66_IN_66_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_66_IN_66_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_66_IN_66_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_66_IN_66_MASK, .index = PINMUX_MIO_PERIPH_INSEL_66_IN_66_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_67_REG_OFFSET 0x260
+#define PINMUX_MIO_PERIPH_INSEL_67_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_67_IN_67_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_67_IN_67_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_67_IN_67_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_67_IN_67_MASK, .index = PINMUX_MIO_PERIPH_INSEL_67_IN_67_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_68_REG_OFFSET 0x264
+#define PINMUX_MIO_PERIPH_INSEL_68_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_68_IN_68_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_68_IN_68_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_68_IN_68_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_68_IN_68_MASK, .index = PINMUX_MIO_PERIPH_INSEL_68_IN_68_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_69_REG_OFFSET 0x268
+#define PINMUX_MIO_PERIPH_INSEL_69_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_69_IN_69_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_69_IN_69_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_69_IN_69_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_69_IN_69_MASK, .index = PINMUX_MIO_PERIPH_INSEL_69_IN_69_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_70_REG_OFFSET 0x26c
+#define PINMUX_MIO_PERIPH_INSEL_70_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_70_IN_70_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_70_IN_70_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_70_IN_70_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_70_IN_70_MASK, .index = PINMUX_MIO_PERIPH_INSEL_70_IN_70_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_71_REG_OFFSET 0x270
+#define PINMUX_MIO_PERIPH_INSEL_71_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_71_IN_71_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_71_IN_71_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_71_IN_71_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_71_IN_71_MASK, .index = PINMUX_MIO_PERIPH_INSEL_71_IN_71_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_72_REG_OFFSET 0x274
+#define PINMUX_MIO_PERIPH_INSEL_72_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_72_IN_72_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_72_IN_72_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_72_IN_72_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_72_IN_72_MASK, .index = PINMUX_MIO_PERIPH_INSEL_72_IN_72_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_73_REG_OFFSET 0x278
+#define PINMUX_MIO_PERIPH_INSEL_73_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_73_IN_73_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_73_IN_73_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_73_IN_73_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_73_IN_73_MASK, .index = PINMUX_MIO_PERIPH_INSEL_73_IN_73_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_74_REG_OFFSET 0x27c
+#define PINMUX_MIO_PERIPH_INSEL_74_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_74_IN_74_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_74_IN_74_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_74_IN_74_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_74_IN_74_MASK, .index = PINMUX_MIO_PERIPH_INSEL_74_IN_74_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_75_REG_OFFSET 0x280
+#define PINMUX_MIO_PERIPH_INSEL_75_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_75_IN_75_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_75_IN_75_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_75_IN_75_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_75_IN_75_MASK, .index = PINMUX_MIO_PERIPH_INSEL_75_IN_75_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_76_REG_OFFSET 0x284
+#define PINMUX_MIO_PERIPH_INSEL_76_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_76_IN_76_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_76_IN_76_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_76_IN_76_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_76_IN_76_MASK, .index = PINMUX_MIO_PERIPH_INSEL_76_IN_76_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_77_REG_OFFSET 0x288
+#define PINMUX_MIO_PERIPH_INSEL_77_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_77_IN_77_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_77_IN_77_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_77_IN_77_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_77_IN_77_MASK, .index = PINMUX_MIO_PERIPH_INSEL_77_IN_77_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_78_REG_OFFSET 0x28c
+#define PINMUX_MIO_PERIPH_INSEL_78_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_78_IN_78_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_78_IN_78_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_78_IN_78_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_78_IN_78_MASK, .index = PINMUX_MIO_PERIPH_INSEL_78_IN_78_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_79_REG_OFFSET 0x290
+#define PINMUX_MIO_PERIPH_INSEL_79_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_79_IN_79_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_79_IN_79_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_79_IN_79_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_79_IN_79_MASK, .index = PINMUX_MIO_PERIPH_INSEL_79_IN_79_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_80_REG_OFFSET 0x294
+#define PINMUX_MIO_PERIPH_INSEL_80_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_80_IN_80_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_80_IN_80_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_80_IN_80_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_80_IN_80_MASK, .index = PINMUX_MIO_PERIPH_INSEL_80_IN_80_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_81_REG_OFFSET 0x298
+#define PINMUX_MIO_PERIPH_INSEL_81_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_81_IN_81_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_81_IN_81_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_81_IN_81_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_81_IN_81_MASK, .index = PINMUX_MIO_PERIPH_INSEL_81_IN_81_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_82_REG_OFFSET 0x29c
+#define PINMUX_MIO_PERIPH_INSEL_82_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_82_IN_82_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_82_IN_82_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_82_IN_82_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_82_IN_82_MASK, .index = PINMUX_MIO_PERIPH_INSEL_82_IN_82_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_83_REG_OFFSET 0x2a0
+#define PINMUX_MIO_PERIPH_INSEL_83_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_83_IN_83_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_83_IN_83_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_83_IN_83_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_83_IN_83_MASK, .index = PINMUX_MIO_PERIPH_INSEL_83_IN_83_OFFSET })
+
+// Register write enable for MIO output selects. (common parameters)
+#define PINMUX_MIO_OUTSEL_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_OUTSEL_REGWEN_MULTIREG_COUNT 53
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_0_REG_OFFSET 0x2a4
+#define PINMUX_MIO_OUTSEL_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_1_REG_OFFSET 0x2a8
+#define PINMUX_MIO_OUTSEL_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_2_REG_OFFSET 0x2ac
+#define PINMUX_MIO_OUTSEL_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_3_REG_OFFSET 0x2b0
+#define PINMUX_MIO_OUTSEL_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_4_REG_OFFSET 0x2b4
+#define PINMUX_MIO_OUTSEL_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_5_REG_OFFSET 0x2b8
+#define PINMUX_MIO_OUTSEL_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_6_REG_OFFSET 0x2bc
+#define PINMUX_MIO_OUTSEL_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_7_REG_OFFSET 0x2c0
+#define PINMUX_MIO_OUTSEL_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_8_REG_OFFSET 0x2c4
+#define PINMUX_MIO_OUTSEL_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_9_REG_OFFSET 0x2c8
+#define PINMUX_MIO_OUTSEL_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_10_REG_OFFSET 0x2cc
+#define PINMUX_MIO_OUTSEL_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_11_REG_OFFSET 0x2d0
+#define PINMUX_MIO_OUTSEL_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_12_REG_OFFSET 0x2d4
+#define PINMUX_MIO_OUTSEL_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_13_REG_OFFSET 0x2d8
+#define PINMUX_MIO_OUTSEL_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_14_REG_OFFSET 0x2dc
+#define PINMUX_MIO_OUTSEL_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_15_REG_OFFSET 0x2e0
+#define PINMUX_MIO_OUTSEL_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_16_REG_OFFSET 0x2e4
+#define PINMUX_MIO_OUTSEL_REGWEN_16_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_17_REG_OFFSET 0x2e8
+#define PINMUX_MIO_OUTSEL_REGWEN_17_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_18_REG_OFFSET 0x2ec
+#define PINMUX_MIO_OUTSEL_REGWEN_18_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_19_REG_OFFSET 0x2f0
+#define PINMUX_MIO_OUTSEL_REGWEN_19_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_20_REG_OFFSET 0x2f4
+#define PINMUX_MIO_OUTSEL_REGWEN_20_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_21_REG_OFFSET 0x2f8
+#define PINMUX_MIO_OUTSEL_REGWEN_21_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_22_REG_OFFSET 0x2fc
+#define PINMUX_MIO_OUTSEL_REGWEN_22_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_23_REG_OFFSET 0x300
+#define PINMUX_MIO_OUTSEL_REGWEN_23_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_24_REG_OFFSET 0x304
+#define PINMUX_MIO_OUTSEL_REGWEN_24_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_25_REG_OFFSET 0x308
+#define PINMUX_MIO_OUTSEL_REGWEN_25_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_26_REG_OFFSET 0x30c
+#define PINMUX_MIO_OUTSEL_REGWEN_26_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_27_REG_OFFSET 0x310
+#define PINMUX_MIO_OUTSEL_REGWEN_27_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_28_REG_OFFSET 0x314
+#define PINMUX_MIO_OUTSEL_REGWEN_28_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_29_REG_OFFSET 0x318
+#define PINMUX_MIO_OUTSEL_REGWEN_29_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_30_REG_OFFSET 0x31c
+#define PINMUX_MIO_OUTSEL_REGWEN_30_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_31_REG_OFFSET 0x320
+#define PINMUX_MIO_OUTSEL_REGWEN_31_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_32_REG_OFFSET 0x324
+#define PINMUX_MIO_OUTSEL_REGWEN_32_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_33_REG_OFFSET 0x328
+#define PINMUX_MIO_OUTSEL_REGWEN_33_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_34_REG_OFFSET 0x32c
+#define PINMUX_MIO_OUTSEL_REGWEN_34_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_35_REG_OFFSET 0x330
+#define PINMUX_MIO_OUTSEL_REGWEN_35_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_36_REG_OFFSET 0x334
+#define PINMUX_MIO_OUTSEL_REGWEN_36_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_37_REG_OFFSET 0x338
+#define PINMUX_MIO_OUTSEL_REGWEN_37_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_38_REG_OFFSET 0x33c
+#define PINMUX_MIO_OUTSEL_REGWEN_38_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_39_REG_OFFSET 0x340
+#define PINMUX_MIO_OUTSEL_REGWEN_39_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_40_REG_OFFSET 0x344
+#define PINMUX_MIO_OUTSEL_REGWEN_40_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_41_REG_OFFSET 0x348
+#define PINMUX_MIO_OUTSEL_REGWEN_41_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_42_REG_OFFSET 0x34c
+#define PINMUX_MIO_OUTSEL_REGWEN_42_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_43_REG_OFFSET 0x350
+#define PINMUX_MIO_OUTSEL_REGWEN_43_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_44_REG_OFFSET 0x354
+#define PINMUX_MIO_OUTSEL_REGWEN_44_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_45_REG_OFFSET 0x358
+#define PINMUX_MIO_OUTSEL_REGWEN_45_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_46_REG_OFFSET 0x35c
+#define PINMUX_MIO_OUTSEL_REGWEN_46_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_47_REG_OFFSET 0x360
+#define PINMUX_MIO_OUTSEL_REGWEN_47_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_48_REG_OFFSET 0x364
+#define PINMUX_MIO_OUTSEL_REGWEN_48_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_49_REG_OFFSET 0x368
+#define PINMUX_MIO_OUTSEL_REGWEN_49_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_50_REG_OFFSET 0x36c
+#define PINMUX_MIO_OUTSEL_REGWEN_50_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_51_REG_OFFSET 0x370
+#define PINMUX_MIO_OUTSEL_REGWEN_51_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_52_REG_OFFSET 0x374
+#define PINMUX_MIO_OUTSEL_REGWEN_52_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_52_EN_52_BIT 0
+
+// For each muxable pad, this selects the peripheral output. (common
+// parameters)
+#define PINMUX_MIO_OUTSEL_OUT_FIELD_WIDTH 7
+#define PINMUX_MIO_OUTSEL_MULTIREG_COUNT 53
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_0_REG_OFFSET 0x378
+#define PINMUX_MIO_OUTSEL_0_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_0_OUT_0_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET 0
+#define PINMUX_MIO_OUTSEL_0_OUT_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_0_OUT_0_MASK, .index = PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_1_REG_OFFSET 0x37c
+#define PINMUX_MIO_OUTSEL_1_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_1_OUT_1_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET 0
+#define PINMUX_MIO_OUTSEL_1_OUT_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_1_OUT_1_MASK, .index = PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_2_REG_OFFSET 0x380
+#define PINMUX_MIO_OUTSEL_2_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_2_OUT_2_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET 0
+#define PINMUX_MIO_OUTSEL_2_OUT_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_2_OUT_2_MASK, .index = PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_3_REG_OFFSET 0x384
+#define PINMUX_MIO_OUTSEL_3_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_3_OUT_3_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET 0
+#define PINMUX_MIO_OUTSEL_3_OUT_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_3_OUT_3_MASK, .index = PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_4_REG_OFFSET 0x388
+#define PINMUX_MIO_OUTSEL_4_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_4_OUT_4_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET 0
+#define PINMUX_MIO_OUTSEL_4_OUT_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_4_OUT_4_MASK, .index = PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_5_REG_OFFSET 0x38c
+#define PINMUX_MIO_OUTSEL_5_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_5_OUT_5_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET 0
+#define PINMUX_MIO_OUTSEL_5_OUT_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_5_OUT_5_MASK, .index = PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_6_REG_OFFSET 0x390
+#define PINMUX_MIO_OUTSEL_6_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_6_OUT_6_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET 0
+#define PINMUX_MIO_OUTSEL_6_OUT_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_6_OUT_6_MASK, .index = PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_7_REG_OFFSET 0x394
+#define PINMUX_MIO_OUTSEL_7_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_7_OUT_7_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET 0
+#define PINMUX_MIO_OUTSEL_7_OUT_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_7_OUT_7_MASK, .index = PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_8_REG_OFFSET 0x398
+#define PINMUX_MIO_OUTSEL_8_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_8_OUT_8_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET 0
+#define PINMUX_MIO_OUTSEL_8_OUT_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_8_OUT_8_MASK, .index = PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_9_REG_OFFSET 0x39c
+#define PINMUX_MIO_OUTSEL_9_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_9_OUT_9_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET 0
+#define PINMUX_MIO_OUTSEL_9_OUT_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_9_OUT_9_MASK, .index = PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_10_REG_OFFSET 0x3a0
+#define PINMUX_MIO_OUTSEL_10_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_10_OUT_10_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET 0
+#define PINMUX_MIO_OUTSEL_10_OUT_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_10_OUT_10_MASK, .index = PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_11_REG_OFFSET 0x3a4
+#define PINMUX_MIO_OUTSEL_11_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_11_OUT_11_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET 0
+#define PINMUX_MIO_OUTSEL_11_OUT_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_11_OUT_11_MASK, .index = PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_12_REG_OFFSET 0x3a8
+#define PINMUX_MIO_OUTSEL_12_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_12_OUT_12_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_12_OUT_12_OFFSET 0
+#define PINMUX_MIO_OUTSEL_12_OUT_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_12_OUT_12_MASK, .index = PINMUX_MIO_OUTSEL_12_OUT_12_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_13_REG_OFFSET 0x3ac
+#define PINMUX_MIO_OUTSEL_13_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_13_OUT_13_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_13_OUT_13_OFFSET 0
+#define PINMUX_MIO_OUTSEL_13_OUT_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_13_OUT_13_MASK, .index = PINMUX_MIO_OUTSEL_13_OUT_13_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_14_REG_OFFSET 0x3b0
+#define PINMUX_MIO_OUTSEL_14_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_14_OUT_14_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_14_OUT_14_OFFSET 0
+#define PINMUX_MIO_OUTSEL_14_OUT_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_14_OUT_14_MASK, .index = PINMUX_MIO_OUTSEL_14_OUT_14_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_15_REG_OFFSET 0x3b4
+#define PINMUX_MIO_OUTSEL_15_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_15_OUT_15_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_15_OUT_15_OFFSET 0
+#define PINMUX_MIO_OUTSEL_15_OUT_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_15_OUT_15_MASK, .index = PINMUX_MIO_OUTSEL_15_OUT_15_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_16_REG_OFFSET 0x3b8
+#define PINMUX_MIO_OUTSEL_16_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_16_OUT_16_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_16_OUT_16_OFFSET 0
+#define PINMUX_MIO_OUTSEL_16_OUT_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_16_OUT_16_MASK, .index = PINMUX_MIO_OUTSEL_16_OUT_16_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_17_REG_OFFSET 0x3bc
+#define PINMUX_MIO_OUTSEL_17_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_17_OUT_17_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_17_OUT_17_OFFSET 0
+#define PINMUX_MIO_OUTSEL_17_OUT_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_17_OUT_17_MASK, .index = PINMUX_MIO_OUTSEL_17_OUT_17_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_18_REG_OFFSET 0x3c0
+#define PINMUX_MIO_OUTSEL_18_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_18_OUT_18_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_18_OUT_18_OFFSET 0
+#define PINMUX_MIO_OUTSEL_18_OUT_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_18_OUT_18_MASK, .index = PINMUX_MIO_OUTSEL_18_OUT_18_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_19_REG_OFFSET 0x3c4
+#define PINMUX_MIO_OUTSEL_19_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_19_OUT_19_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_19_OUT_19_OFFSET 0
+#define PINMUX_MIO_OUTSEL_19_OUT_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_19_OUT_19_MASK, .index = PINMUX_MIO_OUTSEL_19_OUT_19_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_20_REG_OFFSET 0x3c8
+#define PINMUX_MIO_OUTSEL_20_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_20_OUT_20_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_20_OUT_20_OFFSET 0
+#define PINMUX_MIO_OUTSEL_20_OUT_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_20_OUT_20_MASK, .index = PINMUX_MIO_OUTSEL_20_OUT_20_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_21_REG_OFFSET 0x3cc
+#define PINMUX_MIO_OUTSEL_21_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_21_OUT_21_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_21_OUT_21_OFFSET 0
+#define PINMUX_MIO_OUTSEL_21_OUT_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_21_OUT_21_MASK, .index = PINMUX_MIO_OUTSEL_21_OUT_21_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_22_REG_OFFSET 0x3d0
+#define PINMUX_MIO_OUTSEL_22_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_22_OUT_22_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_22_OUT_22_OFFSET 0
+#define PINMUX_MIO_OUTSEL_22_OUT_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_22_OUT_22_MASK, .index = PINMUX_MIO_OUTSEL_22_OUT_22_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_23_REG_OFFSET 0x3d4
+#define PINMUX_MIO_OUTSEL_23_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_23_OUT_23_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_23_OUT_23_OFFSET 0
+#define PINMUX_MIO_OUTSEL_23_OUT_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_23_OUT_23_MASK, .index = PINMUX_MIO_OUTSEL_23_OUT_23_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_24_REG_OFFSET 0x3d8
+#define PINMUX_MIO_OUTSEL_24_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_24_OUT_24_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_24_OUT_24_OFFSET 0
+#define PINMUX_MIO_OUTSEL_24_OUT_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_24_OUT_24_MASK, .index = PINMUX_MIO_OUTSEL_24_OUT_24_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_25_REG_OFFSET 0x3dc
+#define PINMUX_MIO_OUTSEL_25_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_25_OUT_25_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_25_OUT_25_OFFSET 0
+#define PINMUX_MIO_OUTSEL_25_OUT_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_25_OUT_25_MASK, .index = PINMUX_MIO_OUTSEL_25_OUT_25_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_26_REG_OFFSET 0x3e0
+#define PINMUX_MIO_OUTSEL_26_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_26_OUT_26_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_26_OUT_26_OFFSET 0
+#define PINMUX_MIO_OUTSEL_26_OUT_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_26_OUT_26_MASK, .index = PINMUX_MIO_OUTSEL_26_OUT_26_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_27_REG_OFFSET 0x3e4
+#define PINMUX_MIO_OUTSEL_27_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_27_OUT_27_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_27_OUT_27_OFFSET 0
+#define PINMUX_MIO_OUTSEL_27_OUT_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_27_OUT_27_MASK, .index = PINMUX_MIO_OUTSEL_27_OUT_27_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_28_REG_OFFSET 0x3e8
+#define PINMUX_MIO_OUTSEL_28_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_28_OUT_28_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_28_OUT_28_OFFSET 0
+#define PINMUX_MIO_OUTSEL_28_OUT_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_28_OUT_28_MASK, .index = PINMUX_MIO_OUTSEL_28_OUT_28_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_29_REG_OFFSET 0x3ec
+#define PINMUX_MIO_OUTSEL_29_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_29_OUT_29_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_29_OUT_29_OFFSET 0
+#define PINMUX_MIO_OUTSEL_29_OUT_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_29_OUT_29_MASK, .index = PINMUX_MIO_OUTSEL_29_OUT_29_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_30_REG_OFFSET 0x3f0
+#define PINMUX_MIO_OUTSEL_30_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_30_OUT_30_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_30_OUT_30_OFFSET 0
+#define PINMUX_MIO_OUTSEL_30_OUT_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_30_OUT_30_MASK, .index = PINMUX_MIO_OUTSEL_30_OUT_30_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_31_REG_OFFSET 0x3f4
+#define PINMUX_MIO_OUTSEL_31_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_31_OUT_31_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_31_OUT_31_OFFSET 0
+#define PINMUX_MIO_OUTSEL_31_OUT_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_31_OUT_31_MASK, .index = PINMUX_MIO_OUTSEL_31_OUT_31_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_32_REG_OFFSET 0x3f8
+#define PINMUX_MIO_OUTSEL_32_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_32_OUT_32_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_32_OUT_32_OFFSET 0
+#define PINMUX_MIO_OUTSEL_32_OUT_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_32_OUT_32_MASK, .index = PINMUX_MIO_OUTSEL_32_OUT_32_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_33_REG_OFFSET 0x3fc
+#define PINMUX_MIO_OUTSEL_33_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_33_OUT_33_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_33_OUT_33_OFFSET 0
+#define PINMUX_MIO_OUTSEL_33_OUT_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_33_OUT_33_MASK, .index = PINMUX_MIO_OUTSEL_33_OUT_33_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_34_REG_OFFSET 0x400
+#define PINMUX_MIO_OUTSEL_34_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_34_OUT_34_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_34_OUT_34_OFFSET 0
+#define PINMUX_MIO_OUTSEL_34_OUT_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_34_OUT_34_MASK, .index = PINMUX_MIO_OUTSEL_34_OUT_34_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_35_REG_OFFSET 0x404
+#define PINMUX_MIO_OUTSEL_35_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_35_OUT_35_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_35_OUT_35_OFFSET 0
+#define PINMUX_MIO_OUTSEL_35_OUT_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_35_OUT_35_MASK, .index = PINMUX_MIO_OUTSEL_35_OUT_35_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_36_REG_OFFSET 0x408
+#define PINMUX_MIO_OUTSEL_36_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_36_OUT_36_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_36_OUT_36_OFFSET 0
+#define PINMUX_MIO_OUTSEL_36_OUT_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_36_OUT_36_MASK, .index = PINMUX_MIO_OUTSEL_36_OUT_36_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_37_REG_OFFSET 0x40c
+#define PINMUX_MIO_OUTSEL_37_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_37_OUT_37_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_37_OUT_37_OFFSET 0
+#define PINMUX_MIO_OUTSEL_37_OUT_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_37_OUT_37_MASK, .index = PINMUX_MIO_OUTSEL_37_OUT_37_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_38_REG_OFFSET 0x410
+#define PINMUX_MIO_OUTSEL_38_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_38_OUT_38_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_38_OUT_38_OFFSET 0
+#define PINMUX_MIO_OUTSEL_38_OUT_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_38_OUT_38_MASK, .index = PINMUX_MIO_OUTSEL_38_OUT_38_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_39_REG_OFFSET 0x414
+#define PINMUX_MIO_OUTSEL_39_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_39_OUT_39_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_39_OUT_39_OFFSET 0
+#define PINMUX_MIO_OUTSEL_39_OUT_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_39_OUT_39_MASK, .index = PINMUX_MIO_OUTSEL_39_OUT_39_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_40_REG_OFFSET 0x418
+#define PINMUX_MIO_OUTSEL_40_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_40_OUT_40_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_40_OUT_40_OFFSET 0
+#define PINMUX_MIO_OUTSEL_40_OUT_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_40_OUT_40_MASK, .index = PINMUX_MIO_OUTSEL_40_OUT_40_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_41_REG_OFFSET 0x41c
+#define PINMUX_MIO_OUTSEL_41_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_41_OUT_41_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_41_OUT_41_OFFSET 0
+#define PINMUX_MIO_OUTSEL_41_OUT_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_41_OUT_41_MASK, .index = PINMUX_MIO_OUTSEL_41_OUT_41_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_42_REG_OFFSET 0x420
+#define PINMUX_MIO_OUTSEL_42_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_42_OUT_42_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_42_OUT_42_OFFSET 0
+#define PINMUX_MIO_OUTSEL_42_OUT_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_42_OUT_42_MASK, .index = PINMUX_MIO_OUTSEL_42_OUT_42_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_43_REG_OFFSET 0x424
+#define PINMUX_MIO_OUTSEL_43_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_43_OUT_43_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_43_OUT_43_OFFSET 0
+#define PINMUX_MIO_OUTSEL_43_OUT_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_43_OUT_43_MASK, .index = PINMUX_MIO_OUTSEL_43_OUT_43_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_44_REG_OFFSET 0x428
+#define PINMUX_MIO_OUTSEL_44_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_44_OUT_44_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_44_OUT_44_OFFSET 0
+#define PINMUX_MIO_OUTSEL_44_OUT_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_44_OUT_44_MASK, .index = PINMUX_MIO_OUTSEL_44_OUT_44_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_45_REG_OFFSET 0x42c
+#define PINMUX_MIO_OUTSEL_45_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_45_OUT_45_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_45_OUT_45_OFFSET 0
+#define PINMUX_MIO_OUTSEL_45_OUT_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_45_OUT_45_MASK, .index = PINMUX_MIO_OUTSEL_45_OUT_45_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_46_REG_OFFSET 0x430
+#define PINMUX_MIO_OUTSEL_46_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_46_OUT_46_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_46_OUT_46_OFFSET 0
+#define PINMUX_MIO_OUTSEL_46_OUT_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_46_OUT_46_MASK, .index = PINMUX_MIO_OUTSEL_46_OUT_46_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_47_REG_OFFSET 0x434
+#define PINMUX_MIO_OUTSEL_47_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_47_OUT_47_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_47_OUT_47_OFFSET 0
+#define PINMUX_MIO_OUTSEL_47_OUT_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_47_OUT_47_MASK, .index = PINMUX_MIO_OUTSEL_47_OUT_47_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_48_REG_OFFSET 0x438
+#define PINMUX_MIO_OUTSEL_48_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_48_OUT_48_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_48_OUT_48_OFFSET 0
+#define PINMUX_MIO_OUTSEL_48_OUT_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_48_OUT_48_MASK, .index = PINMUX_MIO_OUTSEL_48_OUT_48_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_49_REG_OFFSET 0x43c
+#define PINMUX_MIO_OUTSEL_49_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_49_OUT_49_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_49_OUT_49_OFFSET 0
+#define PINMUX_MIO_OUTSEL_49_OUT_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_49_OUT_49_MASK, .index = PINMUX_MIO_OUTSEL_49_OUT_49_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_50_REG_OFFSET 0x440
+#define PINMUX_MIO_OUTSEL_50_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_50_OUT_50_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_50_OUT_50_OFFSET 0
+#define PINMUX_MIO_OUTSEL_50_OUT_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_50_OUT_50_MASK, .index = PINMUX_MIO_OUTSEL_50_OUT_50_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_51_REG_OFFSET 0x444
+#define PINMUX_MIO_OUTSEL_51_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_51_OUT_51_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_51_OUT_51_OFFSET 0
+#define PINMUX_MIO_OUTSEL_51_OUT_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_51_OUT_51_MASK, .index = PINMUX_MIO_OUTSEL_51_OUT_51_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_52_REG_OFFSET 0x448
+#define PINMUX_MIO_OUTSEL_52_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_52_OUT_52_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_52_OUT_52_OFFSET 0
+#define PINMUX_MIO_OUTSEL_52_OUT_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_52_OUT_52_MASK, .index = PINMUX_MIO_OUTSEL_52_OUT_52_OFFSET })
+
+// Register write enable for MIO PAD attributes. (common parameters)
+#define PINMUX_MIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 53
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0x44c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0x450
+#define PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0x454
+#define PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0x458
+#define PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0x45c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0x460
+#define PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0x464
+#define PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0x468
+#define PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0x46c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0x470
+#define PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0x474
+#define PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0x478
+#define PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_12_REG_OFFSET 0x47c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_13_REG_OFFSET 0x480
+#define PINMUX_MIO_PAD_ATTR_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_14_REG_OFFSET 0x484
+#define PINMUX_MIO_PAD_ATTR_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_15_REG_OFFSET 0x488
+#define PINMUX_MIO_PAD_ATTR_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_16_REG_OFFSET 0x48c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_16_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_17_REG_OFFSET 0x490
+#define PINMUX_MIO_PAD_ATTR_REGWEN_17_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_18_REG_OFFSET 0x494
+#define PINMUX_MIO_PAD_ATTR_REGWEN_18_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_19_REG_OFFSET 0x498
+#define PINMUX_MIO_PAD_ATTR_REGWEN_19_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_20_REG_OFFSET 0x49c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_20_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_21_REG_OFFSET 0x4a0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_21_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_22_REG_OFFSET 0x4a4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_22_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_23_REG_OFFSET 0x4a8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_23_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_24_REG_OFFSET 0x4ac
+#define PINMUX_MIO_PAD_ATTR_REGWEN_24_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_25_REG_OFFSET 0x4b0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_25_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_26_REG_OFFSET 0x4b4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_26_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_27_REG_OFFSET 0x4b8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_27_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_28_REG_OFFSET 0x4bc
+#define PINMUX_MIO_PAD_ATTR_REGWEN_28_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_29_REG_OFFSET 0x4c0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_29_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_30_REG_OFFSET 0x4c4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_30_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_31_REG_OFFSET 0x4c8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_31_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_32_REG_OFFSET 0x4cc
+#define PINMUX_MIO_PAD_ATTR_REGWEN_32_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_33_REG_OFFSET 0x4d0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_33_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_34_REG_OFFSET 0x4d4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_34_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_35_REG_OFFSET 0x4d8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_35_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_36_REG_OFFSET 0x4dc
+#define PINMUX_MIO_PAD_ATTR_REGWEN_36_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_37_REG_OFFSET 0x4e0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_37_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_38_REG_OFFSET 0x4e4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_38_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_39_REG_OFFSET 0x4e8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_39_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_40_REG_OFFSET 0x4ec
+#define PINMUX_MIO_PAD_ATTR_REGWEN_40_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_41_REG_OFFSET 0x4f0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_41_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_42_REG_OFFSET 0x4f4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_42_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_43_REG_OFFSET 0x4f8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_43_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_44_REG_OFFSET 0x4fc
+#define PINMUX_MIO_PAD_ATTR_REGWEN_44_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_45_REG_OFFSET 0x500
+#define PINMUX_MIO_PAD_ATTR_REGWEN_45_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_46_REG_OFFSET 0x504
+#define PINMUX_MIO_PAD_ATTR_REGWEN_46_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_47_REG_OFFSET 0x508
+#define PINMUX_MIO_PAD_ATTR_REGWEN_47_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_48_REG_OFFSET 0x50c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_48_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_49_REG_OFFSET 0x510
+#define PINMUX_MIO_PAD_ATTR_REGWEN_49_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_50_REG_OFFSET 0x514
+#define PINMUX_MIO_PAD_ATTR_REGWEN_50_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_51_REG_OFFSET 0x518
+#define PINMUX_MIO_PAD_ATTR_REGWEN_51_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_52_REG_OFFSET 0x51c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_52_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_52_EN_52_BIT 0
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_INVERT_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2
+#define PINMUX_MIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4
+#define PINMUX_MIO_PAD_ATTR_MULTIREG_COUNT 53
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_0_REG_OFFSET 0x520
+#define PINMUX_MIO_PAD_ATTR_0_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_0_INVERT_0_BIT 0
+#define PINMUX_MIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1
+#define PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_BIT 2
+#define PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3
+#define PINMUX_MIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4
+#define PINMUX_MIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5
+#define PINMUX_MIO_PAD_ATTR_0_OD_EN_0_BIT 6
+#define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_1_REG_OFFSET 0x524
+#define PINMUX_MIO_PAD_ATTR_1_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_1_INVERT_1_BIT 0
+#define PINMUX_MIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1
+#define PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_BIT 2
+#define PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3
+#define PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4
+#define PINMUX_MIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5
+#define PINMUX_MIO_PAD_ATTR_1_OD_EN_1_BIT 6
+#define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_2_REG_OFFSET 0x528
+#define PINMUX_MIO_PAD_ATTR_2_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_2_INVERT_2_BIT 0
+#define PINMUX_MIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1
+#define PINMUX_MIO_PAD_ATTR_2_PULL_EN_2_BIT 2
+#define PINMUX_MIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3
+#define PINMUX_MIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4
+#define PINMUX_MIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5
+#define PINMUX_MIO_PAD_ATTR_2_OD_EN_2_BIT 6
+#define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_3_REG_OFFSET 0x52c
+#define PINMUX_MIO_PAD_ATTR_3_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_3_INVERT_3_BIT 0
+#define PINMUX_MIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1
+#define PINMUX_MIO_PAD_ATTR_3_PULL_EN_3_BIT 2
+#define PINMUX_MIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3
+#define PINMUX_MIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4
+#define PINMUX_MIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5
+#define PINMUX_MIO_PAD_ATTR_3_OD_EN_3_BIT 6
+#define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_4_REG_OFFSET 0x530
+#define PINMUX_MIO_PAD_ATTR_4_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_4_INVERT_4_BIT 0
+#define PINMUX_MIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1
+#define PINMUX_MIO_PAD_ATTR_4_PULL_EN_4_BIT 2
+#define PINMUX_MIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3
+#define PINMUX_MIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4
+#define PINMUX_MIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5
+#define PINMUX_MIO_PAD_ATTR_4_OD_EN_4_BIT 6
+#define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_5_REG_OFFSET 0x534
+#define PINMUX_MIO_PAD_ATTR_5_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_5_INVERT_5_BIT 0
+#define PINMUX_MIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1
+#define PINMUX_MIO_PAD_ATTR_5_PULL_EN_5_BIT 2
+#define PINMUX_MIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3
+#define PINMUX_MIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4
+#define PINMUX_MIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5
+#define PINMUX_MIO_PAD_ATTR_5_OD_EN_5_BIT 6
+#define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_6_REG_OFFSET 0x538
+#define PINMUX_MIO_PAD_ATTR_6_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_6_INVERT_6_BIT 0
+#define PINMUX_MIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1
+#define PINMUX_MIO_PAD_ATTR_6_PULL_EN_6_BIT 2
+#define PINMUX_MIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3
+#define PINMUX_MIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4
+#define PINMUX_MIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5
+#define PINMUX_MIO_PAD_ATTR_6_OD_EN_6_BIT 6
+#define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_7_REG_OFFSET 0x53c
+#define PINMUX_MIO_PAD_ATTR_7_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_7_INVERT_7_BIT 0
+#define PINMUX_MIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1
+#define PINMUX_MIO_PAD_ATTR_7_PULL_EN_7_BIT 2
+#define PINMUX_MIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3
+#define PINMUX_MIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4
+#define PINMUX_MIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5
+#define PINMUX_MIO_PAD_ATTR_7_OD_EN_7_BIT 6
+#define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_8_REG_OFFSET 0x540
+#define PINMUX_MIO_PAD_ATTR_8_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_8_INVERT_8_BIT 0
+#define PINMUX_MIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1
+#define PINMUX_MIO_PAD_ATTR_8_PULL_EN_8_BIT 2
+#define PINMUX_MIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3
+#define PINMUX_MIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4
+#define PINMUX_MIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5
+#define PINMUX_MIO_PAD_ATTR_8_OD_EN_8_BIT 6
+#define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_9_REG_OFFSET 0x544
+#define PINMUX_MIO_PAD_ATTR_9_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_9_INVERT_9_BIT 0
+#define PINMUX_MIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1
+#define PINMUX_MIO_PAD_ATTR_9_PULL_EN_9_BIT 2
+#define PINMUX_MIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3
+#define PINMUX_MIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4
+#define PINMUX_MIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5
+#define PINMUX_MIO_PAD_ATTR_9_OD_EN_9_BIT 6
+#define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_10_REG_OFFSET 0x548
+#define PINMUX_MIO_PAD_ATTR_10_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_10_INVERT_10_BIT 0
+#define PINMUX_MIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1
+#define PINMUX_MIO_PAD_ATTR_10_PULL_EN_10_BIT 2
+#define PINMUX_MIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3
+#define PINMUX_MIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4
+#define PINMUX_MIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5
+#define PINMUX_MIO_PAD_ATTR_10_OD_EN_10_BIT 6
+#define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_11_REG_OFFSET 0x54c
+#define PINMUX_MIO_PAD_ATTR_11_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_11_INVERT_11_BIT 0
+#define PINMUX_MIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1
+#define PINMUX_MIO_PAD_ATTR_11_PULL_EN_11_BIT 2
+#define PINMUX_MIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3
+#define PINMUX_MIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4
+#define PINMUX_MIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5
+#define PINMUX_MIO_PAD_ATTR_11_OD_EN_11_BIT 6
+#define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_12_REG_OFFSET 0x550
+#define PINMUX_MIO_PAD_ATTR_12_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_12_INVERT_12_BIT 0
+#define PINMUX_MIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_BIT 1
+#define PINMUX_MIO_PAD_ATTR_12_PULL_EN_12_BIT 2
+#define PINMUX_MIO_PAD_ATTR_12_PULL_SELECT_12_BIT 3
+#define PINMUX_MIO_PAD_ATTR_12_KEEPER_EN_12_BIT 4
+#define PINMUX_MIO_PAD_ATTR_12_SCHMITT_EN_12_BIT 5
+#define PINMUX_MIO_PAD_ATTR_12_OD_EN_12_BIT 6
+#define PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_MASK, .index = PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK, .index = PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_13_REG_OFFSET 0x554
+#define PINMUX_MIO_PAD_ATTR_13_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_13_INVERT_13_BIT 0
+#define PINMUX_MIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_BIT 1
+#define PINMUX_MIO_PAD_ATTR_13_PULL_EN_13_BIT 2
+#define PINMUX_MIO_PAD_ATTR_13_PULL_SELECT_13_BIT 3
+#define PINMUX_MIO_PAD_ATTR_13_KEEPER_EN_13_BIT 4
+#define PINMUX_MIO_PAD_ATTR_13_SCHMITT_EN_13_BIT 5
+#define PINMUX_MIO_PAD_ATTR_13_OD_EN_13_BIT 6
+#define PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_MASK, .index = PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK, .index = PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_14_REG_OFFSET 0x558
+#define PINMUX_MIO_PAD_ATTR_14_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_14_INVERT_14_BIT 0
+#define PINMUX_MIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_BIT 1
+#define PINMUX_MIO_PAD_ATTR_14_PULL_EN_14_BIT 2
+#define PINMUX_MIO_PAD_ATTR_14_PULL_SELECT_14_BIT 3
+#define PINMUX_MIO_PAD_ATTR_14_KEEPER_EN_14_BIT 4
+#define PINMUX_MIO_PAD_ATTR_14_SCHMITT_EN_14_BIT 5
+#define PINMUX_MIO_PAD_ATTR_14_OD_EN_14_BIT 6
+#define PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_MASK, .index = PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK, .index = PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_15_REG_OFFSET 0x55c
+#define PINMUX_MIO_PAD_ATTR_15_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_15_INVERT_15_BIT 0
+#define PINMUX_MIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_BIT 1
+#define PINMUX_MIO_PAD_ATTR_15_PULL_EN_15_BIT 2
+#define PINMUX_MIO_PAD_ATTR_15_PULL_SELECT_15_BIT 3
+#define PINMUX_MIO_PAD_ATTR_15_KEEPER_EN_15_BIT 4
+#define PINMUX_MIO_PAD_ATTR_15_SCHMITT_EN_15_BIT 5
+#define PINMUX_MIO_PAD_ATTR_15_OD_EN_15_BIT 6
+#define PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_MASK, .index = PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK, .index = PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_16_REG_OFFSET 0x560
+#define PINMUX_MIO_PAD_ATTR_16_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_16_INVERT_16_BIT 0
+#define PINMUX_MIO_PAD_ATTR_16_VIRTUAL_OD_EN_16_BIT 1
+#define PINMUX_MIO_PAD_ATTR_16_PULL_EN_16_BIT 2
+#define PINMUX_MIO_PAD_ATTR_16_PULL_SELECT_16_BIT 3
+#define PINMUX_MIO_PAD_ATTR_16_KEEPER_EN_16_BIT 4
+#define PINMUX_MIO_PAD_ATTR_16_SCHMITT_EN_16_BIT 5
+#define PINMUX_MIO_PAD_ATTR_16_OD_EN_16_BIT 6
+#define PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_MASK, .index = PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK, .index = PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_17_REG_OFFSET 0x564
+#define PINMUX_MIO_PAD_ATTR_17_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_17_INVERT_17_BIT 0
+#define PINMUX_MIO_PAD_ATTR_17_VIRTUAL_OD_EN_17_BIT 1
+#define PINMUX_MIO_PAD_ATTR_17_PULL_EN_17_BIT 2
+#define PINMUX_MIO_PAD_ATTR_17_PULL_SELECT_17_BIT 3
+#define PINMUX_MIO_PAD_ATTR_17_KEEPER_EN_17_BIT 4
+#define PINMUX_MIO_PAD_ATTR_17_SCHMITT_EN_17_BIT 5
+#define PINMUX_MIO_PAD_ATTR_17_OD_EN_17_BIT 6
+#define PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_MASK, .index = PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK, .index = PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_18_REG_OFFSET 0x568
+#define PINMUX_MIO_PAD_ATTR_18_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_18_INVERT_18_BIT 0
+#define PINMUX_MIO_PAD_ATTR_18_VIRTUAL_OD_EN_18_BIT 1
+#define PINMUX_MIO_PAD_ATTR_18_PULL_EN_18_BIT 2
+#define PINMUX_MIO_PAD_ATTR_18_PULL_SELECT_18_BIT 3
+#define PINMUX_MIO_PAD_ATTR_18_KEEPER_EN_18_BIT 4
+#define PINMUX_MIO_PAD_ATTR_18_SCHMITT_EN_18_BIT 5
+#define PINMUX_MIO_PAD_ATTR_18_OD_EN_18_BIT 6
+#define PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_MASK, .index = PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK, .index = PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_19_REG_OFFSET 0x56c
+#define PINMUX_MIO_PAD_ATTR_19_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_19_INVERT_19_BIT 0
+#define PINMUX_MIO_PAD_ATTR_19_VIRTUAL_OD_EN_19_BIT 1
+#define PINMUX_MIO_PAD_ATTR_19_PULL_EN_19_BIT 2
+#define PINMUX_MIO_PAD_ATTR_19_PULL_SELECT_19_BIT 3
+#define PINMUX_MIO_PAD_ATTR_19_KEEPER_EN_19_BIT 4
+#define PINMUX_MIO_PAD_ATTR_19_SCHMITT_EN_19_BIT 5
+#define PINMUX_MIO_PAD_ATTR_19_OD_EN_19_BIT 6
+#define PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_MASK, .index = PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK, .index = PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_20_REG_OFFSET 0x570
+#define PINMUX_MIO_PAD_ATTR_20_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_20_INVERT_20_BIT 0
+#define PINMUX_MIO_PAD_ATTR_20_VIRTUAL_OD_EN_20_BIT 1
+#define PINMUX_MIO_PAD_ATTR_20_PULL_EN_20_BIT 2
+#define PINMUX_MIO_PAD_ATTR_20_PULL_SELECT_20_BIT 3
+#define PINMUX_MIO_PAD_ATTR_20_KEEPER_EN_20_BIT 4
+#define PINMUX_MIO_PAD_ATTR_20_SCHMITT_EN_20_BIT 5
+#define PINMUX_MIO_PAD_ATTR_20_OD_EN_20_BIT 6
+#define PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_MASK, .index = PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK, .index = PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_21_REG_OFFSET 0x574
+#define PINMUX_MIO_PAD_ATTR_21_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_21_INVERT_21_BIT 0
+#define PINMUX_MIO_PAD_ATTR_21_VIRTUAL_OD_EN_21_BIT 1
+#define PINMUX_MIO_PAD_ATTR_21_PULL_EN_21_BIT 2
+#define PINMUX_MIO_PAD_ATTR_21_PULL_SELECT_21_BIT 3
+#define PINMUX_MIO_PAD_ATTR_21_KEEPER_EN_21_BIT 4
+#define PINMUX_MIO_PAD_ATTR_21_SCHMITT_EN_21_BIT 5
+#define PINMUX_MIO_PAD_ATTR_21_OD_EN_21_BIT 6
+#define PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_MASK, .index = PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK, .index = PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_22_REG_OFFSET 0x578
+#define PINMUX_MIO_PAD_ATTR_22_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_22_INVERT_22_BIT 0
+#define PINMUX_MIO_PAD_ATTR_22_VIRTUAL_OD_EN_22_BIT 1
+#define PINMUX_MIO_PAD_ATTR_22_PULL_EN_22_BIT 2
+#define PINMUX_MIO_PAD_ATTR_22_PULL_SELECT_22_BIT 3
+#define PINMUX_MIO_PAD_ATTR_22_KEEPER_EN_22_BIT 4
+#define PINMUX_MIO_PAD_ATTR_22_SCHMITT_EN_22_BIT 5
+#define PINMUX_MIO_PAD_ATTR_22_OD_EN_22_BIT 6
+#define PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_MASK, .index = PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK, .index = PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_23_REG_OFFSET 0x57c
+#define PINMUX_MIO_PAD_ATTR_23_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_23_INVERT_23_BIT 0
+#define PINMUX_MIO_PAD_ATTR_23_VIRTUAL_OD_EN_23_BIT 1
+#define PINMUX_MIO_PAD_ATTR_23_PULL_EN_23_BIT 2
+#define PINMUX_MIO_PAD_ATTR_23_PULL_SELECT_23_BIT 3
+#define PINMUX_MIO_PAD_ATTR_23_KEEPER_EN_23_BIT 4
+#define PINMUX_MIO_PAD_ATTR_23_SCHMITT_EN_23_BIT 5
+#define PINMUX_MIO_PAD_ATTR_23_OD_EN_23_BIT 6
+#define PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_MASK, .index = PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK, .index = PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_24_REG_OFFSET 0x580
+#define PINMUX_MIO_PAD_ATTR_24_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_24_INVERT_24_BIT 0
+#define PINMUX_MIO_PAD_ATTR_24_VIRTUAL_OD_EN_24_BIT 1
+#define PINMUX_MIO_PAD_ATTR_24_PULL_EN_24_BIT 2
+#define PINMUX_MIO_PAD_ATTR_24_PULL_SELECT_24_BIT 3
+#define PINMUX_MIO_PAD_ATTR_24_KEEPER_EN_24_BIT 4
+#define PINMUX_MIO_PAD_ATTR_24_SCHMITT_EN_24_BIT 5
+#define PINMUX_MIO_PAD_ATTR_24_OD_EN_24_BIT 6
+#define PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_MASK, .index = PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK, .index = PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_25_REG_OFFSET 0x584
+#define PINMUX_MIO_PAD_ATTR_25_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_25_INVERT_25_BIT 0
+#define PINMUX_MIO_PAD_ATTR_25_VIRTUAL_OD_EN_25_BIT 1
+#define PINMUX_MIO_PAD_ATTR_25_PULL_EN_25_BIT 2
+#define PINMUX_MIO_PAD_ATTR_25_PULL_SELECT_25_BIT 3
+#define PINMUX_MIO_PAD_ATTR_25_KEEPER_EN_25_BIT 4
+#define PINMUX_MIO_PAD_ATTR_25_SCHMITT_EN_25_BIT 5
+#define PINMUX_MIO_PAD_ATTR_25_OD_EN_25_BIT 6
+#define PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_MASK, .index = PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK, .index = PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_26_REG_OFFSET 0x588
+#define PINMUX_MIO_PAD_ATTR_26_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_26_INVERT_26_BIT 0
+#define PINMUX_MIO_PAD_ATTR_26_VIRTUAL_OD_EN_26_BIT 1
+#define PINMUX_MIO_PAD_ATTR_26_PULL_EN_26_BIT 2
+#define PINMUX_MIO_PAD_ATTR_26_PULL_SELECT_26_BIT 3
+#define PINMUX_MIO_PAD_ATTR_26_KEEPER_EN_26_BIT 4
+#define PINMUX_MIO_PAD_ATTR_26_SCHMITT_EN_26_BIT 5
+#define PINMUX_MIO_PAD_ATTR_26_OD_EN_26_BIT 6
+#define PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_MASK, .index = PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK, .index = PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_27_REG_OFFSET 0x58c
+#define PINMUX_MIO_PAD_ATTR_27_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_27_INVERT_27_BIT 0
+#define PINMUX_MIO_PAD_ATTR_27_VIRTUAL_OD_EN_27_BIT 1
+#define PINMUX_MIO_PAD_ATTR_27_PULL_EN_27_BIT 2
+#define PINMUX_MIO_PAD_ATTR_27_PULL_SELECT_27_BIT 3
+#define PINMUX_MIO_PAD_ATTR_27_KEEPER_EN_27_BIT 4
+#define PINMUX_MIO_PAD_ATTR_27_SCHMITT_EN_27_BIT 5
+#define PINMUX_MIO_PAD_ATTR_27_OD_EN_27_BIT 6
+#define PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_MASK, .index = PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK, .index = PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_28_REG_OFFSET 0x590
+#define PINMUX_MIO_PAD_ATTR_28_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_28_INVERT_28_BIT 0
+#define PINMUX_MIO_PAD_ATTR_28_VIRTUAL_OD_EN_28_BIT 1
+#define PINMUX_MIO_PAD_ATTR_28_PULL_EN_28_BIT 2
+#define PINMUX_MIO_PAD_ATTR_28_PULL_SELECT_28_BIT 3
+#define PINMUX_MIO_PAD_ATTR_28_KEEPER_EN_28_BIT 4
+#define PINMUX_MIO_PAD_ATTR_28_SCHMITT_EN_28_BIT 5
+#define PINMUX_MIO_PAD_ATTR_28_OD_EN_28_BIT 6
+#define PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_MASK, .index = PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK, .index = PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_29_REG_OFFSET 0x594
+#define PINMUX_MIO_PAD_ATTR_29_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_29_INVERT_29_BIT 0
+#define PINMUX_MIO_PAD_ATTR_29_VIRTUAL_OD_EN_29_BIT 1
+#define PINMUX_MIO_PAD_ATTR_29_PULL_EN_29_BIT 2
+#define PINMUX_MIO_PAD_ATTR_29_PULL_SELECT_29_BIT 3
+#define PINMUX_MIO_PAD_ATTR_29_KEEPER_EN_29_BIT 4
+#define PINMUX_MIO_PAD_ATTR_29_SCHMITT_EN_29_BIT 5
+#define PINMUX_MIO_PAD_ATTR_29_OD_EN_29_BIT 6
+#define PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_MASK, .index = PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK, .index = PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_30_REG_OFFSET 0x598
+#define PINMUX_MIO_PAD_ATTR_30_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_30_INVERT_30_BIT 0
+#define PINMUX_MIO_PAD_ATTR_30_VIRTUAL_OD_EN_30_BIT 1
+#define PINMUX_MIO_PAD_ATTR_30_PULL_EN_30_BIT 2
+#define PINMUX_MIO_PAD_ATTR_30_PULL_SELECT_30_BIT 3
+#define PINMUX_MIO_PAD_ATTR_30_KEEPER_EN_30_BIT 4
+#define PINMUX_MIO_PAD_ATTR_30_SCHMITT_EN_30_BIT 5
+#define PINMUX_MIO_PAD_ATTR_30_OD_EN_30_BIT 6
+#define PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_MASK, .index = PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK, .index = PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_31_REG_OFFSET 0x59c
+#define PINMUX_MIO_PAD_ATTR_31_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_31_INVERT_31_BIT 0
+#define PINMUX_MIO_PAD_ATTR_31_VIRTUAL_OD_EN_31_BIT 1
+#define PINMUX_MIO_PAD_ATTR_31_PULL_EN_31_BIT 2
+#define PINMUX_MIO_PAD_ATTR_31_PULL_SELECT_31_BIT 3
+#define PINMUX_MIO_PAD_ATTR_31_KEEPER_EN_31_BIT 4
+#define PINMUX_MIO_PAD_ATTR_31_SCHMITT_EN_31_BIT 5
+#define PINMUX_MIO_PAD_ATTR_31_OD_EN_31_BIT 6
+#define PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_MASK, .index = PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK, .index = PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_32_REG_OFFSET 0x5a0
+#define PINMUX_MIO_PAD_ATTR_32_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_32_INVERT_32_BIT 0
+#define PINMUX_MIO_PAD_ATTR_32_VIRTUAL_OD_EN_32_BIT 1
+#define PINMUX_MIO_PAD_ATTR_32_PULL_EN_32_BIT 2
+#define PINMUX_MIO_PAD_ATTR_32_PULL_SELECT_32_BIT 3
+#define PINMUX_MIO_PAD_ATTR_32_KEEPER_EN_32_BIT 4
+#define PINMUX_MIO_PAD_ATTR_32_SCHMITT_EN_32_BIT 5
+#define PINMUX_MIO_PAD_ATTR_32_OD_EN_32_BIT 6
+#define PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_MASK, .index = PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK, .index = PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_33_REG_OFFSET 0x5a4
+#define PINMUX_MIO_PAD_ATTR_33_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_33_INVERT_33_BIT 0
+#define PINMUX_MIO_PAD_ATTR_33_VIRTUAL_OD_EN_33_BIT 1
+#define PINMUX_MIO_PAD_ATTR_33_PULL_EN_33_BIT 2
+#define PINMUX_MIO_PAD_ATTR_33_PULL_SELECT_33_BIT 3
+#define PINMUX_MIO_PAD_ATTR_33_KEEPER_EN_33_BIT 4
+#define PINMUX_MIO_PAD_ATTR_33_SCHMITT_EN_33_BIT 5
+#define PINMUX_MIO_PAD_ATTR_33_OD_EN_33_BIT 6
+#define PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_MASK, .index = PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK, .index = PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_34_REG_OFFSET 0x5a8
+#define PINMUX_MIO_PAD_ATTR_34_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_34_INVERT_34_BIT 0
+#define PINMUX_MIO_PAD_ATTR_34_VIRTUAL_OD_EN_34_BIT 1
+#define PINMUX_MIO_PAD_ATTR_34_PULL_EN_34_BIT 2
+#define PINMUX_MIO_PAD_ATTR_34_PULL_SELECT_34_BIT 3
+#define PINMUX_MIO_PAD_ATTR_34_KEEPER_EN_34_BIT 4
+#define PINMUX_MIO_PAD_ATTR_34_SCHMITT_EN_34_BIT 5
+#define PINMUX_MIO_PAD_ATTR_34_OD_EN_34_BIT 6
+#define PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_MASK, .index = PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK, .index = PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_35_REG_OFFSET 0x5ac
+#define PINMUX_MIO_PAD_ATTR_35_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_35_INVERT_35_BIT 0
+#define PINMUX_MIO_PAD_ATTR_35_VIRTUAL_OD_EN_35_BIT 1
+#define PINMUX_MIO_PAD_ATTR_35_PULL_EN_35_BIT 2
+#define PINMUX_MIO_PAD_ATTR_35_PULL_SELECT_35_BIT 3
+#define PINMUX_MIO_PAD_ATTR_35_KEEPER_EN_35_BIT 4
+#define PINMUX_MIO_PAD_ATTR_35_SCHMITT_EN_35_BIT 5
+#define PINMUX_MIO_PAD_ATTR_35_OD_EN_35_BIT 6
+#define PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_MASK, .index = PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK, .index = PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_36_REG_OFFSET 0x5b0
+#define PINMUX_MIO_PAD_ATTR_36_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_36_INVERT_36_BIT 0
+#define PINMUX_MIO_PAD_ATTR_36_VIRTUAL_OD_EN_36_BIT 1
+#define PINMUX_MIO_PAD_ATTR_36_PULL_EN_36_BIT 2
+#define PINMUX_MIO_PAD_ATTR_36_PULL_SELECT_36_BIT 3
+#define PINMUX_MIO_PAD_ATTR_36_KEEPER_EN_36_BIT 4
+#define PINMUX_MIO_PAD_ATTR_36_SCHMITT_EN_36_BIT 5
+#define PINMUX_MIO_PAD_ATTR_36_OD_EN_36_BIT 6
+#define PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_MASK, .index = PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK, .index = PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_37_REG_OFFSET 0x5b4
+#define PINMUX_MIO_PAD_ATTR_37_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_37_INVERT_37_BIT 0
+#define PINMUX_MIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_BIT 1
+#define PINMUX_MIO_PAD_ATTR_37_PULL_EN_37_BIT 2
+#define PINMUX_MIO_PAD_ATTR_37_PULL_SELECT_37_BIT 3
+#define PINMUX_MIO_PAD_ATTR_37_KEEPER_EN_37_BIT 4
+#define PINMUX_MIO_PAD_ATTR_37_SCHMITT_EN_37_BIT 5
+#define PINMUX_MIO_PAD_ATTR_37_OD_EN_37_BIT 6
+#define PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_MASK, .index = PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK, .index = PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_38_REG_OFFSET 0x5b8
+#define PINMUX_MIO_PAD_ATTR_38_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_38_INVERT_38_BIT 0
+#define PINMUX_MIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_BIT 1
+#define PINMUX_MIO_PAD_ATTR_38_PULL_EN_38_BIT 2
+#define PINMUX_MIO_PAD_ATTR_38_PULL_SELECT_38_BIT 3
+#define PINMUX_MIO_PAD_ATTR_38_KEEPER_EN_38_BIT 4
+#define PINMUX_MIO_PAD_ATTR_38_SCHMITT_EN_38_BIT 5
+#define PINMUX_MIO_PAD_ATTR_38_OD_EN_38_BIT 6
+#define PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_MASK, .index = PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK, .index = PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_39_REG_OFFSET 0x5bc
+#define PINMUX_MIO_PAD_ATTR_39_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_39_INVERT_39_BIT 0
+#define PINMUX_MIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_BIT 1
+#define PINMUX_MIO_PAD_ATTR_39_PULL_EN_39_BIT 2
+#define PINMUX_MIO_PAD_ATTR_39_PULL_SELECT_39_BIT 3
+#define PINMUX_MIO_PAD_ATTR_39_KEEPER_EN_39_BIT 4
+#define PINMUX_MIO_PAD_ATTR_39_SCHMITT_EN_39_BIT 5
+#define PINMUX_MIO_PAD_ATTR_39_OD_EN_39_BIT 6
+#define PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_MASK, .index = PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK, .index = PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_40_REG_OFFSET 0x5c0
+#define PINMUX_MIO_PAD_ATTR_40_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_40_INVERT_40_BIT 0
+#define PINMUX_MIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_BIT 1
+#define PINMUX_MIO_PAD_ATTR_40_PULL_EN_40_BIT 2
+#define PINMUX_MIO_PAD_ATTR_40_PULL_SELECT_40_BIT 3
+#define PINMUX_MIO_PAD_ATTR_40_KEEPER_EN_40_BIT 4
+#define PINMUX_MIO_PAD_ATTR_40_SCHMITT_EN_40_BIT 5
+#define PINMUX_MIO_PAD_ATTR_40_OD_EN_40_BIT 6
+#define PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_MASK, .index = PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK, .index = PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_41_REG_OFFSET 0x5c4
+#define PINMUX_MIO_PAD_ATTR_41_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_41_INVERT_41_BIT 0
+#define PINMUX_MIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_BIT 1
+#define PINMUX_MIO_PAD_ATTR_41_PULL_EN_41_BIT 2
+#define PINMUX_MIO_PAD_ATTR_41_PULL_SELECT_41_BIT 3
+#define PINMUX_MIO_PAD_ATTR_41_KEEPER_EN_41_BIT 4
+#define PINMUX_MIO_PAD_ATTR_41_SCHMITT_EN_41_BIT 5
+#define PINMUX_MIO_PAD_ATTR_41_OD_EN_41_BIT 6
+#define PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_MASK, .index = PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK, .index = PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_42_REG_OFFSET 0x5c8
+#define PINMUX_MIO_PAD_ATTR_42_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_42_INVERT_42_BIT 0
+#define PINMUX_MIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_BIT 1
+#define PINMUX_MIO_PAD_ATTR_42_PULL_EN_42_BIT 2
+#define PINMUX_MIO_PAD_ATTR_42_PULL_SELECT_42_BIT 3
+#define PINMUX_MIO_PAD_ATTR_42_KEEPER_EN_42_BIT 4
+#define PINMUX_MIO_PAD_ATTR_42_SCHMITT_EN_42_BIT 5
+#define PINMUX_MIO_PAD_ATTR_42_OD_EN_42_BIT 6
+#define PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_MASK, .index = PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK, .index = PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_43_REG_OFFSET 0x5cc
+#define PINMUX_MIO_PAD_ATTR_43_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_43_INVERT_43_BIT 0
+#define PINMUX_MIO_PAD_ATTR_43_VIRTUAL_OD_EN_43_BIT 1
+#define PINMUX_MIO_PAD_ATTR_43_PULL_EN_43_BIT 2
+#define PINMUX_MIO_PAD_ATTR_43_PULL_SELECT_43_BIT 3
+#define PINMUX_MIO_PAD_ATTR_43_KEEPER_EN_43_BIT 4
+#define PINMUX_MIO_PAD_ATTR_43_SCHMITT_EN_43_BIT 5
+#define PINMUX_MIO_PAD_ATTR_43_OD_EN_43_BIT 6
+#define PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_MASK, .index = PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK, .index = PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_44_REG_OFFSET 0x5d0
+#define PINMUX_MIO_PAD_ATTR_44_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_44_INVERT_44_BIT 0
+#define PINMUX_MIO_PAD_ATTR_44_VIRTUAL_OD_EN_44_BIT 1
+#define PINMUX_MIO_PAD_ATTR_44_PULL_EN_44_BIT 2
+#define PINMUX_MIO_PAD_ATTR_44_PULL_SELECT_44_BIT 3
+#define PINMUX_MIO_PAD_ATTR_44_KEEPER_EN_44_BIT 4
+#define PINMUX_MIO_PAD_ATTR_44_SCHMITT_EN_44_BIT 5
+#define PINMUX_MIO_PAD_ATTR_44_OD_EN_44_BIT 6
+#define PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_MASK, .index = PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK, .index = PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_45_REG_OFFSET 0x5d4
+#define PINMUX_MIO_PAD_ATTR_45_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_45_INVERT_45_BIT 0
+#define PINMUX_MIO_PAD_ATTR_45_VIRTUAL_OD_EN_45_BIT 1
+#define PINMUX_MIO_PAD_ATTR_45_PULL_EN_45_BIT 2
+#define PINMUX_MIO_PAD_ATTR_45_PULL_SELECT_45_BIT 3
+#define PINMUX_MIO_PAD_ATTR_45_KEEPER_EN_45_BIT 4
+#define PINMUX_MIO_PAD_ATTR_45_SCHMITT_EN_45_BIT 5
+#define PINMUX_MIO_PAD_ATTR_45_OD_EN_45_BIT 6
+#define PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_MASK, .index = PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK, .index = PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_46_REG_OFFSET 0x5d8
+#define PINMUX_MIO_PAD_ATTR_46_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_46_INVERT_46_BIT 0
+#define PINMUX_MIO_PAD_ATTR_46_VIRTUAL_OD_EN_46_BIT 1
+#define PINMUX_MIO_PAD_ATTR_46_PULL_EN_46_BIT 2
+#define PINMUX_MIO_PAD_ATTR_46_PULL_SELECT_46_BIT 3
+#define PINMUX_MIO_PAD_ATTR_46_KEEPER_EN_46_BIT 4
+#define PINMUX_MIO_PAD_ATTR_46_SCHMITT_EN_46_BIT 5
+#define PINMUX_MIO_PAD_ATTR_46_OD_EN_46_BIT 6
+#define PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_MASK, .index = PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK, .index = PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_47_REG_OFFSET 0x5dc
+#define PINMUX_MIO_PAD_ATTR_47_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_47_INVERT_47_BIT 0
+#define PINMUX_MIO_PAD_ATTR_47_VIRTUAL_OD_EN_47_BIT 1
+#define PINMUX_MIO_PAD_ATTR_47_PULL_EN_47_BIT 2
+#define PINMUX_MIO_PAD_ATTR_47_PULL_SELECT_47_BIT 3
+#define PINMUX_MIO_PAD_ATTR_47_KEEPER_EN_47_BIT 4
+#define PINMUX_MIO_PAD_ATTR_47_SCHMITT_EN_47_BIT 5
+#define PINMUX_MIO_PAD_ATTR_47_OD_EN_47_BIT 6
+#define PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_MASK, .index = PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_MASK, .index = PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_48_REG_OFFSET 0x5e0
+#define PINMUX_MIO_PAD_ATTR_48_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_48_INVERT_48_BIT 0
+#define PINMUX_MIO_PAD_ATTR_48_VIRTUAL_OD_EN_48_BIT 1
+#define PINMUX_MIO_PAD_ATTR_48_PULL_EN_48_BIT 2
+#define PINMUX_MIO_PAD_ATTR_48_PULL_SELECT_48_BIT 3
+#define PINMUX_MIO_PAD_ATTR_48_KEEPER_EN_48_BIT 4
+#define PINMUX_MIO_PAD_ATTR_48_SCHMITT_EN_48_BIT 5
+#define PINMUX_MIO_PAD_ATTR_48_OD_EN_48_BIT 6
+#define PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_MASK, .index = PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_MASK, .index = PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_49_REG_OFFSET 0x5e4
+#define PINMUX_MIO_PAD_ATTR_49_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_49_INVERT_49_BIT 0
+#define PINMUX_MIO_PAD_ATTR_49_VIRTUAL_OD_EN_49_BIT 1
+#define PINMUX_MIO_PAD_ATTR_49_PULL_EN_49_BIT 2
+#define PINMUX_MIO_PAD_ATTR_49_PULL_SELECT_49_BIT 3
+#define PINMUX_MIO_PAD_ATTR_49_KEEPER_EN_49_BIT 4
+#define PINMUX_MIO_PAD_ATTR_49_SCHMITT_EN_49_BIT 5
+#define PINMUX_MIO_PAD_ATTR_49_OD_EN_49_BIT 6
+#define PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_MASK, .index = PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_MASK, .index = PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_50_REG_OFFSET 0x5e8
+#define PINMUX_MIO_PAD_ATTR_50_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_50_INVERT_50_BIT 0
+#define PINMUX_MIO_PAD_ATTR_50_VIRTUAL_OD_EN_50_BIT 1
+#define PINMUX_MIO_PAD_ATTR_50_PULL_EN_50_BIT 2
+#define PINMUX_MIO_PAD_ATTR_50_PULL_SELECT_50_BIT 3
+#define PINMUX_MIO_PAD_ATTR_50_KEEPER_EN_50_BIT 4
+#define PINMUX_MIO_PAD_ATTR_50_SCHMITT_EN_50_BIT 5
+#define PINMUX_MIO_PAD_ATTR_50_OD_EN_50_BIT 6
+#define PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_MASK, .index = PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_MASK, .index = PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_51_REG_OFFSET 0x5ec
+#define PINMUX_MIO_PAD_ATTR_51_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_51_INVERT_51_BIT 0
+#define PINMUX_MIO_PAD_ATTR_51_VIRTUAL_OD_EN_51_BIT 1
+#define PINMUX_MIO_PAD_ATTR_51_PULL_EN_51_BIT 2
+#define PINMUX_MIO_PAD_ATTR_51_PULL_SELECT_51_BIT 3
+#define PINMUX_MIO_PAD_ATTR_51_KEEPER_EN_51_BIT 4
+#define PINMUX_MIO_PAD_ATTR_51_SCHMITT_EN_51_BIT 5
+#define PINMUX_MIO_PAD_ATTR_51_OD_EN_51_BIT 6
+#define PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_MASK, .index = PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_MASK, .index = PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_52_REG_OFFSET 0x5f0
+#define PINMUX_MIO_PAD_ATTR_52_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_52_INVERT_52_BIT 0
+#define PINMUX_MIO_PAD_ATTR_52_VIRTUAL_OD_EN_52_BIT 1
+#define PINMUX_MIO_PAD_ATTR_52_PULL_EN_52_BIT 2
+#define PINMUX_MIO_PAD_ATTR_52_PULL_SELECT_52_BIT 3
+#define PINMUX_MIO_PAD_ATTR_52_KEEPER_EN_52_BIT 4
+#define PINMUX_MIO_PAD_ATTR_52_SCHMITT_EN_52_BIT 5
+#define PINMUX_MIO_PAD_ATTR_52_OD_EN_52_BIT 6
+#define PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_MASK, .index = PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_MASK, .index = PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_OFFSET })
+
+// Register write enable for DIO PAD attributes. (common parameters)
+#define PINMUX_DIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 16
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0x5f4
+#define PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0x5f8
+#define PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0x5fc
+#define PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0x600
+#define PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0x604
+#define PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0x608
+#define PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0x60c
+#define PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0x610
+#define PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0x614
+#define PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0x618
+#define PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0x61c
+#define PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0x620
+#define PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_OFFSET 0x624
+#define PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_OFFSET 0x628
+#define PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_OFFSET 0x62c
+#define PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_OFFSET 0x630
+#define PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_15_EN_15_BIT 0
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_INVERT_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2
+#define PINMUX_DIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4
+#define PINMUX_DIO_PAD_ATTR_MULTIREG_COUNT 16
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_0_REG_OFFSET 0x634
+#define PINMUX_DIO_PAD_ATTR_0_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_0_INVERT_0_BIT 0
+#define PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1
+#define PINMUX_DIO_PAD_ATTR_0_PULL_EN_0_BIT 2
+#define PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3
+#define PINMUX_DIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4
+#define PINMUX_DIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5
+#define PINMUX_DIO_PAD_ATTR_0_OD_EN_0_BIT 6
+#define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_1_REG_OFFSET 0x638
+#define PINMUX_DIO_PAD_ATTR_1_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_1_INVERT_1_BIT 0
+#define PINMUX_DIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1
+#define PINMUX_DIO_PAD_ATTR_1_PULL_EN_1_BIT 2
+#define PINMUX_DIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3
+#define PINMUX_DIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4
+#define PINMUX_DIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5
+#define PINMUX_DIO_PAD_ATTR_1_OD_EN_1_BIT 6
+#define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_2_REG_OFFSET 0x63c
+#define PINMUX_DIO_PAD_ATTR_2_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_2_INVERT_2_BIT 0
+#define PINMUX_DIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1
+#define PINMUX_DIO_PAD_ATTR_2_PULL_EN_2_BIT 2
+#define PINMUX_DIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3
+#define PINMUX_DIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4
+#define PINMUX_DIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5
+#define PINMUX_DIO_PAD_ATTR_2_OD_EN_2_BIT 6
+#define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_3_REG_OFFSET 0x640
+#define PINMUX_DIO_PAD_ATTR_3_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_3_INVERT_3_BIT 0
+#define PINMUX_DIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1
+#define PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_BIT 2
+#define PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3
+#define PINMUX_DIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4
+#define PINMUX_DIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5
+#define PINMUX_DIO_PAD_ATTR_3_OD_EN_3_BIT 6
+#define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_4_REG_OFFSET 0x644
+#define PINMUX_DIO_PAD_ATTR_4_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_4_INVERT_4_BIT 0
+#define PINMUX_DIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1
+#define PINMUX_DIO_PAD_ATTR_4_PULL_EN_4_BIT 2
+#define PINMUX_DIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3
+#define PINMUX_DIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4
+#define PINMUX_DIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5
+#define PINMUX_DIO_PAD_ATTR_4_OD_EN_4_BIT 6
+#define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_5_REG_OFFSET 0x648
+#define PINMUX_DIO_PAD_ATTR_5_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_5_INVERT_5_BIT 0
+#define PINMUX_DIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1
+#define PINMUX_DIO_PAD_ATTR_5_PULL_EN_5_BIT 2
+#define PINMUX_DIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3
+#define PINMUX_DIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4
+#define PINMUX_DIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5
+#define PINMUX_DIO_PAD_ATTR_5_OD_EN_5_BIT 6
+#define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_6_REG_OFFSET 0x64c
+#define PINMUX_DIO_PAD_ATTR_6_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_6_INVERT_6_BIT 0
+#define PINMUX_DIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1
+#define PINMUX_DIO_PAD_ATTR_6_PULL_EN_6_BIT 2
+#define PINMUX_DIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3
+#define PINMUX_DIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4
+#define PINMUX_DIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5
+#define PINMUX_DIO_PAD_ATTR_6_OD_EN_6_BIT 6
+#define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_7_REG_OFFSET 0x650
+#define PINMUX_DIO_PAD_ATTR_7_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_7_INVERT_7_BIT 0
+#define PINMUX_DIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1
+#define PINMUX_DIO_PAD_ATTR_7_PULL_EN_7_BIT 2
+#define PINMUX_DIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3
+#define PINMUX_DIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4
+#define PINMUX_DIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5
+#define PINMUX_DIO_PAD_ATTR_7_OD_EN_7_BIT 6
+#define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_8_REG_OFFSET 0x654
+#define PINMUX_DIO_PAD_ATTR_8_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_8_INVERT_8_BIT 0
+#define PINMUX_DIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1
+#define PINMUX_DIO_PAD_ATTR_8_PULL_EN_8_BIT 2
+#define PINMUX_DIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3
+#define PINMUX_DIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4
+#define PINMUX_DIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5
+#define PINMUX_DIO_PAD_ATTR_8_OD_EN_8_BIT 6
+#define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_9_REG_OFFSET 0x658
+#define PINMUX_DIO_PAD_ATTR_9_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_9_INVERT_9_BIT 0
+#define PINMUX_DIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1
+#define PINMUX_DIO_PAD_ATTR_9_PULL_EN_9_BIT 2
+#define PINMUX_DIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3
+#define PINMUX_DIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4
+#define PINMUX_DIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5
+#define PINMUX_DIO_PAD_ATTR_9_OD_EN_9_BIT 6
+#define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_10_REG_OFFSET 0x65c
+#define PINMUX_DIO_PAD_ATTR_10_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_10_INVERT_10_BIT 0
+#define PINMUX_DIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1
+#define PINMUX_DIO_PAD_ATTR_10_PULL_EN_10_BIT 2
+#define PINMUX_DIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3
+#define PINMUX_DIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4
+#define PINMUX_DIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5
+#define PINMUX_DIO_PAD_ATTR_10_OD_EN_10_BIT 6
+#define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_11_REG_OFFSET 0x660
+#define PINMUX_DIO_PAD_ATTR_11_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_11_INVERT_11_BIT 0
+#define PINMUX_DIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1
+#define PINMUX_DIO_PAD_ATTR_11_PULL_EN_11_BIT 2
+#define PINMUX_DIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3
+#define PINMUX_DIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4
+#define PINMUX_DIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5
+#define PINMUX_DIO_PAD_ATTR_11_OD_EN_11_BIT 6
+#define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_12_REG_OFFSET 0x664
+#define PINMUX_DIO_PAD_ATTR_12_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_12_INVERT_12_BIT 0
+#define PINMUX_DIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_BIT 1
+#define PINMUX_DIO_PAD_ATTR_12_PULL_EN_12_BIT 2
+#define PINMUX_DIO_PAD_ATTR_12_PULL_SELECT_12_BIT 3
+#define PINMUX_DIO_PAD_ATTR_12_KEEPER_EN_12_BIT 4
+#define PINMUX_DIO_PAD_ATTR_12_SCHMITT_EN_12_BIT 5
+#define PINMUX_DIO_PAD_ATTR_12_OD_EN_12_BIT 6
+#define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_13_REG_OFFSET 0x668
+#define PINMUX_DIO_PAD_ATTR_13_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_13_INVERT_13_BIT 0
+#define PINMUX_DIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_BIT 1
+#define PINMUX_DIO_PAD_ATTR_13_PULL_EN_13_BIT 2
+#define PINMUX_DIO_PAD_ATTR_13_PULL_SELECT_13_BIT 3
+#define PINMUX_DIO_PAD_ATTR_13_KEEPER_EN_13_BIT 4
+#define PINMUX_DIO_PAD_ATTR_13_SCHMITT_EN_13_BIT 5
+#define PINMUX_DIO_PAD_ATTR_13_OD_EN_13_BIT 6
+#define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_14_REG_OFFSET 0x66c
+#define PINMUX_DIO_PAD_ATTR_14_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_14_INVERT_14_BIT 0
+#define PINMUX_DIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_BIT 1
+#define PINMUX_DIO_PAD_ATTR_14_PULL_EN_14_BIT 2
+#define PINMUX_DIO_PAD_ATTR_14_PULL_SELECT_14_BIT 3
+#define PINMUX_DIO_PAD_ATTR_14_KEEPER_EN_14_BIT 4
+#define PINMUX_DIO_PAD_ATTR_14_SCHMITT_EN_14_BIT 5
+#define PINMUX_DIO_PAD_ATTR_14_OD_EN_14_BIT 6
+#define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_15_REG_OFFSET 0x670
+#define PINMUX_DIO_PAD_ATTR_15_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_15_INVERT_15_BIT 0
+#define PINMUX_DIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_BIT 1
+#define PINMUX_DIO_PAD_ATTR_15_PULL_EN_15_BIT 2
+#define PINMUX_DIO_PAD_ATTR_15_PULL_SELECT_15_BIT 3
+#define PINMUX_DIO_PAD_ATTR_15_KEEPER_EN_15_BIT 4
+#define PINMUX_DIO_PAD_ATTR_15_SCHMITT_EN_15_BIT 5
+#define PINMUX_DIO_PAD_ATTR_15_OD_EN_15_BIT 6
+#define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET })
+
+// Register indicating whether the corresponding pad is in sleep mode.
+// (common parameters)
+#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 2
+
+// Register indicating whether the corresponding pad is in sleep mode.
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_OFFSET 0x674
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_0_BIT 0
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_1_BIT 1
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_2_BIT 2
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_3_BIT 3
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_4_BIT 4
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_5_BIT 5
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_6_BIT 6
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_7_BIT 7
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_8_BIT 8
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_9_BIT 9
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_10_BIT 10
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_11_BIT 11
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_12_BIT 12
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_13_BIT 13
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_14_BIT 14
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_15_BIT 15
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_16_BIT 16
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_17_BIT 17
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_18_BIT 18
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_19_BIT 19
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_20_BIT 20
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_21_BIT 21
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_22_BIT 22
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_23_BIT 23
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_24_BIT 24
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_25_BIT 25
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_26_BIT 26
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_27_BIT 27
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_28_BIT 28
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_29_BIT 29
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_30_BIT 30
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_31_BIT 31
+
+// Register indicating whether the corresponding pad is in sleep mode.
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_REG_OFFSET 0x678
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_32_BIT 0
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_33_BIT 1
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_34_BIT 2
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_35_BIT 3
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_36_BIT 4
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_37_BIT 5
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_38_BIT 6
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_39_BIT 7
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_40_BIT 8
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_41_BIT 9
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_42_BIT 10
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_43_BIT 11
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_44_BIT 12
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_45_BIT 13
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_46_BIT 14
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_47_BIT 15
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_48_BIT 16
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_49_BIT 17
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_50_BIT 18
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_51_BIT 19
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_52_BIT 20
+
+// Register write enable for MIO sleep value configuration. (common
+// parameters)
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 53
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x67c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x680
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x684
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x688
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x68c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x690
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x694
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x698
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x69c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x6a0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x6a4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x6a8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_12_REG_OFFSET 0x6ac
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_13_REG_OFFSET 0x6b0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_14_REG_OFFSET 0x6b4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_15_REG_OFFSET 0x6b8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_16_REG_OFFSET 0x6bc
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_16_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_17_REG_OFFSET 0x6c0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_17_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_18_REG_OFFSET 0x6c4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_18_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_19_REG_OFFSET 0x6c8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_19_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_20_REG_OFFSET 0x6cc
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_20_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_21_REG_OFFSET 0x6d0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_21_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_22_REG_OFFSET 0x6d4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_22_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_23_REG_OFFSET 0x6d8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_23_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_24_REG_OFFSET 0x6dc
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_24_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_25_REG_OFFSET 0x6e0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_25_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_26_REG_OFFSET 0x6e4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_26_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_27_REG_OFFSET 0x6e8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_27_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_28_REG_OFFSET 0x6ec
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_28_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_29_REG_OFFSET 0x6f0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_29_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_30_REG_OFFSET 0x6f4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_30_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_31_REG_OFFSET 0x6f8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_31_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_32_REG_OFFSET 0x6fc
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_32_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_33_REG_OFFSET 0x700
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_33_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_34_REG_OFFSET 0x704
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_34_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_35_REG_OFFSET 0x708
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_35_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_36_REG_OFFSET 0x70c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_36_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_37_REG_OFFSET 0x710
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_37_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_38_REG_OFFSET 0x714
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_38_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_39_REG_OFFSET 0x718
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_39_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_40_REG_OFFSET 0x71c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_40_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_41_REG_OFFSET 0x720
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_41_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_42_REG_OFFSET 0x724
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_42_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_43_REG_OFFSET 0x728
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_43_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_44_REG_OFFSET 0x72c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_44_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_45_REG_OFFSET 0x730
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_45_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_46_REG_OFFSET 0x734
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_46_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_47_REG_OFFSET 0x738
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_47_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_48_REG_OFFSET 0x73c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_48_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_49_REG_OFFSET 0x740
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_49_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_50_REG_OFFSET 0x744
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_50_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_51_REG_OFFSET 0x748
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_51_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_52_REG_OFFSET 0x74c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_52_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_52_EN_52_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad. (common parameters)
+#define PINMUX_MIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_SLEEP_EN_MULTIREG_COUNT 53
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_0_REG_OFFSET 0x750
+#define PINMUX_MIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_0_EN_0_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_1_REG_OFFSET 0x754
+#define PINMUX_MIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_1_EN_1_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_2_REG_OFFSET 0x758
+#define PINMUX_MIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_2_EN_2_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_3_REG_OFFSET 0x75c
+#define PINMUX_MIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_3_EN_3_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_4_REG_OFFSET 0x760
+#define PINMUX_MIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_4_EN_4_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_5_REG_OFFSET 0x764
+#define PINMUX_MIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_5_EN_5_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_6_REG_OFFSET 0x768
+#define PINMUX_MIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_6_EN_6_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_7_REG_OFFSET 0x76c
+#define PINMUX_MIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_7_EN_7_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_8_REG_OFFSET 0x770
+#define PINMUX_MIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_8_EN_8_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_9_REG_OFFSET 0x774
+#define PINMUX_MIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_9_EN_9_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_10_REG_OFFSET 0x778
+#define PINMUX_MIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_10_EN_10_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_11_REG_OFFSET 0x77c
+#define PINMUX_MIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_11_EN_11_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_12_REG_OFFSET 0x780
+#define PINMUX_MIO_PAD_SLEEP_EN_12_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_12_EN_12_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_13_REG_OFFSET 0x784
+#define PINMUX_MIO_PAD_SLEEP_EN_13_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_13_EN_13_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_14_REG_OFFSET 0x788
+#define PINMUX_MIO_PAD_SLEEP_EN_14_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_14_EN_14_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_15_REG_OFFSET 0x78c
+#define PINMUX_MIO_PAD_SLEEP_EN_15_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_15_EN_15_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_16_REG_OFFSET 0x790
+#define PINMUX_MIO_PAD_SLEEP_EN_16_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_16_EN_16_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_17_REG_OFFSET 0x794
+#define PINMUX_MIO_PAD_SLEEP_EN_17_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_17_EN_17_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_18_REG_OFFSET 0x798
+#define PINMUX_MIO_PAD_SLEEP_EN_18_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_18_EN_18_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_19_REG_OFFSET 0x79c
+#define PINMUX_MIO_PAD_SLEEP_EN_19_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_19_EN_19_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_20_REG_OFFSET 0x7a0
+#define PINMUX_MIO_PAD_SLEEP_EN_20_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_20_EN_20_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_21_REG_OFFSET 0x7a4
+#define PINMUX_MIO_PAD_SLEEP_EN_21_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_21_EN_21_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_22_REG_OFFSET 0x7a8
+#define PINMUX_MIO_PAD_SLEEP_EN_22_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_22_EN_22_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_23_REG_OFFSET 0x7ac
+#define PINMUX_MIO_PAD_SLEEP_EN_23_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_23_EN_23_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_24_REG_OFFSET 0x7b0
+#define PINMUX_MIO_PAD_SLEEP_EN_24_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_24_EN_24_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_25_REG_OFFSET 0x7b4
+#define PINMUX_MIO_PAD_SLEEP_EN_25_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_25_EN_25_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_26_REG_OFFSET 0x7b8
+#define PINMUX_MIO_PAD_SLEEP_EN_26_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_26_EN_26_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_27_REG_OFFSET 0x7bc
+#define PINMUX_MIO_PAD_SLEEP_EN_27_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_27_EN_27_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_28_REG_OFFSET 0x7c0
+#define PINMUX_MIO_PAD_SLEEP_EN_28_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_28_EN_28_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_29_REG_OFFSET 0x7c4
+#define PINMUX_MIO_PAD_SLEEP_EN_29_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_29_EN_29_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_30_REG_OFFSET 0x7c8
+#define PINMUX_MIO_PAD_SLEEP_EN_30_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_30_EN_30_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_31_REG_OFFSET 0x7cc
+#define PINMUX_MIO_PAD_SLEEP_EN_31_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_31_EN_31_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_32_REG_OFFSET 0x7d0
+#define PINMUX_MIO_PAD_SLEEP_EN_32_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_32_EN_32_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_33_REG_OFFSET 0x7d4
+#define PINMUX_MIO_PAD_SLEEP_EN_33_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_33_EN_33_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_34_REG_OFFSET 0x7d8
+#define PINMUX_MIO_PAD_SLEEP_EN_34_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_34_EN_34_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_35_REG_OFFSET 0x7dc
+#define PINMUX_MIO_PAD_SLEEP_EN_35_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_35_EN_35_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_36_REG_OFFSET 0x7e0
+#define PINMUX_MIO_PAD_SLEEP_EN_36_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_36_EN_36_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_37_REG_OFFSET 0x7e4
+#define PINMUX_MIO_PAD_SLEEP_EN_37_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_37_EN_37_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_38_REG_OFFSET 0x7e8
+#define PINMUX_MIO_PAD_SLEEP_EN_38_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_38_EN_38_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_39_REG_OFFSET 0x7ec
+#define PINMUX_MIO_PAD_SLEEP_EN_39_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_39_EN_39_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_40_REG_OFFSET 0x7f0
+#define PINMUX_MIO_PAD_SLEEP_EN_40_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_40_EN_40_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_41_REG_OFFSET 0x7f4
+#define PINMUX_MIO_PAD_SLEEP_EN_41_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_41_EN_41_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_42_REG_OFFSET 0x7f8
+#define PINMUX_MIO_PAD_SLEEP_EN_42_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_42_EN_42_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_43_REG_OFFSET 0x7fc
+#define PINMUX_MIO_PAD_SLEEP_EN_43_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_43_EN_43_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_44_REG_OFFSET 0x800
+#define PINMUX_MIO_PAD_SLEEP_EN_44_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_44_EN_44_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_45_REG_OFFSET 0x804
+#define PINMUX_MIO_PAD_SLEEP_EN_45_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_45_EN_45_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_46_REG_OFFSET 0x808
+#define PINMUX_MIO_PAD_SLEEP_EN_46_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_46_EN_46_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_47_REG_OFFSET 0x80c
+#define PINMUX_MIO_PAD_SLEEP_EN_47_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_47_EN_47_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_48_REG_OFFSET 0x810
+#define PINMUX_MIO_PAD_SLEEP_EN_48_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_48_EN_48_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_49_REG_OFFSET 0x814
+#define PINMUX_MIO_PAD_SLEEP_EN_49_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_49_EN_49_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_50_REG_OFFSET 0x818
+#define PINMUX_MIO_PAD_SLEEP_EN_50_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_50_EN_50_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_51_REG_OFFSET 0x81c
+#define PINMUX_MIO_PAD_SLEEP_EN_51_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_51_EN_51_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_52_REG_OFFSET 0x820
+#define PINMUX_MIO_PAD_SLEEP_EN_52_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_52_EN_52_BIT 0
+
+// Defines sleep behavior of the corresponding muxed pad. (common parameters)
+#define PINMUX_MIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2
+#define PINMUX_MIO_PAD_SLEEP_MODE_MULTIREG_COUNT 53
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x824
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET })
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x828
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x82c
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x830
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x834
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x838
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x83c
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x840
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x844
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x848
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x84c
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x850
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_REG_OFFSET 0x854
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_REG_OFFSET 0x858
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_REG_OFFSET 0x85c
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_REG_OFFSET 0x860
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_REG_OFFSET 0x864
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_REG_OFFSET 0x868
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_REG_OFFSET 0x86c
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_REG_OFFSET 0x870
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_REG_OFFSET 0x874
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_REG_OFFSET 0x878
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_REG_OFFSET 0x87c
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_REG_OFFSET 0x880
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_REG_OFFSET 0x884
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_REG_OFFSET 0x888
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_REG_OFFSET 0x88c
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_REG_OFFSET 0x890
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_REG_OFFSET 0x894
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_REG_OFFSET 0x898
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_REG_OFFSET 0x89c
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_REG_OFFSET 0x8a0
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_REG_OFFSET 0x8a4
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_REG_OFFSET 0x8a8
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_REG_OFFSET 0x8ac
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_REG_OFFSET 0x8b0
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_REG_OFFSET 0x8b4
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_REG_OFFSET 0x8b8
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_REG_OFFSET 0x8bc
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_REG_OFFSET 0x8c0
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_REG_OFFSET 0x8c4
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_REG_OFFSET 0x8c8
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_REG_OFFSET 0x8cc
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_REG_OFFSET 0x8d0
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_REG_OFFSET 0x8d4
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_REG_OFFSET 0x8d8
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_REG_OFFSET 0x8dc
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_REG_OFFSET 0x8e0
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_REG_OFFSET 0x8e4
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_REG_OFFSET 0x8e8
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_REG_OFFSET 0x8ec
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_REG_OFFSET 0x8f0
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_REG_OFFSET 0x8f4
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_OFFSET })
+
+// Register indicating whether the corresponding pad is in sleep mode.
+// (common parameters)
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 1
+
+// Register indicating whether the corresponding pad is in sleep mode.
+#define PINMUX_DIO_PAD_SLEEP_STATUS_REG_OFFSET 0x8f8
+#define PINMUX_DIO_PAD_SLEEP_STATUS_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_0_BIT 0
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_1_BIT 1
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_2_BIT 2
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_3_BIT 3
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_4_BIT 4
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_5_BIT 5
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_6_BIT 6
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_7_BIT 7
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_8_BIT 8
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_9_BIT 9
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_10_BIT 10
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_11_BIT 11
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_12_BIT 12
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_13_BIT 13
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_14_BIT 14
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_15_BIT 15
+
+// Register write enable for DIO sleep value configuration. (common
+// parameters)
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 16
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x8fc
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x900
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x904
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x908
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x90c
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x910
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x914
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x918
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x91c
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x920
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x924
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x928
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_OFFSET 0x92c
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_OFFSET 0x930
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_OFFSET 0x934
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_OFFSET 0x938
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_15_EN_15_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad. (common
+// parameters)
+#define PINMUX_DIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_SLEEP_EN_MULTIREG_COUNT 16
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_0_REG_OFFSET 0x93c
+#define PINMUX_DIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_0_EN_0_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_1_REG_OFFSET 0x940
+#define PINMUX_DIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_1_EN_1_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_2_REG_OFFSET 0x944
+#define PINMUX_DIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_2_EN_2_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_3_REG_OFFSET 0x948
+#define PINMUX_DIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_3_EN_3_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_4_REG_OFFSET 0x94c
+#define PINMUX_DIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_4_EN_4_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_5_REG_OFFSET 0x950
+#define PINMUX_DIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_5_EN_5_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_6_REG_OFFSET 0x954
+#define PINMUX_DIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_6_EN_6_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_7_REG_OFFSET 0x958
+#define PINMUX_DIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_7_EN_7_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_8_REG_OFFSET 0x95c
+#define PINMUX_DIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_8_EN_8_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_9_REG_OFFSET 0x960
+#define PINMUX_DIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_9_EN_9_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_10_REG_OFFSET 0x964
+#define PINMUX_DIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_10_EN_10_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_11_REG_OFFSET 0x968
+#define PINMUX_DIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_11_EN_11_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_12_REG_OFFSET 0x96c
+#define PINMUX_DIO_PAD_SLEEP_EN_12_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_12_EN_12_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_13_REG_OFFSET 0x970
+#define PINMUX_DIO_PAD_SLEEP_EN_13_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_13_EN_13_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_14_REG_OFFSET 0x974
+#define PINMUX_DIO_PAD_SLEEP_EN_14_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_14_EN_14_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_15_REG_OFFSET 0x978
+#define PINMUX_DIO_PAD_SLEEP_EN_15_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_15_EN_15_BIT 0
+
+// Defines sleep behavior of the corresponding dedicated pad. (common
+// parameters)
+#define PINMUX_DIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2
+#define PINMUX_DIO_PAD_SLEEP_MODE_MULTIREG_COUNT 16
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x97c
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET })
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x980
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x984
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x988
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x98c
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x990
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x994
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x998
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x99c
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x9a0
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x9a4
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x9a8
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_REG_OFFSET 0x9ac
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_REG_OFFSET 0x9b0
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_REG_OFFSET 0x9b4
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_REG_OFFSET 0x9b8
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET })
+
+// Register write enable for wakeup detectors. (common parameters)
+#define PINMUX_WKUP_DETECTOR_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_WKUP_DETECTOR_REGWEN_MULTIREG_COUNT 8
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_0_REG_OFFSET 0x9bc
+#define PINMUX_WKUP_DETECTOR_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_1_REG_OFFSET 0x9c0
+#define PINMUX_WKUP_DETECTOR_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_2_REG_OFFSET 0x9c4
+#define PINMUX_WKUP_DETECTOR_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_3_REG_OFFSET 0x9c8
+#define PINMUX_WKUP_DETECTOR_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_4_REG_OFFSET 0x9cc
+#define PINMUX_WKUP_DETECTOR_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_5_REG_OFFSET 0x9d0
+#define PINMUX_WKUP_DETECTOR_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_6_REG_OFFSET 0x9d4
+#define PINMUX_WKUP_DETECTOR_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_7_REG_OFFSET 0x9d8
+#define PINMUX_WKUP_DETECTOR_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_7_EN_7_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_EN_FIELD_WIDTH 1
+#define PINMUX_WKUP_DETECTOR_EN_MULTIREG_COUNT 8
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_0_REG_OFFSET 0x9dc
+#define PINMUX_WKUP_DETECTOR_EN_0_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_0_EN_0_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_1_REG_OFFSET 0x9e0
+#define PINMUX_WKUP_DETECTOR_EN_1_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_1_EN_1_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_2_REG_OFFSET 0x9e4
+#define PINMUX_WKUP_DETECTOR_EN_2_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_2_EN_2_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET 0x9e8
+#define PINMUX_WKUP_DETECTOR_EN_3_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_3_EN_3_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_4_REG_OFFSET 0x9ec
+#define PINMUX_WKUP_DETECTOR_EN_4_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_4_EN_4_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_5_REG_OFFSET 0x9f0
+#define PINMUX_WKUP_DETECTOR_EN_5_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_5_EN_5_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_6_REG_OFFSET 0x9f4
+#define PINMUX_WKUP_DETECTOR_EN_6_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_6_EN_6_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_7_REG_OFFSET 0x9f8
+#define PINMUX_WKUP_DETECTOR_EN_7_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_7_EN_7_BIT 0
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_MODE_FIELD_WIDTH 3
+#define PINMUX_WKUP_DETECTOR_FILTER_FIELD_WIDTH 1
+#define PINMUX_WKUP_DETECTOR_MIODIO_FIELD_WIDTH 1
+#define PINMUX_WKUP_DETECTOR_MULTIREG_COUNT 8
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_0_REG_OFFSET 0x9fc
+#define PINMUX_WKUP_DETECTOR_0_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_0_MODE_0_MASK, .index = PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET })
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_POSEDGE 0x0
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_NEGEDGE 0x1
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_EDGE 0x2
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDHIGH 0x3
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDLOW 0x4
+#define PINMUX_WKUP_DETECTOR_0_FILTER_0_BIT 3
+#define PINMUX_WKUP_DETECTOR_0_MIODIO_0_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_1_REG_OFFSET 0xa00
+#define PINMUX_WKUP_DETECTOR_1_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_1_MODE_1_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_1_MODE_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_1_MODE_1_MASK, .index = PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET })
+#define PINMUX_WKUP_DETECTOR_1_FILTER_1_BIT 3
+#define PINMUX_WKUP_DETECTOR_1_MIODIO_1_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_2_REG_OFFSET 0xa04
+#define PINMUX_WKUP_DETECTOR_2_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_2_MODE_2_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_2_MODE_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_2_MODE_2_MASK, .index = PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET })
+#define PINMUX_WKUP_DETECTOR_2_FILTER_2_BIT 3
+#define PINMUX_WKUP_DETECTOR_2_MIODIO_2_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_3_REG_OFFSET 0xa08
+#define PINMUX_WKUP_DETECTOR_3_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_3_MODE_3_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_3_MODE_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_3_MODE_3_MASK, .index = PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET })
+#define PINMUX_WKUP_DETECTOR_3_FILTER_3_BIT 3
+#define PINMUX_WKUP_DETECTOR_3_MIODIO_3_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_4_REG_OFFSET 0xa0c
+#define PINMUX_WKUP_DETECTOR_4_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_4_MODE_4_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_4_MODE_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_4_MODE_4_MASK, .index = PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET })
+#define PINMUX_WKUP_DETECTOR_4_FILTER_4_BIT 3
+#define PINMUX_WKUP_DETECTOR_4_MIODIO_4_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_5_REG_OFFSET 0xa10
+#define PINMUX_WKUP_DETECTOR_5_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_5_MODE_5_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_5_MODE_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_5_MODE_5_MASK, .index = PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET })
+#define PINMUX_WKUP_DETECTOR_5_FILTER_5_BIT 3
+#define PINMUX_WKUP_DETECTOR_5_MIODIO_5_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_6_REG_OFFSET 0xa14
+#define PINMUX_WKUP_DETECTOR_6_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_6_MODE_6_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_6_MODE_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_6_MODE_6_MASK, .index = PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET })
+#define PINMUX_WKUP_DETECTOR_6_FILTER_6_BIT 3
+#define PINMUX_WKUP_DETECTOR_6_MIODIO_6_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_7_REG_OFFSET 0xa18
+#define PINMUX_WKUP_DETECTOR_7_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_7_MODE_7_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_7_MODE_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_7_MODE_7_MASK, .index = PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET })
+#define PINMUX_WKUP_DETECTOR_7_FILTER_7_BIT 3
+#define PINMUX_WKUP_DETECTOR_7_MIODIO_7_BIT 4
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_TH_FIELD_WIDTH 8
+#define PINMUX_WKUP_DETECTOR_CNT_TH_MULTIREG_COUNT 8
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_OFFSET 0xa1c
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_OFFSET 0xa20
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_OFFSET 0xa24
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_OFFSET 0xa28
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_OFFSET 0xa2c
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_OFFSET 0xa30
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_OFFSET 0xa34
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_OFFSET 0xa38
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_SEL_FIELD_WIDTH 6
+#define PINMUX_WKUP_DETECTOR_PADSEL_MULTIREG_COUNT 8
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_REG_OFFSET 0xa3c
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_REG_OFFSET 0xa40
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_REG_OFFSET 0xa44
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_REG_OFFSET 0xa48
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_REG_OFFSET 0xa4c
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_REG_OFFSET 0xa50
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_REG_OFFSET 0xa54
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_REG_OFFSET 0xa58
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET })
+
+// Cause registers for wakeup detectors.
+#define PINMUX_WKUP_CAUSE_CAUSE_FIELD_WIDTH 1
+#define PINMUX_WKUP_CAUSE_MULTIREG_COUNT 1
+
+// Cause registers for wakeup detectors.
+#define PINMUX_WKUP_CAUSE_REG_OFFSET 0xa5c
+#define PINMUX_WKUP_CAUSE_REG_RESVAL 0x0
+#define PINMUX_WKUP_CAUSE_CAUSE_0_BIT 0
+#define PINMUX_WKUP_CAUSE_CAUSE_1_BIT 1
+#define PINMUX_WKUP_CAUSE_CAUSE_2_BIT 2
+#define PINMUX_WKUP_CAUSE_CAUSE_3_BIT 3
+#define PINMUX_WKUP_CAUSE_CAUSE_4_BIT 4
+#define PINMUX_WKUP_CAUSE_CAUSE_5_BIT 5
+#define PINMUX_WKUP_CAUSE_CAUSE_6_BIT 6
+#define PINMUX_WKUP_CAUSE_CAUSE_7_BIT 7
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _PINMUX_REG_DEFS_
+// End generated register defines for pinmux
\ No newline at end of file
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/rv_plic_regs.h b/hw/top_sencha/sparrow/hw/top_sencha/rv_plic_regs.h
new file mode 100644
index 0000000..365bfbf
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/rv_plic_regs.h
@@ -0,0 +1,2256 @@
+// Generated register defines for rv_plic
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _RV_PLIC_REG_DEFS_
+#define _RV_PLIC_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of interrupt sources
+#define RV_PLIC_PARAM_NUM_SRC 190
+
+// Number of Targets (Harts)
+#define RV_PLIC_PARAM_NUM_TARGET 2
+
+// Width of priority signals
+#define RV_PLIC_PARAM_PRIO_WIDTH 2
+
+// Number of alerts
+#define RV_PLIC_PARAM_NUM_ALERTS 1
+
+// Register width
+#define RV_PLIC_PARAM_REG_WIDTH 32
+
+// Interrupt Source 0 Priority
+#define RV_PLIC_PRIO0_REG_OFFSET 0x0
+#define RV_PLIC_PRIO0_REG_RESVAL 0x0
+#define RV_PLIC_PRIO0_PRIO0_MASK 0x3
+#define RV_PLIC_PRIO0_PRIO0_OFFSET 0
+#define RV_PLIC_PRIO0_PRIO0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO0_PRIO0_MASK, .index = RV_PLIC_PRIO0_PRIO0_OFFSET })
+
+// Interrupt Source 1 Priority
+#define RV_PLIC_PRIO1_REG_OFFSET 0x4
+#define RV_PLIC_PRIO1_REG_RESVAL 0x0
+#define RV_PLIC_PRIO1_PRIO1_MASK 0x3
+#define RV_PLIC_PRIO1_PRIO1_OFFSET 0
+#define RV_PLIC_PRIO1_PRIO1_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO1_PRIO1_MASK, .index = RV_PLIC_PRIO1_PRIO1_OFFSET })
+
+// Interrupt Source 2 Priority
+#define RV_PLIC_PRIO2_REG_OFFSET 0x8
+#define RV_PLIC_PRIO2_REG_RESVAL 0x0
+#define RV_PLIC_PRIO2_PRIO2_MASK 0x3
+#define RV_PLIC_PRIO2_PRIO2_OFFSET 0
+#define RV_PLIC_PRIO2_PRIO2_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO2_PRIO2_MASK, .index = RV_PLIC_PRIO2_PRIO2_OFFSET })
+
+// Interrupt Source 3 Priority
+#define RV_PLIC_PRIO3_REG_OFFSET 0xc
+#define RV_PLIC_PRIO3_REG_RESVAL 0x0
+#define RV_PLIC_PRIO3_PRIO3_MASK 0x3
+#define RV_PLIC_PRIO3_PRIO3_OFFSET 0
+#define RV_PLIC_PRIO3_PRIO3_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO3_PRIO3_MASK, .index = RV_PLIC_PRIO3_PRIO3_OFFSET })
+
+// Interrupt Source 4 Priority
+#define RV_PLIC_PRIO4_REG_OFFSET 0x10
+#define RV_PLIC_PRIO4_REG_RESVAL 0x0
+#define RV_PLIC_PRIO4_PRIO4_MASK 0x3
+#define RV_PLIC_PRIO4_PRIO4_OFFSET 0
+#define RV_PLIC_PRIO4_PRIO4_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO4_PRIO4_MASK, .index = RV_PLIC_PRIO4_PRIO4_OFFSET })
+
+// Interrupt Source 5 Priority
+#define RV_PLIC_PRIO5_REG_OFFSET 0x14
+#define RV_PLIC_PRIO5_REG_RESVAL 0x0
+#define RV_PLIC_PRIO5_PRIO5_MASK 0x3
+#define RV_PLIC_PRIO5_PRIO5_OFFSET 0
+#define RV_PLIC_PRIO5_PRIO5_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO5_PRIO5_MASK, .index = RV_PLIC_PRIO5_PRIO5_OFFSET })
+
+// Interrupt Source 6 Priority
+#define RV_PLIC_PRIO6_REG_OFFSET 0x18
+#define RV_PLIC_PRIO6_REG_RESVAL 0x0
+#define RV_PLIC_PRIO6_PRIO6_MASK 0x3
+#define RV_PLIC_PRIO6_PRIO6_OFFSET 0
+#define RV_PLIC_PRIO6_PRIO6_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO6_PRIO6_MASK, .index = RV_PLIC_PRIO6_PRIO6_OFFSET })
+
+// Interrupt Source 7 Priority
+#define RV_PLIC_PRIO7_REG_OFFSET 0x1c
+#define RV_PLIC_PRIO7_REG_RESVAL 0x0
+#define RV_PLIC_PRIO7_PRIO7_MASK 0x3
+#define RV_PLIC_PRIO7_PRIO7_OFFSET 0
+#define RV_PLIC_PRIO7_PRIO7_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO7_PRIO7_MASK, .index = RV_PLIC_PRIO7_PRIO7_OFFSET })
+
+// Interrupt Source 8 Priority
+#define RV_PLIC_PRIO8_REG_OFFSET 0x20
+#define RV_PLIC_PRIO8_REG_RESVAL 0x0
+#define RV_PLIC_PRIO8_PRIO8_MASK 0x3
+#define RV_PLIC_PRIO8_PRIO8_OFFSET 0
+#define RV_PLIC_PRIO8_PRIO8_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO8_PRIO8_MASK, .index = RV_PLIC_PRIO8_PRIO8_OFFSET })
+
+// Interrupt Source 9 Priority
+#define RV_PLIC_PRIO9_REG_OFFSET 0x24
+#define RV_PLIC_PRIO9_REG_RESVAL 0x0
+#define RV_PLIC_PRIO9_PRIO9_MASK 0x3
+#define RV_PLIC_PRIO9_PRIO9_OFFSET 0
+#define RV_PLIC_PRIO9_PRIO9_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO9_PRIO9_MASK, .index = RV_PLIC_PRIO9_PRIO9_OFFSET })
+
+// Interrupt Source 10 Priority
+#define RV_PLIC_PRIO10_REG_OFFSET 0x28
+#define RV_PLIC_PRIO10_REG_RESVAL 0x0
+#define RV_PLIC_PRIO10_PRIO10_MASK 0x3
+#define RV_PLIC_PRIO10_PRIO10_OFFSET 0
+#define RV_PLIC_PRIO10_PRIO10_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO10_PRIO10_MASK, .index = RV_PLIC_PRIO10_PRIO10_OFFSET })
+
+// Interrupt Source 11 Priority
+#define RV_PLIC_PRIO11_REG_OFFSET 0x2c
+#define RV_PLIC_PRIO11_REG_RESVAL 0x0
+#define RV_PLIC_PRIO11_PRIO11_MASK 0x3
+#define RV_PLIC_PRIO11_PRIO11_OFFSET 0
+#define RV_PLIC_PRIO11_PRIO11_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO11_PRIO11_MASK, .index = RV_PLIC_PRIO11_PRIO11_OFFSET })
+
+// Interrupt Source 12 Priority
+#define RV_PLIC_PRIO12_REG_OFFSET 0x30
+#define RV_PLIC_PRIO12_REG_RESVAL 0x0
+#define RV_PLIC_PRIO12_PRIO12_MASK 0x3
+#define RV_PLIC_PRIO12_PRIO12_OFFSET 0
+#define RV_PLIC_PRIO12_PRIO12_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO12_PRIO12_MASK, .index = RV_PLIC_PRIO12_PRIO12_OFFSET })
+
+// Interrupt Source 13 Priority
+#define RV_PLIC_PRIO13_REG_OFFSET 0x34
+#define RV_PLIC_PRIO13_REG_RESVAL 0x0
+#define RV_PLIC_PRIO13_PRIO13_MASK 0x3
+#define RV_PLIC_PRIO13_PRIO13_OFFSET 0
+#define RV_PLIC_PRIO13_PRIO13_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO13_PRIO13_MASK, .index = RV_PLIC_PRIO13_PRIO13_OFFSET })
+
+// Interrupt Source 14 Priority
+#define RV_PLIC_PRIO14_REG_OFFSET 0x38
+#define RV_PLIC_PRIO14_REG_RESVAL 0x0
+#define RV_PLIC_PRIO14_PRIO14_MASK 0x3
+#define RV_PLIC_PRIO14_PRIO14_OFFSET 0
+#define RV_PLIC_PRIO14_PRIO14_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO14_PRIO14_MASK, .index = RV_PLIC_PRIO14_PRIO14_OFFSET })
+
+// Interrupt Source 15 Priority
+#define RV_PLIC_PRIO15_REG_OFFSET 0x3c
+#define RV_PLIC_PRIO15_REG_RESVAL 0x0
+#define RV_PLIC_PRIO15_PRIO15_MASK 0x3
+#define RV_PLIC_PRIO15_PRIO15_OFFSET 0
+#define RV_PLIC_PRIO15_PRIO15_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO15_PRIO15_MASK, .index = RV_PLIC_PRIO15_PRIO15_OFFSET })
+
+// Interrupt Source 16 Priority
+#define RV_PLIC_PRIO16_REG_OFFSET 0x40
+#define RV_PLIC_PRIO16_REG_RESVAL 0x0
+#define RV_PLIC_PRIO16_PRIO16_MASK 0x3
+#define RV_PLIC_PRIO16_PRIO16_OFFSET 0
+#define RV_PLIC_PRIO16_PRIO16_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO16_PRIO16_MASK, .index = RV_PLIC_PRIO16_PRIO16_OFFSET })
+
+// Interrupt Source 17 Priority
+#define RV_PLIC_PRIO17_REG_OFFSET 0x44
+#define RV_PLIC_PRIO17_REG_RESVAL 0x0
+#define RV_PLIC_PRIO17_PRIO17_MASK 0x3
+#define RV_PLIC_PRIO17_PRIO17_OFFSET 0
+#define RV_PLIC_PRIO17_PRIO17_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO17_PRIO17_MASK, .index = RV_PLIC_PRIO17_PRIO17_OFFSET })
+
+// Interrupt Source 18 Priority
+#define RV_PLIC_PRIO18_REG_OFFSET 0x48
+#define RV_PLIC_PRIO18_REG_RESVAL 0x0
+#define RV_PLIC_PRIO18_PRIO18_MASK 0x3
+#define RV_PLIC_PRIO18_PRIO18_OFFSET 0
+#define RV_PLIC_PRIO18_PRIO18_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO18_PRIO18_MASK, .index = RV_PLIC_PRIO18_PRIO18_OFFSET })
+
+// Interrupt Source 19 Priority
+#define RV_PLIC_PRIO19_REG_OFFSET 0x4c
+#define RV_PLIC_PRIO19_REG_RESVAL 0x0
+#define RV_PLIC_PRIO19_PRIO19_MASK 0x3
+#define RV_PLIC_PRIO19_PRIO19_OFFSET 0
+#define RV_PLIC_PRIO19_PRIO19_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO19_PRIO19_MASK, .index = RV_PLIC_PRIO19_PRIO19_OFFSET })
+
+// Interrupt Source 20 Priority
+#define RV_PLIC_PRIO20_REG_OFFSET 0x50
+#define RV_PLIC_PRIO20_REG_RESVAL 0x0
+#define RV_PLIC_PRIO20_PRIO20_MASK 0x3
+#define RV_PLIC_PRIO20_PRIO20_OFFSET 0
+#define RV_PLIC_PRIO20_PRIO20_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO20_PRIO20_MASK, .index = RV_PLIC_PRIO20_PRIO20_OFFSET })
+
+// Interrupt Source 21 Priority
+#define RV_PLIC_PRIO21_REG_OFFSET 0x54
+#define RV_PLIC_PRIO21_REG_RESVAL 0x0
+#define RV_PLIC_PRIO21_PRIO21_MASK 0x3
+#define RV_PLIC_PRIO21_PRIO21_OFFSET 0
+#define RV_PLIC_PRIO21_PRIO21_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO21_PRIO21_MASK, .index = RV_PLIC_PRIO21_PRIO21_OFFSET })
+
+// Interrupt Source 22 Priority
+#define RV_PLIC_PRIO22_REG_OFFSET 0x58
+#define RV_PLIC_PRIO22_REG_RESVAL 0x0
+#define RV_PLIC_PRIO22_PRIO22_MASK 0x3
+#define RV_PLIC_PRIO22_PRIO22_OFFSET 0
+#define RV_PLIC_PRIO22_PRIO22_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO22_PRIO22_MASK, .index = RV_PLIC_PRIO22_PRIO22_OFFSET })
+
+// Interrupt Source 23 Priority
+#define RV_PLIC_PRIO23_REG_OFFSET 0x5c
+#define RV_PLIC_PRIO23_REG_RESVAL 0x0
+#define RV_PLIC_PRIO23_PRIO23_MASK 0x3
+#define RV_PLIC_PRIO23_PRIO23_OFFSET 0
+#define RV_PLIC_PRIO23_PRIO23_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO23_PRIO23_MASK, .index = RV_PLIC_PRIO23_PRIO23_OFFSET })
+
+// Interrupt Source 24 Priority
+#define RV_PLIC_PRIO24_REG_OFFSET 0x60
+#define RV_PLIC_PRIO24_REG_RESVAL 0x0
+#define RV_PLIC_PRIO24_PRIO24_MASK 0x3
+#define RV_PLIC_PRIO24_PRIO24_OFFSET 0
+#define RV_PLIC_PRIO24_PRIO24_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO24_PRIO24_MASK, .index = RV_PLIC_PRIO24_PRIO24_OFFSET })
+
+// Interrupt Source 25 Priority
+#define RV_PLIC_PRIO25_REG_OFFSET 0x64
+#define RV_PLIC_PRIO25_REG_RESVAL 0x0
+#define RV_PLIC_PRIO25_PRIO25_MASK 0x3
+#define RV_PLIC_PRIO25_PRIO25_OFFSET 0
+#define RV_PLIC_PRIO25_PRIO25_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO25_PRIO25_MASK, .index = RV_PLIC_PRIO25_PRIO25_OFFSET })
+
+// Interrupt Source 26 Priority
+#define RV_PLIC_PRIO26_REG_OFFSET 0x68
+#define RV_PLIC_PRIO26_REG_RESVAL 0x0
+#define RV_PLIC_PRIO26_PRIO26_MASK 0x3
+#define RV_PLIC_PRIO26_PRIO26_OFFSET 0
+#define RV_PLIC_PRIO26_PRIO26_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO26_PRIO26_MASK, .index = RV_PLIC_PRIO26_PRIO26_OFFSET })
+
+// Interrupt Source 27 Priority
+#define RV_PLIC_PRIO27_REG_OFFSET 0x6c
+#define RV_PLIC_PRIO27_REG_RESVAL 0x0
+#define RV_PLIC_PRIO27_PRIO27_MASK 0x3
+#define RV_PLIC_PRIO27_PRIO27_OFFSET 0
+#define RV_PLIC_PRIO27_PRIO27_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO27_PRIO27_MASK, .index = RV_PLIC_PRIO27_PRIO27_OFFSET })
+
+// Interrupt Source 28 Priority
+#define RV_PLIC_PRIO28_REG_OFFSET 0x70
+#define RV_PLIC_PRIO28_REG_RESVAL 0x0
+#define RV_PLIC_PRIO28_PRIO28_MASK 0x3
+#define RV_PLIC_PRIO28_PRIO28_OFFSET 0
+#define RV_PLIC_PRIO28_PRIO28_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO28_PRIO28_MASK, .index = RV_PLIC_PRIO28_PRIO28_OFFSET })
+
+// Interrupt Source 29 Priority
+#define RV_PLIC_PRIO29_REG_OFFSET 0x74
+#define RV_PLIC_PRIO29_REG_RESVAL 0x0
+#define RV_PLIC_PRIO29_PRIO29_MASK 0x3
+#define RV_PLIC_PRIO29_PRIO29_OFFSET 0
+#define RV_PLIC_PRIO29_PRIO29_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO29_PRIO29_MASK, .index = RV_PLIC_PRIO29_PRIO29_OFFSET })
+
+// Interrupt Source 30 Priority
+#define RV_PLIC_PRIO30_REG_OFFSET 0x78
+#define RV_PLIC_PRIO30_REG_RESVAL 0x0
+#define RV_PLIC_PRIO30_PRIO30_MASK 0x3
+#define RV_PLIC_PRIO30_PRIO30_OFFSET 0
+#define RV_PLIC_PRIO30_PRIO30_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO30_PRIO30_MASK, .index = RV_PLIC_PRIO30_PRIO30_OFFSET })
+
+// Interrupt Source 31 Priority
+#define RV_PLIC_PRIO31_REG_OFFSET 0x7c
+#define RV_PLIC_PRIO31_REG_RESVAL 0x0
+#define RV_PLIC_PRIO31_PRIO31_MASK 0x3
+#define RV_PLIC_PRIO31_PRIO31_OFFSET 0
+#define RV_PLIC_PRIO31_PRIO31_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO31_PRIO31_MASK, .index = RV_PLIC_PRIO31_PRIO31_OFFSET })
+
+// Interrupt Source 32 Priority
+#define RV_PLIC_PRIO32_REG_OFFSET 0x80
+#define RV_PLIC_PRIO32_REG_RESVAL 0x0
+#define RV_PLIC_PRIO32_PRIO32_MASK 0x3
+#define RV_PLIC_PRIO32_PRIO32_OFFSET 0
+#define RV_PLIC_PRIO32_PRIO32_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO32_PRIO32_MASK, .index = RV_PLIC_PRIO32_PRIO32_OFFSET })
+
+// Interrupt Source 33 Priority
+#define RV_PLIC_PRIO33_REG_OFFSET 0x84
+#define RV_PLIC_PRIO33_REG_RESVAL 0x0
+#define RV_PLIC_PRIO33_PRIO33_MASK 0x3
+#define RV_PLIC_PRIO33_PRIO33_OFFSET 0
+#define RV_PLIC_PRIO33_PRIO33_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO33_PRIO33_MASK, .index = RV_PLIC_PRIO33_PRIO33_OFFSET })
+
+// Interrupt Source 34 Priority
+#define RV_PLIC_PRIO34_REG_OFFSET 0x88
+#define RV_PLIC_PRIO34_REG_RESVAL 0x0
+#define RV_PLIC_PRIO34_PRIO34_MASK 0x3
+#define RV_PLIC_PRIO34_PRIO34_OFFSET 0
+#define RV_PLIC_PRIO34_PRIO34_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO34_PRIO34_MASK, .index = RV_PLIC_PRIO34_PRIO34_OFFSET })
+
+// Interrupt Source 35 Priority
+#define RV_PLIC_PRIO35_REG_OFFSET 0x8c
+#define RV_PLIC_PRIO35_REG_RESVAL 0x0
+#define RV_PLIC_PRIO35_PRIO35_MASK 0x3
+#define RV_PLIC_PRIO35_PRIO35_OFFSET 0
+#define RV_PLIC_PRIO35_PRIO35_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO35_PRIO35_MASK, .index = RV_PLIC_PRIO35_PRIO35_OFFSET })
+
+// Interrupt Source 36 Priority
+#define RV_PLIC_PRIO36_REG_OFFSET 0x90
+#define RV_PLIC_PRIO36_REG_RESVAL 0x0
+#define RV_PLIC_PRIO36_PRIO36_MASK 0x3
+#define RV_PLIC_PRIO36_PRIO36_OFFSET 0
+#define RV_PLIC_PRIO36_PRIO36_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO36_PRIO36_MASK, .index = RV_PLIC_PRIO36_PRIO36_OFFSET })
+
+// Interrupt Source 37 Priority
+#define RV_PLIC_PRIO37_REG_OFFSET 0x94
+#define RV_PLIC_PRIO37_REG_RESVAL 0x0
+#define RV_PLIC_PRIO37_PRIO37_MASK 0x3
+#define RV_PLIC_PRIO37_PRIO37_OFFSET 0
+#define RV_PLIC_PRIO37_PRIO37_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO37_PRIO37_MASK, .index = RV_PLIC_PRIO37_PRIO37_OFFSET })
+
+// Interrupt Source 38 Priority
+#define RV_PLIC_PRIO38_REG_OFFSET 0x98
+#define RV_PLIC_PRIO38_REG_RESVAL 0x0
+#define RV_PLIC_PRIO38_PRIO38_MASK 0x3
+#define RV_PLIC_PRIO38_PRIO38_OFFSET 0
+#define RV_PLIC_PRIO38_PRIO38_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO38_PRIO38_MASK, .index = RV_PLIC_PRIO38_PRIO38_OFFSET })
+
+// Interrupt Source 39 Priority
+#define RV_PLIC_PRIO39_REG_OFFSET 0x9c
+#define RV_PLIC_PRIO39_REG_RESVAL 0x0
+#define RV_PLIC_PRIO39_PRIO39_MASK 0x3
+#define RV_PLIC_PRIO39_PRIO39_OFFSET 0
+#define RV_PLIC_PRIO39_PRIO39_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO39_PRIO39_MASK, .index = RV_PLIC_PRIO39_PRIO39_OFFSET })
+
+// Interrupt Source 40 Priority
+#define RV_PLIC_PRIO40_REG_OFFSET 0xa0
+#define RV_PLIC_PRIO40_REG_RESVAL 0x0
+#define RV_PLIC_PRIO40_PRIO40_MASK 0x3
+#define RV_PLIC_PRIO40_PRIO40_OFFSET 0
+#define RV_PLIC_PRIO40_PRIO40_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO40_PRIO40_MASK, .index = RV_PLIC_PRIO40_PRIO40_OFFSET })
+
+// Interrupt Source 41 Priority
+#define RV_PLIC_PRIO41_REG_OFFSET 0xa4
+#define RV_PLIC_PRIO41_REG_RESVAL 0x0
+#define RV_PLIC_PRIO41_PRIO41_MASK 0x3
+#define RV_PLIC_PRIO41_PRIO41_OFFSET 0
+#define RV_PLIC_PRIO41_PRIO41_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO41_PRIO41_MASK, .index = RV_PLIC_PRIO41_PRIO41_OFFSET })
+
+// Interrupt Source 42 Priority
+#define RV_PLIC_PRIO42_REG_OFFSET 0xa8
+#define RV_PLIC_PRIO42_REG_RESVAL 0x0
+#define RV_PLIC_PRIO42_PRIO42_MASK 0x3
+#define RV_PLIC_PRIO42_PRIO42_OFFSET 0
+#define RV_PLIC_PRIO42_PRIO42_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO42_PRIO42_MASK, .index = RV_PLIC_PRIO42_PRIO42_OFFSET })
+
+// Interrupt Source 43 Priority
+#define RV_PLIC_PRIO43_REG_OFFSET 0xac
+#define RV_PLIC_PRIO43_REG_RESVAL 0x0
+#define RV_PLIC_PRIO43_PRIO43_MASK 0x3
+#define RV_PLIC_PRIO43_PRIO43_OFFSET 0
+#define RV_PLIC_PRIO43_PRIO43_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO43_PRIO43_MASK, .index = RV_PLIC_PRIO43_PRIO43_OFFSET })
+
+// Interrupt Source 44 Priority
+#define RV_PLIC_PRIO44_REG_OFFSET 0xb0
+#define RV_PLIC_PRIO44_REG_RESVAL 0x0
+#define RV_PLIC_PRIO44_PRIO44_MASK 0x3
+#define RV_PLIC_PRIO44_PRIO44_OFFSET 0
+#define RV_PLIC_PRIO44_PRIO44_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO44_PRIO44_MASK, .index = RV_PLIC_PRIO44_PRIO44_OFFSET })
+
+// Interrupt Source 45 Priority
+#define RV_PLIC_PRIO45_REG_OFFSET 0xb4
+#define RV_PLIC_PRIO45_REG_RESVAL 0x0
+#define RV_PLIC_PRIO45_PRIO45_MASK 0x3
+#define RV_PLIC_PRIO45_PRIO45_OFFSET 0
+#define RV_PLIC_PRIO45_PRIO45_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO45_PRIO45_MASK, .index = RV_PLIC_PRIO45_PRIO45_OFFSET })
+
+// Interrupt Source 46 Priority
+#define RV_PLIC_PRIO46_REG_OFFSET 0xb8
+#define RV_PLIC_PRIO46_REG_RESVAL 0x0
+#define RV_PLIC_PRIO46_PRIO46_MASK 0x3
+#define RV_PLIC_PRIO46_PRIO46_OFFSET 0
+#define RV_PLIC_PRIO46_PRIO46_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO46_PRIO46_MASK, .index = RV_PLIC_PRIO46_PRIO46_OFFSET })
+
+// Interrupt Source 47 Priority
+#define RV_PLIC_PRIO47_REG_OFFSET 0xbc
+#define RV_PLIC_PRIO47_REG_RESVAL 0x0
+#define RV_PLIC_PRIO47_PRIO47_MASK 0x3
+#define RV_PLIC_PRIO47_PRIO47_OFFSET 0
+#define RV_PLIC_PRIO47_PRIO47_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO47_PRIO47_MASK, .index = RV_PLIC_PRIO47_PRIO47_OFFSET })
+
+// Interrupt Source 48 Priority
+#define RV_PLIC_PRIO48_REG_OFFSET 0xc0
+#define RV_PLIC_PRIO48_REG_RESVAL 0x0
+#define RV_PLIC_PRIO48_PRIO48_MASK 0x3
+#define RV_PLIC_PRIO48_PRIO48_OFFSET 0
+#define RV_PLIC_PRIO48_PRIO48_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO48_PRIO48_MASK, .index = RV_PLIC_PRIO48_PRIO48_OFFSET })
+
+// Interrupt Source 49 Priority
+#define RV_PLIC_PRIO49_REG_OFFSET 0xc4
+#define RV_PLIC_PRIO49_REG_RESVAL 0x0
+#define RV_PLIC_PRIO49_PRIO49_MASK 0x3
+#define RV_PLIC_PRIO49_PRIO49_OFFSET 0
+#define RV_PLIC_PRIO49_PRIO49_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO49_PRIO49_MASK, .index = RV_PLIC_PRIO49_PRIO49_OFFSET })
+
+// Interrupt Source 50 Priority
+#define RV_PLIC_PRIO50_REG_OFFSET 0xc8
+#define RV_PLIC_PRIO50_REG_RESVAL 0x0
+#define RV_PLIC_PRIO50_PRIO50_MASK 0x3
+#define RV_PLIC_PRIO50_PRIO50_OFFSET 0
+#define RV_PLIC_PRIO50_PRIO50_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO50_PRIO50_MASK, .index = RV_PLIC_PRIO50_PRIO50_OFFSET })
+
+// Interrupt Source 51 Priority
+#define RV_PLIC_PRIO51_REG_OFFSET 0xcc
+#define RV_PLIC_PRIO51_REG_RESVAL 0x0
+#define RV_PLIC_PRIO51_PRIO51_MASK 0x3
+#define RV_PLIC_PRIO51_PRIO51_OFFSET 0
+#define RV_PLIC_PRIO51_PRIO51_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO51_PRIO51_MASK, .index = RV_PLIC_PRIO51_PRIO51_OFFSET })
+
+// Interrupt Source 52 Priority
+#define RV_PLIC_PRIO52_REG_OFFSET 0xd0
+#define RV_PLIC_PRIO52_REG_RESVAL 0x0
+#define RV_PLIC_PRIO52_PRIO52_MASK 0x3
+#define RV_PLIC_PRIO52_PRIO52_OFFSET 0
+#define RV_PLIC_PRIO52_PRIO52_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO52_PRIO52_MASK, .index = RV_PLIC_PRIO52_PRIO52_OFFSET })
+
+// Interrupt Source 53 Priority
+#define RV_PLIC_PRIO53_REG_OFFSET 0xd4
+#define RV_PLIC_PRIO53_REG_RESVAL 0x0
+#define RV_PLIC_PRIO53_PRIO53_MASK 0x3
+#define RV_PLIC_PRIO53_PRIO53_OFFSET 0
+#define RV_PLIC_PRIO53_PRIO53_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO53_PRIO53_MASK, .index = RV_PLIC_PRIO53_PRIO53_OFFSET })
+
+// Interrupt Source 54 Priority
+#define RV_PLIC_PRIO54_REG_OFFSET 0xd8
+#define RV_PLIC_PRIO54_REG_RESVAL 0x0
+#define RV_PLIC_PRIO54_PRIO54_MASK 0x3
+#define RV_PLIC_PRIO54_PRIO54_OFFSET 0
+#define RV_PLIC_PRIO54_PRIO54_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO54_PRIO54_MASK, .index = RV_PLIC_PRIO54_PRIO54_OFFSET })
+
+// Interrupt Source 55 Priority
+#define RV_PLIC_PRIO55_REG_OFFSET 0xdc
+#define RV_PLIC_PRIO55_REG_RESVAL 0x0
+#define RV_PLIC_PRIO55_PRIO55_MASK 0x3
+#define RV_PLIC_PRIO55_PRIO55_OFFSET 0
+#define RV_PLIC_PRIO55_PRIO55_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO55_PRIO55_MASK, .index = RV_PLIC_PRIO55_PRIO55_OFFSET })
+
+// Interrupt Source 56 Priority
+#define RV_PLIC_PRIO56_REG_OFFSET 0xe0
+#define RV_PLIC_PRIO56_REG_RESVAL 0x0
+#define RV_PLIC_PRIO56_PRIO56_MASK 0x3
+#define RV_PLIC_PRIO56_PRIO56_OFFSET 0
+#define RV_PLIC_PRIO56_PRIO56_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO56_PRIO56_MASK, .index = RV_PLIC_PRIO56_PRIO56_OFFSET })
+
+// Interrupt Source 57 Priority
+#define RV_PLIC_PRIO57_REG_OFFSET 0xe4
+#define RV_PLIC_PRIO57_REG_RESVAL 0x0
+#define RV_PLIC_PRIO57_PRIO57_MASK 0x3
+#define RV_PLIC_PRIO57_PRIO57_OFFSET 0
+#define RV_PLIC_PRIO57_PRIO57_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO57_PRIO57_MASK, .index = RV_PLIC_PRIO57_PRIO57_OFFSET })
+
+// Interrupt Source 58 Priority
+#define RV_PLIC_PRIO58_REG_OFFSET 0xe8
+#define RV_PLIC_PRIO58_REG_RESVAL 0x0
+#define RV_PLIC_PRIO58_PRIO58_MASK 0x3
+#define RV_PLIC_PRIO58_PRIO58_OFFSET 0
+#define RV_PLIC_PRIO58_PRIO58_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO58_PRIO58_MASK, .index = RV_PLIC_PRIO58_PRIO58_OFFSET })
+
+// Interrupt Source 59 Priority
+#define RV_PLIC_PRIO59_REG_OFFSET 0xec
+#define RV_PLIC_PRIO59_REG_RESVAL 0x0
+#define RV_PLIC_PRIO59_PRIO59_MASK 0x3
+#define RV_PLIC_PRIO59_PRIO59_OFFSET 0
+#define RV_PLIC_PRIO59_PRIO59_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO59_PRIO59_MASK, .index = RV_PLIC_PRIO59_PRIO59_OFFSET })
+
+// Interrupt Source 60 Priority
+#define RV_PLIC_PRIO60_REG_OFFSET 0xf0
+#define RV_PLIC_PRIO60_REG_RESVAL 0x0
+#define RV_PLIC_PRIO60_PRIO60_MASK 0x3
+#define RV_PLIC_PRIO60_PRIO60_OFFSET 0
+#define RV_PLIC_PRIO60_PRIO60_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO60_PRIO60_MASK, .index = RV_PLIC_PRIO60_PRIO60_OFFSET })
+
+// Interrupt Source 61 Priority
+#define RV_PLIC_PRIO61_REG_OFFSET 0xf4
+#define RV_PLIC_PRIO61_REG_RESVAL 0x0
+#define RV_PLIC_PRIO61_PRIO61_MASK 0x3
+#define RV_PLIC_PRIO61_PRIO61_OFFSET 0
+#define RV_PLIC_PRIO61_PRIO61_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO61_PRIO61_MASK, .index = RV_PLIC_PRIO61_PRIO61_OFFSET })
+
+// Interrupt Source 62 Priority
+#define RV_PLIC_PRIO62_REG_OFFSET 0xf8
+#define RV_PLIC_PRIO62_REG_RESVAL 0x0
+#define RV_PLIC_PRIO62_PRIO62_MASK 0x3
+#define RV_PLIC_PRIO62_PRIO62_OFFSET 0
+#define RV_PLIC_PRIO62_PRIO62_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO62_PRIO62_MASK, .index = RV_PLIC_PRIO62_PRIO62_OFFSET })
+
+// Interrupt Source 63 Priority
+#define RV_PLIC_PRIO63_REG_OFFSET 0xfc
+#define RV_PLIC_PRIO63_REG_RESVAL 0x0
+#define RV_PLIC_PRIO63_PRIO63_MASK 0x3
+#define RV_PLIC_PRIO63_PRIO63_OFFSET 0
+#define RV_PLIC_PRIO63_PRIO63_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO63_PRIO63_MASK, .index = RV_PLIC_PRIO63_PRIO63_OFFSET })
+
+// Interrupt Source 64 Priority
+#define RV_PLIC_PRIO64_REG_OFFSET 0x100
+#define RV_PLIC_PRIO64_REG_RESVAL 0x0
+#define RV_PLIC_PRIO64_PRIO64_MASK 0x3
+#define RV_PLIC_PRIO64_PRIO64_OFFSET 0
+#define RV_PLIC_PRIO64_PRIO64_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO64_PRIO64_MASK, .index = RV_PLIC_PRIO64_PRIO64_OFFSET })
+
+// Interrupt Source 65 Priority
+#define RV_PLIC_PRIO65_REG_OFFSET 0x104
+#define RV_PLIC_PRIO65_REG_RESVAL 0x0
+#define RV_PLIC_PRIO65_PRIO65_MASK 0x3
+#define RV_PLIC_PRIO65_PRIO65_OFFSET 0
+#define RV_PLIC_PRIO65_PRIO65_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO65_PRIO65_MASK, .index = RV_PLIC_PRIO65_PRIO65_OFFSET })
+
+// Interrupt Source 66 Priority
+#define RV_PLIC_PRIO66_REG_OFFSET 0x108
+#define RV_PLIC_PRIO66_REG_RESVAL 0x0
+#define RV_PLIC_PRIO66_PRIO66_MASK 0x3
+#define RV_PLIC_PRIO66_PRIO66_OFFSET 0
+#define RV_PLIC_PRIO66_PRIO66_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO66_PRIO66_MASK, .index = RV_PLIC_PRIO66_PRIO66_OFFSET })
+
+// Interrupt Source 67 Priority
+#define RV_PLIC_PRIO67_REG_OFFSET 0x10c
+#define RV_PLIC_PRIO67_REG_RESVAL 0x0
+#define RV_PLIC_PRIO67_PRIO67_MASK 0x3
+#define RV_PLIC_PRIO67_PRIO67_OFFSET 0
+#define RV_PLIC_PRIO67_PRIO67_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO67_PRIO67_MASK, .index = RV_PLIC_PRIO67_PRIO67_OFFSET })
+
+// Interrupt Source 68 Priority
+#define RV_PLIC_PRIO68_REG_OFFSET 0x110
+#define RV_PLIC_PRIO68_REG_RESVAL 0x0
+#define RV_PLIC_PRIO68_PRIO68_MASK 0x3
+#define RV_PLIC_PRIO68_PRIO68_OFFSET 0
+#define RV_PLIC_PRIO68_PRIO68_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO68_PRIO68_MASK, .index = RV_PLIC_PRIO68_PRIO68_OFFSET })
+
+// Interrupt Source 69 Priority
+#define RV_PLIC_PRIO69_REG_OFFSET 0x114
+#define RV_PLIC_PRIO69_REG_RESVAL 0x0
+#define RV_PLIC_PRIO69_PRIO69_MASK 0x3
+#define RV_PLIC_PRIO69_PRIO69_OFFSET 0
+#define RV_PLIC_PRIO69_PRIO69_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO69_PRIO69_MASK, .index = RV_PLIC_PRIO69_PRIO69_OFFSET })
+
+// Interrupt Source 70 Priority
+#define RV_PLIC_PRIO70_REG_OFFSET 0x118
+#define RV_PLIC_PRIO70_REG_RESVAL 0x0
+#define RV_PLIC_PRIO70_PRIO70_MASK 0x3
+#define RV_PLIC_PRIO70_PRIO70_OFFSET 0
+#define RV_PLIC_PRIO70_PRIO70_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO70_PRIO70_MASK, .index = RV_PLIC_PRIO70_PRIO70_OFFSET })
+
+// Interrupt Source 71 Priority
+#define RV_PLIC_PRIO71_REG_OFFSET 0x11c
+#define RV_PLIC_PRIO71_REG_RESVAL 0x0
+#define RV_PLIC_PRIO71_PRIO71_MASK 0x3
+#define RV_PLIC_PRIO71_PRIO71_OFFSET 0
+#define RV_PLIC_PRIO71_PRIO71_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO71_PRIO71_MASK, .index = RV_PLIC_PRIO71_PRIO71_OFFSET })
+
+// Interrupt Source 72 Priority
+#define RV_PLIC_PRIO72_REG_OFFSET 0x120
+#define RV_PLIC_PRIO72_REG_RESVAL 0x0
+#define RV_PLIC_PRIO72_PRIO72_MASK 0x3
+#define RV_PLIC_PRIO72_PRIO72_OFFSET 0
+#define RV_PLIC_PRIO72_PRIO72_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO72_PRIO72_MASK, .index = RV_PLIC_PRIO72_PRIO72_OFFSET })
+
+// Interrupt Source 73 Priority
+#define RV_PLIC_PRIO73_REG_OFFSET 0x124
+#define RV_PLIC_PRIO73_REG_RESVAL 0x0
+#define RV_PLIC_PRIO73_PRIO73_MASK 0x3
+#define RV_PLIC_PRIO73_PRIO73_OFFSET 0
+#define RV_PLIC_PRIO73_PRIO73_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO73_PRIO73_MASK, .index = RV_PLIC_PRIO73_PRIO73_OFFSET })
+
+// Interrupt Source 74 Priority
+#define RV_PLIC_PRIO74_REG_OFFSET 0x128
+#define RV_PLIC_PRIO74_REG_RESVAL 0x0
+#define RV_PLIC_PRIO74_PRIO74_MASK 0x3
+#define RV_PLIC_PRIO74_PRIO74_OFFSET 0
+#define RV_PLIC_PRIO74_PRIO74_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO74_PRIO74_MASK, .index = RV_PLIC_PRIO74_PRIO74_OFFSET })
+
+// Interrupt Source 75 Priority
+#define RV_PLIC_PRIO75_REG_OFFSET 0x12c
+#define RV_PLIC_PRIO75_REG_RESVAL 0x0
+#define RV_PLIC_PRIO75_PRIO75_MASK 0x3
+#define RV_PLIC_PRIO75_PRIO75_OFFSET 0
+#define RV_PLIC_PRIO75_PRIO75_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO75_PRIO75_MASK, .index = RV_PLIC_PRIO75_PRIO75_OFFSET })
+
+// Interrupt Source 76 Priority
+#define RV_PLIC_PRIO76_REG_OFFSET 0x130
+#define RV_PLIC_PRIO76_REG_RESVAL 0x0
+#define RV_PLIC_PRIO76_PRIO76_MASK 0x3
+#define RV_PLIC_PRIO76_PRIO76_OFFSET 0
+#define RV_PLIC_PRIO76_PRIO76_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO76_PRIO76_MASK, .index = RV_PLIC_PRIO76_PRIO76_OFFSET })
+
+// Interrupt Source 77 Priority
+#define RV_PLIC_PRIO77_REG_OFFSET 0x134
+#define RV_PLIC_PRIO77_REG_RESVAL 0x0
+#define RV_PLIC_PRIO77_PRIO77_MASK 0x3
+#define RV_PLIC_PRIO77_PRIO77_OFFSET 0
+#define RV_PLIC_PRIO77_PRIO77_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO77_PRIO77_MASK, .index = RV_PLIC_PRIO77_PRIO77_OFFSET })
+
+// Interrupt Source 78 Priority
+#define RV_PLIC_PRIO78_REG_OFFSET 0x138
+#define RV_PLIC_PRIO78_REG_RESVAL 0x0
+#define RV_PLIC_PRIO78_PRIO78_MASK 0x3
+#define RV_PLIC_PRIO78_PRIO78_OFFSET 0
+#define RV_PLIC_PRIO78_PRIO78_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO78_PRIO78_MASK, .index = RV_PLIC_PRIO78_PRIO78_OFFSET })
+
+// Interrupt Source 79 Priority
+#define RV_PLIC_PRIO79_REG_OFFSET 0x13c
+#define RV_PLIC_PRIO79_REG_RESVAL 0x0
+#define RV_PLIC_PRIO79_PRIO79_MASK 0x3
+#define RV_PLIC_PRIO79_PRIO79_OFFSET 0
+#define RV_PLIC_PRIO79_PRIO79_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO79_PRIO79_MASK, .index = RV_PLIC_PRIO79_PRIO79_OFFSET })
+
+// Interrupt Source 80 Priority
+#define RV_PLIC_PRIO80_REG_OFFSET 0x140
+#define RV_PLIC_PRIO80_REG_RESVAL 0x0
+#define RV_PLIC_PRIO80_PRIO80_MASK 0x3
+#define RV_PLIC_PRIO80_PRIO80_OFFSET 0
+#define RV_PLIC_PRIO80_PRIO80_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO80_PRIO80_MASK, .index = RV_PLIC_PRIO80_PRIO80_OFFSET })
+
+// Interrupt Source 81 Priority
+#define RV_PLIC_PRIO81_REG_OFFSET 0x144
+#define RV_PLIC_PRIO81_REG_RESVAL 0x0
+#define RV_PLIC_PRIO81_PRIO81_MASK 0x3
+#define RV_PLIC_PRIO81_PRIO81_OFFSET 0
+#define RV_PLIC_PRIO81_PRIO81_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO81_PRIO81_MASK, .index = RV_PLIC_PRIO81_PRIO81_OFFSET })
+
+// Interrupt Source 82 Priority
+#define RV_PLIC_PRIO82_REG_OFFSET 0x148
+#define RV_PLIC_PRIO82_REG_RESVAL 0x0
+#define RV_PLIC_PRIO82_PRIO82_MASK 0x3
+#define RV_PLIC_PRIO82_PRIO82_OFFSET 0
+#define RV_PLIC_PRIO82_PRIO82_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO82_PRIO82_MASK, .index = RV_PLIC_PRIO82_PRIO82_OFFSET })
+
+// Interrupt Source 83 Priority
+#define RV_PLIC_PRIO83_REG_OFFSET 0x14c
+#define RV_PLIC_PRIO83_REG_RESVAL 0x0
+#define RV_PLIC_PRIO83_PRIO83_MASK 0x3
+#define RV_PLIC_PRIO83_PRIO83_OFFSET 0
+#define RV_PLIC_PRIO83_PRIO83_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO83_PRIO83_MASK, .index = RV_PLIC_PRIO83_PRIO83_OFFSET })
+
+// Interrupt Source 84 Priority
+#define RV_PLIC_PRIO84_REG_OFFSET 0x150
+#define RV_PLIC_PRIO84_REG_RESVAL 0x0
+#define RV_PLIC_PRIO84_PRIO84_MASK 0x3
+#define RV_PLIC_PRIO84_PRIO84_OFFSET 0
+#define RV_PLIC_PRIO84_PRIO84_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO84_PRIO84_MASK, .index = RV_PLIC_PRIO84_PRIO84_OFFSET })
+
+// Interrupt Source 85 Priority
+#define RV_PLIC_PRIO85_REG_OFFSET 0x154
+#define RV_PLIC_PRIO85_REG_RESVAL 0x0
+#define RV_PLIC_PRIO85_PRIO85_MASK 0x3
+#define RV_PLIC_PRIO85_PRIO85_OFFSET 0
+#define RV_PLIC_PRIO85_PRIO85_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO85_PRIO85_MASK, .index = RV_PLIC_PRIO85_PRIO85_OFFSET })
+
+// Interrupt Source 86 Priority
+#define RV_PLIC_PRIO86_REG_OFFSET 0x158
+#define RV_PLIC_PRIO86_REG_RESVAL 0x0
+#define RV_PLIC_PRIO86_PRIO86_MASK 0x3
+#define RV_PLIC_PRIO86_PRIO86_OFFSET 0
+#define RV_PLIC_PRIO86_PRIO86_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO86_PRIO86_MASK, .index = RV_PLIC_PRIO86_PRIO86_OFFSET })
+
+// Interrupt Source 87 Priority
+#define RV_PLIC_PRIO87_REG_OFFSET 0x15c
+#define RV_PLIC_PRIO87_REG_RESVAL 0x0
+#define RV_PLIC_PRIO87_PRIO87_MASK 0x3
+#define RV_PLIC_PRIO87_PRIO87_OFFSET 0
+#define RV_PLIC_PRIO87_PRIO87_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO87_PRIO87_MASK, .index = RV_PLIC_PRIO87_PRIO87_OFFSET })
+
+// Interrupt Source 88 Priority
+#define RV_PLIC_PRIO88_REG_OFFSET 0x160
+#define RV_PLIC_PRIO88_REG_RESVAL 0x0
+#define RV_PLIC_PRIO88_PRIO88_MASK 0x3
+#define RV_PLIC_PRIO88_PRIO88_OFFSET 0
+#define RV_PLIC_PRIO88_PRIO88_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO88_PRIO88_MASK, .index = RV_PLIC_PRIO88_PRIO88_OFFSET })
+
+// Interrupt Source 89 Priority
+#define RV_PLIC_PRIO89_REG_OFFSET 0x164
+#define RV_PLIC_PRIO89_REG_RESVAL 0x0
+#define RV_PLIC_PRIO89_PRIO89_MASK 0x3
+#define RV_PLIC_PRIO89_PRIO89_OFFSET 0
+#define RV_PLIC_PRIO89_PRIO89_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO89_PRIO89_MASK, .index = RV_PLIC_PRIO89_PRIO89_OFFSET })
+
+// Interrupt Source 90 Priority
+#define RV_PLIC_PRIO90_REG_OFFSET 0x168
+#define RV_PLIC_PRIO90_REG_RESVAL 0x0
+#define RV_PLIC_PRIO90_PRIO90_MASK 0x3
+#define RV_PLIC_PRIO90_PRIO90_OFFSET 0
+#define RV_PLIC_PRIO90_PRIO90_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO90_PRIO90_MASK, .index = RV_PLIC_PRIO90_PRIO90_OFFSET })
+
+// Interrupt Source 91 Priority
+#define RV_PLIC_PRIO91_REG_OFFSET 0x16c
+#define RV_PLIC_PRIO91_REG_RESVAL 0x0
+#define RV_PLIC_PRIO91_PRIO91_MASK 0x3
+#define RV_PLIC_PRIO91_PRIO91_OFFSET 0
+#define RV_PLIC_PRIO91_PRIO91_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO91_PRIO91_MASK, .index = RV_PLIC_PRIO91_PRIO91_OFFSET })
+
+// Interrupt Source 92 Priority
+#define RV_PLIC_PRIO92_REG_OFFSET 0x170
+#define RV_PLIC_PRIO92_REG_RESVAL 0x0
+#define RV_PLIC_PRIO92_PRIO92_MASK 0x3
+#define RV_PLIC_PRIO92_PRIO92_OFFSET 0
+#define RV_PLIC_PRIO92_PRIO92_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO92_PRIO92_MASK, .index = RV_PLIC_PRIO92_PRIO92_OFFSET })
+
+// Interrupt Source 93 Priority
+#define RV_PLIC_PRIO93_REG_OFFSET 0x174
+#define RV_PLIC_PRIO93_REG_RESVAL 0x0
+#define RV_PLIC_PRIO93_PRIO93_MASK 0x3
+#define RV_PLIC_PRIO93_PRIO93_OFFSET 0
+#define RV_PLIC_PRIO93_PRIO93_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO93_PRIO93_MASK, .index = RV_PLIC_PRIO93_PRIO93_OFFSET })
+
+// Interrupt Source 94 Priority
+#define RV_PLIC_PRIO94_REG_OFFSET 0x178
+#define RV_PLIC_PRIO94_REG_RESVAL 0x0
+#define RV_PLIC_PRIO94_PRIO94_MASK 0x3
+#define RV_PLIC_PRIO94_PRIO94_OFFSET 0
+#define RV_PLIC_PRIO94_PRIO94_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO94_PRIO94_MASK, .index = RV_PLIC_PRIO94_PRIO94_OFFSET })
+
+// Interrupt Source 95 Priority
+#define RV_PLIC_PRIO95_REG_OFFSET 0x17c
+#define RV_PLIC_PRIO95_REG_RESVAL 0x0
+#define RV_PLIC_PRIO95_PRIO95_MASK 0x3
+#define RV_PLIC_PRIO95_PRIO95_OFFSET 0
+#define RV_PLIC_PRIO95_PRIO95_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO95_PRIO95_MASK, .index = RV_PLIC_PRIO95_PRIO95_OFFSET })
+
+// Interrupt Source 96 Priority
+#define RV_PLIC_PRIO96_REG_OFFSET 0x180
+#define RV_PLIC_PRIO96_REG_RESVAL 0x0
+#define RV_PLIC_PRIO96_PRIO96_MASK 0x3
+#define RV_PLIC_PRIO96_PRIO96_OFFSET 0
+#define RV_PLIC_PRIO96_PRIO96_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO96_PRIO96_MASK, .index = RV_PLIC_PRIO96_PRIO96_OFFSET })
+
+// Interrupt Source 97 Priority
+#define RV_PLIC_PRIO97_REG_OFFSET 0x184
+#define RV_PLIC_PRIO97_REG_RESVAL 0x0
+#define RV_PLIC_PRIO97_PRIO97_MASK 0x3
+#define RV_PLIC_PRIO97_PRIO97_OFFSET 0
+#define RV_PLIC_PRIO97_PRIO97_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO97_PRIO97_MASK, .index = RV_PLIC_PRIO97_PRIO97_OFFSET })
+
+// Interrupt Source 98 Priority
+#define RV_PLIC_PRIO98_REG_OFFSET 0x188
+#define RV_PLIC_PRIO98_REG_RESVAL 0x0
+#define RV_PLIC_PRIO98_PRIO98_MASK 0x3
+#define RV_PLIC_PRIO98_PRIO98_OFFSET 0
+#define RV_PLIC_PRIO98_PRIO98_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO98_PRIO98_MASK, .index = RV_PLIC_PRIO98_PRIO98_OFFSET })
+
+// Interrupt Source 99 Priority
+#define RV_PLIC_PRIO99_REG_OFFSET 0x18c
+#define RV_PLIC_PRIO99_REG_RESVAL 0x0
+#define RV_PLIC_PRIO99_PRIO99_MASK 0x3
+#define RV_PLIC_PRIO99_PRIO99_OFFSET 0
+#define RV_PLIC_PRIO99_PRIO99_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO99_PRIO99_MASK, .index = RV_PLIC_PRIO99_PRIO99_OFFSET })
+
+// Interrupt Source 100 Priority
+#define RV_PLIC_PRIO100_REG_OFFSET 0x190
+#define RV_PLIC_PRIO100_REG_RESVAL 0x0
+#define RV_PLIC_PRIO100_PRIO100_MASK 0x3
+#define RV_PLIC_PRIO100_PRIO100_OFFSET 0
+#define RV_PLIC_PRIO100_PRIO100_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO100_PRIO100_MASK, .index = RV_PLIC_PRIO100_PRIO100_OFFSET })
+
+// Interrupt Source 101 Priority
+#define RV_PLIC_PRIO101_REG_OFFSET 0x194
+#define RV_PLIC_PRIO101_REG_RESVAL 0x0
+#define RV_PLIC_PRIO101_PRIO101_MASK 0x3
+#define RV_PLIC_PRIO101_PRIO101_OFFSET 0
+#define RV_PLIC_PRIO101_PRIO101_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO101_PRIO101_MASK, .index = RV_PLIC_PRIO101_PRIO101_OFFSET })
+
+// Interrupt Source 102 Priority
+#define RV_PLIC_PRIO102_REG_OFFSET 0x198
+#define RV_PLIC_PRIO102_REG_RESVAL 0x0
+#define RV_PLIC_PRIO102_PRIO102_MASK 0x3
+#define RV_PLIC_PRIO102_PRIO102_OFFSET 0
+#define RV_PLIC_PRIO102_PRIO102_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO102_PRIO102_MASK, .index = RV_PLIC_PRIO102_PRIO102_OFFSET })
+
+// Interrupt Source 103 Priority
+#define RV_PLIC_PRIO103_REG_OFFSET 0x19c
+#define RV_PLIC_PRIO103_REG_RESVAL 0x0
+#define RV_PLIC_PRIO103_PRIO103_MASK 0x3
+#define RV_PLIC_PRIO103_PRIO103_OFFSET 0
+#define RV_PLIC_PRIO103_PRIO103_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO103_PRIO103_MASK, .index = RV_PLIC_PRIO103_PRIO103_OFFSET })
+
+// Interrupt Source 104 Priority
+#define RV_PLIC_PRIO104_REG_OFFSET 0x1a0
+#define RV_PLIC_PRIO104_REG_RESVAL 0x0
+#define RV_PLIC_PRIO104_PRIO104_MASK 0x3
+#define RV_PLIC_PRIO104_PRIO104_OFFSET 0
+#define RV_PLIC_PRIO104_PRIO104_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO104_PRIO104_MASK, .index = RV_PLIC_PRIO104_PRIO104_OFFSET })
+
+// Interrupt Source 105 Priority
+#define RV_PLIC_PRIO105_REG_OFFSET 0x1a4
+#define RV_PLIC_PRIO105_REG_RESVAL 0x0
+#define RV_PLIC_PRIO105_PRIO105_MASK 0x3
+#define RV_PLIC_PRIO105_PRIO105_OFFSET 0
+#define RV_PLIC_PRIO105_PRIO105_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO105_PRIO105_MASK, .index = RV_PLIC_PRIO105_PRIO105_OFFSET })
+
+// Interrupt Source 106 Priority
+#define RV_PLIC_PRIO106_REG_OFFSET 0x1a8
+#define RV_PLIC_PRIO106_REG_RESVAL 0x0
+#define RV_PLIC_PRIO106_PRIO106_MASK 0x3
+#define RV_PLIC_PRIO106_PRIO106_OFFSET 0
+#define RV_PLIC_PRIO106_PRIO106_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO106_PRIO106_MASK, .index = RV_PLIC_PRIO106_PRIO106_OFFSET })
+
+// Interrupt Source 107 Priority
+#define RV_PLIC_PRIO107_REG_OFFSET 0x1ac
+#define RV_PLIC_PRIO107_REG_RESVAL 0x0
+#define RV_PLIC_PRIO107_PRIO107_MASK 0x3
+#define RV_PLIC_PRIO107_PRIO107_OFFSET 0
+#define RV_PLIC_PRIO107_PRIO107_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO107_PRIO107_MASK, .index = RV_PLIC_PRIO107_PRIO107_OFFSET })
+
+// Interrupt Source 108 Priority
+#define RV_PLIC_PRIO108_REG_OFFSET 0x1b0
+#define RV_PLIC_PRIO108_REG_RESVAL 0x0
+#define RV_PLIC_PRIO108_PRIO108_MASK 0x3
+#define RV_PLIC_PRIO108_PRIO108_OFFSET 0
+#define RV_PLIC_PRIO108_PRIO108_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO108_PRIO108_MASK, .index = RV_PLIC_PRIO108_PRIO108_OFFSET })
+
+// Interrupt Source 109 Priority
+#define RV_PLIC_PRIO109_REG_OFFSET 0x1b4
+#define RV_PLIC_PRIO109_REG_RESVAL 0x0
+#define RV_PLIC_PRIO109_PRIO109_MASK 0x3
+#define RV_PLIC_PRIO109_PRIO109_OFFSET 0
+#define RV_PLIC_PRIO109_PRIO109_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO109_PRIO109_MASK, .index = RV_PLIC_PRIO109_PRIO109_OFFSET })
+
+// Interrupt Source 110 Priority
+#define RV_PLIC_PRIO110_REG_OFFSET 0x1b8
+#define RV_PLIC_PRIO110_REG_RESVAL 0x0
+#define RV_PLIC_PRIO110_PRIO110_MASK 0x3
+#define RV_PLIC_PRIO110_PRIO110_OFFSET 0
+#define RV_PLIC_PRIO110_PRIO110_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO110_PRIO110_MASK, .index = RV_PLIC_PRIO110_PRIO110_OFFSET })
+
+// Interrupt Source 111 Priority
+#define RV_PLIC_PRIO111_REG_OFFSET 0x1bc
+#define RV_PLIC_PRIO111_REG_RESVAL 0x0
+#define RV_PLIC_PRIO111_PRIO111_MASK 0x3
+#define RV_PLIC_PRIO111_PRIO111_OFFSET 0
+#define RV_PLIC_PRIO111_PRIO111_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO111_PRIO111_MASK, .index = RV_PLIC_PRIO111_PRIO111_OFFSET })
+
+// Interrupt Source 112 Priority
+#define RV_PLIC_PRIO112_REG_OFFSET 0x1c0
+#define RV_PLIC_PRIO112_REG_RESVAL 0x0
+#define RV_PLIC_PRIO112_PRIO112_MASK 0x3
+#define RV_PLIC_PRIO112_PRIO112_OFFSET 0
+#define RV_PLIC_PRIO112_PRIO112_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO112_PRIO112_MASK, .index = RV_PLIC_PRIO112_PRIO112_OFFSET })
+
+// Interrupt Source 113 Priority
+#define RV_PLIC_PRIO113_REG_OFFSET 0x1c4
+#define RV_PLIC_PRIO113_REG_RESVAL 0x0
+#define RV_PLIC_PRIO113_PRIO113_MASK 0x3
+#define RV_PLIC_PRIO113_PRIO113_OFFSET 0
+#define RV_PLIC_PRIO113_PRIO113_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO113_PRIO113_MASK, .index = RV_PLIC_PRIO113_PRIO113_OFFSET })
+
+// Interrupt Source 114 Priority
+#define RV_PLIC_PRIO114_REG_OFFSET 0x1c8
+#define RV_PLIC_PRIO114_REG_RESVAL 0x0
+#define RV_PLIC_PRIO114_PRIO114_MASK 0x3
+#define RV_PLIC_PRIO114_PRIO114_OFFSET 0
+#define RV_PLIC_PRIO114_PRIO114_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO114_PRIO114_MASK, .index = RV_PLIC_PRIO114_PRIO114_OFFSET })
+
+// Interrupt Source 115 Priority
+#define RV_PLIC_PRIO115_REG_OFFSET 0x1cc
+#define RV_PLIC_PRIO115_REG_RESVAL 0x0
+#define RV_PLIC_PRIO115_PRIO115_MASK 0x3
+#define RV_PLIC_PRIO115_PRIO115_OFFSET 0
+#define RV_PLIC_PRIO115_PRIO115_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO115_PRIO115_MASK, .index = RV_PLIC_PRIO115_PRIO115_OFFSET })
+
+// Interrupt Source 116 Priority
+#define RV_PLIC_PRIO116_REG_OFFSET 0x1d0
+#define RV_PLIC_PRIO116_REG_RESVAL 0x0
+#define RV_PLIC_PRIO116_PRIO116_MASK 0x3
+#define RV_PLIC_PRIO116_PRIO116_OFFSET 0
+#define RV_PLIC_PRIO116_PRIO116_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO116_PRIO116_MASK, .index = RV_PLIC_PRIO116_PRIO116_OFFSET })
+
+// Interrupt Source 117 Priority
+#define RV_PLIC_PRIO117_REG_OFFSET 0x1d4
+#define RV_PLIC_PRIO117_REG_RESVAL 0x0
+#define RV_PLIC_PRIO117_PRIO117_MASK 0x3
+#define RV_PLIC_PRIO117_PRIO117_OFFSET 0
+#define RV_PLIC_PRIO117_PRIO117_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO117_PRIO117_MASK, .index = RV_PLIC_PRIO117_PRIO117_OFFSET })
+
+// Interrupt Source 118 Priority
+#define RV_PLIC_PRIO118_REG_OFFSET 0x1d8
+#define RV_PLIC_PRIO118_REG_RESVAL 0x0
+#define RV_PLIC_PRIO118_PRIO118_MASK 0x3
+#define RV_PLIC_PRIO118_PRIO118_OFFSET 0
+#define RV_PLIC_PRIO118_PRIO118_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO118_PRIO118_MASK, .index = RV_PLIC_PRIO118_PRIO118_OFFSET })
+
+// Interrupt Source 119 Priority
+#define RV_PLIC_PRIO119_REG_OFFSET 0x1dc
+#define RV_PLIC_PRIO119_REG_RESVAL 0x0
+#define RV_PLIC_PRIO119_PRIO119_MASK 0x3
+#define RV_PLIC_PRIO119_PRIO119_OFFSET 0
+#define RV_PLIC_PRIO119_PRIO119_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO119_PRIO119_MASK, .index = RV_PLIC_PRIO119_PRIO119_OFFSET })
+
+// Interrupt Source 120 Priority
+#define RV_PLIC_PRIO120_REG_OFFSET 0x1e0
+#define RV_PLIC_PRIO120_REG_RESVAL 0x0
+#define RV_PLIC_PRIO120_PRIO120_MASK 0x3
+#define RV_PLIC_PRIO120_PRIO120_OFFSET 0
+#define RV_PLIC_PRIO120_PRIO120_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO120_PRIO120_MASK, .index = RV_PLIC_PRIO120_PRIO120_OFFSET })
+
+// Interrupt Source 121 Priority
+#define RV_PLIC_PRIO121_REG_OFFSET 0x1e4
+#define RV_PLIC_PRIO121_REG_RESVAL 0x0
+#define RV_PLIC_PRIO121_PRIO121_MASK 0x3
+#define RV_PLIC_PRIO121_PRIO121_OFFSET 0
+#define RV_PLIC_PRIO121_PRIO121_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO121_PRIO121_MASK, .index = RV_PLIC_PRIO121_PRIO121_OFFSET })
+
+// Interrupt Source 122 Priority
+#define RV_PLIC_PRIO122_REG_OFFSET 0x1e8
+#define RV_PLIC_PRIO122_REG_RESVAL 0x0
+#define RV_PLIC_PRIO122_PRIO122_MASK 0x3
+#define RV_PLIC_PRIO122_PRIO122_OFFSET 0
+#define RV_PLIC_PRIO122_PRIO122_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO122_PRIO122_MASK, .index = RV_PLIC_PRIO122_PRIO122_OFFSET })
+
+// Interrupt Source 123 Priority
+#define RV_PLIC_PRIO123_REG_OFFSET 0x1ec
+#define RV_PLIC_PRIO123_REG_RESVAL 0x0
+#define RV_PLIC_PRIO123_PRIO123_MASK 0x3
+#define RV_PLIC_PRIO123_PRIO123_OFFSET 0
+#define RV_PLIC_PRIO123_PRIO123_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO123_PRIO123_MASK, .index = RV_PLIC_PRIO123_PRIO123_OFFSET })
+
+// Interrupt Source 124 Priority
+#define RV_PLIC_PRIO124_REG_OFFSET 0x1f0
+#define RV_PLIC_PRIO124_REG_RESVAL 0x0
+#define RV_PLIC_PRIO124_PRIO124_MASK 0x3
+#define RV_PLIC_PRIO124_PRIO124_OFFSET 0
+#define RV_PLIC_PRIO124_PRIO124_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO124_PRIO124_MASK, .index = RV_PLIC_PRIO124_PRIO124_OFFSET })
+
+// Interrupt Source 125 Priority
+#define RV_PLIC_PRIO125_REG_OFFSET 0x1f4
+#define RV_PLIC_PRIO125_REG_RESVAL 0x0
+#define RV_PLIC_PRIO125_PRIO125_MASK 0x3
+#define RV_PLIC_PRIO125_PRIO125_OFFSET 0
+#define RV_PLIC_PRIO125_PRIO125_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO125_PRIO125_MASK, .index = RV_PLIC_PRIO125_PRIO125_OFFSET })
+
+// Interrupt Source 126 Priority
+#define RV_PLIC_PRIO126_REG_OFFSET 0x1f8
+#define RV_PLIC_PRIO126_REG_RESVAL 0x0
+#define RV_PLIC_PRIO126_PRIO126_MASK 0x3
+#define RV_PLIC_PRIO126_PRIO126_OFFSET 0
+#define RV_PLIC_PRIO126_PRIO126_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO126_PRIO126_MASK, .index = RV_PLIC_PRIO126_PRIO126_OFFSET })
+
+// Interrupt Source 127 Priority
+#define RV_PLIC_PRIO127_REG_OFFSET 0x1fc
+#define RV_PLIC_PRIO127_REG_RESVAL 0x0
+#define RV_PLIC_PRIO127_PRIO127_MASK 0x3
+#define RV_PLIC_PRIO127_PRIO127_OFFSET 0
+#define RV_PLIC_PRIO127_PRIO127_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO127_PRIO127_MASK, .index = RV_PLIC_PRIO127_PRIO127_OFFSET })
+
+// Interrupt Source 128 Priority
+#define RV_PLIC_PRIO128_REG_OFFSET 0x200
+#define RV_PLIC_PRIO128_REG_RESVAL 0x0
+#define RV_PLIC_PRIO128_PRIO128_MASK 0x3
+#define RV_PLIC_PRIO128_PRIO128_OFFSET 0
+#define RV_PLIC_PRIO128_PRIO128_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO128_PRIO128_MASK, .index = RV_PLIC_PRIO128_PRIO128_OFFSET })
+
+// Interrupt Source 129 Priority
+#define RV_PLIC_PRIO129_REG_OFFSET 0x204
+#define RV_PLIC_PRIO129_REG_RESVAL 0x0
+#define RV_PLIC_PRIO129_PRIO129_MASK 0x3
+#define RV_PLIC_PRIO129_PRIO129_OFFSET 0
+#define RV_PLIC_PRIO129_PRIO129_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO129_PRIO129_MASK, .index = RV_PLIC_PRIO129_PRIO129_OFFSET })
+
+// Interrupt Source 130 Priority
+#define RV_PLIC_PRIO130_REG_OFFSET 0x208
+#define RV_PLIC_PRIO130_REG_RESVAL 0x0
+#define RV_PLIC_PRIO130_PRIO130_MASK 0x3
+#define RV_PLIC_PRIO130_PRIO130_OFFSET 0
+#define RV_PLIC_PRIO130_PRIO130_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO130_PRIO130_MASK, .index = RV_PLIC_PRIO130_PRIO130_OFFSET })
+
+// Interrupt Source 131 Priority
+#define RV_PLIC_PRIO131_REG_OFFSET 0x20c
+#define RV_PLIC_PRIO131_REG_RESVAL 0x0
+#define RV_PLIC_PRIO131_PRIO131_MASK 0x3
+#define RV_PLIC_PRIO131_PRIO131_OFFSET 0
+#define RV_PLIC_PRIO131_PRIO131_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO131_PRIO131_MASK, .index = RV_PLIC_PRIO131_PRIO131_OFFSET })
+
+// Interrupt Source 132 Priority
+#define RV_PLIC_PRIO132_REG_OFFSET 0x210
+#define RV_PLIC_PRIO132_REG_RESVAL 0x0
+#define RV_PLIC_PRIO132_PRIO132_MASK 0x3
+#define RV_PLIC_PRIO132_PRIO132_OFFSET 0
+#define RV_PLIC_PRIO132_PRIO132_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO132_PRIO132_MASK, .index = RV_PLIC_PRIO132_PRIO132_OFFSET })
+
+// Interrupt Source 133 Priority
+#define RV_PLIC_PRIO133_REG_OFFSET 0x214
+#define RV_PLIC_PRIO133_REG_RESVAL 0x0
+#define RV_PLIC_PRIO133_PRIO133_MASK 0x3
+#define RV_PLIC_PRIO133_PRIO133_OFFSET 0
+#define RV_PLIC_PRIO133_PRIO133_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO133_PRIO133_MASK, .index = RV_PLIC_PRIO133_PRIO133_OFFSET })
+
+// Interrupt Source 134 Priority
+#define RV_PLIC_PRIO134_REG_OFFSET 0x218
+#define RV_PLIC_PRIO134_REG_RESVAL 0x0
+#define RV_PLIC_PRIO134_PRIO134_MASK 0x3
+#define RV_PLIC_PRIO134_PRIO134_OFFSET 0
+#define RV_PLIC_PRIO134_PRIO134_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO134_PRIO134_MASK, .index = RV_PLIC_PRIO134_PRIO134_OFFSET })
+
+// Interrupt Source 135 Priority
+#define RV_PLIC_PRIO135_REG_OFFSET 0x21c
+#define RV_PLIC_PRIO135_REG_RESVAL 0x0
+#define RV_PLIC_PRIO135_PRIO135_MASK 0x3
+#define RV_PLIC_PRIO135_PRIO135_OFFSET 0
+#define RV_PLIC_PRIO135_PRIO135_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO135_PRIO135_MASK, .index = RV_PLIC_PRIO135_PRIO135_OFFSET })
+
+// Interrupt Source 136 Priority
+#define RV_PLIC_PRIO136_REG_OFFSET 0x220
+#define RV_PLIC_PRIO136_REG_RESVAL 0x0
+#define RV_PLIC_PRIO136_PRIO136_MASK 0x3
+#define RV_PLIC_PRIO136_PRIO136_OFFSET 0
+#define RV_PLIC_PRIO136_PRIO136_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO136_PRIO136_MASK, .index = RV_PLIC_PRIO136_PRIO136_OFFSET })
+
+// Interrupt Source 137 Priority
+#define RV_PLIC_PRIO137_REG_OFFSET 0x224
+#define RV_PLIC_PRIO137_REG_RESVAL 0x0
+#define RV_PLIC_PRIO137_PRIO137_MASK 0x3
+#define RV_PLIC_PRIO137_PRIO137_OFFSET 0
+#define RV_PLIC_PRIO137_PRIO137_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO137_PRIO137_MASK, .index = RV_PLIC_PRIO137_PRIO137_OFFSET })
+
+// Interrupt Source 138 Priority
+#define RV_PLIC_PRIO138_REG_OFFSET 0x228
+#define RV_PLIC_PRIO138_REG_RESVAL 0x0
+#define RV_PLIC_PRIO138_PRIO138_MASK 0x3
+#define RV_PLIC_PRIO138_PRIO138_OFFSET 0
+#define RV_PLIC_PRIO138_PRIO138_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO138_PRIO138_MASK, .index = RV_PLIC_PRIO138_PRIO138_OFFSET })
+
+// Interrupt Source 139 Priority
+#define RV_PLIC_PRIO139_REG_OFFSET 0x22c
+#define RV_PLIC_PRIO139_REG_RESVAL 0x0
+#define RV_PLIC_PRIO139_PRIO139_MASK 0x3
+#define RV_PLIC_PRIO139_PRIO139_OFFSET 0
+#define RV_PLIC_PRIO139_PRIO139_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO139_PRIO139_MASK, .index = RV_PLIC_PRIO139_PRIO139_OFFSET })
+
+// Interrupt Source 140 Priority
+#define RV_PLIC_PRIO140_REG_OFFSET 0x230
+#define RV_PLIC_PRIO140_REG_RESVAL 0x0
+#define RV_PLIC_PRIO140_PRIO140_MASK 0x3
+#define RV_PLIC_PRIO140_PRIO140_OFFSET 0
+#define RV_PLIC_PRIO140_PRIO140_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO140_PRIO140_MASK, .index = RV_PLIC_PRIO140_PRIO140_OFFSET })
+
+// Interrupt Source 141 Priority
+#define RV_PLIC_PRIO141_REG_OFFSET 0x234
+#define RV_PLIC_PRIO141_REG_RESVAL 0x0
+#define RV_PLIC_PRIO141_PRIO141_MASK 0x3
+#define RV_PLIC_PRIO141_PRIO141_OFFSET 0
+#define RV_PLIC_PRIO141_PRIO141_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO141_PRIO141_MASK, .index = RV_PLIC_PRIO141_PRIO141_OFFSET })
+
+// Interrupt Source 142 Priority
+#define RV_PLIC_PRIO142_REG_OFFSET 0x238
+#define RV_PLIC_PRIO142_REG_RESVAL 0x0
+#define RV_PLIC_PRIO142_PRIO142_MASK 0x3
+#define RV_PLIC_PRIO142_PRIO142_OFFSET 0
+#define RV_PLIC_PRIO142_PRIO142_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO142_PRIO142_MASK, .index = RV_PLIC_PRIO142_PRIO142_OFFSET })
+
+// Interrupt Source 143 Priority
+#define RV_PLIC_PRIO143_REG_OFFSET 0x23c
+#define RV_PLIC_PRIO143_REG_RESVAL 0x0
+#define RV_PLIC_PRIO143_PRIO143_MASK 0x3
+#define RV_PLIC_PRIO143_PRIO143_OFFSET 0
+#define RV_PLIC_PRIO143_PRIO143_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO143_PRIO143_MASK, .index = RV_PLIC_PRIO143_PRIO143_OFFSET })
+
+// Interrupt Source 144 Priority
+#define RV_PLIC_PRIO144_REG_OFFSET 0x240
+#define RV_PLIC_PRIO144_REG_RESVAL 0x0
+#define RV_PLIC_PRIO144_PRIO144_MASK 0x3
+#define RV_PLIC_PRIO144_PRIO144_OFFSET 0
+#define RV_PLIC_PRIO144_PRIO144_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO144_PRIO144_MASK, .index = RV_PLIC_PRIO144_PRIO144_OFFSET })
+
+// Interrupt Source 145 Priority
+#define RV_PLIC_PRIO145_REG_OFFSET 0x244
+#define RV_PLIC_PRIO145_REG_RESVAL 0x0
+#define RV_PLIC_PRIO145_PRIO145_MASK 0x3
+#define RV_PLIC_PRIO145_PRIO145_OFFSET 0
+#define RV_PLIC_PRIO145_PRIO145_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO145_PRIO145_MASK, .index = RV_PLIC_PRIO145_PRIO145_OFFSET })
+
+// Interrupt Source 146 Priority
+#define RV_PLIC_PRIO146_REG_OFFSET 0x248
+#define RV_PLIC_PRIO146_REG_RESVAL 0x0
+#define RV_PLIC_PRIO146_PRIO146_MASK 0x3
+#define RV_PLIC_PRIO146_PRIO146_OFFSET 0
+#define RV_PLIC_PRIO146_PRIO146_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO146_PRIO146_MASK, .index = RV_PLIC_PRIO146_PRIO146_OFFSET })
+
+// Interrupt Source 147 Priority
+#define RV_PLIC_PRIO147_REG_OFFSET 0x24c
+#define RV_PLIC_PRIO147_REG_RESVAL 0x0
+#define RV_PLIC_PRIO147_PRIO147_MASK 0x3
+#define RV_PLIC_PRIO147_PRIO147_OFFSET 0
+#define RV_PLIC_PRIO147_PRIO147_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO147_PRIO147_MASK, .index = RV_PLIC_PRIO147_PRIO147_OFFSET })
+
+// Interrupt Source 148 Priority
+#define RV_PLIC_PRIO148_REG_OFFSET 0x250
+#define RV_PLIC_PRIO148_REG_RESVAL 0x0
+#define RV_PLIC_PRIO148_PRIO148_MASK 0x3
+#define RV_PLIC_PRIO148_PRIO148_OFFSET 0
+#define RV_PLIC_PRIO148_PRIO148_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO148_PRIO148_MASK, .index = RV_PLIC_PRIO148_PRIO148_OFFSET })
+
+// Interrupt Source 149 Priority
+#define RV_PLIC_PRIO149_REG_OFFSET 0x254
+#define RV_PLIC_PRIO149_REG_RESVAL 0x0
+#define RV_PLIC_PRIO149_PRIO149_MASK 0x3
+#define RV_PLIC_PRIO149_PRIO149_OFFSET 0
+#define RV_PLIC_PRIO149_PRIO149_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO149_PRIO149_MASK, .index = RV_PLIC_PRIO149_PRIO149_OFFSET })
+
+// Interrupt Source 150 Priority
+#define RV_PLIC_PRIO150_REG_OFFSET 0x258
+#define RV_PLIC_PRIO150_REG_RESVAL 0x0
+#define RV_PLIC_PRIO150_PRIO150_MASK 0x3
+#define RV_PLIC_PRIO150_PRIO150_OFFSET 0
+#define RV_PLIC_PRIO150_PRIO150_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO150_PRIO150_MASK, .index = RV_PLIC_PRIO150_PRIO150_OFFSET })
+
+// Interrupt Source 151 Priority
+#define RV_PLIC_PRIO151_REG_OFFSET 0x25c
+#define RV_PLIC_PRIO151_REG_RESVAL 0x0
+#define RV_PLIC_PRIO151_PRIO151_MASK 0x3
+#define RV_PLIC_PRIO151_PRIO151_OFFSET 0
+#define RV_PLIC_PRIO151_PRIO151_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO151_PRIO151_MASK, .index = RV_PLIC_PRIO151_PRIO151_OFFSET })
+
+// Interrupt Source 152 Priority
+#define RV_PLIC_PRIO152_REG_OFFSET 0x260
+#define RV_PLIC_PRIO152_REG_RESVAL 0x0
+#define RV_PLIC_PRIO152_PRIO152_MASK 0x3
+#define RV_PLIC_PRIO152_PRIO152_OFFSET 0
+#define RV_PLIC_PRIO152_PRIO152_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO152_PRIO152_MASK, .index = RV_PLIC_PRIO152_PRIO152_OFFSET })
+
+// Interrupt Source 153 Priority
+#define RV_PLIC_PRIO153_REG_OFFSET 0x264
+#define RV_PLIC_PRIO153_REG_RESVAL 0x0
+#define RV_PLIC_PRIO153_PRIO153_MASK 0x3
+#define RV_PLIC_PRIO153_PRIO153_OFFSET 0
+#define RV_PLIC_PRIO153_PRIO153_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO153_PRIO153_MASK, .index = RV_PLIC_PRIO153_PRIO153_OFFSET })
+
+// Interrupt Source 154 Priority
+#define RV_PLIC_PRIO154_REG_OFFSET 0x268
+#define RV_PLIC_PRIO154_REG_RESVAL 0x0
+#define RV_PLIC_PRIO154_PRIO154_MASK 0x3
+#define RV_PLIC_PRIO154_PRIO154_OFFSET 0
+#define RV_PLIC_PRIO154_PRIO154_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO154_PRIO154_MASK, .index = RV_PLIC_PRIO154_PRIO154_OFFSET })
+
+// Interrupt Source 155 Priority
+#define RV_PLIC_PRIO155_REG_OFFSET 0x26c
+#define RV_PLIC_PRIO155_REG_RESVAL 0x0
+#define RV_PLIC_PRIO155_PRIO155_MASK 0x3
+#define RV_PLIC_PRIO155_PRIO155_OFFSET 0
+#define RV_PLIC_PRIO155_PRIO155_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO155_PRIO155_MASK, .index = RV_PLIC_PRIO155_PRIO155_OFFSET })
+
+// Interrupt Source 156 Priority
+#define RV_PLIC_PRIO156_REG_OFFSET 0x270
+#define RV_PLIC_PRIO156_REG_RESVAL 0x0
+#define RV_PLIC_PRIO156_PRIO156_MASK 0x3
+#define RV_PLIC_PRIO156_PRIO156_OFFSET 0
+#define RV_PLIC_PRIO156_PRIO156_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO156_PRIO156_MASK, .index = RV_PLIC_PRIO156_PRIO156_OFFSET })
+
+// Interrupt Source 157 Priority
+#define RV_PLIC_PRIO157_REG_OFFSET 0x274
+#define RV_PLIC_PRIO157_REG_RESVAL 0x0
+#define RV_PLIC_PRIO157_PRIO157_MASK 0x3
+#define RV_PLIC_PRIO157_PRIO157_OFFSET 0
+#define RV_PLIC_PRIO157_PRIO157_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO157_PRIO157_MASK, .index = RV_PLIC_PRIO157_PRIO157_OFFSET })
+
+// Interrupt Source 158 Priority
+#define RV_PLIC_PRIO158_REG_OFFSET 0x278
+#define RV_PLIC_PRIO158_REG_RESVAL 0x0
+#define RV_PLIC_PRIO158_PRIO158_MASK 0x3
+#define RV_PLIC_PRIO158_PRIO158_OFFSET 0
+#define RV_PLIC_PRIO158_PRIO158_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO158_PRIO158_MASK, .index = RV_PLIC_PRIO158_PRIO158_OFFSET })
+
+// Interrupt Source 159 Priority
+#define RV_PLIC_PRIO159_REG_OFFSET 0x27c
+#define RV_PLIC_PRIO159_REG_RESVAL 0x0
+#define RV_PLIC_PRIO159_PRIO159_MASK 0x3
+#define RV_PLIC_PRIO159_PRIO159_OFFSET 0
+#define RV_PLIC_PRIO159_PRIO159_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO159_PRIO159_MASK, .index = RV_PLIC_PRIO159_PRIO159_OFFSET })
+
+// Interrupt Source 160 Priority
+#define RV_PLIC_PRIO160_REG_OFFSET 0x280
+#define RV_PLIC_PRIO160_REG_RESVAL 0x0
+#define RV_PLIC_PRIO160_PRIO160_MASK 0x3
+#define RV_PLIC_PRIO160_PRIO160_OFFSET 0
+#define RV_PLIC_PRIO160_PRIO160_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO160_PRIO160_MASK, .index = RV_PLIC_PRIO160_PRIO160_OFFSET })
+
+// Interrupt Source 161 Priority
+#define RV_PLIC_PRIO161_REG_OFFSET 0x284
+#define RV_PLIC_PRIO161_REG_RESVAL 0x0
+#define RV_PLIC_PRIO161_PRIO161_MASK 0x3
+#define RV_PLIC_PRIO161_PRIO161_OFFSET 0
+#define RV_PLIC_PRIO161_PRIO161_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO161_PRIO161_MASK, .index = RV_PLIC_PRIO161_PRIO161_OFFSET })
+
+// Interrupt Source 162 Priority
+#define RV_PLIC_PRIO162_REG_OFFSET 0x288
+#define RV_PLIC_PRIO162_REG_RESVAL 0x0
+#define RV_PLIC_PRIO162_PRIO162_MASK 0x3
+#define RV_PLIC_PRIO162_PRIO162_OFFSET 0
+#define RV_PLIC_PRIO162_PRIO162_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO162_PRIO162_MASK, .index = RV_PLIC_PRIO162_PRIO162_OFFSET })
+
+// Interrupt Source 163 Priority
+#define RV_PLIC_PRIO163_REG_OFFSET 0x28c
+#define RV_PLIC_PRIO163_REG_RESVAL 0x0
+#define RV_PLIC_PRIO163_PRIO163_MASK 0x3
+#define RV_PLIC_PRIO163_PRIO163_OFFSET 0
+#define RV_PLIC_PRIO163_PRIO163_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO163_PRIO163_MASK, .index = RV_PLIC_PRIO163_PRIO163_OFFSET })
+
+// Interrupt Source 164 Priority
+#define RV_PLIC_PRIO164_REG_OFFSET 0x290
+#define RV_PLIC_PRIO164_REG_RESVAL 0x0
+#define RV_PLIC_PRIO164_PRIO164_MASK 0x3
+#define RV_PLIC_PRIO164_PRIO164_OFFSET 0
+#define RV_PLIC_PRIO164_PRIO164_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO164_PRIO164_MASK, .index = RV_PLIC_PRIO164_PRIO164_OFFSET })
+
+// Interrupt Source 165 Priority
+#define RV_PLIC_PRIO165_REG_OFFSET 0x294
+#define RV_PLIC_PRIO165_REG_RESVAL 0x0
+#define RV_PLIC_PRIO165_PRIO165_MASK 0x3
+#define RV_PLIC_PRIO165_PRIO165_OFFSET 0
+#define RV_PLIC_PRIO165_PRIO165_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO165_PRIO165_MASK, .index = RV_PLIC_PRIO165_PRIO165_OFFSET })
+
+// Interrupt Source 166 Priority
+#define RV_PLIC_PRIO166_REG_OFFSET 0x298
+#define RV_PLIC_PRIO166_REG_RESVAL 0x0
+#define RV_PLIC_PRIO166_PRIO166_MASK 0x3
+#define RV_PLIC_PRIO166_PRIO166_OFFSET 0
+#define RV_PLIC_PRIO166_PRIO166_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO166_PRIO166_MASK, .index = RV_PLIC_PRIO166_PRIO166_OFFSET })
+
+// Interrupt Source 167 Priority
+#define RV_PLIC_PRIO167_REG_OFFSET 0x29c
+#define RV_PLIC_PRIO167_REG_RESVAL 0x0
+#define RV_PLIC_PRIO167_PRIO167_MASK 0x3
+#define RV_PLIC_PRIO167_PRIO167_OFFSET 0
+#define RV_PLIC_PRIO167_PRIO167_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO167_PRIO167_MASK, .index = RV_PLIC_PRIO167_PRIO167_OFFSET })
+
+// Interrupt Source 168 Priority
+#define RV_PLIC_PRIO168_REG_OFFSET 0x2a0
+#define RV_PLIC_PRIO168_REG_RESVAL 0x0
+#define RV_PLIC_PRIO168_PRIO168_MASK 0x3
+#define RV_PLIC_PRIO168_PRIO168_OFFSET 0
+#define RV_PLIC_PRIO168_PRIO168_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO168_PRIO168_MASK, .index = RV_PLIC_PRIO168_PRIO168_OFFSET })
+
+// Interrupt Source 169 Priority
+#define RV_PLIC_PRIO169_REG_OFFSET 0x2a4
+#define RV_PLIC_PRIO169_REG_RESVAL 0x0
+#define RV_PLIC_PRIO169_PRIO169_MASK 0x3
+#define RV_PLIC_PRIO169_PRIO169_OFFSET 0
+#define RV_PLIC_PRIO169_PRIO169_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO169_PRIO169_MASK, .index = RV_PLIC_PRIO169_PRIO169_OFFSET })
+
+// Interrupt Source 170 Priority
+#define RV_PLIC_PRIO170_REG_OFFSET 0x2a8
+#define RV_PLIC_PRIO170_REG_RESVAL 0x0
+#define RV_PLIC_PRIO170_PRIO170_MASK 0x3
+#define RV_PLIC_PRIO170_PRIO170_OFFSET 0
+#define RV_PLIC_PRIO170_PRIO170_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO170_PRIO170_MASK, .index = RV_PLIC_PRIO170_PRIO170_OFFSET })
+
+// Interrupt Source 171 Priority
+#define RV_PLIC_PRIO171_REG_OFFSET 0x2ac
+#define RV_PLIC_PRIO171_REG_RESVAL 0x0
+#define RV_PLIC_PRIO171_PRIO171_MASK 0x3
+#define RV_PLIC_PRIO171_PRIO171_OFFSET 0
+#define RV_PLIC_PRIO171_PRIO171_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO171_PRIO171_MASK, .index = RV_PLIC_PRIO171_PRIO171_OFFSET })
+
+// Interrupt Source 172 Priority
+#define RV_PLIC_PRIO172_REG_OFFSET 0x2b0
+#define RV_PLIC_PRIO172_REG_RESVAL 0x0
+#define RV_PLIC_PRIO172_PRIO172_MASK 0x3
+#define RV_PLIC_PRIO172_PRIO172_OFFSET 0
+#define RV_PLIC_PRIO172_PRIO172_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO172_PRIO172_MASK, .index = RV_PLIC_PRIO172_PRIO172_OFFSET })
+
+// Interrupt Source 173 Priority
+#define RV_PLIC_PRIO173_REG_OFFSET 0x2b4
+#define RV_PLIC_PRIO173_REG_RESVAL 0x0
+#define RV_PLIC_PRIO173_PRIO173_MASK 0x3
+#define RV_PLIC_PRIO173_PRIO173_OFFSET 0
+#define RV_PLIC_PRIO173_PRIO173_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO173_PRIO173_MASK, .index = RV_PLIC_PRIO173_PRIO173_OFFSET })
+
+// Interrupt Source 174 Priority
+#define RV_PLIC_PRIO174_REG_OFFSET 0x2b8
+#define RV_PLIC_PRIO174_REG_RESVAL 0x0
+#define RV_PLIC_PRIO174_PRIO174_MASK 0x3
+#define RV_PLIC_PRIO174_PRIO174_OFFSET 0
+#define RV_PLIC_PRIO174_PRIO174_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO174_PRIO174_MASK, .index = RV_PLIC_PRIO174_PRIO174_OFFSET })
+
+// Interrupt Source 175 Priority
+#define RV_PLIC_PRIO175_REG_OFFSET 0x2bc
+#define RV_PLIC_PRIO175_REG_RESVAL 0x0
+#define RV_PLIC_PRIO175_PRIO175_MASK 0x3
+#define RV_PLIC_PRIO175_PRIO175_OFFSET 0
+#define RV_PLIC_PRIO175_PRIO175_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO175_PRIO175_MASK, .index = RV_PLIC_PRIO175_PRIO175_OFFSET })
+
+// Interrupt Source 176 Priority
+#define RV_PLIC_PRIO176_REG_OFFSET 0x2c0
+#define RV_PLIC_PRIO176_REG_RESVAL 0x0
+#define RV_PLIC_PRIO176_PRIO176_MASK 0x3
+#define RV_PLIC_PRIO176_PRIO176_OFFSET 0
+#define RV_PLIC_PRIO176_PRIO176_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO176_PRIO176_MASK, .index = RV_PLIC_PRIO176_PRIO176_OFFSET })
+
+// Interrupt Source 177 Priority
+#define RV_PLIC_PRIO177_REG_OFFSET 0x2c4
+#define RV_PLIC_PRIO177_REG_RESVAL 0x0
+#define RV_PLIC_PRIO177_PRIO177_MASK 0x3
+#define RV_PLIC_PRIO177_PRIO177_OFFSET 0
+#define RV_PLIC_PRIO177_PRIO177_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO177_PRIO177_MASK, .index = RV_PLIC_PRIO177_PRIO177_OFFSET })
+
+// Interrupt Source 178 Priority
+#define RV_PLIC_PRIO178_REG_OFFSET 0x2c8
+#define RV_PLIC_PRIO178_REG_RESVAL 0x0
+#define RV_PLIC_PRIO178_PRIO178_MASK 0x3
+#define RV_PLIC_PRIO178_PRIO178_OFFSET 0
+#define RV_PLIC_PRIO178_PRIO178_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO178_PRIO178_MASK, .index = RV_PLIC_PRIO178_PRIO178_OFFSET })
+
+// Interrupt Source 179 Priority
+#define RV_PLIC_PRIO179_REG_OFFSET 0x2cc
+#define RV_PLIC_PRIO179_REG_RESVAL 0x0
+#define RV_PLIC_PRIO179_PRIO179_MASK 0x3
+#define RV_PLIC_PRIO179_PRIO179_OFFSET 0
+#define RV_PLIC_PRIO179_PRIO179_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO179_PRIO179_MASK, .index = RV_PLIC_PRIO179_PRIO179_OFFSET })
+
+// Interrupt Source 180 Priority
+#define RV_PLIC_PRIO180_REG_OFFSET 0x2d0
+#define RV_PLIC_PRIO180_REG_RESVAL 0x0
+#define RV_PLIC_PRIO180_PRIO180_MASK 0x3
+#define RV_PLIC_PRIO180_PRIO180_OFFSET 0
+#define RV_PLIC_PRIO180_PRIO180_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO180_PRIO180_MASK, .index = RV_PLIC_PRIO180_PRIO180_OFFSET })
+
+// Interrupt Source 181 Priority
+#define RV_PLIC_PRIO181_REG_OFFSET 0x2d4
+#define RV_PLIC_PRIO181_REG_RESVAL 0x0
+#define RV_PLIC_PRIO181_PRIO181_MASK 0x3
+#define RV_PLIC_PRIO181_PRIO181_OFFSET 0
+#define RV_PLIC_PRIO181_PRIO181_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO181_PRIO181_MASK, .index = RV_PLIC_PRIO181_PRIO181_OFFSET })
+
+// Interrupt Source 182 Priority
+#define RV_PLIC_PRIO182_REG_OFFSET 0x2d8
+#define RV_PLIC_PRIO182_REG_RESVAL 0x0
+#define RV_PLIC_PRIO182_PRIO182_MASK 0x3
+#define RV_PLIC_PRIO182_PRIO182_OFFSET 0
+#define RV_PLIC_PRIO182_PRIO182_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO182_PRIO182_MASK, .index = RV_PLIC_PRIO182_PRIO182_OFFSET })
+
+// Interrupt Source 183 Priority
+#define RV_PLIC_PRIO183_REG_OFFSET 0x2dc
+#define RV_PLIC_PRIO183_REG_RESVAL 0x0
+#define RV_PLIC_PRIO183_PRIO183_MASK 0x3
+#define RV_PLIC_PRIO183_PRIO183_OFFSET 0
+#define RV_PLIC_PRIO183_PRIO183_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO183_PRIO183_MASK, .index = RV_PLIC_PRIO183_PRIO183_OFFSET })
+
+// Interrupt Source 184 Priority
+#define RV_PLIC_PRIO184_REG_OFFSET 0x2e0
+#define RV_PLIC_PRIO184_REG_RESVAL 0x0
+#define RV_PLIC_PRIO184_PRIO184_MASK 0x3
+#define RV_PLIC_PRIO184_PRIO184_OFFSET 0
+#define RV_PLIC_PRIO184_PRIO184_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO184_PRIO184_MASK, .index = RV_PLIC_PRIO184_PRIO184_OFFSET })
+
+// Interrupt Source 185 Priority
+#define RV_PLIC_PRIO185_REG_OFFSET 0x2e4
+#define RV_PLIC_PRIO185_REG_RESVAL 0x0
+#define RV_PLIC_PRIO185_PRIO185_MASK 0x3
+#define RV_PLIC_PRIO185_PRIO185_OFFSET 0
+#define RV_PLIC_PRIO185_PRIO185_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO185_PRIO185_MASK, .index = RV_PLIC_PRIO185_PRIO185_OFFSET })
+
+// Interrupt Source 186 Priority
+#define RV_PLIC_PRIO186_REG_OFFSET 0x2e8
+#define RV_PLIC_PRIO186_REG_RESVAL 0x0
+#define RV_PLIC_PRIO186_PRIO186_MASK 0x3
+#define RV_PLIC_PRIO186_PRIO186_OFFSET 0
+#define RV_PLIC_PRIO186_PRIO186_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO186_PRIO186_MASK, .index = RV_PLIC_PRIO186_PRIO186_OFFSET })
+
+// Interrupt Source 187 Priority
+#define RV_PLIC_PRIO187_REG_OFFSET 0x2ec
+#define RV_PLIC_PRIO187_REG_RESVAL 0x0
+#define RV_PLIC_PRIO187_PRIO187_MASK 0x3
+#define RV_PLIC_PRIO187_PRIO187_OFFSET 0
+#define RV_PLIC_PRIO187_PRIO187_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO187_PRIO187_MASK, .index = RV_PLIC_PRIO187_PRIO187_OFFSET })
+
+// Interrupt Source 188 Priority
+#define RV_PLIC_PRIO188_REG_OFFSET 0x2f0
+#define RV_PLIC_PRIO188_REG_RESVAL 0x0
+#define RV_PLIC_PRIO188_PRIO188_MASK 0x3
+#define RV_PLIC_PRIO188_PRIO188_OFFSET 0
+#define RV_PLIC_PRIO188_PRIO188_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO188_PRIO188_MASK, .index = RV_PLIC_PRIO188_PRIO188_OFFSET })
+
+// Interrupt Source 189 Priority
+#define RV_PLIC_PRIO189_REG_OFFSET 0x2f4
+#define RV_PLIC_PRIO189_REG_RESVAL 0x0
+#define RV_PLIC_PRIO189_PRIO189_MASK 0x3
+#define RV_PLIC_PRIO189_PRIO189_OFFSET 0
+#define RV_PLIC_PRIO189_PRIO189_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO189_PRIO189_MASK, .index = RV_PLIC_PRIO189_PRIO189_OFFSET })
+
+// Interrupt Pending (common parameters)
+#define RV_PLIC_IP_P_FIELD_WIDTH 1
+#define RV_PLIC_IP_MULTIREG_COUNT 6
+
+// Interrupt Pending
+#define RV_PLIC_IP_0_REG_OFFSET 0x1000
+#define RV_PLIC_IP_0_REG_RESVAL 0x0
+#define RV_PLIC_IP_0_P_0_BIT 0
+#define RV_PLIC_IP_0_P_1_BIT 1
+#define RV_PLIC_IP_0_P_2_BIT 2
+#define RV_PLIC_IP_0_P_3_BIT 3
+#define RV_PLIC_IP_0_P_4_BIT 4
+#define RV_PLIC_IP_0_P_5_BIT 5
+#define RV_PLIC_IP_0_P_6_BIT 6
+#define RV_PLIC_IP_0_P_7_BIT 7
+#define RV_PLIC_IP_0_P_8_BIT 8
+#define RV_PLIC_IP_0_P_9_BIT 9
+#define RV_PLIC_IP_0_P_10_BIT 10
+#define RV_PLIC_IP_0_P_11_BIT 11
+#define RV_PLIC_IP_0_P_12_BIT 12
+#define RV_PLIC_IP_0_P_13_BIT 13
+#define RV_PLIC_IP_0_P_14_BIT 14
+#define RV_PLIC_IP_0_P_15_BIT 15
+#define RV_PLIC_IP_0_P_16_BIT 16
+#define RV_PLIC_IP_0_P_17_BIT 17
+#define RV_PLIC_IP_0_P_18_BIT 18
+#define RV_PLIC_IP_0_P_19_BIT 19
+#define RV_PLIC_IP_0_P_20_BIT 20
+#define RV_PLIC_IP_0_P_21_BIT 21
+#define RV_PLIC_IP_0_P_22_BIT 22
+#define RV_PLIC_IP_0_P_23_BIT 23
+#define RV_PLIC_IP_0_P_24_BIT 24
+#define RV_PLIC_IP_0_P_25_BIT 25
+#define RV_PLIC_IP_0_P_26_BIT 26
+#define RV_PLIC_IP_0_P_27_BIT 27
+#define RV_PLIC_IP_0_P_28_BIT 28
+#define RV_PLIC_IP_0_P_29_BIT 29
+#define RV_PLIC_IP_0_P_30_BIT 30
+#define RV_PLIC_IP_0_P_31_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_1_REG_OFFSET 0x1004
+#define RV_PLIC_IP_1_REG_RESVAL 0x0
+#define RV_PLIC_IP_1_P_32_BIT 0
+#define RV_PLIC_IP_1_P_33_BIT 1
+#define RV_PLIC_IP_1_P_34_BIT 2
+#define RV_PLIC_IP_1_P_35_BIT 3
+#define RV_PLIC_IP_1_P_36_BIT 4
+#define RV_PLIC_IP_1_P_37_BIT 5
+#define RV_PLIC_IP_1_P_38_BIT 6
+#define RV_PLIC_IP_1_P_39_BIT 7
+#define RV_PLIC_IP_1_P_40_BIT 8
+#define RV_PLIC_IP_1_P_41_BIT 9
+#define RV_PLIC_IP_1_P_42_BIT 10
+#define RV_PLIC_IP_1_P_43_BIT 11
+#define RV_PLIC_IP_1_P_44_BIT 12
+#define RV_PLIC_IP_1_P_45_BIT 13
+#define RV_PLIC_IP_1_P_46_BIT 14
+#define RV_PLIC_IP_1_P_47_BIT 15
+#define RV_PLIC_IP_1_P_48_BIT 16
+#define RV_PLIC_IP_1_P_49_BIT 17
+#define RV_PLIC_IP_1_P_50_BIT 18
+#define RV_PLIC_IP_1_P_51_BIT 19
+#define RV_PLIC_IP_1_P_52_BIT 20
+#define RV_PLIC_IP_1_P_53_BIT 21
+#define RV_PLIC_IP_1_P_54_BIT 22
+#define RV_PLIC_IP_1_P_55_BIT 23
+#define RV_PLIC_IP_1_P_56_BIT 24
+#define RV_PLIC_IP_1_P_57_BIT 25
+#define RV_PLIC_IP_1_P_58_BIT 26
+#define RV_PLIC_IP_1_P_59_BIT 27
+#define RV_PLIC_IP_1_P_60_BIT 28
+#define RV_PLIC_IP_1_P_61_BIT 29
+#define RV_PLIC_IP_1_P_62_BIT 30
+#define RV_PLIC_IP_1_P_63_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_2_REG_OFFSET 0x1008
+#define RV_PLIC_IP_2_REG_RESVAL 0x0
+#define RV_PLIC_IP_2_P_64_BIT 0
+#define RV_PLIC_IP_2_P_65_BIT 1
+#define RV_PLIC_IP_2_P_66_BIT 2
+#define RV_PLIC_IP_2_P_67_BIT 3
+#define RV_PLIC_IP_2_P_68_BIT 4
+#define RV_PLIC_IP_2_P_69_BIT 5
+#define RV_PLIC_IP_2_P_70_BIT 6
+#define RV_PLIC_IP_2_P_71_BIT 7
+#define RV_PLIC_IP_2_P_72_BIT 8
+#define RV_PLIC_IP_2_P_73_BIT 9
+#define RV_PLIC_IP_2_P_74_BIT 10
+#define RV_PLIC_IP_2_P_75_BIT 11
+#define RV_PLIC_IP_2_P_76_BIT 12
+#define RV_PLIC_IP_2_P_77_BIT 13
+#define RV_PLIC_IP_2_P_78_BIT 14
+#define RV_PLIC_IP_2_P_79_BIT 15
+#define RV_PLIC_IP_2_P_80_BIT 16
+#define RV_PLIC_IP_2_P_81_BIT 17
+#define RV_PLIC_IP_2_P_82_BIT 18
+#define RV_PLIC_IP_2_P_83_BIT 19
+#define RV_PLIC_IP_2_P_84_BIT 20
+#define RV_PLIC_IP_2_P_85_BIT 21
+#define RV_PLIC_IP_2_P_86_BIT 22
+#define RV_PLIC_IP_2_P_87_BIT 23
+#define RV_PLIC_IP_2_P_88_BIT 24
+#define RV_PLIC_IP_2_P_89_BIT 25
+#define RV_PLIC_IP_2_P_90_BIT 26
+#define RV_PLIC_IP_2_P_91_BIT 27
+#define RV_PLIC_IP_2_P_92_BIT 28
+#define RV_PLIC_IP_2_P_93_BIT 29
+#define RV_PLIC_IP_2_P_94_BIT 30
+#define RV_PLIC_IP_2_P_95_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_3_REG_OFFSET 0x100c
+#define RV_PLIC_IP_3_REG_RESVAL 0x0
+#define RV_PLIC_IP_3_P_96_BIT 0
+#define RV_PLIC_IP_3_P_97_BIT 1
+#define RV_PLIC_IP_3_P_98_BIT 2
+#define RV_PLIC_IP_3_P_99_BIT 3
+#define RV_PLIC_IP_3_P_100_BIT 4
+#define RV_PLIC_IP_3_P_101_BIT 5
+#define RV_PLIC_IP_3_P_102_BIT 6
+#define RV_PLIC_IP_3_P_103_BIT 7
+#define RV_PLIC_IP_3_P_104_BIT 8
+#define RV_PLIC_IP_3_P_105_BIT 9
+#define RV_PLIC_IP_3_P_106_BIT 10
+#define RV_PLIC_IP_3_P_107_BIT 11
+#define RV_PLIC_IP_3_P_108_BIT 12
+#define RV_PLIC_IP_3_P_109_BIT 13
+#define RV_PLIC_IP_3_P_110_BIT 14
+#define RV_PLIC_IP_3_P_111_BIT 15
+#define RV_PLIC_IP_3_P_112_BIT 16
+#define RV_PLIC_IP_3_P_113_BIT 17
+#define RV_PLIC_IP_3_P_114_BIT 18
+#define RV_PLIC_IP_3_P_115_BIT 19
+#define RV_PLIC_IP_3_P_116_BIT 20
+#define RV_PLIC_IP_3_P_117_BIT 21
+#define RV_PLIC_IP_3_P_118_BIT 22
+#define RV_PLIC_IP_3_P_119_BIT 23
+#define RV_PLIC_IP_3_P_120_BIT 24
+#define RV_PLIC_IP_3_P_121_BIT 25
+#define RV_PLIC_IP_3_P_122_BIT 26
+#define RV_PLIC_IP_3_P_123_BIT 27
+#define RV_PLIC_IP_3_P_124_BIT 28
+#define RV_PLIC_IP_3_P_125_BIT 29
+#define RV_PLIC_IP_3_P_126_BIT 30
+#define RV_PLIC_IP_3_P_127_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_4_REG_OFFSET 0x1010
+#define RV_PLIC_IP_4_REG_RESVAL 0x0
+#define RV_PLIC_IP_4_P_128_BIT 0
+#define RV_PLIC_IP_4_P_129_BIT 1
+#define RV_PLIC_IP_4_P_130_BIT 2
+#define RV_PLIC_IP_4_P_131_BIT 3
+#define RV_PLIC_IP_4_P_132_BIT 4
+#define RV_PLIC_IP_4_P_133_BIT 5
+#define RV_PLIC_IP_4_P_134_BIT 6
+#define RV_PLIC_IP_4_P_135_BIT 7
+#define RV_PLIC_IP_4_P_136_BIT 8
+#define RV_PLIC_IP_4_P_137_BIT 9
+#define RV_PLIC_IP_4_P_138_BIT 10
+#define RV_PLIC_IP_4_P_139_BIT 11
+#define RV_PLIC_IP_4_P_140_BIT 12
+#define RV_PLIC_IP_4_P_141_BIT 13
+#define RV_PLIC_IP_4_P_142_BIT 14
+#define RV_PLIC_IP_4_P_143_BIT 15
+#define RV_PLIC_IP_4_P_144_BIT 16
+#define RV_PLIC_IP_4_P_145_BIT 17
+#define RV_PLIC_IP_4_P_146_BIT 18
+#define RV_PLIC_IP_4_P_147_BIT 19
+#define RV_PLIC_IP_4_P_148_BIT 20
+#define RV_PLIC_IP_4_P_149_BIT 21
+#define RV_PLIC_IP_4_P_150_BIT 22
+#define RV_PLIC_IP_4_P_151_BIT 23
+#define RV_PLIC_IP_4_P_152_BIT 24
+#define RV_PLIC_IP_4_P_153_BIT 25
+#define RV_PLIC_IP_4_P_154_BIT 26
+#define RV_PLIC_IP_4_P_155_BIT 27
+#define RV_PLIC_IP_4_P_156_BIT 28
+#define RV_PLIC_IP_4_P_157_BIT 29
+#define RV_PLIC_IP_4_P_158_BIT 30
+#define RV_PLIC_IP_4_P_159_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_5_REG_OFFSET 0x1014
+#define RV_PLIC_IP_5_REG_RESVAL 0x0
+#define RV_PLIC_IP_5_P_160_BIT 0
+#define RV_PLIC_IP_5_P_161_BIT 1
+#define RV_PLIC_IP_5_P_162_BIT 2
+#define RV_PLIC_IP_5_P_163_BIT 3
+#define RV_PLIC_IP_5_P_164_BIT 4
+#define RV_PLIC_IP_5_P_165_BIT 5
+#define RV_PLIC_IP_5_P_166_BIT 6
+#define RV_PLIC_IP_5_P_167_BIT 7
+#define RV_PLIC_IP_5_P_168_BIT 8
+#define RV_PLIC_IP_5_P_169_BIT 9
+#define RV_PLIC_IP_5_P_170_BIT 10
+#define RV_PLIC_IP_5_P_171_BIT 11
+#define RV_PLIC_IP_5_P_172_BIT 12
+#define RV_PLIC_IP_5_P_173_BIT 13
+#define RV_PLIC_IP_5_P_174_BIT 14
+#define RV_PLIC_IP_5_P_175_BIT 15
+#define RV_PLIC_IP_5_P_176_BIT 16
+#define RV_PLIC_IP_5_P_177_BIT 17
+#define RV_PLIC_IP_5_P_178_BIT 18
+#define RV_PLIC_IP_5_P_179_BIT 19
+#define RV_PLIC_IP_5_P_180_BIT 20
+#define RV_PLIC_IP_5_P_181_BIT 21
+#define RV_PLIC_IP_5_P_182_BIT 22
+#define RV_PLIC_IP_5_P_183_BIT 23
+#define RV_PLIC_IP_5_P_184_BIT 24
+#define RV_PLIC_IP_5_P_185_BIT 25
+#define RV_PLIC_IP_5_P_186_BIT 26
+#define RV_PLIC_IP_5_P_187_BIT 27
+#define RV_PLIC_IP_5_P_188_BIT 28
+#define RV_PLIC_IP_5_P_189_BIT 29
+
+// Interrupt Enable for Target 0 (common parameters)
+#define RV_PLIC_IE0_E_FIELD_WIDTH 1
+#define RV_PLIC_IE0_MULTIREG_COUNT 6
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_0_REG_OFFSET 0x2000
+#define RV_PLIC_IE0_0_REG_RESVAL 0x0
+#define RV_PLIC_IE0_0_E_0_BIT 0
+#define RV_PLIC_IE0_0_E_1_BIT 1
+#define RV_PLIC_IE0_0_E_2_BIT 2
+#define RV_PLIC_IE0_0_E_3_BIT 3
+#define RV_PLIC_IE0_0_E_4_BIT 4
+#define RV_PLIC_IE0_0_E_5_BIT 5
+#define RV_PLIC_IE0_0_E_6_BIT 6
+#define RV_PLIC_IE0_0_E_7_BIT 7
+#define RV_PLIC_IE0_0_E_8_BIT 8
+#define RV_PLIC_IE0_0_E_9_BIT 9
+#define RV_PLIC_IE0_0_E_10_BIT 10
+#define RV_PLIC_IE0_0_E_11_BIT 11
+#define RV_PLIC_IE0_0_E_12_BIT 12
+#define RV_PLIC_IE0_0_E_13_BIT 13
+#define RV_PLIC_IE0_0_E_14_BIT 14
+#define RV_PLIC_IE0_0_E_15_BIT 15
+#define RV_PLIC_IE0_0_E_16_BIT 16
+#define RV_PLIC_IE0_0_E_17_BIT 17
+#define RV_PLIC_IE0_0_E_18_BIT 18
+#define RV_PLIC_IE0_0_E_19_BIT 19
+#define RV_PLIC_IE0_0_E_20_BIT 20
+#define RV_PLIC_IE0_0_E_21_BIT 21
+#define RV_PLIC_IE0_0_E_22_BIT 22
+#define RV_PLIC_IE0_0_E_23_BIT 23
+#define RV_PLIC_IE0_0_E_24_BIT 24
+#define RV_PLIC_IE0_0_E_25_BIT 25
+#define RV_PLIC_IE0_0_E_26_BIT 26
+#define RV_PLIC_IE0_0_E_27_BIT 27
+#define RV_PLIC_IE0_0_E_28_BIT 28
+#define RV_PLIC_IE0_0_E_29_BIT 29
+#define RV_PLIC_IE0_0_E_30_BIT 30
+#define RV_PLIC_IE0_0_E_31_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_1_REG_OFFSET 0x2004
+#define RV_PLIC_IE0_1_REG_RESVAL 0x0
+#define RV_PLIC_IE0_1_E_32_BIT 0
+#define RV_PLIC_IE0_1_E_33_BIT 1
+#define RV_PLIC_IE0_1_E_34_BIT 2
+#define RV_PLIC_IE0_1_E_35_BIT 3
+#define RV_PLIC_IE0_1_E_36_BIT 4
+#define RV_PLIC_IE0_1_E_37_BIT 5
+#define RV_PLIC_IE0_1_E_38_BIT 6
+#define RV_PLIC_IE0_1_E_39_BIT 7
+#define RV_PLIC_IE0_1_E_40_BIT 8
+#define RV_PLIC_IE0_1_E_41_BIT 9
+#define RV_PLIC_IE0_1_E_42_BIT 10
+#define RV_PLIC_IE0_1_E_43_BIT 11
+#define RV_PLIC_IE0_1_E_44_BIT 12
+#define RV_PLIC_IE0_1_E_45_BIT 13
+#define RV_PLIC_IE0_1_E_46_BIT 14
+#define RV_PLIC_IE0_1_E_47_BIT 15
+#define RV_PLIC_IE0_1_E_48_BIT 16
+#define RV_PLIC_IE0_1_E_49_BIT 17
+#define RV_PLIC_IE0_1_E_50_BIT 18
+#define RV_PLIC_IE0_1_E_51_BIT 19
+#define RV_PLIC_IE0_1_E_52_BIT 20
+#define RV_PLIC_IE0_1_E_53_BIT 21
+#define RV_PLIC_IE0_1_E_54_BIT 22
+#define RV_PLIC_IE0_1_E_55_BIT 23
+#define RV_PLIC_IE0_1_E_56_BIT 24
+#define RV_PLIC_IE0_1_E_57_BIT 25
+#define RV_PLIC_IE0_1_E_58_BIT 26
+#define RV_PLIC_IE0_1_E_59_BIT 27
+#define RV_PLIC_IE0_1_E_60_BIT 28
+#define RV_PLIC_IE0_1_E_61_BIT 29
+#define RV_PLIC_IE0_1_E_62_BIT 30
+#define RV_PLIC_IE0_1_E_63_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_2_REG_OFFSET 0x2008
+#define RV_PLIC_IE0_2_REG_RESVAL 0x0
+#define RV_PLIC_IE0_2_E_64_BIT 0
+#define RV_PLIC_IE0_2_E_65_BIT 1
+#define RV_PLIC_IE0_2_E_66_BIT 2
+#define RV_PLIC_IE0_2_E_67_BIT 3
+#define RV_PLIC_IE0_2_E_68_BIT 4
+#define RV_PLIC_IE0_2_E_69_BIT 5
+#define RV_PLIC_IE0_2_E_70_BIT 6
+#define RV_PLIC_IE0_2_E_71_BIT 7
+#define RV_PLIC_IE0_2_E_72_BIT 8
+#define RV_PLIC_IE0_2_E_73_BIT 9
+#define RV_PLIC_IE0_2_E_74_BIT 10
+#define RV_PLIC_IE0_2_E_75_BIT 11
+#define RV_PLIC_IE0_2_E_76_BIT 12
+#define RV_PLIC_IE0_2_E_77_BIT 13
+#define RV_PLIC_IE0_2_E_78_BIT 14
+#define RV_PLIC_IE0_2_E_79_BIT 15
+#define RV_PLIC_IE0_2_E_80_BIT 16
+#define RV_PLIC_IE0_2_E_81_BIT 17
+#define RV_PLIC_IE0_2_E_82_BIT 18
+#define RV_PLIC_IE0_2_E_83_BIT 19
+#define RV_PLIC_IE0_2_E_84_BIT 20
+#define RV_PLIC_IE0_2_E_85_BIT 21
+#define RV_PLIC_IE0_2_E_86_BIT 22
+#define RV_PLIC_IE0_2_E_87_BIT 23
+#define RV_PLIC_IE0_2_E_88_BIT 24
+#define RV_PLIC_IE0_2_E_89_BIT 25
+#define RV_PLIC_IE0_2_E_90_BIT 26
+#define RV_PLIC_IE0_2_E_91_BIT 27
+#define RV_PLIC_IE0_2_E_92_BIT 28
+#define RV_PLIC_IE0_2_E_93_BIT 29
+#define RV_PLIC_IE0_2_E_94_BIT 30
+#define RV_PLIC_IE0_2_E_95_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_3_REG_OFFSET 0x200c
+#define RV_PLIC_IE0_3_REG_RESVAL 0x0
+#define RV_PLIC_IE0_3_E_96_BIT 0
+#define RV_PLIC_IE0_3_E_97_BIT 1
+#define RV_PLIC_IE0_3_E_98_BIT 2
+#define RV_PLIC_IE0_3_E_99_BIT 3
+#define RV_PLIC_IE0_3_E_100_BIT 4
+#define RV_PLIC_IE0_3_E_101_BIT 5
+#define RV_PLIC_IE0_3_E_102_BIT 6
+#define RV_PLIC_IE0_3_E_103_BIT 7
+#define RV_PLIC_IE0_3_E_104_BIT 8
+#define RV_PLIC_IE0_3_E_105_BIT 9
+#define RV_PLIC_IE0_3_E_106_BIT 10
+#define RV_PLIC_IE0_3_E_107_BIT 11
+#define RV_PLIC_IE0_3_E_108_BIT 12
+#define RV_PLIC_IE0_3_E_109_BIT 13
+#define RV_PLIC_IE0_3_E_110_BIT 14
+#define RV_PLIC_IE0_3_E_111_BIT 15
+#define RV_PLIC_IE0_3_E_112_BIT 16
+#define RV_PLIC_IE0_3_E_113_BIT 17
+#define RV_PLIC_IE0_3_E_114_BIT 18
+#define RV_PLIC_IE0_3_E_115_BIT 19
+#define RV_PLIC_IE0_3_E_116_BIT 20
+#define RV_PLIC_IE0_3_E_117_BIT 21
+#define RV_PLIC_IE0_3_E_118_BIT 22
+#define RV_PLIC_IE0_3_E_119_BIT 23
+#define RV_PLIC_IE0_3_E_120_BIT 24
+#define RV_PLIC_IE0_3_E_121_BIT 25
+#define RV_PLIC_IE0_3_E_122_BIT 26
+#define RV_PLIC_IE0_3_E_123_BIT 27
+#define RV_PLIC_IE0_3_E_124_BIT 28
+#define RV_PLIC_IE0_3_E_125_BIT 29
+#define RV_PLIC_IE0_3_E_126_BIT 30
+#define RV_PLIC_IE0_3_E_127_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_4_REG_OFFSET 0x2010
+#define RV_PLIC_IE0_4_REG_RESVAL 0x0
+#define RV_PLIC_IE0_4_E_128_BIT 0
+#define RV_PLIC_IE0_4_E_129_BIT 1
+#define RV_PLIC_IE0_4_E_130_BIT 2
+#define RV_PLIC_IE0_4_E_131_BIT 3
+#define RV_PLIC_IE0_4_E_132_BIT 4
+#define RV_PLIC_IE0_4_E_133_BIT 5
+#define RV_PLIC_IE0_4_E_134_BIT 6
+#define RV_PLIC_IE0_4_E_135_BIT 7
+#define RV_PLIC_IE0_4_E_136_BIT 8
+#define RV_PLIC_IE0_4_E_137_BIT 9
+#define RV_PLIC_IE0_4_E_138_BIT 10
+#define RV_PLIC_IE0_4_E_139_BIT 11
+#define RV_PLIC_IE0_4_E_140_BIT 12
+#define RV_PLIC_IE0_4_E_141_BIT 13
+#define RV_PLIC_IE0_4_E_142_BIT 14
+#define RV_PLIC_IE0_4_E_143_BIT 15
+#define RV_PLIC_IE0_4_E_144_BIT 16
+#define RV_PLIC_IE0_4_E_145_BIT 17
+#define RV_PLIC_IE0_4_E_146_BIT 18
+#define RV_PLIC_IE0_4_E_147_BIT 19
+#define RV_PLIC_IE0_4_E_148_BIT 20
+#define RV_PLIC_IE0_4_E_149_BIT 21
+#define RV_PLIC_IE0_4_E_150_BIT 22
+#define RV_PLIC_IE0_4_E_151_BIT 23
+#define RV_PLIC_IE0_4_E_152_BIT 24
+#define RV_PLIC_IE0_4_E_153_BIT 25
+#define RV_PLIC_IE0_4_E_154_BIT 26
+#define RV_PLIC_IE0_4_E_155_BIT 27
+#define RV_PLIC_IE0_4_E_156_BIT 28
+#define RV_PLIC_IE0_4_E_157_BIT 29
+#define RV_PLIC_IE0_4_E_158_BIT 30
+#define RV_PLIC_IE0_4_E_159_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_5_REG_OFFSET 0x2014
+#define RV_PLIC_IE0_5_REG_RESVAL 0x0
+#define RV_PLIC_IE0_5_E_160_BIT 0
+#define RV_PLIC_IE0_5_E_161_BIT 1
+#define RV_PLIC_IE0_5_E_162_BIT 2
+#define RV_PLIC_IE0_5_E_163_BIT 3
+#define RV_PLIC_IE0_5_E_164_BIT 4
+#define RV_PLIC_IE0_5_E_165_BIT 5
+#define RV_PLIC_IE0_5_E_166_BIT 6
+#define RV_PLIC_IE0_5_E_167_BIT 7
+#define RV_PLIC_IE0_5_E_168_BIT 8
+#define RV_PLIC_IE0_5_E_169_BIT 9
+#define RV_PLIC_IE0_5_E_170_BIT 10
+#define RV_PLIC_IE0_5_E_171_BIT 11
+#define RV_PLIC_IE0_5_E_172_BIT 12
+#define RV_PLIC_IE0_5_E_173_BIT 13
+#define RV_PLIC_IE0_5_E_174_BIT 14
+#define RV_PLIC_IE0_5_E_175_BIT 15
+#define RV_PLIC_IE0_5_E_176_BIT 16
+#define RV_PLIC_IE0_5_E_177_BIT 17
+#define RV_PLIC_IE0_5_E_178_BIT 18
+#define RV_PLIC_IE0_5_E_179_BIT 19
+#define RV_PLIC_IE0_5_E_180_BIT 20
+#define RV_PLIC_IE0_5_E_181_BIT 21
+#define RV_PLIC_IE0_5_E_182_BIT 22
+#define RV_PLIC_IE0_5_E_183_BIT 23
+#define RV_PLIC_IE0_5_E_184_BIT 24
+#define RV_PLIC_IE0_5_E_185_BIT 25
+#define RV_PLIC_IE0_5_E_186_BIT 26
+#define RV_PLIC_IE0_5_E_187_BIT 27
+#define RV_PLIC_IE0_5_E_188_BIT 28
+#define RV_PLIC_IE0_5_E_189_BIT 29
+
+// Interrupt Enable for Target 1 (common parameters)
+#define RV_PLIC_IE1_E_FIELD_WIDTH 1
+#define RV_PLIC_IE1_MULTIREG_COUNT 6
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_0_REG_OFFSET 0x2100
+#define RV_PLIC_IE1_0_REG_RESVAL 0x0
+#define RV_PLIC_IE1_0_E_0_BIT 0
+#define RV_PLIC_IE1_0_E_1_BIT 1
+#define RV_PLIC_IE1_0_E_2_BIT 2
+#define RV_PLIC_IE1_0_E_3_BIT 3
+#define RV_PLIC_IE1_0_E_4_BIT 4
+#define RV_PLIC_IE1_0_E_5_BIT 5
+#define RV_PLIC_IE1_0_E_6_BIT 6
+#define RV_PLIC_IE1_0_E_7_BIT 7
+#define RV_PLIC_IE1_0_E_8_BIT 8
+#define RV_PLIC_IE1_0_E_9_BIT 9
+#define RV_PLIC_IE1_0_E_10_BIT 10
+#define RV_PLIC_IE1_0_E_11_BIT 11
+#define RV_PLIC_IE1_0_E_12_BIT 12
+#define RV_PLIC_IE1_0_E_13_BIT 13
+#define RV_PLIC_IE1_0_E_14_BIT 14
+#define RV_PLIC_IE1_0_E_15_BIT 15
+#define RV_PLIC_IE1_0_E_16_BIT 16
+#define RV_PLIC_IE1_0_E_17_BIT 17
+#define RV_PLIC_IE1_0_E_18_BIT 18
+#define RV_PLIC_IE1_0_E_19_BIT 19
+#define RV_PLIC_IE1_0_E_20_BIT 20
+#define RV_PLIC_IE1_0_E_21_BIT 21
+#define RV_PLIC_IE1_0_E_22_BIT 22
+#define RV_PLIC_IE1_0_E_23_BIT 23
+#define RV_PLIC_IE1_0_E_24_BIT 24
+#define RV_PLIC_IE1_0_E_25_BIT 25
+#define RV_PLIC_IE1_0_E_26_BIT 26
+#define RV_PLIC_IE1_0_E_27_BIT 27
+#define RV_PLIC_IE1_0_E_28_BIT 28
+#define RV_PLIC_IE1_0_E_29_BIT 29
+#define RV_PLIC_IE1_0_E_30_BIT 30
+#define RV_PLIC_IE1_0_E_31_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_1_REG_OFFSET 0x2104
+#define RV_PLIC_IE1_1_REG_RESVAL 0x0
+#define RV_PLIC_IE1_1_E_32_BIT 0
+#define RV_PLIC_IE1_1_E_33_BIT 1
+#define RV_PLIC_IE1_1_E_34_BIT 2
+#define RV_PLIC_IE1_1_E_35_BIT 3
+#define RV_PLIC_IE1_1_E_36_BIT 4
+#define RV_PLIC_IE1_1_E_37_BIT 5
+#define RV_PLIC_IE1_1_E_38_BIT 6
+#define RV_PLIC_IE1_1_E_39_BIT 7
+#define RV_PLIC_IE1_1_E_40_BIT 8
+#define RV_PLIC_IE1_1_E_41_BIT 9
+#define RV_PLIC_IE1_1_E_42_BIT 10
+#define RV_PLIC_IE1_1_E_43_BIT 11
+#define RV_PLIC_IE1_1_E_44_BIT 12
+#define RV_PLIC_IE1_1_E_45_BIT 13
+#define RV_PLIC_IE1_1_E_46_BIT 14
+#define RV_PLIC_IE1_1_E_47_BIT 15
+#define RV_PLIC_IE1_1_E_48_BIT 16
+#define RV_PLIC_IE1_1_E_49_BIT 17
+#define RV_PLIC_IE1_1_E_50_BIT 18
+#define RV_PLIC_IE1_1_E_51_BIT 19
+#define RV_PLIC_IE1_1_E_52_BIT 20
+#define RV_PLIC_IE1_1_E_53_BIT 21
+#define RV_PLIC_IE1_1_E_54_BIT 22
+#define RV_PLIC_IE1_1_E_55_BIT 23
+#define RV_PLIC_IE1_1_E_56_BIT 24
+#define RV_PLIC_IE1_1_E_57_BIT 25
+#define RV_PLIC_IE1_1_E_58_BIT 26
+#define RV_PLIC_IE1_1_E_59_BIT 27
+#define RV_PLIC_IE1_1_E_60_BIT 28
+#define RV_PLIC_IE1_1_E_61_BIT 29
+#define RV_PLIC_IE1_1_E_62_BIT 30
+#define RV_PLIC_IE1_1_E_63_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_2_REG_OFFSET 0x2108
+#define RV_PLIC_IE1_2_REG_RESVAL 0x0
+#define RV_PLIC_IE1_2_E_64_BIT 0
+#define RV_PLIC_IE1_2_E_65_BIT 1
+#define RV_PLIC_IE1_2_E_66_BIT 2
+#define RV_PLIC_IE1_2_E_67_BIT 3
+#define RV_PLIC_IE1_2_E_68_BIT 4
+#define RV_PLIC_IE1_2_E_69_BIT 5
+#define RV_PLIC_IE1_2_E_70_BIT 6
+#define RV_PLIC_IE1_2_E_71_BIT 7
+#define RV_PLIC_IE1_2_E_72_BIT 8
+#define RV_PLIC_IE1_2_E_73_BIT 9
+#define RV_PLIC_IE1_2_E_74_BIT 10
+#define RV_PLIC_IE1_2_E_75_BIT 11
+#define RV_PLIC_IE1_2_E_76_BIT 12
+#define RV_PLIC_IE1_2_E_77_BIT 13
+#define RV_PLIC_IE1_2_E_78_BIT 14
+#define RV_PLIC_IE1_2_E_79_BIT 15
+#define RV_PLIC_IE1_2_E_80_BIT 16
+#define RV_PLIC_IE1_2_E_81_BIT 17
+#define RV_PLIC_IE1_2_E_82_BIT 18
+#define RV_PLIC_IE1_2_E_83_BIT 19
+#define RV_PLIC_IE1_2_E_84_BIT 20
+#define RV_PLIC_IE1_2_E_85_BIT 21
+#define RV_PLIC_IE1_2_E_86_BIT 22
+#define RV_PLIC_IE1_2_E_87_BIT 23
+#define RV_PLIC_IE1_2_E_88_BIT 24
+#define RV_PLIC_IE1_2_E_89_BIT 25
+#define RV_PLIC_IE1_2_E_90_BIT 26
+#define RV_PLIC_IE1_2_E_91_BIT 27
+#define RV_PLIC_IE1_2_E_92_BIT 28
+#define RV_PLIC_IE1_2_E_93_BIT 29
+#define RV_PLIC_IE1_2_E_94_BIT 30
+#define RV_PLIC_IE1_2_E_95_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_3_REG_OFFSET 0x210c
+#define RV_PLIC_IE1_3_REG_RESVAL 0x0
+#define RV_PLIC_IE1_3_E_96_BIT 0
+#define RV_PLIC_IE1_3_E_97_BIT 1
+#define RV_PLIC_IE1_3_E_98_BIT 2
+#define RV_PLIC_IE1_3_E_99_BIT 3
+#define RV_PLIC_IE1_3_E_100_BIT 4
+#define RV_PLIC_IE1_3_E_101_BIT 5
+#define RV_PLIC_IE1_3_E_102_BIT 6
+#define RV_PLIC_IE1_3_E_103_BIT 7
+#define RV_PLIC_IE1_3_E_104_BIT 8
+#define RV_PLIC_IE1_3_E_105_BIT 9
+#define RV_PLIC_IE1_3_E_106_BIT 10
+#define RV_PLIC_IE1_3_E_107_BIT 11
+#define RV_PLIC_IE1_3_E_108_BIT 12
+#define RV_PLIC_IE1_3_E_109_BIT 13
+#define RV_PLIC_IE1_3_E_110_BIT 14
+#define RV_PLIC_IE1_3_E_111_BIT 15
+#define RV_PLIC_IE1_3_E_112_BIT 16
+#define RV_PLIC_IE1_3_E_113_BIT 17
+#define RV_PLIC_IE1_3_E_114_BIT 18
+#define RV_PLIC_IE1_3_E_115_BIT 19
+#define RV_PLIC_IE1_3_E_116_BIT 20
+#define RV_PLIC_IE1_3_E_117_BIT 21
+#define RV_PLIC_IE1_3_E_118_BIT 22
+#define RV_PLIC_IE1_3_E_119_BIT 23
+#define RV_PLIC_IE1_3_E_120_BIT 24
+#define RV_PLIC_IE1_3_E_121_BIT 25
+#define RV_PLIC_IE1_3_E_122_BIT 26
+#define RV_PLIC_IE1_3_E_123_BIT 27
+#define RV_PLIC_IE1_3_E_124_BIT 28
+#define RV_PLIC_IE1_3_E_125_BIT 29
+#define RV_PLIC_IE1_3_E_126_BIT 30
+#define RV_PLIC_IE1_3_E_127_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_4_REG_OFFSET 0x2110
+#define RV_PLIC_IE1_4_REG_RESVAL 0x0
+#define RV_PLIC_IE1_4_E_128_BIT 0
+#define RV_PLIC_IE1_4_E_129_BIT 1
+#define RV_PLIC_IE1_4_E_130_BIT 2
+#define RV_PLIC_IE1_4_E_131_BIT 3
+#define RV_PLIC_IE1_4_E_132_BIT 4
+#define RV_PLIC_IE1_4_E_133_BIT 5
+#define RV_PLIC_IE1_4_E_134_BIT 6
+#define RV_PLIC_IE1_4_E_135_BIT 7
+#define RV_PLIC_IE1_4_E_136_BIT 8
+#define RV_PLIC_IE1_4_E_137_BIT 9
+#define RV_PLIC_IE1_4_E_138_BIT 10
+#define RV_PLIC_IE1_4_E_139_BIT 11
+#define RV_PLIC_IE1_4_E_140_BIT 12
+#define RV_PLIC_IE1_4_E_141_BIT 13
+#define RV_PLIC_IE1_4_E_142_BIT 14
+#define RV_PLIC_IE1_4_E_143_BIT 15
+#define RV_PLIC_IE1_4_E_144_BIT 16
+#define RV_PLIC_IE1_4_E_145_BIT 17
+#define RV_PLIC_IE1_4_E_146_BIT 18
+#define RV_PLIC_IE1_4_E_147_BIT 19
+#define RV_PLIC_IE1_4_E_148_BIT 20
+#define RV_PLIC_IE1_4_E_149_BIT 21
+#define RV_PLIC_IE1_4_E_150_BIT 22
+#define RV_PLIC_IE1_4_E_151_BIT 23
+#define RV_PLIC_IE1_4_E_152_BIT 24
+#define RV_PLIC_IE1_4_E_153_BIT 25
+#define RV_PLIC_IE1_4_E_154_BIT 26
+#define RV_PLIC_IE1_4_E_155_BIT 27
+#define RV_PLIC_IE1_4_E_156_BIT 28
+#define RV_PLIC_IE1_4_E_157_BIT 29
+#define RV_PLIC_IE1_4_E_158_BIT 30
+#define RV_PLIC_IE1_4_E_159_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_5_REG_OFFSET 0x2114
+#define RV_PLIC_IE1_5_REG_RESVAL 0x0
+#define RV_PLIC_IE1_5_E_160_BIT 0
+#define RV_PLIC_IE1_5_E_161_BIT 1
+#define RV_PLIC_IE1_5_E_162_BIT 2
+#define RV_PLIC_IE1_5_E_163_BIT 3
+#define RV_PLIC_IE1_5_E_164_BIT 4
+#define RV_PLIC_IE1_5_E_165_BIT 5
+#define RV_PLIC_IE1_5_E_166_BIT 6
+#define RV_PLIC_IE1_5_E_167_BIT 7
+#define RV_PLIC_IE1_5_E_168_BIT 8
+#define RV_PLIC_IE1_5_E_169_BIT 9
+#define RV_PLIC_IE1_5_E_170_BIT 10
+#define RV_PLIC_IE1_5_E_171_BIT 11
+#define RV_PLIC_IE1_5_E_172_BIT 12
+#define RV_PLIC_IE1_5_E_173_BIT 13
+#define RV_PLIC_IE1_5_E_174_BIT 14
+#define RV_PLIC_IE1_5_E_175_BIT 15
+#define RV_PLIC_IE1_5_E_176_BIT 16
+#define RV_PLIC_IE1_5_E_177_BIT 17
+#define RV_PLIC_IE1_5_E_178_BIT 18
+#define RV_PLIC_IE1_5_E_179_BIT 19
+#define RV_PLIC_IE1_5_E_180_BIT 20
+#define RV_PLIC_IE1_5_E_181_BIT 21
+#define RV_PLIC_IE1_5_E_182_BIT 22
+#define RV_PLIC_IE1_5_E_183_BIT 23
+#define RV_PLIC_IE1_5_E_184_BIT 24
+#define RV_PLIC_IE1_5_E_185_BIT 25
+#define RV_PLIC_IE1_5_E_186_BIT 26
+#define RV_PLIC_IE1_5_E_187_BIT 27
+#define RV_PLIC_IE1_5_E_188_BIT 28
+#define RV_PLIC_IE1_5_E_189_BIT 29
+
+// Threshold of priority for Target 0
+#define RV_PLIC_THRESHOLD0_REG_OFFSET 0x200000
+#define RV_PLIC_THRESHOLD0_REG_RESVAL 0x0
+#define RV_PLIC_THRESHOLD0_THRESHOLD0_MASK 0x3
+#define RV_PLIC_THRESHOLD0_THRESHOLD0_OFFSET 0
+#define RV_PLIC_THRESHOLD0_THRESHOLD0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_THRESHOLD0_THRESHOLD0_MASK, .index = RV_PLIC_THRESHOLD0_THRESHOLD0_OFFSET })
+
+// Claim interrupt by read, complete interrupt by write for Target 0.
+#define RV_PLIC_CC0_REG_OFFSET 0x200004
+#define RV_PLIC_CC0_REG_RESVAL 0x0
+#define RV_PLIC_CC0_CC0_MASK 0xff
+#define RV_PLIC_CC0_CC0_OFFSET 0
+#define RV_PLIC_CC0_CC0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_CC0_CC0_MASK, .index = RV_PLIC_CC0_CC0_OFFSET })
+
+// Threshold of priority for Target 1
+#define RV_PLIC_THRESHOLD1_REG_OFFSET 0x201000
+#define RV_PLIC_THRESHOLD1_REG_RESVAL 0x0
+#define RV_PLIC_THRESHOLD1_THRESHOLD1_MASK 0x3
+#define RV_PLIC_THRESHOLD1_THRESHOLD1_OFFSET 0
+#define RV_PLIC_THRESHOLD1_THRESHOLD1_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_THRESHOLD1_THRESHOLD1_MASK, .index = RV_PLIC_THRESHOLD1_THRESHOLD1_OFFSET })
+
+// Claim interrupt by read, complete interrupt by write for Target 1.
+#define RV_PLIC_CC1_REG_OFFSET 0x201004
+#define RV_PLIC_CC1_REG_RESVAL 0x0
+#define RV_PLIC_CC1_CC1_MASK 0xff
+#define RV_PLIC_CC1_CC1_OFFSET 0
+#define RV_PLIC_CC1_CC1_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_CC1_CC1_MASK, .index = RV_PLIC_CC1_CC1_OFFSET })
+
+// msip for Hart 0.
+#define RV_PLIC_MSIP0_REG_OFFSET 0x4000000
+#define RV_PLIC_MSIP0_REG_RESVAL 0x0
+#define RV_PLIC_MSIP0_MSIP0_BIT 0
+
+// msip for Hart 1.
+#define RV_PLIC_MSIP1_REG_OFFSET 0x4000004
+#define RV_PLIC_MSIP1_REG_RESVAL 0x0
+#define RV_PLIC_MSIP1_MSIP1_BIT 0
+
+// Alert Test Register.
+#define RV_PLIC_ALERT_TEST_REG_OFFSET 0x4004000
+#define RV_PLIC_ALERT_TEST_REG_RESVAL 0x0
+#define RV_PLIC_ALERT_TEST_FATAL_FAULT_BIT 0
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _RV_PLIC_REG_DEFS_
+// End generated register defines for rv_plic
\ No newline at end of file
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/rv_plic_smc_regs.h b/hw/top_sencha/sparrow/hw/top_sencha/rv_plic_smc_regs.h
new file mode 100644
index 0000000..9b2d0cf
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/rv_plic_smc_regs.h
@@ -0,0 +1,555 @@
+// Generated register defines for rv_plic_smc
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _RV_PLIC_SMC_REG_DEFS_
+#define _RV_PLIC_SMC_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of interrupt sources
+#define RV_PLIC_SMC_PARAM_NUM_SRC 47
+
+// Number of Targets (Harts)
+#define RV_PLIC_SMC_PARAM_NUM_TARGET 1
+
+// Width of priority signals
+#define RV_PLIC_SMC_PARAM_PRIO_WIDTH 2
+
+// Number of alerts
+#define RV_PLIC_SMC_PARAM_NUM_ALERTS 1
+
+// Register width
+#define RV_PLIC_SMC_PARAM_REG_WIDTH 32
+
+// Interrupt Source 0 Priority
+#define RV_PLIC_SMC_PRIO0_REG_OFFSET 0x0
+#define RV_PLIC_SMC_PRIO0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO0_PRIO0_MASK 0x3
+#define RV_PLIC_SMC_PRIO0_PRIO0_OFFSET 0
+#define RV_PLIC_SMC_PRIO0_PRIO0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO0_PRIO0_MASK, .index = RV_PLIC_SMC_PRIO0_PRIO0_OFFSET })
+
+// Interrupt Source 1 Priority
+#define RV_PLIC_SMC_PRIO1_REG_OFFSET 0x4
+#define RV_PLIC_SMC_PRIO1_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO1_PRIO1_MASK 0x3
+#define RV_PLIC_SMC_PRIO1_PRIO1_OFFSET 0
+#define RV_PLIC_SMC_PRIO1_PRIO1_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO1_PRIO1_MASK, .index = RV_PLIC_SMC_PRIO1_PRIO1_OFFSET })
+
+// Interrupt Source 2 Priority
+#define RV_PLIC_SMC_PRIO2_REG_OFFSET 0x8
+#define RV_PLIC_SMC_PRIO2_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO2_PRIO2_MASK 0x3
+#define RV_PLIC_SMC_PRIO2_PRIO2_OFFSET 0
+#define RV_PLIC_SMC_PRIO2_PRIO2_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO2_PRIO2_MASK, .index = RV_PLIC_SMC_PRIO2_PRIO2_OFFSET })
+
+// Interrupt Source 3 Priority
+#define RV_PLIC_SMC_PRIO3_REG_OFFSET 0xc
+#define RV_PLIC_SMC_PRIO3_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO3_PRIO3_MASK 0x3
+#define RV_PLIC_SMC_PRIO3_PRIO3_OFFSET 0
+#define RV_PLIC_SMC_PRIO3_PRIO3_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO3_PRIO3_MASK, .index = RV_PLIC_SMC_PRIO3_PRIO3_OFFSET })
+
+// Interrupt Source 4 Priority
+#define RV_PLIC_SMC_PRIO4_REG_OFFSET 0x10
+#define RV_PLIC_SMC_PRIO4_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO4_PRIO4_MASK 0x3
+#define RV_PLIC_SMC_PRIO4_PRIO4_OFFSET 0
+#define RV_PLIC_SMC_PRIO4_PRIO4_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO4_PRIO4_MASK, .index = RV_PLIC_SMC_PRIO4_PRIO4_OFFSET })
+
+// Interrupt Source 5 Priority
+#define RV_PLIC_SMC_PRIO5_REG_OFFSET 0x14
+#define RV_PLIC_SMC_PRIO5_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO5_PRIO5_MASK 0x3
+#define RV_PLIC_SMC_PRIO5_PRIO5_OFFSET 0
+#define RV_PLIC_SMC_PRIO5_PRIO5_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO5_PRIO5_MASK, .index = RV_PLIC_SMC_PRIO5_PRIO5_OFFSET })
+
+// Interrupt Source 6 Priority
+#define RV_PLIC_SMC_PRIO6_REG_OFFSET 0x18
+#define RV_PLIC_SMC_PRIO6_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO6_PRIO6_MASK 0x3
+#define RV_PLIC_SMC_PRIO6_PRIO6_OFFSET 0
+#define RV_PLIC_SMC_PRIO6_PRIO6_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO6_PRIO6_MASK, .index = RV_PLIC_SMC_PRIO6_PRIO6_OFFSET })
+
+// Interrupt Source 7 Priority
+#define RV_PLIC_SMC_PRIO7_REG_OFFSET 0x1c
+#define RV_PLIC_SMC_PRIO7_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO7_PRIO7_MASK 0x3
+#define RV_PLIC_SMC_PRIO7_PRIO7_OFFSET 0
+#define RV_PLIC_SMC_PRIO7_PRIO7_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO7_PRIO7_MASK, .index = RV_PLIC_SMC_PRIO7_PRIO7_OFFSET })
+
+// Interrupt Source 8 Priority
+#define RV_PLIC_SMC_PRIO8_REG_OFFSET 0x20
+#define RV_PLIC_SMC_PRIO8_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO8_PRIO8_MASK 0x3
+#define RV_PLIC_SMC_PRIO8_PRIO8_OFFSET 0
+#define RV_PLIC_SMC_PRIO8_PRIO8_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO8_PRIO8_MASK, .index = RV_PLIC_SMC_PRIO8_PRIO8_OFFSET })
+
+// Interrupt Source 9 Priority
+#define RV_PLIC_SMC_PRIO9_REG_OFFSET 0x24
+#define RV_PLIC_SMC_PRIO9_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO9_PRIO9_MASK 0x3
+#define RV_PLIC_SMC_PRIO9_PRIO9_OFFSET 0
+#define RV_PLIC_SMC_PRIO9_PRIO9_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO9_PRIO9_MASK, .index = RV_PLIC_SMC_PRIO9_PRIO9_OFFSET })
+
+// Interrupt Source 10 Priority
+#define RV_PLIC_SMC_PRIO10_REG_OFFSET 0x28
+#define RV_PLIC_SMC_PRIO10_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO10_PRIO10_MASK 0x3
+#define RV_PLIC_SMC_PRIO10_PRIO10_OFFSET 0
+#define RV_PLIC_SMC_PRIO10_PRIO10_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO10_PRIO10_MASK, .index = RV_PLIC_SMC_PRIO10_PRIO10_OFFSET })
+
+// Interrupt Source 11 Priority
+#define RV_PLIC_SMC_PRIO11_REG_OFFSET 0x2c
+#define RV_PLIC_SMC_PRIO11_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO11_PRIO11_MASK 0x3
+#define RV_PLIC_SMC_PRIO11_PRIO11_OFFSET 0
+#define RV_PLIC_SMC_PRIO11_PRIO11_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO11_PRIO11_MASK, .index = RV_PLIC_SMC_PRIO11_PRIO11_OFFSET })
+
+// Interrupt Source 12 Priority
+#define RV_PLIC_SMC_PRIO12_REG_OFFSET 0x30
+#define RV_PLIC_SMC_PRIO12_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO12_PRIO12_MASK 0x3
+#define RV_PLIC_SMC_PRIO12_PRIO12_OFFSET 0
+#define RV_PLIC_SMC_PRIO12_PRIO12_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO12_PRIO12_MASK, .index = RV_PLIC_SMC_PRIO12_PRIO12_OFFSET })
+
+// Interrupt Source 13 Priority
+#define RV_PLIC_SMC_PRIO13_REG_OFFSET 0x34
+#define RV_PLIC_SMC_PRIO13_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO13_PRIO13_MASK 0x3
+#define RV_PLIC_SMC_PRIO13_PRIO13_OFFSET 0
+#define RV_PLIC_SMC_PRIO13_PRIO13_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO13_PRIO13_MASK, .index = RV_PLIC_SMC_PRIO13_PRIO13_OFFSET })
+
+// Interrupt Source 14 Priority
+#define RV_PLIC_SMC_PRIO14_REG_OFFSET 0x38
+#define RV_PLIC_SMC_PRIO14_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO14_PRIO14_MASK 0x3
+#define RV_PLIC_SMC_PRIO14_PRIO14_OFFSET 0
+#define RV_PLIC_SMC_PRIO14_PRIO14_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO14_PRIO14_MASK, .index = RV_PLIC_SMC_PRIO14_PRIO14_OFFSET })
+
+// Interrupt Source 15 Priority
+#define RV_PLIC_SMC_PRIO15_REG_OFFSET 0x3c
+#define RV_PLIC_SMC_PRIO15_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO15_PRIO15_MASK 0x3
+#define RV_PLIC_SMC_PRIO15_PRIO15_OFFSET 0
+#define RV_PLIC_SMC_PRIO15_PRIO15_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO15_PRIO15_MASK, .index = RV_PLIC_SMC_PRIO15_PRIO15_OFFSET })
+
+// Interrupt Source 16 Priority
+#define RV_PLIC_SMC_PRIO16_REG_OFFSET 0x40
+#define RV_PLIC_SMC_PRIO16_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO16_PRIO16_MASK 0x3
+#define RV_PLIC_SMC_PRIO16_PRIO16_OFFSET 0
+#define RV_PLIC_SMC_PRIO16_PRIO16_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO16_PRIO16_MASK, .index = RV_PLIC_SMC_PRIO16_PRIO16_OFFSET })
+
+// Interrupt Source 17 Priority
+#define RV_PLIC_SMC_PRIO17_REG_OFFSET 0x44
+#define RV_PLIC_SMC_PRIO17_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO17_PRIO17_MASK 0x3
+#define RV_PLIC_SMC_PRIO17_PRIO17_OFFSET 0
+#define RV_PLIC_SMC_PRIO17_PRIO17_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO17_PRIO17_MASK, .index = RV_PLIC_SMC_PRIO17_PRIO17_OFFSET })
+
+// Interrupt Source 18 Priority
+#define RV_PLIC_SMC_PRIO18_REG_OFFSET 0x48
+#define RV_PLIC_SMC_PRIO18_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO18_PRIO18_MASK 0x3
+#define RV_PLIC_SMC_PRIO18_PRIO18_OFFSET 0
+#define RV_PLIC_SMC_PRIO18_PRIO18_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO18_PRIO18_MASK, .index = RV_PLIC_SMC_PRIO18_PRIO18_OFFSET })
+
+// Interrupt Source 19 Priority
+#define RV_PLIC_SMC_PRIO19_REG_OFFSET 0x4c
+#define RV_PLIC_SMC_PRIO19_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO19_PRIO19_MASK 0x3
+#define RV_PLIC_SMC_PRIO19_PRIO19_OFFSET 0
+#define RV_PLIC_SMC_PRIO19_PRIO19_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO19_PRIO19_MASK, .index = RV_PLIC_SMC_PRIO19_PRIO19_OFFSET })
+
+// Interrupt Source 20 Priority
+#define RV_PLIC_SMC_PRIO20_REG_OFFSET 0x50
+#define RV_PLIC_SMC_PRIO20_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO20_PRIO20_MASK 0x3
+#define RV_PLIC_SMC_PRIO20_PRIO20_OFFSET 0
+#define RV_PLIC_SMC_PRIO20_PRIO20_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO20_PRIO20_MASK, .index = RV_PLIC_SMC_PRIO20_PRIO20_OFFSET })
+
+// Interrupt Source 21 Priority
+#define RV_PLIC_SMC_PRIO21_REG_OFFSET 0x54
+#define RV_PLIC_SMC_PRIO21_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO21_PRIO21_MASK 0x3
+#define RV_PLIC_SMC_PRIO21_PRIO21_OFFSET 0
+#define RV_PLIC_SMC_PRIO21_PRIO21_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO21_PRIO21_MASK, .index = RV_PLIC_SMC_PRIO21_PRIO21_OFFSET })
+
+// Interrupt Source 22 Priority
+#define RV_PLIC_SMC_PRIO22_REG_OFFSET 0x58
+#define RV_PLIC_SMC_PRIO22_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO22_PRIO22_MASK 0x3
+#define RV_PLIC_SMC_PRIO22_PRIO22_OFFSET 0
+#define RV_PLIC_SMC_PRIO22_PRIO22_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO22_PRIO22_MASK, .index = RV_PLIC_SMC_PRIO22_PRIO22_OFFSET })
+
+// Interrupt Source 23 Priority
+#define RV_PLIC_SMC_PRIO23_REG_OFFSET 0x5c
+#define RV_PLIC_SMC_PRIO23_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO23_PRIO23_MASK 0x3
+#define RV_PLIC_SMC_PRIO23_PRIO23_OFFSET 0
+#define RV_PLIC_SMC_PRIO23_PRIO23_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO23_PRIO23_MASK, .index = RV_PLIC_SMC_PRIO23_PRIO23_OFFSET })
+
+// Interrupt Source 24 Priority
+#define RV_PLIC_SMC_PRIO24_REG_OFFSET 0x60
+#define RV_PLIC_SMC_PRIO24_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO24_PRIO24_MASK 0x3
+#define RV_PLIC_SMC_PRIO24_PRIO24_OFFSET 0
+#define RV_PLIC_SMC_PRIO24_PRIO24_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO24_PRIO24_MASK, .index = RV_PLIC_SMC_PRIO24_PRIO24_OFFSET })
+
+// Interrupt Source 25 Priority
+#define RV_PLIC_SMC_PRIO25_REG_OFFSET 0x64
+#define RV_PLIC_SMC_PRIO25_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO25_PRIO25_MASK 0x3
+#define RV_PLIC_SMC_PRIO25_PRIO25_OFFSET 0
+#define RV_PLIC_SMC_PRIO25_PRIO25_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO25_PRIO25_MASK, .index = RV_PLIC_SMC_PRIO25_PRIO25_OFFSET })
+
+// Interrupt Source 26 Priority
+#define RV_PLIC_SMC_PRIO26_REG_OFFSET 0x68
+#define RV_PLIC_SMC_PRIO26_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO26_PRIO26_MASK 0x3
+#define RV_PLIC_SMC_PRIO26_PRIO26_OFFSET 0
+#define RV_PLIC_SMC_PRIO26_PRIO26_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO26_PRIO26_MASK, .index = RV_PLIC_SMC_PRIO26_PRIO26_OFFSET })
+
+// Interrupt Source 27 Priority
+#define RV_PLIC_SMC_PRIO27_REG_OFFSET 0x6c
+#define RV_PLIC_SMC_PRIO27_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO27_PRIO27_MASK 0x3
+#define RV_PLIC_SMC_PRIO27_PRIO27_OFFSET 0
+#define RV_PLIC_SMC_PRIO27_PRIO27_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO27_PRIO27_MASK, .index = RV_PLIC_SMC_PRIO27_PRIO27_OFFSET })
+
+// Interrupt Source 28 Priority
+#define RV_PLIC_SMC_PRIO28_REG_OFFSET 0x70
+#define RV_PLIC_SMC_PRIO28_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO28_PRIO28_MASK 0x3
+#define RV_PLIC_SMC_PRIO28_PRIO28_OFFSET 0
+#define RV_PLIC_SMC_PRIO28_PRIO28_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO28_PRIO28_MASK, .index = RV_PLIC_SMC_PRIO28_PRIO28_OFFSET })
+
+// Interrupt Source 29 Priority
+#define RV_PLIC_SMC_PRIO29_REG_OFFSET 0x74
+#define RV_PLIC_SMC_PRIO29_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO29_PRIO29_MASK 0x3
+#define RV_PLIC_SMC_PRIO29_PRIO29_OFFSET 0
+#define RV_PLIC_SMC_PRIO29_PRIO29_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO29_PRIO29_MASK, .index = RV_PLIC_SMC_PRIO29_PRIO29_OFFSET })
+
+// Interrupt Source 30 Priority
+#define RV_PLIC_SMC_PRIO30_REG_OFFSET 0x78
+#define RV_PLIC_SMC_PRIO30_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO30_PRIO30_MASK 0x3
+#define RV_PLIC_SMC_PRIO30_PRIO30_OFFSET 0
+#define RV_PLIC_SMC_PRIO30_PRIO30_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO30_PRIO30_MASK, .index = RV_PLIC_SMC_PRIO30_PRIO30_OFFSET })
+
+// Interrupt Source 31 Priority
+#define RV_PLIC_SMC_PRIO31_REG_OFFSET 0x7c
+#define RV_PLIC_SMC_PRIO31_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO31_PRIO31_MASK 0x3
+#define RV_PLIC_SMC_PRIO31_PRIO31_OFFSET 0
+#define RV_PLIC_SMC_PRIO31_PRIO31_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO31_PRIO31_MASK, .index = RV_PLIC_SMC_PRIO31_PRIO31_OFFSET })
+
+// Interrupt Source 32 Priority
+#define RV_PLIC_SMC_PRIO32_REG_OFFSET 0x80
+#define RV_PLIC_SMC_PRIO32_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO32_PRIO32_MASK 0x3
+#define RV_PLIC_SMC_PRIO32_PRIO32_OFFSET 0
+#define RV_PLIC_SMC_PRIO32_PRIO32_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO32_PRIO32_MASK, .index = RV_PLIC_SMC_PRIO32_PRIO32_OFFSET })
+
+// Interrupt Source 33 Priority
+#define RV_PLIC_SMC_PRIO33_REG_OFFSET 0x84
+#define RV_PLIC_SMC_PRIO33_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO33_PRIO33_MASK 0x3
+#define RV_PLIC_SMC_PRIO33_PRIO33_OFFSET 0
+#define RV_PLIC_SMC_PRIO33_PRIO33_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO33_PRIO33_MASK, .index = RV_PLIC_SMC_PRIO33_PRIO33_OFFSET })
+
+// Interrupt Source 34 Priority
+#define RV_PLIC_SMC_PRIO34_REG_OFFSET 0x88
+#define RV_PLIC_SMC_PRIO34_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO34_PRIO34_MASK 0x3
+#define RV_PLIC_SMC_PRIO34_PRIO34_OFFSET 0
+#define RV_PLIC_SMC_PRIO34_PRIO34_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO34_PRIO34_MASK, .index = RV_PLIC_SMC_PRIO34_PRIO34_OFFSET })
+
+// Interrupt Source 35 Priority
+#define RV_PLIC_SMC_PRIO35_REG_OFFSET 0x8c
+#define RV_PLIC_SMC_PRIO35_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO35_PRIO35_MASK 0x3
+#define RV_PLIC_SMC_PRIO35_PRIO35_OFFSET 0
+#define RV_PLIC_SMC_PRIO35_PRIO35_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO35_PRIO35_MASK, .index = RV_PLIC_SMC_PRIO35_PRIO35_OFFSET })
+
+// Interrupt Source 36 Priority
+#define RV_PLIC_SMC_PRIO36_REG_OFFSET 0x90
+#define RV_PLIC_SMC_PRIO36_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO36_PRIO36_MASK 0x3
+#define RV_PLIC_SMC_PRIO36_PRIO36_OFFSET 0
+#define RV_PLIC_SMC_PRIO36_PRIO36_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO36_PRIO36_MASK, .index = RV_PLIC_SMC_PRIO36_PRIO36_OFFSET })
+
+// Interrupt Source 37 Priority
+#define RV_PLIC_SMC_PRIO37_REG_OFFSET 0x94
+#define RV_PLIC_SMC_PRIO37_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO37_PRIO37_MASK 0x3
+#define RV_PLIC_SMC_PRIO37_PRIO37_OFFSET 0
+#define RV_PLIC_SMC_PRIO37_PRIO37_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO37_PRIO37_MASK, .index = RV_PLIC_SMC_PRIO37_PRIO37_OFFSET })
+
+// Interrupt Source 38 Priority
+#define RV_PLIC_SMC_PRIO38_REG_OFFSET 0x98
+#define RV_PLIC_SMC_PRIO38_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO38_PRIO38_MASK 0x3
+#define RV_PLIC_SMC_PRIO38_PRIO38_OFFSET 0
+#define RV_PLIC_SMC_PRIO38_PRIO38_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO38_PRIO38_MASK, .index = RV_PLIC_SMC_PRIO38_PRIO38_OFFSET })
+
+// Interrupt Source 39 Priority
+#define RV_PLIC_SMC_PRIO39_REG_OFFSET 0x9c
+#define RV_PLIC_SMC_PRIO39_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO39_PRIO39_MASK 0x3
+#define RV_PLIC_SMC_PRIO39_PRIO39_OFFSET 0
+#define RV_PLIC_SMC_PRIO39_PRIO39_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO39_PRIO39_MASK, .index = RV_PLIC_SMC_PRIO39_PRIO39_OFFSET })
+
+// Interrupt Source 40 Priority
+#define RV_PLIC_SMC_PRIO40_REG_OFFSET 0xa0
+#define RV_PLIC_SMC_PRIO40_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO40_PRIO40_MASK 0x3
+#define RV_PLIC_SMC_PRIO40_PRIO40_OFFSET 0
+#define RV_PLIC_SMC_PRIO40_PRIO40_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO40_PRIO40_MASK, .index = RV_PLIC_SMC_PRIO40_PRIO40_OFFSET })
+
+// Interrupt Source 41 Priority
+#define RV_PLIC_SMC_PRIO41_REG_OFFSET 0xa4
+#define RV_PLIC_SMC_PRIO41_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO41_PRIO41_MASK 0x3
+#define RV_PLIC_SMC_PRIO41_PRIO41_OFFSET 0
+#define RV_PLIC_SMC_PRIO41_PRIO41_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO41_PRIO41_MASK, .index = RV_PLIC_SMC_PRIO41_PRIO41_OFFSET })
+
+// Interrupt Source 42 Priority
+#define RV_PLIC_SMC_PRIO42_REG_OFFSET 0xa8
+#define RV_PLIC_SMC_PRIO42_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO42_PRIO42_MASK 0x3
+#define RV_PLIC_SMC_PRIO42_PRIO42_OFFSET 0
+#define RV_PLIC_SMC_PRIO42_PRIO42_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO42_PRIO42_MASK, .index = RV_PLIC_SMC_PRIO42_PRIO42_OFFSET })
+
+// Interrupt Source 43 Priority
+#define RV_PLIC_SMC_PRIO43_REG_OFFSET 0xac
+#define RV_PLIC_SMC_PRIO43_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO43_PRIO43_MASK 0x3
+#define RV_PLIC_SMC_PRIO43_PRIO43_OFFSET 0
+#define RV_PLIC_SMC_PRIO43_PRIO43_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO43_PRIO43_MASK, .index = RV_PLIC_SMC_PRIO43_PRIO43_OFFSET })
+
+// Interrupt Source 44 Priority
+#define RV_PLIC_SMC_PRIO44_REG_OFFSET 0xb0
+#define RV_PLIC_SMC_PRIO44_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO44_PRIO44_MASK 0x3
+#define RV_PLIC_SMC_PRIO44_PRIO44_OFFSET 0
+#define RV_PLIC_SMC_PRIO44_PRIO44_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO44_PRIO44_MASK, .index = RV_PLIC_SMC_PRIO44_PRIO44_OFFSET })
+
+// Interrupt Source 45 Priority
+#define RV_PLIC_SMC_PRIO45_REG_OFFSET 0xb4
+#define RV_PLIC_SMC_PRIO45_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO45_PRIO45_MASK 0x3
+#define RV_PLIC_SMC_PRIO45_PRIO45_OFFSET 0
+#define RV_PLIC_SMC_PRIO45_PRIO45_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO45_PRIO45_MASK, .index = RV_PLIC_SMC_PRIO45_PRIO45_OFFSET })
+
+// Interrupt Source 46 Priority
+#define RV_PLIC_SMC_PRIO46_REG_OFFSET 0xb8
+#define RV_PLIC_SMC_PRIO46_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO46_PRIO46_MASK 0x3
+#define RV_PLIC_SMC_PRIO46_PRIO46_OFFSET 0
+#define RV_PLIC_SMC_PRIO46_PRIO46_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO46_PRIO46_MASK, .index = RV_PLIC_SMC_PRIO46_PRIO46_OFFSET })
+
+// Interrupt Pending (common parameters)
+#define RV_PLIC_SMC_IP_P_FIELD_WIDTH 1
+#define RV_PLIC_SMC_IP_MULTIREG_COUNT 2
+
+// Interrupt Pending
+#define RV_PLIC_SMC_IP_0_REG_OFFSET 0x1000
+#define RV_PLIC_SMC_IP_0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_IP_0_P_0_BIT 0
+#define RV_PLIC_SMC_IP_0_P_1_BIT 1
+#define RV_PLIC_SMC_IP_0_P_2_BIT 2
+#define RV_PLIC_SMC_IP_0_P_3_BIT 3
+#define RV_PLIC_SMC_IP_0_P_4_BIT 4
+#define RV_PLIC_SMC_IP_0_P_5_BIT 5
+#define RV_PLIC_SMC_IP_0_P_6_BIT 6
+#define RV_PLIC_SMC_IP_0_P_7_BIT 7
+#define RV_PLIC_SMC_IP_0_P_8_BIT 8
+#define RV_PLIC_SMC_IP_0_P_9_BIT 9
+#define RV_PLIC_SMC_IP_0_P_10_BIT 10
+#define RV_PLIC_SMC_IP_0_P_11_BIT 11
+#define RV_PLIC_SMC_IP_0_P_12_BIT 12
+#define RV_PLIC_SMC_IP_0_P_13_BIT 13
+#define RV_PLIC_SMC_IP_0_P_14_BIT 14
+#define RV_PLIC_SMC_IP_0_P_15_BIT 15
+#define RV_PLIC_SMC_IP_0_P_16_BIT 16
+#define RV_PLIC_SMC_IP_0_P_17_BIT 17
+#define RV_PLIC_SMC_IP_0_P_18_BIT 18
+#define RV_PLIC_SMC_IP_0_P_19_BIT 19
+#define RV_PLIC_SMC_IP_0_P_20_BIT 20
+#define RV_PLIC_SMC_IP_0_P_21_BIT 21
+#define RV_PLIC_SMC_IP_0_P_22_BIT 22
+#define RV_PLIC_SMC_IP_0_P_23_BIT 23
+#define RV_PLIC_SMC_IP_0_P_24_BIT 24
+#define RV_PLIC_SMC_IP_0_P_25_BIT 25
+#define RV_PLIC_SMC_IP_0_P_26_BIT 26
+#define RV_PLIC_SMC_IP_0_P_27_BIT 27
+#define RV_PLIC_SMC_IP_0_P_28_BIT 28
+#define RV_PLIC_SMC_IP_0_P_29_BIT 29
+#define RV_PLIC_SMC_IP_0_P_30_BIT 30
+#define RV_PLIC_SMC_IP_0_P_31_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_SMC_IP_1_REG_OFFSET 0x1004
+#define RV_PLIC_SMC_IP_1_REG_RESVAL 0x0
+#define RV_PLIC_SMC_IP_1_P_32_BIT 0
+#define RV_PLIC_SMC_IP_1_P_33_BIT 1
+#define RV_PLIC_SMC_IP_1_P_34_BIT 2
+#define RV_PLIC_SMC_IP_1_P_35_BIT 3
+#define RV_PLIC_SMC_IP_1_P_36_BIT 4
+#define RV_PLIC_SMC_IP_1_P_37_BIT 5
+#define RV_PLIC_SMC_IP_1_P_38_BIT 6
+#define RV_PLIC_SMC_IP_1_P_39_BIT 7
+#define RV_PLIC_SMC_IP_1_P_40_BIT 8
+#define RV_PLIC_SMC_IP_1_P_41_BIT 9
+#define RV_PLIC_SMC_IP_1_P_42_BIT 10
+#define RV_PLIC_SMC_IP_1_P_43_BIT 11
+#define RV_PLIC_SMC_IP_1_P_44_BIT 12
+#define RV_PLIC_SMC_IP_1_P_45_BIT 13
+#define RV_PLIC_SMC_IP_1_P_46_BIT 14
+
+// Interrupt Enable for Target 0 (common parameters)
+#define RV_PLIC_SMC_IE0_E_FIELD_WIDTH 1
+#define RV_PLIC_SMC_IE0_MULTIREG_COUNT 2
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_SMC_IE0_0_REG_OFFSET 0x2000
+#define RV_PLIC_SMC_IE0_0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_IE0_0_E_0_BIT 0
+#define RV_PLIC_SMC_IE0_0_E_1_BIT 1
+#define RV_PLIC_SMC_IE0_0_E_2_BIT 2
+#define RV_PLIC_SMC_IE0_0_E_3_BIT 3
+#define RV_PLIC_SMC_IE0_0_E_4_BIT 4
+#define RV_PLIC_SMC_IE0_0_E_5_BIT 5
+#define RV_PLIC_SMC_IE0_0_E_6_BIT 6
+#define RV_PLIC_SMC_IE0_0_E_7_BIT 7
+#define RV_PLIC_SMC_IE0_0_E_8_BIT 8
+#define RV_PLIC_SMC_IE0_0_E_9_BIT 9
+#define RV_PLIC_SMC_IE0_0_E_10_BIT 10
+#define RV_PLIC_SMC_IE0_0_E_11_BIT 11
+#define RV_PLIC_SMC_IE0_0_E_12_BIT 12
+#define RV_PLIC_SMC_IE0_0_E_13_BIT 13
+#define RV_PLIC_SMC_IE0_0_E_14_BIT 14
+#define RV_PLIC_SMC_IE0_0_E_15_BIT 15
+#define RV_PLIC_SMC_IE0_0_E_16_BIT 16
+#define RV_PLIC_SMC_IE0_0_E_17_BIT 17
+#define RV_PLIC_SMC_IE0_0_E_18_BIT 18
+#define RV_PLIC_SMC_IE0_0_E_19_BIT 19
+#define RV_PLIC_SMC_IE0_0_E_20_BIT 20
+#define RV_PLIC_SMC_IE0_0_E_21_BIT 21
+#define RV_PLIC_SMC_IE0_0_E_22_BIT 22
+#define RV_PLIC_SMC_IE0_0_E_23_BIT 23
+#define RV_PLIC_SMC_IE0_0_E_24_BIT 24
+#define RV_PLIC_SMC_IE0_0_E_25_BIT 25
+#define RV_PLIC_SMC_IE0_0_E_26_BIT 26
+#define RV_PLIC_SMC_IE0_0_E_27_BIT 27
+#define RV_PLIC_SMC_IE0_0_E_28_BIT 28
+#define RV_PLIC_SMC_IE0_0_E_29_BIT 29
+#define RV_PLIC_SMC_IE0_0_E_30_BIT 30
+#define RV_PLIC_SMC_IE0_0_E_31_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_SMC_IE0_1_REG_OFFSET 0x2004
+#define RV_PLIC_SMC_IE0_1_REG_RESVAL 0x0
+#define RV_PLIC_SMC_IE0_1_E_32_BIT 0
+#define RV_PLIC_SMC_IE0_1_E_33_BIT 1
+#define RV_PLIC_SMC_IE0_1_E_34_BIT 2
+#define RV_PLIC_SMC_IE0_1_E_35_BIT 3
+#define RV_PLIC_SMC_IE0_1_E_36_BIT 4
+#define RV_PLIC_SMC_IE0_1_E_37_BIT 5
+#define RV_PLIC_SMC_IE0_1_E_38_BIT 6
+#define RV_PLIC_SMC_IE0_1_E_39_BIT 7
+#define RV_PLIC_SMC_IE0_1_E_40_BIT 8
+#define RV_PLIC_SMC_IE0_1_E_41_BIT 9
+#define RV_PLIC_SMC_IE0_1_E_42_BIT 10
+#define RV_PLIC_SMC_IE0_1_E_43_BIT 11
+#define RV_PLIC_SMC_IE0_1_E_44_BIT 12
+#define RV_PLIC_SMC_IE0_1_E_45_BIT 13
+#define RV_PLIC_SMC_IE0_1_E_46_BIT 14
+
+// Threshold of priority for Target 0
+#define RV_PLIC_SMC_THRESHOLD0_REG_OFFSET 0x200000
+#define RV_PLIC_SMC_THRESHOLD0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_MASK 0x3
+#define RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_OFFSET 0
+#define RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_MASK, .index = RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_OFFSET })
+
+// Claim interrupt by read, complete interrupt by write for Target 0.
+#define RV_PLIC_SMC_CC0_REG_OFFSET 0x200004
+#define RV_PLIC_SMC_CC0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_CC0_CC0_MASK 0x3f
+#define RV_PLIC_SMC_CC0_CC0_OFFSET 0
+#define RV_PLIC_SMC_CC0_CC0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_CC0_CC0_MASK, .index = RV_PLIC_SMC_CC0_CC0_OFFSET })
+
+// msip for Hart 0.
+#define RV_PLIC_SMC_MSIP0_REG_OFFSET 0x4000000
+#define RV_PLIC_SMC_MSIP0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_MSIP0_MSIP0_BIT 0
+
+// Alert Test Register.
+#define RV_PLIC_SMC_ALERT_TEST_REG_OFFSET 0x4004000
+#define RV_PLIC_SMC_ALERT_TEST_REG_RESVAL 0x0
+#define RV_PLIC_SMC_ALERT_TEST_FATAL_FAULT_BIT 0
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _RV_PLIC_SMC_REG_DEFS_
+// End generated register defines for rv_plic_smc
\ No newline at end of file
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/BUILD b/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/BUILD
new file mode 100644
index 0000000..5502e84
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/BUILD
@@ -0,0 +1,12 @@
+# Copyright 2022 Google Inc. All Rights Reserved.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+load("@lowrisc_opentitan//rules:linker.bzl", "ld_library")
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/top_sencha.c b/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/top_sencha.c
new file mode 100644
index 0000000..5e45082
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/top_sencha.c
@@ -0,0 +1,343 @@
+// Copyright 2022 Google Inc.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "hw/top_sencha/sw/autogen/top_sencha.h"
+
+/**
+ * PLIC Interrupt Source to Peripheral Map
+ *
+ * This array is a mapping from `top_sencha_plic_irq_id_t` to
+ * `top_sencha_plic_peripheral_t`.
+ */
+const top_sencha_plic_peripheral_t
+ top_sencha_plic_interrupt_for_peripheral[190] = {
+ [kTopMatchaPlicIrqIdNone] = kTopMatchaPlicPeripheralUnknown,
+ [kTopMatchaPlicIrqIdUart0TxWatermark] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxWatermark] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0TxEmpty] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxOverflow] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxFrameErr] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxBreakErr] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxTimeout] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxParityErr] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart1TxWatermark] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxWatermark] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1TxEmpty] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxOverflow] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxFrameErr] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxBreakErr] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxTimeout] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxParityErr] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart2TxWatermark] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxWatermark] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2TxEmpty] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxOverflow] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxFrameErr] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxBreakErr] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxTimeout] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxParityErr] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart3TxWatermark] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxWatermark] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3TxEmpty] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxOverflow] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxFrameErr] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxBreakErr] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxTimeout] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxParityErr] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdGpioGpio0] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio1] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio2] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio3] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio4] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio5] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio6] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio7] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio8] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio9] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio10] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio11] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio12] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio13] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio14] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio15] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio16] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio17] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio18] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio19] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio20] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio21] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio22] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio23] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio24] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio25] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio26] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio27] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio28] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio29] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio30] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio31] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericRxFull] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericRxWatermark] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericTxWatermark] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericRxError] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericRxOverflow] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericTxUnderflow] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceUploadPayloadNotEmpty] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceUploadPayloadOverflow] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceReadbufWatermark] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceReadbufFlip] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceTpmHeaderNotEmpty] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdI2c0FmtThreshold] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0RxThreshold] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0FmtOverflow] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0RxOverflow] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0Nak] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0SclInterference] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0SdaInterference] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0StretchTimeout] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0SdaUnstable] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0CmdComplete] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0TxStretch] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0TxOverflow] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0AcqFull] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0UnexpStop] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0HostTimeout] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c1FmtThreshold] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1RxThreshold] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1FmtOverflow] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1RxOverflow] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1Nak] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1SclInterference] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1SdaInterference] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1StretchTimeout] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1SdaUnstable] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1CmdComplete] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1TxStretch] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1TxOverflow] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1AcqFull] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1UnexpStop] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1HostTimeout] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c2FmtThreshold] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2RxThreshold] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2FmtOverflow] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2RxOverflow] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2Nak] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2SclInterference] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2SdaInterference] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2StretchTimeout] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2SdaUnstable] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2CmdComplete] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2TxStretch] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2TxOverflow] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2AcqFull] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2UnexpStop] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2HostTimeout] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdPattgenDoneCh0] = kTopMatchaPlicPeripheralPattgen,
+ [kTopMatchaPlicIrqIdPattgenDoneCh1] = kTopMatchaPlicPeripheralPattgen,
+ [kTopMatchaPlicIrqIdRvTimerTimerExpiredHart0Timer0] = kTopMatchaPlicPeripheralRvTimer,
+ [kTopMatchaPlicIrqIdOtpCtrlOtpOperationDone] = kTopMatchaPlicPeripheralOtpCtrl,
+ [kTopMatchaPlicIrqIdOtpCtrlOtpError] = kTopMatchaPlicPeripheralOtpCtrl,
+ [kTopMatchaPlicIrqIdAlertHandlerClassa] = kTopMatchaPlicPeripheralAlertHandler,
+ [kTopMatchaPlicIrqIdAlertHandlerClassb] = kTopMatchaPlicPeripheralAlertHandler,
+ [kTopMatchaPlicIrqIdAlertHandlerClassc] = kTopMatchaPlicPeripheralAlertHandler,
+ [kTopMatchaPlicIrqIdAlertHandlerClassd] = kTopMatchaPlicPeripheralAlertHandler,
+ [kTopMatchaPlicIrqIdSpiHost0Error] = kTopMatchaPlicPeripheralSpiHost0,
+ [kTopMatchaPlicIrqIdSpiHost0SpiEvent] = kTopMatchaPlicPeripheralSpiHost0,
+ [kTopMatchaPlicIrqIdSpiHost1Error] = kTopMatchaPlicPeripheralSpiHost1,
+ [kTopMatchaPlicIrqIdSpiHost1SpiEvent] = kTopMatchaPlicPeripheralSpiHost1,
+ [kTopMatchaPlicIrqIdUsbdevPktReceived] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevPktSent] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevDisconnected] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevHostLost] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkReset] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkSuspend] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkResume] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevAvEmpty] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevRxFull] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevAvOverflow] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkInErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevRxCrcErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevRxPidErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevRxBitstuffErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevFrame] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevPowered] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkOutErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdPwrmgrAonWakeup] = kTopMatchaPlicPeripheralPwrmgrAon,
+ [kTopMatchaPlicIrqIdSysrstCtrlAonEventDetected] = kTopMatchaPlicPeripheralSysrstCtrlAon,
+ [kTopMatchaPlicIrqIdAdcCtrlAonMatchDone] = kTopMatchaPlicPeripheralAdcCtrlAon,
+ [kTopMatchaPlicIrqIdAonTimerAonWkupTimerExpired] = kTopMatchaPlicPeripheralAonTimerAon,
+ [kTopMatchaPlicIrqIdAonTimerAonWdogTimerBark] = kTopMatchaPlicPeripheralAonTimerAon,
+ [kTopMatchaPlicIrqIdSensorCtrlIoStatusChange] = kTopMatchaPlicPeripheralSensorCtrl,
+ [kTopMatchaPlicIrqIdSensorCtrlInitStatusChange] = kTopMatchaPlicPeripheralSensorCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlProgEmpty] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlProgLvl] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlRdFull] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlRdLvl] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlOpDone] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlCorrErr] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdHmacHmacDone] = kTopMatchaPlicPeripheralHmac,
+ [kTopMatchaPlicIrqIdHmacFifoEmpty] = kTopMatchaPlicPeripheralHmac,
+ [kTopMatchaPlicIrqIdHmacHmacErr] = kTopMatchaPlicPeripheralHmac,
+ [kTopMatchaPlicIrqIdKmacKmacDone] = kTopMatchaPlicPeripheralKmac,
+ [kTopMatchaPlicIrqIdKmacFifoEmpty] = kTopMatchaPlicPeripheralKmac,
+ [kTopMatchaPlicIrqIdKmacKmacErr] = kTopMatchaPlicPeripheralKmac,
+ [kTopMatchaPlicIrqIdOtbnDone] = kTopMatchaPlicPeripheralOtbn,
+ [kTopMatchaPlicIrqIdKeymgrOpDone] = kTopMatchaPlicPeripheralKeymgr,
+ [kTopMatchaPlicIrqIdCsrngCsCmdReqDone] = kTopMatchaPlicPeripheralCsrng,
+ [kTopMatchaPlicIrqIdCsrngCsEntropyReq] = kTopMatchaPlicPeripheralCsrng,
+ [kTopMatchaPlicIrqIdCsrngCsHwInstExc] = kTopMatchaPlicPeripheralCsrng,
+ [kTopMatchaPlicIrqIdCsrngCsFatalErr] = kTopMatchaPlicPeripheralCsrng,
+ [kTopMatchaPlicIrqIdEntropySrcEsEntropyValid] = kTopMatchaPlicPeripheralEntropySrc,
+ [kTopMatchaPlicIrqIdEntropySrcEsHealthTestFailed] = kTopMatchaPlicPeripheralEntropySrc,
+ [kTopMatchaPlicIrqIdEntropySrcEsObserveFifoReady] = kTopMatchaPlicPeripheralEntropySrc,
+ [kTopMatchaPlicIrqIdEntropySrcEsFatalErr] = kTopMatchaPlicPeripheralEntropySrc,
+ [kTopMatchaPlicIrqIdEdn0EdnCmdReqDone] = kTopMatchaPlicPeripheralEdn0,
+ [kTopMatchaPlicIrqIdEdn0EdnFatalErr] = kTopMatchaPlicPeripheralEdn0,
+ [kTopMatchaPlicIrqIdEdn1EdnCmdReqDone] = kTopMatchaPlicPeripheralEdn1,
+ [kTopMatchaPlicIrqIdEdn1EdnFatalErr] = kTopMatchaPlicPeripheralEdn1,
+ [kTopMatchaPlicIrqIdDma0WriterDone] = kTopMatchaPlicPeripheralDma0,
+ [kTopMatchaPlicIrqIdDma0ReaderDone] = kTopMatchaPlicPeripheralDma0,
+ [kTopMatchaPlicIrqIdTlulMailboxSecWtirq] = kTopMatchaPlicPeripheralTlulMailboxSec,
+ [kTopMatchaPlicIrqIdTlulMailboxSecRtirq] = kTopMatchaPlicPeripheralTlulMailboxSec,
+ [kTopMatchaPlicIrqIdTlulMailboxSecEirq] = kTopMatchaPlicPeripheralTlulMailboxSec,
+};
+
+const top_sencha_plic_peripheral_smc_t
+ top_sencha_plic_interrupt_for_peripheral_smc[47] = {
+ [kTopMatchaPlicIrqIdNoneSmc] = kTopMatchaPlicPeripheralUnknownSmc,
+ [kTopMatchaPlicIrqIdSmcUartTxWatermark] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxWatermark] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartTxEmpty] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxOverflow] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxFrameErr] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxBreakErr] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxTimeout] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxParityErr] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdRvTimerSmcTimerExpiredHart0Timer0] = kTopMatchaPlicPeripheralRvTimerSmc,
+ [kTopMatchaPlicIrqIdCamI2cFmtThreshold] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cRxThreshold] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cFmtOverflow] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cRxOverflow] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cNak] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cSclInterference] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cSdaInterference] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cStretchTimeout] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cSdaUnstable] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cCmdComplete] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cTxStretch] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cTxOverflow] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cAcqFull] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cUnexpStop] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cHostTimeout] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamCtrlCamMotionDetect] = kTopMatchaPlicPeripheralCamCtrl,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperIsp] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperMi] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperMipi] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperEncoder] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperUpstream] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperAudioSmc] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdDmaSmcWriterDone] = kTopMatchaPlicPeripheralDmaSmc,
+ [kTopMatchaPlicIrqIdDmaSmcReaderDone] = kTopMatchaPlicPeripheralDmaSmc,
+ [kTopMatchaPlicIrqIdTlulMailboxSmcWtirq] = kTopMatchaPlicPeripheralTlulMailboxSmc,
+ [kTopMatchaPlicIrqIdTlulMailboxSmcRtirq] = kTopMatchaPlicPeripheralTlulMailboxSmc,
+ [kTopMatchaPlicIrqIdTlulMailboxSmcEirq] = kTopMatchaPlicPeripheralTlulMailboxSmc,
+ [kTopMatchaPlicIrqIdMlTopHostReq] = kTopMatchaPlicPeripheralMlTop,
+ [kTopMatchaPlicIrqIdMlTopFinish] = kTopMatchaPlicPeripheralMlTop,
+ [kTopMatchaPlicIrqIdMlTopFault] = kTopMatchaPlicPeripheralMlTop,
+ [kTopMatchaPlicIrqIdSpiHost2Error] = kTopMatchaPlicPeripheralSpiHost2,
+ [kTopMatchaPlicIrqIdSpiHost2SpiEvent] = kTopMatchaPlicPeripheralSpiHost2,
+ [kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0] = kTopMatchaPlicPeripheralRvTimerSmc2,
+ [kTopMatchaPlicIrqIdI2s0TxWatermark] = kTopMatchaPlicPeripheralI2s0,
+ [kTopMatchaPlicIrqIdI2s0RxWatermark] = kTopMatchaPlicPeripheralI2s0,
+ [kTopMatchaPlicIrqIdI2s0TxEmpty] = kTopMatchaPlicPeripheralI2s0,
+ [kTopMatchaPlicIrqIdI2s0RxOverflow] = kTopMatchaPlicPeripheralI2s0,
+};
+
+
+/**
+ * Alert Handler Alert Source to Peripheral Map
+ *
+ * This array is a mapping from `top_sencha_alert_id_t` to
+ * `top_sencha_alert_peripheral_t`.
+ */
+const top_sencha_alert_peripheral_t
+ top_sencha_alert_for_peripheral[75] = {
+ [kTopMatchaAlertIdUart0FatalFault] = kTopMatchaAlertPeripheralUart0,
+ [kTopMatchaAlertIdUart1FatalFault] = kTopMatchaAlertPeripheralUart1,
+ [kTopMatchaAlertIdUart2FatalFault] = kTopMatchaAlertPeripheralUart2,
+ [kTopMatchaAlertIdUart3FatalFault] = kTopMatchaAlertPeripheralUart3,
+ [kTopMatchaAlertIdGpioFatalFault] = kTopMatchaAlertPeripheralGpio,
+ [kTopMatchaAlertIdSpiDeviceFatalFault] = kTopMatchaAlertPeripheralSpiDevice,
+ [kTopMatchaAlertIdI2c0FatalFault] = kTopMatchaAlertPeripheralI2c0,
+ [kTopMatchaAlertIdI2c1FatalFault] = kTopMatchaAlertPeripheralI2c1,
+ [kTopMatchaAlertIdI2c2FatalFault] = kTopMatchaAlertPeripheralI2c2,
+ [kTopMatchaAlertIdPattgenFatalFault] = kTopMatchaAlertPeripheralPattgen,
+ [kTopMatchaAlertIdRvTimerFatalFault] = kTopMatchaAlertPeripheralRvTimer,
+ [kTopMatchaAlertIdOtpCtrlFatalMacroError] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdOtpCtrlFatalCheckError] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdOtpCtrlFatalBusIntegError] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdOtpCtrlFatalPrimOtpAlert] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdOtpCtrlRecovPrimOtpAlert] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdLcCtrlFatalProgError] = kTopMatchaAlertPeripheralLcCtrl,
+ [kTopMatchaAlertIdLcCtrlFatalStateError] = kTopMatchaAlertPeripheralLcCtrl,
+ [kTopMatchaAlertIdLcCtrlFatalBusIntegError] = kTopMatchaAlertPeripheralLcCtrl,
+ [kTopMatchaAlertIdSpiHost0FatalFault] = kTopMatchaAlertPeripheralSpiHost0,
+ [kTopMatchaAlertIdSpiHost1FatalFault] = kTopMatchaAlertPeripheralSpiHost1,
+ [kTopMatchaAlertIdUsbdevFatalFault] = kTopMatchaAlertPeripheralUsbdev,
+ [kTopMatchaAlertIdPwrmgrAonFatalFault] = kTopMatchaAlertPeripheralPwrmgrAon,
+ [kTopMatchaAlertIdRstmgrAonFatalFault] = kTopMatchaAlertPeripheralRstmgrAon,
+ [kTopMatchaAlertIdRstmgrAonFatalCnstyFault] = kTopMatchaAlertPeripheralRstmgrAon,
+ [kTopMatchaAlertIdClkmgrAonRecovFault] = kTopMatchaAlertPeripheralClkmgrAon,
+ [kTopMatchaAlertIdClkmgrAonFatalFault] = kTopMatchaAlertPeripheralClkmgrAon,
+ [kTopMatchaAlertIdSysrstCtrlAonFatalFault] = kTopMatchaAlertPeripheralSysrstCtrlAon,
+ [kTopMatchaAlertIdAdcCtrlAonFatalFault] = kTopMatchaAlertPeripheralAdcCtrlAon,
+ [kTopMatchaAlertIdPwmAonFatalFault] = kTopMatchaAlertPeripheralPwmAon,
+ [kTopMatchaAlertIdPinmuxAonFatalFault] = kTopMatchaAlertPeripheralPinmuxAon,
+ [kTopMatchaAlertIdAonTimerAonFatalFault] = kTopMatchaAlertPeripheralAonTimerAon,
+ [kTopMatchaAlertIdSensorCtrlRecovAlert] = kTopMatchaAlertPeripheralSensorCtrl,
+ [kTopMatchaAlertIdSensorCtrlFatalAlert] = kTopMatchaAlertPeripheralSensorCtrl,
+ [kTopMatchaAlertIdSramCtrlRetAonFatalError] = kTopMatchaAlertPeripheralSramCtrlRetAon,
+ [kTopMatchaAlertIdFlashCtrlRecovErr] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdFlashCtrlFatalStdErr] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdFlashCtrlFatalErr] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdFlashCtrlFatalPrimFlashAlert] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdFlashCtrlRecovPrimFlashAlert] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdRvDmFatalFault] = kTopMatchaAlertPeripheralRvDm,
+ [kTopMatchaAlertIdRvPlicFatalFault] = kTopMatchaAlertPeripheralRvPlic,
+ [kTopMatchaAlertIdAesRecovCtrlUpdateErr] = kTopMatchaAlertPeripheralAes,
+ [kTopMatchaAlertIdAesFatalFault] = kTopMatchaAlertPeripheralAes,
+ [kTopMatchaAlertIdHmacFatalFault] = kTopMatchaAlertPeripheralHmac,
+ [kTopMatchaAlertIdKmacRecovOperationErr] = kTopMatchaAlertPeripheralKmac,
+ [kTopMatchaAlertIdKmacFatalFaultErr] = kTopMatchaAlertPeripheralKmac,
+ [kTopMatchaAlertIdOtbnFatal] = kTopMatchaAlertPeripheralOtbn,
+ [kTopMatchaAlertIdOtbnRecov] = kTopMatchaAlertPeripheralOtbn,
+ [kTopMatchaAlertIdKeymgrRecovOperationErr] = kTopMatchaAlertPeripheralKeymgr,
+ [kTopMatchaAlertIdKeymgrFatalFaultErr] = kTopMatchaAlertPeripheralKeymgr,
+ [kTopMatchaAlertIdCsrngRecovAlert] = kTopMatchaAlertPeripheralCsrng,
+ [kTopMatchaAlertIdCsrngFatalAlert] = kTopMatchaAlertPeripheralCsrng,
+ [kTopMatchaAlertIdEntropySrcRecovAlert] = kTopMatchaAlertPeripheralEntropySrc,
+ [kTopMatchaAlertIdEntropySrcFatalAlert] = kTopMatchaAlertPeripheralEntropySrc,
+ [kTopMatchaAlertIdEdn0RecovAlert] = kTopMatchaAlertPeripheralEdn0,
+ [kTopMatchaAlertIdEdn0FatalAlert] = kTopMatchaAlertPeripheralEdn0,
+ [kTopMatchaAlertIdEdn1RecovAlert] = kTopMatchaAlertPeripheralEdn1,
+ [kTopMatchaAlertIdEdn1FatalAlert] = kTopMatchaAlertPeripheralEdn1,
+ [kTopMatchaAlertIdSramCtrlMainFatalError] = kTopMatchaAlertPeripheralSramCtrlMain,
+ [kTopMatchaAlertIdRomCtrlFatal] = kTopMatchaAlertPeripheralRomCtrl,
+ [kTopMatchaAlertIdRvCoreIbexSecFatalSwErr] = kTopMatchaAlertPeripheralRvCoreIbexSec,
+ [kTopMatchaAlertIdRvCoreIbexSecRecovSwErr] = kTopMatchaAlertPeripheralRvCoreIbexSec,
+ [kTopMatchaAlertIdRvCoreIbexSecFatalHwErr] = kTopMatchaAlertPeripheralRvCoreIbexSec,
+ [kTopMatchaAlertIdRvCoreIbexSecRecovHwErr] = kTopMatchaAlertPeripheralRvCoreIbexSec,
+ [kTopMatchaAlertIdSmcUartFatalFault] = kTopMatchaAlertPeripheralSmcUart,
+ [kTopMatchaAlertIdRvTimerSmcFatalFault] = kTopMatchaAlertPeripheralRvTimerSmc,
+ [kTopMatchaAlertIdCamI2cFatalFault] = kTopMatchaAlertPeripheralCamI2c,
+ [kTopMatchaAlertIdRvPlicSmcFatalFault] = kTopMatchaAlertPeripheralRvPlicSmc,
+ [kTopMatchaAlertIdSpiHost2FatalFault] = kTopMatchaAlertPeripheralSpiHost2,
+ [kTopMatchaAlertIdRvTimerSmc2FatalFault] = kTopMatchaAlertPeripheralRvTimerSmc2,
+ [kTopMatchaAlertIdRvCoreIbexSmcFatalSwErr] = kTopMatchaAlertPeripheralRvCoreIbexSmc,
+ [kTopMatchaAlertIdRvCoreIbexSmcRecovSwErr] = kTopMatchaAlertPeripheralRvCoreIbexSmc,
+ [kTopMatchaAlertIdRvCoreIbexSmcFatalHwErr] = kTopMatchaAlertPeripheralRvCoreIbexSmc,
+ [kTopMatchaAlertIdRvCoreIbexSmcRecovHwErr] = kTopMatchaAlertPeripheralRvCoreIbexSmc,
+};
+
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/top_sencha.h b/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/top_sencha.h
new file mode 100644
index 0000000..9b61696
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/top_sencha.h
@@ -0,0 +1,2392 @@
+// Copyright Google Inc.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_H_
+#define MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_H_
+
+#define MATCHA_SPARROW
+
+/**
+ * @file
+ * @brief Top-specific Definitions
+ *
+ * This file contains preprocessor and type definitions for use within the
+ * device C/C++ codebase.
+ *
+ * These definitions are for information that depends on the top-specific chip
+ * configuration, which includes:
+ * - Device Memory Information (for Peripherals and Memory)
+ * - PLIC Interrupt ID Names and Source Mappings
+ * - Alert ID Names and Source Mappings
+ * - Pinmux Pin/Select Names
+ * - Power Manager Wakeups
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Peripheral base address for uart0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART0_BASE_ADDR 0x40000000u
+
+/**
+ * Peripheral size for uart0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART0_BASE_ADDR and
+ * `TOP_MATCHA_UART0_BASE_ADDR + TOP_MATCHA_UART0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for uart1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART1_BASE_ADDR 0x40010000u
+
+/**
+ * Peripheral size for uart1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART1_BASE_ADDR and
+ * `TOP_MATCHA_UART1_BASE_ADDR + TOP_MATCHA_UART1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART1_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for uart2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART2_BASE_ADDR 0x40020000u
+
+/**
+ * Peripheral size for uart2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART2_BASE_ADDR and
+ * `TOP_MATCHA_UART2_BASE_ADDR + TOP_MATCHA_UART2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART2_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for uart3 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART3_BASE_ADDR 0x40030000u
+
+/**
+ * Peripheral size for uart3 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART3_BASE_ADDR and
+ * `TOP_MATCHA_UART3_BASE_ADDR + TOP_MATCHA_UART3_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART3_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for gpio in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_GPIO_BASE_ADDR 0x40040000u
+
+/**
+ * Peripheral size for gpio in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_GPIO_BASE_ADDR and
+ * `TOP_MATCHA_GPIO_BASE_ADDR + TOP_MATCHA_GPIO_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_GPIO_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for spi_device in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_DEVICE_BASE_ADDR 0x40050000u
+
+/**
+ * Peripheral size for spi_device in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_DEVICE_BASE_ADDR and
+ * `TOP_MATCHA_SPI_DEVICE_BASE_ADDR + TOP_MATCHA_SPI_DEVICE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_DEVICE_SIZE_BYTES 0x2000u
+
+/**
+ * Peripheral base address for i2c0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C0_BASE_ADDR 0x40080000u
+
+/**
+ * Peripheral size for i2c0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C0_BASE_ADDR and
+ * `TOP_MATCHA_I2C0_BASE_ADDR + TOP_MATCHA_I2C0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C0_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for i2c1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C1_BASE_ADDR 0x40090000u
+
+/**
+ * Peripheral size for i2c1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C1_BASE_ADDR and
+ * `TOP_MATCHA_I2C1_BASE_ADDR + TOP_MATCHA_I2C1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C1_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for i2c2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C2_BASE_ADDR 0x400A0000u
+
+/**
+ * Peripheral size for i2c2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C2_BASE_ADDR and
+ * `TOP_MATCHA_I2C2_BASE_ADDR + TOP_MATCHA_I2C2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C2_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for pattgen in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PATTGEN_BASE_ADDR 0x400E0000u
+
+/**
+ * Peripheral size for pattgen in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PATTGEN_BASE_ADDR and
+ * `TOP_MATCHA_PATTGEN_BASE_ADDR + TOP_MATCHA_PATTGEN_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PATTGEN_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_timer in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_BASE_ADDR 0x40100000u
+
+/**
+ * Peripheral size for rv_timer in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_BASE_ADDR + TOP_MATCHA_RV_TIMER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for core device on otp_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR 0x40130000u
+
+/**
+ * Peripheral size for core device on otp_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR and
+ * `TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR + TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES 0x2000u
+
+/**
+ * Peripheral base address for prim device on otp_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR 0x40132000u
+
+/**
+ * Peripheral size for prim device on otp_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR and
+ * `TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for lc_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_LC_CTRL_BASE_ADDR 0x40140000u
+
+/**
+ * Peripheral size for lc_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_LC_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_LC_CTRL_BASE_ADDR + TOP_MATCHA_LC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_LC_CTRL_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for alert_handler in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ALERT_HANDLER_BASE_ADDR 0x40150000u
+
+/**
+ * Peripheral size for alert_handler in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ALERT_HANDLER_BASE_ADDR and
+ * `TOP_MATCHA_ALERT_HANDLER_BASE_ADDR + TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES 0x800u
+
+/**
+ * Peripheral base address for spi_host0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST0_BASE_ADDR 0x40300000u
+
+/**
+ * Peripheral size for spi_host0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST0_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST0_BASE_ADDR + TOP_MATCHA_SPI_HOST0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for spi_host1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST1_BASE_ADDR 0x40310000u
+
+/**
+ * Peripheral size for spi_host1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST1_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST1_BASE_ADDR + TOP_MATCHA_SPI_HOST1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST1_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for usbdev in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_USBDEV_BASE_ADDR 0x40320000u
+
+/**
+ * Peripheral size for usbdev in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_USBDEV_BASE_ADDR and
+ * `TOP_MATCHA_USBDEV_BASE_ADDR + TOP_MATCHA_USBDEV_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_USBDEV_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for pwrmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PWRMGR_AON_BASE_ADDR 0x40400000u
+
+/**
+ * Peripheral size for pwrmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PWRMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_PWRMGR_AON_BASE_ADDR + TOP_MATCHA_PWRMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PWRMGR_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for rstmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RSTMGR_AON_BASE_ADDR 0x40410000u
+
+/**
+ * Peripheral size for rstmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RSTMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_RSTMGR_AON_BASE_ADDR + TOP_MATCHA_RSTMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RSTMGR_AON_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for clkmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CLKMGR_AON_BASE_ADDR 0x40420000u
+
+/**
+ * Peripheral size for clkmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CLKMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_CLKMGR_AON_BASE_ADDR + TOP_MATCHA_CLKMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CLKMGR_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for sysrst_ctrl_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
+
+/**
+ * Peripheral size for sysrst_ctrl_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR and
+ * `TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR + TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for adc_ctrl_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR 0x40440000u
+
+/**
+ * Peripheral size for adc_ctrl_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR and
+ * `TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR + TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for pwm_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PWM_AON_BASE_ADDR 0x40450000u
+
+/**
+ * Peripheral size for pwm_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PWM_AON_BASE_ADDR and
+ * `TOP_MATCHA_PWM_AON_BASE_ADDR + TOP_MATCHA_PWM_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PWM_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for pinmux_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PINMUX_AON_BASE_ADDR 0x40460000u
+
+/**
+ * Peripheral size for pinmux_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PINMUX_AON_BASE_ADDR and
+ * `TOP_MATCHA_PINMUX_AON_BASE_ADDR + TOP_MATCHA_PINMUX_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PINMUX_AON_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for aon_timer_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AON_TIMER_AON_BASE_ADDR 0x40470000u
+
+/**
+ * Peripheral size for aon_timer_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AON_TIMER_AON_BASE_ADDR and
+ * `TOP_MATCHA_AON_TIMER_AON_BASE_ADDR + TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for ast in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AST_BASE_ADDR 0x40480000u
+
+/**
+ * Peripheral size for ast in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AST_BASE_ADDR and
+ * `TOP_MATCHA_AST_BASE_ADDR + TOP_MATCHA_AST_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AST_SIZE_BYTES 0x400u
+
+/**
+ * Peripheral base address for sensor_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SENSOR_CTRL_BASE_ADDR 0x40490000u
+
+/**
+ * Peripheral size for sensor_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SENSOR_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_SENSOR_CTRL_BASE_ADDR + TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for ast_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AST_AON_BASE_ADDR 0x404C0000u
+
+/**
+ * Peripheral size for ast_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AST_AON_BASE_ADDR and
+ * `TOP_MATCHA_AST_AON_BASE_ADDR + TOP_MATCHA_AST_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AST_AON_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for regs device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
+
+/**
+ * Peripheral size for regs device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for ram device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
+
+/**
+ * Peripheral size for ram device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for core device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
+
+/**
+ * Peripheral size for core device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for prim device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u
+
+/**
+ * Peripheral size for prim device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for mem device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
+
+/**
+ * Peripheral size for mem device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u
+
+/**
+ * Peripheral base address for regs device on rv_dm in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_DM_REGS_BASE_ADDR 0x6000u
+
+/**
+ * Peripheral size for regs device on rv_dm in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_DM_REGS_BASE_ADDR and
+ * `TOP_MATCHA_RV_DM_REGS_BASE_ADDR + TOP_MATCHA_RV_DM_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_DM_REGS_SIZE_BYTES 0x4u
+
+/**
+ * Peripheral base address for mem device on rv_dm in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_DM_MEM_BASE_ADDR 0x4000u
+
+/**
+ * Peripheral size for mem device on rv_dm in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_DM_MEM_BASE_ADDR and
+ * `TOP_MATCHA_RV_DM_MEM_BASE_ADDR + TOP_MATCHA_RV_DM_MEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_DM_MEM_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for rv_plic in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_PLIC_BASE_ADDR 0x48000000u
+
+/**
+ * Peripheral size for rv_plic in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_PLIC_BASE_ADDR and
+ * `TOP_MATCHA_RV_PLIC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_PLIC_SIZE_BYTES 0x8000000u
+
+/**
+ * Peripheral base address for aes in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AES_BASE_ADDR 0x41100000u
+
+/**
+ * Peripheral size for aes in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AES_BASE_ADDR and
+ * `TOP_MATCHA_AES_BASE_ADDR + TOP_MATCHA_AES_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AES_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for hmac in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_HMAC_BASE_ADDR 0x41110000u
+
+/**
+ * Peripheral size for hmac in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_HMAC_BASE_ADDR and
+ * `TOP_MATCHA_HMAC_BASE_ADDR + TOP_MATCHA_HMAC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_HMAC_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for kmac in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_KMAC_BASE_ADDR 0x41120000u
+
+/**
+ * Peripheral size for kmac in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_KMAC_BASE_ADDR and
+ * `TOP_MATCHA_KMAC_BASE_ADDR + TOP_MATCHA_KMAC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_KMAC_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for otbn in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTBN_BASE_ADDR 0x41130000u
+
+/**
+ * Peripheral size for otbn in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTBN_BASE_ADDR and
+ * `TOP_MATCHA_OTBN_BASE_ADDR + TOP_MATCHA_OTBN_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTBN_SIZE_BYTES 0x10000u
+
+/**
+ * Peripheral base address for keymgr in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_KEYMGR_BASE_ADDR 0x41140000u
+
+/**
+ * Peripheral size for keymgr in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_KEYMGR_BASE_ADDR and
+ * `TOP_MATCHA_KEYMGR_BASE_ADDR + TOP_MATCHA_KEYMGR_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_KEYMGR_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for csrng in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CSRNG_BASE_ADDR 0x41150000u
+
+/**
+ * Peripheral size for csrng in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CSRNG_BASE_ADDR and
+ * `TOP_MATCHA_CSRNG_BASE_ADDR + TOP_MATCHA_CSRNG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CSRNG_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for entropy_src in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ENTROPY_SRC_BASE_ADDR 0x41160000u
+
+/**
+ * Peripheral size for entropy_src in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ENTROPY_SRC_BASE_ADDR and
+ * `TOP_MATCHA_ENTROPY_SRC_BASE_ADDR + TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for edn0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_EDN0_BASE_ADDR 0x41170000u
+
+/**
+ * Peripheral size for edn0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_EDN0_BASE_ADDR and
+ * `TOP_MATCHA_EDN0_BASE_ADDR + TOP_MATCHA_EDN0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_EDN0_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for edn1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_EDN1_BASE_ADDR 0x41180000u
+
+/**
+ * Peripheral size for edn1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_EDN1_BASE_ADDR and
+ * `TOP_MATCHA_EDN1_BASE_ADDR + TOP_MATCHA_EDN1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_EDN1_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for regs device on sram_ctrl_main in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
+
+/**
+ * Peripheral size for regs device on sram_ctrl_main in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for ram device on sram_ctrl_main in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
+
+/**
+ * Peripheral size for ram device on sram_ctrl_main in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
+
+/**
+ * Peripheral base address for regs device on rom_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
+
+/**
+ * Peripheral size for regs device on rom_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR and
+ * `TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR + TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for rom device on rom_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR 0x8000u
+
+/**
+ * Peripheral size for rom device on rom_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR and
+ * `TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR + TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
+
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_sec in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR 0x411F0000u
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_sec in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR and
+ * `TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for dma0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_DMA0_BASE_ADDR 0x40200000u
+
+/**
+ * Peripheral size for dma0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_DMA0_BASE_ADDR and
+ * `TOP_MATCHA_DMA0_BASE_ADDR + TOP_MATCHA_DMA0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_DMA0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for smc_uart in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SMC_UART_BASE_ADDR 0x54000000u
+
+/**
+ * Peripheral size for smc_uart in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SMC_UART_BASE_ADDR and
+ * `TOP_MATCHA_SMC_UART_BASE_ADDR + TOP_MATCHA_SMC_UART_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SMC_UART_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_timer_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR 0x54010000u
+
+/**
+ * Peripheral size for rv_timer_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for smc_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SMC_CTRL_BASE_ADDR 0x54020000u
+
+/**
+ * Peripheral size for smc_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SMC_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_SMC_CTRL_BASE_ADDR + TOP_MATCHA_SMC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SMC_CTRL_SIZE_BYTES 0x8u
+
+/**
+ * Peripheral base address for cam_i2c in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CAM_I2C_BASE_ADDR 0x54040000u
+
+/**
+ * Peripheral size for cam_i2c in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CAM_I2C_BASE_ADDR and
+ * `TOP_MATCHA_CAM_I2C_BASE_ADDR + TOP_MATCHA_CAM_I2C_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CAM_I2C_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for cam_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CAM_CTRL_BASE_ADDR 0x54050000u
+
+/**
+ * Peripheral size for cam_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CAM_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_CAM_CTRL_BASE_ADDR + TOP_MATCHA_CAM_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CAM_CTRL_SIZE_BYTES 0x10u
+
+/**
+ * Peripheral base address for vca device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR 0x55400000u
+
+/**
+ * Peripheral size for vca device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_SIZE_BYTES 0x400000u
+
+/**
+ * Peripheral base address for isp device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR 0x54060000u
+
+/**
+ * Peripheral size for isp device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_SIZE_BYTES 0x10000u
+
+/**
+ * Peripheral base address for enc device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR 0x55200000u
+
+/**
+ * Peripheral size for enc device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_SIZE_BYTES 0x10000u
+
+/**
+ * Peripheral base address for stream_buf device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR 0x55000000u
+
+/**
+ * Peripheral size for stream_buf device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_SIZE_BYTES 0x200000u
+
+/**
+ * Peripheral base address for vsi_ctl_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR 0x55210000u
+
+/**
+ * Peripheral size for vsi_ctl_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR and
+ * `TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR + TOP_MATCHA_VSI_CTL_WRAPPER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VSI_CTL_WRAPPER_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for dma_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_DMA_SMC_BASE_ADDR 0x54070000u
+
+/**
+ * Peripheral size for dma_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_DMA_SMC_BASE_ADDR and
+ * `TOP_MATCHA_DMA_SMC_BASE_ADDR + TOP_MATCHA_DMA_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_DMA_SMC_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_plic_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR 0x60000000u
+
+/**
+ * Peripheral size for rv_plic_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR and
+ * `TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES 0x8000000u
+
+/**
+ * Peripheral base address for tlul_mailbox_sec in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR 0x40800000u
+
+/**
+ * Peripheral size for tlul_mailbox_sec in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR and
+ * `TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for tlul_mailbox_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR 0x540F1000u
+
+/**
+ * Peripheral size for tlul_mailbox_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR and
+ * `TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for core device on ml_top in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ML_TOP_CORE_BASE_ADDR 0x5C000000u
+
+/**
+ * Peripheral size for core device on ml_top in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ML_TOP_CORE_BASE_ADDR and
+ * `TOP_MATCHA_ML_TOP_CORE_BASE_ADDR + TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for dmem device on ml_top in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR 0x5A000000u
+
+/**
+ * Peripheral size for dmem device on ml_top in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR and
+ * `TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR + TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000u
+
+/**
+ * Peripheral base address for spi_host2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST2_BASE_ADDR 0x54090000u
+
+/**
+ * Peripheral size for spi_host2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST2_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST2_BASE_ADDR + TOP_MATCHA_SPI_HOST2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST2_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_timer_smc2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR 0x54011000u
+
+/**
+ * Peripheral size for rv_timer_smc2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for i2s0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2S0_BASE_ADDR 0x54100000u
+
+/**
+ * Peripheral size for i2s0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2S0_BASE_ADDR and
+ * `TOP_MATCHA_I2S0_BASE_ADDR + TOP_MATCHA_I2S0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2S0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR 0x54030000u
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR and
+ * `TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES 0x100u
+
+
+/**
+ * Memory base address for ram_smc in top matcha.
+ */
+#define TOP_MATCHA_RAM_SMC_BASE_ADDR 0x50000000u
+
+/**
+ * Memory size for ram_smc in top matcha.
+ */
+#define TOP_MATCHA_RAM_SMC_SIZE_BYTES 0x400000u
+
+/**
+ * Memory base address for ram_ret_aon in top matcha.
+ */
+#define TOP_MATCHA_RAM_RET_AON_BASE_ADDR 0x40600000u
+
+/**
+ * Memory size for ram_ret_aon in top matcha.
+ */
+#define TOP_MATCHA_RAM_RET_AON_SIZE_BYTES 0x1000u
+
+/**
+ * Memory base address for eflash in top matcha.
+ */
+#define TOP_MATCHA_EFLASH_BASE_ADDR 0x20000000u
+
+/**
+ * Memory size for eflash in top matcha.
+ */
+#define TOP_MATCHA_EFLASH_SIZE_BYTES 0x100000u
+
+/**
+ * Memory base address for ram_main in top matcha.
+ */
+#define TOP_MATCHA_RAM_MAIN_BASE_ADDR 0x10000000u
+
+/**
+ * Memory size for ram_main in top matcha.
+ */
+#define TOP_MATCHA_RAM_MAIN_SIZE_BYTES 0x20000u
+
+/**
+ * Memory base address for rom in top matcha.
+ */
+#define TOP_MATCHA_ROM_BASE_ADDR 0x8000u
+
+/**
+ * Memory size for rom in top matcha.
+ */
+#define TOP_MATCHA_ROM_SIZE_BYTES 0x8000u
+
+/**
+ * Memory base address for video_sram in top matcha.
+ */
+#define TOP_MATCHA_VIDEO_SRAM_BASE_ADDR 0x55000000u
+
+/**
+ * Memory size for video_sram in top matcha.
+ */
+#define TOP_MATCHA_VIDEO_SRAM_SIZE_BYTES 0x200000u
+
+/**
+ * Memory base address for ram_ml_dmem in top matcha.
+ */
+#define TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR 0x5A000000u
+
+/**
+ * Memory size for ram_ml_dmem in top matcha.
+ */
+#define TOP_MATCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000u
+
+
+/**
+ * PLIC Interrupt Source Peripheral.
+ *
+ * Enumeration used to determine which peripheral asserted the corresponding
+ * interrupt.
+ */
+typedef enum top_sencha_plic_peripheral {
+ kTopMatchaPlicPeripheralUnknown = 0, /**< Unknown Peripheral */
+ kTopMatchaPlicPeripheralUart0 = 1, /**< uart0 */
+ kTopMatchaPlicPeripheralUart1 = 2, /**< uart1 */
+ kTopMatchaPlicPeripheralUart2 = 3, /**< uart2 */
+ kTopMatchaPlicPeripheralUart3 = 4, /**< uart3 */
+ kTopMatchaPlicPeripheralGpio = 5, /**< gpio */
+ kTopMatchaPlicPeripheralSpiDevice = 6, /**< spi_device */
+ kTopMatchaPlicPeripheralI2c0 = 7, /**< i2c0 */
+ kTopMatchaPlicPeripheralI2c1 = 8, /**< i2c1 */
+ kTopMatchaPlicPeripheralI2c2 = 9, /**< i2c2 */
+ kTopMatchaPlicPeripheralPattgen = 10, /**< pattgen */
+ kTopMatchaPlicPeripheralRvTimer = 11, /**< rv_timer */
+ kTopMatchaPlicPeripheralOtpCtrl = 12, /**< otp_ctrl */
+ kTopMatchaPlicPeripheralAlertHandler = 13, /**< alert_handler */
+ kTopMatchaPlicPeripheralSpiHost0 = 14, /**< spi_host0 */
+ kTopMatchaPlicPeripheralSpiHost1 = 15, /**< spi_host1 */
+ kTopMatchaPlicPeripheralUsbdev = 16, /**< usbdev */
+ kTopMatchaPlicPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
+ kTopMatchaPlicPeripheralSysrstCtrlAon = 18, /**< sysrst_ctrl_aon */
+ kTopMatchaPlicPeripheralAdcCtrlAon = 19, /**< adc_ctrl_aon */
+ kTopMatchaPlicPeripheralAonTimerAon = 20, /**< aon_timer_aon */
+ kTopMatchaPlicPeripheralSensorCtrl = 21, /**< sensor_ctrl */
+ kTopMatchaPlicPeripheralFlashCtrl = 22, /**< flash_ctrl */
+ kTopMatchaPlicPeripheralHmac = 23, /**< hmac */
+ kTopMatchaPlicPeripheralKmac = 24, /**< kmac */
+ kTopMatchaPlicPeripheralOtbn = 25, /**< otbn */
+ kTopMatchaPlicPeripheralKeymgr = 26, /**< keymgr */
+ kTopMatchaPlicPeripheralCsrng = 27, /**< csrng */
+ kTopMatchaPlicPeripheralEntropySrc = 28, /**< entropy_src */
+ kTopMatchaPlicPeripheralEdn0 = 29, /**< edn0 */
+ kTopMatchaPlicPeripheralEdn1 = 30, /**< edn1 */
+ kTopMatchaPlicPeripheralDma0 = 31, /**< dma0 */
+ kTopMatchaPlicPeripheralTlulMailboxSec = 32, /**< tlul_mailbox_sec */
+ kTopMatchaPlicPeripheralLast = 32, /**< \internal Final PLIC peripheral */
+} top_sencha_plic_peripheral_t;
+
+typedef enum top_sencha_plic_peripheral_smc {
+ kTopMatchaPlicPeripheralUnknownSmc = 0, /**< Unknown Peripheral */
+ kTopMatchaPlicPeripheralSmcUart = 1, /**< smc_uart */
+ kTopMatchaPlicPeripheralRvTimerSmc = 2, /**< rv_timer_smc */
+ kTopMatchaPlicPeripheralCamI2c = 3, /**< cam_i2c */
+ kTopMatchaPlicPeripheralCamCtrl = 4, /**< cam_ctrl */
+ kTopMatchaPlicPeripheralVideoAudioWrapper = 5, /**< video_audio_wrapper */
+ kTopMatchaPlicPeripheralDmaSmc = 6, /**< dma_smc */
+ kTopMatchaPlicPeripheralTlulMailboxSmc = 7, /**< tlul_mailbox_smc */
+ kTopMatchaPlicPeripheralMlTop = 8, /**< ml_top */
+ kTopMatchaPlicPeripheralSpiHost2 = 9, /**< spi_host2 */
+ kTopMatchaPlicPeripheralRvTimerSmc2 = 10, /**< rv_timer_smc2 */
+ kTopMatchaPlicPeripheralI2s0 = 11, /**< i2s0 */
+ kTopMatchaPlicPeripheralLastSmc = 11, /**< \internal Final PLIC peripheral */
+} top_sencha_plic_peripheral_smc_t;
+
+/**
+ * PLIC Interrupt Source.
+ *
+ * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
+ * the same peripheral are guaranteed to be consecutive.
+ */
+typedef enum top_sencha_plic_irq_id {
+ kTopMatchaPlicIrqIdNone = 0, /**< No Interrupt */
+ kTopMatchaPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
+ kTopMatchaPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
+ kTopMatchaPlicIrqIdUart0TxEmpty = 3, /**< uart0_tx_empty */
+ kTopMatchaPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
+ kTopMatchaPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
+ kTopMatchaPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
+ kTopMatchaPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
+ kTopMatchaPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
+ kTopMatchaPlicIrqIdUart1TxWatermark = 9, /**< uart1_tx_watermark */
+ kTopMatchaPlicIrqIdUart1RxWatermark = 10, /**< uart1_rx_watermark */
+ kTopMatchaPlicIrqIdUart1TxEmpty = 11, /**< uart1_tx_empty */
+ kTopMatchaPlicIrqIdUart1RxOverflow = 12, /**< uart1_rx_overflow */
+ kTopMatchaPlicIrqIdUart1RxFrameErr = 13, /**< uart1_rx_frame_err */
+ kTopMatchaPlicIrqIdUart1RxBreakErr = 14, /**< uart1_rx_break_err */
+ kTopMatchaPlicIrqIdUart1RxTimeout = 15, /**< uart1_rx_timeout */
+ kTopMatchaPlicIrqIdUart1RxParityErr = 16, /**< uart1_rx_parity_err */
+ kTopMatchaPlicIrqIdUart2TxWatermark = 17, /**< uart2_tx_watermark */
+ kTopMatchaPlicIrqIdUart2RxWatermark = 18, /**< uart2_rx_watermark */
+ kTopMatchaPlicIrqIdUart2TxEmpty = 19, /**< uart2_tx_empty */
+ kTopMatchaPlicIrqIdUart2RxOverflow = 20, /**< uart2_rx_overflow */
+ kTopMatchaPlicIrqIdUart2RxFrameErr = 21, /**< uart2_rx_frame_err */
+ kTopMatchaPlicIrqIdUart2RxBreakErr = 22, /**< uart2_rx_break_err */
+ kTopMatchaPlicIrqIdUart2RxTimeout = 23, /**< uart2_rx_timeout */
+ kTopMatchaPlicIrqIdUart2RxParityErr = 24, /**< uart2_rx_parity_err */
+ kTopMatchaPlicIrqIdUart3TxWatermark = 25, /**< uart3_tx_watermark */
+ kTopMatchaPlicIrqIdUart3RxWatermark = 26, /**< uart3_rx_watermark */
+ kTopMatchaPlicIrqIdUart3TxEmpty = 27, /**< uart3_tx_empty */
+ kTopMatchaPlicIrqIdUart3RxOverflow = 28, /**< uart3_rx_overflow */
+ kTopMatchaPlicIrqIdUart3RxFrameErr = 29, /**< uart3_rx_frame_err */
+ kTopMatchaPlicIrqIdUart3RxBreakErr = 30, /**< uart3_rx_break_err */
+ kTopMatchaPlicIrqIdUart3RxTimeout = 31, /**< uart3_rx_timeout */
+ kTopMatchaPlicIrqIdUart3RxParityErr = 32, /**< uart3_rx_parity_err */
+ kTopMatchaPlicIrqIdGpioGpio0 = 33, /**< gpio_gpio 0 */
+ kTopMatchaPlicIrqIdGpioGpio1 = 34, /**< gpio_gpio 1 */
+ kTopMatchaPlicIrqIdGpioGpio2 = 35, /**< gpio_gpio 2 */
+ kTopMatchaPlicIrqIdGpioGpio3 = 36, /**< gpio_gpio 3 */
+ kTopMatchaPlicIrqIdGpioGpio4 = 37, /**< gpio_gpio 4 */
+ kTopMatchaPlicIrqIdGpioGpio5 = 38, /**< gpio_gpio 5 */
+ kTopMatchaPlicIrqIdGpioGpio6 = 39, /**< gpio_gpio 6 */
+ kTopMatchaPlicIrqIdGpioGpio7 = 40, /**< gpio_gpio 7 */
+ kTopMatchaPlicIrqIdGpioGpio8 = 41, /**< gpio_gpio 8 */
+ kTopMatchaPlicIrqIdGpioGpio9 = 42, /**< gpio_gpio 9 */
+ kTopMatchaPlicIrqIdGpioGpio10 = 43, /**< gpio_gpio 10 */
+ kTopMatchaPlicIrqIdGpioGpio11 = 44, /**< gpio_gpio 11 */
+ kTopMatchaPlicIrqIdGpioGpio12 = 45, /**< gpio_gpio 12 */
+ kTopMatchaPlicIrqIdGpioGpio13 = 46, /**< gpio_gpio 13 */
+ kTopMatchaPlicIrqIdGpioGpio14 = 47, /**< gpio_gpio 14 */
+ kTopMatchaPlicIrqIdGpioGpio15 = 48, /**< gpio_gpio 15 */
+ kTopMatchaPlicIrqIdGpioGpio16 = 49, /**< gpio_gpio 16 */
+ kTopMatchaPlicIrqIdGpioGpio17 = 50, /**< gpio_gpio 17 */
+ kTopMatchaPlicIrqIdGpioGpio18 = 51, /**< gpio_gpio 18 */
+ kTopMatchaPlicIrqIdGpioGpio19 = 52, /**< gpio_gpio 19 */
+ kTopMatchaPlicIrqIdGpioGpio20 = 53, /**< gpio_gpio 20 */
+ kTopMatchaPlicIrqIdGpioGpio21 = 54, /**< gpio_gpio 21 */
+ kTopMatchaPlicIrqIdGpioGpio22 = 55, /**< gpio_gpio 22 */
+ kTopMatchaPlicIrqIdGpioGpio23 = 56, /**< gpio_gpio 23 */
+ kTopMatchaPlicIrqIdGpioGpio24 = 57, /**< gpio_gpio 24 */
+ kTopMatchaPlicIrqIdGpioGpio25 = 58, /**< gpio_gpio 25 */
+ kTopMatchaPlicIrqIdGpioGpio26 = 59, /**< gpio_gpio 26 */
+ kTopMatchaPlicIrqIdGpioGpio27 = 60, /**< gpio_gpio 27 */
+ kTopMatchaPlicIrqIdGpioGpio28 = 61, /**< gpio_gpio 28 */
+ kTopMatchaPlicIrqIdGpioGpio29 = 62, /**< gpio_gpio 29 */
+ kTopMatchaPlicIrqIdGpioGpio30 = 63, /**< gpio_gpio 30 */
+ kTopMatchaPlicIrqIdGpioGpio31 = 64, /**< gpio_gpio 31 */
+ kTopMatchaPlicIrqIdSpiDeviceGenericRxFull = 65, /**< spi_device_generic_rx_full */
+ kTopMatchaPlicIrqIdSpiDeviceGenericRxWatermark = 66, /**< spi_device_generic_rx_watermark */
+ kTopMatchaPlicIrqIdSpiDeviceGenericTxWatermark = 67, /**< spi_device_generic_tx_watermark */
+ kTopMatchaPlicIrqIdSpiDeviceGenericRxError = 68, /**< spi_device_generic_rx_error */
+ kTopMatchaPlicIrqIdSpiDeviceGenericRxOverflow = 69, /**< spi_device_generic_rx_overflow */
+ kTopMatchaPlicIrqIdSpiDeviceGenericTxUnderflow = 70, /**< spi_device_generic_tx_underflow */
+ kTopMatchaPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 71, /**< spi_device_upload_cmdfifo_not_empty */
+ kTopMatchaPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 72, /**< spi_device_upload_payload_not_empty */
+ kTopMatchaPlicIrqIdSpiDeviceUploadPayloadOverflow = 73, /**< spi_device_upload_payload_overflow */
+ kTopMatchaPlicIrqIdSpiDeviceReadbufWatermark = 74, /**< spi_device_readbuf_watermark */
+ kTopMatchaPlicIrqIdSpiDeviceReadbufFlip = 75, /**< spi_device_readbuf_flip */
+ kTopMatchaPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 76, /**< spi_device_tpm_header_not_empty */
+ kTopMatchaPlicIrqIdI2c0FmtThreshold = 77, /**< i2c0_fmt_threshold */
+ kTopMatchaPlicIrqIdI2c0RxThreshold = 78, /**< i2c0_rx_threshold */
+ kTopMatchaPlicIrqIdI2c0FmtOverflow = 79, /**< i2c0_fmt_overflow */
+ kTopMatchaPlicIrqIdI2c0RxOverflow = 80, /**< i2c0_rx_overflow */
+ kTopMatchaPlicIrqIdI2c0Nak = 81, /**< i2c0_nak */
+ kTopMatchaPlicIrqIdI2c0SclInterference = 82, /**< i2c0_scl_interference */
+ kTopMatchaPlicIrqIdI2c0SdaInterference = 83, /**< i2c0_sda_interference */
+ kTopMatchaPlicIrqIdI2c0StretchTimeout = 84, /**< i2c0_stretch_timeout */
+ kTopMatchaPlicIrqIdI2c0SdaUnstable = 85, /**< i2c0_sda_unstable */
+ kTopMatchaPlicIrqIdI2c0CmdComplete = 86, /**< i2c0_cmd_complete */
+ kTopMatchaPlicIrqIdI2c0TxStretch = 87, /**< i2c0_tx_stretch */
+ kTopMatchaPlicIrqIdI2c0TxOverflow = 88, /**< i2c0_tx_overflow */
+ kTopMatchaPlicIrqIdI2c0AcqFull = 89, /**< i2c0_acq_full */
+ kTopMatchaPlicIrqIdI2c0UnexpStop = 90, /**< i2c0_unexp_stop */
+ kTopMatchaPlicIrqIdI2c0HostTimeout = 91, /**< i2c0_host_timeout */
+ kTopMatchaPlicIrqIdI2c1FmtThreshold = 92, /**< i2c1_fmt_threshold */
+ kTopMatchaPlicIrqIdI2c1RxThreshold = 93, /**< i2c1_rx_threshold */
+ kTopMatchaPlicIrqIdI2c1FmtOverflow = 94, /**< i2c1_fmt_overflow */
+ kTopMatchaPlicIrqIdI2c1RxOverflow = 95, /**< i2c1_rx_overflow */
+ kTopMatchaPlicIrqIdI2c1Nak = 96, /**< i2c1_nak */
+ kTopMatchaPlicIrqIdI2c1SclInterference = 97, /**< i2c1_scl_interference */
+ kTopMatchaPlicIrqIdI2c1SdaInterference = 98, /**< i2c1_sda_interference */
+ kTopMatchaPlicIrqIdI2c1StretchTimeout = 99, /**< i2c1_stretch_timeout */
+ kTopMatchaPlicIrqIdI2c1SdaUnstable = 100, /**< i2c1_sda_unstable */
+ kTopMatchaPlicIrqIdI2c1CmdComplete = 101, /**< i2c1_cmd_complete */
+ kTopMatchaPlicIrqIdI2c1TxStretch = 102, /**< i2c1_tx_stretch */
+ kTopMatchaPlicIrqIdI2c1TxOverflow = 103, /**< i2c1_tx_overflow */
+ kTopMatchaPlicIrqIdI2c1AcqFull = 104, /**< i2c1_acq_full */
+ kTopMatchaPlicIrqIdI2c1UnexpStop = 105, /**< i2c1_unexp_stop */
+ kTopMatchaPlicIrqIdI2c1HostTimeout = 106, /**< i2c1_host_timeout */
+ kTopMatchaPlicIrqIdI2c2FmtThreshold = 107, /**< i2c2_fmt_threshold */
+ kTopMatchaPlicIrqIdI2c2RxThreshold = 108, /**< i2c2_rx_threshold */
+ kTopMatchaPlicIrqIdI2c2FmtOverflow = 109, /**< i2c2_fmt_overflow */
+ kTopMatchaPlicIrqIdI2c2RxOverflow = 110, /**< i2c2_rx_overflow */
+ kTopMatchaPlicIrqIdI2c2Nak = 111, /**< i2c2_nak */
+ kTopMatchaPlicIrqIdI2c2SclInterference = 112, /**< i2c2_scl_interference */
+ kTopMatchaPlicIrqIdI2c2SdaInterference = 113, /**< i2c2_sda_interference */
+ kTopMatchaPlicIrqIdI2c2StretchTimeout = 114, /**< i2c2_stretch_timeout */
+ kTopMatchaPlicIrqIdI2c2SdaUnstable = 115, /**< i2c2_sda_unstable */
+ kTopMatchaPlicIrqIdI2c2CmdComplete = 116, /**< i2c2_cmd_complete */
+ kTopMatchaPlicIrqIdI2c2TxStretch = 117, /**< i2c2_tx_stretch */
+ kTopMatchaPlicIrqIdI2c2TxOverflow = 118, /**< i2c2_tx_overflow */
+ kTopMatchaPlicIrqIdI2c2AcqFull = 119, /**< i2c2_acq_full */
+ kTopMatchaPlicIrqIdI2c2UnexpStop = 120, /**< i2c2_unexp_stop */
+ kTopMatchaPlicIrqIdI2c2HostTimeout = 121, /**< i2c2_host_timeout */
+ kTopMatchaPlicIrqIdPattgenDoneCh0 = 122, /**< pattgen_done_ch0 */
+ kTopMatchaPlicIrqIdPattgenDoneCh1 = 123, /**< pattgen_done_ch1 */
+ kTopMatchaPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 124, /**< rv_timer_timer_expired_hart0_timer0 */
+ kTopMatchaPlicIrqIdOtpCtrlOtpOperationDone = 125, /**< otp_ctrl_otp_operation_done */
+ kTopMatchaPlicIrqIdOtpCtrlOtpError = 126, /**< otp_ctrl_otp_error */
+ kTopMatchaPlicIrqIdAlertHandlerClassa = 127, /**< alert_handler_classa */
+ kTopMatchaPlicIrqIdAlertHandlerClassb = 128, /**< alert_handler_classb */
+ kTopMatchaPlicIrqIdAlertHandlerClassc = 129, /**< alert_handler_classc */
+ kTopMatchaPlicIrqIdAlertHandlerClassd = 130, /**< alert_handler_classd */
+ kTopMatchaPlicIrqIdSpiHost0Error = 131, /**< spi_host0_error */
+ kTopMatchaPlicIrqIdSpiHost0SpiEvent = 132, /**< spi_host0_spi_event */
+ kTopMatchaPlicIrqIdSpiHost1Error = 133, /**< spi_host1_error */
+ kTopMatchaPlicIrqIdSpiHost1SpiEvent = 134, /**< spi_host1_spi_event */
+ kTopMatchaPlicIrqIdUsbdevPktReceived = 135, /**< usbdev_pkt_received */
+ kTopMatchaPlicIrqIdUsbdevPktSent = 136, /**< usbdev_pkt_sent */
+ kTopMatchaPlicIrqIdUsbdevDisconnected = 137, /**< usbdev_disconnected */
+ kTopMatchaPlicIrqIdUsbdevHostLost = 138, /**< usbdev_host_lost */
+ kTopMatchaPlicIrqIdUsbdevLinkReset = 139, /**< usbdev_link_reset */
+ kTopMatchaPlicIrqIdUsbdevLinkSuspend = 140, /**< usbdev_link_suspend */
+ kTopMatchaPlicIrqIdUsbdevLinkResume = 141, /**< usbdev_link_resume */
+ kTopMatchaPlicIrqIdUsbdevAvEmpty = 142, /**< usbdev_av_empty */
+ kTopMatchaPlicIrqIdUsbdevRxFull = 143, /**< usbdev_rx_full */
+ kTopMatchaPlicIrqIdUsbdevAvOverflow = 144, /**< usbdev_av_overflow */
+ kTopMatchaPlicIrqIdUsbdevLinkInErr = 145, /**< usbdev_link_in_err */
+ kTopMatchaPlicIrqIdUsbdevRxCrcErr = 146, /**< usbdev_rx_crc_err */
+ kTopMatchaPlicIrqIdUsbdevRxPidErr = 147, /**< usbdev_rx_pid_err */
+ kTopMatchaPlicIrqIdUsbdevRxBitstuffErr = 148, /**< usbdev_rx_bitstuff_err */
+ kTopMatchaPlicIrqIdUsbdevFrame = 149, /**< usbdev_frame */
+ kTopMatchaPlicIrqIdUsbdevPowered = 150, /**< usbdev_powered */
+ kTopMatchaPlicIrqIdUsbdevLinkOutErr = 151, /**< usbdev_link_out_err */
+ kTopMatchaPlicIrqIdPwrmgrAonWakeup = 152, /**< pwrmgr_aon_wakeup */
+ kTopMatchaPlicIrqIdSysrstCtrlAonEventDetected = 153, /**< sysrst_ctrl_aon_event_detected */
+ kTopMatchaPlicIrqIdAdcCtrlAonMatchDone = 154, /**< adc_ctrl_aon_match_done */
+ kTopMatchaPlicIrqIdAonTimerAonWkupTimerExpired = 155, /**< aon_timer_aon_wkup_timer_expired */
+ kTopMatchaPlicIrqIdAonTimerAonWdogTimerBark = 156, /**< aon_timer_aon_wdog_timer_bark */
+ kTopMatchaPlicIrqIdSensorCtrlIoStatusChange = 157, /**< sensor_ctrl_io_status_change */
+ kTopMatchaPlicIrqIdSensorCtrlInitStatusChange = 158, /**< sensor_ctrl_init_status_change */
+ kTopMatchaPlicIrqIdFlashCtrlProgEmpty = 159, /**< flash_ctrl_prog_empty */
+ kTopMatchaPlicIrqIdFlashCtrlProgLvl = 160, /**< flash_ctrl_prog_lvl */
+ kTopMatchaPlicIrqIdFlashCtrlRdFull = 161, /**< flash_ctrl_rd_full */
+ kTopMatchaPlicIrqIdFlashCtrlRdLvl = 162, /**< flash_ctrl_rd_lvl */
+ kTopMatchaPlicIrqIdFlashCtrlOpDone = 163, /**< flash_ctrl_op_done */
+ kTopMatchaPlicIrqIdFlashCtrlCorrErr = 164, /**< flash_ctrl_corr_err */
+ kTopMatchaPlicIrqIdHmacHmacDone = 165, /**< hmac_hmac_done */
+ kTopMatchaPlicIrqIdHmacFifoEmpty = 166, /**< hmac_fifo_empty */
+ kTopMatchaPlicIrqIdHmacHmacErr = 167, /**< hmac_hmac_err */
+ kTopMatchaPlicIrqIdKmacKmacDone = 168, /**< kmac_kmac_done */
+ kTopMatchaPlicIrqIdKmacFifoEmpty = 169, /**< kmac_fifo_empty */
+ kTopMatchaPlicIrqIdKmacKmacErr = 170, /**< kmac_kmac_err */
+ kTopMatchaPlicIrqIdOtbnDone = 171, /**< otbn_done */
+ kTopMatchaPlicIrqIdKeymgrOpDone = 172, /**< keymgr_op_done */
+ kTopMatchaPlicIrqIdCsrngCsCmdReqDone = 173, /**< csrng_cs_cmd_req_done */
+ kTopMatchaPlicIrqIdCsrngCsEntropyReq = 174, /**< csrng_cs_entropy_req */
+ kTopMatchaPlicIrqIdCsrngCsHwInstExc = 175, /**< csrng_cs_hw_inst_exc */
+ kTopMatchaPlicIrqIdCsrngCsFatalErr = 176, /**< csrng_cs_fatal_err */
+ kTopMatchaPlicIrqIdEntropySrcEsEntropyValid = 177, /**< entropy_src_es_entropy_valid */
+ kTopMatchaPlicIrqIdEntropySrcEsHealthTestFailed = 178, /**< entropy_src_es_health_test_failed */
+ kTopMatchaPlicIrqIdEntropySrcEsObserveFifoReady = 179, /**< entropy_src_es_observe_fifo_ready */
+ kTopMatchaPlicIrqIdEntropySrcEsFatalErr = 180, /**< entropy_src_es_fatal_err */
+ kTopMatchaPlicIrqIdEdn0EdnCmdReqDone = 181, /**< edn0_edn_cmd_req_done */
+ kTopMatchaPlicIrqIdEdn0EdnFatalErr = 182, /**< edn0_edn_fatal_err */
+ kTopMatchaPlicIrqIdEdn1EdnCmdReqDone = 183, /**< edn1_edn_cmd_req_done */
+ kTopMatchaPlicIrqIdEdn1EdnFatalErr = 184, /**< edn1_edn_fatal_err */
+ kTopMatchaPlicIrqIdDma0WriterDone = 185, /**< dma0_writer_done */
+ kTopMatchaPlicIrqIdDma0ReaderDone = 186, /**< dma0_reader_done */
+ kTopMatchaPlicIrqIdTlulMailboxSecWtirq = 187, /**< tlul_mailbox_sec_wtirq */
+ kTopMatchaPlicIrqIdTlulMailboxSecRtirq = 188, /**< tlul_mailbox_sec_rtirq */
+ kTopMatchaPlicIrqIdTlulMailboxSecEirq = 189, /**< tlul_mailbox_sec_eirq */
+ kTopMatchaPlicIrqIdLast = 189, /**< \internal The Last Valid Interrupt ID. */
+} top_sencha_plic_irq_id_t;
+
+typedef enum top_sencha_plic_irq_id_smc {
+ kTopMatchaPlicIrqIdNoneSmc = 0, /**< No Interrupt */
+ kTopMatchaPlicIrqIdSmcUartTxWatermark = 1, /**< smc_uart_tx_watermark */
+ kTopMatchaPlicIrqIdSmcUartRxWatermark = 2, /**< smc_uart_rx_watermark */
+ kTopMatchaPlicIrqIdSmcUartTxEmpty = 3, /**< smc_uart_tx_empty */
+ kTopMatchaPlicIrqIdSmcUartRxOverflow = 4, /**< smc_uart_rx_overflow */
+ kTopMatchaPlicIrqIdSmcUartRxFrameErr = 5, /**< smc_uart_rx_frame_err */
+ kTopMatchaPlicIrqIdSmcUartRxBreakErr = 6, /**< smc_uart_rx_break_err */
+ kTopMatchaPlicIrqIdSmcUartRxTimeout = 7, /**< smc_uart_rx_timeout */
+ kTopMatchaPlicIrqIdSmcUartRxParityErr = 8, /**< smc_uart_rx_parity_err */
+ kTopMatchaPlicIrqIdRvTimerSmcTimerExpiredHart0Timer0 = 9, /**< rv_timer_smc_timer_expired_hart0_timer0 */
+ kTopMatchaPlicIrqIdCamI2cFmtThreshold = 10, /**< cam_i2c_fmt_threshold */
+ kTopMatchaPlicIrqIdCamI2cRxThreshold = 11, /**< cam_i2c_rx_threshold */
+ kTopMatchaPlicIrqIdCamI2cFmtOverflow = 12, /**< cam_i2c_fmt_overflow */
+ kTopMatchaPlicIrqIdCamI2cRxOverflow = 13, /**< cam_i2c_rx_overflow */
+ kTopMatchaPlicIrqIdCamI2cNak = 14, /**< cam_i2c_nak */
+ kTopMatchaPlicIrqIdCamI2cSclInterference = 15, /**< cam_i2c_scl_interference */
+ kTopMatchaPlicIrqIdCamI2cSdaInterference = 16, /**< cam_i2c_sda_interference */
+ kTopMatchaPlicIrqIdCamI2cStretchTimeout = 17, /**< cam_i2c_stretch_timeout */
+ kTopMatchaPlicIrqIdCamI2cSdaUnstable = 18, /**< cam_i2c_sda_unstable */
+ kTopMatchaPlicIrqIdCamI2cCmdComplete = 19, /**< cam_i2c_cmd_complete */
+ kTopMatchaPlicIrqIdCamI2cTxStretch = 20, /**< cam_i2c_tx_stretch */
+ kTopMatchaPlicIrqIdCamI2cTxOverflow = 21, /**< cam_i2c_tx_overflow */
+ kTopMatchaPlicIrqIdCamI2cAcqFull = 22, /**< cam_i2c_acq_full */
+ kTopMatchaPlicIrqIdCamI2cUnexpStop = 23, /**< cam_i2c_unexp_stop */
+ kTopMatchaPlicIrqIdCamI2cHostTimeout = 24, /**< cam_i2c_host_timeout */
+ kTopMatchaPlicIrqIdCamCtrlCamMotionDetect = 25, /**< cam_ctrl_cam_motion_detect */
+ kTopMatchaPlicIrqIdVideoAudioWrapperIsp = 26, /**< video_audio_wrapper_isp */
+ kTopMatchaPlicIrqIdVideoAudioWrapperMi = 27, /**< video_audio_wrapper_mi */
+ kTopMatchaPlicIrqIdVideoAudioWrapperMipi = 28, /**< video_audio_wrapper_mipi */
+ kTopMatchaPlicIrqIdVideoAudioWrapperEncoder = 29, /**< video_audio_wrapper_encoder */
+ kTopMatchaPlicIrqIdVideoAudioWrapperUpstream = 30, /**< video_audio_wrapper_upstream */
+ kTopMatchaPlicIrqIdVideoAudioWrapperAudioSmc = 31, /**< video_audio_wrapper_audio_smc */
+ kTopMatchaPlicIrqIdDmaSmcWriterDone = 32, /**< dma_smc_writer_done */
+ kTopMatchaPlicIrqIdDmaSmcReaderDone = 33, /**< dma_smc_reader_done */
+ kTopMatchaPlicIrqIdTlulMailboxSmcWtirq = 34, /**< tlul_mailbox_smc_wtirq */
+ kTopMatchaPlicIrqIdTlulMailboxSmcRtirq = 35, /**< tlul_mailbox_smc_rtirq */
+ kTopMatchaPlicIrqIdTlulMailboxSmcEirq = 36, /**< tlul_mailbox_smc_eirq */
+ kTopMatchaPlicIrqIdMlTopHostReq = 37, /**< ml_top_host_req */
+ kTopMatchaPlicIrqIdMlTopFinish = 38, /**< ml_top_finish */
+ kTopMatchaPlicIrqIdMlTopFault = 39, /**< ml_top_fault */
+ kTopMatchaPlicIrqIdSpiHost2Error = 40, /**< spi_host2_error */
+ kTopMatchaPlicIrqIdSpiHost2SpiEvent = 41, /**< spi_host2_spi_event */
+ kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0 = 42, /**< rv_timer_smc2_timer_expired_hart0_timer0 */
+ kTopMatchaPlicIrqIdI2s0TxWatermark = 43, /**< i2s0_tx_watermark */
+ kTopMatchaPlicIrqIdI2s0RxWatermark = 44, /**< i2s0_rx_watermark */
+ kTopMatchaPlicIrqIdI2s0TxEmpty = 45, /**< i2s0_tx_empty */
+ kTopMatchaPlicIrqIdI2s0RxOverflow = 46, /**< i2s0_rx_overflow */
+ kTopMatchaPlicIrqIdLastSmc = 46, /**< \internal The Last Valid Interrupt ID. */
+} top_sencha_plic_irq_id_smc_t;
+
+/**
+ * PLIC Interrupt Source to Peripheral Map
+ *
+ * This array is a mapping from `top_sencha_plic_irq_id_t` to
+ * `top_sencha_plic_peripheral_t`.
+ */
+extern const top_sencha_plic_peripheral_t
+ top_sencha_plic_interrupt_for_peripheral[190];
+
+extern const top_sencha_plic_peripheral_smc_t
+ top_sencha_plic_interrupt_for_peripheral_smc[47];
+
+/**
+ * PLIC Interrupt Target.
+ *
+ * Enumeration used to determine which set of IE, CC, threshold registers to
+ * access for a given interrupt target.
+ */
+typedef enum top_sencha_plic_target {
+ kTopMatchaPlicTargetIbex0 = 0, /**< Ibex Core 0 */
+ kTopMatchaPlicTargetIbex1 = 1, /**< Ibex Core 1 */
+ kTopMatchaPlicTargetLast = 1, /**< \internal Final PLIC target */
+} top_sencha_plic_target_t;
+
+typedef enum top_sencha_plic_target_smc {
+ kTopMatchaPlicTargetIbex0Smc = 0, /**< Ibex Core 0 */
+ kTopMatchaPlicTargetLastSmc = 0, /**< \internal Final PLIC target */
+} top_sencha_plic_target_smc_t;
+
+/**
+ * Alert Handler Source Peripheral.
+ *
+ * Enumeration used to determine which peripheral asserted the corresponding
+ * alert.
+ */
+typedef enum top_sencha_alert_peripheral {
+ kTopMatchaAlertPeripheralUart0 = 0, /**< uart0 */
+ kTopMatchaAlertPeripheralUart1 = 1, /**< uart1 */
+ kTopMatchaAlertPeripheralUart2 = 2, /**< uart2 */
+ kTopMatchaAlertPeripheralUart3 = 3, /**< uart3 */
+ kTopMatchaAlertPeripheralGpio = 4, /**< gpio */
+ kTopMatchaAlertPeripheralSpiDevice = 5, /**< spi_device */
+ kTopMatchaAlertPeripheralI2c0 = 6, /**< i2c0 */
+ kTopMatchaAlertPeripheralI2c1 = 7, /**< i2c1 */
+ kTopMatchaAlertPeripheralI2c2 = 8, /**< i2c2 */
+ kTopMatchaAlertPeripheralPattgen = 9, /**< pattgen */
+ kTopMatchaAlertPeripheralRvTimer = 10, /**< rv_timer */
+ kTopMatchaAlertPeripheralOtpCtrl = 11, /**< otp_ctrl */
+ kTopMatchaAlertPeripheralLcCtrl = 12, /**< lc_ctrl */
+ kTopMatchaAlertPeripheralSpiHost0 = 13, /**< spi_host0 */
+ kTopMatchaAlertPeripheralSpiHost1 = 14, /**< spi_host1 */
+ kTopMatchaAlertPeripheralUsbdev = 15, /**< usbdev */
+ kTopMatchaAlertPeripheralPwrmgrAon = 16, /**< pwrmgr_aon */
+ kTopMatchaAlertPeripheralRstmgrAon = 17, /**< rstmgr_aon */
+ kTopMatchaAlertPeripheralClkmgrAon = 18, /**< clkmgr_aon */
+ kTopMatchaAlertPeripheralSysrstCtrlAon = 19, /**< sysrst_ctrl_aon */
+ kTopMatchaAlertPeripheralAdcCtrlAon = 20, /**< adc_ctrl_aon */
+ kTopMatchaAlertPeripheralPwmAon = 21, /**< pwm_aon */
+ kTopMatchaAlertPeripheralPinmuxAon = 22, /**< pinmux_aon */
+ kTopMatchaAlertPeripheralAonTimerAon = 23, /**< aon_timer_aon */
+ kTopMatchaAlertPeripheralSensorCtrl = 24, /**< sensor_ctrl */
+ kTopMatchaAlertPeripheralSramCtrlRetAon = 25, /**< sram_ctrl_ret_aon */
+ kTopMatchaAlertPeripheralFlashCtrl = 26, /**< flash_ctrl */
+ kTopMatchaAlertPeripheralRvDm = 27, /**< rv_dm */
+ kTopMatchaAlertPeripheralRvPlic = 28, /**< rv_plic */
+ kTopMatchaAlertPeripheralAes = 29, /**< aes */
+ kTopMatchaAlertPeripheralHmac = 30, /**< hmac */
+ kTopMatchaAlertPeripheralKmac = 31, /**< kmac */
+ kTopMatchaAlertPeripheralOtbn = 32, /**< otbn */
+ kTopMatchaAlertPeripheralKeymgr = 33, /**< keymgr */
+ kTopMatchaAlertPeripheralCsrng = 34, /**< csrng */
+ kTopMatchaAlertPeripheralEntropySrc = 35, /**< entropy_src */
+ kTopMatchaAlertPeripheralEdn0 = 36, /**< edn0 */
+ kTopMatchaAlertPeripheralEdn1 = 37, /**< edn1 */
+ kTopMatchaAlertPeripheralSramCtrlMain = 38, /**< sram_ctrl_main */
+ kTopMatchaAlertPeripheralRomCtrl = 39, /**< rom_ctrl */
+ kTopMatchaAlertPeripheralRvCoreIbexSec = 40, /**< rv_core_ibex_sec */
+ kTopMatchaAlertPeripheralSmcUart = 41, /**< smc_uart */
+ kTopMatchaAlertPeripheralRvTimerSmc = 42, /**< rv_timer_smc */
+ kTopMatchaAlertPeripheralCamI2c = 43, /**< cam_i2c */
+ kTopMatchaAlertPeripheralRvPlicSmc = 44, /**< rv_plic_smc */
+ kTopMatchaAlertPeripheralSpiHost2 = 45, /**< spi_host2 */
+ kTopMatchaAlertPeripheralRvTimerSmc2 = 46, /**< rv_timer_smc2 */
+ kTopMatchaAlertPeripheralRvCoreIbexSmc = 47, /**< rv_core_ibex_smc */
+ kTopMatchaAlertPeripheralLast = 47, /**< \internal Final Alert peripheral */
+} top_sencha_alert_peripheral_t;
+
+/**
+ * Alert Handler Alert Source.
+ *
+ * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
+ * the same peripheral are guaranteed to be consecutive.
+ */
+typedef enum top_sencha_alert_id {
+ kTopMatchaAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */
+ kTopMatchaAlertIdUart1FatalFault = 1, /**< uart1_fatal_fault */
+ kTopMatchaAlertIdUart2FatalFault = 2, /**< uart2_fatal_fault */
+ kTopMatchaAlertIdUart3FatalFault = 3, /**< uart3_fatal_fault */
+ kTopMatchaAlertIdGpioFatalFault = 4, /**< gpio_fatal_fault */
+ kTopMatchaAlertIdSpiDeviceFatalFault = 5, /**< spi_device_fatal_fault */
+ kTopMatchaAlertIdI2c0FatalFault = 6, /**< i2c0_fatal_fault */
+ kTopMatchaAlertIdI2c1FatalFault = 7, /**< i2c1_fatal_fault */
+ kTopMatchaAlertIdI2c2FatalFault = 8, /**< i2c2_fatal_fault */
+ kTopMatchaAlertIdPattgenFatalFault = 9, /**< pattgen_fatal_fault */
+ kTopMatchaAlertIdRvTimerFatalFault = 10, /**< rv_timer_fatal_fault */
+ kTopMatchaAlertIdOtpCtrlFatalMacroError = 11, /**< otp_ctrl_fatal_macro_error */
+ kTopMatchaAlertIdOtpCtrlFatalCheckError = 12, /**< otp_ctrl_fatal_check_error */
+ kTopMatchaAlertIdOtpCtrlFatalBusIntegError = 13, /**< otp_ctrl_fatal_bus_integ_error */
+ kTopMatchaAlertIdOtpCtrlFatalPrimOtpAlert = 14, /**< otp_ctrl_fatal_prim_otp_alert */
+ kTopMatchaAlertIdOtpCtrlRecovPrimOtpAlert = 15, /**< otp_ctrl_recov_prim_otp_alert */
+ kTopMatchaAlertIdLcCtrlFatalProgError = 16, /**< lc_ctrl_fatal_prog_error */
+ kTopMatchaAlertIdLcCtrlFatalStateError = 17, /**< lc_ctrl_fatal_state_error */
+ kTopMatchaAlertIdLcCtrlFatalBusIntegError = 18, /**< lc_ctrl_fatal_bus_integ_error */
+ kTopMatchaAlertIdSpiHost0FatalFault = 19, /**< spi_host0_fatal_fault */
+ kTopMatchaAlertIdSpiHost1FatalFault = 20, /**< spi_host1_fatal_fault */
+ kTopMatchaAlertIdUsbdevFatalFault = 21, /**< usbdev_fatal_fault */
+ kTopMatchaAlertIdPwrmgrAonFatalFault = 22, /**< pwrmgr_aon_fatal_fault */
+ kTopMatchaAlertIdRstmgrAonFatalFault = 23, /**< rstmgr_aon_fatal_fault */
+ kTopMatchaAlertIdRstmgrAonFatalCnstyFault = 24, /**< rstmgr_aon_fatal_cnsty_fault */
+ kTopMatchaAlertIdClkmgrAonRecovFault = 25, /**< clkmgr_aon_recov_fault */
+ kTopMatchaAlertIdClkmgrAonFatalFault = 26, /**< clkmgr_aon_fatal_fault */
+ kTopMatchaAlertIdSysrstCtrlAonFatalFault = 27, /**< sysrst_ctrl_aon_fatal_fault */
+ kTopMatchaAlertIdAdcCtrlAonFatalFault = 28, /**< adc_ctrl_aon_fatal_fault */
+ kTopMatchaAlertIdPwmAonFatalFault = 29, /**< pwm_aon_fatal_fault */
+ kTopMatchaAlertIdPinmuxAonFatalFault = 30, /**< pinmux_aon_fatal_fault */
+ kTopMatchaAlertIdAonTimerAonFatalFault = 31, /**< aon_timer_aon_fatal_fault */
+ kTopMatchaAlertIdSensorCtrlRecovAlert = 32, /**< sensor_ctrl_recov_alert */
+ kTopMatchaAlertIdSensorCtrlFatalAlert = 33, /**< sensor_ctrl_fatal_alert */
+ kTopMatchaAlertIdSramCtrlRetAonFatalError = 34, /**< sram_ctrl_ret_aon_fatal_error */
+ kTopMatchaAlertIdFlashCtrlRecovErr = 35, /**< flash_ctrl_recov_err */
+ kTopMatchaAlertIdFlashCtrlFatalStdErr = 36, /**< flash_ctrl_fatal_std_err */
+ kTopMatchaAlertIdFlashCtrlFatalErr = 37, /**< flash_ctrl_fatal_err */
+ kTopMatchaAlertIdFlashCtrlFatalPrimFlashAlert = 38, /**< flash_ctrl_fatal_prim_flash_alert */
+ kTopMatchaAlertIdFlashCtrlRecovPrimFlashAlert = 39, /**< flash_ctrl_recov_prim_flash_alert */
+ kTopMatchaAlertIdRvDmFatalFault = 40, /**< rv_dm_fatal_fault */
+ kTopMatchaAlertIdRvPlicFatalFault = 41, /**< rv_plic_fatal_fault */
+ kTopMatchaAlertIdAesRecovCtrlUpdateErr = 42, /**< aes_recov_ctrl_update_err */
+ kTopMatchaAlertIdAesFatalFault = 43, /**< aes_fatal_fault */
+ kTopMatchaAlertIdHmacFatalFault = 44, /**< hmac_fatal_fault */
+ kTopMatchaAlertIdKmacRecovOperationErr = 45, /**< kmac_recov_operation_err */
+ kTopMatchaAlertIdKmacFatalFaultErr = 46, /**< kmac_fatal_fault_err */
+ kTopMatchaAlertIdOtbnFatal = 47, /**< otbn_fatal */
+ kTopMatchaAlertIdOtbnRecov = 48, /**< otbn_recov */
+ kTopMatchaAlertIdKeymgrRecovOperationErr = 49, /**< keymgr_recov_operation_err */
+ kTopMatchaAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */
+ kTopMatchaAlertIdCsrngRecovAlert = 51, /**< csrng_recov_alert */
+ kTopMatchaAlertIdCsrngFatalAlert = 52, /**< csrng_fatal_alert */
+ kTopMatchaAlertIdEntropySrcRecovAlert = 53, /**< entropy_src_recov_alert */
+ kTopMatchaAlertIdEntropySrcFatalAlert = 54, /**< entropy_src_fatal_alert */
+ kTopMatchaAlertIdEdn0RecovAlert = 55, /**< edn0_recov_alert */
+ kTopMatchaAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */
+ kTopMatchaAlertIdEdn1RecovAlert = 57, /**< edn1_recov_alert */
+ kTopMatchaAlertIdEdn1FatalAlert = 58, /**< edn1_fatal_alert */
+ kTopMatchaAlertIdSramCtrlMainFatalError = 59, /**< sram_ctrl_main_fatal_error */
+ kTopMatchaAlertIdRomCtrlFatal = 60, /**< rom_ctrl_fatal */
+ kTopMatchaAlertIdRvCoreIbexSecFatalSwErr = 61, /**< rv_core_ibex_sec_fatal_sw_err */
+ kTopMatchaAlertIdRvCoreIbexSecRecovSwErr = 62, /**< rv_core_ibex_sec_recov_sw_err */
+ kTopMatchaAlertIdRvCoreIbexSecFatalHwErr = 63, /**< rv_core_ibex_sec_fatal_hw_err */
+ kTopMatchaAlertIdRvCoreIbexSecRecovHwErr = 64, /**< rv_core_ibex_sec_recov_hw_err */
+ kTopMatchaAlertIdSmcUartFatalFault = 65, /**< smc_uart_fatal_fault */
+ kTopMatchaAlertIdRvTimerSmcFatalFault = 66, /**< rv_timer_smc_fatal_fault */
+ kTopMatchaAlertIdCamI2cFatalFault = 67, /**< cam_i2c_fatal_fault */
+ kTopMatchaAlertIdRvPlicSmcFatalFault = 68, /**< rv_plic_smc_fatal_fault */
+ kTopMatchaAlertIdSpiHost2FatalFault = 69, /**< spi_host2_fatal_fault */
+ kTopMatchaAlertIdRvTimerSmc2FatalFault = 70, /**< rv_timer_smc2_fatal_fault */
+ kTopMatchaAlertIdRvCoreIbexSmcFatalSwErr = 71, /**< rv_core_ibex_smc_fatal_sw_err */
+ kTopMatchaAlertIdRvCoreIbexSmcRecovSwErr = 72, /**< rv_core_ibex_smc_recov_sw_err */
+ kTopMatchaAlertIdRvCoreIbexSmcFatalHwErr = 73, /**< rv_core_ibex_smc_fatal_hw_err */
+ kTopMatchaAlertIdRvCoreIbexSmcRecovHwErr = 74, /**< rv_core_ibex_smc_recov_hw_err */
+ kTopMatchaAlertIdLast = 74, /**< \internal The Last Valid Alert ID. */
+} top_sencha_alert_id_t;
+
+/**
+ * Alert Handler Alert Source to Peripheral Map
+ *
+ * This array is a mapping from `top_sencha_alert_id_t` to
+ * `top_sencha_alert_peripheral_t`.
+ */
+extern const top_sencha_alert_peripheral_t
+ top_sencha_alert_for_peripheral[75];
+
+#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
+
+// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
+// 0 and 1 are tied to value 0 and 1
+#define NUM_MIO_PADS 53
+#define NUM_DIO_PADS 16
+
+#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
+
+/**
+ * Pinmux Peripheral Input.
+ */
+typedef enum top_sencha_pinmux_peripheral_in {
+ kTopMatchaPinmuxPeripheralInGpioGpio0 = 0, /**< Peripheral Input 0 */
+ kTopMatchaPinmuxPeripheralInGpioGpio1 = 1, /**< Peripheral Input 1 */
+ kTopMatchaPinmuxPeripheralInGpioGpio2 = 2, /**< Peripheral Input 2 */
+ kTopMatchaPinmuxPeripheralInGpioGpio3 = 3, /**< Peripheral Input 3 */
+ kTopMatchaPinmuxPeripheralInGpioGpio4 = 4, /**< Peripheral Input 4 */
+ kTopMatchaPinmuxPeripheralInGpioGpio5 = 5, /**< Peripheral Input 5 */
+ kTopMatchaPinmuxPeripheralInGpioGpio6 = 6, /**< Peripheral Input 6 */
+ kTopMatchaPinmuxPeripheralInGpioGpio7 = 7, /**< Peripheral Input 7 */
+ kTopMatchaPinmuxPeripheralInGpioGpio8 = 8, /**< Peripheral Input 8 */
+ kTopMatchaPinmuxPeripheralInGpioGpio9 = 9, /**< Peripheral Input 9 */
+ kTopMatchaPinmuxPeripheralInGpioGpio10 = 10, /**< Peripheral Input 10 */
+ kTopMatchaPinmuxPeripheralInGpioGpio11 = 11, /**< Peripheral Input 11 */
+ kTopMatchaPinmuxPeripheralInGpioGpio12 = 12, /**< Peripheral Input 12 */
+ kTopMatchaPinmuxPeripheralInGpioGpio13 = 13, /**< Peripheral Input 13 */
+ kTopMatchaPinmuxPeripheralInGpioGpio14 = 14, /**< Peripheral Input 14 */
+ kTopMatchaPinmuxPeripheralInGpioGpio15 = 15, /**< Peripheral Input 15 */
+ kTopMatchaPinmuxPeripheralInGpioGpio16 = 16, /**< Peripheral Input 16 */
+ kTopMatchaPinmuxPeripheralInGpioGpio17 = 17, /**< Peripheral Input 17 */
+ kTopMatchaPinmuxPeripheralInGpioGpio18 = 18, /**< Peripheral Input 18 */
+ kTopMatchaPinmuxPeripheralInGpioGpio19 = 19, /**< Peripheral Input 19 */
+ kTopMatchaPinmuxPeripheralInGpioGpio20 = 20, /**< Peripheral Input 20 */
+ kTopMatchaPinmuxPeripheralInGpioGpio21 = 21, /**< Peripheral Input 21 */
+ kTopMatchaPinmuxPeripheralInGpioGpio22 = 22, /**< Peripheral Input 22 */
+ kTopMatchaPinmuxPeripheralInGpioGpio23 = 23, /**< Peripheral Input 23 */
+ kTopMatchaPinmuxPeripheralInGpioGpio24 = 24, /**< Peripheral Input 24 */
+ kTopMatchaPinmuxPeripheralInGpioGpio25 = 25, /**< Peripheral Input 25 */
+ kTopMatchaPinmuxPeripheralInGpioGpio26 = 26, /**< Peripheral Input 26 */
+ kTopMatchaPinmuxPeripheralInGpioGpio27 = 27, /**< Peripheral Input 27 */
+ kTopMatchaPinmuxPeripheralInGpioGpio28 = 28, /**< Peripheral Input 28 */
+ kTopMatchaPinmuxPeripheralInGpioGpio29 = 29, /**< Peripheral Input 29 */
+ kTopMatchaPinmuxPeripheralInGpioGpio30 = 30, /**< Peripheral Input 30 */
+ kTopMatchaPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */
+ kTopMatchaPinmuxPeripheralInI2c0Sda = 32, /**< Peripheral Input 32 */
+ kTopMatchaPinmuxPeripheralInI2c0Scl = 33, /**< Peripheral Input 33 */
+ kTopMatchaPinmuxPeripheralInI2c1Sda = 34, /**< Peripheral Input 34 */
+ kTopMatchaPinmuxPeripheralInI2c1Scl = 35, /**< Peripheral Input 35 */
+ kTopMatchaPinmuxPeripheralInI2c2Sda = 36, /**< Peripheral Input 36 */
+ kTopMatchaPinmuxPeripheralInI2c2Scl = 37, /**< Peripheral Input 37 */
+ kTopMatchaPinmuxPeripheralInCamI2cSda = 38, /**< Peripheral Input 38 */
+ kTopMatchaPinmuxPeripheralInCamI2cScl = 39, /**< Peripheral Input 39 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperAudioI2sWs = 40, /**< Peripheral Input 40 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperAudioI2sSck = 41, /**< Peripheral Input 41 */
+ kTopMatchaPinmuxPeripheralInSpiHost1Sd0 = 42, /**< Peripheral Input 42 */
+ kTopMatchaPinmuxPeripheralInSpiHost1Sd1 = 43, /**< Peripheral Input 43 */
+ kTopMatchaPinmuxPeripheralInSpiHost1Sd2 = 44, /**< Peripheral Input 44 */
+ kTopMatchaPinmuxPeripheralInSpiHost1Sd3 = 45, /**< Peripheral Input 45 */
+ kTopMatchaPinmuxPeripheralInSpiHost2Sd0 = 46, /**< Peripheral Input 46 */
+ kTopMatchaPinmuxPeripheralInSpiHost2Sd1 = 47, /**< Peripheral Input 47 */
+ kTopMatchaPinmuxPeripheralInSpiHost2Sd2 = 48, /**< Peripheral Input 48 */
+ kTopMatchaPinmuxPeripheralInSpiHost2Sd3 = 49, /**< Peripheral Input 49 */
+ kTopMatchaPinmuxPeripheralInUart0Rx = 50, /**< Peripheral Input 50 */
+ kTopMatchaPinmuxPeripheralInUart1Rx = 51, /**< Peripheral Input 51 */
+ kTopMatchaPinmuxPeripheralInUart2Rx = 52, /**< Peripheral Input 52 */
+ kTopMatchaPinmuxPeripheralInSmcUartRx = 53, /**< Peripheral Input 53 */
+ kTopMatchaPinmuxPeripheralInCamCtrlCamInt = 54, /**< Peripheral Input 54 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData0 = 55, /**< Peripheral Input 55 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData1 = 56, /**< Peripheral Input 56 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData2 = 57, /**< Peripheral Input 57 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData3 = 58, /**< Peripheral Input 58 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData4 = 59, /**< Peripheral Input 59 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData5 = 60, /**< Peripheral Input 60 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData6 = 61, /**< Peripheral Input 61 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData7 = 62, /**< Peripheral Input 62 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSHsync = 63, /**< Peripheral Input 63 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSVsync = 64, /**< Peripheral Input 64 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperAudioPdmDat = 65, /**< Peripheral Input 65 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperJtagTck = 66, /**< Peripheral Input 66 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperJtagTms = 67, /**< Peripheral Input 67 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperJtagTdi = 68, /**< Peripheral Input 68 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperJtagRstn = 69, /**< Peripheral Input 69 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperAudioI2sSdIn = 70, /**< Peripheral Input 70 */
+ kTopMatchaPinmuxPeripheralInVsiCtlWrapperIspSclk = 71, /**< Peripheral Input 71 */
+ kTopMatchaPinmuxPeripheralInI2s0RxSd = 72, /**< Peripheral Input 72 */
+ kTopMatchaPinmuxPeripheralInSpiDeviceTpmCsb = 73, /**< Peripheral Input 73 */
+ kTopMatchaPinmuxPeripheralInFlashCtrlTck = 74, /**< Peripheral Input 74 */
+ kTopMatchaPinmuxPeripheralInFlashCtrlTms = 75, /**< Peripheral Input 75 */
+ kTopMatchaPinmuxPeripheralInFlashCtrlTdi = 76, /**< Peripheral Input 76 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonAcPresent = 77, /**< Peripheral Input 77 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey0In = 78, /**< Peripheral Input 78 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey1In = 79, /**< Peripheral Input 79 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey2In = 80, /**< Peripheral Input 80 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonPwrbIn = 81, /**< Peripheral Input 81 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonLidOpen = 82, /**< Peripheral Input 82 */
+ kTopMatchaPinmuxPeripheralInUsbdevSense = 83, /**< Peripheral Input 83 */
+ kTopMatchaPinmuxPeripheralInLast = 83, /**< \internal Last valid peripheral input */
+} top_sencha_pinmux_peripheral_in_t;
+
+/**
+ * Pinmux MIO Input Selector.
+ */
+typedef enum top_sencha_pinmux_insel {
+ kTopMatchaPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
+ kTopMatchaPinmuxInselConstantOne = 1, /**< Tie constantly to one */
+ kTopMatchaPinmuxInselIoa0 = 2, /**< MIO Pad 0 */
+ kTopMatchaPinmuxInselIoa1 = 3, /**< MIO Pad 1 */
+ kTopMatchaPinmuxInselIoa2 = 4, /**< MIO Pad 2 */
+ kTopMatchaPinmuxInselIoa3 = 5, /**< MIO Pad 3 */
+ kTopMatchaPinmuxInselIoa4 = 6, /**< MIO Pad 4 */
+ kTopMatchaPinmuxInselIoa5 = 7, /**< MIO Pad 5 */
+ kTopMatchaPinmuxInselIoa6 = 8, /**< MIO Pad 6 */
+ kTopMatchaPinmuxInselIoa7 = 9, /**< MIO Pad 7 */
+ kTopMatchaPinmuxInselIoa8 = 10, /**< MIO Pad 8 */
+ kTopMatchaPinmuxInselIob0 = 11, /**< MIO Pad 9 */
+ kTopMatchaPinmuxInselIob1 = 12, /**< MIO Pad 10 */
+ kTopMatchaPinmuxInselIob2 = 13, /**< MIO Pad 11 */
+ kTopMatchaPinmuxInselIob3 = 14, /**< MIO Pad 12 */
+ kTopMatchaPinmuxInselIob4 = 15, /**< MIO Pad 13 */
+ kTopMatchaPinmuxInselIob5 = 16, /**< MIO Pad 14 */
+ kTopMatchaPinmuxInselIob6 = 17, /**< MIO Pad 15 */
+ kTopMatchaPinmuxInselIob7 = 18, /**< MIO Pad 16 */
+ kTopMatchaPinmuxInselIob8 = 19, /**< MIO Pad 17 */
+ kTopMatchaPinmuxInselIob9 = 20, /**< MIO Pad 18 */
+ kTopMatchaPinmuxInselIob10 = 21, /**< MIO Pad 19 */
+ kTopMatchaPinmuxInselIob11 = 22, /**< MIO Pad 20 */
+ kTopMatchaPinmuxInselIob12 = 23, /**< MIO Pad 21 */
+ kTopMatchaPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
+ kTopMatchaPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
+ kTopMatchaPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
+ kTopMatchaPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
+ kTopMatchaPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
+ kTopMatchaPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
+ kTopMatchaPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
+ kTopMatchaPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
+ kTopMatchaPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
+ kTopMatchaPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
+ kTopMatchaPinmuxInselIoc10 = 34, /**< MIO Pad 32 */
+ kTopMatchaPinmuxInselIoc11 = 35, /**< MIO Pad 33 */
+ kTopMatchaPinmuxInselIoc12 = 36, /**< MIO Pad 34 */
+ kTopMatchaPinmuxInselIor0 = 37, /**< MIO Pad 35 */
+ kTopMatchaPinmuxInselIor1 = 38, /**< MIO Pad 36 */
+ kTopMatchaPinmuxInselIor2 = 39, /**< MIO Pad 37 */
+ kTopMatchaPinmuxInselIor3 = 40, /**< MIO Pad 38 */
+ kTopMatchaPinmuxInselIor4 = 41, /**< MIO Pad 39 */
+ kTopMatchaPinmuxInselIor5 = 42, /**< MIO Pad 40 */
+ kTopMatchaPinmuxInselIor6 = 43, /**< MIO Pad 41 */
+ kTopMatchaPinmuxInselIor7 = 44, /**< MIO Pad 42 */
+ kTopMatchaPinmuxInselIor10 = 45, /**< MIO Pad 43 */
+ kTopMatchaPinmuxInselIor11 = 46, /**< MIO Pad 44 */
+ kTopMatchaPinmuxInselIor12 = 47, /**< MIO Pad 45 */
+ kTopMatchaPinmuxInselIor13 = 48, /**< MIO Pad 46 */
+ kTopMatchaPinmuxInselIod0 = 49, /**< MIO Pad 47 */
+ kTopMatchaPinmuxInselIod1 = 50, /**< MIO Pad 48 */
+ kTopMatchaPinmuxInselIod2 = 51, /**< MIO Pad 49 */
+ kTopMatchaPinmuxInselIod3 = 52, /**< MIO Pad 50 */
+ kTopMatchaPinmuxInselIod4 = 53, /**< MIO Pad 51 */
+ kTopMatchaPinmuxInselIod5 = 54, /**< MIO Pad 52 */
+ kTopMatchaPinmuxInselLast = 54, /**< \internal Last valid insel value */
+} top_sencha_pinmux_insel_t;
+
+/**
+ * Pinmux MIO Output.
+ */
+typedef enum top_sencha_pinmux_mio_out {
+ kTopMatchaPinmuxMioOutIoa0 = 0, /**< MIO Pad 0 */
+ kTopMatchaPinmuxMioOutIoa1 = 1, /**< MIO Pad 1 */
+ kTopMatchaPinmuxMioOutIoa2 = 2, /**< MIO Pad 2 */
+ kTopMatchaPinmuxMioOutIoa3 = 3, /**< MIO Pad 3 */
+ kTopMatchaPinmuxMioOutIoa4 = 4, /**< MIO Pad 4 */
+ kTopMatchaPinmuxMioOutIoa5 = 5, /**< MIO Pad 5 */
+ kTopMatchaPinmuxMioOutIoa6 = 6, /**< MIO Pad 6 */
+ kTopMatchaPinmuxMioOutIoa7 = 7, /**< MIO Pad 7 */
+ kTopMatchaPinmuxMioOutIoa8 = 8, /**< MIO Pad 8 */
+ kTopMatchaPinmuxMioOutIob0 = 9, /**< MIO Pad 9 */
+ kTopMatchaPinmuxMioOutIob1 = 10, /**< MIO Pad 10 */
+ kTopMatchaPinmuxMioOutIob2 = 11, /**< MIO Pad 11 */
+ kTopMatchaPinmuxMioOutIob3 = 12, /**< MIO Pad 12 */
+ kTopMatchaPinmuxMioOutIob4 = 13, /**< MIO Pad 13 */
+ kTopMatchaPinmuxMioOutIob5 = 14, /**< MIO Pad 14 */
+ kTopMatchaPinmuxMioOutIob6 = 15, /**< MIO Pad 15 */
+ kTopMatchaPinmuxMioOutIob7 = 16, /**< MIO Pad 16 */
+ kTopMatchaPinmuxMioOutIob8 = 17, /**< MIO Pad 17 */
+ kTopMatchaPinmuxMioOutIob9 = 18, /**< MIO Pad 18 */
+ kTopMatchaPinmuxMioOutIob10 = 19, /**< MIO Pad 19 */
+ kTopMatchaPinmuxMioOutIob11 = 20, /**< MIO Pad 20 */
+ kTopMatchaPinmuxMioOutIob12 = 21, /**< MIO Pad 21 */
+ kTopMatchaPinmuxMioOutIoc0 = 22, /**< MIO Pad 22 */
+ kTopMatchaPinmuxMioOutIoc1 = 23, /**< MIO Pad 23 */
+ kTopMatchaPinmuxMioOutIoc2 = 24, /**< MIO Pad 24 */
+ kTopMatchaPinmuxMioOutIoc3 = 25, /**< MIO Pad 25 */
+ kTopMatchaPinmuxMioOutIoc4 = 26, /**< MIO Pad 26 */
+ kTopMatchaPinmuxMioOutIoc5 = 27, /**< MIO Pad 27 */
+ kTopMatchaPinmuxMioOutIoc6 = 28, /**< MIO Pad 28 */
+ kTopMatchaPinmuxMioOutIoc7 = 29, /**< MIO Pad 29 */
+ kTopMatchaPinmuxMioOutIoc8 = 30, /**< MIO Pad 30 */
+ kTopMatchaPinmuxMioOutIoc9 = 31, /**< MIO Pad 31 */
+ kTopMatchaPinmuxMioOutIoc10 = 32, /**< MIO Pad 32 */
+ kTopMatchaPinmuxMioOutIoc11 = 33, /**< MIO Pad 33 */
+ kTopMatchaPinmuxMioOutIoc12 = 34, /**< MIO Pad 34 */
+ kTopMatchaPinmuxMioOutIor0 = 35, /**< MIO Pad 35 */
+ kTopMatchaPinmuxMioOutIor1 = 36, /**< MIO Pad 36 */
+ kTopMatchaPinmuxMioOutIor2 = 37, /**< MIO Pad 37 */
+ kTopMatchaPinmuxMioOutIor3 = 38, /**< MIO Pad 38 */
+ kTopMatchaPinmuxMioOutIor4 = 39, /**< MIO Pad 39 */
+ kTopMatchaPinmuxMioOutIor5 = 40, /**< MIO Pad 40 */
+ kTopMatchaPinmuxMioOutIor6 = 41, /**< MIO Pad 41 */
+ kTopMatchaPinmuxMioOutIor7 = 42, /**< MIO Pad 42 */
+ kTopMatchaPinmuxMioOutIor10 = 43, /**< MIO Pad 43 */
+ kTopMatchaPinmuxMioOutIor11 = 44, /**< MIO Pad 44 */
+ kTopMatchaPinmuxMioOutIor12 = 45, /**< MIO Pad 45 */
+ kTopMatchaPinmuxMioOutIor13 = 46, /**< MIO Pad 46 */
+ kTopMatchaPinmuxMioOutIod0 = 47, /**< MIO Pad 47 */
+ kTopMatchaPinmuxMioOutIod1 = 48, /**< MIO Pad 48 */
+ kTopMatchaPinmuxMioOutIod2 = 49, /**< MIO Pad 49 */
+ kTopMatchaPinmuxMioOutIod3 = 50, /**< MIO Pad 50 */
+ kTopMatchaPinmuxMioOutIod4 = 51, /**< MIO Pad 51 */
+ kTopMatchaPinmuxMioOutIod5 = 52, /**< MIO Pad 52 */
+ kTopMatchaPinmuxMioOutLast = 52, /**< \internal Last valid mio output */
+} top_sencha_pinmux_mio_out_t;
+
+/**
+ * Pinmux Peripheral Output Selector.
+ */
+typedef enum top_sencha_pinmux_outsel {
+ kTopMatchaPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
+ kTopMatchaPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
+ kTopMatchaPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
+ kTopMatchaPinmuxOutselGpioGpio0 = 3, /**< Peripheral Output 0 */
+ kTopMatchaPinmuxOutselGpioGpio1 = 4, /**< Peripheral Output 1 */
+ kTopMatchaPinmuxOutselGpioGpio2 = 5, /**< Peripheral Output 2 */
+ kTopMatchaPinmuxOutselGpioGpio3 = 6, /**< Peripheral Output 3 */
+ kTopMatchaPinmuxOutselGpioGpio4 = 7, /**< Peripheral Output 4 */
+ kTopMatchaPinmuxOutselGpioGpio5 = 8, /**< Peripheral Output 5 */
+ kTopMatchaPinmuxOutselGpioGpio6 = 9, /**< Peripheral Output 6 */
+ kTopMatchaPinmuxOutselGpioGpio7 = 10, /**< Peripheral Output 7 */
+ kTopMatchaPinmuxOutselGpioGpio8 = 11, /**< Peripheral Output 8 */
+ kTopMatchaPinmuxOutselGpioGpio9 = 12, /**< Peripheral Output 9 */
+ kTopMatchaPinmuxOutselGpioGpio10 = 13, /**< Peripheral Output 10 */
+ kTopMatchaPinmuxOutselGpioGpio11 = 14, /**< Peripheral Output 11 */
+ kTopMatchaPinmuxOutselGpioGpio12 = 15, /**< Peripheral Output 12 */
+ kTopMatchaPinmuxOutselGpioGpio13 = 16, /**< Peripheral Output 13 */
+ kTopMatchaPinmuxOutselGpioGpio14 = 17, /**< Peripheral Output 14 */
+ kTopMatchaPinmuxOutselGpioGpio15 = 18, /**< Peripheral Output 15 */
+ kTopMatchaPinmuxOutselGpioGpio16 = 19, /**< Peripheral Output 16 */
+ kTopMatchaPinmuxOutselGpioGpio17 = 20, /**< Peripheral Output 17 */
+ kTopMatchaPinmuxOutselGpioGpio18 = 21, /**< Peripheral Output 18 */
+ kTopMatchaPinmuxOutselGpioGpio19 = 22, /**< Peripheral Output 19 */
+ kTopMatchaPinmuxOutselGpioGpio20 = 23, /**< Peripheral Output 20 */
+ kTopMatchaPinmuxOutselGpioGpio21 = 24, /**< Peripheral Output 21 */
+ kTopMatchaPinmuxOutselGpioGpio22 = 25, /**< Peripheral Output 22 */
+ kTopMatchaPinmuxOutselGpioGpio23 = 26, /**< Peripheral Output 23 */
+ kTopMatchaPinmuxOutselGpioGpio24 = 27, /**< Peripheral Output 24 */
+ kTopMatchaPinmuxOutselGpioGpio25 = 28, /**< Peripheral Output 25 */
+ kTopMatchaPinmuxOutselGpioGpio26 = 29, /**< Peripheral Output 26 */
+ kTopMatchaPinmuxOutselGpioGpio27 = 30, /**< Peripheral Output 27 */
+ kTopMatchaPinmuxOutselGpioGpio28 = 31, /**< Peripheral Output 28 */
+ kTopMatchaPinmuxOutselGpioGpio29 = 32, /**< Peripheral Output 29 */
+ kTopMatchaPinmuxOutselGpioGpio30 = 33, /**< Peripheral Output 30 */
+ kTopMatchaPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */
+ kTopMatchaPinmuxOutselI2c0Sda = 35, /**< Peripheral Output 32 */
+ kTopMatchaPinmuxOutselI2c0Scl = 36, /**< Peripheral Output 33 */
+ kTopMatchaPinmuxOutselI2c1Sda = 37, /**< Peripheral Output 34 */
+ kTopMatchaPinmuxOutselI2c1Scl = 38, /**< Peripheral Output 35 */
+ kTopMatchaPinmuxOutselI2c2Sda = 39, /**< Peripheral Output 36 */
+ kTopMatchaPinmuxOutselI2c2Scl = 40, /**< Peripheral Output 37 */
+ kTopMatchaPinmuxOutselCamI2cSda = 41, /**< Peripheral Output 38 */
+ kTopMatchaPinmuxOutselCamI2cScl = 42, /**< Peripheral Output 39 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperAudioI2sWs = 43, /**< Peripheral Output 40 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperAudioI2sSck = 44, /**< Peripheral Output 41 */
+ kTopMatchaPinmuxOutselSpiHost1Sd0 = 45, /**< Peripheral Output 42 */
+ kTopMatchaPinmuxOutselSpiHost1Sd1 = 46, /**< Peripheral Output 43 */
+ kTopMatchaPinmuxOutselSpiHost1Sd2 = 47, /**< Peripheral Output 44 */
+ kTopMatchaPinmuxOutselSpiHost1Sd3 = 48, /**< Peripheral Output 45 */
+ kTopMatchaPinmuxOutselSpiHost2Sd0 = 49, /**< Peripheral Output 46 */
+ kTopMatchaPinmuxOutselSpiHost2Sd1 = 50, /**< Peripheral Output 47 */
+ kTopMatchaPinmuxOutselSpiHost2Sd2 = 51, /**< Peripheral Output 48 */
+ kTopMatchaPinmuxOutselSpiHost2Sd3 = 52, /**< Peripheral Output 49 */
+ kTopMatchaPinmuxOutselUart0Tx = 53, /**< Peripheral Output 50 */
+ kTopMatchaPinmuxOutselUart1Tx = 54, /**< Peripheral Output 51 */
+ kTopMatchaPinmuxOutselUart2Tx = 55, /**< Peripheral Output 52 */
+ kTopMatchaPinmuxOutselSmcUartTx = 56, /**< Peripheral Output 53 */
+ kTopMatchaPinmuxOutselCamCtrlCamTrig = 57, /**< Peripheral Output 54 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperJtagTdo = 58, /**< Peripheral Output 55 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperAudioPdmClk = 59, /**< Peripheral Output 56 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperAudioI2sSdOut = 60, /**< Peripheral Output 57 */
+ kTopMatchaPinmuxOutselVsiCtlWrapperPllSysClkoDiv8 = 61, /**< Peripheral Output 58 */
+ kTopMatchaPinmuxOutselVsiCtlWrapperPllMlClkoDiv8 = 62, /**< Peripheral Output 59 */
+ kTopMatchaPinmuxOutselVsiCtlWrapperPllAudioClkoDiv8 = 63, /**< Peripheral Output 60 */
+ kTopMatchaPinmuxOutselI2s0RxSclk = 64, /**< Peripheral Output 61 */
+ kTopMatchaPinmuxOutselI2s0RxWs = 65, /**< Peripheral Output 62 */
+ kTopMatchaPinmuxOutselI2s0TxSclk = 66, /**< Peripheral Output 63 */
+ kTopMatchaPinmuxOutselI2s0TxWs = 67, /**< Peripheral Output 64 */
+ kTopMatchaPinmuxOutselI2s0TxSd = 68, /**< Peripheral Output 65 */
+ kTopMatchaPinmuxOutselPattgenPda0Tx = 69, /**< Peripheral Output 66 */
+ kTopMatchaPinmuxOutselPattgenPcl0Tx = 70, /**< Peripheral Output 67 */
+ kTopMatchaPinmuxOutselPattgenPda1Tx = 71, /**< Peripheral Output 68 */
+ kTopMatchaPinmuxOutselPattgenPcl1Tx = 72, /**< Peripheral Output 69 */
+ kTopMatchaPinmuxOutselSpiHost1Sck = 73, /**< Peripheral Output 70 */
+ kTopMatchaPinmuxOutselSpiHost1Csb = 74, /**< Peripheral Output 71 */
+ kTopMatchaPinmuxOutselSpiHost2Sck = 75, /**< Peripheral Output 72 */
+ kTopMatchaPinmuxOutselSpiHost2Csb = 76, /**< Peripheral Output 73 */
+ kTopMatchaPinmuxOutselFlashCtrlTdo = 77, /**< Peripheral Output 74 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut0 = 78, /**< Peripheral Output 75 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut1 = 79, /**< Peripheral Output 76 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut2 = 80, /**< Peripheral Output 77 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut3 = 81, /**< Peripheral Output 78 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut4 = 82, /**< Peripheral Output 79 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut5 = 83, /**< Peripheral Output 80 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut6 = 84, /**< Peripheral Output 81 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut7 = 85, /**< Peripheral Output 82 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut8 = 86, /**< Peripheral Output 83 */
+ kTopMatchaPinmuxOutselPwmAonPwm0 = 87, /**< Peripheral Output 84 */
+ kTopMatchaPinmuxOutselPwmAonPwm1 = 88, /**< Peripheral Output 85 */
+ kTopMatchaPinmuxOutselPwmAonPwm2 = 89, /**< Peripheral Output 86 */
+ kTopMatchaPinmuxOutselPwmAonPwm3 = 90, /**< Peripheral Output 87 */
+ kTopMatchaPinmuxOutselPwmAonPwm4 = 91, /**< Peripheral Output 88 */
+ kTopMatchaPinmuxOutselPwmAonPwm5 = 92, /**< Peripheral Output 89 */
+ kTopMatchaPinmuxOutselOtpCtrlTest0 = 93, /**< Peripheral Output 90 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonBatDisable = 94, /**< Peripheral Output 91 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonKey0Out = 95, /**< Peripheral Output 92 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonKey1Out = 96, /**< Peripheral Output 93 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonKey2Out = 97, /**< Peripheral Output 94 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonPwrbOut = 98, /**< Peripheral Output 95 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonZ3Wakeup = 99, /**< Peripheral Output 96 */
+ kTopMatchaPinmuxOutselLast = 99, /**< \internal Last valid outsel value */
+} top_sencha_pinmux_outsel_t;
+
+/**
+ * Dedicated Pad Selects
+ */
+typedef enum top_sencha_direct_pads {
+ kTopMatchaDirectPadsUsbdevUsbDp = 0, /**< */
+ kTopMatchaDirectPadsUsbdevUsbDn = 1, /**< */
+ kTopMatchaDirectPadsSpiHost0Sd0 = 2, /**< */
+ kTopMatchaDirectPadsSpiHost0Sd1 = 3, /**< */
+ kTopMatchaDirectPadsSpiHost0Sd2 = 4, /**< */
+ kTopMatchaDirectPadsSpiHost0Sd3 = 5, /**< */
+ kTopMatchaDirectPadsSpiDeviceSd0 = 6, /**< */
+ kTopMatchaDirectPadsSpiDeviceSd1 = 7, /**< */
+ kTopMatchaDirectPadsSpiDeviceSd2 = 8, /**< */
+ kTopMatchaDirectPadsSpiDeviceSd3 = 9, /**< */
+ kTopMatchaDirectPadsSysrstCtrlAonEcRstL = 10, /**< */
+ kTopMatchaDirectPadsSysrstCtrlAonFlashWpL = 11, /**< */
+ kTopMatchaDirectPadsSpiDeviceSck = 12, /**< */
+ kTopMatchaDirectPadsSpiDeviceCsb = 13, /**< */
+ kTopMatchaDirectPadsSpiHost0Sck = 14, /**< */
+ kTopMatchaDirectPadsSpiHost0Csb = 15, /**< */
+ kTopMatchaDirectPadsLast = 15, /**< \internal Last valid direct pad */
+} top_sencha_direct_pads_t;
+
+/**
+ * Muxed Pad Selects
+ */
+typedef enum top_sencha_muxed_pads {
+ kTopMatchaMuxedPadsIoa0 = 0, /**< */
+ kTopMatchaMuxedPadsIoa1 = 1, /**< */
+ kTopMatchaMuxedPadsIoa2 = 2, /**< */
+ kTopMatchaMuxedPadsIoa3 = 3, /**< */
+ kTopMatchaMuxedPadsIoa4 = 4, /**< */
+ kTopMatchaMuxedPadsIoa5 = 5, /**< */
+ kTopMatchaMuxedPadsIoa6 = 6, /**< */
+ kTopMatchaMuxedPadsIoa7 = 7, /**< */
+ kTopMatchaMuxedPadsIoa8 = 8, /**< */
+ kTopMatchaMuxedPadsIob0 = 9, /**< */
+ kTopMatchaMuxedPadsIob1 = 10, /**< */
+ kTopMatchaMuxedPadsIob2 = 11, /**< */
+ kTopMatchaMuxedPadsIob3 = 12, /**< */
+ kTopMatchaMuxedPadsIob4 = 13, /**< */
+ kTopMatchaMuxedPadsIob5 = 14, /**< */
+ kTopMatchaMuxedPadsIob6 = 15, /**< */
+ kTopMatchaMuxedPadsIob7 = 16, /**< */
+ kTopMatchaMuxedPadsIob8 = 17, /**< */
+ kTopMatchaMuxedPadsIob9 = 18, /**< */
+ kTopMatchaMuxedPadsIob10 = 19, /**< */
+ kTopMatchaMuxedPadsIob11 = 20, /**< */
+ kTopMatchaMuxedPadsIob12 = 21, /**< */
+ kTopMatchaMuxedPadsIoc0 = 22, /**< */
+ kTopMatchaMuxedPadsIoc1 = 23, /**< */
+ kTopMatchaMuxedPadsIoc2 = 24, /**< */
+ kTopMatchaMuxedPadsIoc3 = 25, /**< */
+ kTopMatchaMuxedPadsIoc4 = 26, /**< */
+ kTopMatchaMuxedPadsIoc5 = 27, /**< */
+ kTopMatchaMuxedPadsIoc6 = 28, /**< */
+ kTopMatchaMuxedPadsIoc7 = 29, /**< */
+ kTopMatchaMuxedPadsIoc8 = 30, /**< */
+ kTopMatchaMuxedPadsIoc9 = 31, /**< */
+ kTopMatchaMuxedPadsIoc10 = 32, /**< */
+ kTopMatchaMuxedPadsIoc11 = 33, /**< */
+ kTopMatchaMuxedPadsIoc12 = 34, /**< */
+ kTopMatchaMuxedPadsIor0 = 35, /**< */
+ kTopMatchaMuxedPadsIor1 = 36, /**< */
+ kTopMatchaMuxedPadsIor2 = 37, /**< */
+ kTopMatchaMuxedPadsIor3 = 38, /**< */
+ kTopMatchaMuxedPadsIor4 = 39, /**< */
+ kTopMatchaMuxedPadsIor5 = 40, /**< */
+ kTopMatchaMuxedPadsIor6 = 41, /**< */
+ kTopMatchaMuxedPadsIor7 = 42, /**< */
+ kTopMatchaMuxedPadsIor10 = 43, /**< */
+ kTopMatchaMuxedPadsIor11 = 44, /**< */
+ kTopMatchaMuxedPadsIor12 = 45, /**< */
+ kTopMatchaMuxedPadsIor13 = 46, /**< */
+ kTopMatchaMuxedPadsIod0 = 47, /**< */
+ kTopMatchaMuxedPadsIod1 = 48, /**< */
+ kTopMatchaMuxedPadsIod2 = 49, /**< */
+ kTopMatchaMuxedPadsIod3 = 50, /**< */
+ kTopMatchaMuxedPadsIod4 = 51, /**< */
+ kTopMatchaMuxedPadsIod5 = 52, /**< */
+ kTopMatchaMuxedPadsLast = 52, /**< \internal Last valid muxed pad */
+} top_sencha_muxed_pads_t;
+
+/**
+ * Power Manager Wakeup Signals
+ */
+typedef enum top_sencha_power_manager_wake_ups {
+ kTopMatchaPowerManagerWakeUpsSysrstCtrlAonWkupReq = 0, /**< */
+ kTopMatchaPowerManagerWakeUpsAdcCtrlAonWkupReq = 1, /**< */
+ kTopMatchaPowerManagerWakeUpsPinmuxAonPinWkupReq = 2, /**< */
+ kTopMatchaPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3, /**< */
+ kTopMatchaPowerManagerWakeUpsAonTimerAonWkupReq = 4, /**< */
+ kTopMatchaPowerManagerWakeUpsSensorCtrlWkupReq = 5, /**< */
+ kTopMatchaPowerManagerWakeUpsLast = 5, /**< \internal Last valid pwrmgr wakeup signal */
+} top_sencha_power_manager_wake_ups_t;
+
+/**
+ * Reset Manager Software Controlled Resets
+ */
+typedef enum top_sencha_reset_manager_sw_resets {
+ kTopMatchaResetManagerSwResetsSpiDevice = 0, /**< */
+ kTopMatchaResetManagerSwResetsSpiHost0 = 1, /**< */
+ kTopMatchaResetManagerSwResetsSpiHost1 = 2, /**< */
+ kTopMatchaResetManagerSwResetsSpiHost2 = 3, /**< */
+ kTopMatchaResetManagerSwResetsUsb = 4, /**< */
+ kTopMatchaResetManagerSwResetsUsbAon = 5, /**< */
+ kTopMatchaResetManagerSwResetsI2c0 = 6, /**< */
+ kTopMatchaResetManagerSwResetsI2c1 = 7, /**< */
+ kTopMatchaResetManagerSwResetsI2c2 = 8, /**< */
+ kTopMatchaResetManagerSwResetsSmc = 9, /**< */
+ kTopMatchaResetManagerSwResetsMl = 10, /**< */
+ kTopMatchaResetManagerSwResetsCamI2c = 11, /**< */
+ kTopMatchaResetManagerSwResetsVideo = 12, /**< */
+ kTopMatchaResetManagerSwResetsAudio = 13, /**< */
+ kTopMatchaResetManagerSwResetsLast = 13, /**< \internal Last valid rstmgr software reset request */
+} top_sencha_reset_manager_sw_resets_t;
+
+/**
+ * Power Manager Reset Request Signals
+ */
+typedef enum top_sencha_power_manager_reset_requests {
+ kTopMatchaPowerManagerResetRequestsSysrstCtrlAonRstReq = 0, /**< */
+ kTopMatchaPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1, /**< */
+ kTopMatchaPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */
+} top_sencha_power_manager_reset_requests_t;
+
+/**
+ * Clock Manager Software-Controlled ("Gated") Clocks.
+ *
+ * The Software has full control over these clocks.
+ */
+typedef enum top_sencha_gateable_clocks {
+ kTopMatchaGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
+ kTopMatchaGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
+ kTopMatchaGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
+ kTopMatchaGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
+ kTopMatchaGateableClocksMlPeri = 4, /**< Clock clk_ml_peri in group peri */
+ kTopMatchaGateableClocksAudioPeri = 5, /**< Clock clk_audio_peri in group peri */
+ kTopMatchaGateableClocksSmcPeri = 6, /**< Clock clk_smc_peri in group peri */
+ kTopMatchaGateableClocksLast = 6, /**< \internal Last Valid Gateable Clock */
+} top_sencha_gateable_clocks_t;
+
+/**
+ * Clock Manager Software-Hinted Clocks.
+ *
+ * The Software has partial control over these clocks. It can ask them to stop,
+ * but the clock manager is in control of whether the clock actually is stopped.
+ */
+typedef enum top_sencha_hintable_clocks {
+ kTopMatchaHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */
+ kTopMatchaHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */
+ kTopMatchaHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */
+ kTopMatchaHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */
+ kTopMatchaHintableClocksSmcVideoAudioWrapper = 4, /**< Clock clk_smc_video_audio_wrapper in group trans */
+ kTopMatchaHintableClocksVideoVsiCtlWrapper = 5, /**< Clock clk_video_vsi_ctl_wrapper in group trans */
+ kTopMatchaHintableClocksAudioVsiCtlWrapper = 6, /**< Clock clk_audio_vsi_ctl_wrapper in group trans */
+ kTopMatchaHintableClocksLast = 6, /**< \internal Last Valid Hintable Clock */
+} top_sencha_hintable_clocks_t;
+
+/**
+ * MMIO Region
+ *
+ * MMIO region excludes any memory that is separate from the module
+ * configuration space, i.e. ROM, main SRAM, and flash are excluded but
+ * retention SRAM, spi_device memory, or usbdev memory are included.
+ */
+#define TOP_MATCHA_MMIO_BASE_ADDR 0x40000000u
+#define TOP_MATCHA_MMIO_SIZE_BYTES 0x28000000u
+
+// Header Extern Guard
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_H_
diff --git a/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/top_sencha_memory.h b/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/top_sencha_memory.h
new file mode 100644
index 0000000..32d46ac
--- /dev/null
+++ b/hw/top_sencha/sparrow/hw/top_sencha/sw/autogen/top_sencha_memory.h
@@ -0,0 +1,1333 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_MEMORY_H_
+#define MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_MEMORY_H_
+
+/**
+ * @file
+ * @brief Assembler-only Top-Specific Definitions.
+ *
+ * This file contains preprocessor definitions for use within assembly code.
+ *
+ * These are not shared with C/C++ code because these are only allowed to be
+ * preprocessor definitions, no data or type declarations are allowed. The
+ * assembler is also stricter about literals (not allowing suffixes for
+ * signed/unsigned which are sensible to use for unsigned values in C/C++).
+ */
+
+// Include guard for assembler
+#ifdef __ASSEMBLER__
+
+
+/**
+ * Memory base for sram_ctrl_ret_aon_ram_ret_aon in top matcha.
+ */
+#define TOP_MATCHA_RAM_RET_AON_BASE_ADDR 0x40600000
+
+/**
+ * Memory size for sram_ctrl_ret_aon_ram_ret_aon in top matcha.
+ */
+#define TOP_MATCHA_RAM_RET_AON_SIZE_BYTES 0x1000
+
+/**
+ * Memory base for flash_ctrl_eflash in top matcha.
+ */
+#define TOP_MATCHA_EFLASH_BASE_ADDR 0x20000000
+
+/**
+ * Memory size for flash_ctrl_eflash in top matcha.
+ */
+#define TOP_MATCHA_EFLASH_SIZE_BYTES 0x100000
+
+/**
+ * Memory base for sram_ctrl_main_ram_main in top matcha.
+ */
+#define TOP_MATCHA_RAM_MAIN_BASE_ADDR 0x10000000
+
+/**
+ * Memory size for sram_ctrl_main_ram_main in top matcha.
+ */
+#define TOP_MATCHA_RAM_MAIN_SIZE_BYTES 0x20000
+
+/**
+ * Memory base for rom_ctrl_rom in top matcha.
+ */
+#define TOP_MATCHA_ROM_BASE_ADDR 0x00008000
+
+/**
+ * Memory size for rom_ctrl_rom in top matcha.
+ */
+#define TOP_MATCHA_ROM_SIZE_BYTES 0x8000
+
+/**
+ * Memory base for video_audio_wrapper_video_sram in top matcha.
+ */
+#define TOP_MATCHA_VIDEO_SRAM_BASE_ADDR 0x55000000
+
+/**
+ * Memory size for video_audio_wrapper_video_sram in top matcha.
+ */
+#define TOP_MATCHA_VIDEO_SRAM_SIZE_BYTES 0x200000
+
+/**
+ * Memory base for ml_top_ram_ml_dmem in top matcha.
+ */
+#define TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR 0x5A000000
+
+/**
+ * Memory size for ml_top_ram_ml_dmem in top matcha.
+ */
+#define TOP_MATCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000
+
+
+/**
+ * Memory base address for ram_smc in top matcha.
+ */
+#define TOP_MATCHA_RAM_SMC_BASE_ADDR 0x50000000
+
+/**
+ * Memory size for ram_smc in top matcha.
+ */
+#define TOP_MATCHA_RAM_SMC_SIZE_BYTES 0x400000
+
+
+/**
+ * Peripheral base address for uart0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART0_BASE_ADDR 0x40000000
+
+/**
+ * Peripheral size for uart0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART0_BASE_ADDR and
+ * `TOP_MATCHA_UART0_BASE_ADDR + TOP_MATCHA_UART0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for uart1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART1_BASE_ADDR 0x40010000
+
+/**
+ * Peripheral size for uart1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART1_BASE_ADDR and
+ * `TOP_MATCHA_UART1_BASE_ADDR + TOP_MATCHA_UART1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART1_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for uart2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART2_BASE_ADDR 0x40020000
+
+/**
+ * Peripheral size for uart2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART2_BASE_ADDR and
+ * `TOP_MATCHA_UART2_BASE_ADDR + TOP_MATCHA_UART2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART2_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for uart3 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART3_BASE_ADDR 0x40030000
+
+/**
+ * Peripheral size for uart3 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART3_BASE_ADDR and
+ * `TOP_MATCHA_UART3_BASE_ADDR + TOP_MATCHA_UART3_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART3_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for gpio in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_GPIO_BASE_ADDR 0x40040000
+
+/**
+ * Peripheral size for gpio in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_GPIO_BASE_ADDR and
+ * `TOP_MATCHA_GPIO_BASE_ADDR + TOP_MATCHA_GPIO_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_GPIO_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for spi_device in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_DEVICE_BASE_ADDR 0x40050000
+
+/**
+ * Peripheral size for spi_device in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_DEVICE_BASE_ADDR and
+ * `TOP_MATCHA_SPI_DEVICE_BASE_ADDR + TOP_MATCHA_SPI_DEVICE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_DEVICE_SIZE_BYTES 0x2000
+/**
+ * Peripheral base address for i2c0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C0_BASE_ADDR 0x40080000
+
+/**
+ * Peripheral size for i2c0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C0_BASE_ADDR and
+ * `TOP_MATCHA_I2C0_BASE_ADDR + TOP_MATCHA_I2C0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C0_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for i2c1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C1_BASE_ADDR 0x40090000
+
+/**
+ * Peripheral size for i2c1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C1_BASE_ADDR and
+ * `TOP_MATCHA_I2C1_BASE_ADDR + TOP_MATCHA_I2C1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C1_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for i2c2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C2_BASE_ADDR 0x400A0000
+
+/**
+ * Peripheral size for i2c2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C2_BASE_ADDR and
+ * `TOP_MATCHA_I2C2_BASE_ADDR + TOP_MATCHA_I2C2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C2_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for pattgen in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PATTGEN_BASE_ADDR 0x400E0000
+
+/**
+ * Peripheral size for pattgen in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PATTGEN_BASE_ADDR and
+ * `TOP_MATCHA_PATTGEN_BASE_ADDR + TOP_MATCHA_PATTGEN_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PATTGEN_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_timer in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_BASE_ADDR 0x40100000
+
+/**
+ * Peripheral size for rv_timer in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_BASE_ADDR + TOP_MATCHA_RV_TIMER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for core device on otp_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR 0x40130000
+
+/**
+ * Peripheral size for core device on otp_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR and
+ * `TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR + TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES 0x2000
+/**
+ * Peripheral base address for prim device on otp_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR 0x40132000
+
+/**
+ * Peripheral size for prim device on otp_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR and
+ * `TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES 0x20
+/**
+ * Peripheral base address for lc_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_LC_CTRL_BASE_ADDR 0x40140000
+
+/**
+ * Peripheral size for lc_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_LC_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_LC_CTRL_BASE_ADDR + TOP_MATCHA_LC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_LC_CTRL_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for alert_handler in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ALERT_HANDLER_BASE_ADDR 0x40150000
+
+/**
+ * Peripheral size for alert_handler in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ALERT_HANDLER_BASE_ADDR and
+ * `TOP_MATCHA_ALERT_HANDLER_BASE_ADDR + TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES 0x800
+/**
+ * Peripheral base address for spi_host0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST0_BASE_ADDR 0x40300000
+
+/**
+ * Peripheral size for spi_host0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST0_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST0_BASE_ADDR + TOP_MATCHA_SPI_HOST0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for spi_host1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST1_BASE_ADDR 0x40310000
+
+/**
+ * Peripheral size for spi_host1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST1_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST1_BASE_ADDR + TOP_MATCHA_SPI_HOST1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST1_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for usbdev in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_USBDEV_BASE_ADDR 0x40320000
+
+/**
+ * Peripheral size for usbdev in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_USBDEV_BASE_ADDR and
+ * `TOP_MATCHA_USBDEV_BASE_ADDR + TOP_MATCHA_USBDEV_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_USBDEV_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for pwrmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PWRMGR_AON_BASE_ADDR 0x40400000
+
+/**
+ * Peripheral size for pwrmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PWRMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_PWRMGR_AON_BASE_ADDR + TOP_MATCHA_PWRMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PWRMGR_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for rstmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RSTMGR_AON_BASE_ADDR 0x40410000
+
+/**
+ * Peripheral size for rstmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RSTMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_RSTMGR_AON_BASE_ADDR + TOP_MATCHA_RSTMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RSTMGR_AON_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for clkmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CLKMGR_AON_BASE_ADDR 0x40420000
+
+/**
+ * Peripheral size for clkmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CLKMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_CLKMGR_AON_BASE_ADDR + TOP_MATCHA_CLKMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CLKMGR_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for sysrst_ctrl_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR 0x40430000
+
+/**
+ * Peripheral size for sysrst_ctrl_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR and
+ * `TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR + TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for adc_ctrl_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR 0x40440000
+
+/**
+ * Peripheral size for adc_ctrl_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR and
+ * `TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR + TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for pwm_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PWM_AON_BASE_ADDR 0x40450000
+
+/**
+ * Peripheral size for pwm_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PWM_AON_BASE_ADDR and
+ * `TOP_MATCHA_PWM_AON_BASE_ADDR + TOP_MATCHA_PWM_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PWM_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for pinmux_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PINMUX_AON_BASE_ADDR 0x40460000
+
+/**
+ * Peripheral size for pinmux_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PINMUX_AON_BASE_ADDR and
+ * `TOP_MATCHA_PINMUX_AON_BASE_ADDR + TOP_MATCHA_PINMUX_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PINMUX_AON_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for aon_timer_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AON_TIMER_AON_BASE_ADDR 0x40470000
+
+/**
+ * Peripheral size for aon_timer_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AON_TIMER_AON_BASE_ADDR and
+ * `TOP_MATCHA_AON_TIMER_AON_BASE_ADDR + TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for ast in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AST_BASE_ADDR 0x40480000
+
+/**
+ * Peripheral size for ast in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AST_BASE_ADDR and
+ * `TOP_MATCHA_AST_BASE_ADDR + TOP_MATCHA_AST_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AST_SIZE_BYTES 0x400
+/**
+ * Peripheral base address for sensor_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SENSOR_CTRL_BASE_ADDR 0x40490000
+
+/**
+ * Peripheral size for sensor_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SENSOR_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_SENSOR_CTRL_BASE_ADDR + TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for ast_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AST_AON_BASE_ADDR 0x404C0000
+
+/**
+ * Peripheral size for ast_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AST_AON_BASE_ADDR and
+ * `TOP_MATCHA_AST_AON_BASE_ADDR + TOP_MATCHA_AST_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AST_AON_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for regs device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000
+
+/**
+ * Peripheral size for regs device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x20
+/**
+ * Peripheral base address for ram device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000
+
+/**
+ * Peripheral size for ram device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for core device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR 0x41000000
+
+/**
+ * Peripheral size for core device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for prim device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000
+
+/**
+ * Peripheral size for prim device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for mem device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR 0x20000000
+
+/**
+ * Peripheral size for mem device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES 0x100000
+/**
+ * Peripheral base address for regs device on rv_dm in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_DM_REGS_BASE_ADDR 0x6000
+
+/**
+ * Peripheral size for regs device on rv_dm in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_DM_REGS_BASE_ADDR and
+ * `TOP_MATCHA_RV_DM_REGS_BASE_ADDR + TOP_MATCHA_RV_DM_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_DM_REGS_SIZE_BYTES 0x4
+/**
+ * Peripheral base address for mem device on rv_dm in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_DM_MEM_BASE_ADDR 0x4000
+
+/**
+ * Peripheral size for mem device on rv_dm in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_DM_MEM_BASE_ADDR and
+ * `TOP_MATCHA_RV_DM_MEM_BASE_ADDR + TOP_MATCHA_RV_DM_MEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_DM_MEM_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for rv_plic in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_PLIC_BASE_ADDR 0x48000000
+
+/**
+ * Peripheral size for rv_plic in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_PLIC_BASE_ADDR and
+ * `TOP_MATCHA_RV_PLIC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_PLIC_SIZE_BYTES 0x8000000
+/**
+ * Peripheral base address for aes in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AES_BASE_ADDR 0x41100000
+
+/**
+ * Peripheral size for aes in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AES_BASE_ADDR and
+ * `TOP_MATCHA_AES_BASE_ADDR + TOP_MATCHA_AES_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AES_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for hmac in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_HMAC_BASE_ADDR 0x41110000
+
+/**
+ * Peripheral size for hmac in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_HMAC_BASE_ADDR and
+ * `TOP_MATCHA_HMAC_BASE_ADDR + TOP_MATCHA_HMAC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_HMAC_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for kmac in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_KMAC_BASE_ADDR 0x41120000
+
+/**
+ * Peripheral size for kmac in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_KMAC_BASE_ADDR and
+ * `TOP_MATCHA_KMAC_BASE_ADDR + TOP_MATCHA_KMAC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_KMAC_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for otbn in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTBN_BASE_ADDR 0x41130000
+
+/**
+ * Peripheral size for otbn in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTBN_BASE_ADDR and
+ * `TOP_MATCHA_OTBN_BASE_ADDR + TOP_MATCHA_OTBN_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTBN_SIZE_BYTES 0x10000
+/**
+ * Peripheral base address for keymgr in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_KEYMGR_BASE_ADDR 0x41140000
+
+/**
+ * Peripheral size for keymgr in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_KEYMGR_BASE_ADDR and
+ * `TOP_MATCHA_KEYMGR_BASE_ADDR + TOP_MATCHA_KEYMGR_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_KEYMGR_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for csrng in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CSRNG_BASE_ADDR 0x41150000
+
+/**
+ * Peripheral size for csrng in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CSRNG_BASE_ADDR and
+ * `TOP_MATCHA_CSRNG_BASE_ADDR + TOP_MATCHA_CSRNG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CSRNG_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for entropy_src in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ENTROPY_SRC_BASE_ADDR 0x41160000
+
+/**
+ * Peripheral size for entropy_src in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ENTROPY_SRC_BASE_ADDR and
+ * `TOP_MATCHA_ENTROPY_SRC_BASE_ADDR + TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for edn0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_EDN0_BASE_ADDR 0x41170000
+
+/**
+ * Peripheral size for edn0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_EDN0_BASE_ADDR and
+ * `TOP_MATCHA_EDN0_BASE_ADDR + TOP_MATCHA_EDN0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_EDN0_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for edn1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_EDN1_BASE_ADDR 0x41180000
+
+/**
+ * Peripheral size for edn1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_EDN1_BASE_ADDR and
+ * `TOP_MATCHA_EDN1_BASE_ADDR + TOP_MATCHA_EDN1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_EDN1_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for regs device on sram_ctrl_main in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000
+
+/**
+ * Peripheral size for regs device on sram_ctrl_main in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x20
+/**
+ * Peripheral base address for ram device on sram_ctrl_main in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000
+
+/**
+ * Peripheral size for ram device on sram_ctrl_main in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000
+/**
+ * Peripheral base address for regs device on rom_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR 0x411E0000
+
+/**
+ * Peripheral size for regs device on rom_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR and
+ * `TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR + TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for rom device on rom_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR 0x8000
+
+/**
+ * Peripheral size for rom device on rom_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR and
+ * `TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR + TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES 0x8000
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_sec in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR 0x411F0000
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_sec in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR and
+ * `TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for dma0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_DMA0_BASE_ADDR 0x40200000
+
+/**
+ * Peripheral size for dma0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_DMA0_BASE_ADDR and
+ * `TOP_MATCHA_DMA0_BASE_ADDR + TOP_MATCHA_DMA0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_DMA0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for smc_uart in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SMC_UART_BASE_ADDR 0x54000000
+
+/**
+ * Peripheral size for smc_uart in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SMC_UART_BASE_ADDR and
+ * `TOP_MATCHA_SMC_UART_BASE_ADDR + TOP_MATCHA_SMC_UART_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SMC_UART_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_timer_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR 0x54010000
+
+/**
+ * Peripheral size for rv_timer_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for smc_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SMC_CTRL_BASE_ADDR 0x54020000
+
+/**
+ * Peripheral size for smc_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SMC_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_SMC_CTRL_BASE_ADDR + TOP_MATCHA_SMC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SMC_CTRL_SIZE_BYTES 0x8
+/**
+ * Peripheral base address for cam_i2c in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CAM_I2C_BASE_ADDR 0x54040000
+
+/**
+ * Peripheral size for cam_i2c in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CAM_I2C_BASE_ADDR and
+ * `TOP_MATCHA_CAM_I2C_BASE_ADDR + TOP_MATCHA_CAM_I2C_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CAM_I2C_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for cam_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CAM_CTRL_BASE_ADDR 0x54050000
+
+/**
+ * Peripheral size for cam_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CAM_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_CAM_CTRL_BASE_ADDR + TOP_MATCHA_CAM_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CAM_CTRL_SIZE_BYTES 0x10
+/**
+ * Peripheral base address for vca device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR 0x55400000
+
+/**
+ * Peripheral size for vca device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_SIZE_BYTES 0x400000
+/**
+ * Peripheral base address for isp device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR 0x54060000
+
+/**
+ * Peripheral size for isp device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_SIZE_BYTES 0x10000
+/**
+ * Peripheral base address for enc device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR 0x55200000
+
+/**
+ * Peripheral size for enc device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_SIZE_BYTES 0x10000
+/**
+ * Peripheral base address for stream_buf device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR 0x55000000
+
+/**
+ * Peripheral size for stream_buf device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_SIZE_BYTES 0x200000
+/**
+ * Peripheral base address for vsi_ctl_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR 0x55210000
+
+/**
+ * Peripheral size for vsi_ctl_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR and
+ * `TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR + TOP_MATCHA_VSI_CTL_WRAPPER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VSI_CTL_WRAPPER_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for dma_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_DMA_SMC_BASE_ADDR 0x54070000
+
+/**
+ * Peripheral size for dma_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_DMA_SMC_BASE_ADDR and
+ * `TOP_MATCHA_DMA_SMC_BASE_ADDR + TOP_MATCHA_DMA_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_DMA_SMC_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_plic_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR 0x60000000
+
+/**
+ * Peripheral size for rv_plic_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR and
+ * `TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES 0x8000000
+/**
+ * Peripheral base address for tlul_mailbox_sec in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR 0x40800000
+
+/**
+ * Peripheral size for tlul_mailbox_sec in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR and
+ * `TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for tlul_mailbox_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR 0x540F1000
+
+/**
+ * Peripheral size for tlul_mailbox_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR and
+ * `TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for core device on ml_top in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ML_TOP_CORE_BASE_ADDR 0x5C000000
+
+/**
+ * Peripheral size for core device on ml_top in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ML_TOP_CORE_BASE_ADDR and
+ * `TOP_MATCHA_ML_TOP_CORE_BASE_ADDR + TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for dmem device on ml_top in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR 0x5A000000
+
+/**
+ * Peripheral size for dmem device on ml_top in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR and
+ * `TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR + TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000
+/**
+ * Peripheral base address for spi_host2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST2_BASE_ADDR 0x54090000
+
+/**
+ * Peripheral size for spi_host2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST2_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST2_BASE_ADDR + TOP_MATCHA_SPI_HOST2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST2_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_timer_smc2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR 0x54011000
+
+/**
+ * Peripheral size for rv_timer_smc2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for i2s0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2S0_BASE_ADDR 0x54100000
+
+/**
+ * Peripheral size for i2s0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2S0_BASE_ADDR and
+ * `TOP_MATCHA_I2S0_BASE_ADDR + TOP_MATCHA_I2S0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2S0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR 0x54030000
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR and
+ * `TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES 0x100
+
+/**
+ * MMIO Region
+ *
+ * MMIO region excludes any memory that is separate from the module
+ * configuration space, i.e. ROM, main SRAM, and flash are excluded but
+ * retention SRAM, spi_device memory, or usbdev memory are included.
+ */
+#define TOP_MATCHA_MMIO_BASE_ADDR 0x40000000
+#define TOP_MATCHA_MMIO_SIZE_BYTES 0x28000000
+
+#endif // __ASSEMBLER__
+
+#endif // MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_MEMORY_H_
diff --git a/hw/top_sencha/sw/BUILD b/hw/top_sencha/sw/BUILD
new file mode 100644
index 0000000..8709363
--- /dev/null
+++ b/hw/top_sencha/sw/BUILD
@@ -0,0 +1,23 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
+
+cc_library(
+ name = "top_sencha",
+ deps = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_sencha/sparrow:top_sencha",
+ ],
+ "//conditions:default": [
+ "//hw/top_sencha/sw/autogen:top_sencha",
+ ],
+ }),
+)
+
diff --git a/hw/top_sencha/sw/autogen/.clang-format b/hw/top_sencha/sw/autogen/.clang-format
new file mode 100644
index 0000000..7cb47a7
--- /dev/null
+++ b/hw/top_sencha/sw/autogen/.clang-format
@@ -0,0 +1,4 @@
+# This disables clang-format on all files in the sw/autogen directory.
+# This is needed so that git-clang-format and similar scripts work.
+DisableFormat: true
+SortIncludes: false
diff --git a/hw/top_sencha/sw/autogen/BUILD b/hw/top_sencha/sw/autogen/BUILD
new file mode 100644
index 0000000..237a62e
--- /dev/null
+++ b/hw/top_sencha/sw/autogen/BUILD
@@ -0,0 +1,28 @@
+# Copyright 2023 Google Inc. All Rights Reserved.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+load("@lowrisc_opentitan//rules:linker.bzl", "ld_library")
+
+package(default_visibility = ["//visibility:public"])
+
+cc_library(
+ name = "top_sencha",
+ srcs = [
+ "top_sencha.c",
+ ],
+ hdrs = [
+ "top_sencha.h",
+ "top_sencha_memory.h",
+ ],
+)
+
+ld_library(
+ name = "top_sencha_memory",
+ includes = ["top_sencha_memory.ld"],
+)
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_sencha/top_pkg.core b/hw/top_sencha/top_pkg.core
new file mode 100644
index 0000000..ad42ccd
--- /dev/null
+++ b/hw/top_sencha/top_pkg.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# XXX: This name is currently required as global identifier until we have
+# support for "interfaces" or a similar concept.
+# Tracked in https://github.com/olofk/fusesoc/issues/235
+name: "lowrisc:constants:top_pkg"
+description: "Toplevel-wide constants for Sencha"
+filesets:
+ files_rtl:
+ files:
+ - rtl/top_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/top_sencha.core b/hw/top_sencha/top_sencha.core
new file mode 100644
index 0000000..025bf6a
--- /dev/null
+++ b/hw/top_sencha/top_sencha.core
@@ -0,0 +1,157 @@
+CAPI=2:
+# Copyright 2024 Google LLC
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:top_sencha:0.1"
+description: "Technology-independent Sencha toplevel"
+filesets:
+ files_rtl_generic:
+ depend:
+ - google:ahb:headers
+ - google:axi:headers
+ - google:ip:cam_ctrl
+ - google:ip:dma
+ - google:ip:isp_wrapper
+ - google:ip:i2s
+ - google:ip:ml_top
+ - google:ip:rv_core_smc
+ - google:ip:smc_ctrl
+ - google:ip:tlul_mailbox
+ - google:ip:tluh_adapter_sram
+ - google:systems:pwrmgr
+ - lowrisc:ip:uart:0.1
+ - lowrisc:opentitan:top_sencha_alert_handler
+ - lowrisc:ip:gpio
+ - lowrisc:ip:rv_core_ibex
+ - lowrisc:ip:rv_dm
+ - lowrisc:opentitan:top_sencha_rv_plic
+ - lowrisc:opentitan:top_sencha_rv_plic_smc
+ - lowrisc:ip:pinmux
+ - lowrisc:ip:rv_timer
+ - lowrisc:ip:tlul
+ - lowrisc:ip:spi_device
+ - lowrisc:ip:spi_host
+ - lowrisc:ip:i2c
+ - lowrisc:ip:pattgen
+ - lowrisc:ip:pwm
+ - lowrisc:ip:aes
+ - lowrisc:ip:entropy_src
+ - lowrisc:ip:csrng
+ - lowrisc:ip:edn
+ - lowrisc:ip:hmac
+ - lowrisc:ip:kmac
+ - lowrisc:ip:otbn
+ - lowrisc:prim:ram_1p_scr
+ - lowrisc:prim:ram_1p_adv
+ - lowrisc:prim:rom_adv
+ - lowrisc:prim:flash
+ - lowrisc:ip:flash_ctrl
+ - lowrisc:ip:sram_ctrl
+ - lowrisc:ip:keymgr
+ - lowrisc:constants:top_pkg
+ - lowrisc:constants:jtag_id_pkg
+ - lowrisc:ip:otp_ctrl
+ - lowrisc:ip:lc_ctrl
+ - lowrisc:ip:usbdev
+ - lowrisc:top_sencha:xbar_main
+ - lowrisc:top_sencha:xbar_peri
+ - lowrisc:top_sencha:xbar_smc
+ - lowrisc:top_sencha:xbar_dbg
+ - lowrisc:ip:rstmgr
+ - lowrisc:ip:aon_timer
+ - lowrisc:ip:adc_ctrl
+ - lowrisc:ip:sysrst_ctrl
+ - lowrisc:ip:rom_ctrl
+ - lowrisc:systems:clkmgr
+ - lowrisc:systems:sensor_ctrl
+ - lowrisc:tlul:headers
+ - lowrisc:prim:all
+ - lowrisc:prim:usb_diff_rx
+ - lowrisc:prim:mubi
+ - lowrisc:systems:top_sencha_pkg
+ - "fileset_partner ? (partner:systems:ast_pkg)"
+ - "!fileset_partner ? (lowrisc:systems:ast_pkg)"
+ files:
+ - rtl/autogen/top_sencha_rnd_cnst_pkg.sv
+ - rtl/autogen/top_sencha.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/top_sencha.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/top_sencha.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/top_sencha.vbw
+ file_type: veribleLintWaiver
+
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+ IBEX_CUSTOM_PMP_RESET_VALUES:
+ datatype: bool
+ default: true
+ paramtype: vlogdefine
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl_generic
+ toplevel: top_sencha
+ parameters:
+ - IBEX_CUSTOM_PMP_RESET_VALUES
+
+ sim:
+ default_tool: icarus
+ filesets:
+ - files_rtl_generic
+ toplevel: top_sencha
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
+ syn:
+ <<: *default_target
+ # TODO: set default to DC once
+ # this option is available
+ # olofk/edalize#89
+ default_tool: icarus
+ parameters:
+ - SYNTHESIS=true
+ toplevel: top_sencha
+
+ formal:
+ <<: *default_target
+ toplevel: top_sencha
diff --git a/hw/top_sencha/top_sencha_pkg.core b/hw/top_sencha/top_sencha_pkg.core
new file mode 100644
index 0000000..632a87b
--- /dev/null
+++ b/hw/top_sencha/top_sencha_pkg.core
@@ -0,0 +1,16 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:top_sencha_pkg:0.1"
+description: "Autogenerated top_sencha_pkg used in RTL and DV."
+filesets:
+ files_rtl:
+ files:
+ - rtl/autogen/top_sencha_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
