hw/top_sencha/ip/ast/rtl/vio_pgd.sv

// Copyright 2024 Google LLC
// Copyright lowRISC contributors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//      http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

//############################################################################
// *Name: vio_pgd
// *Module Description:  VIO Power Good
//############################################################################
`ifdef SYNTHESIS
`ifndef PRIM_DEFAULT_IMPL
`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
`endif
`endif

module vio_pgd (
  output logic vio_pok_o
);

// Local signal for testing hook
logic gen_supp_a;
assign gen_supp_a = 1'b1;

`ifndef SYNTHESIS
// Behavioral Model
////////////////////////////////////////
// The initial is needed to clear the X of the delays at the start
// Also to force a power-up effect at the bgining.
logic init_start;

initial begin
  init_start = 1'b1; #1;
  init_start = 1'b0;
end

always (* xprop_off *) @( * ) begin
  if ( init_start ) begin
    vio_pok_o <= 1'b0;
  end
  if ( !init_start && gen_supp_a ) begin
    vio_pok_o <= #(ast_bhv_pkg::VIO_POK_RDLY) gen_supp_a;
  end
  if ( !init_start && !gen_supp_a ) begin
    vio_pok_o <= #(ast_bhv_pkg::VIO_POK_FDLY) gen_supp_a;
  end
end
`else
// SYNTHESIS/VERILATOR/LINTER/FPGA
//////////////////////////////////////
localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;

if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
  // FPGA Specific (place holder)
  ///////////////////////////////////////
  assign vio_pok_o = gen_supp_a;
end else begin : gen_generic
  assign vio_pok_o = gen_supp_a;
end
`endif

endmodule : vio_pgd