Merge "Add the build mode cover_reg_top_no_dma to solve the problem with chip_jtag_csr_rw"
diff --git a/hw/top_matcha/data/clocks_nexus.xdc b/hw/top_matcha/data/clocks_nexus.xdc
index 7035428..74cbd85 100644
--- a/hw/top_matcha/data/clocks_nexus.xdc
+++ b/hw/top_matcha/data/clocks_nexus.xdc
@@ -5,6 +5,12 @@
## Clock Signal
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports IO_CLK]
+## Rename MMCM outputs for less bug-prone parsing.
+## Some auto-derived clocks can have names that include brackets.
+create_generated_clock -name clk_main [get_pin clkgen/pll/CLKOUT0]
+create_generated_clock -name clk_usb_48 [get_pin clkgen/pll/CLKOUT1]
+create_generated_clock -name clk_aon [get_pin clkgen/pll/CLKOUT4]
+
## Clock Domain Crossings
set clks_10_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]]
set clks_48_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT1]]
@@ -20,8 +26,10 @@
#Recommended Div4 clock constraints from Xilinx
#TODO uncomment below line and integrate u_div4 in path to make constraint more generic
-#set u_div4 top_*/u_clkmgr_aon/u_no_scan_io_div4_div
-create_generated_clock -name clkDiv4 -divide_by 4 -source [get_pins top_matcha/u_clkmgr_aon/u_no_scan_io_div4_div/gen_div.clk_int_reg/C] [get_pins top_matcha/u_clkmgr_aon/u_no_scan_io_div4_div/gen_div.clk_int_reg/Q]
+set u_div4 top_*/u_clkmgr_aon/u_no_scan_io_div4_div
+create_generated_clock -name clkDiv4 -divide_by 4 -source [get_pins ${u_div4}/gen_div.clk_int_reg/C] [get_pins ${u_div4}/gen_div.clk_int_reg/Q]
+
+#
# the step-down mux is implemented with a LUT right now and the mux switches on the falling edge.
# therefore, Vivado propagates both clock edges down the clock network.
@@ -39,45 +47,39 @@
create_clock -add -name rv_jtag_tck -period 200.00 -waveform {0 5} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
## SPI clocks
+set spi_dev_data [get_ports {SPI_DEV_D0 SPI_DEV_D1 SPI_DEV_D2 SPI_DEV_D3}]
create_clock -add -name clk_spi -period 100.00 -waveform {0 50} [get_ports SPI_DEV_CLK]
create_clock -add -name clk_cs -period 1000.00 -waveform {0 50} [get_ports SPI_DEV_CS_L]
-set_input_delay -clock clk_spi 5 [get_ports SPI_DEV_D0]
-set_input_delay -clock clk_spi 5 [get_ports SPI_DEV_D1]
-set_input_delay -clock clk_spi 5 [get_ports SPI_DEV_D2]
-set_input_delay -clock clk_spi 5 [get_ports SPI_DEV_D3]
-set_input_delay -clock clk_spi 5 [get_ports SPI_DEV_CS_L]
-set_output_delay -clock clk_spi 5 [get_ports SPI_DEV_D0] -add_delay
-set_output_delay -clock clk_spi 5 [get_ports SPI_DEV_D1] -add_delay
-set_output_delay -clock clk_spi 5 [get_ports SPI_DEV_D2] -add_delay
-set_output_delay -clock clk_spi 5 [get_ports SPI_DEV_D3] -add_delay
+set_input_delay -clock clk_spi 5 ${spi_dev_data} -add_delay
+set_output_delay -clock clk_spi 5 ${spi_dev_data} -add_delay
+# set_input_delay -clock clk_spi -clock_fall -min ${spi_dev_in_delay_min} ${spi_dev_data} -add_delay
+# set_input_delay -clock clk_spi -clock_fall -max ${spi_dev_in_delay_max} ${spi_dev_data} -add_delay
## Camera Clock
#8-bit, QVGA 60FPS @ 6MHz > setting to 10M to keep numbers round
#create_clock -add -name clk_cam_pclk -period 100.00 -waveform {0 50} [get_ports ISP_DVP_PCLK]
##SPI Host IO Delay
-set_input_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_D0]
-set_input_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_D1]
-set_input_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_D2]
-set_input_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_D3]
-set_input_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_CLK]
-set_input_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_CS_L]
-set_output_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_D0]
-set_output_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_D1]
-set_output_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_D2]
-set_output_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_D3]
-set_output_delay -clock [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT0]] 5 [get_ports SPI_HOST_CS_L]
+## SPI Passthrough constraints
+create_generated_clock -name clk_spi_pt -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_ports SPI_HOST_CLK]
+set spi_pt_data [get_ports {SPI_HOST_D0 SPI_HOST_D1 SPI_HOST_D2 SPI_HOST_D3}]
+set_input_delay -clock clk_spi_pt -clock_fall 7 ${spi_pt_data} -add_delay
+
+set_output_delay -clock clk_spi_pt 7 ${spi_pt_data} -add_delay
+set_output_delay -clock clk_spi_pt 7 [get_ports SPI_HOST_CS_L] -add_delay
+
## GPIO IO Delay
-set_input_delay -clock clkDiv4 5 [get_ports IOA*]
-set_input_delay -clock clkDiv4 5 [get_ports IOB*]
-set_input_delay -clock clkDiv4 5 [get_ports IOC*]
-set_input_delay -clock clkDiv4 5 [get_ports IOR*]
-set_output_delay -clock clkDiv4 5 [get_ports IOA*]
-set_output_delay -clock clkDiv4 5 [get_ports IOB*]
-set_output_delay -clock clkDiv4 5 [get_ports IOC*]
-set_output_delay -clock clkDiv4 5 [get_ports IOR*]
+set ioa_muxed_ports [get_ports IOA*]
+set iob_muxed_ports [get_ports IOB*]
+set ioc_muxed_ports [get_ports IOC*]
+set ioc_muxed_ports [get_ports IOD*]
+set ior_muxed_ports [get_ports -filter {NAME != IOR8 && NAME != IOR9} IOR*]
+set all_muxed_ports "${ioa_muxed_ports} ${iob_muxed_ports} ${ioc_muxed_ports} ${ior_muxed_ports}"
+
+set_input_delay -clock clkDiv4 5 [get_ports ${all_muxed_ports}]
+set_output_delay -clock clkDiv4 5 [get_ports ${all_muxed_ports}]
create_generated_clock -name clk_i2s_rx -divide_by 22 -source [get_pin ${u_pll}/CLKOUT1] [get_pins top_matcha/u_i2s0/i2s_core/bufg_rx_audio_clk/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
create_generated_clock -name clk_i2s_tx -divide_by 22 -source [get_pin ${u_pll}/CLKOUT1] [get_pins top_matcha/u_i2s0/i2s_core/bufg_tx_audio_clk/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
@@ -108,4 +110,16 @@
create_generated_clock -name clk_spi_in -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_in_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O]
create_generated_clock -name clk_spi_out -divide_by 1 -source [get_ports SPI_DEV_CLK] [get_pins top_*/u_spi_device/u_clk_spi_out_buf/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufr.bufr_i/O] -invert
-set_clock_groups -group ${clks_10_unbuf} -group ${clks_48_unbuf} -group ${clks_aon_unbuf} -group clk_io_div2 -group clkDiv4 -group lc_jtag_tck -group rv_jtag_tck -group {clk_spi clk_spi_in clk_spi_out} -group clk_cs -group sys_clk_pin -group clk_i2s_rx -group clk_i2s_tx -asynchronous
+set_clock_groups -asynchronous \
+ -group ${clks_10_unbuf} \
+ -group ${clks_48_unbuf} \
+ -group ${clks_aon_unbuf} \
+ -group clk_io_div2 \
+ -group clkDiv4 \
+ -group lc_jtag_tck \
+ -group rv_jtag_tck \
+ -group {clk_spi clk_spi_in clk_spi_out clk_spi_pt} \
+ -group clk_cs \
+ -group sys_clk_pin \
+ -group clk_i2s_rx \
+ -group clk_i2s_tx
diff --git a/hw/top_matcha/data/pins_nexus.xdc b/hw/top_matcha/data/pins_nexus.xdc
index 748e430..8a7083a 100644
--- a/hw/top_matcha/data/pins_nexus.xdc
+++ b/hw/top_matcha/data/pins_nexus.xdc
@@ -87,14 +87,14 @@
set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [ get_ports { IOC12 }]; #RSTB (FLASH1_RSTB)
## Nexus PMOD3 connect to interace Connector (J263, 3.3V through level shifter), Bank62 LVCMOS18
-#set_property -dict { PACKAGE_PIN AU40 IOSTANDARD LVCMOS18 } [get_ports { IOC2 }]; #PMOD3_1_FPGA
-#set_property -dict { PACKAGE_PIN AV40 IOSTANDARD LVCMOS18 } [get_ports { IOC3 }]; #PMOD3_2_FPGA USED FOR UART to match nexus
-#set_property -dict { PACKAGE_PIN AW40 IOSTANDARD LVCMOS18 } [get_ports { IOC4 }]; #PMOD3_3_FPGA USED FOR UART to match nexus
-set_property -dict { PACKAGE_PIN AY39 IOSTANDARD LVCMOS18 } [get_ports { IOA0 }]; #PMOD3_4_FPGA IOA0 moved for IOC8 TAP0
-set_property -dict { PACKAGE_PIN AU39 IOSTANDARD LVCMOS18 } [get_ports { IOC6 }]; #PMOD3_7_FPGA
-set_property -dict { PACKAGE_PIN AV39 IOSTANDARD LVCMOS18 } [get_ports { IOC7 }]; #PMOD3_8_FPGA
-set_property -dict { PACKAGE_PIN AW37 IOSTANDARD LVCMOS18 } [get_ports { IOA1 }]; #PMOD3_9_FPGA IOA1 moved for IOC5 TAP1
-set_property -dict { PACKAGE_PIN AW38 IOSTANDARD LVCMOS18 } [get_ports { IOC9 }]; #PMOD3_10_FPGA
+set_property -dict { PACKAGE_PIN AU40 IOSTANDARD LVCMOS18 } [get_ports { IOD0 }]; #PMOD3_1_FPGA
+set_property -dict { PACKAGE_PIN AV40 IOSTANDARD LVCMOS18 } [get_ports { IOD1 }]; #PMOD3_2_FPGA
+set_property -dict { PACKAGE_PIN AW40 IOSTANDARD LVCMOS18 } [get_ports { IOD2 }]; #PMOD3_3_FPGA
+set_property -dict { PACKAGE_PIN AY39 IOSTANDARD LVCMOS18 } [get_ports { IOD3 }]; #PMOD3_4_FPGA
+set_property -dict { PACKAGE_PIN AU39 IOSTANDARD LVCMOS18 } [get_ports { IOD4 }]; #PMOD3_7_FPGA
+set_property -dict { PACKAGE_PIN AV39 IOSTANDARD LVCMOS18 } [get_ports { IOD5 }]; #PMOD3_8_FPGA
+# set_property -dict { PACKAGE_PIN AW37 IOSTANDARD LVCMOS18 } [get_ports { IOA1 }]; #PMOD3_9_FPGA
+# set_property -dict { PACKAGE_PIN AW38 IOSTANDARD LVCMOS18 } [get_ports { IOC9 }]; #PMOD3_10_FPGA
## Parallel Camera Nexus SMC J14 pins for HPS
@@ -129,12 +129,12 @@
set_property -dict { PACKAGE_PIN AM32 IOSTANDARD LVCMOS18 } [get_ports { IOB7 }]; #PMOD1_4_FPGA -ISP_DVP_D7
set_property -dict { PACKAGE_PIN AN33 IOSTANDARD LVCMOS18 } [get_ports { IOB8 }]; #PMOD2_1_FPGA -ISP_DVP_PCLK
#set_property -dict { PACKAGE_PIN AN34 IOSTANDARD LVCMOS18 } [get_ports { ISP_DVP_MCLK }]; #PMOD2_7_FPGA -ISP_DVP_MCLK
-set_property -dict { PACKAGE_PIN AM31 IOSTANDARD LVCMOS18 } [get_ports { IOA2 }]; #PMOD2_2_FPGA -ISP_DVP_VSYNC
-set_property -dict { PACKAGE_PIN AP33 IOSTANDARD LVCMOS18 } [get_ports { IOA3 }]; #PMOD2_8_FPGA -ISP_DVP_HSYNC
-set_property -dict { PACKAGE_PIN AR35 IOSTANDARD LVCMOS18 } [get_ports { IOA4 }]; #PCAM_SCL/PMOD2_9_FPGA -CAM_SCL
-set_property -dict { PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 } [get_ports { IOA5 }]; #PCAM_SDA/PMOD2_3_FPGA -CAM_SDA
-set_property -dict { PACKAGE_PIN AT36 IOSTANDARD LVCMOS18 } [get_ports { IOA6 }]; #PMOD2_4_FPGA -CAM_INT
-set_property -dict { PACKAGE_PIN AT37 IOSTANDARD LVCMOS18 } [get_ports { IOA7 }]; #PMOD2_10_FPGA -CAM_TRIG
+set_property -dict { PACKAGE_PIN AM31 IOSTANDARD LVCMOS18 } [get_ports { IOA2 }]; #PMOD2_2_FPGA -ISP_DVP_VSYNC
+set_property -dict { PACKAGE_PIN AP33 IOSTANDARD LVCMOS18 } [get_ports { IOA3 }]; #PMOD2_8_FPGA -ISP_DVP_HSYNC
+set_property -dict { PACKAGE_PIN AR35 IOSTANDARD LVCMOS18 } [get_ports { IOA4 }]; #PCAM_SCL/PMOD2_9_FPGA -CAM_SCL
+set_property -dict { PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 } [get_ports { IOA5 }]; #PCAM_SDA/PMOD2_3_FPGA -CAM_SDA
+set_property -dict { PACKAGE_PIN AT36 IOSTANDARD LVCMOS18 } [get_ports { IOA6 }]; #PMOD2_4_FPGA -CAM_INT
+set_property -dict { PACKAGE_PIN AT37 IOSTANDARD LVCMOS18 } [get_ports { IOA7 }]; #PMOD2_10_FPGA -CAM_TRIG
@@ -143,25 +143,25 @@
set_property -dict { PACKAGE_PIN AY38 IOSTANDARD LVCMOS18 } [get_ports { IOB10 }]; #PMOD4_1_FPGA -SPI_HOST2_D0
set_property -dict { PACKAGE_PIN BA39 IOSTANDARD LVCMOS18 } [get_ports { IOB11 }]; #PMOD4_2_FPGA -SPI_HOST2_D1
set_property -dict { PACKAGE_PIN AW35 IOSTANDARD LVCMOS18 } [get_ports { IOB12 }]; #PMOD4_3_FPGA -SPI_HOST2_D2
-set_property -dict { PACKAGE_PIN AY35 IOSTANDARD LVCMOS18 } [get_ports { IOR11 }]; #PMOD4_4_FPGA -SPI_HOST2_D3
-set_property -dict { PACKAGE_PIN AY40 IOSTANDARD LVCMOS18 } [get_ports { IOR12 }]; #PMOD4_7_FPGA -SPI_HOST2_CLK
+set_property -dict { PACKAGE_PIN AY35 IOSTANDARD LVCMOS18 } [get_ports { IOR11 }]; #PMOD4_4_FPGA -SPI_HOST2_D3
+set_property -dict { PACKAGE_PIN AY40 IOSTANDARD LVCMOS18 } [get_ports { IOR12 }]; #PMOD4_7_FPGA -SPI_HOST2_CLK
set_property -dict { PACKAGE_PIN BA40 IOSTANDARD LVCMOS18 } [get_ports { IOR13 }]; #PMOD4_8_FPGA -SPI_HOST2_CS_L
#set_property -dict { PACKAGE_PIN AW36 IOSTANDARD LVCMOS18 } [get_ports { IOB7 }]; #PMOD4_9_FPGA
#set_property -dict { PACKAGE_PIN BC40 IOSTANDARD LVCMOS18 } [get_ports { IOB8 }]; #PMOD4_10_FPGA
##OLD## J271 pins for prototyping. Bank 63 -- IOB7/8 previously for display control moved. IOD0/1 will be used for display control signals for demo.
-set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS18 } [get_ports { IOD0 }]; #EXP1x10_J271_P1
-set_property -dict { PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports { IOD1 }]; #EXP1x10_J271_P3
-set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS18 } [get_ports { IOD2 }]; #EXP1x10_J271_P5
-set_property -dict { PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports { IOD3 }]; #EXP1x10_J271_P7
-set_property -dict { PACKAGE_PIN AG31 IOSTANDARD LVCMOS18 } [get_ports { IOD4 }]; #EXP1x10_J271_P9
-set_property -dict { PACKAGE_PIN AH31 IOSTANDARD LVCMOS18 } [get_ports { IOD5 }]; #EXP1x10_J271_P11
-# set_property -dict { PACKAGE_PIN AG32 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P13
+# set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P1
+# set_property -dict { PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P3
+# set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P5
+# set_property -dict { PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P7
+# set_property -dict { PACKAGE_PIN AG31 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P9
+# set_property -dict { PACKAGE_PIN AH31 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P11
+# set_property -dict { PACKAGE_PIN AG32 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P13
#EXP1x10_J271_P19 held by IO_UPHY_DPPULLUP
#EXP1x10_J271_P17 unused
-# set_property -dict { PACKAGE_PIN AG33 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P19
+# set_property -dict { PACKAGE_PIN AG33 IOSTANDARD LVCMOS18 } [get_ports { xx }]; #EXP1x10_J271_P19
-###2## IO_TRIGGER, IO_CLKOUT and USB signals moved to FMC_HA pins for now. Skipping FMC_HA00_CC, FMC_HA01_CC as they are clocks
+###Unused Signals
set_property -dict { PACKAGE_PIN BD13 IOSTANDARD LVCMOS18 } [get_ports { IO_TRIGGER }]; #FMC_HA02_P
set_property -dict { PACKAGE_PIN BE13 IOSTANDARD LVCMOS18 } [get_ports { IO_CLKOUT }]; #FMC_HA02_N
set_property -dict { PACKAGE_PIN BD12 IOSTANDARD LVCMOS18 } [get_ports { USB_P }]; #FMC_HA03_P
@@ -170,6 +170,12 @@
set_property -dict { PACKAGE_PIN BB12 IOSTANDARD LVCMOS18 } [get_ports { IO_USB_DNPULLUP0 }]; #FMC_HA04_N
set_property -dict { PACKAGE_PIN BC11 IOSTANDARD LVCMOS18 } [get_ports { IO_USB_DPPULLUP0 }]; #FMC_HA05_P
set_property -dict { PACKAGE_PIN BD11 IOSTANDARD LVCMOS18 } [get_ports { IOB9 }]; #FMC_HA05_N
+#MISC from PMOD3
+set_property -dict { PACKAGE_PIN BE15 IOSTANDARD LVCMOS18 } [get_ports { IOA0 }]; #FMC_HA06_P
+set_property -dict { PACKAGE_PIN BF15 IOSTANDARD LVCMOS18 } [get_ports { IOC6 }]; #FMC_HA06_N
+set_property -dict { PACKAGE_PIN BE14 IOSTANDARD LVCMOS18 } [get_ports { IOC7 }]; #FMC_HA07_P
+set_property -dict { PACKAGE_PIN BF14 IOSTANDARD LVCMOS18 } [get_ports { IOA1 }]; #FMC_HA07_N
+set_property -dict { PACKAGE_PIN BC15 IOSTANDARD LVCMOS18 } [get_ports { IOC9 }]; #FMC_HA08_P
## TI TUSB1T1105AMHX USB Transceiver "usbdev" testing, Bank 64 LVCMOS18
diff --git a/hw/top_matcha/dv/chip_sim_cfg.hjson b/hw/top_matcha/dv/chip_sim_cfg.hjson
index 6b69cb8..27b8948 100644
--- a/hw/top_matcha/dv/chip_sim_cfg.hjson
+++ b/hw/top_matcha/dv/chip_sim_cfg.hjson
@@ -460,7 +460,7 @@
uvm_test_seq: chip_sw_base_vseq
sw_images: [
"//sw/device/tests/smc:smc_kelvin_hello_test:6:matcha",
- "//sw/device/tests/kelvin/testdata:kelvin_hello_world:7:matcha"]
+ "//sw/device/tests/kelvin:kelvin_hello_world:7:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
@@ -579,7 +579,9 @@
{
name: chip_sw_smc_kelvin_checksum_test
uvm_test_seq: chip_sw_base_vseq
- sw_images: ["//sw/device/tests/smc:smc_kelvin_checksum_test:6:matcha"]
+ sw_images: [
+ "//sw/device/tests/smc:smc_kelvin_checksum_test:6:matcha",
+ "//sw/device/tests/kelvin:kelvin_checksum:7:matcha"]
en_run_modes: ["sw_test_mode_test_simple_sec"]
run_opts:["+sw_test_timeout_ns=40_000_000"]
}
@@ -2136,6 +2138,7 @@
"chip_sw_smc_isp_wrapper_irq_test",
"chip_sw_smc_isp_wrapper_test",
"chip_sw_smc_isp_wrapper_tpg_64_64_test",
+ "chip_sw_smc_kelvin_checksum_test",
"chip_sw_smc_kelvin_hello_test",
"chip_sw_smc_lsu_interrupt_boundary_test",
"chip_sw_smc_lsu_page_boundary_test",
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv b/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
index ac1a588..7c71d09 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
@@ -84,6 +84,7 @@
// cfg_en (LSB) is unused in memory module and does not qualify volt_sel
assign ram_cfg.ram_cfg = { 3'b0, volt_sel_i, 1'b0 };
+ assign ram_cfg.rf_cfg = 5'b0;
// xbar_sram only support Byte-Mask for now. i.e 8 data bits per mask bit.
assign xbar_wmask_b = {xbar_wmask[248], xbar_wmask[240], xbar_wmask[232], xbar_wmask[224],
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
index 3900a48..43e5d2c 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
@@ -81,6 +81,16 @@
hw2reg.error_status.d_mem_disable_access.de = 1'b0;
end
+ assign hw2reg.init_end.valid.d = 1'b0;
+ assign hw2reg.init_end.valid.de = 1'b0;
+ assign hw2reg.init_end.address.d = 22'b0;
+ assign hw2reg.init_end.address.de = 22'b0;
+ assign hw2reg.init_status.init_pending.d = 1'b0;
+ assign hw2reg.init_status.init_pending.de = 1'b0;
+ assign hw2reg.init_status.init_done.d = 1'b0;
+ assign hw2reg.init_status.init_done.de = 1'b0;
+ assign core0_cid[7] = 1'b0;
+
// ML_top Control
ml_top_core_reg_top u_reg (
.clk_i,
diff --git a/rules/matcha.bzl b/rules/matcha.bzl
index b3026bc..c83860c 100644
--- a/rules/matcha.bzl
+++ b/rules/matcha.bzl
@@ -635,18 +635,25 @@
srcs: The c source files.
**kwargs: Additional arguments forward to cc_binary.
Emits rules:
+ bin_to_vmem named: <name>_vmem
+ Generating the 256-bitwidth vmem output for the target.
+ 256_bitwidth_vmem named: <name>.256.vmem
+ Containing the 256-bitwidth vmem output.
filegroup named: <name>.bin
Containing the binary output for the target.
filegroup named: <name>.elf
Containing all elf output for the target.
+ filegroup named: <name>
+ Containing cc outputs and 256-bitwidth vmem target.
"""
srcs = srcs + [
"//sw/device/lib/testing/test_framework:kelvin_gloss.c",
"//sw/device/lib/testing/test_framework:kelvin_start.S",
"@lowrisc_opentitan//sw/device/lib/crt:crt.S",
]
+ kelvin_cc_name = "{}_cc".format(name)
kelvin_binary_impl(
- name = name,
+ name = kelvin_cc_name,
srcs = srcs,
linker_script = "//sw/device/lib/testing/test_framework:kelvin.ld",
linker_script_includes = [
@@ -656,13 +663,49 @@
)
# Need to create the following filegroups to make the output discoverable.
+ bin_name = "{}.bin".format(name)
native.filegroup(
- name = "{}.bin".format(name),
- srcs = [name],
+ name = bin_name,
+ srcs = [kelvin_cc_name],
output_group = "bin_file",
)
+ elf_name = "{}.elf".format(name)
native.filegroup(
- name = "{}.elf".format(name),
- srcs = [name],
+ name = elf_name,
+ srcs = [kelvin_cc_name],
output_group = "elf_file",
)
+
+ # Generate vmem file for dv testbench
+ # Memory in ml_top has word size 256. srec_cat supports only up to 128.
+ # Build a flow to transform 32-bitwidth format into 256-bitwidth format.
+ vmem_32_name = "{}.32.vmem".format(name)
+ vmem_256_name = "{}.256.vmem".format(name)
+ bin_to_vmem(
+ name = vmem_32_name,
+ bin = bin_name,
+ word_size = 32,
+ )
+
+ cmd = """
+ $(location //util:gen_vmem_256) \
+ --input=$< \
+ --output=$@
+ """
+ vmem_name = "{}_vmem".format(name)
+ native.genrule(
+ name = vmem_name,
+ srcs = [vmem_32_name],
+ outs = [vmem_256_name],
+ cmd = cmd,
+ tools = ["@matcha//util:gen_vmem_256"],
+ **kwargs
+ )
+ native.filegroup(
+ name = name,
+ srcs = [
+ bin_name,
+ elf_name,
+ vmem_name,
+ ],
+ )
diff --git a/sw/device/tests/kelvin/testdata/BUILD b/sw/device/tests/kelvin/testdata/BUILD
deleted file mode 100644
index 9b00741..0000000
--- a/sw/device/tests/kelvin/testdata/BUILD
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright 2023 Google contributors.
-
-package(default_visibility = ["//visibility:public"])
-
-filegroup(
- name = "kelvin_hello_world",
- srcs = ["kelvin_hello_world.256.vmem"],
-)
diff --git a/sw/device/tests/kelvin/testdata/kelvin_hello_world.256.vmem b/sw/device/tests/kelvin/testdata/kelvin_hello_world.256.vmem
deleted file mode 100755
index ec7f4b2..0000000
--- a/sw/device/tests/kelvin/testdata/kelvin_hello_world.256.vmem
+++ /dev/null
@@ -1,12 +0,0 @@
-/* http://srecord.sourceforge.net/ */
-@00000000 0000041300000393000003130000021394C18193000011970001011310020117
-@00000001 0000089300000813000007930000071300000693000006130000059300000493
-@00000002 00000C9300000C1300000B9300000B1300000A9300000A130000099300000913
-@00000003 200005932000051300000F9300000F1300000E9300000E1300000D9300000D13
-@00000004 FE946AE300440413000280E70004228300947A631540049315400413064000EF
-@00000005 001007B70000006F08000073000080E701408093000000970000059300000513
-@00000006 0000051326000077FED798E3FEE7AE2300170713004787930007A703001016B7
-@00000007 FEB56CE3004505130005202300029E630032F29300B562B302B5706300008067
-@00000008 0032F29300C2E2B300B562B302B57C63C00010730000806700B5146300008067
-@00000009 004505130055202300460613000622830262E26340A5833340C502B302029863
-@0000000A FFFFFFFFC00010730000806700B51463 00008067FEB568E3
diff --git a/sw/device/tests/smc/smc_kelvin_checksum_test.c b/sw/device/tests/smc/smc_kelvin_checksum_test.c
index 5b70a23..9c038a0 100644
--- a/sw/device/tests/smc/smc_kelvin_checksum_test.c
+++ b/sw/device/tests/smc/smc_kelvin_checksum_test.c
@@ -67,7 +67,7 @@
while (intr_state == 0x0) {
intr_state = mmio_region_read32(base_addr, ML_TOP_INTR_STATE_REG_OFFSET);
- busy_spin_micros(10 * 1000);
+ busy_spin_micros(200);
}
// Received interrupts from Kelvin core, check if only FINISH asserted
diff --git a/util/BUILD b/util/BUILD
index b83b8e6..4016ec9 100644
--- a/util/BUILD
+++ b/util/BUILD
@@ -79,6 +79,13 @@
],
)
+py_binary(
+ name = "gen_vmem_256",
+ srcs = [
+ "gen_vmem_256.py",
+ ],
+)
+
filegroup(
name = "topgen_tpl_files",
srcs = glob(["topgen/**/*.tpl"]) + [
diff --git a/util/gen_vmem_256.py b/util/gen_vmem_256.py
new file mode 100644
index 0000000..d85ad5d
--- /dev/null
+++ b/util/gen_vmem_256.py
@@ -0,0 +1,73 @@
+#!/usr/bin/env python3
+# Copyright 2023 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+"""
+Generate 256-bitwidth vmem file from 32-bitwidth vmem file
+"""
+
+import argparse
+import re
+
+def main():
+ """
+ Args:
+ input: The input 32-bitwidth vmem file name.
+ output: The output 256-bitwidth vmem file name.
+ """
+ parser = argparse.ArgumentParser(description='Generate 256-bitwidth vmem file.')
+ parser.add_argument("--input",
+ "-i",
+ action='store',
+ required=True,
+ help="Input 32-bitwidth vmem file")
+ parser.add_argument("--output",
+ "-o",
+ required=True,
+ help="Output 256-bitwidth vmem file")
+ parser.add_argument("--entry_addr",
+ default = 0x0,
+ help="Entry address of kelvin program")
+ args = parser.parse_args()
+
+ # Open input/output files
+ infile = open(args.input, 'r')
+ outfile = open(args.output, 'w')
+
+ # Fetch each line from 32-bitwidth vmem file and dump each data line for
+ # 256-bitwidth vmem file.
+ addr_base = args.entry_addr
+ mem_data_line = ""
+ word_per_line = 8
+ for line in infile.readlines():
+ # Ignore comment
+ if re.match(r"\/\*(.)*\*\/", line):
+ continue
+ tokens = line.split()
+ m = re.match(r"@([0-9a-fA-F]{8})", tokens[0])
+ addr = int(m[1], 16)
+ for token in tokens[1:]:
+ mem_data_line = token + mem_data_line
+ addr = addr + 1
+ # Write out a mem data line when it is ready
+ if (addr % word_per_line) == 0:
+ outfile.write(f"@{addr_base:08X} {mem_data_line}\n")
+ addr_base = int((addr + args.entry_addr) / word_per_line)
+ mem_data_line = ""
+ if mem_data_line:
+ outfile.write(f"@{addr_base:08X} {mem_data_line}\n")
+ infile.close()
+ outfile.close()
+
+if __name__ == "__main__":
+ main()
