| commit | 57e3ee84ac53ebdb5f2013e015e9c2d8aa6ea071 | [log] [tgz] |
|---|---|---|
| author | Naveen Dodda <ndodda@google.com> | Thu Oct 02 01:31:07 2025 +0000 |
| committer | Naveen Dodda <ndodda@google.com> | Fri Oct 03 15:48:31 2025 -0700 |
| tree | f6db34d2aa8230543bc69e2973b3e05cdd9c9010 | |
| parent | d1b068938f0abd949a248d9b50779aed1a11527f [diff] |
Remaining segmented load tests
* This test uses workaround for compiler bug
* Adds indexed segmented loads for SEW 32 for index width 16, 8
* Test : bazel run //tests/cocotb:rvv_load_store_test_load32_index16_seg
bazel run //tests/cocotb:rvv_load_store_test_load32_index8_seg
Change-Id: I1462a3143db9228a3e42315fcf14179e51f51044
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog