| #port width Verilog SystemC |
| io_aclk 1 bit sc_clock |
| io_halted 1 bit sc_logic |
| io_fault 1 bit sc_logic |
| io_wfi 1 bit sc_logic |
| io_irq 1 bit sc_logic |
| |
| io_slog_valid 1 bit sc_logic |
| io_slog_addr 5 bit_vector sc_lv |
| io_slog_data 32 bit_vector sc_lv |
| |
| io_debug_en 4 bit_vector sc_lv |
| io_debug_cycles 32 bit_vector sc_lv |
| io_debug_addr_0 32 bit_vector sc_lv |
| io_debug_addr_1 32 bit_vector sc_lv |
| io_debug_addr_2 32 bit_vector sc_lv |
| io_debug_addr_3 32 bit_vector sc_lv |
| io_debug_inst_0 32 bit_vector sc_lv |
| io_debug_inst_1 32 bit_vector sc_lv |
| io_debug_inst_2 32 bit_vector sc_lv |
| io_debug_inst_3 32 bit_vector sc_lv |
| |
| io_debug_dbus_valid 1 bit sc_logic |
| io_debug_dbus_bits_addr 32 bit_vector sc_lv |
| io_debug_dbus_bits_wdata 128 bit_vector sc_lv |
| io_debug_dbus_bits_write 1 bit sc_logic |
| io_debug_dispatch_0_instFire 1 bit sc_logic |
| io_debug_dispatch_1_instFire 1 bit sc_logic |
| io_debug_dispatch_2_instFire 1 bit sc_logic |
| io_debug_dispatch_3_instFire 1 bit sc_logic |
| io_debug_dispatch_0_instAddr 32 bit_vector sc_lv |
| io_debug_dispatch_1_instAddr 32 bit_vector sc_lv |
| io_debug_dispatch_2_instAddr 32 bit_vector sc_lv |
| io_debug_dispatch_3_instAddr 32 bit_vector sc_lv |
| io_debug_dispatch_0_instInst 32 bit_vector sc_lv |
| io_debug_dispatch_1_instInst 32 bit_vector sc_lv |
| io_debug_dispatch_2_instInst 32 bit_vector sc_lv |
| io_debug_dispatch_3_instInst 32 bit_vector sc_lv |
| io_debug_regfile_writeAddr_0_valid 1 bit sc_logic |
| io_debug_regfile_writeAddr_1_valid 1 bit sc_logic |
| io_debug_regfile_writeAddr_2_valid 1 bit sc_logic |
| io_debug_regfile_writeAddr_3_valid 1 bit sc_logic |
| io_debug_regfile_writeAddr_0_bits 5 bit_vector sc_lv |
| io_debug_regfile_writeAddr_1_bits 5 bit_vector sc_lv |
| io_debug_regfile_writeAddr_2_bits 5 bit_vector sc_lv |
| io_debug_regfile_writeAddr_3_bits 5 bit_vector sc_lv |
| io_debug_regfile_writeData_0_valid 1 bit sc_logic |
| io_debug_regfile_writeData_1_valid 1 bit sc_logic |
| io_debug_regfile_writeData_2_valid 1 bit sc_logic |
| io_debug_regfile_writeData_3_valid 1 bit sc_logic |
| io_debug_regfile_writeData_4_valid 1 bit sc_logic |
| io_debug_regfile_writeData_5_valid 1 bit sc_logic |
| io_debug_regfile_writeData_0_bits_addr 5 bit_vector sc_lv |
| io_debug_regfile_writeData_1_bits_addr 5 bit_vector sc_lv |
| io_debug_regfile_writeData_2_bits_addr 5 bit_vector sc_lv |
| io_debug_regfile_writeData_3_bits_addr 5 bit_vector sc_lv |
| io_debug_regfile_writeData_4_bits_addr 5 bit_vector sc_lv |
| io_debug_regfile_writeData_5_bits_addr 5 bit_vector sc_lv |
| io_debug_regfile_writeData_0_bits_data 32 bit_vector sc_lv |
| io_debug_regfile_writeData_1_bits_data 32 bit_vector sc_lv |
| io_debug_regfile_writeData_2_bits_data 32 bit_vector sc_lv |
| io_debug_regfile_writeData_3_bits_data 32 bit_vector sc_lv |
| io_debug_regfile_writeData_4_bits_data 32 bit_vector sc_lv |
| io_debug_regfile_writeData_5_bits_data 32 bit_vector sc_lv |
| io_debug_float_writeAddr_valid 1 bit sc_logic |
| io_debug_float_writeAddr_bits 5 bit_vector sc_lv |
| io_debug_float_writeData_0_valid 1 bit sc_logic |
| io_debug_float_writeData_1_valid 1 bit sc_logic |
| io_debug_float_writeData_0_bits_addr 32 bit_vector sc_lv |
| io_debug_float_writeData_1_bits_addr 32 bit_vector sc_lv |
| io_debug_float_writeData_0_bits_data 32 bit_vector sc_lv |
| io_debug_float_writeData_1_bits_data 32 bit_vector sc_lv |
| |
| io_dm_req_valid 1 bit sc_logic |
| io_dm_req_ready 1 bit sc_logic |
| io_dm_req_bits_address 32 bit_vector sc_lv |
| io_dm_req_bits_data 32 bit_vector sc_lv |
| io_dm_req_bits_op 2 bit_vector sc_lv |
| io_dm_rsp_valid 1 bit sc_logic |
| io_dm_rsp_ready 1 bit sc_logic |
| io_dm_rsp_bits_data 32 bit_vector sc_lv |
| io_dm_rsp_bits_op 2 bit_vector sc_lv |
| |
| io_axi_slave_write_addr_ready 1 bit sc_logic |
| io_axi_slave_write_addr_valid 1 bit sc_logic |
| io_axi_slave_write_addr_bits_addr 32 bit_vector sc_lv |
| io_axi_slave_write_addr_bits_prot 3 bit_vector sc_lv |
| io_axi_slave_write_addr_bits_id 6 bit_vector sc_lv |
| io_axi_slave_write_addr_bits_len 8 bit_vector sc_lv |
| io_axi_slave_write_addr_bits_size 3 bit_vector sc_lv |
| io_axi_slave_write_addr_bits_burst 2 bit_vector sc_lv |
| io_axi_slave_write_addr_bits_lock 1 bit sc_logic |
| io_axi_slave_write_addr_bits_cache 4 bit_vector sc_lv |
| io_axi_slave_write_addr_bits_qos 4 bit_vector sc_lv |
| io_axi_slave_write_addr_bits_region 4 bit_vector sc_lv |
| |
| io_axi_slave_write_data_ready 1 bit sc_logic |
| io_axi_slave_write_data_valid 1 bit sc_logic |
| io_axi_slave_write_data_bits_data 128 bit_vector sc_lv |
| io_axi_slave_write_data_bits_last 1 bit sc_logic |
| io_axi_slave_write_data_bits_strb 16 bit_vector sc_lv |
| |
| io_axi_slave_write_resp_ready 1 bit sc_logic |
| io_axi_slave_write_resp_valid 1 bit sc_logic |
| io_axi_slave_write_resp_bits_id 6 bit_vector sc_lv |
| io_axi_slave_write_resp_bits_resp 2 bit_vector sc_lv |
| |
| io_axi_slave_read_addr_ready 1 bit sc_logic |
| io_axi_slave_read_addr_valid 1 bit sc_logic |
| io_axi_slave_read_addr_bits_addr 32 bit_vector sc_lv |
| io_axi_slave_read_addr_bits_prot 3 bit_vector sc_lv |
| io_axi_slave_read_addr_bits_id 6 bit_vector sc_lv |
| io_axi_slave_read_addr_bits_len 8 bit_vector sc_lv |
| io_axi_slave_read_addr_bits_size 3 bit_vector sc_lv |
| io_axi_slave_read_addr_bits_burst 2 bit_vector sc_lv |
| io_axi_slave_read_addr_bits_lock 1 bit sc_logic |
| io_axi_slave_read_addr_bits_cache 4 bit_vector sc_lv |
| io_axi_slave_read_addr_bits_qos 4 bit_vector sc_lv |
| io_axi_slave_read_addr_bits_region 4 bit_vector sc_lv |
| |
| io_axi_slave_read_data_ready 1 bit sc_logic |
| io_axi_slave_read_data_valid 1 bit sc_logic |
| io_axi_slave_read_data_bits_data 128 bit_vector sc_lv |
| io_axi_slave_read_data_bits_id 6 bit_vector sc_lv |
| io_axi_slave_read_data_bits_resp 2 bit_vector sc_lv |
| io_axi_slave_read_data_bits_last 1 bit sc_logic |
| |
| io_axi_master_write_addr_ready 1 bit sc_logic |
| io_axi_master_write_addr_valid 1 bit sc_logic |
| io_axi_master_write_addr_bits_addr 32 bit_vector sc_lv |
| io_axi_master_write_addr_bits_prot 3 bit_vector sc_lv |
| io_axi_master_write_addr_bits_id 6 bit_vector sc_lv |
| io_axi_master_write_addr_bits_len 8 bit_vector sc_lv |
| io_axi_master_write_addr_bits_size 3 bit_vector sc_lv |
| io_axi_master_write_addr_bits_burst 2 bit_vector sc_lv |
| io_axi_master_write_addr_bits_lock 1 bit sc_logic |
| io_axi_master_write_addr_bits_cache 4 bit_vector sc_lv |
| io_axi_master_write_addr_bits_qos 4 bit_vector sc_lv |
| io_axi_master_write_addr_bits_region 4 bit_vector sc_lv |
| |
| io_axi_master_write_data_ready 1 bit sc_logic |
| io_axi_master_write_data_valid 1 bit sc_logic |
| io_axi_master_write_data_bits_data 128 bit_vector sc_lv |
| io_axi_master_write_data_bits_last 1 bit sc_logic |
| io_axi_master_write_data_bits_strb 16 bit_vector sc_lv |
| |
| io_axi_master_write_resp_ready 1 bit sc_logic |
| io_axi_master_write_resp_valid 1 bit sc_logic |
| io_axi_master_write_resp_bits_id 6 bit_vector sc_lv |
| io_axi_master_write_resp_bits_resp 2 bit_vector sc_lv |
| |
| io_axi_master_read_addr_ready 1 bit sc_logic |
| io_axi_master_read_addr_valid 1 bit sc_logic |
| io_axi_master_read_addr_bits_addr 32 bit_vector sc_lv |
| io_axi_master_read_addr_bits_prot 3 bit_vector sc_lv |
| io_axi_master_read_addr_bits_id 6 bit_vector sc_lv |
| io_axi_master_read_addr_bits_len 8 bit_vector sc_lv |
| io_axi_master_read_addr_bits_size 3 bit_vector sc_lv |
| io_axi_master_read_addr_bits_burst 2 bit_vector sc_lv |
| io_axi_master_read_addr_bits_lock 1 bit sc_logic |
| io_axi_master_read_addr_bits_cache 4 bit_vector sc_lv |
| io_axi_master_read_addr_bits_qos 4 bit_vector sc_lv |
| io_axi_master_read_addr_bits_region 4 bit_vector sc_lv |
| |
| io_axi_master_read_data_ready 1 bit sc_logic |
| io_axi_master_read_data_valid 1 bit sc_logic |
| io_axi_master_read_data_bits_data 128 bit_vector sc_lv |
| io_axi_master_read_data_bits_id 6 bit_vector sc_lv |
| io_axi_master_read_data_bits_resp 2 bit_vector sc_lv |
| io_axi_master_read_data_bits_last 1 bit sc_logic |
