Merge changes Ic8198274,I9ff37f51

* changes:
  Update bazel rule lint
  Add repo preupload config

PREUPLOAD.cfg

diff --git a/PREUPLOAD.cfg b/PREUPLOAD.cfg
new file mode 100644
index 0000000..f88c10e
--- /dev/null
+++ b/PREUPLOAD.cfg
@@ -0,0 +1,17 @@
+# Per-project `repo upload` hook settings.
+# https://android.googlesource.com/platform/tools/repohooks
+
+[Options]
+ignore_merged_commits = true
+
+[Builtin Hooks]
+pylint3 = true
+cpplint = true
+clang_format = true
+
+[Builtin Hooks Options]
+clang_format = --commit ${PREUPLOAD_COMMIT} --style file --extensions c,h,cc,cpp
+
+[Hook Scripts]
+buildifier = ${REPO_ROOT}/scripts/preupload-hooks/run_buildifier.sh ${PREUPLOAD_COMMIT}
+yapf-diff = ${REPO_ROOT}/scripts/preupload-hooks/yapf-diff.sh ${PREUPLOAD_COMMIT}

rules/chisel.bzl

diff --git a/rules/chisel.bzl b/rules/chisel.bzl
index 5ce9315..d097498 100644
--- a/rules/chisel.bzl
+++ b/rules/chisel.bzl
@@ -2,10 +2,11 @@
 load("@rules_hdl//verilog:providers.bzl", "VerilogInfo", "verilog_library")
 load("@kelvin_hw//rules:verilator.bzl", "verilator_cc_library")
 
-def chisel_library(name,
-                   srcs = [],
-                   deps = [],
-                   visibility = None):
+def chisel_library(
+        name,
+        srcs = [],
+        deps = [],
+        visibility = None):
     scala_library(
         name = name,
         srcs = srcs,
@@ -20,11 +21,12 @@
         visibility = visibility,
     )
 
-def chisel_binary(name,
-                  main_class,
-                  srcs = [],
-                  deps = [],
-                  visibility = None):
+def chisel_binary(
+        name,
+        main_class,
+        srcs = [],
+        deps = [],
+        visibility = None):
     scala_binary(
         name = name,
         srcs = srcs,
@@ -40,15 +42,16 @@
         visibility = visibility,
     )
 
-def chisel_cc_library(name,
-                      chisel_lib,
-                      emit_class,
-                      module_name,
-                      verilog_deps=[]):
+def chisel_cc_library(
+        name,
+        chisel_lib,
+        emit_class,
+        module_name,
+        verilog_deps = []):
     gen_binary_name = name + "_emit_verilog_binary"
     chisel_binary(
         name = gen_binary_name,
-        deps = [ chisel_lib ],
+        deps = [chisel_lib],
         main_class = emit_class,
     )
 

rules/verilator.bzl

diff --git a/rules/verilator.bzl b/rules/verilator.bzl
index 834cd68..6f1b72e 100644
--- a/rules/verilator.bzl
+++ b/rules/verilator.bzl
@@ -220,4 +220,4 @@
         "@bazel_tools//tools/cpp:toolchain_type",
     ],
     fragments = ["cpp"],
-)
\ No newline at end of file
+)