Apply inline asm only to vle in indexed load tests When data width is different from index width, lmul is also different. If written in intrinsics, we hit a compiler bug in llvm and gcc that incorrectly combines the vset, causing the vle to see bad lmul. A previous workaround rewrites the tests in inline asm. This new workaround rewrites only the vle part in inline asm, passing the results out as intrinsics-compatible vector data types, allowing the indexed loads to happen in intrinsics. This reduces the number of constraints we need on the asm blocks and reduces the chance of bugs. A bug within indexed load tests' expected output generation is fixed. Change-Id: I7bf1e8a7e9208753e6428a19c178f6f0e40e43e6
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog