)]}'
{
  "commit": "e7c87ff77408722f7581db6d59a1558d218d4a1e",
  "tree": "6963d6dd0538ea661b78759757588fe625762b76",
  "parents": [
    "6e984db30268501ef4a76213e0ec2ab62b8add00"
  ],
  "author": {
    "name": "David Gao",
    "email": "davidgao@google.com",
    "time": "Sun Sep 21 04:26:31 2025 +0000"
  },
  "committer": {
    "name": "David Gao",
    "email": "davidgao@google.com",
    "time": "Sun Sep 21 08:52:37 2025 +0000"
  },
  "message": "Apply inline asm only to vle in indexed load tests\n\nWhen data width is different from index width, lmul is also different.\nIf written in intrinsics, we hit a compiler bug in llvm and gcc that\nincorrectly combines the vset, causing the vle to see bad lmul.\n\nA previous workaround rewrites the tests in inline asm.\n\nThis new workaround rewrites only the vle part in inline asm, passing\nthe results out as intrinsics-compatible vector data types, allowing\nthe indexed loads to happen in intrinsics. This reduces the number of\nconstraints we need on the asm blocks and reduces the chance of\nbugs.\n\nA bug within indexed load tests\u0027 expected output generation is fixed.\n\nChange-Id: I7bf1e8a7e9208753e6428a19c178f6f0e40e43e6\n",
  "tree_diff": [
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