Improve coverage for indexed stores ddtype > idtype. Change-Id: I678b1239826d2b0aa1f0ee0476ed1e825dd0df90
diff --git a/tests/cocotb/BUILD b/tests/cocotb/BUILD index 0888e46..b184773 100644 --- a/tests/cocotb/BUILD +++ b/tests/cocotb/BUILD
@@ -195,7 +195,10 @@ "load8_segment2_stride6_m1", "load16_segment2_stride6_m1", "store8_index8", + "store16_index8", "store16_index16", + "store32_index8", + "store32_index16", "store32_index32", "store8_seg_unit", "store16_seg_unit",
diff --git a/tests/cocotb/rvv/load_store/BUILD b/tests/cocotb/rvv/load_store/BUILD index e220ce9..30014f6 100644 --- a/tests/cocotb/rvv/load_store/BUILD +++ b/tests/cocotb/rvv/load_store/BUILD
@@ -92,9 +92,18 @@ "store8_index8": { "srcs": ["store8_index8.cc"], }, + "store16_index8": { + "srcs": ["store16_index8.cc"], + }, "store16_index16": { "srcs": ["store16_index16.cc"], }, + "store32_index8": { + "srcs": ["store32_index8.cc"], + }, + "store32_index16": { + "srcs": ["store32_index16.cc"], + }, "store32_index32": { "srcs": ["store32_index32.cc"], }, @@ -137,7 +146,10 @@ ":load32_stride8_m1.elf", ":load32_stride8_m1_partial.elf", ":store8_index8.elf", + ":store16_index8.elf", ":store16_index16.elf", + ":store32_index8.elf", + ":store32_index16.elf", ":store32_index32.elf", ":store8_seg_unit", ":store16_seg_unit",
diff --git a/tests/cocotb/rvv/load_store/store16_index8.cc b/tests/cocotb/rvv/load_store/store16_index8.cc new file mode 100644 index 0000000..1a9b19c --- /dev/null +++ b/tests/cocotb/rvv/load_store/store16_index8.cc
@@ -0,0 +1,136 @@ +// Copyright 2025 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include <riscv_vector.h> +#include <stdint.h> + +namespace { +constexpr size_t scatter_count = 64; +constexpr size_t buf_size = 256; +} // namespace + +size_t vl __attribute__((section(".data"))) = 8; +// Indices are always unsigned. +uint8_t index_buf[scatter_count] __attribute__((section(".data"))); +// These instructions don't differentiate signed/unsigned so we only need to +// test one. The types come from intrinsic level. +uint16_t in_buf[scatter_count] __attribute__((section(".data"))); +uint16_t out_buf[buf_size] __attribute__((section(".data"))); + +extern "C" { +// Unordered +__attribute__((used, retain)) void vsuxei8_v_u16mf2() { + auto indices = __riscv_vle8_v_u8mf4(index_buf, vl); + auto data = __riscv_vle16_v_u16mf2(in_buf, vl); + __riscv_vsuxei8_v_u16mf2(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei8_v_u16m1() { + auto indices = __riscv_vle8_v_u8mf2(index_buf, vl); + auto data = __riscv_vle16_v_u16m1(in_buf, vl); + __riscv_vsuxei8_v_u16m1(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei8_v_u16m2() { + vuint8m1_t indices; + asm("vsetvli zero, %[vl], e8, m1, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m1(index_buf, vl); + auto data = __riscv_vle16_v_u16m2(in_buf, vl); + __riscv_vsuxei8_v_u16m2(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei8_v_u16m4() { + vuint8m2_t indices; + asm("vsetvli zero, %[vl], e8, m2, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m2(index_buf, vl); + auto data = __riscv_vle16_v_u16m4(in_buf, vl); + __riscv_vsuxei8_v_u16m4(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei8_v_u16m8() { + vuint8m4_t indices; + asm("vsetvli zero, %[vl], e8, m4, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m4(index_buf, vl); + auto data = __riscv_vle16_v_u16m8(in_buf, vl); + __riscv_vsuxei8_v_u16m8(out_buf, indices, data, vl); +} + +// Ordered +__attribute__((used, retain)) void vsoxei8_v_u16mf2() { + auto indices = __riscv_vle8_v_u8mf4(index_buf, vl); + auto data = __riscv_vle16_v_u16mf2(in_buf, vl); + __riscv_vsoxei8_v_u16mf2(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei8_v_u16m1() { + auto indices = __riscv_vle8_v_u8mf2(index_buf, vl); + auto data = __riscv_vle16_v_u16m1(in_buf, vl); + __riscv_vsoxei8_v_u16m1(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei8_v_u16m2() { + vuint8m1_t indices; + asm("vsetvli zero, %[vl], e8, m1, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m1(index_buf, vl); + auto data = __riscv_vle16_v_u16m2(in_buf, vl); + __riscv_vsoxei8_v_u16m2(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei8_v_u16m4() { + vuint8m2_t indices; + asm("vsetvli zero, %[vl], e8, m2, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m2(index_buf, vl); + auto data = __riscv_vle16_v_u16m4(in_buf, vl); + __riscv_vsoxei8_v_u16m4(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei8_v_u16m8() { + vuint8m4_t indices; + asm("vsetvli zero, %[vl], e8, m4, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m4(index_buf, vl); + auto data = __riscv_vle16_v_u16m8(in_buf, vl); + __riscv_vsoxei8_v_u16m8(out_buf, indices, data, vl); +} +} + +void (*impl)() __attribute__((section(".data"))) = &vsuxei8_v_u16m1; + +int main(int argc, char** argv) { + impl(); + return 0; +}
diff --git a/tests/cocotb/rvv/load_store/store32_index16.cc b/tests/cocotb/rvv/load_store/store32_index16.cc new file mode 100644 index 0000000..65cbc5d --- /dev/null +++ b/tests/cocotb/rvv/load_store/store32_index16.cc
@@ -0,0 +1,136 @@ +// Copyright 2025 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include <riscv_vector.h> +#include <stdint.h> + +namespace { +constexpr size_t scatter_count = 32; +constexpr size_t buf_size = 4000; +} // namespace + +size_t vl __attribute__((section(".data"))) = 4; +// Indices are always unsigned. +uint16_t index_buf[scatter_count] __attribute__((section(".data"))); +// These instructions don't differentiate signed/unsigned so we only need to +// test one. The types come from intrinsic level. +uint32_t in_buf[scatter_count] __attribute__((section(".data"))); +uint32_t out_buf[buf_size] __attribute__((section(".data"))); + +extern "C" { +// Unordered +__attribute__((used, retain)) void vsuxei16_v_u32m1() { + vuint16mf2_t indices; + asm("vsetvli zero, %[vl], e16, mf2, ta, ma;" + "vle16.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle16_v_u16mf2(index_buf, vl); + auto data = __riscv_vle32_v_u32m1(in_buf, vl); + __riscv_vsuxei16_v_u32m1(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei16_v_u32m2() { + vuint16m1_t indices; + asm("vsetvli zero, %[vl], e16, m1, ta, ma;" + "vle16.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle16_v_u16m1(index_buf, vl); + auto data = __riscv_vle32_v_u32m2(in_buf, vl); + __riscv_vsuxei16_v_u32m2(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei16_v_u32m4() { + vuint16m2_t indices; + asm("vsetvli zero, %[vl], e16, m2, ta, ma;" + "vle16.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle16_v_u16m1(index_buf, vl); + auto data = __riscv_vle32_v_u32m4(in_buf, vl); + __riscv_vsuxei16_v_u32m4(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei16_v_u32m8() { + vuint16m4_t indices; + asm("vsetvli zero, %[vl], e16, m4, ta, ma;" + "vle16.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle16_v_u16m2(index_buf, vl); + auto data = __riscv_vle32_v_u32m8(in_buf, vl); + __riscv_vsuxei16_v_u32m8(out_buf, indices, data, vl); +} + +// Ordered +__attribute__((used, retain)) void vsoxei16_v_u32m1() { + vuint16mf2_t indices; + asm("vsetvli zero, %[vl], e16, mf2, ta, ma;" + "vle16.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle16_v_u16mf2(index_buf, vl); + auto data = __riscv_vle32_v_u32m1(in_buf, vl); + __riscv_vsoxei16_v_u32m1(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei16_v_u32m2() { + vuint16m1_t indices; + asm("vsetvli zero, %[vl], e16, m1, ta, ma;" + "vle16.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle16_v_u8mf2(index_buf, vl); + auto data = __riscv_vle32_v_u32m2(in_buf, vl); + __riscv_vsoxei16_v_u32m2(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei16_v_u32m4() { + vuint16m2_t indices; + asm("vsetvli zero, %[vl], e16, m2, ta, ma;" + "vle16.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle16_v_u8m1(index_buf, vl); + auto data = __riscv_vle32_v_u32m4(in_buf, vl); + __riscv_vsoxei16_v_u32m4(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei16_v_u32m8() { + vuint16m4_t indices; + asm("vsetvli zero, %[vl], e16, m4, ta, ma;" + "vle16.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle16_v_u8m2(index_buf, vl); + auto data = __riscv_vle32_v_u32m8(in_buf, vl); + __riscv_vsoxei16_v_u32m8(out_buf, indices, data, vl); +} +} + +void (*impl)() __attribute__((section(".data"))) = &vsuxei16_v_u32m1; + +int main(int argc, char** argv) { + impl(); + return 0; +}
diff --git a/tests/cocotb/rvv/load_store/store32_index8.cc b/tests/cocotb/rvv/load_store/store32_index8.cc new file mode 100644 index 0000000..e79ff9f --- /dev/null +++ b/tests/cocotb/rvv/load_store/store32_index8.cc
@@ -0,0 +1,136 @@ +// Copyright 2025 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include <riscv_vector.h> +#include <stdint.h> + +namespace { +constexpr size_t scatter_count = 32; +constexpr size_t buf_size = 257; +} // namespace + +size_t vl __attribute__((section(".data"))) = 4; +// Indices are always unsigned. +uint8_t index_buf[scatter_count] __attribute__((section(".data"))); +// These instructions don't differentiate signed/unsigned so we only need to +// test one. The types come from intrinsic level. +uint32_t in_buf[scatter_count] __attribute__((section(".data"))); +uint32_t out_buf[buf_size] __attribute__((section(".data"))); + +extern "C" { +// Unordered +__attribute__((used, retain)) void vsuxei8_v_u32m1() { + vuint8mf4_t indices; + asm("vsetvli zero, %[vl], e8, mf4, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8mf4(index_buf, vl); + auto data = __riscv_vle32_v_u32m1(in_buf, vl); + __riscv_vsuxei8_v_u32m1(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei8_v_u32m2() { + vuint8mf2_t indices; + asm("vsetvli zero, %[vl], e8, mf2, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8mf2(index_buf, vl); + auto data = __riscv_vle32_v_u32m2(in_buf, vl); + __riscv_vsuxei8_v_u32m2(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei8_v_u32m4() { + vuint8m1_t indices; + asm("vsetvli zero, %[vl], e8, m1, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m1(index_buf, vl); + auto data = __riscv_vle32_v_u32m4(in_buf, vl); + __riscv_vsuxei8_v_u32m4(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsuxei8_v_u32m8() { + vuint8m2_t indices; + asm("vsetvli zero, %[vl], e8, m2, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m2(index_buf, vl); + auto data = __riscv_vle32_v_u32m8(in_buf, vl); + __riscv_vsuxei8_v_u32m8(out_buf, indices, data, vl); +} + +// Ordered +__attribute__((used, retain)) void vsoxei8_v_u32m1() { + vuint8mf4_t indices; + asm("vsetvli zero, %[vl], e8, mf4, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8mf4(index_buf, vl); + auto data = __riscv_vle32_v_u32m1(in_buf, vl); + __riscv_vsoxei8_v_u32m1(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei8_v_u32m2() { + vuint8mf2_t indices; + asm("vsetvli zero, %[vl], e8, mf2, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8mf2(index_buf, vl); + auto data = __riscv_vle32_v_u32m2(in_buf, vl); + __riscv_vsoxei8_v_u32m2(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei8_v_u32m4() { + vuint8m1_t indices; + asm("vsetvli zero, %[vl], e8, m1, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m1(index_buf, vl); + auto data = __riscv_vle32_v_u32m4(in_buf, vl); + __riscv_vsoxei8_v_u32m4(out_buf, indices, data, vl); +} + +__attribute__((used, retain)) void vsoxei8_v_u32m8() { + vuint8m2_t indices; + asm("vsetvli zero, %[vl], e8, m2, ta, ma;" + "vle8.v %[index], %[index_buf];" + : [index] "=vr"(indices) + : [vl] "r"(vl), [index_buf] "m"(index_buf)); + // TODO: Revert once compiler bug is eliminated + // auto indices = __riscv_vle8_v_u8m2(index_buf, vl); + auto data = __riscv_vle32_v_u32m8(in_buf, vl); + __riscv_vsoxei8_v_u32m8(out_buf, indices, data, vl); +} +} + +void (*impl)() __attribute__((section(".data"))) = &vsuxei8_v_u32m1; + +int main(int argc, char** argv) { + impl(); + return 0; +}
diff --git a/tests/cocotb/rvv_load_store_test.py b/tests/cocotb/rvv_load_store_test.py index 1e0d7e6..dcfdb5a 100644 --- a/tests/cocotb/rvv_load_store_test.py +++ b/tests/cocotb/rvv_load_store_test.py
@@ -909,6 +909,48 @@ @cocotb.test() +async def store16_index8(dut): + """Test vs*xei8_v_u16 usage accessible from intrinsics.""" + def make_test_case(impl: str, vl: int): + return { + 'impl': impl, + 'vl': vl, + 'out_size': 256, + } + + await vector_store_indexed( + dut = dut, + elf_name = 'store16_index8.elf', + cases = [ + # Unordered + make_test_case('vsuxei8_v_u16mf2', vl = 4), + make_test_case('vsuxei8_v_u16mf2', vl = 3), + make_test_case('vsuxei8_v_u16m1', vl = 8), + make_test_case('vsuxei8_v_u16m1', vl = 7), + make_test_case('vsuxei8_v_u16m2', vl = 16), + make_test_case('vsuxei8_v_u16m2', vl = 15), + make_test_case('vsuxei8_v_u16m4', vl = 32), + make_test_case('vsuxei8_v_u16m4', vl = 31), + make_test_case('vsuxei8_v_u16m8', vl = 64), + make_test_case('vsuxei8_v_u16m8', vl = 63), + # Ordered + make_test_case('vsoxei8_v_u16mf2', vl = 4), + make_test_case('vsoxei8_v_u16mf2', vl = 3), + make_test_case('vsoxei8_v_u16m1', vl = 8), + make_test_case('vsoxei8_v_u16m1', vl = 7), + make_test_case('vsoxei8_v_u16m2', vl = 16), + make_test_case('vsoxei8_v_u16m2', vl = 15), + make_test_case('vsoxei8_v_u16m4', vl = 32), + make_test_case('vsoxei8_v_u16m4', vl = 31), + make_test_case('vsoxei8_v_u16m8', vl = 64), + make_test_case('vsoxei8_v_u16m8', vl = 63), + ], + data_dtype = np.uint16, + index_dtype = np.uint8, + ) + + +@cocotb.test() async def store16_index16(dut): """Test vs*xei16_v_u16 usage accessible from intrinsics.""" def make_test_case(impl: str, vl: int): @@ -951,6 +993,82 @@ @cocotb.test() +async def store32_index8(dut): + """Test vs*xei8_v_u32 usage accessible from intrinsics.""" + def make_test_case(impl: str, vl: int): + return { + 'impl': impl, + 'vl': vl, + 'out_size': 257, + } + + await vector_store_indexed( + dut = dut, + elf_name = 'store32_index8.elf', + cases = [ + # Unordered + make_test_case('vsuxei8_v_u32m1', vl = 4), + make_test_case('vsuxei8_v_u32m1', vl = 3), + make_test_case('vsuxei8_v_u32m2', vl = 8), + make_test_case('vsuxei8_v_u32m2', vl = 7), + make_test_case('vsuxei8_v_u32m4', vl = 16), + make_test_case('vsuxei8_v_u32m4', vl = 15), + make_test_case('vsuxei8_v_u32m8', vl = 32), + make_test_case('vsuxei8_v_u32m8', vl = 31), + # Ordered + make_test_case('vsoxei8_v_u32m1', vl = 4), + make_test_case('vsoxei8_v_u32m1', vl = 3), + make_test_case('vsoxei8_v_u32m2', vl = 8), + make_test_case('vsoxei8_v_u32m2', vl = 7), + make_test_case('vsoxei8_v_u32m4', vl = 16), + make_test_case('vsoxei8_v_u32m4', vl = 15), + make_test_case('vsoxei8_v_u32m8', vl = 32), + make_test_case('vsoxei8_v_u32m8', vl = 31), + ], + data_dtype = np.uint32, + index_dtype = np.uint8, + ) + + +@cocotb.test() +async def store32_index16(dut): + """Test vs*xei16_v_u32 usage accessible from intrinsics.""" + def make_test_case(impl: str, vl: int): + return { + 'impl': impl, + 'vl': vl, + 'out_size': 4000, + } + + await vector_store_indexed( + dut = dut, + elf_name = 'store32_index16.elf', + cases = [ + # Unordered + make_test_case('vsuxei16_v_u32m1', vl = 4), + make_test_case('vsuxei16_v_u32m1', vl = 3), + make_test_case('vsuxei16_v_u32m2', vl = 8), + make_test_case('vsuxei16_v_u32m2', vl = 7), + make_test_case('vsuxei16_v_u32m4', vl = 16), + make_test_case('vsuxei16_v_u32m4', vl = 15), + make_test_case('vsuxei16_v_u32m8', vl = 32), + make_test_case('vsuxei16_v_u32m8', vl = 31), + # Ordered + make_test_case('vsoxei16_v_u32m1', vl = 4), + make_test_case('vsoxei16_v_u32m1', vl = 3), + make_test_case('vsoxei16_v_u32m2', vl = 8), + make_test_case('vsoxei16_v_u32m2', vl = 7), + make_test_case('vsoxei16_v_u32m4', vl = 16), + make_test_case('vsoxei16_v_u32m4', vl = 15), + make_test_case('vsoxei16_v_u32m8', vl = 32), + make_test_case('vsoxei16_v_u32m8', vl = 31), + ], + data_dtype = np.uint32, + index_dtype = np.uint16, + ) + + +@cocotb.test() async def store32_index32(dut): """Test vs*xei32_v_u32 usage accessible from intrinsics.""" def make_test_case(impl: str, vl: int):