| commit | d884f10a8bcbb16721b8368afef83fa79760538f | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Mar 05 13:15:26 2024 -0800 |
| committer | Alex Van Damme <atv@google.com> | Tue Mar 05 22:53:38 2024 +0000 |
| tree | 868da606e4a499f6fb4aa74a3a91c487166e20df | |
| parent | 54f4343593b76b78de676f18b7790874d83a3029 [diff] |
Fixes in fetch for non-4 instructionLanes - These fixups allow the kelvin_sw_test suite to pass on 1, 2, and 4 instructionLanes. Change-Id: I6e7efe36d9f562765ce4a6617fa377e6f87cb7cf
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog