| commit | d28bde072267460cc8680bb736b8e625d87eeb7e | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Sep 09 10:15:17 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Tue Sep 16 17:52:23 2025 -0700 |
| tree | a04dde39f4715a2b29da4761b65a46f9c9adb1b1 | |
| parent | 707495c9dda43cebc685606ea32c95eb99503b67 [diff] |
feat(spi2tlul): Implement efficient bulk data transfers Implements a high-throughput bulk data transfer mechanism for the Spi2TLUL bridge. The previous implementation relied on single-byte read/write operations to the data buffer port, which was inefficient for large data transfers due to the overhead of sending an address for every byte. This change introduces dedicated bulk read and write ports. A single SPI command can now initiate a transfer of up to 256 bytes, significantly improving data throughput for tasks like loading programs or model weights. Key changes include: - A new command-decoding FSM in the Spi2TLUL Chisel module to distinguish between single-register access and bulk transfers. - A robust, double-buffered MISO path to prevent data loss during back-to-back SPI transactions. - New `new_bulk_write` and `new_bulk_read` methods in the Python `SPIMaster` test utility. - Enumerations for SPI register addresses and commands in the Python test utilities for improved readability and maintainability. - Comprehensive cocotb tests verifying the new bulk transfer modes, including a stress test for transfers up to 64KB. Change-Id: I72c614fadb5620c86a4150bedffef14857f47217
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog