)]}'
{
  "commit": "d28bde072267460cc8680bb736b8e625d87eeb7e",
  "tree": "a04dde39f4715a2b29da4761b65a46f9c9adb1b1",
  "parents": [
    "707495c9dda43cebc685606ea32c95eb99503b67"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Tue Sep 09 10:15:17 2025 -0700"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Tue Sep 16 17:52:23 2025 -0700"
  },
  "message": "feat(spi2tlul): Implement efficient bulk data transfers\n\nImplements a high-throughput bulk data transfer mechanism for the\nSpi2TLUL bridge. The previous implementation relied on single-byte\nread/write operations to the data buffer port, which was inefficient\nfor large data transfers due to the overhead of sending an address\nfor every byte.\n\nThis change introduces dedicated bulk read and write ports. A single\nSPI command can now initiate a transfer of up to 256 bytes,\nsignificantly improving data throughput for tasks like loading programs\nor model weights.\n\nKey changes include:\n- A new command-decoding FSM in the Spi2TLUL Chisel module to\n  distinguish between single-register access and bulk transfers.\n- A robust, double-buffered MISO path to prevent data loss during\n  back-to-back SPI transactions.\n- New `new_bulk_write` and `new_bulk_read` methods in the Python\n  `SPIMaster` test utility.\n- Enumerations for SPI register addresses and commands in the Python\n  test utilities for improved readability and maintainability.\n- Comprehensive cocotb tests verifying the new bulk transfer modes,\n  including a stress test for transfers up to 64KB.\n\nChange-Id: I72c614fadb5620c86a4150bedffef14857f47217\n",
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