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opensecura / hw / kelvin / 59bb2dda94bb558c3636f6e2a5a4e88af2403554
commit59bb2dda94bb558c3636f6e2a5a4e88af2403554[log] [tgz]
authorAlex Van Damme <atv@google.com>Mon Aug 04 13:44:14 2025 -0700
committerAlex Van Damme <atv@google.com>Wed Aug 06 16:55:45 2025 -0700
tree21fde34535faf7490b7192fe042226c97a8a1e92
parenta9d0294073a83fec97fae4992cd231c1cdde6dd8 [diff]
feat(fpga): Add supporting IPs for Kelvin SoC

Change-Id: I127d67f8c0e87d13972c7b804ba8db8dc4ffc202
19 files changed
tree: 21fde34535faf7490b7192fe042226c97a8a1e92
  1. doc/
  2. examples/
  3. external/
  4. fpga/
  5. hdl/
  6. hw_sim/
  7. kelvin_test_utils/
  8. lib/
  9. platforms/
  10. rules/
  11. tests/
  12. third_party/
  13. toolchain/
  14. utils/
  15. .bazelrc
  16. .bazelversion
  17. .gitignore
  18. CONTRIBUTING.md
  19. LICENSE
  20. PREUPLOAD.cfg
  21. README.md
  22. WORKSPACE
README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Getting Started

  • If you are hardware engineer looking to integrate Kelvin into your design, check out our integration guide.
  • If you are a software engineer looking to write code for Kelvin, start with this tutorial.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog