| commit | a9d0294073a83fec97fae4992cd231c1cdde6dd8 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Mon Aug 04 13:44:06 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Wed Aug 06 16:55:44 2025 -0700 |
| tree | bfbf71d49e5245a950910a98f959241e9af4b98a | |
| parent | 502e0d9a666f48d9eab7fe8e67a727e2d4fbe165 [diff] |
feat(fpga): Add Ibex core IP and generation docs Change-Id: Ia89d87940b11e60e17c74669a36fc5cbe7694cb2
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog