| commit | 734ed668ddf52c1fd26ee8e2f5c14422f429663a | [log] [tgz] |
|---|---|---|
| author | pu.wang <pu.wang@verisilicon.com> | Tue Jan 21 18:36:38 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Mar 06 14:56:41 2025 -0800 |
| tree | 1994e162a51a7f950d35cb4b133241dd73df5af8 | |
| parent | b39fc1cb60ff31fae34017c76ed9e9857d98ed4a [diff] |
Update tb: 1. fix xrf retire condition in monitor 2. Fix vcpop/vfirst logic 3. Fix tail elements behavior of mask producing instructions. Now it will writeback calculation result for tail element. Change-Id: I9629e3b80b92935b90368a179e432dd7c44e2393
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog