| commit | b39fc1cb60ff31fae34017c76ed9e9857d98ed4a | [log] [tgz] |
|---|---|---|
| author | pu.wang <pu.wang@verisilicon.com> | Mon Jan 20 21:59:19 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Mar 06 14:56:41 2025 -0800 |
| tree | 2de06130080b99da90b5490bdb2a6eb2b83532c0 | |
| parent | bfb3f0c72d7dc982018cbcf0ad81353707a76573 [diff] |
Update tb: 1. Fix vstart constraint: vl <=vlmax_max-1 2. Use byte_strobe for vrf retire check. Change-Id: I382da8ccdc5daa5866fb84d997dc4e216f9be179
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog