commit bcfbc2b3765e9848d268ab270f19a67237410b49
author Tianyu Li <Tianyu.Li@verisilicon.com> Tue Nov 19 14:34:30 2024 +0800
committer Derek Chow <derekjchow@google.com> Wed Nov 20 21:41:31 2024 +0000
tree 4855ac8e6d6a8d20f824fd73d0c16db9a26a8a94
parent 7e8caeaf604d973596e8dcf7227d303a6a9ab397

change its module name.

Change-Id: I646f6d6ac1d678c49548da596858456c3f9ecabb

hdl/verilog/common/dff.sv

diff --git a/hdl/verilog/common/dff.sv b/hdl/verilog/common/dff.sv
index 8045e46..1cc7aca 100644
--- a/hdl/verilog/common/dff.sv
+++ b/hdl/verilog/common/dff.sv
@@ -2,7 +2,7 @@
 //   Order of ports is:  q, clk, [rst_n], [e], d
 //   E.g.  DFF #(4) qsig (qsig, clk, rst_n, dsig);
 
-module dffr ( q, clk, rst_n, d ) ; // FF with async rst_n;  
+module dff ( q, clk, rst_n, d ) ; // FF with async rst_n;  
   parameter WIDTH = 1 ;
   input 	clk ;
   input 	rst_n ;