Reuse VRegfile interface types in VAluInt.
Change-Id: Idac5db35534832fe69cb38afc34e238aae7a9fed
diff --git a/hdl/chisel/src/kelvin/vector/VAlu.scala b/hdl/chisel/src/kelvin/vector/VAlu.scala
index 03f6f36..34aa41d 100644
--- a/hdl/chisel/src/kelvin/vector/VAlu.scala
+++ b/hdl/chisel/src/kelvin/vector/VAlu.scala
@@ -62,17 +62,6 @@
io.read(i).tag := 0.U
}
- for (i <- 0 until io.write.length) {
- io.write(i).valid := false.B
- io.write(i).addr := 0.U
- io.write(i).data := 0.U
- }
-
- for (i <- 0 until io.whint.length) {
- io.whint(i).valid := false.B
- io.whint(i).addr := 0.U
- }
-
// ---------------------------------------------------------------------------
// Opcode checks.
for (i <- 0 until io.in.bits.length) {
@@ -352,19 +341,11 @@
alu0.io.read(5).data := io.read(5).data
alu0.io.read(6).data := io.read(6).data
- io.write(0).valid := alu0.io.write(0).valid
- io.write(0).addr := alu0.io.write(0).addr
- io.write(0).data := alu0.io.write(0).data
+ io.write(0) := alu0.io.write(0)
+ io.write(1) := alu0.io.write(1)
- io.write(1).valid := alu0.io.write(1).valid
- io.write(1).addr := alu0.io.write(1).addr
- io.write(1).data := alu0.io.write(1).data
-
- io.whint(0).valid := alu0.io.whint(0).valid
- io.whint(0).addr := alu0.io.whint(0).addr
-
- io.whint(1).valid := alu0.io.whint(1).valid
- io.whint(1).addr := alu0.io.whint(1).addr
+ io.whint(0) := alu0.io.whint(0)
+ io.whint(1) := alu0.io.whint(1)
// ---------------------------------------------------------------------------
// Alu1.
@@ -386,19 +367,11 @@
alu1.io.read(5).data := io.read(2).data
alu1.io.read(6).data := io.read(6).data
- io.write(2).valid := alu1.io.write(0).valid
- io.write(2).addr := alu1.io.write(0).addr
- io.write(2).data := alu1.io.write(0).data
+ io.write(2) := alu1.io.write(0)
+ io.write(3) := alu1.io.write(1)
- io.write(3).valid := alu1.io.write(1).valid
- io.write(3).addr := alu1.io.write(1).addr
- io.write(3).data := alu1.io.write(1).data
-
- io.whint(2).valid := alu1.io.whint(0).valid
- io.whint(2).addr := alu1.io.whint(0).addr
-
- io.whint(3).valid := alu1.io.whint(1).valid
- io.whint(3).addr := alu1.io.whint(1).addr
+ io.whint(2) := alu1.io.whint(0)
+ io.whint(3) := alu1.io.whint(1)
// ---------------------------------------------------------------------------
// Active.
diff --git a/hdl/chisel/src/kelvin/vector/VAluInt.scala b/hdl/chisel/src/kelvin/vector/VAluInt.scala
index b919d5d..64ec7a9 100644
--- a/hdl/chisel/src/kelvin/vector/VAluInt.scala
+++ b/hdl/chisel/src/kelvin/vector/VAluInt.scala
@@ -43,15 +43,8 @@
val read = Vec(7, Input(new Bundle {
val data = UInt(p.vectorBits.W)
}))
- val write = Vec(2, Output(new Bundle {
- val valid = Bool()
- val addr = UInt(6.W)
- val data = UInt(p.vectorBits.W)
- }))
- val whint = Vec(2, Output(new Bundle {
- val valid = Bool()
- val addr = UInt(6.W)
- }))
+ val write = Vec(2, new VRegfileWriteIO(p))
+ val whint = Vec(2, new VRegfileWhintIO(p))
})
class AluAddr extends Bundle {
