Add GF22 Compiled Memories to Design Add GF22 compiled memories. Make Sram .v files more generic to accomodate different technologies. Change-Id: Ibf994fc361247494d62e88f0c331fb13e69f846e
diff --git a/hdl/chisel/src/kelvin/BUILD b/hdl/chisel/src/kelvin/BUILD index 6fe855e..88fa0b3 100644 --- a/hdl/chisel/src/kelvin/BUILD +++ b/hdl/chisel/src/kelvin/BUILD
@@ -338,13 +338,13 @@ srcs = [ "SramNx128.scala", "Sram_12ffcp_128x128.scala", - "Sram_12ffcp_2048x128.scala", - "Sram_12ffcp_512x128.scala", + "Sram_2048x128.scala", + "Sram_512x128.scala", ], resources = [ "//hdl/verilog:Sram_12ffcp_128x128.v", - "//hdl/verilog:Sram_12ffcp_2048x128.v", - "//hdl/verilog:Sram_12ffcp_512x128.v", + "//hdl/verilog:Sram_2048x128.v", + "//hdl/verilog:Sram_512x128.v", ], deps = [ ":kelvin_base", @@ -521,6 +521,8 @@ "CKLNQD10BWP6T20P96CPDLVT", "TS1N12FFCLLMBLVTD2048X128M4SWBSHO", "TS1N12FFCLLSBLVTD512X128M4SWBSHO", + "sasdulssd8LOW1p512x128m4b1w0c0p0d0l0rm3sdrw01", + "sasdulssd8LOW1p2048x128m4b2w0c0p0d0l0rm3sdrw01", ] CORE_MINI_AXI_LINT_TAGS = [
diff --git a/hdl/chisel/src/kelvin/SramNx128.scala b/hdl/chisel/src/kelvin/SramNx128.scala index f8434d4..979a213 100644 --- a/hdl/chisel/src/kelvin/SramNx128.scala +++ b/hdl/chisel/src/kelvin/SramNx128.scala
@@ -51,8 +51,8 @@ val sramModules = (0 until nSramModules).map(x => (mod2048, mod512) match { - case (true, _) => Module(new Sram_12ffcp_2048x128) - case (_, true) => Module(new Sram_12ffcp_512x128) + case (true, _) => Module(new Sram_2048x128) + case (_, true) => Module(new Sram_512x128) case (false, false) => Module(new Sram_12ffcp_128x128) } )
diff --git a/hdl/chisel/src/kelvin/Sram_12ffcp_512x128.scala b/hdl/chisel/src/kelvin/Sram_12ffcp_512x128.scala deleted file mode 100644 index 8f24386..0000000 --- a/hdl/chisel/src/kelvin/Sram_12ffcp_512x128.scala +++ /dev/null
@@ -1,21 +0,0 @@ -// Copyright 2024 Google LLC -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -package kelvin - -import chisel3.util.HasBlackBoxResource - -class Sram_12ffcp_512x128 extends SRAM128(9) with HasBlackBoxResource { - addResource("hdl/verilog/Sram_12ffcp_512x128.v") -}
diff --git a/hdl/chisel/src/kelvin/Sram_12ffcp_2048x128.scala b/hdl/chisel/src/kelvin/Sram_2048x128.scala similarity index 83% copy from hdl/chisel/src/kelvin/Sram_12ffcp_2048x128.scala copy to hdl/chisel/src/kelvin/Sram_2048x128.scala index bdf1623..c1601cc 100644 --- a/hdl/chisel/src/kelvin/Sram_12ffcp_2048x128.scala +++ b/hdl/chisel/src/kelvin/Sram_2048x128.scala
@@ -16,6 +16,6 @@ import chisel3.util.HasBlackBoxResource -class Sram_12ffcp_2048x128 extends SRAM128(11) with HasBlackBoxResource { - addResource("hdl/verilog/Sram_12ffcp_2048x128.v") +class Sram_2048x128 extends SRAM128(11) with HasBlackBoxResource { + addResource("hdl/verilog/Sram_2048x128.v") }
diff --git a/hdl/chisel/src/kelvin/Sram_12ffcp_2048x128.scala b/hdl/chisel/src/kelvin/Sram_512x128.scala similarity index 83% rename from hdl/chisel/src/kelvin/Sram_12ffcp_2048x128.scala rename to hdl/chisel/src/kelvin/Sram_512x128.scala index bdf1623..5c56c6e 100644 --- a/hdl/chisel/src/kelvin/Sram_12ffcp_2048x128.scala +++ b/hdl/chisel/src/kelvin/Sram_512x128.scala
@@ -16,6 +16,6 @@ import chisel3.util.HasBlackBoxResource -class Sram_12ffcp_2048x128 extends SRAM128(11) with HasBlackBoxResource { - addResource("hdl/verilog/Sram_12ffcp_2048x128.v") +class Sram_512x128 extends SRAM128(9) with HasBlackBoxResource { + addResource("hdl/verilog/Sram_512x128.v") }
diff --git a/hdl/verilog/BUILD b/hdl/verilog/BUILD index 7df6c6a..270aac5 100644 --- a/hdl/verilog/BUILD +++ b/hdl/verilog/BUILD
@@ -18,8 +18,8 @@ srcs = [ "ClockGate.sv", "Sram_12ffcp_128x128.v", - "Sram_12ffcp_512x128.v", - "Sram_12ffcp_2048x128.v", + "Sram_512x128.v", + "Sram_2048x128.v", "Sram_1rw_256x256.v", "Sram_1rwm_256x288.v", "RstSync.sv",
diff --git a/hdl/verilog/Sram_12ffcp_2048x128.v b/hdl/verilog/Sram_2048x128.v similarity index 71% rename from hdl/verilog/Sram_12ffcp_2048x128.v rename to hdl/verilog/Sram_2048x128.v index feecf89..4fb84e1 100644 --- a/hdl/verilog/Sram_12ffcp_2048x128.v +++ b/hdl/verilog/Sram_2048x128.v
@@ -12,7 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -module Sram_12ffcp_2048x128( +module Sram_2048x128( input clock, input enable, input write, @@ -22,7 +22,13 @@ output [127:0] rdata ); -`ifndef USE_GENERIC +/////////////////////////// +///// SRAM Selection ////// +/////////////////////////// +`ifdef USE_TSMC12FFC +/////////////////////////// +///// TSMC12FFC SRAM ////// +/////////////////////////// wire [127:0] nwmask; genvar i; generate @@ -66,8 +72,44 @@ .WTSEL(2'b1) // Write Test Select (input [1:0]) `endif ); +`elsif USE_GF22 +/////////////////////////// +//////// GF22 SRAM //////// +/////////////////////////// + wire [127:0] nwmask; + genvar i; + generate + for (i = 0; i < 16; i++) begin + assign nwmask[8*i +: 8] = {8{wmask[i]}}; + end + endgenerate + sasdulssd8LOW1p2048x128m4b2w0c0p0d0l0rm3sdrw01 u_gf22_sram ( + // Data Output + .Q(rdata), // Data Output [127:0] + // Data Input + .ADR(addr), // Address [10:0] + .D(wdata), // Data Input [127:0] + .WEM(nwmask), // Write Enable Mask [127:0] (active high) + .WE(write), // Write Enable (active high) + .ME(enable), // Memory Enable (active high) + .CLK(clock), // Clock + // Test and Power-saving pins - tied off + .TEST1(1'b0), + .TEST_RNM(1'b0), + .RME(1'b0), + .RM(4'b0), + .WA(2'b0), + .WPULSE(3'b0), + .LS(1'b0), + .BC0(1'b0), + .BC1(1'b0), + .BC2(1'b0) + ); `else +/////////////////////////// +////// Generic SRAM /////// +/////////////////////////// reg [127:0] mem [0:2047]; reg [10:0] raddr;
diff --git a/hdl/verilog/Sram_12ffcp_512x128.v b/hdl/verilog/Sram_512x128.v similarity index 76% rename from hdl/verilog/Sram_12ffcp_512x128.v rename to hdl/verilog/Sram_512x128.v index 4b849ff..63033b0 100644 --- a/hdl/verilog/Sram_12ffcp_512x128.v +++ b/hdl/verilog/Sram_512x128.v
@@ -12,7 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -module Sram_12ffcp_512x128( +module Sram_512x128( input clock, input enable, input write, @@ -22,7 +22,13 @@ output [127:0] rdata ); -`ifndef USE_GENERIC +/////////////////////////// +///// SRAM Selection ////// +/////////////////////////// +`ifdef USE_TSMC12FFC +/////////////////////////// +///// TSMC12FFC SRAM ////// +/////////////////////////// wire [127:0] nwmask; genvar i; generate @@ -66,8 +72,41 @@ .WTSEL(2'b0) // Write Test Select (input [1:0]) `endif ); +`elsif USE_GF22 +/////////////////////////// +//////// GF22 SRAM //////// +/////////////////////////// + wire [127:0] nwmask; + genvar i; + generate + for (i = 0; i < 16; i++) begin + assign nwmask[8*i +: 8] = {8{wmask[i]}}; + end + endgenerate + sasdulssd8LOW1p512x128m4b1w0c0p0d0l0rm3sdrw01 u_gf22_sram ( + .Q(rdata), + .ADR(addr), + .D(wdata), + .WEM(nwmask), + .WE(write), + .ME(enable), + .CLK(clock), + .TEST1(1'b0), + .TEST_RNM(1'b0), + .RME(1'b0), + .RM(4'b0), + .WA(2'b0), + .WPULSE(3'b0), + .LS(1'b0), + .BC0(1'b0), + .BC1(1'b0), + .BC2(1'b0) + ); `else +/////////////////////////// +////// Generic SRAM /////// +/////////////////////////// reg [127:0] mem [0:511]; reg [8:0] raddr; @@ -98,6 +137,6 @@ raddr <= addr; end end -`endif // FFCP12_SRAM +`endif endmodule