| commit | e42e486fd83e7bd275e1397d26a8b7bea04e529c | [log] [tgz] |
|---|---|---|
| author | Derek Chow <derekjchow@google.com> | Sun Jul 13 01:05:22 2025 +0000 |
| committer | Derek Chow <derekjchow@google.com> | Mon Jul 14 10:35:07 2025 -0700 |
| tree | 6ab417b7c6b05dd14ce189c79d29f015f2734f3d | |
| parent | b8e7e6d1b7648ebd5f1a16bcdfd0c73c6b51d091 [diff] |
Add queue to AXI master output write. Change-Id: Iaf8d9ddaa19c7239f9d330710e834d54a7b4ebd3
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog