| commit | b8e7e6d1b7648ebd5f1a16bcdfd0c73c6b51d091 | [log] [tgz] |
|---|---|---|
| author | Derek Chow <derekjchow@google.com> | Fri Jul 11 13:13:05 2025 -0700 |
| committer | Derek Chow <derekjchow@google.com> | Fri Jul 11 17:21:29 2025 -0700 |
| tree | 87ec2527be97e2bd0bc4cf286ea91efcb2432c18 | |
| parent | 546429bc19e7f968368e1e713140f7022e2f0118 [diff] |
Support for segmented loads. Change-Id: Iabe9a16f4a44e5c3815a1af994d3c6a66cb1a0cd
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog