commit a2c167c175cdb50dc76ef656d586b50ea2ddda0f
author Yenkai Wang <ykwang@google.com> Fri Aug 18 19:30:53 2023 +0000
committer Gerrit Code Review <noreply-gerritcodereview@google.com> Fri Aug 18 19:30:53 2023 +0000
tree 8b99a41f0780afddf2c0151a6bd8e2fa4ef3bb85
parent 003c90afcf30c17cfcbfa35041ecced1d6347067
parent 8f160789dbb6ca327fcb1c636d37167c5e6cfb26

Merge "[HW][Kelvin][Sram_1rwm_256x288.v] move FPGA defined macro"

hdl/verilog/Sram_1rwm_256x288.v

diff --git a/hdl/verilog/Sram_1rwm_256x288.v b/hdl/verilog/Sram_1rwm_256x288.v
index 011c7cc..425b662 100644
--- a/hdl/verilog/Sram_1rwm_256x288.v
+++ b/hdl/verilog/Sram_1rwm_256x288.v
@@ -11,13 +11,12 @@
   input          volt_sel
 );
 
+`ifdef FPGA
 reg [287:0] mem [0:255];
 reg [7:0] raddr;
 
 assign rdata = mem[raddr];
 
-`ifdef FPGA
-
 always @(posedge clock) begin
   for (int i = 0; i < 32; i++) begin
     if (valid & write & wmask[i]) begin