Remove extra vd from RvvCompressedInstruction

- We don't need this extra field, simply extract the low bits from
  `bits` when needed.

Change-Id: I5f19f3588a52f0616425cd6ed0b9e7eb9fb10b14

hdl/chisel/src/kelvin/rvv/RvvCore.scala

diff --git a/hdl/chisel/src/kelvin/rvv/RvvCore.scala b/hdl/chisel/src/kelvin/rvv/RvvCore.scala
index f9529df..75ae92a 100644
--- a/hdl/chisel/src/kelvin/rvv/RvvCore.scala
+++ b/hdl/chisel/src/kelvin/rvv/RvvCore.scala
@@ -40,7 +40,6 @@
             |    input [31:0] inst_GENI_bits_pc,
             |    input [1:0] inst_GENI_bits_opcode,
             |    input [24:0] inst_GENI_bits_bits,
-            |    input [31:0] inst_GENI_bits_vd,
             |""".stripMargin.replaceAll("GENI", i.toString)
     }
 

hdl/chisel/src/kelvin/rvv/RvvDecode.scala

diff --git a/hdl/chisel/src/kelvin/rvv/RvvDecode.scala b/hdl/chisel/src/kelvin/rvv/RvvDecode.scala
index 092cb1a..03f1b7d 100644
--- a/hdl/chisel/src/kelvin/rvv/RvvDecode.scala
+++ b/hdl/chisel/src/kelvin/rvv/RvvDecode.scala
@@ -36,7 +36,6 @@
   val pc = UInt(32.W)
   val opcode = RvvCompressedOpcode()
   val bits = UInt(25.W)
-  val vd = UInt(5.W)
 
   def funct6(): UInt = {
     bits(24, 19)
@@ -118,7 +117,6 @@
       _.bits.opcode -> new_opcode.bits,
       _.bits.pc -> pc,
       _.bits.bits -> bits,
-      _.bits.vd -> bits(4, 0),
     )
   }
 }

hdl/chisel/src/kelvin/scalar/Decode.scala

diff --git a/hdl/chisel/src/kelvin/scalar/Decode.scala b/hdl/chisel/src/kelvin/scalar/Decode.scala
index c2f1435..b808286 100644
--- a/hdl/chisel/src/kelvin/scalar/Decode.scala
+++ b/hdl/chisel/src/kelvin/scalar/Decode.scala
@@ -758,7 +758,7 @@
     if (p.enableRvv) {
       val rvvRdMark_valid = io.rvv.get(i).fire && d.rvv.get.bits.writesVectorRegister()
       io.rvvRdMark.get(i).valid := rvvRdMark_valid
-      io.rvvRdMark.get(i).addr := d.rvv.get.bits.vd
+      io.rvvRdMark.get(i).addr := d.rvv.get.bits.bits(4,0) // vd
     }
 
     // Register file bus address port.