Make core_sim simulation trace and cycle configurable
To run core_sim with cycles and trace specified
```
core_sim --trace --cycles 50000 <bin path>
```
Change-Id: I8eb7b5aad4d16179bee7ddd31b899a86dfa021f0
diff --git a/rules/repos.bzl b/rules/repos.bzl
index ebcf1b7..e22179c 100644
--- a/rules/repos.bzl
+++ b/rules/repos.bzl
@@ -44,3 +44,10 @@
strip_prefix = "rules_foreign_cc-0.9.0",
url = "https://github.com/bazelbuild/rules_foreign_cc/archive/refs/tags/0.9.0.tar.gz",
)
+
+ http_archive(
+ name = "com_google_absl",
+ sha256 = "3ea49a7d97421b88a8c48a0de16c16048e17725c7ec0f1d3ea2683a2a75adc21",
+ strip_prefix = "abseil-cpp-20230125.0",
+ urls = ["https://github.com/abseil/abseil-cpp/archive/refs/tags/20230125.0.tar.gz"],
+ )
diff --git a/tests/verilator_sim/BUILD b/tests/verilator_sim/BUILD
index d549d23..a974e32 100644
--- a/tests/verilator_sim/BUILD
+++ b/tests/verilator_sim/BUILD
@@ -35,6 +35,9 @@
":kelvin_if",
":sim_libs",
"//hdl/chisel:core_cc_library",
+ "@com_google_absl//absl/flags:flag",
+ "@com_google_absl//absl/flags:parse",
+ "@com_google_absl//absl/flags:usage",
],
)
@@ -114,7 +117,7 @@
cc_test(
name = "valuint_tb",
- size="large",
+ size = "large",
srcs = [
"kelvin/valuint_tb.cc",
],
diff --git a/tests/verilator_sim/kelvin/core_tb.cc b/tests/verilator_sim/kelvin/core_tb.cc
index c449816..f23c1f7 100644
--- a/tests/verilator_sim/kelvin/core_tb.cc
+++ b/tests/verilator_sim/kelvin/core_tb.cc
@@ -1,13 +1,16 @@
// Copyright 2023 Google LLC
-#include "tests/verilator_sim/sysc_tb.h"
-
-#include "VCore.h"
-
+#include "VCore.h" // Generated
+#include "absl/flags/flag.h"
+#include "absl/flags/parse.h"
+#include "absl/flags/usage.h"
#include "tests/verilator_sim/kelvin/core_if.h"
#include "tests/verilator_sim/kelvin/debug_if.h"
#include "tests/verilator_sim/kelvin/kelvin_cfg.h"
+#include "tests/verilator_sim/sysc_tb.h"
+ABSL_FLAG(int, cycles, 100000000, "Simulation cycles");
+ABSL_FLAG(bool, trace, false, "Dump VCD trace");
struct Core_tb : Sysc_tb {
sc_in<bool> io_halted;
@@ -21,9 +24,10 @@
}
};
-static void Core_run(const char* name, const char* bin, const bool trace) {
+static void Core_run(const char* name, const char* bin, const int cycles,
+ const bool trace) {
VCore core(name);
- Core_tb tb("Core_tb", 100000000, /* random= */ false);
+ Core_tb tb("Core_tb", cycles, /* random= */ false);
Core_if mif("Core_if", bin);
Debug_if dbg("Debug_if", &mif);
@@ -209,7 +213,9 @@
dbg.io_slog_addr(io_slog_addr);
dbg.io_slog_data(io_slog_data);
-#define BINDAXI(a) core.a(a); mif.a(a)
+#define BINDAXI(a) \
+ core.a(a); \
+ mif.a(a)
BINDAXI(io_axi0_write_addr_ready);
BINDAXI(io_axi0_write_addr_valid);
BINDAXI(io_axi0_write_addr_bits_addr);
@@ -261,12 +267,17 @@
}
int sc_main(int argc, char *argv[]) {
- if (argc <= 1) {
- printf("Expected binary file argument\n");
- return -1;
+ absl::SetProgramUsageMessage("Kelvin SystemC simulation tool");
+ auto out_args = absl::ParseCommandLine(argc, argv);
+ argc = out_args.size();
+ argv = &out_args[0];
+ if (argc != 2) {
+ fprintf(stderr, "Need one binary input file\n");
+ return 1;
}
-
const char* path = argv[1];
- Core_run(Sysc_tb::get_name(argv[0]), path, false);
+
+ Core_run(Sysc_tb::get_name(argv[0]), path, absl::GetFlag(FLAGS_cycles),
+ absl::GetFlag(FLAGS_trace));
return 0;
}
diff --git a/tests/verilator_sim/sysc_tb.h b/tests/verilator_sim/sysc_tb.h
index b097a7d..6caca7f 100644
--- a/tests/verilator_sim/sysc_tb.h
+++ b/tests/verilator_sim/sysc_tb.h
@@ -16,7 +16,7 @@
using sc_dt::sc_bv;
-const char *vcd_path_ = "/tmp/kelvin/vcd";
+const char *vcd_path_ = "/tmp";
#define BIND(a, b) a.b(b)
#define BIND2(a, b, c) \
