| commit | 9e2fc99ed7e6cd4400b2c8f134245a811bc94f22 | [log] [tgz] |
|---|---|---|
| author | Cindy Liu <hcindyl@google.com> | Sun Aug 27 18:34:29 2023 -0700 |
| committer | Cindy Liu <hcindyl@google.com> | Mon Aug 28 14:26:52 2023 -0700 |
| tree | a21e82e8dd8aead271d500d7af63789bdff1f823 | |
| parent | 57ed25d42794ceff2f4c517cb099126c2fa579a6 [diff] |
Make core_sim simulation trace and cycle configurable To run core_sim with cycles and trace specified ``` core_sim --trace --cycles 50000 <bin path> ``` Change-Id: I8eb7b5aad4d16179bee7ddd31b899a86dfa021f0
Kelvin is a RISC-V32IM core with a custom instruction set.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog