Make core_sim simulation trace and cycle configurable

To run core_sim with cycles and trace specified

core_sim --trace --cycles 50000 <bin path>

Change-Id: I8eb7b5aad4d16179bee7ddd31b899a86dfa021f0
4 files changed
tree: a21e82e8dd8aead271d500d7af63789bdff1f823
  1. external/
  2. hdl/
  3. lib/
  4. rules/
  5. tests/
  6. utils/
  7. .bazelrc
  8. .gitignore
  9. PREUPLOAD.cfg


Kelvin is a RISC-V32IM core with a custom instruction set.


Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog