Add RVV to tracing - Plumb the output from rvvCore's writeback into the RetirementBuffer. - If rvv is enabled, RetirementBuffer is expanded to handle the full VLEN. - Pass along the vector data to rvviTrace, as well. Change-Id: I418a9963e336ef9b916fc268371cc8339d0a88a8

tree: b99f0fa44cd92bb8bbbefec85ce2e7463114401c

README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Getting Started

If you are hardware engineer looking to integrate Kelvin into your design, check out our integration guide.
If you are a software engineer looking to write code for Kelvin, start with this tutorial.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog