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opensecura / hw / kelvin / 98e88c479e8f4f73e4b7e4a41e30b4b7f50c15ff
commit98e88c479e8f4f73e4b7e4a41e30b4b7f50c15ff[log] [tgz]
authorAlex Van Damme <atv@google.com>Tue Jul 08 15:26:34 2025 -0700
committerAlex Van Damme <atv@google.com>Tue Aug 12 15:41:37 2025 -0700
treeb99f0fa44cd92bb8bbbefec85ce2e7463114401c
parent1aee13e8cb90d42e777e5588af4a51c0d58cf1b9 [diff]
Add RVV to tracing

- Plumb the output from rvvCore's writeback into the RetirementBuffer.
- If rvv is enabled, RetirementBuffer is expanded to handle the full
  VLEN.
- Pass along the vector data to rvviTrace, as well.

Change-Id: I418a9963e336ef9b916fc268371cc8339d0a88a8
15 files changed
tree: b99f0fa44cd92bb8bbbefec85ce2e7463114401c
  1. doc/
  2. examples/
  3. external/
  4. fpga/
  5. hdl/
  6. hw_sim/
  7. kelvin_test_utils/
  8. lib/
  9. platforms/
  10. rules/
  11. tests/
  12. third_party/
  13. toolchain/
  14. utils/
  15. .bazelrc
  16. .bazelversion
  17. .gitignore
  18. CONTRIBUTING.md
  19. LICENSE
  20. PREUPLOAD.cfg
  21. README.md
  22. WORKSPACE
README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Getting Started

  • If you are hardware engineer looking to integrate Kelvin into your design, check out our integration guide.
  • If you are a software engineer looking to write code for Kelvin, start with this tutorial.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog