| commit | 1aee13e8cb90d42e777e5588af4a51c0d58cf1b9 | [log] [tgz] |
|---|---|---|
| author | Lun Dong <lundong@google.com> | Thu Aug 07 21:51:07 2025 +0000 |
| committer | Lun Dong <lundong@google.com> | Tue Aug 12 15:09:13 2025 -0700 |
| tree | 10e24b00746e302c785b928f91cf41258dc708ee | |
| parent | 814bc6c3ec9f287309db9571510f6dc02ab19b1d [diff] |
Add support for RVV for kelvin simulator Also some minor clean-ups. Change-Id: I091bd299ac49a2d19ecab0c1b7ee0b6435a5d264
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog