commit 8f160789dbb6ca327fcb1c636d37167c5e6cfb26
author Yenkai Wang <ykwang@google.com> Thu Aug 17 14:10:55 2023 -0600
committer Yenkai Wang <ykwang@google.com> Thu Aug 17 14:10:58 2023 -0600
tree 56fbb735a728926d27acac923cc3e4c623cbbae0
parent 27ba5bdbc5cfd039232181307aacbc8327a61322

[HW][Kelvin][Sram_1rwm_256x288.v] move FPGA defined macro

1. Move 2 registers defintion and assign statement inside "ifdef FPGA" branch.
2. It will fix the both VCS and ASIC synthesis reported lint errors.

Change-Id: I4f3005810e89e25c11b9f3ddcd2bddf556a81486

hdl/verilog/Sram_1rwm_256x288.v

diff --git a/hdl/verilog/Sram_1rwm_256x288.v b/hdl/verilog/Sram_1rwm_256x288.v
index 011c7cc..425b662 100644
--- a/hdl/verilog/Sram_1rwm_256x288.v
+++ b/hdl/verilog/Sram_1rwm_256x288.v
@@ -11,13 +11,12 @@
   input          volt_sel
 );
 
+`ifdef FPGA
 reg [287:0] mem [0:255];
 reg [7:0] raddr;
 
 assign rdata = mem[raddr];
 
-`ifdef FPGA
-
 always @(posedge clock) begin
   for (int i = 0; i < 32; i++) begin
     if (valid & write & wmask[i]) begin