diff --git a/hdl/verilog/Sram_1rwm_256x288.v b/hdl/verilog/Sram_1rwm_256x288.v
index 011c7cc..425b662 100644
--- a/hdl/verilog/Sram_1rwm_256x288.v
+++ b/hdl/verilog/Sram_1rwm_256x288.v
@@ -11,13 +11,12 @@
   input          volt_sel
 );
 
+`ifdef FPGA
 reg [287:0] mem [0:255];
 reg [7:0] raddr;
 
 assign rdata = mem[raddr];
 
-`ifdef FPGA
-
 always @(posedge clock) begin
   for (int i = 0; i < 32; i++) begin
     if (valid & write & wmask[i]) begin