| commit | 8f160789dbb6ca327fcb1c636d37167c5e6cfb26 | [log] [tgz] |
|---|---|---|
| author | Yenkai Wang <ykwang@google.com> | Thu Aug 17 14:10:55 2023 -0600 |
| committer | Yenkai Wang <ykwang@google.com> | Thu Aug 17 14:10:58 2023 -0600 |
| tree | 56fbb735a728926d27acac923cc3e4c623cbbae0 | |
| parent | 27ba5bdbc5cfd039232181307aacbc8327a61322 [diff] |
[HW][Kelvin][Sram_1rwm_256x288.v] move FPGA defined macro 1. Move 2 registers defintion and assign statement inside "ifdef FPGA" branch. 2. It will fix the both VCS and ASIC synthesis reported lint errors. Change-Id: I4f3005810e89e25c11b9f3ddcd2bddf556a81486
Kelvin is a RISC-V32IM core with a custom instruction set.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel build //hdl/chisel:kelvin_cc_library_emit_verilog