)]}'
{
  "commit": "8f160789dbb6ca327fcb1c636d37167c5e6cfb26",
  "tree": "56fbb735a728926d27acac923cc3e4c623cbbae0",
  "parents": [
    "27ba5bdbc5cfd039232181307aacbc8327a61322"
  ],
  "author": {
    "name": "Yenkai Wang",
    "email": "ykwang@google.com",
    "time": "Thu Aug 17 14:10:55 2023 -0600"
  },
  "committer": {
    "name": "Yenkai Wang",
    "email": "ykwang@google.com",
    "time": "Thu Aug 17 14:10:58 2023 -0600"
  },
  "message": "[HW][Kelvin][Sram_1rwm_256x288.v] move FPGA defined macro\n\n1. Move 2 registers defintion and assign statement inside \"ifdef FPGA\" branch.\n2. It will fix the both VCS and ASIC synthesis reported lint errors.\n\nChange-Id: I4f3005810e89e25c11b9f3ddcd2bddf556a81486\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "011c7cc7c605323bb328555d3a6c82287f3bcfb2",
      "old_mode": 33188,
      "old_path": "hdl/verilog/Sram_1rwm_256x288.v",
      "new_id": "425b6623533fcf8a624b35adfb4e18823e3403f3",
      "new_mode": 33188,
      "new_path": "hdl/verilog/Sram_1rwm_256x288.v"
    }
  ]
}