commit | 8ed7b045ef01ae8da0b95ff6d2e0e7c40aea1230 | [log] [tgz] |
---|---|---|
author | Michael Hoang <hoangm@google.com> | Mon Aug 21 21:47:34 2023 +0000 |
committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | Mon Aug 21 21:47:34 2023 +0000 |
tree | 774f88a3197b478db8e7c87aab268ab73af95fd3 | |
parent | f1f7ea210ef41063e597f1f07f8fa8e4747e1b15 [diff] | |
parent | 1c0aaf037960c3f13dbe19fe428126f6dea58c3a [diff] |
Merge changes from topics "kelvin-vsubsu", "kelvin_reg_0" * changes: Initialize several registers to 0 Fix vsubs.u
Kelvin is a RISC-V32IM core with a custom instruction set.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog