| commit | 8da8e6b6283807cb94ac1957ebdf1ac328f8a512 | [log] [tgz] |
|---|---|---|
| author | Pu Wang <pu.wang@verisilicon.com> | Mon Jan 13 13:48:38 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Tue Jan 21 13:33:29 2025 -0800 |
| tree | 2e62afceec1367457e3599e61e3d2aeecdf490dc | |
| parent | e7f7d59c03bc2d9c8be9842013604dd35b982bea [diff] |
update support signals which only used in tb Change-Id: I9cc56fbb800b9ae41fc363f99133633ecc39a6d5
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog