| commit | e7f7d59c03bc2d9c8be9842013604dd35b982bea | [log] [tgz] |
|---|---|---|
| author | Tianyu Li <Tianyu.Li@verisilicon.com> | Mon Jan 13 10:55:00 2025 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Tue Jan 21 13:33:29 2025 -0800 |
| tree | a578f35ce9f70f0b5cdccbe9aab983965b094dbb | |
| parent | 213d4d8c1f436d3805e37f4ab9b37dd979dd0daa [diff] |
Fix the problem of read ports of VRF assignment. Change-Id: I8dd157939ec9482d3cf8dfc831a1fcb2f77afc05
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog