commit | 8477fa8bef38dff634146c1d33ab4a036ef1003a | [log] [tgz] |
---|---|---|
author | Derek Chow <derekjchow@google.com> | Tue Apr 02 14:00:04 2024 -0700 |
committer | Derek Chow <derekjchow@google.com> | Tue Apr 02 14:00:04 2024 -0700 |
tree | 50e904dbbf95dfba84db9d2c1d991e33171b5618 | |
parent | bfeb649ed2dad4994e3d30bcdb9aaab69afee699 [diff] |
Disable assert in FifoX. ivalid can be set without iactive. Change-Id: I386f09a12a3015e4257ab31e16419c1ea15a1ad1
diff --git a/hdl/chisel/src/common/FifoX.scala b/hdl/chisel/src/common/FifoX.scala index ee3f041..7e6a925 100644 --- a/hdl/chisel/src/common/FifoX.scala +++ b/hdl/chisel/src/common/FifoX.scala
@@ -131,7 +131,6 @@ when (mcount > 0.U) { mslice.io.in.bits := mem(outpos) } .elsewhen (ivalid) { - assert(PopCount(iactive) >= 1.U) when (iactive =/= 0.U) { val idx = PriorityEncoder(iactive) mslice.io.in.bits := io.in.bits(idx).bits