commit | 7f34b1728279dec1d6f6159a1314557edaefc5e2 | [log] [tgz] |
---|---|---|
author | Tianyu <Tianyu@verisilicon.com> | Mon Jul 14 17:11:31 2025 +0800 |
committer | Derek Chow <derekjchow@google.com> | Tue Aug 05 10:49:53 2025 -0700 |
tree | fdfde50ecf5e154a22f0a8c8395f1c163e2e0e0a | |
parent | c0600ce66c09cd536a49d88eb3cb1aaf788dcbc8 [diff] |
update waiver file for decoder Change-Id: I625b7318d7f758186eb50aca4c5d99b395bba7c0
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog