Update bazel rule lint
Change-Id: Ic8198274a3692ddb71fd2f655ad7ec1ccc7bcfa5
diff --git a/rules/chisel.bzl b/rules/chisel.bzl
index 5ce9315..d097498 100644
--- a/rules/chisel.bzl
+++ b/rules/chisel.bzl
@@ -2,10 +2,11 @@
load("@rules_hdl//verilog:providers.bzl", "VerilogInfo", "verilog_library")
load("@kelvin_hw//rules:verilator.bzl", "verilator_cc_library")
-def chisel_library(name,
- srcs = [],
- deps = [],
- visibility = None):
+def chisel_library(
+ name,
+ srcs = [],
+ deps = [],
+ visibility = None):
scala_library(
name = name,
srcs = srcs,
@@ -20,11 +21,12 @@
visibility = visibility,
)
-def chisel_binary(name,
- main_class,
- srcs = [],
- deps = [],
- visibility = None):
+def chisel_binary(
+ name,
+ main_class,
+ srcs = [],
+ deps = [],
+ visibility = None):
scala_binary(
name = name,
srcs = srcs,
@@ -40,15 +42,16 @@
visibility = visibility,
)
-def chisel_cc_library(name,
- chisel_lib,
- emit_class,
- module_name,
- verilog_deps=[]):
+def chisel_cc_library(
+ name,
+ chisel_lib,
+ emit_class,
+ module_name,
+ verilog_deps = []):
gen_binary_name = name + "_emit_verilog_binary"
chisel_binary(
name = gen_binary_name,
- deps = [ chisel_lib ],
+ deps = [chisel_lib],
main_class = emit_class,
)
diff --git a/rules/verilator.bzl b/rules/verilator.bzl
index 834cd68..6f1b72e 100644
--- a/rules/verilator.bzl
+++ b/rules/verilator.bzl
@@ -220,4 +220,4 @@
"@bazel_tools//tools/cpp:toolchain_type",
],
fragments = ["cpp"],
-)
\ No newline at end of file
+)