blob: 1d2dfff370826d9229b5bdb6d5454343d9bff4ce [file] [log] [blame]
From 8ed6f3b89518638da3d9e1e51c96bd50785cd41c Mon Sep 17 00:00:00 2001
From: Alex Van Damme <atv@google.com>
Date: Mon, 16 Sep 2024 17:03:33 -0700
Subject: [PATCH 3/3] Invert AXI reset polarity
Change-Id: I7f63d4d52806345e0396165767187d9aa93c6339
---
.../VerilatorIntegrationLibrary/src/buses/axi-slave.cpp | 4 ++--
.../VerilatorIntegrationLibrary/src/buses/axi.cpp | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi-slave.cpp b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi-slave.cpp
index 2a3678ba..0155c5cd 100644
--- a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi-slave.cpp
+++ b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi-slave.cpp
@@ -214,10 +214,10 @@ void AxiSlave::writeHandler()
void AxiSlave::reset()
{
- *aresetn = 1;
- tick(true);
*aresetn = 0;
tick(true);
+ *aresetn = 1;
+ tick(true);
}
// You can't read/write using slave bus
diff --git a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp
index c4e15dd3..ddc47cfa 100644
--- a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp
+++ b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp
@@ -117,8 +117,8 @@ uint64_t Axi::read(int width, uint64_t addr)
void Axi::reset()
{
- *aresetn = 1;
- tick(true);
*aresetn = 0;
tick(true);
+ *aresetn = 1;
+ tick(true);
}
--
2.46.0.662.g92d0881bb0-goog