Connect xsat to CSR.

Change-Id: Ic87075412de4b8645aee82bb58d4d0ab2841f566

hdl/chisel/src/kelvin/rvv/RvvCore.scala

diff --git a/hdl/chisel/src/kelvin/rvv/RvvCore.scala b/hdl/chisel/src/kelvin/rvv/RvvCore.scala
index f039c91..24ded3a 100644
--- a/hdl/chisel/src/kelvin/rvv/RvvCore.scala
+++ b/hdl/chisel/src/kelvin/rvv/RvvCore.scala
@@ -100,6 +100,7 @@
     moduleInterface += """    output vcsr_valid,
         |    output [VSTART_LEN:0] vcsr_vstart,
         |    output [1:0] vcsr_xrm,
+        |    output vcsr_vxsat,
         |    input vcsr_ready,
         |""".stripMargin.replaceAll("VSTART_LEN", (log2Ceil(vlen) - 1).toString)
 
@@ -215,6 +216,7 @@
     coreInstantiation += """  RVVConfigState vector_csr;
         |  assign vcsr_vstart = vector_csr.vstart;
         |  assign vcsr_xrm = vector_csr.xrm;
+        |  assign vcsr_vxsat = vector_csr.xsat;
         |""".stripMargin
     // RVV Config State temp output
     coreInstantiation += """  RVVConfigState config_state;
@@ -308,6 +310,7 @@
     val vcsr_valid = Output(Bool())
     val vcsr_vstart = Output(UInt(7.W))
     val vcsr_xrm = Output(UInt(2.W))
+    val vcsr_vxsat = Output(Bool())
     val vcsr_ready = Input(Bool())
 
     // TODO(derekjchow): Parameterize
@@ -394,6 +397,7 @@
 
   val vstart = RegInit(0.U(log2Ceil(p.rvvVlen).W))
   val vxrm = RegInit(0.U(2.W))
+  val vxsat = RegInit(false.B)
 
   val rstn = (!reset.asBool).asAsyncReset
   val rvvCoreWrapper = Module(new RvvCoreWrapper(p))
@@ -405,10 +409,11 @@
   rvvCoreWrapper.io.async_rd <> io.async_rd
 
   rvvCoreWrapper.io.vstart := Mux(
-      io.csr.csr_vstart.valid, io.csr.csr_vstart.bits, vstart)
+      io.csr.vstart_write.valid, io.csr.vstart_write.bits, vstart)
   rvvCoreWrapper.io.vxrm := Mux(
-      io.csr.csr_vxrm.valid, io.csr.csr_vxrm.bits, vxrm)
-  rvvCoreWrapper.io.vxsat := 0.U
+      io.csr.vxrm_write.valid, io.csr.vxrm_write.bits, vxrm)
+  rvvCoreWrapper.io.vxsat := Mux(
+      io.csr.vxsat_write.valid, io.csr.vxsat_write.bits, vxsat)
   rvvCoreWrapper.io.vcsr_ready := true.B
 
   io.rvv2lsu <> rvvCoreWrapper.io.rvv2lsu
@@ -427,17 +432,24 @@
 
   val vstart_wdata = MuxCase(vstart, Seq(
       rvvCoreWrapper.io.vcsr_valid -> rvvCoreWrapper.io.vcsr_vstart,
-      io.csr.csr_vstart.valid -> io.csr.csr_vstart.bits,
+      io.csr.vstart_write.valid -> io.csr.vstart_write.bits,
   ))
   vstart := vstart_wdata
 
   val vxrm_wdata = MuxCase(vxrm, Seq(
       rvvCoreWrapper.io.vcsr_valid -> rvvCoreWrapper.io.vcsr_xrm,
-      io.csr.csr_vxrm.valid -> io.csr.csr_vxrm.bits,
+      io.csr.vxrm_write.valid -> io.csr.vxrm_write.bits,
   ))
   vxrm := vxrm_wdata
 
+  val vxsat_wdata = MuxCase(vxsat, Seq(
+      rvvCoreWrapper.io.vcsr_valid -> rvvCoreWrapper.io.vcsr_vxsat,
+      io.csr.vxsat_write.valid -> io.csr.vxsat_write.bits,
+  ))
+  vxsat := vxsat_wdata
+
   io.csr.vstart := vstart
   io.csr.vxrm := vxrm
+  io.csr.vxsat := vxsat
 }
 

hdl/chisel/src/kelvin/rvv/RvvInterface.scala

diff --git a/hdl/chisel/src/kelvin/rvv/RvvInterface.scala b/hdl/chisel/src/kelvin/rvv/RvvInterface.scala
index babad57..1f6e8e5 100644
--- a/hdl/chisel/src/kelvin/rvv/RvvInterface.scala
+++ b/hdl/chisel/src/kelvin/rvv/RvvInterface.scala
@@ -74,6 +74,8 @@
 class RvvCsrIO(p: Parameters) extends Bundle {
   val vstart = Output(UInt(log2Ceil(p.rvvVlen).W))
   val vxrm = Output(UInt(2.W))
-  val csr_vstart = Input(Valid(UInt(log2Ceil(p.rvvVlen).W)))
-  val csr_vxrm = Input(Valid(UInt(2.W)))
+  val vxsat = Output(Bool())
+  val vstart_write = Input(Valid(UInt(log2Ceil(p.rvvVlen).W)))
+  val vxrm_write = Input(Valid(UInt(2.W)))
+  val vxsat_write = Input(Valid(Bool()))
 }
\ No newline at end of file

hdl/chisel/src/kelvin/scalar/Csr.scala

diff --git a/hdl/chisel/src/kelvin/scalar/Csr.scala b/hdl/chisel/src/kelvin/scalar/Csr.scala
index 2b92bfd..80a4f26 100644
--- a/hdl/chisel/src/kelvin/scalar/Csr.scala
+++ b/hdl/chisel/src/kelvin/scalar/Csr.scala
@@ -22,9 +22,11 @@
   // To Csr from RvvCore
   val vstart = Input(UInt(log2Ceil(p.rvvVlen).W))
   val vxrm = Input(UInt(2.W))
+  val vxsat = Input(Bool())
   // From Csr to RvvCore
   val vstart_write = Output(Valid(UInt(log2Ceil(p.rvvVlen).W)))
   val vxrm_write = Output(Valid(UInt(2.W)))
+  val vxsat_write = Output(Valid(Bool()))
 }
 
 object Csr {
@@ -38,7 +40,8 @@
   val FRM       = Value(0x002.U(12.W))
   val FCSR      = Value(0x003.U(12.W))
   val VSTART    = Value(0x008.U(12.W))
-  val VXRM      = Value(0x009.U(12.W))
+  val VXSAT     = Value(0x009.U(12.W))
+  val VXRM      = Value(0x00A.U(12.W))
   val MSTATUS   = Value(0x300.U(12.W))
   val MISA      = Value(0x301.U(12.W))
   val MIE       = Value(0x304.U(12.W))
@@ -297,6 +300,7 @@
   val fcsrEn      = csr_address === CsrAddress.FCSR
   val vstartEn    = Option.when(p.enableRvv) { csr_address === CsrAddress.VSTART }
   val vxrmEn      = Option.when(p.enableRvv) { csr_address === CsrAddress.VXRM }
+  val vxsatEn     = Option.when(p.enableRvv) { csr_address === CsrAddress.VXSAT }
   val mstatusEn   = csr_address === CsrAddress.MSTATUS
   val misaEn      = csr_address === CsrAddress.MISA
   val mieEn       = csr_address === CsrAddress.MIE
@@ -406,6 +410,7 @@
         Seq(
           vstartEn.get -> io.rvv.get.vstart,
           vxrmEn.get   -> io.rvv.get.vxrm,
+          vxsatEn.get  -> io.rvv.get.vxsat,
           vlenbEn.get -> 16.U(32.W),  // Vector length in Bytes
         )
       }.getOrElse(Seq())
@@ -465,6 +470,8 @@
     io.rvv.get.vstart_write.bits  := wdata(log2Ceil(p.rvvVlen)-1, 0)
     io.rvv.get.vxrm_write.valid   := req.valid && vxrmEn.get
     io.rvv.get.vxrm_write.bits    := wdata(1,0)
+    io.rvv.get.vxsat_write.valid  := req.valid && vxsatEn.get
+    io.rvv.get.vxsat_write.bits   := wdata(0)
   }
 
   // mcycle implementation

hdl/chisel/src/kelvin/scalar/SCore.scala

diff --git a/hdl/chisel/src/kelvin/scalar/SCore.scala b/hdl/chisel/src/kelvin/scalar/SCore.scala
index 68bfdd3..7a46f36 100644
--- a/hdl/chisel/src/kelvin/scalar/SCore.scala
+++ b/hdl/chisel/src/kelvin/scalar/SCore.scala
@@ -428,10 +428,12 @@
     // Register inputs
     io.rvvcore.get.rs := regfile.io.readData
 
-    io.rvvcore.get.csr.csr_vstart <> csr.io.rvv.get.vstart_write
-    io.rvvcore.get.csr.csr_vxrm <> csr.io.rvv.get.vxrm_write
+    io.rvvcore.get.csr.vstart_write <> csr.io.rvv.get.vstart_write
+    io.rvvcore.get.csr.vxrm_write <> csr.io.rvv.get.vxrm_write
+    io.rvvcore.get.csr.vxsat_write <> csr.io.rvv.get.vxsat_write
     csr.io.rvv.get.vstart := io.rvvcore.get.csr.vstart
     csr.io.rvv.get.vxrm := io.rvvcore.get.csr.vxrm
+    csr.io.rvv.get.vxsat := io.rvvcore.get.csr.vxsat
   }
 
   // ---------------------------------------------------------------------------

hdl/verilog/rvv/design/RvvFrontEnd.sv

diff --git a/hdl/verilog/rvv/design/RvvFrontEnd.sv b/hdl/verilog/rvv/design/RvvFrontEnd.sv
index 428b252..d69c93c 100644
--- a/hdl/verilog/rvv/design/RvvFrontEnd.sv
+++ b/hdl/verilog/rvv/design/RvvFrontEnd.sv
@@ -126,7 +126,7 @@
     inst_config_state[0] = config_state_q;
     inst_config_state[0].vstart = vstart_i;
     inst_config_state[0].xrm = RVVXRM'(vxrm_i);
-    //inst_config_state[0].xsat = vxsat_i;
+    inst_config_state[0].xsat = vxsat_i;
     for (int i = 0; i < N; i++) begin
       inst_config_state[i+1] = inst_config_state[i];
       is_setvl[i] = 0;

hdl/verilog/rvv/inc/rvv_backend.svh

diff --git a/hdl/verilog/rvv/inc/rvv_backend.svh b/hdl/verilog/rvv/inc/rvv_backend.svh
index 671b33b..170478b 100755
--- a/hdl/verilog/rvv/inc/rvv_backend.svh
+++ b/hdl/verilog/rvv/inc/rvv_backend.svh
@@ -46,7 +46,7 @@
   logic [`VTYPE_VMA_WIDTH-1:0]  ma;        // 0:inactive element undisturbed, 1:inactive element agnostic
   logic [`VTYPE_VTA_WIDTH-1:0]  ta;        // 0:tail undisturbed, 1:tail agnostic
   RVVXRM                        xrm;       
-  //logic [`VCSR_VXSAT_WIDTH-1:0] xsat;   // rvv dont need this bit, but output this to rvs            
+  logic [`VCSR_VXSAT_WIDTH-1:0] xsat;   // rvv dont need this bit, but output this to rvs
   RVVSEW                        sew;
   RVVLMUL                       lmul;
 } RVVConfigState;