blob: a0ba2752d6010ad111bb7adc14b0185d1c6c7b82 [file] [log] [blame]
From 0f690bbffd3d69a1e0d729e5969bec0a6650aa3e Mon Sep 17 00:00:00 2001
From: Alex Van Damme <atv@google.com>
Date: Thu, 12 Sep 2024 10:12:36 -0700
Subject: [PATCH 1/2] Tweaks to AXI
Change-Id: I8e04eb66f7efa6ac4efe7e475f5cc31769308f17
---
.../hdl/modules/axi/renode_axi_if.sv | 2 +-
.../VerilatorIntegrationLibrary/src/buses/axi.cpp | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/hdl/modules/axi/renode_axi_if.sv b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/hdl/modules/axi/renode_axi_if.sv
index 9b4d0318..3ccc5f64 100644
--- a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/hdl/modules/axi/renode_axi_if.sv
+++ b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/hdl/modules/axi/renode_axi_if.sv
@@ -7,7 +7,7 @@
interface renode_axi_if #(
int unsigned AddressWidth = 32,
- int unsigned DataWidth = 32,
+ int unsigned DataWidth = 128,
int unsigned TransactionIdWidth = 8
) (
input logic aclk
diff --git a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp
index 4df493fb..c4e15dd3 100644
--- a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp
+++ b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp
@@ -9,7 +9,7 @@
BaseAxi::BaseAxi(uint32_t dataWidth, uint32_t addrWidth)
{
- if(dataWidth != 32)
+ if(dataWidth > 128)
throw "Unsupported AXI data width";
this->dataWidth = dataWidth;
@@ -92,7 +92,7 @@ uint64_t Axi::read(int width, uint64_t addr)
*arvalid = 1;
*arlen = 0; // TODO: Variable read length
- *arsize = 2; // TODO: Variable read width
+ *arsize = std::log2(width);
*arburst = static_cast<uint8_t>(AxiBurstType::INCR);
*araddr = addr;
--
2.46.0.662.g92d0881bb0-goog